UNIT – IV

INPUT-OUTPUT ORGANIZATION

Peripheral devices
 In addition to the processor and a set of memory modules, the third key element of a
computer system is a set of input-output subsystem referred to as I/O, provides an efficient
mode of communication between the central system and the outside environment.
 Programs and data must be entered into computer memory for processing and results
obtained from computations must be recorded or displayed for the user.
 Devices that are under the direct control of the computer are said to be connected online.
These devices are designed to read information into or out of the memory unit upon
command from CPU.
 Input or output devices attached to the computer are also called peripherals.
 Among the most common peripherals are keyboards, display units, and printers.
 Perhaps those provide auxiliary storage for the systems are magnetic disks and tapes.
 Peripherals are electromechanical and electromagnetic devices of some complexity.
 We can broadly classify peripheral devices into three categories:
 Human Readable: Communicating with the computer users, e.g. video display
terminal, printers etc.
 Machine Readable: Communicating with equipments, e.g. magnetic disk, magnetic
tape, sensor, actuators used in robotics etc.
 Communication: Communicating with remote devices means exchanging data with
that, e.g. modem, NIC (network interface Card) etc.

Fig: Block diagram of Peripheral device

 Control signals determine the function that the device will perform such as send data to I/O
module, accept data from I/O module.
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 Status signals indicate the state of the device i.e. device is ready or not.
 Data bits are actual data transformation.
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Computer Organization and Architecture By S RAMESH Asst. Professor

  Control logic associated with the device controls the device's operation in response to
direction from the I/O module.
 The transducer converts data from electrical to other forms of energy during output and
from other forms to electrical during input.
 Buffer is associated with the transducer to temporarily hold data being transferred
between the I/O module and external devices i.e. peripheral environment.

Input Device
 Keyboard
 Optical input devices
 Card Reader
 Paper Tape Reader
 Optical Character Recognition (OCR)
 Optical Bar code reader (OBR)
 Digitizer
 Optical Mark Reader
 Magnetic Input Devices
 Magnetic Stripe Reader
 Magnetic Ink Character Recognition (MICR)
 Screen Input Devices
 Touch Screen
 Light Pen
 Mouse
 Analog Input Devices

Output Device
 Card Puncher, Paper Tape Puncher
 Monitor (CRT, LCD, LED)
 Printer (Impact, Ink Jet, Laser, Dot Matrix)
 Plotter
 Analog
 Voice

I/O MODULES
 I/O modules interface to the system bus or central switch (CPU and Memory), interfaces
and controls to one or more peripheral devices.
 I/O operations are accomplished through a wide assortment of external devices that
provide a means of exchanging data between external environment and computer by a link
to an I/O module.
 The link is used to exchange control status and data between I/O module and the external
devices.
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 Fig: Model of I/O module
 Peripherals are not directly connected to the system bus instead an I/O module is used
which contains logic for performing a communication between the peripherals and the
system bus.
 The reasons due to which peripherals do not directly connected to the system bus are:
 There are a wide variety of peripherals with various methods of operation. It would
be impractical to incorporate the necessary logic within the processor to control a
range of devices.
 The data transfer rate of peripherals is often much slower than that of the memory
or processor. Thus, it is impractical to use high speed system bus to communicate
directly with a peripheral and vice versa.
 Peripherals often use different data format and word length than the computer to
which they are connected.
 Thus an I/O module is required which performs two major functions.
 Interface to the processor and memory via the system bus
 Interface to one or more peripherals by tailored data links

I/O Module Functions

The I/O module is a special hardware component interface between the CPU and peripherals to
supervise and synchronize all I/O transformation.

The detailed functions of I/O modules are;

Control & Timing:
 I/O module includes control and timing to coordinate the flow of traffic between internal
resources and external devices.
 The control of the transfer of data from external devices to processor consists following
steps:
 The processor interrogates the I/O module to check status of the attached device.
 The I/O module returns the device status.
 If the device is operational and ready to transmit, the processor requests the
transfer of data by means of a command to I/O module.
 The I/O module obtains the unit of data from the external device.
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 The data are transferred from the I/O module to the processor.
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Computer Organization and Architecture By S RAMESH Asst. Professor

Processor Communication:
 I/O module communicates with the processor which involves:
 Command decoding: I/O module accepts commands from the processor.
 Data: Data are exchanged between the processor and I/O module over the bus.
 Status reporting: Peripherals are too slow and it is important to know the status of
I/O module.
 Address recognition: I/O module must recognize one unique address for each
peripheral it controls.

Device Communication:
It involves commands, status information and data.

Data Buffering:
 I/O module must be able to operate at both device and memory speeds.
 If the I/O device operates at a rate higher than the memory access rate, then the I/O module
performs data buffering.
 If I/O devices rate slower than memory, it buffers data so as not to tie up the memory in
slower transfer operation.

Error Detection:
 I/O module is responsible for error detection such as mechanical and electrical malfunction
reported by device e.g. paper jam, bad ink track & unintentional changes to the bit pattern
and transmission error.

I/O Module Structure

 The I/O bus from the processor is attached to all peripheral interfaces
 To communicate with the particular devices, the processor places a device address on the
address bus.
 Each interface contains an address decoder that monitors the address line.
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 When the interface detects the particular device address, it activates the path between the
data line and devices that it controls.
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  At the same time that the address is made available in the address line, the processor
provides a function code in the control way includes control command, output data and
input data.

I/O Module Decisions

 Hide or reveal device properties to CPU
 Support multiple or single device
 Control device functions or leave for CPU
 Also O/S decisions
 e.g. Unix treats everything it can as a file

Input-Output interface
 Input-Output interface provides a method for transferring information between internal
storage (such as memory and CPU registers) and external I/O devices.
 Peripherals connected to a computer need special communication links for interfacing them
with the central processing unit.
 The communication link resolves the following differences between the computer and
peripheral devices.
 Devices and signals
 Peripherals - Electromechanical Devices CPU or Memory - Electronic Device
 Data Transfer Rate
 Peripherals - Usually slower
 CPU or Memory - Usually faster than peripherals
 Some kinds of Synchronization mechanism may be needed
 Unit of Information
 Peripherals - Byte CPU or Memory - Word
 Operating Modes
 Peripherals - Autonomous, Asynchronous CPU or Memory – Synchronous
 To resolve these differences, computer systems include special hardware components
(Interfaces) between the CPU and peripherals to supervise and synchronize all input and
output interfaces.

I/O Bus and Interface Modules

The I/O bus consists of data lines, address lines and control lines.

Fig: Connection of I/O bus to input-output devices

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 Interface performs the following:

 Decodes the device address (device code)
 Decodes the commands (operation)
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 Provides signals for the peripheral controller
Synchronizes the data flow and supervises the transfer rate between peripheral and
CPU or Memory
 I/O commands that the interface may receive:
 Control command: issued to activate the peripheral and to inform it what to do.
 Status command: used to test various status conditions in the interface and the
peripheral.
 Output data: causes the interface to respond by transferring data from the bus into
one of its registers.
 Input data: is the opposite of the data output.

I/O versus Memory Bus

 Computer buses can be used to communicate with memory and I/O in three ways:
 Use two separate buses, one for memory and other for I/O. In this method, all data,
address and control lines would be separate for memory and I/O.
 Use one common bus for both memory and I/O but have separate control lines.
There is a separate read and write lines; I/O read and I/O write for I/O and memory
read and memory write for memory.
 Use a common bus for memory and I/O with common control line. This I/O
configuration is called memory mapped.

Isolated I/O versus Memory Mapped I/O

 Isolated I/O
 Separate I/O read/write control lines in addition to memory read/write control
lines
 Separate (isolated) memory and I/O address spaces
 Distinct input and output instructions

 Memory-mapped I/O
 A single set of read/write control lines (no distinction between memory and I/O
transfer)
 Memory and I/O addresses share the common address space which reduces memory
address range available
 No specific input or output instruction so the same memory reference instructions
can be used for I/O transfers
 Considerable flexibility in handling I/O operations

Example of I/O Interface

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  Information in each port can be assigned a meaning depending on the mode of operation of
the I/O device
 Port A = Data; Port B = Command; Port C = Status
 CPU initializes (loads) each port by transferring a byte to the Control Register
 Allows CPU can define the mode of operation of each port
 Programmable Port: By changing the bits in the control register, it is possible to
change the interface characteristics

Modes of transfer
 Data Transfer between the central computer and I/O devices may be handled in a variety of
modes.
 Some modes use CPU as an intermediate path, others transfer the data directly to and from
the memory unit.
 Data transfer to and from peripherals may be handled in one of three possible modes.
 Programmed I/O
 Interrupt Driven I/O
 Direct Memory Access (DMA)
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PROGRAMMED I/O
 Programmed I/O operations are the result of I/O instructions written in the computer
program.
 In programmed I/O, each data transfer in initiated by the instructions in the CPU and hence
the CPU is in the continuous monitoring of the interface.
 Input instruction is used to transfer data from I/O device to CPU, store instruction is used to
transfer data from CPU to memory and output instruction is used to transfer data from CPU
to I/O device.
 This technique is generally used in very slow speed computer and is not a efficient method
if the speed of the CPU and I/O is different.

 I/O device places the data on the I/O bus and enables its data valid signal
 The interface accepts the data in the data register and sets the F bit of status register and
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also enables the data accepted signal.

 Data valid line is disables by I/O device.
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  CPU is in a continuous monitoring of the interface in which it checks the F bit of the status
register.
 If it is set i.e. 1, then the CPU reads the data from data register and sets F bit to zero
 If it is reset i.e. 0, then the CPU remains monitoring the interface.
 Interface disables the data accepted signal and the system goes to initial state where next
item of data is placed on the data bus.

Characteristics:
 Continuous CPU involvement
 CPU slowed down to I/O speed
 Simple
 Least hardware
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Polling, or polled operation, in computer science, refers to actively sampling the status of an
external device by a client program as a synchronous activity. Polling is most often used in terms of
input/output (I/O), and is also referred to as polled I/O or software driven I/O.
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Interrupt-driven I/O
 Polling takes valuable CPU time
 Open communication only when some data has to be passed -> Interrupt.
 I/O interface, instead of the CPU, monitors the I/O device
 When the interface determines that the I/O device is ready for data transfer, it generates an
Interrupt Request to the CPU
 Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches
 to the service routine to process the data transfer, and then returns to the task it was
performing
 The problem with programmed I/O is that the processor has to wait a long time for the I/O
module of concern to be ready for either reception or transmission of data.
 The processor, while waiting, must repeatedly interrogate the status of the I/O module.
 As a result, the level of the performance of the entire system is severely degraded.
 An alternative is for the processor to issue an I/O command to a module and then go on to
do some other useful work.
 The I/O module will then interrupt the processor to request service when it is ready to
exchange data with processor.
 The processor then executes the data transfer, and then resumes its former processing. The
interrupt can be initiated either by software or by hardware.

Interrupt Driven I/O basic operation

 CPU issues read command
 I/O module gets data from peripheral whilst CPU does other work
 I/O module interrupts CPU
 CPU requests data
 I/O module transfers data

Interrupt Processing from CPU viewpoint

 Issue read command
 Do other work
 Check for interrupt at end of each instruction cycle
 f interrupted:-
 Save context (registers)
 Process interrupt
 Fetch data & store

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Priority Interrupt
 Determines which interrupt is to be served first when two or more requests are made
simultaneously
 Also determines which interrupts are permitted to interrupt the computer while another is
being serviced
 Higher priority interrupts can make requests while servicing a lower priority interrupt

Priority Interrupt by Software (Polling)

 Priority is established by the order of polling the devices (interrupt sources), that is identify
the highest-priority source by software means
 One common branch address is used for all interrupts
 Program polls the interrupt sources in sequence
 The highest-priority source is tested first
 Flexible since it is established by software
 Low cost since it needs a very little hardware
 Very slow

Priority Interrupt by Hardware

 Require a priority interrupt manager which accepts all the interrupt requests to determine
the highest priority request
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 Fast since identification of the highest priority interrupt request is identified by the
hardware
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Computer Organization and Architecture By S RAMESH Asst. Professor

  Fast since each interrupt source has its own interrupt vector to access directly to its own
service routine
1. Daisy Chain Priority (Serial)

 Interrupt Request from any device

 CPU responds by INTACK
 Any device receives signal (INTACK) at PI puts the VAD on the bus
 Among interrupt requesting devices the only device which is physically closest to CPU gets
INTACK and it blocks INTACK to propagate to the next device

2. Parallel Priority
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 Fig: Parallel Priority Interrupts Hardware

 IEN: Set or Clear by instructions ION or IOF

 IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to
load VAD generated by the Priority Logic
 Interrupt Register:
 Each bit is associated with an Interrupt Request from different Interrupt Source -
different priority level
 Each bit can be cleared by a program instruction
 Mask Register:
 Mask Register is associated with Interrupt Register
 Each bit can be set or cleared by an Instruction

Priority Encoder
 Determines the highest priority interrupt when more than one interrupts take place

Interrupt Cycle
At the end of each Instruction cycle
 CPU checks IEN and IST
 If IEN and IST = 1, CPU -> Interrupt Cycle
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 SP  SP – 1; Decrement stack pointer

 M[SP]  PC; Push PC into stack
 INTACK  1; Enable interrupt acknowledge
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  PC  VAD; Transfer vector address to PC
 IEN  0; Disable further interrupts
 Go To Fetch to execute the first instruction in the interrupt service routine

DMA (DIRECT MEMORY ACCESS)

 Large blocks of data transferred at a high speed to or from high speed devices, magnetic
drums, disks, tapes, etc.
 DMA controller Interface that provides I/O transfer of data directly to and from the memory
and the I/O device
 CPU initializes the DMA controller by sending a memory address and the number of words
to be transferred
 Actual transfer of data is done directly between the device and memory through
DMA controller -> Freeing CPU for other tasks
The transfer of data between the peripheral and memory without the interaction of CPU and
letting the peripheral device manage the memory bus directly is termed as Direct Memory Access
(DMA).

Fig: CPU bus signal for DMA transfer

 The two control signals Bus Request and Bus Grant are used to fascinate the DMA transfer.
 The bus request input is used by the DMA controller to request the CPU for the control of
the buses.
 When BR signal is high, the CPU terminates the execution of the current instructions and
then places the address, data, read and write lines to the high impedance state and sends
the bus grant signal.
 The DMA controller now takes the control of the buses and transfers the data directly
between memory and I/O without processor interaction.
 When the transfer is completed, the bus request signal is made low by DMA.
 In response to which CPU disables the bus grant and again CPU takes the control of address,
data, read and write lines.
 The transfer of data between the memory and I/O of course facilitates in two ways which
are DMA Burst and Cycle Stealing.
 DMA Burst: The block of data consisting a number of memory words is transferred
at a time.
 Cycle Stealing: DMA transfers one data word at a time after which it must return
control of the buses to the CPU.
 CPU is usually much faster than I/O (DMA), thus CPU uses the most of the memory cycles
 DMA Controller steals the memory cycles from CPU
 For those stolen cycles, CPU remains idle
 For those slow CPU, DMA Controller may steal most of the memory cycles which may cause
CPU remain idle long time

DMA Controller
 The DMA controller communicates with the CPU through the data bus and control lines.
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 DMA select signal is used for selecting the controller, the register select is for selecting the
register.
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Computer Organization and Architecture By S RAMESH Asst. Professor

  When the bus grant signal is zero, the CPU communicates through the data bus to read or
write into the DMA register.
 When bus grant is one, the DMA controller takes the control of buses and transfers the data
between the memory and I/O.

Fig: Block diagram of DMA controller

 The address register specifies the desired location of the memory which is incremented
after each word is transferred to the memory.
 The word count register holds the number of words to be transferred which is decremented
after each transfer until it is zero. When it is zero, it indicates the end of transfer.
 After which the bus grant signal from CPU is made low and CPU returns to its normal
operation.
 The control register specifies the mode of transfer which is Read or Write.

DMA Transfer
 DMA request signal is given from I/O device to DMA controller.
 DMA sends the bus request signal to CPU in response to which CPU disables its current
instructions and initialize the DMA by sending the following information.
 The starting address of the memory block where the data are available (for read)
and where data to be stored (for write)
 The word count which is the number of words in the memory block
 Control to specify the mode of transfer
 Sends a bust grant as 1 so that DMA controller can take the control of the buses
 DMA sends the DMA acknowledge signal in response to which peripheral device puts
the words in the data bus (for write) or receives a word from the data bus (for read).
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 Fig: DMA transfer in a computer system
DMA Operation
 CPU tells DMA controller:-
 Read/Write
 Device address
 Starting address of memory block for data
 Amount of data to be transferred
 CPU carries on with other work
 DMA controller deals with transfer
 DMA controller sends interrupt when finished

I/O Processors
 Processor with direct memory access capability that communicates with I/O devices
 Channel accesses memory by cycle stealing
 Channel can execute a Channel Program
 Stored in the main memory
 Consists of Channel Command Word(CCW)
 Each CCW specifies the parameters needed by the channel to control the I/O devices and
perform data transfer operations
 CPU initiates the channel by executing a channel I/O class instruction and once initiated,
channel operates independently of the CPU
 A computer may incorporate one or more external processors and assign them the task of
communicating directly with the I/O devices so that no each interface need to communicate
with the CPU.
 An I/O processor (IOP) is a processor with direct memory access capability that
communicates with I/O devices.
 IOP instructions are specifically designed to facilitate I/O transfer.
 The IOP can perform other processing tasks such as arithmetic logic, branching and code
translation.
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  The memory unit occupies a central position and can communicate with each processor by
means of direct memory access.
 The CPU is responsible for processing data needed in the solution of computational tasks.
The IOP provides a path for transferring data between various peripheral devices and
memory unit.
 In most computer systems, the CPU is the master while the IOP is a slave processor.
 The CPU initiates the IOP and after which the IOP operates independent of CPU and transfer
data between the peripheral and memory.
 For example, the IOP receives 5 bytes from an input device at the device rate and bit
capacity.
 After which the IOP packs them into one block of 40 bits and transfer them to memory.
 Similarly the O/P word transfer from memory to IOP is directed from the IOP to the O/P
device at the device rate and bit capacity.

CPU – IOP Communication

 The memory unit acts as a message center where each processor leaves information for the
other.
 The operation of typical IOP is appreciated with the example by which the CPU and IOP
communication.

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  The CPU sends an instruction to test the IOP path.
 The IOP responds by inserting a status word in memory for the CPU to check.
 The bits of the status word indicate the condition of the IOP and I/O device, such as IOP
overload condition, device busy with another transfer or device ready for I/O transfer.
 The CPU refers to the status word in in memory to decide what to do next.
 If all right up to this, the CPU sends the instruction to start I/O transfer.
 The CPU now continues with another program while IOP is busy with I/O program.
 When IOP terminates the execution, it sends an interrupt request to CPU.
 CPU responds by issuing an instruction to read the status from the IOP.
 IOP responds by placing the contents to its status report into specified memory location.
 Status word indicates whether the transfer has been completed or with error.

Data Communication Processor

Distributes and collects data from many remote terminals connected through telephone and other
communication lines.
 Transmission:
 Synchronous
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 Asynchronous
 Transmission Error:
 Parity
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 Checksum
Computer Organization and Architecture By S RAMESH Asst. Professor
  Cyclic Redundancy Check
 Longitudinal Redundancy Check  Transmission Modes:
 Simples
 Half Duplex
 Full Duplex

Data Link & Protocol

 A data communication (command) processor is an I/O processor that distributes and
collects data from remote terminals connected through telephone and other
communication lines.
 In processor communication, processor communicates with the I/O device through a
common bus i.e. data and control with sharing by each peripherals.
 In data communication, processor communicates with each terminal through a single pair
of wires.

 The way that remote terminals are connected to a data communication processor is via
telephone lines or other public or private communication facilities.
 The data communication may be either through synchronous transmission or through
asynchronous transmission.
 One of the functions of data communication processor is check for transmission errors.
 An error can be detected by checking the parity in each character received.
 The other ways are checksum, longitudinal redundancy check (LRC) and cyclic redundancy
check (CRC).

 Data can be transmitted between two points through three different modes.
 First is simplex where data can be transmitted in only one direction such as TV
broadcasting.
 Second is half duplex where data can be transmitted in both directions at a time such as
walkie-talkie. The third is full duplex where data can be transmitted in both directions
simultaneously such as telephone.

 The communication lines, modems and other equipment used in the transmission of
information between two or more stations is called data link.
 The orderly transfer of information in a data link is accomplished by means of a protocol.

MEMORY ORGANIZATION
MEMORY HIERARCHY

Memory hierarchy in a computer system:

Memory hierarchy system consists of all storage devices employed in a computer system from the
slow but high capacity auxiliary memory to a relatively faster main memory, to an even smaller
and faster cache memory accessible to the high speed processing logic.

 Main Memory: memory unit that communicates directly with the CPU (RAM)
 Auxiliary Memory: device that provide backup storage (Disk Drives)
 Cache Memory: special very-high-speed memory to increase the processing speed (Cache
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RAM)

 Figure12- 1 illustrates the components in a typical memory hierarchy.

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  At the bottom of the hierarchy are the relatively slow magnetic tapes used to store
removable files.
 Next are the Magnetic disks used as backup storage.
 The main memory occupies a central position by being able to communicate directly with
CPU and with auxiliary memory devices through an I/O process.
 Program not currently needed in main memory are transferred into auxiliary memory to
provide space for currently used programs and data.
 The cache memory is used for storing segments of programs currently being executed in
the CPU.
 The I/O processor manages data transfer between auxiliary memory and main memory.
 The auxiliary memory has a large storage capacity is relatively inexpensive, but has low
access speed compared to main memory.
 The cache memory is very small, relatively expensive, and has very high access speed.
 The CPU has direct access to both cache and main memory but not to auxiliary memory.

Multiprogramming:
 Many operating systems are designed to enable the CPU to process a number of
independent programs concurrently.
 Multiprogramming refers to the existence of 2 or more programs in different parts of the
memory hierarchy at the same time.

Memory management System:

 The part of the computer system that supervises the flow of information between auxiliary
memory and main memory.

MAIN MEMORY
 Main memory is the central storage unit in a computer system. It is a relatively large and
fast memory used to store programs and data during the computer operation.
 The principal technology used for the main memory is based on semiconductor integrated
circuits.
 Integrated circuits RAM chips are available in two possible operating modes, static and
dynamic.
 Static RAM – Consists of internal flip flops that store the binary information.
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 Dynamic RAM – Stores the binary information in the form of electric charges that are
applied to capacitors.
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Computer Organization and Architecture By S RAMESH Asst. Professor

  Most of the main memory in a general purpose computer is made up of RAM integrated
circuit chips, but a portion of the memory may be constructed with ROM chips.
 Read Only Memory –Store programs that are permanently resident in the computer
and for tables of constants that do not change in value once the production of the
computer is completed.
 The ROM portion of main memory is needed for storing an initial program called a
Bootstrap loader.
 Boot strap loader –function is start the computer software operating when power is
turned on.
 Boot strap program loads a portion of operating system from disc to main memory
and control is then transferred to operating system.

RAM and ROM CHIP

 RAM chip –utilizes bidirectional data bus with three state buffers to perform
communication with CPU
 The block diagram of a RAM Chip is shown in Fig.12-2.
 The capacity of memory is 128 words of eight bits (one byte) per word.
 This requires a 7-bit address and an 8-bit bidirectional data bus.
 The read and write inputs specify the memory operation and the two chips select (CS)
control inputs are enabling the chip only when it is selected by the microprocessor.
 The read and write inputs are sometimes combined into one line labelled R/W.

 The function table listed in Fig.12-2(b) specifies the operation of the RAM chip.
 The unit is in operation only when CS1=1 and CS2=0.The bar on top of the second select
variable indicates that this input is enabled when it is equal to 0.
 If the chip select inputs are not enabled, or if they are enabled but the read or write inputs
are not enabled, the memory is inhibited and its data bus is in a high-impedance state.
 When CS1=1 and CS2=0, the memory can be placed in a write or read mode.
 When the WR input is enabled, the memory stores a byte from the data bus into a location
specified by the address input lines.

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  When the RD input is enabled, the content of the selected byte is placed into the data bus.
 The RD and WR signals control the memory operation as well as the bus buffers associated
with the bidirectional data bus.

ROM
 A memory is called a read-only memory, or ROM, when information can be written into it only
once at the time of manufacture. A logic value 0 is stored in the cell if the transistor is connected
to ground at point P; otherwise, a 1 is stored.
 The bit line is connected through a resistor to the power supply.
 To read the state of the cell, the word line is activated to close the transistor switch.
 As a result, the voltage on the bit line drops to near zero if there is a connection between the
transistor and ground.
 If there is no connection to ground, the bit line remains at the high voltage level, indicating a 1.
 A sense circuit at the end of the bit line generates the proper output value.
 The state of the connection to ground in each cell is determined when the chip is manufactured,
using a mask with a pattern that represents the information to be stored.

 A ROM chip is organized externally in a similar manner.

 However, since a ROM can only read, the data bus can only be in an output mode.
 The block diagram of a ROM chip is shown in fig.12-3.
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  The nine address lines in the ROM chip specify any one of the512 bytes stored in it.
 The two chip select inputs must be CS1=1 and CS2=0 for the unit to operate.
 Otherwise, the data bus is in a high-impedance state.

PROM
 Some ROM designs allow the data to be loaded by the user, thus providing a programmable
ROM (PROM).
 Programmability is achieved by inserting a fuse at point P.
 Before it is programmed, the memory contains all 0s.
 The user can insert 1s at the required locations by burning out the fuses at these locations using
high-current pulses. Of course, this process is irreversible.
 PROMs provide flexibility and convenience not available with ROMs.
 The cost of preparing the masks needed for storing a particular information pattern makes ROMs
cost effective only in large volumes.
 The alternative technology of PROMs provides a more convenient and considerably less
expensive approach, because memory chips can be programmed directly by the user.

EPROM
 Another type of ROM chip provides an even higher level of convenience.
 It allows the stored data to be erased and new data to be written into it.
 Such an erasable, reprogrammable ROM is usually called an EPROM.
 It provides considerable flexibility during the development phase of digital systems.
 Since EPROMs are capable of retaining stored information for a long time, they can be used in
place of ROMs or PROMs while software is being developed.
 In this way, memory changes and updates can be easily made.
 An EPROM cell has a structure similar to the ROM cell in Figure.
 However, the connection to ground at point P is made through a special transistor.
 The transistor is normally turned off, creating an open switch. It can be turned on by injecting
charge into it that becomes trapped inside.
 Thus, an EPROM cell can be used to construct a memory in the same way as the previously
discussed ROM cell.
 Erasure requires dissipating the charge trapped in the transistors that form the memory cells.
 This can be done by exposing the chip to ultraviolet light, which erases the entire contents of the
chip.
 To make this possible, EPROM chips are mounted in packages that have transparent windows.
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EEPROM
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 An EPROM must be physically removed from the circuit for reprogramming.

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  Also, the stored information cannot be erased selectively.
 The entire contents of the chip are erased when exposed to ultraviolet light.
 Another type of erasable PROM can be programmed, erased, and reprogrammed electrically.
 Such a chip is called an electrically erasable PROM, or EEPROM. It does not have to be
removed for erasure.
 Moreover, it is possible to erase the cell contents selectively.
 One disadvantage of EEPROMs is that different voltages are needed for erasing, writing, and
reading the stored data, which increases circuit complexity.
 However, this disadvantage is outweighed by the many advantages of EEPROMs.
 They have replaced EPROMs in practice.

Memory Address Map

 The interconnection between memory and processor is then established from knowledge of
the size of memory needed and the type of RAM and ROM chips available.
 The addressing of memory can be established by means of a table that specify the memory
address assigned to each chip.
 The table called Memory address map, is a pictorial representation of assigned address
space for each chip in the system.
 The memory address map for this configuration is shown in table 12-1.

 The component column specifies whether a RAM or a ROM chip is used.

 The hexadecimal address column assigns a range of hexadecimal equivalent addresses for
each chip. The address bus lines are listed in the third column.
 The RAM chips have 128 bytes and need seven address lines.
 The ROM chip has 512 bytes and needs 9 address lines.

Memory Connection to CPU:

 RAM and ROM chips are connected to a CPU through the data and address buses.
 The low order lines in the address bus select the byte within the chips and other lines in the
address bus select a particular chip through its chip select inputs.

 The connection of memory chips to the CPU is shown in Fig.12-4.

 This configuration gives a memory capacity of 512 bytes of RAM and 512 bytes of ROM.
 Each RAM receives the seven low-order bits of the address bus to select one of 128 possible
bytes.
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 The particular RAM chip selected is determined from lines 8 and 9 in the address bus.
 This is done through a 2 X 4 decoder whose outputs go to the CS1 inputs in each RAM chip.
 Thus, when address lines 8 and 9 are equal to 00, the first RAM chip is selected.
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  When 01, the second RAM chip is select, and so on.
 The RD and WR outputs from the microprocessor are applied to the inputs of each RAM
chip.
 The selection between RAM and ROM is achieved through bus line 10.
 The RAMs are selected when the bit in this line is 0, and the ROM when the bit is 1.
 Address bus lines 1 to 9 are applied to the input address of ROM without going through the
decoder.
 The data bus of the ROM has only an output capability, whereas the data bus connected to
the RAMs can transfer information in both directions.

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AUXILIARY MEMORY
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  The time required to find an item stored in memory can be reduced considerably if stored
data can be identified for access by the content of the data itself rather than by an address.
 A memory unit accessed by content is called an associative memory or content addressable
memory (CAM).
 CAM is accessed simultaneously and in parallel on the basis of data content rather
than by specific address or location
 Associative memory is more expensive than a RAM because each cell must have
storage capability as well as logic circuits
 Argument register –holds an external argument for content matching
 Key register –mask for choosing a particular field or key in the argument word

Hardware Organization

 It consists of a memory array and logic for m words with n bits per word.
 The argument register A and key register K each have n bits, one for each bit of a word.
 The match register M has m bits, one for each memory word.
 Each word in memory is compared in parallel with the content of the argument register.
 The words that match the bits of the argument register set a corresponding bit in the match
register. After the matching process, those bits in the match register that have been set
indicate the fact that their corresponding words have been matched.
 Reading is accomplished by a sequential access to memory for those words whose
corresponding bits in the match register have been set.
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 The relation between the memory array and external registers in an associative memory is
shown in Fig.12-7.
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  The cells in the array are marked by the letter C with two subscripts.
 The first subscript gives the word number and second specifies the bit position in the word.
 Thus cell Cij is the cell for bit j in word i.
 A bit Aj in the argument register is compared with all the bits in column j of the array
provided that kj =1.This is done for all columns j=1, 2,…, n.
 If a match occurs between all the unmasked bits of the argument and the bits in word I, the
corresponding bit Mi in the match register is set to 1.
 If one or more unmasked bits of the argument and the word do not match, M i is cleared to 0.

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  It consists of flip-flop storage element Fij and the circuits for reading, writing, and matching
the cell. The input bit is transferred into the storage cell during a write operation.
 The bit stored is read out during a read operation.
 The match logic compares the content of the storage cell with corresponding unmasked bit
of the argument and provides an output for the decision logic that sets the bit in M i.

Match Logic

 The match logic for each word can be derived from the comparison algorithm for two
binary numbers.
 First, neglect the key bits and compare the argument in A with the bits stored in the cells of
the words.

 Word i is equal to the argument in A if Aj=F ijfor j=1,2,…..,n.

 Two bits are equal if they are both 1 or both 0. The equality of two bits can be expressed
logically by the Boolean function
xj=Aj Fij + Aj ‘Fij ‘
 Where xj = 1 if the pair of bits in position j are equal; otherwise, xj =0.
 For a word i is equal to the argument in A we must have all xj variables equal to 1.
 This is the condition for setting the corresponding match bit Mi to 1.
 The Boolean function for this condition is Mi = x1 x2 x3…… xn

 Each cell requires two AND gate and one OR gate.

 The inverters for A and K are needed once for each column and are used for all bits in the
column.
 The output of all OR gates in the cells of the same word go to the input of a common AND
gate to generate the match signal for Mi.
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 Mi will be logic 1 if a match occurs and 0 if no match occurs.

Read and Write operation
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Read Operation
 If more than one word in memory matches the unmasked argument field, all the matched
words will have 1’s in the corresponding bit position of the match register
 In read operation all matched words are read insequence by applying a read signal to
each word line whose corresponding Mi bit is a logic 1
 In applications where no two identical items are stored in the memory, only one word may
match, in which case we can use Mi output directly as a read signal for the corresponding
word

Write Operation
Can take two different forms
1. Entire memory may be loaded with new information
2. Unwanted words to be deleted and new words to be inserted

1.Entire memory : writing can be done by addressing each location in sequence – This makes it
random access memory for writing and content addressable memory for reading – number of lines
needed for decoding is d Where m = 2 d , m is number of words.

2. Unwanted words to be deleted and newwords to be inserted:

 Tag register is used which has as many bits as there are words in memory
 For every active (valid) word in memory, the corresponding bit in tag register is set to 1
 When word is deleted the corresponding tag bit is reset to 0
 The word is stored in the memory by scanning the tag register until the first 0 bit is
encountered after storing the word the bit is set to 1.

CACHE MEMORY
 Effectiveness of cache mechanism is based on a property of computer programs called
“locality of reference”
 The references to memory at any given time interval tend to be confined within a localized
areas
 Analysis of programs shows that most of their execution time is spent on routines in which
instructions are executed repeatedly These instructions may be – loops, nested loops , or
few procedures that call each other
 Many instructions in localized areas of program are executed repeatedly during some time
period and reminder of the program is accessed infrequently, this property is called
“Locality of Reference”.

Locality of Reference
Locality of reference is manifested in two ways:
1. Temporal- means that a recently executed instruction is likely to be executed again very soon.
 The information which will be used in near future is likely tobe in use already (e.g. reuse
of information in loops)
2. Spatial- means that instructions in close proximity to a recently executed instruction are also
likely to be executed soon
 If a word is accessed, adjacent (near) words are likely to be accessed soon (e.g. related data
items (arrays) are usually stored together; instructions are executed sequentially)
3. If active segments of a program can be placed in a fast (cache) memory, then total execution time
can be reduced significantly
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4. Temporal Locality of Reference suggests whenever an information (instruction or data) is

needed first, this item should be brought in to cache
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5. Spatial aspect of Locality of Reference suggests that instead of bringing just one item from the
main memory to the cache, it is wise to bring several items that reside at adjacent addresses as
well (i.e., a block of information)

Principles of cache

 The main memory can store 32k words of 12 bits each.

 The cache is capable of storing 512 of these words at any given time. For every word stored,
there is a duplicate copy in main memory.
 The CPU communicates with both memories. It first sends a 15 bit address to cache.
 If there is a hit, the CPU accepts the 12 bit data from cache. If there is a miss, the CPU reads
the word from main memory and the word is then transferred to cache.
 When a read request is received from CPU, contents of a block of memory words containing
the location specified are transferred in to cache
 When the program references any of the locations in this block, the contents are
read from the cache Number of blocks in cache is smaller than number of blocks in
main memory
 Correspondence between main memory blocks and those in the cache is specified by
a mapping function
 Assume cache is full and memory word not in cache is referenced
 Control hardware decides which block from cache is to be removed to create space
for new block containing referenced word from memory
 Collection of rules for making this decision is called “Replacement algorithm”

Read/ Write operations on cache

Cache Hit Operation
 CPU issues Read/Write requests using addresses thatrefer to locations in main memory
 Cache control circuitry determines whether requested word currently exists in cache
 If it does, Read/Write operation is performed on the appropriate location in cache
(Read/Write Hit)

Read/Write operations on cache in case of Hit

 In Read operation main memory is not involved.
 In Write operation two things can happen.
1. Cache and main memory locations are updatedsimultaneously (“Write Through”) OR
2. Update only cache location and mark it as “Dirty orModified Bit” and update main
memory location at the time of cache block removal (“Write Back” or “Copy Back”).

Read/Write operations on cache in case of Miss Read Operation

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When addressed word is not in cache Read Miss occurs there are two ways this can be dealt with
1. Entire block of words that contain the requested word is copied from main memory to cache and
the particular word requested is forwarded to CPU from the cache (Load Through) (OR)
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2. The requested word from memory is sent to CPU first and then the cache is updated (Early
Restart)

Write Operation
 If addressed word is not in cache Write Miss occurs
 If write through protocol is used information is directly written in to main memory
 In write back protocol, block containing the word is first brought in to cache , the desired
word is then overwritten.

Mapping Functions
 Correspondence between main memory blocks and those in the cache is specified by a
memory mapping function
 There are three techniques in memory mapping:
1. Direct Mapping
2. Associative Mapping
3. Set Associative Mapping

Direct mapping:
 A particular block of main memory can be brought to a particular block of cache memory.
So, it is not flexible.

 In fig 12-12. The CPU address of 15 bits is divided into two fields.
 The nine least significant bits constitute the index field and remaining six bits form the tag
field.
 The main memory needs an address that includes both the tag and the index bits.
 The number of bits in the index field is equal to the number of address bits required to
access the cache memory.
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  The direct mapping cache organization uses the n- bit address to access the main memory
and the k-bit index to access the cache.
 Each word in cache consists of the data word and associated tag.
 When a new word is first brought into the cache, the tag bits are stored alongside the data
bits.
 When the CPU generates a memory request, the index field is used the index field is used for
the address to access the cache.
 The tag field of the CPU address is compared with the tag in the word read from the cache.
 If the two tags match, there is a hit and the desired data word is in cache.
 If there is no match, there is a miss and the required word is read from main memory.

 In fig 12-14, the index field is now divided into two parts:
 Block field and the word field.
 In a 512 word cache there are 64 blocks of 8 words each, since 64X8=512.
 The block number is specified with a 6 bit field and the word with in the block is
specified with a 3-bit field.
 The tag field stored within the cache is common to all eight words of the same block. 149
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Associative mapping:
 In this mapping function, any block of Main memory can potentially reside in any cache
block position.
 This is much more flexible mapping method.
 In fig 12-11, The associative memory stores both address and content(data) of the memory
word.
 This permits any location in cache to store any word from main memory.
 The diagram shows three words presently stored in the cache.
 The address value of 15 bits is shown as a five-digit octal number and its corresponding 12-
bit word is shown as a four-digit octal number.
 A CPU address of 15-bits is placed in the argument register and the associative memory is
searched for a matching address.
 If address is found, the corresponding 12-bit data is read and sent to the CPU. If no match
occurs, the main memory is accessed for the word.

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Set-associative mapping:
 In this method, blocks of cache are grouped into sets, and the mapping allows a block of
main memory to reside in any block of a specific set.
 From the flexibility point of view, it is in between to the other two methods.
 The octal numbers listed in Fig.12-15 are with reference to the main memory contents.
 When the CPU generates a memory request, the index values of the address is used to
access the cache.
 The tag field of the CPU address is then compared with both tags in the cache to determine
if a match occurs.
 The comparison logic dine by an associative search of the tags in the set similar to an
associative memory search thus the name “Set Associative”.

Replacement Policies
 When the cache is full and there is necessity to bring new data to cache, then a decision
must be made as to which data from cache is to be removed
 The guideline for taking a decision about which data is to be removed is called replacement
policy Replacement policy depends on mapping
 There is no specific policy in case of Direct mapping as we have no choice of block
placement in cache Replacement Policies

In case of associative mapping

 A simple procedure is to replace cells of the cache in round robin order whenever a new
word is requested from memory
 This constitutes a First-in First-out (FIFO) replacement policy

In case of set associative mapping

 Random replacement
 First-in First-out (FIFO) (item chosen is the item that has been in the set longest)
 Least Recently Used (LRU)( item chosen is the itemthat has been least recently used by
CPU)
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VIRTUAL MEMORY
 Early days memory was expensive – hence small
 Programmers were using secondary storage for overlaying
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  Programmers were responsible for breaking programs in to overlays, decide where to keep
in secondary memory, arranging for transfer of overlays between main memory and
secondary memory
 In 1961 Manchester University proposed a method for performing overlay process
automatically which has given rise to the concept of Virtual memory today

Virtual Memory - Background

 Separate concept of address space andmemory locations
 Programs reference instructions and data that is independent of available physical memory
Addresses issued by processor for Instructions or Data are called Virtual or Logical
addresses
 Virtual addresses are translated in to physical addresses by a combination of Hardware and
Software components

Types of Memory
 Real memory
 Main memory
 Virtual memory
 Memory on disk
 Allows for effective multiprogramming andrelieves the user of tight constraints of main
memory

Address Space and Memory Space

 Address used by a programmer is called virtual address and set of such addresses is called
address space
 Address in main memory is called a locationor physical address and set of such locations
is called the memory space
 The Address Space is allowed to be largerthan the memory space in computers with
virtual memory

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 In a multiprogram computer system, programs and data are transferred to and from
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  Suppose that program1 is currently being executed in the CPU.
 Program1 and a portion of its associated data are moved from auxiliary memory into main
memory as shown in fig. 12-16.
 Portions of programs and data need not be in contiguous locations in memory since
information is being moved in out, and empty spaces may be available in scattered locations
in memory.

 In fig 12-17, to map a virtual address of 20 bits to a physical address of 15 bits.

 The mapping is a dynamic operation, which means that every address is translated
immediately as a word is referenced by CPU.
 The mapping table may be stored in a separate memory.
 In first case, an additional unit is required as well as one extra memory access time.
 In the second case, the table takes space from main memory and two accesses to memory
are required with program running at half speed.
 A third alternative is to use an associative memory.

Address Mapping Using Pages

 The physical memory is broken down into groups of equal size called blocks, which may
range from 64 to 4096 word each.
 The term page refers to groups of address space of the same size.
 Portions of programs are moved from auxiliary memory to main memory in records equal
to the size of a page.
 The term “page frame” is sometimes used to denote a block.

 In fig 12-18, a virtual address has 13 bits.

 Since each page consists of 1024 words, the high order three bits of virtual address will
specify one of the eight pages and the low order 10 bits give the line address within the
page.
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  The organization of the memory mapping table in a paged system is shown in Fig.12-19.
 The memory page table consists of eight word, one for each page.
 The address in the page table denotes the page number and the content of the word gives
the block number where that page is stored in main memory.
 The table shows that pages 1, 2, 5 and 6 are now available in main memory in blocks 3, 0, 1
and 2, respectively.

Associative Memory Page Table

 A random-access memory page table is inefficient with respect to storage utilization.
 Replace the random access memory-page table with an associative memory of four words
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as shown in Fig12-20.
 Each entry in the associative memory array consists of two fields.
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  The last two bits constitute a field for storing the block number.
 The virtual address is placed in the argument register.

Address Translation
 A table is needed to map virtual address to a physical address (dynamic operation)
 This table may be kept in
 a separate memory or
 main memory or
 associative memory

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