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A SPICE Netlist to Graphical Schematic Conversion Utility

Preprint · August 2019

DOI: 10.13140/RG.2.2.30170.49606

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 A SPICE Netlist to Graphical Schematic Conversion Utility
Mark Sitkowski
Design Simulation Systems Ltd
http://www.designsim.com.au

Introduction
There are occasions when legacy analogue or digital netlists, perhaps created by hand,
need to be converted into a schematic drawing.
With a little effort, this can sometimes be achieved in a matter of a few hours.
However, when time is at a premium, or when there are just too many netlists, it may be
useful to employ a tool to perform the conversion.

We present a simple utility, imaginatively named ‘net2gex’, which takes, as its input, a
standard SPICE netlist, and converts this to a SCALD (JPL’s ‘Structured Computer-Aided
Logic Design’ standard) schematic diagram.

The utility has many idiosyncrasies, chief among which is the fact that aesthetic
considerations are thrown aside, in favour of connectivity. In other words, it produces
singularly ugly drawings.
Another peculiarity is that, even though the connectivity is correct, the graphical drawing
sometimes shows wires crossing over both pins of a component, without short-circuiting it.
A little manual manipulation of the schematic overcomes both of these idiosyncrasies.

Occasionally, net2gex makes real errors, and these definitely need manual correction.

Some prerequisites
 The netlist must be a standard Berkeley SPICE2 or SPICE3 format netlist. No
enhancements, no extensions
 Any .SUBCKT definitions must be at the very end of the netlist. The utility quits when
it sees one, on the assumption that it has read the complete top level circuit
 All sub-circuits must have an accessible SCALD format body drawing. Almost by
definition, sub-circuits have an unpredictable number of pins, so without a body,
there will be a blank space
 The netlist must include a ground line, which must be node 0

Implementation
Invocation is as follows:

net2gex <filename.netlist>

The suffix is then stripped from the file name, and replaced with ‘_1’. The resulting name, in
this case ‘filename_1’ is used in the creation of a drawing directory.

Note: Although the suffix, which is shown as .netlist, is mandatory, it may be anything like
.ckt, .cir, .net, etc, as long as it exists.

The netlist is then read, and all the devices and their interconnections are loaded into
internal data structures. Node 0 is identified, and replaced with a number which is one more
than the maximum number of nodes in the circuit. The reason for this is that SPICE treats
node 0 as ground, whereas SCALD treats it as ‘NC’ i.e not connected.
Node 0 is then named ‘GND’, while other circuit nodes are assigned names, of the format
‘NODEn’, where ‘n’ is the original SPICE node number. These can be changed in the
schematic editor by the user.

Devices are allocated to sets, according to the node number of the first pin, then that of the
second pin and so on. This facilitates the grouping of devices likely to be connected, so as to
minimise the length of the connecting wire.

Next, a simplistic algorithm locates all devices with at least one pin connected to ground in
alternate columns of the bottom row of a matrix, whose initial dimensions are the square root
of the number of devices. The distance between rows is 700 pixels, and between columns is
800 pixels. This allows space to run connecting wires between columns. It will be noted that
devices on the bottom row will only occupy the odd-numbered columns.

Devices with no ground connections are placed in the row above those that do, in the
nearest even-numbered column to a device on the bottom row with which they share at least
one node number.
The row count advances, as other devices whose node numbers are of the same set as
those below them are added.

Next, a dummy ground symbol is added to the bottom left-hand corner of the schematic, at
coordinates (100, 50). This places the circuit diagram into the first quadrant of the coordinate
map.

Two optimisation functions now run: one for rows, and the other for columns, each with the
goal of minimising distances between devices connected to the same node number.
A check-and-correct routine then ensures that we haven’t placed two or more parts over the
top of each other. If we have, we add another row for each part we need to move.
There is now enough information to create the connectivity file, spice_cn.1.1, and the
graphic description file, spice.1.1, which are placed in the directory we created on startup.

Finally, we perform orthogonal wiring of all the devices, which permits fairly easy manual
repositioning of each component. There was, initially, an option to perform point-to-point
wiring, but the result was such a mess, and so difficult to manually reposition, that this option
was discontinued.

See ‘Shortcomings and Omissions’, at the end of this document.

Testing
We tested the utility as follows:

1. Create a neat and tidy schematic by hand

2. Compile it to create a netlist
3. Run the netlist through the simulator
4. Now feed the netlist to net2gex and view the resulting schematic drawing
5. With no modifications whatever, compile the newly-created schematic
6. Run the netlist through the simulator, and compare the results with (3)
7. Do this for two circuits of differing content and complexity

Example 1: Double-Balanced Suppressed-Carrier Modulator

Figure 1 shows the original circuit schematic, and is followed by its netlist which we used as
input to net2gex, in the attempt to recreate the schematic:
 Figure 1

dbm
.tran 1.0000e-08 5.0000e-06 0.0000e+00
*#iplot all
*#run
*#quit
.print tran v(8) v(10) v(1) i(v1)
.model bc214 pnp bf=140 isc=15e-9
+tf=2n tr=7n vaf=45 cje=5pf vje=0.6 cjc=2pf ikf=0.01

r1 1 0 22
r2 11 2 22
v1 7 0 dc 12
v2 6 0 dc 7.5
v3 8 0 sin 12 50e-3 10meg
v4 9 0 dc 7.5
v5 10 0 sin 7.5 50e-3 1meg
v6 11 0 dc 15
q1 4 8 2 bc214
q2 0 9 4 bc214
q3 0 10 3 bc214
q4 3 7 2 bc214
q5 1 6 3 bc214
q6 1 10 4 bc214
.end

Running the above netlist through the simulator gave the result shown in Figure 2, which
displays the 10MHz carrier, the 1MHz signal, the modulated carrier, and the current in the
12volt power supply:
 Figure 2

The netlist we just simulated was used, untouched, as input to net2gex. The resulting
(ugly...) schematic is shown in Figure 3. At this scale, all text is suppressed, which makes
the circuit look a little stark, but all values and component identifiers reappear when a
section is zoomed-in:

Figure 3
Next, we compiled the schematic of Figure 3, and obtained the netlist which follows. To this
we added the simulator directives from the original netlist:

dbm_1
.tran 1.0000e-08 5.0000e-06 0.0000e+00
*#iplot all
*#run
*#quit
.print tran v(8) v(10) v(1) i(v1)
.model bc214 pnp bf=140 isc=15e-9
+tf=2n tr=7n vaf=45 cje=5pf vje=0.6 cjc=2pf ikf=0.01

r1 1 0 22
r2 11 2 22
v1 7 0 dc 12
v2 6 0 dc 7.5
v3 8 0 sin 12 50e-3 10meg
v4 9 0 dc 7.5
v5 10 0 sin 7.5 50e-3 1meg
v6 11 0 dc 15
q1 4 8 2 bc214
q2 0 9 4 bc214
q3 0 10 3 bc214
q4 3 7 2 bc214
q5 1 6 3 bc214
q6 1 10 4 bc214
.end

Running this netlist through the simulator gave us the results shown in Figure 4 which, apart
from the different names of the nodes, shows that there has been no damage to the original
circuit’s connectivity:

Figure 4
Example 2: 7-Pole Elliptical Filter

Figure 5

This circuit is more complex than the modulator, and uses voltage-controlled voltage sources
(instead of operational amplifiers) and no semiconductor devices - with the exception of the
two clamping diodes.
Its netlist follows:

7pole_elliptic
.ac dec 5.0000e+01 1.0000e+00 1.0000e+07
*#iplot all
*#run
*#quit
.print ac v(18)
.model dthr d vj=0.1

r1 6 5 92k6
r2 7 8 100k
r3 15 14 50k9
r4 11 0 5k78
r5 12 17 248k12
c1 9 8 10n
r6 2 1 100k
r7 9 3 92k6
r8 7 5 10k
r9 13 12 50k9
v1 2 0 pwl 0 0 1ms 0 1.1ms 10 dc 0 ac 1
r10 1 3 100k
r11 1 0 107k8
c2 6 3 10n
r12 5 10 155k1
r13 10 8 100k
r14 10 12 10k
c3 13 14 1n
r15 11 14 100k
r16 10 16 100k
c4 15 16 1n
r17 17 16 100k
r18 17 18 100k
vx 20 0 15
vy 0 19 15
r19 7 0 1g
e1 5 0 1 7 1e6
e2 3 0 0 6 1e6
e3 8 0 0 9 1e6
e4 12 0 11 10 1e6
e5 14 0 0 13 1e6
e6 16 0 0 15 1e6
e7 18 0 0 17 1e6
d1 19 18 dthr
d2 18 20 dthr
.end

Simulating this netlist produces the frequency response shown in Figure 6, below:

Figure 6

The same netlist was used to recreate the filter’s schematic drawing, and produced the
(equally ugly) circuit diagram of Figure 7:
 Figure 7

While we have this drawing on the display, it is worth examining it in detail, to show one of
the shortcomings of the software.
Zooming in to view the top two devices of the group on the left-hand side of the drawing
shows an apparent short-circuit, where a wire crosses both terminals of resistor R12:

Figure 8

However, highlighting the wires entering and leaving the resistor shows that there are two
distinct and separate nets.
 Figure 9

Figure 10

Normally, we would spend some time tidying up the drawing, to make it look a bit more
professional. However, the object of the exercise is to check the connectivity and integrity of
the resulting circuit, so we compile it ‘as is’, and obtain the following netlist:
7pole_elliptic_1
.ac dec 5.0000e+01 1.0000e+00 1.0000e+07
*#iplot all
*#run
*#quit
.print ac v(18)
.model dthr d is=1e-10 cjo=1p

r1 6 5 92k6
r2 7 8 100k
r3 15 14 50k9
r4 11 0 5k78
r5 12 17 248k12
c1 9 8 10n
r6 2 1 100k
r7 9 3 92k6
r8 7 5 10k
r9 13 12 50k9
v1 2 0 pwl 0 0 1ms 0 1.1ms 10 dc 0 ac 1
r10 1 3 100k
r11 1 0 107k8
c2 6 3 10n
r12 5 10 155k1
r13 10 8 100k
r14 10 12 10k
c3 13 14 1n
r15 11 14 100k
r16 10 16 100k
c4 15 16 1n
r17 17 16 100k
r18 17 18 100k
v2 20 0 15
v3 0 19 15
r19 7 0 1g
e1 5 0 1 7 1e6
e2 3 0 0 6 1e6
e3 8 0 0 9 1e6
e4 12 0 11 10 1e6
e5 14 0 0 13 1e6
e6 16 0 0 15 1e6
e7 18 0 0 17 1e6
d1 19 18 dthr
d2 18 20 dthr
.end

Simulating the netlist gives an identical frequency response to that obtained from the netlist
of our original schematic, proving that the reverse-engineering process has maintained the
integrity of the circuit:
 Figure 11

Shortcomings and Omissions

The section of code which reads parts libraries has been temporarily disabled, so net2gex
uses a set of built-in shapes for all of the components of which it has knowledge. Thus, the
current version cannot handle sub-circuits, for which there is no standard body shape.
Work continues on this feature.
Also, it was designed to recognise devices named ‘Unnn’ as digital parts, which clashes with
the SPICE3 Uniform Distributed RC Lines

Conclusion
A ‘decompiling’ tool has been produced which, despite having a few idiosyncrasies and
producing ugly drawings, may well be of use for visualising the schematic of a netlist
Research continues into ways of improving the appearance of the final result, and of the use
of library parts, instead of the built-in shapes of components.

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