ARM® Cortex®-M3 Based 32-Bit MCU

APM32F103x4x6x8xB
ARM® Cortex®-M3 based 32-bit MCU
Version: V 1.2
- 1 DMA, 7 separate configurable
1. Features channels are supported
 System Architecture  Timers
- 32-bit ARM® Cortex®-M3 core - 1 16-bit advanced control timer TMR1,
- Up to 96MHz working frequency support dead zone control and emergency

braking functions
 Clock and Memories
- 3 16-bit general-purpose timers
- HXT: 4MHz~16MHz external crystal
TMR2/3/4, each with up to 4 independent
oscillator supported
channels to support input capture, output
- LXT: 32.768KHz RTC oscillator
comparison, PWM, pulse count and other
supported
functions
- HIRC: 8 MHz RC oscillator with
- 2 watchdog timers(Independent IWDT
calibration
and Window WWDT)
- LIRC: 40 KHz RC oscillator
- 1 24-bit autodecrement SysTick
- Flash : maximum 128 Kbytes
TMRer
- SRAM : maximum 20 Kbytes
 Communication Interfaces
 Power supply and low-power mode
- 3 USARTs, support ISO7816, LIN and
- 2.0 ~ 3.6 V reset supply voltage
IrDA
- Support programmable voltage
- 2 I2C, support SMBus/PMBus
Detector(PVD)
- 2 SPIs with a maximum transfer speed
- Sleep, Stop and Standby modes
of 18Mbps
- VBat power supply can support RTC
- 1 QSPI, support single - and four-wire
and backup registers
access to Flash
 FPU
- 1 USB 2.0 FS Device
- Independent FPU module supports
- 1 CAN 2.0B, USB and CAN can work
floating point operations
independently at the same time)
 ADCs and Temperature Sensor  1 CRC Unit
- 2 12-bit ADCs, 16 input channels are  96-bit UID
supported
 Serial wire debug SWD and JTAG
- ADC voltage conversion range:
interfaces
0~VDDA
 Chip Packaging
- Double-sample and hold capability
- LQFP100/LQFP64/LQFP48/QFN36
supported
- 1 on-chip temperature sensor  Applications
 I/O - Medical devices, PC peripherals,

industrial control, smart meters, household
- 80/51/37/26 I/Os selectable,
appliances
depending on models and packages
- All I/O pins are mappable to 16
external interrupt
 DMA
CONTENTS
1. Features ................................................................................................................................................2
2. Overview ...............................................................................................................................................9
3. Features Description ........................................................................................................................ 10
3.1. ARM® Cortex®-M3 Core ...................................................................................................................... 10

3.2. Memory ................................................................................................................................................ 11
3.3. Power Management............................................................................................................................. 11
3.3.1. Power Supply Schemes ...................................................................................................................... 11
3.3.2. Voltage Regulator ............................................................................................................................... 12
3.3.3. Power Supply monitor......................................................................................................................... 12
3.3.4. Low Power Mode ................................................................................................................................ 12
3.4. Clocks and Startup ............................................................................................................................. 13
3.5. RTC and Backup Registers ................................................................................................................ 13
3.6. Boot Modes ......................................................................................................................................... 14

3.7. CRC (Cyclic Redundancy Check) Calculation Unit ............................................................................ 14
3.8. General Purpose IO Port .................................................................................................................... 14
3.9. General-purpose urpose Input\Output Interface ................................................................................. 14
3.10. Interrupt Controller .............................................................................................................................. 14
3.10.1. Nested Vectored Interrupt Controller (NVIC) ...................................................................................... 14
3.10.2. External Interrupt/Event Controller (EXTI) .......................................................................................... 15
3.11. Floating Point Unit (FPU) .................................................................................................................... 15
3.12. DMA .................................................................................................................................................... 15
3.13. Tmrer .................................................................................................................................................. 16

3.14. Watchdog WDT ............................................................................................................................ 16
3.15. Peripheral Interface ............................................................................................................................ 17
3.15.1. I2C Bus ............................................................................................................................................... 17

3.15.2. Universal Synchronous/Asynchronous Receiver Transmitter (USART) ............................................. 17
3.15.3. Serial Peripheral Interface (SPI) ......................................................................................................... 18
3.15.4. Quad SPI Controller (QSPI) ............................................................................................................... 18

3.15.5. Controller Area Network (CAN) .......................................................................................................... 18
3.15.6. Universe Serial Bus (USB) ................................................................................................................. 18
3.15.7. Simultaneous Use of USB Interface and CAN Interface: ................................................................... 18
3.15.8. ADC (Analog/Digital Converter) .......................................................................................................... 18
3.15.9. Temperature Sensor ........................................................................................................................... 19

3.15.10.Debug Interface (SWJ-DP) ............................................................................................................... 19
4. Pin Features ...................................................................................................................................... 20

4.1. Pinouts and Pin Description ............................................................................................................... 20
4.1.1. APM32F103x4x6x8xB Series LQFP100 ............................................................................................ 20
4.1.2. APM32F103x4x6x8xB Series LQFP64 .............................................................................................. 21

4.1.3. APM32F103x4x6x8xB Series LQFP48 .............................................................................................. 22
4.1.4. APM32F103 x4x6x8xb Series QFN36................................................................................................ 23
4.2. Pin Description .................................................................................................................................... 24
4.3. System Diagram ................................................................................................................................. 31
4.4. Clock Tree........................................................................................................................................... 32
4.5. Address Mapping ................................................................................................................................ 33
4.6. Power Supply Scheme ....................................................................................................................... 34
5. Electrical Features ............................................................................................................................ 35
5.1. Parameter Conditions ......................................................................................................................... 35
5.1.1. Maximum and Minimum Values .......................................................................................................... 35
5.1.2. Typical Value ....................................................................................................................................... 35
5.1.3. Typical Curve ...................................................................................................................................... 35
5.1.4. Load Capacitance ............................................................................................................................... 35
5.2. Absolute Maximum Ratings ................................................................................................................ 36
5.2.1. Maximum Rated Voltage Features ..................................................................................................... 36
5.2.2. Maximum Rated Current Features ..................................................................................................... 37
5.2.3. Maximum Temperature Features ........................................................................................................ 38
5.2.4. Maximum Ratings Electrical Sensitivity .............................................................................................. 38
5.2.5. Test Under the General Working Conditions ...................................................................................... 39
5.2.6. Embedded Reset and Power Control Block Features ........................................................................ 40
5.2.7. Built-in Reference Voltage Features Test ........................................................................................... 40
5.2.8. Supply Current Features .................................................................................................................... 41
5.2.9. External Clock Source Features ......................................................................................................... 49
5.2.10. Internal Clock Source Features .......................................................................................................... 52
5.2.11. PLL Features ...................................................................................................................................... 54
5.2.12. Memory Features ................................................................................................................................ 55
5.2.13. I/O Ports Features .............................................................................................................................. 55
5.2.14. NRST Pins Features ........................................................................................................................... 59
5.2.15. Communication Interface .................................................................................................................... 59

5.2.16. 12-bit ADC Features ........................................................................................................................... 64
5.2.17. Temperature Sensor Features ............................................................................................................ 67

5.2.18. EMC Features..................................................................................................................................... 67
6. Packaging Information ..................................................................................................................... 69
6.1. LQFP100 Package Diagram ............................................................................................................... 69

6.2. LQFP64 Package Diagram ................................................................................................................. 72
6.3. LQFP48 Package Diagram ................................................................................................................. 75
6.4. QFN36 Package Diagram .................................................................................................................. 78
7. Ordering Information ........................................................................................................................ 81
8. Package Information ........................................................................................................................ 84
9. Commonly Used Function Module Denomination ........................................................................ 89
10. Reversion History ............................................................................................................................. 90

TABLE CONTENTS
Table 1. APM32F103x4x6x8xB Product Features and Peripheral Configurations .................................. 10
Table 2. Description of Memory ................................................................................................................ 11
Table 3. Power Supply Schemes .............................................................................................................. 11
Table 4. Operation Modes of Voltage Regulator ...................................................................................... 12

Table 5. Low Power Mode ....................................................................................................................... 12
Table 6. TMRer Feature Comparison ...................................................................................................... 16
Table 7. Watchdog ................................................................................................................................... 17
Table 8. APM32F103x4x6x8xB Pin Definitions ....................................................................................... 24
Table 9. Maximum Rated Voltage Features ............................................................................................ 36
Table 10. Maximum Rated Current Features ............................................................................................ 37
Table 11. Temperature Features ................................................................................................................ 38
Table 12. ESD Absolute Maximum Ratings ............................................................................................... 38
Table 13. Static Latch ................................................................................................................................ 38

Table 14. General Working Conditions ...................................................................................................... 39
Table 15. Embedded Reset and Power Control Block Features (T A=25 ) -40 -105 ................... 40
Table 16. Built-in Reference Voltage ......................................................................................................... 40
Table 17. Run-mode Current Consumption, Code with Data Processing Running From Internal Flash .. 42
Table 18. Run-mode Current Consumption, Code with Data processing Running From Internal RAM ... 43
Table 19. Maximum Current Consumption in Sleep Mode, Code Runs from Flash or RAM .................... 44
Table 20. Maximum Current Consumption in Stop Mode and Standby Mode .......................................... 45
Table 21. Run-mode current consumption, code with data processing running from internal Flash ........ 46
Table 22. Run-mode current consumption, code with data processing running from internal RAM ......... 47
Table 23. Typical current consumption in sleep mode, code running from Flash or RAM ........................ 48
Table 24. Typical current Consumption in Stop Mode and Standby Mode ............................................... 49
Table 25. HSE 4~16MHz Oscillator Features............................................................................................ 49

Table 26. LSE Oscillator Features (fLSE =32.768KHz) .............................................................................. 51
Table 27. HSI Oscillator Features .............................................................................................................. 52
Table 28. LSI Oscillator Features .............................................................................................................. 53

Table 29. Wake Up TMRe in Low Power Mode ......................................................................................... 53
Table 30. PLL Features ............................................................................................................................. 54
Table 31. FLASH Memory Features (1)..................................................................................................... 55
Table 32. FLASH Memory Life and Data Retention Period ....................................................................... 55
Table 33. I/O Static Features (Test conditions VCC=2.7-3.6V, TA = -40~105°C) ........................................ 55
Table 34. Voltage Features (test conditions VCC=2.7-3.6V,TA = -40~105°C)........................................... 56
Table 35. Input and Output AC Features ................................................................................................... 57

Table 36. NRST NRST Pin Features (Test condition VCC=3.3V,TA = -40~105°C .................................. 59
Table 37. I2C Interface Features (Test conditions VDD = 3.3V TA = 25°C ........................................... 59
Table 38. SPI Features (VDD= 3.3V TA =25°C) ....................................................................................... 61

Table 39. USB DC Characteristics ............................................................................................................ 63
Table 40. ADC Features (VDD= 2.4-3.6V T A =-40~105°C) ..................................................................... 64
Table 41. Maximum RAIN at fADC=14MHz 1 ..................................................................................... 66
Table 42. ADC Accuracy ............................................................................................................................ 66
Table 43. Temperature Sensor Features ................................................................................................... 67
Table 44. EMS Features ............................................................................................................................ 68
Table 45. EMI Features ............................................................................................................................. 68
Table 46. LQFP100 Package Data ............................................................................................................ 70
Table 47. LQFP64 Package Data .............................................................................................................. 73
Table 48. LQFP Package Data .................................................................................................................. 76
Table 49. QFN36 Package Data ................................................................................................................ 79
Table 50. Ordering Information Table ........................................................................................................ 82
Table 51. Strip Package Parameters Specification ................................................................................... 85
Table 52. Tray Package Diagram .............................................................................................................. 86
Table 53. Tray Package Parameters Specification .................................................................................... 87
Table 54. Commonly Used Function Module Denomination ..................................................................... 89
Table 55. Document Reversion History ..................................................................................................... 90

Figure CONTENTS
Figure 1. LQFP100 Pinout ......................................................................................................................... 20
Figure 2. LQFP64 Pinout ........................................................................................................................... 21
Figure 3. LQFP48 Pinout ........................................................................................................................... 22
Figure 4. QFN36 Pinout ............................................................................................................................ 23

Figure 5. APM32F103x4x6x8xB Series System Diagram......................................................................... 31
Figure 6. APM32F103x4x6x8xB Series Clock Tree .................................................................................. 32
Figure 7. APM32F103x4x6x8xB Series Address Mapping Diagram ......................................................... 33
Figure 8. Power Supply Scheme ............................................................................................................... 34
Figure 9. Load Conditions When Measuring Pin Parameters ................................................................... 35
Figure 10. Pin Input Voltage Measurement Scheme .................................................................................. 36
Figure 11. Current Consumption Measurement Scheme............................................................................ 36
Figure 12. Input and Output AC Features Definition ................................................................................... 58
Figure 13. Bus AC Waveform and Measurement Circuit ............................................................................ 60

Figure 14. TMRing Diagram - Slave Mode and CPHA=0 ........................................................................... 62
Figure 15. SPI TMRing Diagram - Slave Mode and CPHA=0 .................................................................... 62
Figure 16. SPI TMRing Diagram - Master Mode ......................................................................................... 63
Figure 17. USB TMRing: Definition of Data Signal Rise and Fall TMRes .................................................. 64
Figure 18. Typical application of ADC ......................................................................................................... 65
Figure 19. ADC Accuracy Characteristics .................................................................................................. 67
Figure 20. LQFP100 Package Diagram ...................................................................................................... 69
Figure 21. LQFP100-100 pins,14x14mm welding Layout proposal ............................................................ 71
Figure 22. LQFP100-100 pin,14x14mm package identification diagram .................................................... 71

Figure 23. LQFP64 Package Diagram ........................................................................................................ 72
Figure 24. LQFP64-64 pin,10x10mm welding Layout proposal .................................................................. 74
Figure 25. LQFP64-64 pin,10x10mm package identification diagram ........................................................ 74

Figure 26. LQFP48 Package Diagram ........................................................................................................ 75
Figure 27. LQFP48-48 pin,7x7mm welding Layout proposal ...................................................................... 77
Figure 28. LQFP48-48 pin,7x7mm identification diagram........................................................................... 77

Figure 29. QFN36 Package Diagram .......................................................................................................... 78
Figure 30. QFN36 pin, 6 x 6mm Welding Layout Proposal ......................................................................... 80
Figure 31. QFP36 pin, 6x6mm identification diagram ................................................................................. 80
Figure 32. Strip Package Specification Diagram .........................................................................................84

2. Overview
The APM32F103x4x6x8xB series chips are ARM® Cortex®-M3 core based 32-bit
microcontrollers with a maximum operating frequency of 96MHz. Built-in AHB high-performance
bus, combined with high-speed memory and DMA for fast data processing and storage. The
built-in APB advanced peripheral bus expands the rich peripherals and enhanced I/O, ensuring
fast connection and control flexibility. The chips are equipped with a powerful FPU floating-point
arithmetic processing unit that supports single-precision data processing instructions and data
types.
Built-in up to 128K bytes of flash memory and 20K bytes of SRAM memory, and all models
include 2 12-bit ADCs, 3 general-purpose 16-bit timers, 1 advanced control timer and 1
temperature sensor, as well as standard communication interfaces: 2 I2C interfaces, 2 SPI
interfaces, 1 QSPI interface, 3 USART interfaces, 1 USB 2.0 FS interface and 1 CAN 2.0B
interface(USB and CAN can work independently at the same time).
Operating voltage is 2.0V ~ 3.6V, there are two types of operating temperature range selectable:
-40°C~+85°C and -40°C~+105°C. Available for four different package forms of
LQFP100/LQFP64/LQFP48/QFN36, with different peripherals and I/O configurations.
For information about the Arm® Cortex®-M3 core, please refer to the Arm®Cortex®-M3 technical
reference manual, which can be downloaded from ARM’s website.
3. Features Description
See the following table for specific APM32F030x6/x8 product functions and peripheral
configuration.
Functions and peripherals of APM32F103x4x6x8xB

APM32F103xx
Product
T4 T6 T8 TB C4 C6 C8 CB R4 R6 R8 RB V8 VB
Packaging QFN36 LQFP48 LQFP 64 LQFP 100
Flash(Kbytes) 16 32 64 128 16 32 64 128 16 32 64 128 64 128
SRAM(Kbytes) 6 10 20 6 10 20 6 10 20
General-purpose
2 3 2 3 2 3
(16-bit)
Advanced
Timers
1
(16-bit)
SysTick 1
Watchdog 2
RTC 1
SPI 1 2 1 2
Communication
QSPI 1
Interfaces
I2C 1 2 1 2
USART 2 3 2 3
CAN2.0B 1
USB2.0 FS 1
Unit 2
12 bit
ADC
Channel 10 16
GPIOs 26 37 51 80
CPU@Max. frequency M3@96MHz
FPU 1
Operating voltage 2.0 V~ 3.6 V
3.1. ARM® Cortex®-M3 Core

APM32F103x4x6x8xB series with built-in ARM® Cortex®-M3 core, 96MHz working frequency,
and are compatible with ARM’s tools and softwares.
System diagram of APM32F103x4x6x8xB series products is shown in Figure 5.
3.2. Memory
Memory Description
Memory The biggest byte Function
Embedded High-speed
128 Kbytes For storing programs and data
Flash
Can be accessed in bytes, halfwords(1 6bits)
Embedded Static Memory 20 Kbytes
or full words(32bits)
3.3. Power Management

3.3.1. Power Supply Schemes
Power Supply Schemes
Name Voltage Range Description
VDD directly supplies power to IO port, and VDD

VDD 2.0 3.6V supplies power to core circuit through voltage
regulator.
Connected to VDD, it supplies power to the analog
parts of ADC, reset module, RC oscillator and PLL.
VDDA 2.4 3.6V When ADC is being used, VDDA is greater than or
equal to 2.4V. VDDA and VSSA must be connected to
VDD and VSS respectively.
Automatically supply power to RTC, external
VBAT 1.8V 3.6V 32KHz oscillator and backup registers when VDD is
off.
Note: See Figure 8 for more details on how to connect power supply pins.
3.3.2. Voltage Regulator
There are three main modes of voltage regulator. The working mode of MCU can be adjusted
by voltage regulator to reduce power consumption.
Operation Modes of Voltage Regulator
Name Description
1.6V power supply(core, memory, peripherals) in normal

Main Mode(MR)
regulation mode
1.6V power supply in low power mode to preserve the
Low Power Mode(LPR)
contents of register and SRAM
Used in Standby mode: the regulator output is in high
impedance: the kernel circuitry is powered down, inducing
Power Down Mode
zero consumption (but the contents of the registers and
SRAM are lost)
This regulator is always enabled after reset, and outputs with high impedance in power-down
mode.
3.3.3. Power Supply Monitor

Two circuits of power-on reset (POR) and power-down reset (PDR), are integrated inside the
product. When VDD reaches the set threshold VPOR/PDR, the system works normally. When VDD
is below the specified threshold VPOR/PDR, the system remains in a reset state without the need
for an external reset circuit.
For details of VPOR/PDR, please refer to the electrical feature in chapter 5.
3.3.4. Low Power Mode

The product supports the following three low power consumption modes, which can be
configured by users to meet the best application requirements.
Low Power Consumption Mode
Mode Types Description
In Sleep mode, only the CPU is stopped. All peripherals continue to

Sleep Mode
operate and can wake up the CPU when an interrupt/event occurs.
Mode Types Description
The Stop mode achieves the lowest power consumption while retaining
the content of SRAM and registers. At this point, part of the 1.6V power
supply are stopped, resulting in the HSE, HSI, and PLL clocks are
Stop Mode
disabled. The voltage regulator is either in normal or in low-power
mode. Interrupt, event wakeup configured as EINT can wake up the
CPU from stop mode.
The Standby mode is used to achieve the lowest power consumption.
The internal voltage regulator is switched off so that part of 1.6 V
domain is powered off. The HXT, HIRC, and PLL clocks are also
switched off. The contents of SRAM and registers are lost, but contents
Standby Mode
of the backup registers will still remain, and the standby circuit will still
work. The external reset signal on NRST, IWDT, will reset an ascending
edge on the WKUP pin or the RTC clock will then terminate the chip
standby mode.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by
entering stop or standby mode. QSPI interrupts cannot wake up low power mode.
3.4. Clocks and Startup

The internal 8MHz RC oscillator serves as the default clock for system startup, and can be
switched to the external 4-16mhz clock with failure monitoring through configuration.
When an external clock failure is detected, the system will automatically switch to an internal
RC oscillator, and if an interrupt is set, the software can receive the related interrupt.
The frequencies of AHB high-speed APB(APB2) and low-speed APB(APB1) can be
configured through the predivider. The maximum frequency of AHB and high-speed APB is
96MHz and that of low speed APB is 48MHz.
See Figure 6 for details on the clock tree.
3.5. RTC and Backup Registers

The RTC has a set of continuously running counters, which can provide calendar alarm
interruption and stage interruption functions with softwares. Its clock source can choose
external 32.768khz crystal oscillator, internal 40KHz low-speed RC oscillator or external
high-speed clock with 128 frequency division. Moreover, the RTC clock can be calibrated for
errors through a 512Hz signal.
A backup register for 10 16-bit registers to hold 20 bytes of user data when VDD is off.
RTC and backup registers are powered by VDD when VDD is in effect; otherwise, it will be
powered by VBAT pins. System or power reset source reset, waking up from standby mode,
does not cause the reset of RTC and backup register.
3.6. Boot Modes

At startup, you can choose one of three bootstrap modes through the bootstrap pin:
 Boot from User Flash
 Boot from System Memory
 Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
3.7. CRC (Cyclic Redundancy Check) Calculation Unit

The CRC (Cyclic Redundancy Check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
The CRC calculation unit helps compute a signature of the software during runTMRe, to be
compared with a reference signature generated at link-TMRe and stored at a given memory
location.
3.8. General Purpose IO Port

80/51/37/26 I/O is available for the product, and the specific selection can refer to the model and
package. All I/O can be mapped to 16 external interrupt controllers, and most of I/O support 5V
logic level input.
3.8.1. General-purpose urpose Input\Output Interface

The product can be up to 80 GPIO pins, each of the GPIOs can be configured by software as
output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral
alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All
GPIOs are high current-capable.
The I/Os alternate function configuration can be locked if needed following a specific sequence
in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling
speed.
3.9. Interrupt Controller

3.9.1. Nested Vectored Interrupt Controller (NVIC)
 It can handle 16 priority levels and maskable interrupt channels simultaneously. The closely
coupled NVIC gives low-latency interrupt processing.
 Interrupt entry vector table address passed directly to the core
 Allow early processing of interrupts.
 Processing of late arriving higher priority interrupts
 Support for tail-chaining
 Processor state is automatically saved.
 Interrupt entry restored on interrupt exit with no instruction overhead
 This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2. External Interrupt/Event Controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. Up to 80 GPIOs can be connected to the 16
external interrupt lines. The EXTI can detect an external line with a pulse width shorter than
the Internal APB2 clock period.
3.10. Floating Point Unit (FPU)

The product has a embedded independent FPU floating-point arithmetic processing unit that
supports the IEEE754 standard and supports single-precision floating-point operations.
3.11. DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between source
and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and
advanced-control TMRers TMRx and ADC.
3.12. TMRer
The product includes an advanced-control TMRer (TMR1), three general-purpose TMRers
(TMR2/3/4), an independent watchdog TMRer, a window watchdog TMRer, and a
SysTickTMRer.
The following table compares the features of the advanced-control and general-purpose
TMRers:
TMRer Feature Comparison

Type of
TMRer
TMRer Sys Tick TMRer TMR2 TMR3 TRM4 TMR1
Counter
24-bit 16-bit 16-bit
Resolution
Counter Type Down Up, down, up/down Up, down, up/down
Prescaler
Any integer between 1 and 65536 Any integer between 1 and 65536
Factor
DMA Request
Yes Yes
generation
Capture/Com
pare 4 4
Channels
Complement
No Yes
ary Outputs
Complementary PWM outputs with
programmable inserted dead-TMRes

Synchronization or event chaining function
If configured as a general-purpose 16-bit
provided.
Dedicated for OS TMRer, it has the same features as the
Counters can be frozen in debug mode
Automatic reload function TMRx TMRer.
Can be used to generate PWM outputs
Function Maskable system interrupt If configured as the 16-bit PWM generator,
Each TMRer has independent DMA
Specification generation when the it has full modulation capability
request generation.
counter reaches 0 (0-100%).
It can handle quadrature (incremental)
Programmable clock source In debug mode, the advanced-control
encoder signals and the digital outputs
TMRer counter can be frozen and the
from 1 to 3 hall-effect sensors
PWM outputs disabled.
Synchronization or event chaining provided
3.13. Watchdog WDT

The product includes two watchdogs, providing greater security, TMRe accuracy and flexibility.
The two watchdogs(independent and window watchdog)can be used for detecting and resolving
failures caused by software errors. When the counter reaches a given TMReout value, an
interrupt is triggered (for window watchdogs only) or a system reset is generated.
Watchdog
Counter Counter Prescale
Watchdog functional
Resolution Type Factor
It is clocked from an independent 40 kHz
internal RC oscillator and as it operates
independently from the main clock, it can
Any operate in stop and standby modes.
Independe
integer Reset the device when a problem occurs.
nt 12-bit down
between 1 As a free-running TMRer for application
Watchdog
and 256 TMReout management.
It is hardware- or software-configurable
through the option bytes.
The counter can be frozen in debug mode.
It can be set as free-running.
Reset the device when a problem occurs.
Window
7-bit down - It is clocked from the main clock. It has an
Watchdog
early warning interrupt capability.
The counter can be frozen in debug mode.
3.14. Peripheral Interface

3.14.1. I2C Bus
Two embedded I²C (I2C1, I2C2) bus interfaces can operate in multimaster or slave mode. They
can support standard and fast modes. They support dual slave addressing (7-bit only) and both
7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They
can be served by DMA and they support SM Bus 2.0/PM Bus.
I2C3/4 bus extended the function of I2C 1/2. They can operate in standard, fast and high speed
mode. The fast mode and high speed mode devices are backwards compatible.
3.14.2. Universal Synchronous/Asynchronous Receiver Transmitter (USART)

Three USART communication interfaces are embedded, providing hardware management of
the CTS and RTS signals, and IrDA SIR ENDEC supported. They are ISO 7816 compliant and
have LIN Master/Slave capability. One of the USART interfaces is able to communicate at
speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. All
USART interfaces can be served by the DMA controller.
3.14.3. Serial Peripheral Interface (SPI)

Two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex
and simplex communication modes while the frame is configurable to 8 bits or 16 bits. Both
SPIs can be served by the DMA controller.
3.14.4. Quad SPI Controller (QSPI)

The product has a embedded QSPI dedicated communication interface that can be connected
to external flash via single, dual or quad SPI mode, supporting 8-bit, 16-bit and 32-bit access.
There are 8 bytes of transmit FIFO and 8 bytes of receive FIFO.
3.14.5. Controller Area Network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14
scalable filter banks.
3.14.6. Universe Serial Bus (USB)

The product embeds a USB device peripheral compatible with the USB2.0 full-speed 12 Mbs.
The USB interface implements a full-speed (12 Mbit/s) function interface. It has
software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz
clock is generated from the internal main PLL (the clock source must use a HSE crystal
oscillator).
3.14.7. Simultaneous Use of USB Interface and CAN Interface:

When USB and CAN are used together, you need to:
 Write 0x00000001 at the base address offset 0x100 of the USB.
 The PA11 and PA12 pins are for USB and CAN is used to multiplex other pins.
3.14.8. ADC (Analog/Digital Converter)

Two 12-bit analog-to-digital converters are embedded into APM32F103x8xb performance line
devices and each ADC shares up to 16 external channels, performing conversions in
single-shot or scan modes. In scan mode, automatic conversion is performed on a selected
group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
 Simultaneous sample and hold
 Interleaved sample and hold
 Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is outside
the programmed thresholds.
The events generated by the general-purpose TMRers (TMRx) and the advanced-control TMRer
(TMR1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger
respectively, to allow the application to synchronize A/D conversion and TMRers.
3.14.9. Temperature Sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC12_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
3.14.10. Debug Interface (SWJ-DP)

The product supports serial debug interface (SW-DP) and JTAG (JTAG-DP) debug interface.
The JTAG interface provides a 5-pin standard JTAG interface for the AHB access port. The
SW-DP interface provides a 2-pin (data + clock) interface to the AHB module.
The two pins of the SW-DP interface and the five pins of the JTAG interface are multiplexed.
4. Pin Features
4.1. Pinouts and Pin Description
4.1.1. APM32F103x4x6x8xB Series LQFP100
Figure 1. LQFP100 Pinout
BOOT0
VDD_3
VSS_3
PA15
PA14
PC12
PC11
PC10
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PE1
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD_2
PE3 2 74 VSS_2
PE4 3 73 NC
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13-TAMPER-RTC 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS_5 10 66 PC9
VDD_5 11 65 PC8
OSC_IN 12 64 PC7
OSC_OUT 13 63 PC6
NRST 14 LQFP100 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0-WKUP 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
34
VDD_4
VSS_4
PA3
PA4
PA5
PA7
PA6
PB0
PB1
PB2
PC5
PB10
PB11
VDD_1
PE9
VSS_1
PC4
PE7
PE8
PE10
PE11
PE12
PE13
PE14
PE15
BOOT0
VDD_3
VSS_3
PA15
PA14
PC12
PC11
PC10
PD2
PB9
PB8
PB7
PB5
PB4
PB3
PB6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD_2
PC13-TAMPER-RTC 2 47 VSS_2
PC14-OSC32_IN 3 46 PA13
PD0 OSC_IN 5 44 PA11
PD1 OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0
PC1
8 LQFP64 41 PA8
9 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0-WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_4
PA3
PA4
PA5
PA6
PA7
VDD_4
PB0
PB1
PB2
PC4
PC5
PB10
PB11
VDD_1
VSS_1
BOOT0
VDD_3
VSS_3
PA15
PA14
PB9
PB8
PB7
PB5
PB4
PB3
PB6
48 47 46 45 44 43 42 41 40 39 38 37
VBAT 1 36 VDD_2
PC13-TAMPER-RTC 2 35 VSS_2
PC14-OSC32_IN 3 34 PA13
PD0 OSC_IN 5 32 PA11
PD1 OSC_OUT
NRST
6 LQFP48 31 PA10
7 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0-WKUP 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
VSS_1
PB11
VDD_1
4.1.4. APM32F103 x4x6x8xB Series QFN36
Figure 4. QFN36 Pinout
BOOT0
VSS_3
PA15
PA14
PB3
PB7
PB6
PB5
PB4
36 35 34 33 32 31 30 29 28
VDD_3 1 27 VDD_2
OCS_IN/PD0 2 26 VSS_2
OCS_OUT/PD1 3 25 PA13
NRST 4 24 PA12
VSSA 5 QFN36 23 PA11
VDDA 6 22 PA10
PA0-WKUP 7 21 PA9
PA1 8 20 PA8
PA2 9 19 VDD_1
10 11 12 13 14 15 16 17 18
VSS_1
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
4.2. Pin Description
APM32F103x4x6x8xB Pin Definitions

Main
Pins Alternate functions
I/O level (2)

Function (3)
Type
LQFP100
Pin Name
LQFP48
LQFP64
QFN36
(1)
(after reset) Default Remap
PE2 - - 1 - I/O FT PE2 TRACECK -
PE3 - - 2 - I/O FT PE3 TRACED0 -
VBAT 1 1 6 - S - VBAT - -
PC13-
2 2 7 - I/O - PC13(5) TAMPER-RTC -
TAMPER-RTC(4)
PC14-
3 3 8 - I/O - PC14(5) OSC32_IN -
OSC32_IN(4)
PC15-
4 4 9 - I/O - PC15(5) OSC32_OUT -
OSC32_OUT(4)
VSS_5 - - 10 - S - VSS_5 - -
VDD_5 - - 11 - S - VDD_5 - -
OSC_IN 5 5 12 2 I - OSC_IN - PD0(7)
OSC_OUT 6 6 13 3 O - OSC_OUT - PD1(7)
NRST 7 7 14 4 I/O - NRST - -
PC0 - 8 15 - I/O - PC0 ADC12_IN10 -
PC1 - 9 16 - I/O - PC1 ADC12_IN11 -
PC2 - 10 17 - I/O - PC2 ADC12_IN12 -
PC3 - 11 18 - I/O - PC3 ADC12_IN13 -
VSSA 8 12 19 5 S - VSSA - -
VREF- - - 20 - S - VREF- - -
VREF+ - - 21 - S - VREF+ - -
VDDA 9 13 22 6 S - VDDA - -
Main
I/O level (2)

Function (3)
Type
LQFP100
Pin Name
LQFP48
LQFP64
QFN36
(1)
WKUP/
USART2_CTS(6) /
PA0-WKUP 10 14 23 7 I/O - PA0 -
ADC12_IN0/
TMR2_CH1_ETR(6)
USART2_RTS(6)/
PA1 11 15 24 8 I/O - PA1 ADC12_IN1/ -
TMR2_CH2(6)
USART2_TX(6)/
PA2 12 16 25 9 I/O - PA2 ADC12_IN2/ -
TMR2_CH3(6)
USART2_RX(6)/
PA3 13 17 26 10 I/O - PA3 ADC12_IN3/ -
TMR2_CH4(6)
VSS_4 - 18 27 - S - VSS_4 - -
VDD_4 - 19 28 - S - VDD_4 - -
SPI1_NSS(6)/
PA4 14 20 29 11 I/O - PA4 USART2_CK(6) / -
ADC12_IN4
SPI1_SCK(6)/
PA5 15 21 30 12 I/O - PA5 -
ADC12_IN5
SPI1_MISO(6)/
PA6 16 22 31 13 I/O PA6 ADC12_IN6/ TMR1_BKIN
TMR3_CH1(6)
SPI1_MOSI(6)/
TMR1_CH1
PA7 17 23 32 14 I/O PA7 ADC12_IN7/
N
TMR3_CH2(6)
PC4 - 24 33 - I/O - PC4 ADC12_IN14 -
PC5 - 25 34 - I/O - PC5 ADC12_IN15 -

ADC12_IN8/ TMR1_CH2
PB0 18 26 35 15 I/O - PB0
TMR3_CH3(6) N
ADC12_IN9/ TMR1_CH3
PB1 19 27 36 16 I/O - PB1
TMR3_CH4(6) N
Main
I/O level (2)

Function (3)
Type
LQFP100
Pin Name
LQFP48
LQFP64
QFN36
(1)
PB2 20 28 37 17 I/O FT PB2/BOOT1 - -
PE7 - - 38 - I/O FT PE7 - TMR1_ETR

TMR1_CH1
PE8 - - 39 - I/O FT PE8 -
N
PE9 - - 40 - I/O FT PE9 - TMR1_CH1
TMR1_CH2
PE10 - - 41 - I/O FT PE10 -
N
PE11 - - 42 - I/O FT PE11 - TMR1_CH2
TMR1_CH3
PE12 - - 43 - I/O FT PE12 -
N
PE13 - - 44 - I/O FT PE13 - TMR1_CH3
PE14 - - 45 - I/O FT PE14 - TMR1_CH4
PE15 - - 46 - I/O FT PE15 - TMR1_BKIN

I2C2_SCL/
PB10 21 29 47 - I/O FT PB10 I2C4_SCL/ TMR2_CH3
USART3_TX(6)
I2C2_SDA/
PB11 22 30 48 - I/O FT PB11 I2C4_SDA/ TMR2_CH4
USART3_RX(6)
VSS_1 23 31 49 18 S - VSS_1 - -
VDD_1 24 32 50 19 S - VDD_1 - -
SPI2_NSS/
I2C2_SMBAI/
PB12 25 33 51 - I/O FT PB12
USART3_CK(6)/
TMR1_BKIN(6)
SPI2_SCK/
USART3_CTS(6)/
PB13 26 34 52 - I/O FT PB13
TMR1_CH1N(6)/
QSPI_IO0
PB14 27 35 53 - I/O FT PB14 SPI2_MISO/
Main
I/O level (2)

Function (3)
Type
LQFP100
Pin Name
LQFP48
LQFP64
QFN36
(1)
USART3_RTS(6) /
TMR1_CH2N(6)/
QSPI_IO1
SPI2_MOSI/
PB15 28 36 54 - I/O FT PB15 TMR1_CH3N(6)/ -
QSPI_IO2
PD8 - - 55 - I/O FT PD8 QSPI_IO3 USART3_TX
USART3_R
PD9 - - 56 - I/O FT PD9 -
X
USART3_C
PD10 - - 57 - I/O FT PD10 QSPI_CMU
K
USART3_CT
PD11 - - 58 - I/O FT PD11 -
S
TMR4_CH1/
PD12 - - 59 - I/O FT PD12 QSPI_SS_N USART3_RT
S
PD13 - - 60 - I/O FT PD13 - TMR4_CH2
PD14 - - 61 - I/O FT PD14 - TMR4_CH3
PD15 - - 62 - I/O FT PD15 - TMR4_CH4
PC6 - 37 63 - I/O FT PC6 - TMR3_CH1
PC7 - 38 64 - I/O FT PC7 - TMR3_CH2
PC8 - 39 65 - I/O FT PC8 - TMR3_CH3
PC9 - 40 66 - I/O FT PC9 - TMR3_CH4

USART1_CK/
TMR1_CH1(6)/
PA8 29 41 67 20 I/O FT PA8 -
MCO
USART1_TX(6) /
PA9 30 42 68 21 I/O FT PA9 -
TMR1_CH2(6)
PA10 31 43 69 22 I/O FT PA10 USART1_RX(6)/ -
Main
I/O level (2)

Function (3)
Type
LQFP100
Pin Name
LQFP48
LQFP64
QFN36
(1)
TMR1_CH3(6)
USART1_CTS/USBDM/
PA11 32 44 70 23 I/O FT PA11 USB2DM/ CAN_RX(6)/ -
TMR1_CH4(6)
USART1_RTS/
USBDP/USB2DP/
PA12 33 45 71 24 I/O FT PA12 -
CAN_TX(6)/TMR1_ETR(6
)
JTMS/
PA13 34 46 72 25 I/O FT - PA13
SWDIO
Disconnected - - 73 - - - - Disconnected -
VSS_2 35 47 74 26 S VSS_2 - -
VDD_2 36 48 75 27 S VDD_2 - -
JTCK/
PA14 37 49 76 28 I/O FT - PA14
SWCLK
TMR2_CH1
PA15 38 50 77 29 I/O FT JTDI - _ETR/PA15/
SPI1_NSS
PC10 - 51 78 - I/O FT PC10 - USART3_TX
USART3_R
PC11 - 52 79 - I/O FT PC11 -
X
USART3_C
PC12 - 53 80 - I/O FT PC12 -
K
PD0 - - 81 2 I/O FT PD0 - CAN_RX
PD1 - - 82 3 I/O FT PD1 - CAN_TX
PD2 - 54 83 - I/O FT PD2 TMR3_ETR -

USART2_CT
PD3 - - 84 - I/O FT PD3 -
S
PD4 - - 85 - I/O FT PD4 - USART2_RT
Main
I/O level (2)

Function (3)
Type
LQFP100
Pin Name
LQFP48
LQFP64
QFN36
(1)
PD5 - - 86 - I/O FT PD5 - USART2_TX

USART2_R
PD6 - - 87 - I/O FT PD6 -
X
USART2_C
PD7 - - 88 - I/O FT PD7 -
K
PB3/
TRACESWO
PB3 39 55 89 30 I/O FT JTDO -
TMR2_CH2/
SPI1_SCK
PB4/
PB4 40 56 90 31 I/O FT NJTRST - TMR3_CH1/
SPI1_MISO
TMR3_CH2/
PB5 41 57 91 32 I/O - PB5 I2C1_SMBAI
SPI1_MOSI
I2C1_SCL(6) /I2C3_SCL/
PB6 42 58 92 33 I/O FT PB6 USART1_TX
TMR4_CH1(6)
I2C1_SDA(6) /I2C3_SDA/ USART1_R
PB7 43 59 93 34 I/O FT PB7
TMR4_CH2(6) X
BOOT0 44 60 94 35 I - BOOT0 - -
I2C1_SCL/
PB8 45 61 95 - I/O FT PB8 TMR4_CH3(6) I2C3_SCL/
CAN_RX
I2C1_SDA
PB9 46 62 96 - I/O FT PB9 TMR4_CH4(6) I2C3_SDA
/ CAN_TX
PE0 - - 97 - I/O FT PE0 TMR4_ETR -
PE1 - - 98 - I/O FT PE1 - -
VSS_3 47 63 99 36 S - VSS_3 - -
VDD_3 48 64 100 1 S - VDD_3 - -
(1) I = input, O = output, S = supply, HiZ = high resistance

(2) FT = 5V tolerant.
(3) Function availability depends on the chosen device. For devices having reduced peripheral
counts, it is always the lower number of peripheral that is included. For example, if a device
has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2,
respectively.
(4) PC13, PC14 and PC15 are supplied through the power switch since the switch only sinks a
limited amount of current (3mA). The use of GPIOs from PC13 to PC15 in output mode is
limited: only one GPIO can be used at a TMRe, the speed should not exceed 2 MHz with a
maximum load of 30pF and these IOs must not be used as a current source (e.g. to drive an
LED).
(5) Main function after the first backup domain power-up. Later on, it depends on the contents
of the Backup registers even after reset (because these registers are not reset by the main
reset). For details on how to manage these IOs, refer to the Battery backup domain and
BAKR register description sections in the reference manual.
(6) This alternate function can be remapped by software to some other port pins (if available on
the used package). For more details, refer to the alternate function I/O and debug
configuration section in the reference manual.
4.3. System Diagram
Figure 5. APM32F103x4x6x8xB Series System Diagram
ARM® Cortex®-M3
Systen Bus
D-Code
I-Code
FMC
BUS MATRIX JTAG/SWD
FLASH
DMA AHB BUS SRAM
FPU CRC QSPI

AHB/APB1 BRIDGE AHB/APB2 BRIDGE
TMR2/3/4 AFIO
RTC EINT
WWDT GPIO A/B/C/D/E
IWDT ADC1/2
SPI2 TMR1
USART2/3 SPI1
I2C1/I2C3 USART1
I2C2/I2C4
CAN
BAKR
PMU
USBD/USBD2
(1) The max frequency for APM32F103x8xBx4x6 series AHB and high-speed APB is 96MHz;
(2) The max frequency for APM32F103x8xBx4x6 series low-speed APB clock is 48MHz.
4.4. Clock Tree
Figure 6. APM32F103x4x6x8xB Series Clock Tree
FLITFCLK
to flash programming interface
USB 48 MHz USBCLK

Prescaler to USB interface
8 MHz
HSI RC 1/1.5/2
HSI
FPU
Prescaler
1/2
/2
QSPI
96 MHz max HCLK

PLLSRC PLLMUL SW to AHB bus , core,
Clock memory and DMA
. . .,×16 HSI SYSCLK AHB
×2,×3,×4 Prescaler /8 to Cortex System timer
PLLCLK 96MHz Enable(3bits)
PLL /1,2. .512
HSE max
FCLK Cortex
Free running clock
CSS
APB1 48 MHz max
Prescaler PCLK1
PLLXTPRE /1,2,4,8,16 to APB1
OSC_ OUT Peripheral Clock peripherals
4-16MHz Enable(13bits)
OSC_IN HSE OSC
/2
TMR2,3,4 to TMR2,3
If( APB1 prescaler=1) ×1 and 4
else × 2 TMRXCLK
OSC32_OUT /128 To RTC Peripheral Clock
LSE OSC
Enable (3bits)
32.768KHz LSE RTCCLK
OSC32_IN APB2 96 MHz max
PCLK2
Prescaler
RTCSEL[1:0] /1,2,4,8,16 to APB2
LSI RC LSI to independent watchdog( IWDG) Peripheral Clock peripherals
40KHz Enable(11bits)
IWDGCLK
Main TMR1 timer

If( APB2 prescaler=1) ×1 to TMR1
Clock Output /2 PLLCLK
MCO HSI else × 2 TMR1CLK
HSE Peripheral Clock
SYSCLK Enable(1bits)
ADC
MCO to ADC
Prescaler
/2,4,6,8 ADCCLK
Legend :
HSE= high-speed external clock signal
HSI = high- speed internal clock signal
LSE = low - speed external clock signal
LSI = low - speed internal clock signal
(1) The max frequency for APM32F103x8xBx4x6 series AHB and high-speed APB is 96MHz;
(2) The max frequency for APM32F103x8xBx4x6 series low-speed APB clock is 48MHz.
4.5. Address Mapping
Figure 7. APM32F103x4x6x8xB Series Address Mapping Diagram
APB memory space

0xFFFF FFFF
reserved
0xA000 1FFF
QSPI
0xA000 0000
0xFFFF FFFF reserved
0x4002 4400
FPU
0x4002 4000
7 reserved
0x4002 3400
CRC
0xE010 0000 0x4002 3000
reserved
ARM® Cortex®-M3 0x4002 2400
Flash Interface
0xE000 0000 Internal 0x4002 2000
Peripherals reserved
0x4002 1400
RCM
6 0x4002 1000
reserved
0x4002 0400
0xC000 0000 DMA
0x4002 0000
reserved
0x4001 3C00
USART1
5 0x4001 3800
reserved
0x4001 3400
SPI1
Peripherals 0x4001 3000
TMR1
0xA000 0000 0x4001 2C00
ADC2
0x1FFF FFFF 0x4001 2800
reserved ADC1
4 0x1FFF F80F 0x4001 2400
reserved
Option Bytes 0x4001 1C00
0x8000 0000 Port E
0x1FFF F800 0x4001 1800
Port D
System memory 0x4001 1400
3 Port C
0x4001 1000
0x1FFF F000 Port B
0x4001 0C00
0x6000 0000 Port A
0x4001 0800
EINT
0x4001 0400
2 AFIO
0x4001 0000
reserved
0x4000 7400
reserved PMU
0x4000 0000 Peripherals 0x4000 7000
BAKP
0x4000 6C00
reserved
1 0x4000 6800
CAN
0x4000 6400 Shared 512 byte
SRAM 0x4000 6000 USB/CAN SRAM

0x0801 FFFF USB/USB2 Registers
0x2000 0000 0x4000 5C00
0x4000 5800 I2C2/I2C4
0 Flash memory I2C1/I2C3
0x4000 5400
0x0800 0000 Aliased to Flash or 0x4000 4C00 reserved
0x0000 0000 USART3
system memory 0x4000 4800
depending on BOOT USART2
0x4000 4400
0x0000 0000
pins
0x4000 3C00 reserved
SPI2
0x4000 3800
0x4000 3400 reserved
IWDT
0x4000 3000
WWDT
0x4000 2C00
Reserved RTC
0x4000 2800
reserved
0x4000 0C00
TMR4
0x4000 0800
0x4000 0400 TMR3
0x4000 0000 TMR2
4.6. Power Supply Scheme
Figure 8. Power Supply Scheme

5. Electrical Features
5.1. Parameter Conditions
All voltage parameters are referenced to VSS unless otherwise specified
5.1.1. Maximum and Minimum Values

Unless otherwise stated, all minimum and maximum values are guaranteed on the production
line by testing 100% of the product at ambient temperature TA=25°C under worst ambient
temperature, supply voltage and clock frequency conditions.
Take notes in every table that the data got for passing the comphensive evaluation, design
simulation or process features will not be tested on production lines. Basing on the
comprehensive evaluation and sample tested, the minimum and maximum values come from
the average value's plus or subtract its triple value on the standard distribution (average ±3∑).
5.1.2. Typical Value

Typical data is based on TA =25°C and VDD =3.3V (2 V ≤ VDD ≤ 3.3 V voltage range) unless
otherwise stated. These data are for design guidance only.
5.1.3. Typical Curve

Typical curves are for design guidance only and are not tested unless otherwise stated.
5.1.4. Load Capacitance
Figure 9. Load Conditions When Measuring Pin Parameters
APM32F103XXPIN
C=50 PF
A: load capacitance
Figure 10. Pin Input Voltage Measurement Scheme
APM32F103XXPIN
VIN
B: Pin Input Voltage
Figure 11. Current Consumption Measurement Scheme

IDD_VBAT
VBAT
AFM32F103XXPIN
IDD
VDD
Vref
VDDA
C: Current consumption measurement(IDD+Vref)
5.2. Absolute Maximum Ratings

Loads applied to the device may cause permanent damage to the device if the absolute
maximum ratings are given in the maximum rated voltage Features and maximum rated current
Features. This is just to give the maximum load that can be tolerated, and does not mean that
the functionality of the device is functioning properly under these conditions. The reliability of
device would be affected if it works under the maximum load conditions for a long TMRe.
5.2.1. Maximum Rated Voltage Features
Maximum Rated Voltage Features
Symbol Description Minimum Maximum Unit

External main supply voltage (including VDDA and
VDD - VSS -0.3 4.0
VDD) (1)
V
Input voltage on 5V tolerant pins (2) VSS-0.3 5.5
VIN
Input voltage on other pins(2) VSS-0.3 VDD + 0.3
| ΔVDDx | Voltage difference between different supply pins 50 mV

Symbol Description Minimum Maximum Unit
| VSSx-VSS | Voltage difference between different ground pins 50
(1) All power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to a power
supply within the external allowable range.
(2) If VIN does not exceed the maximum value, IINJ(PIN) will not exceed its limit. If VIN exceeds the
maximum value, IINJ(PIN) must be externally limited to not exceed its maximum value. When
VIN > VDD, there is a forward injection current; when VIN<VSS, there is a reverse injection
current.
5.2.2. Maximum Rated Current Features
Maximum Rated Current Features

Symbol Description Maximum Unit
Total current (supply current) (1) went through the VDD/VDDA power 150
IVDD
cord.
IVSS Total current (outflow current) (1) went through the VSS ground cord. 150
mA
Irrigation current on any I/O and control pins 25
IIO
Source current on any I/O and control pins -25
Injection current of NRST pin ±5
IINJ(PIN) (2) (3) Injection current of HSE's OSC_IN pin and LSE's OSC_IN pin ±5
Injection current of other pins ±5
ΣIINJ(PIN)(2) Total injection current on all I/O and control pins (4) ±25
(1) All power (VDD VDDA) and ground (VSS VSSA) pins must always be connected to a power
supply within the external allowable range.
(2) If VIN does not exceed the maximum value, IINJ(PIN) will not exceed its limit. If VIN exceeds
the maximum value, IINJ(PIN) must be externally limited to not exceed its maximum value.
When VIN > VDD, there is a forward injection current; when VIN < VSS, there is a reverse
injection current.
(3) Reverse injection current can interfere with the analog performance of the ADC.
(4) When several I/O ports have injection current at the same TMRe, the maximum value
ofΣIINJ(PIN) is the sum of the instantaneous absolute values of the forward injection current
and the reverse injection current. These results are based on the calculation of the
maximum value of ΣIINJ(PIN) on the four I/O port pins of the device.
5.2.3. Maximum Temperature Features
Temperature Features
Symbol Description Value Unit
TSTG Storage temperature range -55 ~ + 150 °C
TJ Maximum junction temperature 150 °C
5.2.4. Maximum Ratings Electrical Sensitivity

Electrostatic Discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to
the pins of each sample according to each pin combination. The sample size is 3parts x(n+1)
supply pins. The test is compliant with JS-001-2017/JS-002-2018 standard.
ESD Absolute Maximum Ratings 1
Maximum
Symbol Ratings Conditions Unit
value (1)
Electrostatic discharge TA = +25 °C, compliant with
VESD(HBM) 2000
voltage (human body model) standard JS-001-2017
Electrostatic discharge V
TA = +25 °C, compliant with
VESD(CDM) voltage (charging device 1000
standard JS-002-2018
model)
(1) The sample is measured by a third-party testing agency and is not tested in production
Static Latch-up(LU)
When running a simple application (controlling 2 LED flashes through I/O ports), the test sample
is subjected to false electromagnetic interference until an error occurs, and the flashing LED
indicating the error is for evaluating the latch performance. Two complementary static tests are
required on six parts to assess the latch-up performance:
 A supply overvoltage is applied to each power supply pin
 A current injection is applied to each input, output and configurable I/O pin The test is
compliant with EIA/JESD78E latch-up standard.
Static Latch 1
Symbol Parameters Conditions Type

TA = +25 °C/105°C,compliant
LU Static latch ±200mA
with standard EIA/JESD78E
(1) The sample is measured by a third-party testing agency and is not tested in production.
5.3. Test Under the General Working Conditions
General Working Conditions

Symbol Parameters Conditions Min value Max value Unit
fHCLK Internal AHB clock frequency 0 96
fPCLK1 Internal APB1 clock frequency 0 48
MHz
fPCLK2 Internal APB2 clock frequency 0 96
VDD Standard working voltage 2 3.6 V
Analog operating voltage
2 3.6
(ADC not used) must be the
VDDA(1) V
Analog operating voltage same with VDD(2)
2.4 3.6
(ADC not used)
VBAT Backup operating voltage 1.6 3.6 V
Ambient temperature range Maximum power
-40 105 °C
(temperature label 6) consumption
TA
Ambient temperature range Maximum power
-40 105 °C
(temperature label 7) consumption
TJ Junction temperature range -40 150 °C
(1) When the ADC is used, refer to Chapter 5.2.16.
(2) It is recommended to power VDD and VDDA from the same source. A maximum difference of
300mV between VDD and VDDA can be tolerated during power-up and operation.
5.3.1. Embedded Reset and Power Control Block Features
Embedded Reset and Power Control Block Features (T A=25℃) -40℃~+105℃

Minimum Typical Maximum
Symbol Parameters Conditions Unit
Value Value Value
PLS[2:0]=000 (rising edge) 2.18 2.2 2.22 V
PLS[2:0]=000 (falling edge) 2.08 2.09 2.11 V
PLS[2:0]=001 (rising edge) 2.28 2.3 2.32 V
PLS[2:0]=010 (rising edge) 2.38 2.4 2.42 V
Programmable PLS[2:0]=011 (rising edge) 2.48 2.5 2.52 V
VPVD(3) voltage detector PLS[2:0]=011 (falling edge) 2.37 2.39 2.41 V
level selection PLS[2:0]=100 (rising edge) 2.58 2.6 2.62 V
PLS[2:0]=101 (rising edge) 2.67 2.69 2.72 V
PLS[2:0]=110 (rising edge) 2.77 2.8 2.82 V
PLS[2:0]=111 (rising edge) 2.86 2.89 2.91 V
VPVDhyst(2) PVD hysteresis 107 mV
Power on/power Falling edge 1.87(1) 1.89 1.91 V
VPOR/PDR
down reset threhold Rising edge 1.92 1.94 1.96 V
(2)
VPDRhyst PVD hysteresis 50 mV
TRSTTEMPO Reset Duration 0.9 2.4 ms
(1) The product feature is guaranteed from design down to the minimum VPOR/PDR value.
(2) It is guaranteed from design, and is not tested in production.
(3) It is derived from a comprehensive evaluation and is not tested in production.
5.3.2. Built-in Reference Voltage Features Test
Built-in Reference Voltage

Minimum Typical Maximu
Value Value m Value
-40°C < TA <
Internal reference
VREFINT(1) +105°C 1.198 1.210 1.223 V
voltage
VDD= 2-3.6 V
TS_vrefint(2) ADC sampling TMRe 5.1 17.1 μs
Value Value m Value
when reading the
internal reference
voltage
Variation of the built-in
VREFINT reference voltage in full VDD=3V±10mV 20 mV
temperature range
TCoeff 126 ppm/℃
(1) Data was derived from a comprehensive evaluation and is not tested in production.
5.3.3. Supply Current Features

The current values in the operating modes given in this section are measured by executing
Dhrystone 2.1, the compilation environment is Keil V5, and the compilation optimization level is
L3.
Max Current Consumption
The microcontroller is under the following conditions:
 All I/O pins are in input mode and are connected to a static level –VDD or VSS (no load).
 All peripherals are turned off unless otherwise stated.
 The access time of the flash memory is adjusted to the frequency fHCMU (0~24MHz - 0 wait
cycles, 24~48MHz - 1 wait cycle, 48~72MHz - 2 wait cycles, 72~96MHz - 3 wait cycles).
 The instruction prefetch function is turned on (hint: this setting must be made before the
clock setting and bus division).
 When the peripheral is turned on: fpCMU1 = fHCMU/2 fpCMU2 = fHCMU.
Run-mode Current Consumption, Code with Data Processing Running From Internal Flash
Maximum Value(1)
Symbol Parameters Conditions fHCLK Unit
TA =105°C , VDD=3.6 V
96 MHz 31.05
72MHz 25.78
External clock 48MHz 19.82

(2), enabling all 36MHz 15.19
peripherals 24MHz 11.47
16MHz 8.01
Supply current
8MHz 4.41
IDD in operating mA
96 MHz 20.03
mode
72MHz 17.60

(2), turn off all 36MHz 10.89
16MHz 6.30
8MHz 3.54
(2) When the external clock is 8MHz and fHCMU >8MHz, it enables PLL.
Run-mode Current Consumption, Code with Data processing Running From Internal RAM
Maximum Value(1)
Symbol Parameters Conditions fHCLK Unit
TA =105°C , VDD=3.6 V
96 MHz 27.82
72MHz 21.82
External clock(2), 48MHz 14.39
enabling all 36MHz 11.02

16MHz 5.45
Supply current
8MHz 3.20
IDD in operating mA
96 MHz 16.85
mode
72MHz 12.74

(2),
turn off all 36MHz 6.87
peripherals
24MHz 4.92
16MHz 3.66
8MHz 3.19
Maximum Current Consumption in Sleep Mode, Code Runs from Flash or RAM
Maximum Value(1)
Symbol Parameters Conditions fHCLK TA =105°C , VDD=3.6 Unit
V
96 MHz 17.39
72MHz 13.32
External clock (2), 48MHz 9.14
enabling all 36MHz 7.11

16MHz 3.69
Static Current
8MHz 2.31
IDD during Sleep mA
96 MHz 5.07
Mode
72MHz 4.06
External clock (2), 48MHz 3.02
turn off all 36MHz 2.46

16MHz 1.62
8MHz 1.31
Maximum Current Consumption in Stop Mode and Standby Mode
Maximum Value(1)
TA=105°C VDD=3.6 V
Regulator in run mode,
low-speed and high-speed
internal RC oscillators and 94.19
high-speed oscillator OFF(no
Supply
independent watchdog)
current in
Regulator in low-power mode,
stop mode
internal RC oscillators and 79.18
IDD independent watchdog)
Low-speed internal RC oscillator
17 μA
and independent watchdog ON
Supply
is on, independent watchdog 16.82
current in
OFF
standby
mode
and independent watchdog OFF,
15.89
low-speed oscillator and RTC
OFF
Supply
Low-speed oscillator and RTC
IDD_VBAT current in the 3.0
ON
backup area
Typical Current Consumption
The microcontroller is under the following conditions:
 All I/O pins are in input mode and are connected to a static level –VDD or VSS (no load).
 All peripherals are turned off unless otherwise stated.
 The access time of flash is adjusted to the frequency fHCMU (0~24MHz-0 wait cycles,
24~48MHz-1 wait cycle, 48~72MHz-2 wait cycles,96MHz-3 wait cycles).
 The instruction prefetch function is turned on (hint: this setting must be made before the
clock setting and bus division).
When the peripheral is turned on: fpCMU1 = fHCMU/2 fpCMU2 = fHCMU.
Run-mode current consumption, code with data processing running from internal Flash
Typical Value(1)
TA=25°C,VDD=3.3V
Symbol Parameter fHCMU Unit
External clock(2), External clock (2),
enables all turn off all
peripherals peripherals
96 MHz 30.94 19.37
72MHz 25.47 17.22
Supply current 48MHz 19.35 14.08
IDD in operation 36MHz 14.95 10.67 mA

mode
24MHz 11.17 8.32
16MHz 7.72 6.01
8MHz 4.25 3.28
(1) Data was derived from comprehensive evaluation and is not tested in production.
Run-mode current consumption, code with data processing running from internal RAM
Typical Value(1)
TA=25°C,VDD=3.3V
Symbol Parameter fHCMU External Unit

External clock (2),
clock(2),
turn off all
enables all
peripherals
peripherals
96 MHz 27.53 16.42
72MHz 20.78 12.51
Supply current 48MHz 14.43 8.74
IDD in operation 36MHz 11.02 6.61 mA

mode 24MHz 7.65 4.68
16MHz 5.36 3.37
8MHz 3.08 3.10
Typical current consumption in sleep mode, code running from Flash or RAM
Typical Value(1)
TA=25°C,VDD=3.3V
Symbol Parameter fHCMU External Unit

External clock (2),
clock(2),
turn off all
enables all
peripherals
peripherals
96 MHz 17.18 5.16
72MHz 13.03 3.92
48MHz 9.11 2.88

Supply current
IDD 36MHz 7.06 2.36 mA
in sleep mode
24MHz 5.01 1.85
16MHz 3.67 1.52
8MHz 2.25 1.19
Typical current Consumption in Stop Mode and Standby Mode
Typical Value TA =25°C

Symbol Parameters Conditions VDD VDD VDD Unit
=2.4 V =3.3 V =3.6 V
Regulator in run mode, low-speed
and high-speed internal RC
oscillators and high-speed 22.68 24.02 24.22
oscillator OFF(no independent
Supply current watchdog)
in stop mode Regulator in low-power mode,
internal RC oscillators and 10.91 11.88 11.93
IDD
independent watchdog)
Low-speed internal RC oscillator μA
3.61 5.0 5.49
and independent watchdog ON
Supply current 3.51 4.86 5.32
is on, independent watchdog OFF
in standby
mode
and independent watchdog OFF,
2.91 3.95 4.30
low-speed oscillator and RTC
OFF
Supply current
Low-speed oscillator and RTC
IDD_VBAT in the backup 1.1 1.4 1.4
ON
area
(1) Data was derived from a comprehensive evaluation and is not tested in production
5.3.4. External Clock Source Features

High-speed External Clock Generated From Crystal/Ceramic Resonator
The high-speed external(HSE) clock can be supplied with a 4 to 6MHz crystal\ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 25. In the application, the
resonator and the load capacitors have to be placed as closed as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. For detailed
parameters (frequency, package, accuracy, etc.) of the crystal resonator, please consult the
corresponding manufacturer.
HSE 4~16MHz Oscillator Features(1)(2)

Value Value Value
fOSC_IN Oscillator Frequency: 4 8 16 MHz
RF Feedback Resistance 300 kΩ

Recommended load
capacitance and
CL1&
corresponding crystal RS = 30kΩ 30 pF
CL2(3)
serial impedance (RS)
(4)
VDD=3.3V
i2 HSE drive current VIN=VSS 1.1 mA
30pF load
tSU(HSE)(5) Startup TMRe VDD is stable 1.33 ms
(1) The features parameters of the resonator are given by the crystal/ceramic resonator
manufacturer.
(2) It is derived from a comprehensive evaluation and is not tested in production.
(3) For CL1 and CL2, it is recommended to use high quality ceramic capacitors (typically)
between 5pF and 25pF for high frequency applications. Select the capacitor value to meet
the requirements of the crystal or resonator. Usually CL1 and CL2 have the same parameters.
Crystal manufacturers typically give the parameters of the load capacitance in a serial
combination of CL1 and CL2. When selecting CL1 and CL2, the capacitive reactance of the
PCB and MCU pins should be taken into account (the pin and PCB capacitance can be
roughly esTMRated at 10pF).
(4) Relatively low RF resistance provides protection against problems caused by changes in
leakage and bias conditions when used in wet conditions. However, if the MCU is used in a
harsh wet environment, this factor needs to be taken into account when designing.
(5) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a
stabilized 8 MHz oscillation is reached. This value is measured using a standard crystal
resonator, which may vary greatly depending on the crystal manufacturer.
Figure 12. Typical application of 8MHz crystal oscillator
Low-speed External Clock Generated From the Crystal/Ceramic Resonator

The low-speed external(LSE) clock can be supplied with a 32.768kHz crystal\ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in table 26.In the application, the
resonator and load capacitors have to be placed as close as possible to the oscillator pins in
order to minimize output distortion and startup stabilization time. For detailed parameters
(frequency, package, accuracy, etc.) of the crystal resonator, please consult the
corresponding manufacturer.
LSE Oscillator Features (fLSE =32.768KHz) (1)

Value Value Value
fOSC_IN Oscillator frequency 32.768 KHz
RF Feedback Resistance 7 MΩ
Recommended load
capacitance and
CL1 & CL2(2) corresponding crystal RS = 30kΩ 15 pF
serial impedance (RS)
(3)
VDD = 3.3V,
i2 LSE drive current 1.4 μA
VIN=VSS
tSU(LSE)(4) Start TMRe VDD is stable 2.75 s
(2) See the tips and warnings section below this table.
(3) Use a high quality oscillator with a small RS value (such as MSIV-TIN32.768kHz) to optimize
current consumption. Please consult the crystal manufacturer for details.
(4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a
stabilized 8 MHz oscillation is reached. This value is measured using a standard crystal
resonator, which may vary greatly depending on the crystal manufacturer
Tip: For CL1 and CL2, it is recommended to use a high quality ceramic capacitor between 5pF
and 15pF and select the capacitance value to meet the requirements of the crystal or resonator.
Usually CL1 and CL2 have the same parameters. Crystal manufacturers typically give the
parameters of the load capacitance in a serial combination of CL1 and CL2. Load capacitance CL
has the following formula:CL- CL1 x CL2/( CL1 + CL2) + Cstray where Cstray is the pin capacitance
and board or trace PCB-related capacitance, Typically, it is between 2 pF and 7 pF.
Warning: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly
recommended to use a resonator with a load capacitance CL≤7pF. Never use a resonator with a
load capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL=6 pF, and C stray = 2 pF, then CL1= CL2
=8 pF
Figure 13. Typical application of 32.768MHz crystal oscillator
5.3.5. Internal Clock Source Features

High Speed Internal (HSI) RC Oscillator Tes
HSI Oscillator Features(1)

Value Value m Value
fHSI Frequency 8 MHz
HSI oscillator Factory TA=-25°C
ACCHSI 1 1 %
accuracy calibration VDD = 3.3V
TA=-40~105°C
-2.63 3.56 %
VDD = 2-3.6V
TA =25°C
-0.88 3.28 %
VDD = 2-3.6V
User
-1 1
calibration
HSI oscillator
tSU(HSI) VDD = 3.3V TA =-40~105°C 1.73 2.12 μs
startup TMRe
HSI oscillator power
IDD(HSI) VDD = 3.6V TA =-40~105°C μA
consumption
Low Speed Internal (LSI) RC Oscillator Test
LSI Oscillator Features (1)

Symbol Parameters Unit
Value Value Value
Frequency (VDD = 2-3.6V TA =
fLSI 41 40 50 KHz
-40~105°C)
LSI oscillator startup TMRe
tSU(LSI) 39 μs
(VDD = 3.3V TA = -40~105°C)
LSI oscillator power consumption
IDD(LSI) 1 1.5 μA
(VDD = 3.6V TA = -40~105°C)
1 Data was derived from a comprehensive evaluation and is not tested in production.
Wake Up TMRe in Low Power Mode

The TMRe values in the table are all a wake-up clock source from an 8MHz HSI RC oscillator
and measured during its wake-up phase. The wake-up clock source is deteremined by current
working mode:
 Stop or standby mode: the clock source is the RC oscillator
 Sleep mode: the clock source is the clock set when entering sleep mode
Wake Up TMRe in Low Power Mode

Typical
Value
tWUSLEEP(1) Wake up from sleep mode 1.2 μs
tWUSTOP(1) Wake up from stop mode (regulator is in running-mode) 3.6 μs

Wake-up from stop mode (regulator is low power mode) 6
tWUSTDBY(1) Wake-up from standby mode 32 μs
(1) The wakeup TMRes are measured from the wakeup event to the point in which the user
application code reads the first instruction
5.3.6. PLL Features
PLL Features
Value
Maximu
Symbol Parameters Minimu Typical Unit
m Value
m Value Value (1)
PLL Input clock (2) 2 8 25 MHz

fPLL_IN
Input Clock Duty Cycle 40 60 %
PLL multiplier output clock
fPLL_OUT 16 96 MHz
(VDD = 3.3V TA = -40~105°C
tLOCK PLL lock TMRe 130 μs
(2) Note that the appropriate multiplication factor is used so that the PLL input clock frequency
is consistent with the range determined by fPLL_OUT.
5.3.7. Memory Features
FLASH Memory
FLASH Memory Features (1)

Value Value Value
16-bit
TA = -40~105°C
tprog programming 17.8 18.6 19.5 μs
VDD=2.4~3.6V
TMRe
Page (1K bytes) TA = -40~105°C
tERASE 1.34 1.42 1.51 ms
erase TMRe VDD=2.4~3.6V
Whole erase TA = 25°C
tME 6.5 ms
TMRe VDD=3.3V
Programmable
Vprog TA = -40~105°C 2.0 3.3 3.6 V
voltage
FLASH Memory Life and Data Retention Period

Value Value Value
Thousand
Number of
NEND TA =-40~85℃ 100 TMRes
erase cycles
cycle
Data Retention
tRET TA = 55°C 20 Years
Period
5.3.8. I/O Ports Features

Input/Output Static Features
I/O Static Features (Test conditions VCC=2.7-3.6V, TA = -40~105°C)

Value Value Value
VIL Low level input voltage -0.5 0.8
Standard I/O pin, input high level
2 VDD+0.5
voltage TTL port
VIH V
FT I/O pin(1), input high level
2 5.5
voltage
VIL Input low level voltage CMOS port -0.5 0.3VDD
Value Value Value
VIH Input high level voltage 0.7VDD VDD+0.5
Standard I/O Schmitt trigger
150 mV
voltage hysteresis(2))
Vhys
FT I/O Schmitt trigger voltage
5%VDD mV
hysteresis(2)
VSS ≤ VIN ≤ VDD
±1
Standard I/O port
Input leakage current (3)
μA
Ilkg VIN = 5V
1
I/O FT
Weak pull-up equivalent
RPU VIN = VSS 32 40 49 kΩ
resistance(4)
Weak pull-down equivalent
RPD VIN = VDD 32 40 49 kΩ
resistance (4)
CIO I/O pin capacitance 5 pF
(1) FT = 5V tolerant. To withstand voltages above VDD +0.3, the internal pull-up or pull-down
resistors must be turned off.
(2) The hysteresis voltage of the Schmitt trigger switch level is derived from a comprehensive
evaluation and is not tested in production.
(3) If there is reverse current sinking on adjacent pins, the leakage current may be higher than
the maximum.
(4) The pull-up resistor is designed to be implemented as a true resistor in series with a
controllable PMOS/NMOS switch
Output Drive Current Test
The GPIO (General Purpose Input/Output Port) can sink or output up to ±8mA and can sink up to
±20mA (VOL/VOH reduction). In user applications, the number of I/Os capable of driving current
must be limited so that the current consumed cannot exceed the absolute maximum rating:
 The sum of the currents sourced by all the I/O on VDD, plus the maximum Run consumption
of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD.
 The sum of the currents sunk by all the I/O on VSS, plus the maximum Run consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS.
Output Voltage Test
Output Voltage Features (test conditions VCC=2.7-3.6V,TA = -40~105°C)
Symbol Parameters Conditions Minimum Maximum Unit

Value Value
Output low level, when 8 pins

VOL(1) 0.4
simultaneously sink current TTL port, IIO = +8mA
V
Output high level, when 8 pins 2.7V < VDD < 3.6V
VOH(2) VDD -0.4
simultaneously output current
VOL(1) 0.4
simultaneously sink current CMOS port, IIO = +8mA
V
VOH(2) 2.4
VOL(1)(3) 1.3
simultaneously sink current IIO = +20mA
V
VOH(2)(3) VDD -1.3(4)
(1) The current IIO absorbed by I/O must always follow the absolute maximum rating
requirements, while the sum of the IIO s (all I/O and control pins) must not exceed IVSS.
(2) The current IIO of the I/O output must always follow the absolute maximum rating
requirements, while the sum of the IIO s (all I/O and control pins) must not exceed IVDD.
(4) The driving capability of PC13-15 is not included in this item. The other PC port
specifications are in the voltage range of 3.3V < VDD < 3.6V.
Input and Output AC Features (TA = 25°C)
Input and Output AC Features

MODEx[1:0]
Minimum Maximum
Configuratio Symbol Parameters Conditions Unit
value value
n
CL = 50 pF, VDD =
fmax(IO)out Max frequency(2) 2 MHz
2~3.6V
10 Output high to low
tf(IO)out 50(3)
(2MHz) fall TMRe CL = 50 pF, VDD =
ns
Output low to high 2~3.6V
tr (IO)out 50(3)
rise TMRe
CL = 50 pF, VDD =
2~3.6V
01
Output high to low
(10MHz) tf(IO)out CL = 50 pF, VDD = 24(3)
fall TMRe ns
2~3.6V
tr (IO)out Output low to high 23
MODEx[1:0]
Minimum Maximum
Configuratio Symbol Parameters Conditions Unit
value value
n
rise TMRe
CL = 30 pF, VDD =
2.7~3.6V
11 Output high to low
tf(IO)out 7(3)
(50MHz) fall TMRe CL = 30 pF, VDD =
ns
Output low to high 2.7~3.6V
tr (IO)out 5(3)
rise TMRe
(1) The speed of the I/O port can be configured by MODEx[1:0].
(2) The maximum frequency is defined in the figure below.
(3) It is guaranteed from design and is not tested n production
Figure 14. Input and Output AC Features Definition

5.3.9. NRST Pins Features
The NRST pin input driver is implemented in a CMOS process that is connected to a
permanent pull-up resistor, RPU
NRST NRST Pin Features (Test condition VCC=3.3V,TA = -40~105°C

Maxim
Minimum Typical
Symbol Parameters Conditions um Unit
Value Value
Value
NRST input low level
VIL(NRST)(1) -0.5 0.8
voltage
V
NRST input high level
VIH(NRST) (1)
2 VDD+0.5
voltage
NRST Schmitt trigger
Vhys(NRST) 300 mV
voltage hysteresis
Weak pull-up equivalent
RPU VIN = VSS 32 40 49 kΩ
resistance(2)
(1) Data is guaranteed from design, and is not tested in production.
(2) The pull-up resistor is implemented by a pure resistor in series with a turn-off PMOS/NMOS
transistor. The PMOS/NMOS switch has a small resistance
5.3.10. Communication Interface

I2C Interface Features
I2C Interface Features (Test conditions VDD = 3.3V TA = 25°C
Standard I2C(1) Fast I2C(1) (2)

Symbol Parameters Minimum Maximum Minimum Maximum Unit
Value Value Value Value
tw(SCLL) SCL clock low TMRe 5.05 1.72
μs
tw(SCLH) SCL clock high TMRe 4.94 0.77
tsu(SDA) SDA setup TMRe 4532 1216
th(SDA) SDA hold TMRe 0(3) 503 0(4) 459(3)

tr(SDA) Rise TMRe for SDA and
197 190
tr(SCL) SCL
ns
tf(SDA)
Fall TMRe for SDA and SCL 8 9.8
tf(SCL)
th(STA) Start condition hold TMRe 4.97 0.82
μs
tsu(STA) Repeated start condition 4.93 0.81
Standard I2C(1) Fast I2C(1) (2)
Symbol Parameters Minimum Maximum Minimum Maximum Unit
Value Value Value Value
setup TMRe
tsu(STO) Stop condition setup TMRe 4.91 0.82 μs

Stop to Start condition
tw(STO:STA) 5.27 4.02 μs
TMRe (bus free)
(2) For the bit to reach the maximum frequency of the standard mode I2C, fPCMU1 must be
greater than 2MHz. To achieve the maximum frequency of fast mode I2C, fPCMU1 must be
greater than 4MHz.
(3) If you do not want to stretch the low TMRe of the SCL signal, the maximum hold TMRe of
the start condition must be met.
(4) In order to cross the undefined area of the falling edge of SCL, the SDA signal must be
guaranteed to have a hold TMRe of at least 300 ns inside the MCU.
Figure 15. Bus AC Waveform and Measurement Circuit (1)
(1) Measured points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
SPI Interface Features
SPI Features (VDD= 3.3V TA =25°C)

Minimu Maximum
m Value Value
fSCK Master mode 18

SPI Clock Frequency MHz
1/tc(SCK) Slave Mode 18
tr(SCK) SPI clock rise and fall
Load capacitance: C=30pF 7.1 ns
tf(SCK) TMRes
tsu(NSS) (2) NSS setup TMRe Slave mode fPCMU = 36MHz 111.4 ns
th(NSS) (2) NSS hold TMRe Slave mode fPCMU = 36MHz 55.6 ns
tw(SCKH)(2) Master mode, fPCMU = 36MHz
SCK high and low TMRe 55.1 55.9 ns
tw(SCKL)(2) presc=4
tsu(MI)(2) Master mode 10.9

Data input setup TMRe ns
tsu(SI)(2) Slave mode 21.3
th(MI)(2) Master Mode 35

Data input hold TMRe ns
th(SI)(2) Slave Mode 25
Data output access 6.5 8.7
ta(SO)(2)(3) Slave mode, fPCLK = 20MHz ns
TMRe
Data output disable 12
tdis(SO)(2)(4) Slave mode ns
TMRe
Slave mode (after enable
tv(SO)(2)(1) Data output valid TMRe 19.3 ns
edge)
Master mode (after enable
tv(MO)(2)(1) Data output valid TMRe 7.6 ns
edge)
Slave mode (after enable
th(SO)(2) 10.7
edge)
Data output hold TMRe ns
Master mode (after enable
th(MO)(2) 2
edge)
(1) The SPI1 feature of the remap needs further determination.
(2) It is derived from calculation and is not tested in production.
(3) The minimum value represents the minimum TMRe to drive the output, and the maximum
value represents the maximum TMRe at which the data is valid.
(4) The minimum value represents the minimum TMRe to turn off the output, and the maximum
value represents the maximum TMRe to place the data line in a high impedance state.
Figure 16. TMRing Diagram - Slave Mode and CPHA=0
NSS Input
tc(SCK) th(NSS)
tSU(NSS)
CPHA=0
CPOL=0 th(SCKH)
CPHA=0 tW(SCKL)
CPOL=1
SCK Input
tV(SO) tr(SCK) tdls(SO)
th(SO) tf(SCK)
ta(SO)
MISO
Output MSB OUT BIT 6~1 OUT LSB OUT
tSU(SI)
MSB IN BIT 6~! IN LSB IN
MOSI Input
th(SI)
Figure 17. SPI TMRing Diagram - Slave Mode and CPHA=0

NSS Input
tc(SCK)
tSU(NSS)
th(NSS)
CPHA=1
CPOL=0 tW(SCKH)
CPHA=1 tW(SCKL)
CPOL=1
SCK Input
tr(SCK)
tV(SO) tf(SCK)
MISO ta(SO) th(SO) tdls(SO)
Output
MSB out BIT 6~1 OUT LSB OUT
tSU(SI) th(SI)
Msb in BIT 6~1 IN LSB IN
MOSI Input
(1) The measured points are done at CMOS levels:0.3VDD and 0.7VDD
Figure 18. SPI TMRing Diagram - Master Mode(3)
High
NSS input tc(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
SCK input tW(SCKH)
tr(SCK)
tW(SCKL)
tSU(MI) tf(SCK)
MISO input MSB IN BIT 6~1 IN LSB IN
th(MI)
MOSI BIT 6~1 OUT

MSB OUT LSB OUT
output
tv(MO)
th(MO)
(1) The measured points are done at CMOS levels: 0.3VDD and 0.7VDD
USBD Interface Features
USB DC Characteristics
Minimum Maximum
Symbol Parameter Conditions Unit
Value 1 Value 1
Input levels
USB operating 3
VDD 3.0 3.6 V
voltage 2
Differential input
VDI 4 I USBDP USBDM 0.2
sensitivity
Differential
VCM 4 common mode Include VDI range 0.8 2.5 V
threshold
Single ended
4
VSE 1.3 2.0
receiver threshold
Output levels
Static output level

5
VOL RL of 1.5kΩto 3.6V 0.3
low
V
Static output level
5
VOH RL of 1.5kΩto VSS 2.8 3.6
high
(1) All the voltages are measured from the local ground potential.
(2) In order to be compatible with USB2.0 full-speed electrical specification, USBDP (D +) pin
must pass a 1.5 k Ω resistor connected to the voltage from 3.0 V to 3.6 V.
(3) The function of APM32F103xx can be guaranteed at 2.7V without the electrical
characteristics of degradation in 2.7~ 3.0v voltage range.
(4) Guaranteed by comprehensive evaluation and is not tested in production.
(5) RL is the load connected on the USB drivers.
Figure 19. USB TMRing: Definition of Data Signal Rise and Fall TMRes
USB Full-speed Electrical Characteristics

Minimum Maximum
Value Value
tr Rise TMRe CL = 50pF 4.6 9.3 ns
tf Fall TMRe CL = 50pF 5.2 10.9 ns
Rise&fall TMRes
trfm tr / tf 71 97 %
match
Crossover voltage of
VCRS 1.60 2.17 V
output signal
5.3.11. 12-bit ADC Features
ADC Features (VDD= 2.4-3.6V T A =-40~105°C)

Value Value Value
VDDA Power supply 2.4 3.6 V
Positive reference
VREF+ 2.4 VDDA V
voltage
IVREF Current on VREF+ input pin 260 484 μA
Value Value Value
fADC ADC clock frequency 0.6 14 MHz
fS Sampling rate 0.05 1 MHz
VAIN Conversion voltage range 0 VREF+ V
fADC = 14MHz 5.9 μs
tCAL Calibration TMRe
83 1/fADC
RADC Sampling resistor 1 kΩ
Sample and hold
CADC 2 Pf
capacitor
fADC =
0.107 17.1 μs
tS Sampling TMRe 14MHz
1.5 239.5 1/fADC
fADC =
Total conversion TMRe 1 18 μs
14MHz
tCONV (includes sampling
14~252(tS for sampling + 12.5 for
TMRe) 1/fADC
successive approximation)
(2) Cparasitic must be added to CAIN. It represents the capacitance of the PCB (dependent on
soldering and PCB layout quality) plus the pad capacitance (3 pF). A high Cparasitic value
will downgrade conversion accuracy. To remedy this, fADC should be reduced.
Figure 20. Typical application of ADC
VDD
Sample and hold

VT
0.6V ADC converter
RAIN(1) AINx RADC(1) 12-bit
Converter
VT IL±1μA
VAIN
Cparasitic 0.6V CADC(1)
Parasitic
Capacotor
The formula for calculating the maximum external input impedance is as follows
Formula 1: formula of maximum RAIN
𝑇𝑆
RAIN< -RADC
𝑓𝐴𝐷𝐶 𝐶𝐴𝐷𝐶 ln(2𝑁+2 )
fADC=14MHZ, CADC=12PF(Table 41), RADC=1kΩ(Table 41). Under the requirement of 0.25LSB
sampling error accuracy, the relation between TS and RAIN is shown in the following table:
Maximum RAIN at fADC=14MHz 1
TS cycle tS μs Maximum RAIN kΩ

1.5 0.11 4.5
7.5 0.54 26.6
13.5 0.96 48.7
28.5 2.04 103.9
41.5 2.96 151.7
55.5 3.96 203.2
(1) Data is guaranteed from design and is not tested in production.
ADC Accuracy
Typical Maximum
Symbol Parameter Conditions Unit
value value(3)
ET Total error ±2.5 ±5.5
Eo Offset error fPCMU2=56MHz, ±2.1 ±3.5

fADC=14MHz,RAIN<10KΩ,
EG Gain error ±2.0 ±4
VDDA=2.4~3.6V,TA=-40~105℃ LSB
Differential
ED Measurement was made after ±1.5 ±2.5
linearity error
the ADC calibration
Integral
EL ±1.8 ±3
linearity error
(1) DC accuracy value of ADC is measured after internal calibration
(2) ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the
standard analog input pins should be avoided as this significantly reduces the accuracy of
the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to standard analog pins which may potentially inject negative
current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section
5.3.32 does not affect the ADC accuracy.
Figure 21. ADC Accuracy Characteristics
VREF+ VDDA
[1LSBIDEAL= (Or ，Depending on)]
4096 4096
EG
4095
4094
4093
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3 ED
2
1 LSB IDEAL
1
0
VSSA 1 2 3 4 5 6 7 4093 4094 4095 4096 VDDA
5.3.12. Temperature Sensor Features
Temperature Sensor Features

Value Value Value
Average slope
Avg_Slope(1) 4.1 4.2 4.5 mV/ºC
(VDD = 3.3V, TA = -40~105°C)
V25 Voltage at 25ºC (VDD =2.4-3.6V) 1.38 1.41 1.44 V
tSTART(2) Setup TMRe 4 10 μs
ADC sampling TMRe when reading the
TS_temp(2) (3) 17.1 μs
temperature
(1) Data is guaranteed by analysis on features, and is not tested in production.
(2) Data is guaranteed from design, and is not tested in production.
(3) The shortest sampling TMRe can be determined by the application through multiple
iterations.
5.3.13. EMC Features

Sensitivity tests are sampled for testing during a comprehensive evaluation on the product.
Electromagnetic Sensitivity (EMS)
When running a simple application (controlling 2 LEDs flashing through the I/O port), the test
sample is spurious electromagnetic interference until an error occurs, and LED flashing indicates
an error. The test complies with IEC61000-4-4 standard.
EMS Features
Symbol Parameters Conditions Level
VDD = 3.3V TA = +25 °C
Voltage limits to be applied on any I/O
VFESD fHCMU = 72MHz, complies with 2B
pin to induce a functional disturbance.
IEC 61000-4-2
Fast transit voltage burst limits to be VDD = 3.3V TA = +25 °C
VEFTB applied through 100 pF on VDD and VSS fHCMU = 72MHz, complies with 2B
pins to induce a functional disturbance. IEC 61000-4-4
Electromagnetic Interference (EMI)
Monitor the electromagnetic field emitted by the chip while running a simple application (flashing
2 LEDs through the I/O port). This emission test complies with the SAE J1752/3 standard, which
specifies the load on the test board and pins.
EMI Features
Maximum value
Detection
Symbol Parameters Conditions (fHSE/fHCMU) Unit
frequency band
8/36MHz 8/96MHz
VDD = 3.3V TA = 30-230MHz PASS PASS
SEMI Peak +25 °C, LQFP100 dBμV
130MHz-1GHz PASS PASS
package
6. Packaging Information
6.1. LQFP100 Package Diagram
Figure 22. LQFP100 Package Diagram
(1) Drawing is not to scale.

(2) The inside of the pad on the back is not connected to V SS or VDD.
(3) There is a pad on the bottom of the QPN package that should be soldered to the PCB.
(4) All pins should be soldered to the PCB.
LQFP100 Package Data
DIMENSION LIST(FOOTPRINT: 2.00)
S/N SYM DIMENDIONS REMARKS
1 A MAX. 1.60 OVERALL HEIGHT
2 A1 0.1±0.05 STANDOFF
3 A2 1.40±0.05 PKG THICKNESS
4 D 16.00±0.20 LEAD TIP TO TIP
5 D1 14.00±0.10 PKG LENGTH
6 E 16.00±0.20 LEAD TIP TO TIP
7 E1 14.00±0.10 PKG WDTH
8 L 0.60±0.15 FOOT LENGTH
9 L1 1.00 REF LEAD LENGTH
10 T 0.15 LEAD THICKNESS
11 T1 0.127±0.03 LEAD BASE METAL THICKNESS
12 a 0°~7° FOOT ANGLE
13 b 0.22±0.02 LEAD WIDTH
14 b1 0.20±0.03 LEAD BASE METAL WIDTH
15 e 0.50 BASE LEAD PITCH
16 H(REF.) (12.00) CUM. LEAD PITCH
17 aaa 0.2 PROFILE OF LEAD TIPS
18 bbb 0.2 PROFILE OF MOLD SURFACE
19 ccc 0.08 FOOT COPLANARITY
20 ddd 0.08 FOOT POSITION
(1) Dimensions in millimeters
Figure 23. LQFP100-100 pins,14x14mm welding Layout proposal
1.Dimensions in millimeters
Figure 24. LQFP100-100 pin,14x14mm package identification diagram


(2) The inside of the pad on the back is not connected to VSS or VDD.
LQFP64 Package Data
2 A1 0.100±0.050 STANDOFF
5 D1 10.000±0.100 PKG LENGTH
7 E1 10.000±0.100 PKG WDTH
13 b 0.220±0.050 LEAD WIDTH
Figure 26. LQFP64-64 pin,10x10mm welding Layout proposal
Figure 27. LQFP64-64 pin,10x10mm package identification diagram


(2) The inside of the pad on the back is not connected to VSS or VDD.
LQFP Package Data
2 A1 0.1±0.05 STANDOFF
5 D1 7.00±0.10 PKG LENGTH
7 E1 7.00±0.10 PKG WDTH
13 b 0.22±0.02 LEAD WIDTH
(1) dimensions in millimeters
Figure 29. LQFP48-48 pin,7x7mm welding Layout proposal
Figure 30. LQFP48-48 pin,7x7mm identification diagram

6.4. QFN36 Package Diagram
Figure 31. QFN36 Package Diagram

(2) The inside of the pad on the back is not connected to V SS or VDD.
QFN36 Package Data
SYMBOL MIN NOD MAX
TOTAL THCKNESS A 0.8 0.85 0.9
STANO OFF A1 0 0.02 0.05
MOLO THCKNESS A2 --- 0.65 ---
L/F THCKNESS A3 0.203REF
LEAD WIDTH b 0.2 0.25 0.3
X D 6 BSC
BOOY SIZE
Y E 6 BSC
LEAD PITCH e 0.5 BSC
X D2 4.05 4.15 4.25
EP SIZE
Y E2 4.05 4.15 4.25
LEAD LENGTH L 0.45 0.55 0.65
LEAD TIP TO EXPOSE PAD
EDGE k 0.375 REF
PACKAGE EOGE TOLERANCE aaa 0.1
MOLD FLATNESS ccc 0.1
COPLANARITY eee 0.08
LEAD OFFSET bbb 0.1
EXPOSED PAD OFFSET fff 0.1
(1) dimensions in millimeters
Figure 32. QFN36 pin, 6 x 6mm Welding Layout Proposal
Figure 33. QFP36 pin, 6x6mm identification diagram

7. Ordering Information
Ordering Information Table
Oder No. FLASH(KB) SRAM(KB) Package Temperature range
APM32F103T4U6 16 6 QFN36 industrial level -40℃~85℃
APM32F103TBU6 128 20 QFN36 industrial level -40℃~85℃
APM32F103C4T6 16 6 LQFP48 industrial level -40℃~85℃
APM32F103CBT6 128 20 LQFP48 industrial level -40℃~85℃
APM32F103R4T6 16 6 LQFP64 industrial level -40℃~85℃
APM32F103RBT6 128 20 LQFP64 industrial level -40℃~85℃
APM32F103V8T6 64 20 LQFP100 industrial level -40℃~85℃
APM32F103VBT6 128 20 LQFP100 industrial level -40℃~85℃
APM32F101TBU6 128 20 QFN36 industrial level -40℃~85℃
APM32F101V8T6 64 20 LQFP100 industrial level -40℃~85℃
Oder No. FLASH(KB) SRAM(KB) Package Temperature range
APM32F101VBT6 128 20 LQFP100 industrial level -40℃~85℃
8. Package Information
Figure 34. Strip Package Specification Diagram
All pictures are only for reference, appearance depends on products
Strip Package Parameters Specification
Reel
Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter
Type (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
APM32F103RBT6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F102RBT6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F101RBT6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F103R8T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F102R8T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F101R8T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F103R6T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F102R6T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F101R6T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F103R4T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F102R4T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F101R4T6 LQFP 64 1000 330 12.35 12.35 2.2 16 24 Q1
APM32F103CBT6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F102CBT6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F101CBT6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F103C8T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F102C8T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F101C8T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F103C6T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F102C6T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F101C6T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F103C4T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F102C4T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F101C4T6 LQFP 48 2000 330 9.3 9.3 2.2 12 16 Q1
APM32F103TBU6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
APM32F101TBU6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
APM32F103T8U6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
APM32F101T8U6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
APM32F103T6U6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
APM32F101T6U6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
APM32F103T4U6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
APM32F101T4U6 UFQFPN 36 2500 330 6.4 6.4 1.4 8 16 Q1
Figure 35. Tray Package Diagram

All the pictures are only for reference, appearance depends on products
Tray Package Parameters Specification

Tray Tray
Package X-Dimension Y-Dimension X-Pitch Y-Pitch
Device Pins SPQ Length Width
Type
(mm) (mm) (mm) (mm) (mm) (mm)
APM32F103VBT6 LQFP 100 900 16.6 16.6 20.3 21 322.6 135.9
APM32F101VBT6 LQFP 100 900 16.6 16.6 20.3 21 322.6 135.9
APM32F103V8T6 LQFP 100 900 16.6 16.6 20.3 21 322.6 135.9
APM32F101V8T6 LQFP 100 900 16.6 16.6 20.3 21 322.6 135.9
APM32F103RBT6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F102RBT6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F101RBT6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F103R8T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F102R8T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F101R8T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F103R6T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F102R6T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F101R6T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F103R4T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F102R4T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F101R4T6 LQFP 64 1600 12.3 12.3 15.2 15.7 322.6 135.9
APM32F103CBT6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F102CBT6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F101CBT6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F103C8T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F102C8T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F101C8T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F103C6T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F102C6T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F101C6T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F103C4T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F102C4T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
Tray Tray
Package X-Dimension Y-Dimension X-Pitch Y-Pitch
Device Pins SPQ Length Width
Type
(mm) (mm) (mm) (mm) (mm) (mm)
APM32F101C4T6 LQFP 48 2500 9.7 9.7 12.2 12.6 322.6 135.9
APM32F103TBU6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
APM32F101TBU6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
APM32F103T8U6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
APM32F101T8U6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
APM32F103T6U6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
APM32F101T6U6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
APM32F103T4U6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
APM32F101T4U6 UFQFPN 36 4900 6.2 6.2 8.8 9.2 322.6 135.9
9. Commonly Used Function Module Denomination
Commonly Used Function Module Denomination
Commonly Used Function Module Denomination
Module Function short title
Reset management unit RMU
Clock management unit CMU
Reset and Clock management unit RCM
External Interrupt EINT
General Purpose IO GPIO
Alternate Function IO AFIO
Wakeup controller WAKEUP
Buzzer BUZZER
Independent watchdog timer IWDT
Window watchdog timer WWDT
Timer TMR
CRC Controller CRC
Power management unit PMU
The banked register BAKR
DMA Controller DMA
analog-digital converter ADC
digital-analog converter DAC
Real-time clock RTC
External storage controller EMMC
SDIO Interface SDIO
USB Device Controller USBD
Controller Local Area Network CAN
USB OTG OTG
Ethernet ETH
I2C Interface I2C
Serial Peripheral Interface SPI
Universal Asynchronous Receiver Transmitter UART
Universal Asynchronous/Synchronous Receiver Transmitter USART
Flash memory interface control unit FMC
10. Reversion History
Document Reversion History
Date Version Changes
2/14/2019 1.0.0 Initial release
2/26/2019 1.0.1 Add the notes in Table 8
5/6/2019 1.0.2 Voltage was changed from 1.8V to 1.6V
Added electrical characteristics and commonly used function module
1/3/2020 1.0.3
denomination, and modified the cover
1/24/2020 1.0.4 Extracted section 5.3 from section 5.2
3/4/2020 1.0.5 Generated section 3.14.2

ARM® Cortex®-M3 Based 32-Bit MCU

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APM32F103x4x6x8xB

ARM® Cortex®-M3 based 32-bit MCU

 System Architecture  Timers

- 32-bit ARM® Cortex®-M3 core - 1 16-bit advanced control timer TMR1,

- Up to 96MHz working frequency support dead zone control and emergency

 I/O - Medical devices, PC peripherals,

3. Features Description ........................................................................................................................ 10

3.1. ARM® Cortex®-M3 Core ...................................................................................................................... 10

3.3. Power Management............................................................................................................................. 11

3.3.1. Power Supply Schemes ...................................................................................................................... 11

3.3.2. Voltage Regulator ............................................................................................................................... 12

3.3.3. Power Supply monitor......................................................................................................................... 12

3.3.4. Low Power Mode ................................................................................................................................ 12

3.4. Clocks and Startup ............................................................................................................................. 13

3.5. RTC and Backup Registers ................................................................................................................ 13

3.6. Boot Modes ......................................................................................................................................... 14

3.8. General Purpose IO Port .................................................................................................................... 14

3.9. General-purpose urpose Input\Output Interface ................................................................................. 14

3.10. Interrupt Controller .............................................................................................................................. 14

3.10.1. Nested Vectored Interrupt Controller (NVIC) ...................................................................................... 14

3.10.2. External Interrupt/Event Controller (EXTI) .......................................................................................... 15

3.11. Floating Point Unit (FPU) .................................................................................................................... 15

3.12. DMA .................................................................................................................................................... 15

3.13. Tmrer .................................................................................................................................................. 16

3.15. Peripheral Interface ............................................................................................................................ 17

3.15.1. I2C Bus ............................................................................................................................................... 17

3.15.3. Serial Peripheral Interface (SPI) ......................................................................................................... 18

3.15.4. Quad SPI Controller (QSPI) ............................................................................................................... 18

3.15.6. Universe Serial Bus (USB) ................................................................................................................. 18

3.15.7. Simultaneous Use of USB Interface and CAN Interface: ................................................................... 18

3.15.8. ADC (Analog/Digital Converter) .......................................................................................................... 18

3.15.9. Temperature Sensor ........................................................................................................................... 19

4. Pin Features ...................................................................................................................................... 20

4.1.1. APM32F103x4x6x8xB Series LQFP100 ............................................................................................ 20

4.1.2. APM32F103x4x6x8xB Series LQFP64 .............................................................................................. 21

4.1.4. APM32F103 x4x6x8xb Series QFN36................................................................................................ 23

4.2. Pin Description .................................................................................................................................... 24

4.3. System Diagram ................................................................................................................................. 31

4.4. Clock Tree........................................................................................................................................... 32

4.5. Address Mapping ................................................................................................................................ 33

4.6. Power Supply Scheme ....................................................................................................................... 34

5. Electrical Features ............................................................................................................................ 35

5.1. Parameter Conditions ......................................................................................................................... 35

5.1.1. Maximum and Minimum Values .......................................................................................................... 35

5.1.2. Typical Value ....................................................................................................................................... 35

5.1.3. Typical Curve ...................................................................................................................................... 35

5.1.4. Load Capacitance ............................................................................................................................... 35

5.2. Absolute Maximum Ratings ................................................................................................................ 36

5.2.1. Maximum Rated Voltage Features ..................................................................................................... 36

5.2.2. Maximum Rated Current Features ..................................................................................................... 37

5.2.3. Maximum Temperature Features ........................................................................................................ 38

5.2.4. Maximum Ratings Electrical Sensitivity .............................................................................................. 38

5.2.5. Test Under the General Working Conditions ...................................................................................... 39

5.2.6. Embedded Reset and Power Control Block Features ........................................................................ 40

5.2.7. Built-in Reference Voltage Features Test ........................................................................................... 40

5.2.8. Supply Current Features .................................................................................................................... 41

5.2.9. External Clock Source Features ......................................................................................................... 49

5.2.10. Internal Clock Source Features .......................................................................................................... 52