2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

A PPD and Charge Pump Switching Circuit to

Optimize the Output Phase Noise of the PLL in
O.13-f,lm CMOS
Manas Kumar Hati* and Tarun K. Bhattacharyyat

Email: *manashatUitkgp@rediffmail.com. t tkb@ece.iitkgp.ernet.in

Advanced Technology Development Centre, lIT Kharagpur, India 721302

Abstract-This paper presents the design of a novel Phase with a state machine with memory elements such as f1ip­
Frequency Detector (PFD) and Charge Pump (CP) switching flops [1], as shown in Fig. l. Without state of the art, the
circuits for the frequency synthesizer in phase-locked loop (PLL).
acquisition range is on the order of WLPF [1]. Where, WLPF
Our proposed PFD technique can eliminate the effect of missing
edge and phase ambiguity problems in conventional PFDs circuit.
is the 3-dB bandwidth of the loop filter. However, if the WLPF
Also, a novel CP circuit with a special switching scheme has is large there is a problem of more ripple voltages in the
been incorporated to reduce the current mismatch error and PLL output. But, it is also true that due to the process and
charge injection error problem with this new design technique. temperature variation oscillation centre frequency may very
The design charge pump current mismatch has been checked in
resulting problem of acquisition or detection error due to over
0.13 J.lm CMOS process and worst case mismatch error is 0.025
J.lA for a control voltage range from 0.25 V to 1.0 V for a 1.2 volt
all change of the frequency spectrum. Therefore, keeping the
supply voltage. Phase noise performance of the proposed PFD high WLPF there is a "aided acquisition" which has been
and CP circuit is about -117.3 dBclHz at 1 MHz offset frequency introduced by using a frequency detection circuit along with
for a load capacitance of 10 fF. Current noise of our PFD and CP the phase detection circuit as reported in [1]. Such a scheme
circuit has been measured from the transistors level simulation to
finally increases the acquisition range to the tuning range of
find the phase noise of the fractional-N PLL, for output frequency
of 2.2 GHz with 40 MHz reference signal in CppSim system
the LC-VCO.
simulator. Proposed PFD and CP switching circuit's phase noise
performance shows the 17.36 dB improvement compare to the
NOR based PFD and 7.4 dB improvement compare to the NAND
UP
based PFD topology. Also, the effect of CP current mismatch and f---�
dc offset current at any of the current source or sink has been
incorporated to check the effect on spur and phase noise of
the fractional-N frequency synthesizer. In addition, charge pump
current noise and phase noise modelling has been done here to
find the output phase noise of the PLL considering the PFD and
CP output current noise measured in transistor level in 0.13 J.lm
�KDIV
CMOS. DN
Index Terms-CMOS integrated circuits, phase frequency
detector, dead zone, timing jitter, charge pump switching circuit,
and phase noise. lal Ibl

Fig. 1. (a) Linear PFD architecture and (b) State diagram.

I. INTRODUCTION
A new CP circuit with a switching scheme has been
Phase locked loops (PLLs) are widely used for commu­ incorporated in our design as shown in Fig. 6 and it can
nication, clock phase synchronization, frequency synthesis, eliminate the charge injection error during "off' state of the
wireless system, digital circuits, high performance micro­ current switches. Although, this novel switching circuit for the
processor system, disk drive electronics, and data recovery CP circuit can be implemented using each DFF unit block of
circuits. Charge pump based PLLs draw most attention due NAND or NOR or TSPC based PFD topology. But for our
to their simple structure, CMOS compatibility and low phase design the proposed PFD circuit, there is a need of switching
noise properties. However, there is increasing demand for modification for our clock switching scheme in a different
high frequency operation, low power, and low jitter PLL. way including a AND gate with the proposed DFF technique
A part of a phase locked loop (PLL) based frequency syn­ as shown in Fig. 7 and its output transient response validate
thesizer, is the phase detector (PD) [1]. The phase detectors our design technique as shown in Fig. 8.
detect the phase difference (PD) between the reference clock This paper is organised as follows. Section II deals with
(CLKREF) and the divider clock (CLKDIV)' Some phase PFDs and its non-ideals effects. Section III describes the phase
detectors also detect the frequency errors; they are then called noise of the PFD and CP. Simulation results are depicted in
phase frequency detectors (PFDs) [2]. A PFD is usually built Section IV and Conclusion is given in the last section.

978-1-4799-7926-4/15/$31.00©2015 IEEE
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) -

II. NON-IDE AL EFFECT S IN PFD

Fig. lea) illustrates a common linear tristate PFD archi­
tecture using re-settable DFFs, one AND gate and its state

,---Missing clock edge

diagram is shown in Fig. l(b), and its state is independent of lal Ibl

the duty cycle of the input signals.

CLKREF r------,
Estimated reset time delay of the NOR based PFD circuit is
5Td and it is shown in Fig. 2(b). Where, Td is the equal delay of
�' ��� LI
CLKDlv
the each transistor. Also, it can be designed using the NAND
based architecture to reduce the on time (reset time, treset = __ ____ ____ �

ton) and the optimization of the phase noise has been done by DN
�
setting the proper selection of the WfL ratio [3]. But, in our reset
� ------�
��--�
: '
rj
case the design of the proposed PFD has been shown in Fig. 101
3, that utilizes a novel architecture to eliminate the effects of
Fig. 4. Missing edge problem of the conventional phase frequency detector.
missing edge and phase ambiguity problems. However, details
discussion on jitter and phase noise calculation has not been the phase difference goes near 27r, the leading edge of the
presented here due to brevity. But, the maximum speed can reference triggers the UP signal until the lagging edge of
be higher than the NORINAND based PFD architecture as the divider output comes, which resets both the UP and DN signal
reset delay of our proposed PFD architecture is 3Td (Fig. 3(b)). to low. Due to presence of finite delay of the reset signal,
the reset overwrites the next coming edge of the reference
clock (CLKREF), which is supposed to cause the UP to

�
go high. As a result of the missing edge and a discrepancy
occurs in conventional PFDs [2]. The effect appears as a
�
� negative output phase differences higher than 27r - � where
� � = 27r tresel. . Which depends on the reset path delay
TCLKREF
'K";; :1�-
-;,,}�..j" f--
(treset) and the reference period (TCLKREF)' Note that treset
is determined by the delay of logic gates in the reset path and
,<)
which is not a function of input frequency. The acquisition
Fig. 2. (a) Conventional PFO using NOR gates (b) Estimation of delay (c) slows by how often the wrong information occurs which
Operation of the PFO. depends on �. At an input frequency (TCLKREF 2.treset)
Vdd i
=

----------------------1
where � equals 7r, the PFD outputs the wrong information
PtoposedD FF
half the time fails to acquire frequency lock unconditionally.
This in turn lead PLL to "Pull out" instead of "Pull in". So,

°i::Jr----
the maximum operating frequency can be expressed as

CLKREF �
CL�
I
�__ jil1erofMS-M7 (1)
2.treset
--

�
1- JItterof NOR
=---____

�
�itterofM3-M4
"
.. __ jinerofM12-M1S

�OfM5
�OfMI4
U�inerOIM8

Vdd
D� jinerOfM17
I')
(a)
Fig. 3. Proposed PFO, (a)Jitter contribution to the output (b)eliminates the

A. Missing Edge
non-ideal effects in PFO.

The PFD's characteristic is ideally linear for the entire range B

of input phase difference from -27r to 27r (upper left of Fig.

�
(b)
4(a)). When the inputs differ in frequency, the phase difference
Fig. 5. Phase ambiguity problem in conventional PFO circuit.
-TCLKDIV )
Phase Ambiguity
changes each cycle by 27r. max( c REF
(TCLK .
T LK flEF,TCLKDIV) However,
due to gate delays and parasitic lengthen the "on" state of the B.

reset signal, which can cause missing edges, and this effect Another problem is that the two rising edges to be compared
is never negligible. The effect is shown in Fig. 4(a), when are not unique. At any initial state, the circuit can pick, based
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

upon the previous state, any two rising edges shown in Fig. (treset ton) of the PFD output can be done to find the better
=

5(b) (solid and dashed). In other words output current can be phase noise performance [3] and [4]. Phase noise increases by
in either of the two valid state (solid or dashed) (Fig. 5(a)). the tum on time of the transistors in each gate. Therefore, it is
The effect appears as a negative output for phase differences required to reduce the rise and fall time of the logic gates using
higher than, 21f - �, which depends on the reset path delay NAND based PFD rather than the NOR topology. Therefore,
(treset) and the reference clock period (TcLKREF)' Note that modification has been made to design the NOR PFD to NAND
treset is determined by the delay of logic gates in the reset based PFD [3]. Jitter will modulate the pulse width of the UP
path and is not a function of input frequency. Thus, picking and DN pulses. To get the lower rise and fall time of the
the correct edge to start with can shorten the acquisition time. output pulses, channel length should not be increased high, so
that it will increase the rise and fall time. However, channel
VDD
area of the transistor can be increased by selecting the wider
devices for lower channel length devices. Also, there is a
adverse effect, if we increase the transistor width phase noise
improvement in compensation of high power consumption in
the circuit. The current injection to the PLL output within the
loop bandwidth is equal to if!out,PLL/�I (21f/lcp) .Nnom. =

Where, �I is the error current produce in the CP circuit, due

to the jitter components in the UP and DN pulses and Nnom
is the nominal divider ratio. Phase noise at the PLL output can
be written by the following equation as follows [3]

CP current mismatch for Icp= 20 Il A

level of isolation
(nmos based cascode) -
(increases the o/p impedance)

Fig. 6. A new charge pump circuit with a constant gm OTA and a novel
switching scheme.

,
----------------1

:
::��dF: :
I ""
DfF ,
,
V' H
'- ______ L ____ J___ , Fig. 9. UP, DN current mismatch of the CP circuit.

,-----------------------,
, ,
Tristate PFD: ct=l
<l>divlk] XOR PFD: =2

, ---�:� ,,
,
�--- ��'----------�

Fig. 7. A new clock generation circuit for the CP circuit with proposed PFD ��
qua ti auon :
I n[k]
circuit.

-
III. P H ASE NOISE OF T HE PFD AND CP CIRCUIT
Fig. 10. � 2; Fractional-N frequency synthesizer noise model.
Phase noise of a NAND and TSPC based PFD topology
have been discussed in details as reported in [3]. However, our
proposed PFD design circuit is different from the NANDINOR (2)
or TSPC based PFD topology. Jitter calculation of the pro­
posed PFD technique has been shown in Fig. 3(a). But, in
our design the jitter multiplication comes from the factor of Where, STn( f) denotes the spectral density of the jitter

and is equal to Svn( f)/)...2 ()...

8 rather than 6 in TSPC PFD case [3]. Although, our design component Tn (n=I,2, .. 8) for our proposed PFD (Fig. 3(b))
can eliminate the missing edge and phase ambiguity problems.
d';[t' �). Also, Svn( f) = =

But, few criteria are there, first, the jitter of the NOR gate is the power spectral density and)", is the slope factor, when
modulates the UP and DN pulses width equally, hence the Vout crosses the threshold level VTH i.e: VDD/2. If we
effect of NOR gate jitter is neglected. Similarly, this condition consider, roughly similar gates and rise and fall times, the in­
holds for the ANDI gate present in our proposed PFD design band phase noise observed at the PLL output, can be written
topology. Design optimization and reduction of "on" time as [3]
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

Transient response o11he proposed PFD and proposed CP w�h no�el switching scheme

t o:tIIUPB"'I'�dl'l. : It
..
:t 1:
o
t o:u UPD. "" , r:
2 3 4 5 6

I
Time (sec)

o
co,
"

: �..: 2 3
Ti� '�)
:1 ']
:
4 5 6

t o :DDNCOII,g>di'i!
o ! n ! 2 3
Time (sec)
n ''OJ
:
4 5 6

x 10-"

t o:UIDNBD"'I,g'dl'l:
o�. �v" ':., .•b'.'.4°°•• . . . . . . :� 1
=
...: =:<
6
,____ __ )
Ti� ' ____

1
J
(C'WP)@"'." '''
t ... ....
2 3 4 5

:lkL'''(CPdP).·., ' ·tdi,b, j4 ",.I•••...

Time (sec)

t
o , ,
Time (sec)

Fig. 8. Transient response of the proposed PFD and Proposed CP with novel switching scheme.

�� fractional-N frequency synthesizer noise model is

shown in Fig. 10 and the basic closed loop equation of the
(3) PLL can be written as

H(f) =

1 :�tJ) (4)

Vdd
Where, H(f) is the closed loop gain and A(f) is the open
loop gain of the PLL. A(f) can be written by the following
equation (from Fig. 10)

c)
21f .F(f). (KvJ1 o (Nn1om )
Nnom Icp. (�)
G(f)
A(f) = = . __

Icp
(5)
is the charge pump current and F(f) is the loop filter
transfer function. Type II and Order 3 loop filter with CP
circuit is shown in Fig. 12. Order of the system is defined
by the roll-off factor of the IH(f)I, not by the number of
bias Source independent state variables in the system. However, to avoid
Fig. 11. A basic model for charge pump noise. the inductor awkwardness for the Order 3 design, it could be
Nnom replaced by the active loop filter circuit [5] and [6]. From, (5)
SI
Where, is the divider nominal value. In (3), right
it can be concluded that the A(f) is low pass in nature and
hand side first term (f) signifies the white noise current
has an infinite gain at dc, where H(f) is also low pass in
Sl/
spectral density of the transistor during "on" phase. Second
term f(f) denotes the noise current spectral density of the nature with a low frequency gain of one.
transistor due to its 1/1 noise (transistor "on" states). Last From Fig. 11, it is straight forward to calculate the output
term in the above equation represents the noise created by phase noise spectral density as a function of the charge pump
the transistors over the CL before turning "off" state. Also, in noise spectral density as

)2 (21fNnom)2 ·IH(f)12 ,SIcpn

M1 MlO Sipouf ( I1cp'
our design selection of W/L ratio of the PFD can be done by
solving the power consumption and phase noise optimization
point of view [3]. It is found in Fig. 3(a), that the and = + (6)
0:

device sizes of the transistors andM1 MlO

transistor do not contribute any jitter to the PFD. Therefore,
can be selected
other noise sources

as minImum compare to the other transistors width in the From the above expression it is very clear that the charge
proposed PFD. pump noise on the output phase noise of the PLL decreases
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

with the square of the charge pump current, Ie . However, TABLE I

p
contribution of SIe n is also influenced by the Ie . Where, PLL DESIGN PARAMETERS
p p
SIepn is the charge pump output current noise spectral density.
Closed loop BW, fo
Design Parameters values
And in (6), reference and divider jitter and spur energy has 300E3 Hz
been neglected these are so called "other noise sources". Order 2

fz/ fo
Type II

fre!
Also,
1/8

fvco
(7) 40E6 Hz

fpar.pole
2.2E9 Hz

Icp
Where, 1.2E6 Hz
20/.LA
Detector noise (from, (10)) [-106 lE3 -15]

Kv
gm ex V(IdW) (8) LC-VCO noise -145 @ IOE6
50E6 HzfY
Where, Id and Ware the device current and width, re­ Extracted parameters values

fp
spectively. Also, 'Y has a value of unity at zero VDS and, in K 3.03Ell

fz
6.225E5 Hz

Nnom
long channel devices it decreases toward a value of 2/3. For
3.750E4 Hz

Sp,out
MOSFET, Vdsat can be written as 55
Eg. (10) -106 dBc/Hz

(9)

To keep the output impedance high, as Id increases, W Therefore, (6) can be written as follows :
should be increased to keep the Vdsat constant. As Id/W=
constant, then gm ex Id from (8). Similarly, SIcp n ex Ie
and Sipou., ex 1/Ie . Therefore, Ie should be kept as high as
p Sip
_
o,,' - Ie
1
2
( ) (
2 7r Nn om
2
2 .I
·IH(J)I -2 epn ·D (10)
)
p p p ' a
possible to get better phase noise output due to the charge
pump current noise, however it could be simulated from Where, I; n SIepn is the total mean square current noise
p =

the transistor level design properly and keeping the power contributed by all the noise sources in the UP and DN current
consumption of the circuit in optimization level. supply sources in proposed CP circuit.

I Type II. order I

From Fig. 15, the proposed PFD-CP circuit output noise
current power spectral density of 0.1392E-24 A2/Hz is given
3

for flat region, that gives a Sip,out= -106 dBc/Hz and lIf noise

dBlO plot). Our design parameters for the PLL is reported in

c, comer of lE3 Hz with slope of -15 dB/decade (checked on
c,
R,

Table I to calculate the output phase noise of the PLL due to

our design PFD and CP circuit in 0.13 /Jm CMOS.
For Type II and Order 2 (no inductor in Fig. 12(a» the loop
filter transfer function can be written as [5] and [6]
(a) (b)
1 + s/wz
F(s) = KLP (11)
Fig. 12. Loop filter circuit for Type II and Order 3, with CP noise circuit.
s(1 + s/wp)
In (6), the first assumption is that, at frequencies below Where , KLP Nno= and a=1 for tristate PFD. And
K. Kv1cpa
=

the loop bandwidth, IH(J)I � 1. The second assumption is its value can be derived from CppSim system simulator and
here that the detector noise is dominated by the charge pump calculated value of KLP=1.6665EIO. Also, both the current
noise only, reference jitter and divider jitter are insignificant sources contribute equal noise current spectral density of
(Fig. 14). And the final assumption made here is that the 1.865E-12 A/Hz (Fig. 15). Modeling approach for finding the
charge pump noise magnitude of the positive and negative fractional-N PLL phase noise is shown in Fig. 14.
current sources are same. As the charge pump is not always
"on''', its noise power is not always present however before Phase noise of NOR, NAND and poposed PFD with proposed CP

the "off" state of the transistors there is noise deposited on the

capacitor formed by the loop filter and its output capacitance
(i.e: CL,tot) is (kT /CL,tot)/ fret. Where, fret is the input
reference frequency of the PLL. However, we have neglected
this effect in our calculation. Equation (6), can be modified
by the following equation depending on the duty cycle, which
depends on the reset time of the PFD circuit. For the worst case
4 5
10 10
condition, we will consider the D as 112, i.e: treset � Tre!
= Offset frequency (Hz)

and D
tTsd. Where, Tre! is the period of the reference
=
ref
Fig. 13. Phase noise of NOR, NAND and Proposed PFD with proposed CP
signal applied at the PFD circuit. switching circuit.
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

: ��
�, 540L --------'
--------- 1
�--------�
2

J
o
:tr-------, .. . .. . .. . . ·1
- 2 1
TIME X 10-
2
4

Fig. 18. Simulated synthesizer dynamics.

Fig. 14. Modelling approach for PLL phase noise analysis [5] .

I -- ouput noise current, 3.738-12 AlHzl

Output noise current of the CP
phase noise response compare to the NORINAND based PFD
topology with our proposed PFD and CP circuit. Also, to
get the current noise spectral density we have simulated the
proposed PFD and CP circuit in 0.13 J.lm CMOS (Fig. 15).
In Fig. 17, shows the almost equal phase noise response at 1
104 106
X 10- 19
Frequency (Hz) MHz offset frequency compare to the theoretical calculation
4�--�r=====c=======c=====��-'
1 -- output noise current, 0.1392 9-24 A2/Hzl as shown in Fig. 16. The resulting plot of the control voltage
is shown in Fig. 18. We checked the variation of phase noise
and changing of spurs levels due to the dc current offset of 3
J.lA at any of the UP/DN current branch and results are worsen
104 106 108
Frequency (Hz) compare to the Fig. 17 and also the effect of large offset dc
Fig. 15. Noise current of the proposed PFD-CP' current leads to fail the PLL to lock. Therefore, designing a
low current mismatch and a switching circuit to reduce the
charge injection error is very helpful to reduce the output
phase noise of the PLL due to the CP and PFD. In addition
we found that the phase noise response of our PFD and CP
circuits shows the better response (Fig. 13), that finally helps
to get the lower phase noise output of the PLL.

V. CONCLUSION

In this paper a high speed, low jitter, and fast acquisition

phase frequency detector (proposed PFD) has been designed
-
1
�':-
O
' ---"---'-"-'-'-'''';-
---"---'-'-'-'-''''"T. --'-..i...l.i.i..C"'-;---'-'-'--"
"'-"" for CP-PLL operating at 40 MHz. This PFD completely
FrequancyOtlset(Hz)

eliminates the missing edge and phase ambiguity problems

Fig. 16. Phase noise plot of the Type II and Order 2 Fractional-N PLL
(theoretical model). found in many PFDs and its jitter is lees compare to the
CppSim Simulated Phase Noise lorCell: manaS_lUI_', Lib: Synthesizer_Examples, Sim: test. par
NANDINOR based PFD topology. Finally using our PFD
and switching CP circuit, output PLL phase noise can be
reduced in a great extent compare to other design PFD and
CP topology.

REFERENCES

[I] Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2001.

IEEE Journal of Solid Slate Circuits, vol. 33, no. 2, pp. 295-299, February
[2] H. O. Johansson, "A Simple Precharge CMOS Phase Frequency Detector,"

1998.

Phase/Frequency Detectors," IEEE Trans. on Circuits and Systems-I:

[3] A. Homayoun and Behzad Razavi, "Analysis of Phase Noise in

,
regular papers, vol. 60, no. 3, pp. 529-539, March 2013.
[4] M. K. Hati and Tarun K. Bhattacharyya, "A High O/P Resistance, Wide
FrequencyOllsettromCarrier(MHz)

Fig. 17. Phase noise plot of the Type II and Order 2 Fractional-N PLL Swing and Perfect Current Matching Charge Pump having Switching
(simulation results, Sue2 model [5]). Circuit for PLL," Microelectronics Journal, vol. 44, pp. 649-657, August
2013.
[5] Michael H. Perrott, "PLL Design Using the PLL Design Assistant
IV. SIMULATION RESULT S Program," http://www-mtl.mit.edu/�perrott, April 2, 2005.
[6] Michael H. Perrott, "Fast and Accurate Behavioral Simulation of
Output phase noise response of the proposed PFD, NAND Fractional-N Synthesizers and other PLLlDLL Circuits," Design Automa­
based PFD and NOR based PFD topology with proposed tion Conference (DAC), 2002, pp. 498-503.
CP circuit has been shown in Fig. 13. It shows the better