A O.8ps Minimum-Resolution Sub-Exponent TDC For ADPLL in O.13Jlm CMOS

A O.
8ps Minimum-Resolution Sub-Exponent TDC for ADPLL in

O.13Jlm CMOS
Xiaolu Liu, Na Yan*, Xi Tan, Hao Min
State Key Lab. of ASIC and System, Dept. of M icroelectronics, Fudan University
Room 365, 825 Road Zhangheng, Shanghai, China 201203
* Email: yanna@fudan.edu.cn
Abstract
This
digitally
paper presents
the
design
of
sub-exponent
self-calibrated
time
amplifiers,
which
successively amplifies input time intervals and generates
time-to-digital converter (TDC) that amplifies a time
exponent value of fractional time difference. Section II
residue
describes the operating principle of
to
improve
both
the
time
resolution
and
proposed
TDC
measurement range. The sub-exponent TDC quantizes
structure. Section III shows the simulation results, and
the fractional time difference with a cascading chain of
Section IV summarized this work.
2x time amplifiers. A digitally self-calibrated TA circuit

is developed to achieve large input range and stable gain.
2.
Simulation results show that implemented in SM IC
A.
Circuit description
TDC architecture
O.13llm CMOS, the proposed TDC can achieve a
The block diagram of the proposed TDC architecture is
minimum resolution of 0.8ps, a measurement range of
shown in Fig 1. It consists of a front-end PFD, an integer
14bits, and a power dissipation of 2mW at 60M Hz.
TDC and a sub-exponent TDC. The front-end PFD is
Index Terms-Time-to-digital converter, all-digital PLL,
employed as frequency detector. The integer TDC is the
time amplifier
conventional 7 -bit TDC with one bit resolution equal to

fastest two-inverter delay (4050ps in O.13llm CMOS
1.
Introduction
IN
RECENT
process). The sub-exponent TDC quantizes the fractional

loop
time difference less than 1 LSB of integer TDC and
(ADPLL) in replacement of traditional analog PLL has
generates 7 -bit binary output with each bit representing

2
6
2' \ 2' , . . . ,2' of the two-inverter delay reference. With
years,
all-digital
phase-locked
been a leading drive in the development of frequency

advantages of improved
non-uniform quantizing steps, however, this non-linear
programmability, insensitivity to PVT variations, and
TDC can achieve the same performance as uniform
compact size by eliminating bulky analog elements such
linear
as charge pump and analog loop filter. To achieve jitter
ADPLL system. Since both the 7 -bit output of the
performance comparable to analog PLL, quantization
integer TDC and the 7 -bit output of the sub-exponent
synthesizer design,
for its
TDC,
according to behavioral
simulation
of
error should be sufficiently reduced by improving the
TDC come in binary format, they can be directly merged
resolution of time-to-digital converter (TDC), which is
to a 14-bit output. The phase information is filtered by
employed as phase detector by quantizing time intervals
the digital loop filter and then tunes the oscillating
between two rising edges to digital outputs.

Resolution of conventional delay-lined based TDC is
limited by process technology since
the
minimum
resolvable time quantity is proportional to one inverter

delay, which is about 20ps in O.13llm CMOS[ I ]. To
achieve better time resolution, Vernier delay line is
generally
considered.
Since
the
time
resolution
is
frequency of the DCO. For very small input, this

coarse-fine TDC architecture can improve the resolution
and measurement range simultaneously, resulting in a
fast lock time and low jitter for the ADPLL system.
fREF
fFB
PFO
IntegerTOC
\ 7(MSB)
determined by the difference between two inverter

delays, an excessive number of inverter stages are
required, causing long conversion time, large power
consumption and large area. Another approach is noise
shaping technique which can improve the effective
resolution in an error-feedback manner. However, since
.....
---+
\ 7(LSB)
SubExponent TOC
UP/ON
Figure 1. Block diagram of the proposed TDC
the noise shaping is base on first order delta-sigma

conversion
oversampling,
high
resolution
is
not
The circuit diagram of the sub-exponent TDC which
attainable for fast-varying input.
performs the fine conversion is shown in Fig.2. The
This paper presents a power-efficient sub-exponent TDC
input of the sub-exponent TDC is coupled to the output
with a minimum resolution of 0.8ps in 0.13!lffi CMOS
of the front-end PFD. The input time difference is
process. The proposed structure is based on a chain of
amplified by twice on each stage as propagated through
978-1-61284-193-9/11/$26.00
2011IEEE

-(
Pulse propagation
Jf
td
ff
2td
fl
:rtd
rtd
Arbiter
-----------
D6
D5
D3
D4
td>2r
D2
td>rr
td>rr
D1
DO
td>rr
td<rr
Figure 2. Proposed sub-exponent TDC architecture

the cascading chain of TA. The output of each TA stage
loses most of its control effect on the second transition
is coupled to an arbiter. The arbiter outputs ONE if the
faraway,
input time difference is larger than the two-inverter delay
showing a remarkable drop in gain from the ideal value
reference which is equal to the LSB of the integer TDC.
of two.
the
amount
of
delay
becomes
saturated,
With the XOR arrays, the outputs of the arbiters are

OUT+
converted into 7 bit l-of-n code. Since the two-inverter

delay
reference
corresponds
to 40 60ps
(here
OUT-
we
adjusted it to 50ps), which can be further estimated and

calibrated in the integer TDC according to the process
l
strength, output D6 to D l represent 25ps (=50psxT ) to
6
O.78125ps (=50psx2- ) respectively. The LSB DO covers
IN+
IN-
all input cases below O.78125ps, resulting in a minimum

resolution of O.8ps (approximation of O.78125ps).
B.
Time amplifier
Fig.3 shows the principle of the 2x time amplifier

proposed
in
this
work.
AlB
nodes
are
initially
pre-charged to high when both inputs are low. When

rising edges of the inputs are applied, AlB nodes start
Dependent discharging paths
discharging. Note that the discharging of each side is
Figure 3. Circuit diagram of basic 2x TA
performed by two pull-down paths, a fixed inverter

driven path, by M l and M3, and a dependent path, by
M2 and M4. The discharging strength of one dependent
path is determined by the discharging status of the
counterpart node, as a result the first rising transition
makes the second transition slower by reducing the
discharging strength of the counterpart node, reflected as
a time interval gain in output. When M l, M2, M3 and
M4 are of identical WfL,
the
first discharging is
performed by two identical pull-down paths, while the

second discharging is performed by only one fixed
pull-down path at the end of the transition, given that the
first discharged node shuts down the second dependent
path. So the TA generates a gain of roughly 2 for small
input. For large input, however, as the first transition
C.
Self-calibration circuit
Since the TA used in this design must have a relative

stable gain and a linear input range large enough to cover
the
reference
delay
(Td=50ps)
of
the
arbiter.
self-calibrated TA circuit is proposed in Fig.4, replacing

the initial fixed discharging path with another dependent
path. Similar to M2 and M4, the strengths of M l and M3
are controlled by the counterpart input node; however,
the PMOS diodes give C/D nodes a slow discharging and
guarantee M l and M3 are not completely turning off so
that AlB nodes can be fully discharged to ground. The
size of the PMOS diodes in the replica TA is digitally
calibrated, tuning the TA gain in cascading chain.
OUT+
N
At2 = r
OUT
(1)
One bit error occurs when the amplified result equals 2.

Assuming single stage gain error is E, the requirement
for less than one-bit error can be derived as
(2)
At 2N(1+&,)N < 2r
By substituting (1) and (2), the requirement of single
stage gain error for less than one-bit can be derived as
I
(3)
&' <N
(3) is greatly released than
&' < 1/ 2
in traditional
pipeline ADC, therefore easier to achieve high linearity

with the proposed open-loop time amplifier.
3. Simulation Results
The proposed sub-exponent TDC is implemented in
SM IC O.13!lm CMOS process. Simulation results show
that it can achieve a minimum resolution of O.8ps. The
stage-to-stage delay is sufficiently small so that high
conversion rate of TDC is ensured.
Figure 4. Circuit of proposed self-calibrated TA

With TA input of reference delay and output alignment
of two reference delay, the PD generates calibration
infonnation. Since the input difference of PD is rather
small
when
the
gain
successively
approaches
2,
conventional flip-flops such as the sense-amplifier-based

flip-flop cannot be used. Fig. 5 shows the proposed PD
used in this work because it has equal delay from its two
inputs, start and stop, to the outputs. [2]
The simulated TA gain with/without calibration is shown

in Fig.6. Without calibration, a remarkable drop in TA
gain is seen as predicted, while the proposed calibration
scheme achieves a high linearity for a wide input range
of 50ps. The one-point calibration slightly increased the
gain at small input, but the gain error in the small input
range don't degrade the whole linearity much because of
the non-unifonn sub-exponential characteristic of
the
proposed TDC.
::J
40
.s8 20
00
=: j
j
10
15
20
25
30
35
Input time difference [ps]
40
45
50
2.5 ,----r--,---,----.,--,
2.25
___
,
1.50
uncalibrated
-calibrated
10
. ........ ... .......

15
20
25
30
35
40
45
Input time difference [ps]
.J
50
Figure 6. Simulation of TA transfer cure and gain

Figure 5. Circuit of proposed PD
Compared to pipeline ADC using cascaded amplifiers,
the proposed sub-exponent TDC has better linearity
perfonnance with different
gain error accumulation
mechanisms. In ideal case with no gain error, an input

time difference of At results an output of. after N stages
of amplification, denoted as
The transfer characteristic of the SUb-exponent TDC is

shown in Fig.7 , the ideal transfer curve is also shown for
reference. To estimate the linearity for the exponent
output, the difference in time step between the simulated
and ideal curves is nonnalized to corresponding each-bit
resolution and is denoted by nonnalized differential error
(NDE); the difference in code transition time between
the simulated and ideal curves is nonnalized and is
denoted by normalized absolute error (NAE)[3]. Fig.8

shows
the
simulated
linearity
performance
of
the
sub-exponent TDC.
Considering the degradation of measured performance

compared with simulation results, this work is still very
alluring because this non-uniform sub-exponent structure
can achieve the same jitter performance as uniform
linear TDC of the same minimum resolution, when
adaptively resolve the phase error in ADPLL. It greatly
64
---- target
relieves the challenging design issues of high-resolution
-simulated
TDC, especially in terms of linearity.
48
"
Acknowledgments
32
and
2009ZXO I 031-003-002
Q)
o
U
This work is supported by Important National Science
:;
Technology
Specific
&
Projects
of
China
(no.
no.20 I OZX03001-004-0 I )
and National Natural Science Foundation of China (no.
'IF
0
61076028).
References
u
Input Time Difference [ps]
[ I ] R. B. Staszewski et aI., "1.3V 20ps time-to-digital

converters for frequency synthesis in 90-nm CMOS,"
Figure 7. Simulated TDC transfer characteristic
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 3,
pp. 220-224 (2006).
[2] M injae Lee and Asad A. Abidi, "A 9b, l.25ps
Resolution Coarse-Fine Time-to-Digital Converter in
90nm CMOS that Amplifies a Time Residue", JSSC, vol.
43, no. 4 (2008).
[3] Seon-Kyoo Lee, Young-Hun Seo, Hong-June Park,
"A I GHz ADPLL with a 1.25ps M inimum-Resolution
Sub-Exponent TDC in 0.18 urn CMOS", JSSC, vol. 45,
05
O.25
: : ----3
:
no. 12 (2010).
[4] J. Yu et aI., "A 12-bit vernier ring time-to-digital
--
-0.25
-{l.5
Output Code
1.
32
converter in O.BJ.lm CMOS technology," in IEEE Symp.
64
Figure 8. Simulated TDC linearity performance

4.
Summary
'Iable I TDC perfiormance comparIson
Scheme
Yu [4]
Straayer [5]
This work
VLSI'09
JSSC'09
(Simulated)
Vernier
Noise
Sub-
shaping
exponent
Voltage
l.5V
I .5V
1.2V
Technology
BOnm
BOnm
BOnm
Resolution
8ps
l.2ps
0.8ps
Range
12bit
Ubit
14bit
INLIDNL
I LSB
NA
OAb
7.5mW
31.5mW
2mW
@15M
@50M
@60M
Power
The performance comparison show that this proposed

sub-exponent TDC can achieve a fine resolution and
large measurement range. It is also very power efficient.
VLSI Circuits Dig., pp. 232-233 (2009).

[5] M . Z. Straayer et aI., "An efficient high-resolution
I I -bit
noise-shaping
multipath
gated
ring oscillator
TDC," in IEEE Symp. VLSI Circuits Dig., pp. 82-83

(2008).

A O.8ps Minimum-Resolution Sub-Exponent TDC For ADPLL in O.13Jlm CMOS

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A O.

8ps Minimum-Resolution Sub-Exponent TDC for ADPLL in

successively amplifies input time intervals and generates

time-to-digital converter (TDC) that amplifies a time

exponent value of fractional time difference. Section II

describes the operating principle of

measurement range. The sub-exponent TDC quantizes

structure. Section III shows the simulation results, and

the fractional time difference with a cascading chain of

Section IV summarized this work.

2x time amplifiers. A digitally self-calibrated TA circuit

Simulation results show that implemented in SM IC

O.13llm CMOS, the proposed TDC can achieve a

The block diagram of the proposed TDC architecture is

minimum resolution of 0.8ps, a measurement range of

shown in Fig 1. It consists of a front-end PFD, an integer

14bits, and a power dissipation of 2mW at 60M Hz.

TDC and a sub-exponent TDC. The front-end PFD is

Index Terms-Time-to-digital converter, all-digital PLL,

employed as frequency detector. The integer TDC is the

conventional 7 -bit TDC with one bit resolution equal to

process). The sub-exponent TDC quantizes the fractional

time difference less than 1 LSB of integer TDC and

(ADPLL) in replacement of traditional analog PLL has

generates 7 -bit binary output with each bit representing

been a leading drive in the development of frequency

non-uniform quantizing steps, however, this non-linear

programmability, insensitivity to PVT variations, and

TDC can achieve the same performance as uniform

compact size by eliminating bulky analog elements such

as charge pump and analog loop filter. To achieve jitter

ADPLL system. Since both the 7 -bit output of the

performance comparable to analog PLL, quantization

integer TDC and the 7 -bit output of the sub-exponent

error should be sufficiently reduced by improving the

TDC come in binary format, they can be directly merged

resolution of time-to-digital converter (TDC), which is

to a 14-bit output. The phase information is filtered by

employed as phase detector by quantizing time intervals

the digital loop filter and then tunes the oscillating

between two rising edges to digital outputs.

resolvable time quantity is proportional to one inverter

frequency of the DCO. For very small input, this

determined by the difference between two inverter

Figure 1. Block diagram of the proposed TDC

the noise shaping is base on first order delta-sigma

The circuit diagram of the sub-exponent TDC which

attainable for fast-varying input.

performs the fine conversion is shown in Fig.2. The

This paper presents a power-efficient sub-exponent TDC

input of the sub-exponent TDC is coupled to the output

with a minimum resolution of 0.8ps in 0.13!lffi CMOS

of the front-end PFD. The input time difference is

process. The proposed structure is based on a chain of

amplified by twice on each stage as propagated through

Figure 2. Proposed sub-exponent TDC architecture

loses most of its control effect on the second transition

is coupled to an arbiter. The arbiter outputs ONE if the