Instruction Format

The instruction format is depicted in a rectangular box, symbolizing the instruction bits in
memory words or a control register. The bits grouped are divided into three parts:

1. Addressing Mode: The addressing mode indicates how the data is represented.
2. Opcode: The opcode part indicates the operation type on the data.
3. Operand: The operand part indicates either the data or the address of the data.

A computer performs a task based on the instruction provided. Instruction in computers

comprises groups called fields. These fields contain different information as for computers
everything is in 0 and 1 so each field has different significance based on which a CPU decides
what to perform.
Instruction is of variable length depending upon the number of addresses it contains.
Generally, CPU organization is of three types based on the number of address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization

Single Accumulator Organization

All the operations on a system are performed with an implied accumulator register. The
instruction format in this type of computer uses one address field.
For example, the instruction for arithmetic addition is defined by an assembly language
instruction ‘ADD.’
Where X is the operand’s address, the ADD instruction results in the operation.
AC ← AC + M*X+.
AC is the accumulator register, M[X] symbolizes the memory word located at address

General Register Organization

The general register type computers employ two or three address fields in their instruction
format. Each address field specifies a processor register or a memory. An instruction
symbolized by ADD R1, X specifies the operation R1 ← R + M *X+.
This instruction has two address fields: register R1 and memory address X.

Stack Organization
A computer with a stack organization has PUSH and POP instructions that require an address
field. Hence, the instruction PUSH X pushes the word at address X to the top of the stack. The
stack pointer updates automatically. In stack-organized computers, the operation type
instructions don’t require an address field as the operation is performed on the two items on
the top of the stack.

Types of Instruction Formats

1. Three address instruction
2. Two address instruction
3. One address instruction
4. Zero address instruction

Three Address Instruction

The format of a three address instruction requires three operand fields. These three fields can
be either memory addresses or registers.

Example: The program in assembly language X = (A + B) ∗ (C + D) Consider the instructions given

below that explain each instruction's register transfer operation.

ADD R1, A, B R1 ← M *A+ + M *B+

ADD R2, C, D R2 ← M *C+ + M *D+
MUL X, R1, R2 M *X+ ← R1 ∗ R2

Two processor registers, R1 and R2.

The symbol M [A] denotes the operand at memory address symbolized by A. The operand1 and
operand2 contain the data or address that the CPU will operate. Operand 3 contains the
result’s address.

Two Address Instructions

This instruction is most commonly used in commercial computers. This address instruction
format has three operand fields. The two address fields can either be memory addresses or
registers.
Example: The program to evaluate X = (A + B) ∗ (C + D) is as follows:

MOV R1, A R1 ← M *A+

ADD R1, B R1 ← R1 + M *B+
MOV R2, C R2 ← M *C+
ADD R2, D R2 ← R2 + M *D+
MUL R1, R2 R1 ← R1∗R2
MOV X, R1 M *X+ ← R1

The MOV instruction transfers the operands to the memory from the processor registers. R1,
R2 registers.

One Address Instruction

This instruction uses an implied accumulator for data manipulation operations. An accumulator
is a register used by the CPU to perform logical operations. In one address instruction, the
accumulator is implied, and hence, it does not require an explicit reference. For multiplication
and division, there is a need for a second register. However, here we will neglect the second
register and assume that the accumulator contains the result of all the operations.

Example: The program to evaluate X = (A + B) ∗ (C + D) is as follows:

LOAD A AC ← M *A+
ADD B AC ← A *C+ + M *B+
STORE T M *T+ ← AC
LOAD C AC ← M *C+
ADD D AC ← AC + M *D+
MUL T AC ← AC ∗ M [T]
STORE X M *X+ ← AC

All operations are done between the accumulator(AC) register and a memory operand.
M[ ] is any memory location.
M[T] addresses a temporary memory location for storing the intermediate result.
This instruction format has only one operand field. This address field uses two special
instructions to perform data transfer, namely:
 LOAD: This is used to transfer the data to the accumulator.
 STORE: This is used to move the data from the accumulator to the memory.

Zero Address Instruction

This instruction does not have an operand field, and the location of operands is implicitly
represented. The stack-organized computer system supports these instructions. To evaluate the
arithmetic expression, it is required to convert it into reverse polish notation.

Example: Consider the below operations, which shows how X = (A + B) ∗ (C + D) expression will
be written for a stack-organized computer.

TOS: Top of the Stack

PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) ∗ (A + B)
POP X M *X+ ← TOS
RISC Processor
RISC stands for Reduced Instruction Set Computer Processor, microprocessor
architecture with a simple collection and highly customized set of instructions. It is built
to minimize the instruction execution time by optimizing and limiting the number of
instructions. It means each instruction cycle requires only one clock cycle, and each cycle
contains three parameters: fetch, decode and execute. The RISC processor is also used
to perform various complex instructions by combining them into simpler ones. RISC
chips require several transistors, making it cheaper to design and reduce the execution
time for instruction.

Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC processors,
RISC-V.

Advantages of RISC Processor

1. The RISC processor's performance is better due to the simple and limited number
of the instruction set.
2. It requires several transistors that make it cheaper to design.
3. RISC allows the instruction to use free space on a microprocessor because of its
simplicity.
4. RISC processor is simpler than a CISC processor because of its simple and quick
design, and it can complete its work in one clock cycle.

Disadvantages of RISC Processor

1. The RISC processor's performance may vary according to the code executed
because subsequent instructions may depend on the previous instruction for
their execution in a cycle.
2. Programmers and compilers often use complex instructions.
3. RISC processors require very fast memory to save various instructions that require
a large collection of cache memory to respond to the instruction in a short time.

RISC Architecture
It is a highly customized set of instructions used in portable devices due to system
reliability such as Apple iPod, mobiles/smartphones, Nintendo DS,
Features of RISC Processor
Some important features of RISC processors are:

1. One cycle execution time: For executing each instruction in a computer, the
RISC processors require one CPI (Clock per cycle). And each CPI includes the
fetch, decode and execute method applied in computer instruction.
2. Pipelining technique: The pipelining technique is used in the RISC processors to
execute multiple parts or stages of instructions to perform more efficiently.
3. A large number of registers: RISC processors are optimized with multiple
registers that can be used to store instruction and quickly respond to the
computer and minimize interaction with computer memory.
4. It supports a simple addressing mode and fixed length of instruction for
executing the pipeline.
5. It uses LOAD and STORE instruction to access the memory location.
6. Simple and limited instruction reduces the execution time of a process in a RISC.
CISC Processor
The CISC Stands for Complex Instruction Set Computer, developed by the Intel. It has
a large collection of complex instructions that range from simple to very complex and
specialized in the assembly language level, which takes a long time to execute the
instructions. So, CISC approaches reducing the number of instruction on each program
and ignoring the number of cycles per instruction. It emphasizes to build complex
instructions directly in the hardware because the hardware is always faster than
software. However, CISC chips are relatively slower as compared to RISC chips but use
little instruction than RISC. Examples of CISC processors are VAX, AMD, Intel x86 and the
System/360.

Characteristics of CISC Processor

Following are the main characteristics of the RISC processor:

1. The length of the code is shorts, so it requires very little RAM.

2. CISC or complex instructions may take longer than a single clock cycle to execute
the code.
3. Less instruction is needed to write an application.
4. It provides easier programming in assembly language.
5. Support for complex data structure and easy compilation of high-level languages.
6. It is composed of fewer registers and more addressing nodes, typically 5 to 20.
7. Instructions can be larger than a single word.
8. It emphasizes the building of instruction on hardware because it is faster to
create than the software.

CISC Processors Architecture

The CISC architecture helps reduce program code by embedding multiple operations on
each program instruction, which makes the CISC processor more complex. The CISC
architecture-based computer is designed to decrease memory costs because large
programs or instruction required large memory space to store the data, thus increasing
the memory requirement, and a large collection of memory increases the memory cost,
which makes them more expensive.
Advantages of CISC Processors

1. The compiler requires little effort to translate high-level programs or statement

languages into assembly or machine language in CISC processors.
2. The code length is quite short, which minimizes the memory requirement.
3. To store the instruction on each CISC, it requires very less RAM.
4. Execution of a single instruction requires several low-level tasks.
5. CISC creates a process to manage power usage that adjusts clock speed and
voltage.
6. It uses fewer instructions set to perform the same instruction as the RISC.

Disadvantages of CISC Processors

1. CISC chips are slower than RSIC chips to execute per instruction cycle on each
program.
2. The performance of the machine decreases due to the slowness of the clock
speed.
3. Executing the pipeline in the CISC processor makes it complicated to use.
 4. The CISC chips require more transistors as compared to RISC design.
5. In CISC it uses only 20% of existing instructions in a programming event.

Difference between the RISC and CISC Processors

RISC CISC

It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.

It emphasizes on software to optimize the It emphasizes on hardware to optimize

instruction set. the instruction set.

It is a hard wired unit of programming in the Microprogramming unit in CISC

RISC Processor. Processor.

It requires multiple register sets to store the It requires a single register set to store
instruction. the instruction.

RISC has simple decoding of instruction. CISC has complex decoding of

instruction.

Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.

It uses a limited number of instruction that It uses a large number of instruction that
requires less time to execute the instructions. requires more time to execute the
instructions.

It uses LOAD and STORE that are independent It uses LOAD and STORE instruction in
instructions in the register-to-register a the memory-to-memory interaction of a
program's interaction. program.

RISC has more transistors on memory registers. CISC has transistors to store complex
instructions.

The execution time of RISC is very short. The execution time of CISC is longer.

RISC architecture can be used with high-end CISC architecture can be used with low-
applications like telecommunication, image end applications like home automation,
processing, video processing, etc. security system, etc.

It has fixed format instruction. It has variable format instruction.

The program written for RISC architecture Program written for CISC architecture
needs to take more space in memory. tends to take less space in memory.

Example of RISC: ARM, PA-RISC, Power Examples of CISC: VAX, Motorola 68000
Architecture, Alpha, AVR, ARC and the SPARC. family, System/360, AMD and the Intel
x86 CPUs.