3D-IC TESTING WITH THE MENTOR GRAPHICS TESSENT PLATFORM

STEVE PATERAS, MENTOR GRAPHICS APRIL 2011

S A N D Y I E

I L

L D

C A

O N N A L

T E Y S

S I

T S

w w w . m e n t o r . c o m

W H I T E

P A P E R

3D-IC Testing with the Mentor Graphics Tessent Platform

CONTENTS
Introduction ......................................................................................................................................................................... 2 Known Good Die Requirements Before Packaging ................................................................................................. 2 Die and Interconnect Test Challenges After Packaging ......................................................................................... 4 Example Testing an SOC Containing Stacked Memory and Logic Die .......................................................... 5 Summary ............................................................................................................................................................................... 7 References............................................................................................................................................................................. 7

www.mentor.com/silicon-yield

3D-IC Testing with the Mentor Graphics Tessent Platform

INTRODUCTION
Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moores Law. Current integration and interconnect methods include wirebond and flipchip and have been in production for some time. 3D chips connected via interposers are expected to go into production in 2011 or 2012 at Xilinx, Samsung, IBM, and Sematech [1]. Interposers are providing the logical first step to industrialization of 3D based on through-silicon vias (TSV)s. The next generation of 3D integration incorporates TSV technology as the primary method of interconnect between the die. [2] The migration to 3D-ICs connected by TSVs presents three new test challenges to the industry (Figure 1): 1. The escape rate of defective die at wafer test must be lower to meet a target postpackaging yield; that is, known good die (KGD) requirements must be met first. 2. The bottom die is the only one with external test I/O access in a 3D-IC so there must be a way to deliver test patterns to the upper die in a packaged stack. 3. The test strategy must include a way to test interconnects between the stacked die.

Figure 1. The three main challenges of 3D-IC testing: requirement for higher Known Good Die (KGD); test access after packaging; testing the inter-die connections.

This white paper will specifically address these challenges.

KNOWN GOOD DIE REQUIREMENTS BEFORE PACKAGING

In the traditional single die IC manufacturing process, most of the defective die are eliminated during wafer test. However, wafer testing is inherently limited by the number of probes that can be used to apply stimuli and measure responses of the die on a wafer. Limitations in access to power and ground rails can also limit the ability to apply tests at the full target speed of the device. Because of the cost of overcoming these inherent wafer test limitations, the historic approach has been to allow some test escapes at the wafer level and to catch these during package test. In a single die-per-package flow, the final packaged yield depends on the defects that escape wafer testing and new defects that are introduced in the packaging process. In the 3D package flow, the escape rate at wafer test has a much larger impact on final packaged device yield. This is because a defective die, when packaged with good die, will
www.mentor.com/silicon-yield 2

3D-IC Testing with the Mentor Graphics Tessent Platform

result in a failure of the entire package. This combinational effect means the impact of wafer escapes is magnified exponentially in the final product, adversely affecting package yield. In addition, the cost of defects after packaging is higher because there is more value bound up in a 3D package (see figure 2). Because of these two reinforcing effectsincreasing probability of a package failure as the wafer test escape rate increases, and higher cost of the packaged work in progressthere is a higher KGD, i.e., higher test quality, requirement at wafer test for die intended for multi-die packaging. To achieve higher test quality at wafer sort, engineers need test patterns that will achieve higher fault coverage. They may also need to introduce additional fault models to test for defects that are normally ignored at wafer testthis further expands test pattern size. Of course, an increase in test quality can also lead to longer, more expensive tests.

Figure 2: Test flows for packages with a single die (left), and for 3D packages with multiple die.

The KGD challenge of 3D-IC testing is directly addressed by the Mentor Graphics Tessent test technology: Support for advanced fault models, including at-speed testing, in addition to normal stuck-at and bridge testing. The industrys highest test pattern compression, which enables higher test coverage while lowering the cost of test by reducing tester memory requirements and test time. Hierarchical test capability, which simplifies test development and debugging, reduces test time, and allows high coverage even for complex chips that might be limited by I/O pin count, routing congestion, or, in the case of 3D-ICs, inter-die test paths. Integration of automatic test pattern generation (ATPG) and built-in self test (BIST) techniques to achieve highest coverage at the lowest cost.

Figure 3: Tessent silicon test platform.

www.mentor.com/silicon-yield

3D-IC Testing with the Mentor Graphics Tessent Platform

Tessent TestKompress provides automated RTL-level test control logic insertion, including test pattern compression and decompression elements, and advanced automatic test pattern generation (ATPG) that creates the compressed test patterns, which are applied to the device under test using automatic test equipment To further increase the quality of test and reduce the cost, Mentor delivers a combination of additional embedded test technologies that complement high compression deterministic scan chain testing: The Tessent LogicBIST product generates self test logic that enables hierarchical atspeed testing of internal logic using random patterns that provide a targeted level of test coverage at full rated clock speed. The Tessent BoundaryScan test product generates test logic and patterns to ensure efficient, high quality testing of all I/O circuits, including at-speed tests and leakage tests. The Tessent MemoryBIST product inserts test logic to enable self test of embedded memory with very high coverage and reduced test times. The product can also provide automated repair based on test results. Test patterns can be reprogrammed at any time before or after the device is manufactured. Tessent PLLTest provides self-test logic that enables high precision testing of embedded phase lock loops which control internal chip timing. Tessent SerdesTest provides testing of high speed serial I/O including precise measurement of jitter with sub-picosecond accuracy.

All of these products and technologies work together in the Mentor test flow and ensure comprehensive wafer-level and pre-package testing of each individual die, no matter how complex the functionality

DIE AND INTERCONNECT TEST CHALLENGES AFTER PACKAGING

Beyond the test requirements for individual die, 3D-IC stacks have additional unique test challenges at final test, that is, after the die has been packaged. Each of the die must be re-tested to make sure they remain fully functional. Test access becomes a significant problem because the bottom die is the only one with direct access pins. Post-packaging test may be the first time that full at-speed testing can be performed to ensure the system meets performance requirements. This is due to the wafer test limitations mentioned before. Post-package testing is also the first opportunity to test all the TSV or interposer connections between die for proper connectivity and at-speed performance. For processor and memory stacks, the memory bus interface logic must also be tested at full speed. Consider the standard test access points defined by the IEEE 1149.1 standard. These include a test mode input, test data input and output ports, and a test clock input. In addition, a number of scan data in and scan data out ports are added for the application of scan test patterns. In a bare die, these are all accessible by design. In a single die packaged part, the same test access points are typically brought out to the package I/O pads.

www.mentor.com/silicon-yield

3D-IC Testing with the Mentor Graphics Tessent Platform

However, in a stacked die package, there is only direct access to test access points on the bottom die. To address this, IMEC (the European microelectronics research center) has proposed extensions to the IEEE 1149.1 test architecture standard to allow application of tests in multi-die stacks using test elevators, or TSVs that are dedicated to provide a test access path through the die. The resulting TSV-based 3D test architecture also requires methods to insert bypass logic enabling test patterns to be routed through the stack, and methods to re-sequence and re-time the patterns as appropriate for the extended scan chain paths. The IMEC extensions provide access to all design for test (DFT) resources on all the die in a 3D stack, such as scan chains and test control logic, as well as access to controls for BIST elements. The architecture also allows simultaneous access to resources on multiple die to enable test interactions across the die, in particular TSV interconnect testing, and to enable parallel testing for reduced overall test time. The Tessent tool suite provides support for implementing the IMEC extensions, allowing unique 3D-IC architectural elements to be added using integrated scripting facilities. Tessent ATPG and BIST test products work together to enable comprehensive and cost effective 3D-IC testing with full re-use of die-level tests to minimize test development effort and to enable parallel testing to increase test throughput.

Figure 4. Extensions to the IEEE 1149.1 test architecture standard proposed by IMEC define test elevators, i.e., TSVs dedicated to carrying test information between die.

EXAMPLE TESTING A 3D SOC CONTAINING STACKED MEMORY AND LOGIC DIE

Lets look at an example of how the Tessent test products work together to provide comprehensive, economical testing of advanced 3D-ICs by employing a combination of compressed ATPG and BIST technologies. Figures 5 and 6 show a typical 3D system on chip (SoC) with two logic die and a DRAM die packaged together as a stack, and connected via TSVs. Tessent MemoryBIST is used to create the BIST logic to fully test the DRAM. Note that the MBIST control logic is on the logic chip. This maximizes the real estate available for
www.mentor.com/silicon-yield 5

3D-IC Testing with the Mentor Graphics Tessent Platform

memory cells on the DRAM, and allows at-speed testing of the memory bus logic and connecting TSVs. Tessent MemoryBIST supports post-silicon reprogramming of the BIST patterns to accommodate changes in the memory die, or variant stacks that use different memory designs. Tessent MemoryBIST also supports shared bus configurations where multiple memory die are connected to a processor core on the logic die via the same electrical interconnects, for example, a TSV extending through multiple memory die

Figure 5. Using Tessent MemoryBIST to test the memory die in a 3D stack.

All the bare (single) die BIST and ATPG compression (scan chain) tests can be re-used, saving test development time. The Tessent solution re-sequences the test patterns as required to ensure correct pattern distribution and application across multiple die. They also generate appropriate control patterns to manage bypass logic and to retime the patterns to allow for the inherently greater pattern propagation delay across multiple die.

Figure 6. Using Tessent solutions to re-test multiple die in a 3D stack.

All the test resources are accessed through a standard IEEE 1149.1 test access port (TAP) interface with inter-chip transfer of test signals provided by dedicated test elevator TSVs. The test architecture supports performing tests on multiple die in parallel to reduce test time.

www.mentor.com/silicon-yield

3D-IC Testing with the Mentor Graphics Tessent Platform

To fully test TSV connections between logic portions of two die, Tessent FastScan and Tessent SoCScan work together to implement a hierarchical test approach. Figure 7 illustrates how scan chain test patterns on one die can be used to provide stimuli and capture results from another die, thereby testing the integrity of interface logic and TSV connections. All test data is applied through package connections on the bottom dieno connections to upper stacked die are required. Generation of test patterns and controls are fully automated by the Tessent suite.

Figure 7: Using Tessent solutions to test logic to logic TSV interconnect

SUMMARY
Mentors Tessent test solution addresses the three main challenges of 3D-IC testing: The need for higher KGD test quality to ensure acceptable package yield The ability to enable comprehensive testing of all die within a packaged stack The ability to test all die interconnects after packaging

By using a combination of hierarchical test architecture, high compression scan testing and BIST technologies, the Mentor Graphics Tessent solution provides the highest quality and most economical 3D-IC testing available.

REFERENCES
1. Francoise von Trapp, 3D: Youve Come a Long Way, Baby! Chip Scale Review, Jan/Feb 2011, http://www.chipscalereview.com/issues/0111/content/CSR_Jan-Feb-2011_digital.pdf 2. 3D-IC Standards Key to TSV Adoption, Semiconductor Manufacturing & Design Community, February 22, 2011, http://semimd.com/semi/2011/02/22/hello-world/ .

www.mentor.com/silicon-yield

3D-IC Testing with the Mentor Graphics Tessent Platform

For the latest product information, call us or visit:

w w w . m e n t o r . c o m

2010 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned are this document are trademarks of their respective owners.
Corporate Headquarters Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville OR 97070-7777 Phone: 503.685.7000 Fax: 503.685.1204 Sales and Product Information Phone: 800.547.3000 Silicon Vally Mentor Graphics Corporation 1001 Ridder Park Drive San Jose, California 95131 USA Phone: 408.436.1500 Fax: 408.436.1501 North American Support Center Phone: 800.547.4303 Europe Mentor Graphics Deutschland GmbH Amulfstrasse 201 80634 Munich Phone: +49.89.57096.0 Fax: +49.89.57096.400 Pacific Rim Mentor Graphics(Taiwan) Room 1001, 10F International Trade Building No. 333, Section 1, Keelung Road Phone: 886.2.87252000 Fax: 886.2.27576027 Japan Mentor Graphics Japan Co Ltd Gotenyama Garden 7-35, Kita-shinagawa 4-chrome Shinagawa-Ku, Tokyo 140-0001 Japan Phone: 81.3.5488.3033 Fax: 81.3.5488.3004 EventID