Pression

Tessent: Scan and ATPG
Module 9
Compression Techniques
Objectives
Upon completion of this module, you will be able to:
 Explain what ATPG compression is.

 Explain what EDT compression is.
 Describe when you would use ATPG compression techniques.
 Describe when you would use EDT compression techniques.

 Perform EDT compression.
 Perform the default Tessent TestKompress compression flow.
9-2 • Tessent: Scan and ATPG: Compression Techniques Copyright © 1999-2009 Mentor Graphics Corporation
Understanding the ATPG Process
1. Target faults
2. Generate test cube: 1-5%
3. Random fill: 99-95%
4. Stimuli on ATE 5. Response on ATE
Standard Test Application Process
2. CAPTURE
Scan flops
1. SHIFT IN capture
Stimuli responses
loaded
from ATE
to internal
scan chains
3. SHIFT OUT
(20 channels) Responses
shifted to
ATE
Stimuli
Stimuli ATE Response
Response (20 channels)
ATPG-Based Compression Techniques
 Standard techniques
 Static compression
 Dynamic compression
 Newer and more advanced ATPG approaches
 Multi-clock compression
 Domain analysis
 Algorithm enhancements
 Optimized pattern ordering
Static Compression
 Often not necessary but might help.
 Delete redundant patterns.
 Reverse and random-order fault simulation.
 Pattern count reduction is circuit dependent.
Dynamic Compression
 Standard part of ATPG.
 Several faults targeted per pattern.
 Pattern count reduction is circuit dependent (2x – 10x).
 Increased runtime.
Target Testcube Test Pattern Fault Sim
Multiple Clock Capture Per Pattern
 Lower pattern count, increased ATPG runtime

 Sequential fault simulation
 Up to 60% additional compression on designs with multiple clocks
Clock Domain Analysis and Clock Merging
Shift Capture Shift
C1 C2
C1
Scan C3
Chains SE
C1 C2 C3
Merged
Clock
Pattern
 Automatic in ATPG Expert

 Merging non-interacting clock domains
 Allows several clocks to be targeted at once
 Reduces tester clock requirements
 More efficient pattern generation
 Better compression (typically 20% additional)
ATPG Create Patterns Command
 ATPG CREate PAtterns command automatically performs:
 Quick AU analysis
 Dynamic compression
 Multi clock compression
(if depth >1)
 Static compression
 Basic pattern optimization
ATPG Create Patterns Command (Cont.)
 Automatically reach higher test coverage with fewer patterns.

 Access ATPG expertise with
a single command.
 Optimizes coverage and pattern count within shortest run
time.
 Up-front analysis of design to address:
 RAM shadow logic Compression
 Sequential depth Clock interactions
 Abort limit Contention
 Monitors progress, learns, and adjusts during run.
 Iterative passes target more aggressive solutions.
Balanced Scan Chains
 Reducing Test Time
Balanced
Scan Chains 10
Finished Finished
Shift Time
Unbalanced 10
Scan Chains
Short Scan Chains
 Reducing Test Time
Short 20
Scan Chains
Finished Finished
Shift Time
Long 10
Scan Chains
Embedded Deterministic Test (EDT)
 EDT is the technology behind Tessent TestKompress.
 Based on standard scan with ATPG.
D
D
 Deterministic pattern generation. E
E
CC
C
C
 Requires onboard test logic: O
O
O
O
M
M
M
M
 Decompressor P
P
P
A
P
A
R
R
 Compactor E
E
CC
TT
S
S
 Bypass (Optional) S
S
O
O
RR
O
O
 Reduces test data volume. R
R
 Reduces test application time.

 Logic only added to scan chain I/O.
Compressed
Compressed
Stimuli
Stimuli ATE Compacted
Compacted
Responses
Responses
Basic Terminology
Core
D
D
E
E
CC
C
C
O
O
O
O
M
M
M
M
PP
P
P
AA
R
R
CC
E
E
TT
S
S
O
O
S
S
RR
O
O
Scan Channels R
R
(External)
Scan Chains
(Internal)
Data Volume and Test Application Time
Data Volume = L x W x H
H
No. of Scan Channels
W No. of Patterns
L
Length of Longest Scan Chains
Test Cycles = L x W Test Time = (L x W) / Frequency
EDT Reduces Test Data Volume and Application Time
Standard ATPG
H
L
EDT
EDT appears to the tester as

much shorter scan chains.
H
Decompressor Compactor
L
ATPG With EDT
4. Pseudorandom fill
D
D
E
E CC
C
C O
O
O
O M
M
M
M PP
P
P AA
R
R CC
E
E
3. Calculate S
S
TT
O
O
5. Calculate
S
S
stimuli O
O
RR response
R
R
1. Target faults
2. Generate test cube
EDT Test Application Process
2. CAPTURE
SHIFT IN D
D Scan flops
E
E
Compressed C
C
CC capture
O
O
stimuli shifted O
O
M
M responses
M
M
through P
P
PP (20 chains)
AA
decompressor R
R
CC
E
E
(2 channels) S
S
TT
S
S
O
O 3. SHIFT OUT
RR
Random fill
O
O Responses
R
R
added to stimuli compacted
inside during shift
decompressor to ATE
(20 chains) through
Compressed Compacted compactor
Compressed
Stimuli
Stimuli
ATE Compacted
Responses
Responses (2 channels)
NOTE: Data is loaded cycle-by-cycle.

Example Results of EDT
EDT Logic
Test time decreases with EDT.
The Decompressor
 Logic blocks
 Ring generator
– Generates pseudorandom patterns R
R
II P
P
 Phase shifter N H
H
N
– Eliminates linear dependencies G
G A
A
S
S
 Data and control signals G
G E
E
EE
 EDT_Update NN SS
EE HH
 EDT_Clock RR II
AA FF
 Scan channel and chain inputs TT TT
EE
 Masking data (output only) O
O
RR
RR
 Routing characteristics
 Shallow combinational depth
– High operating speed
The Compactor
 Logic blocks
 XOR tree
– Not MISR based
 Masking Logic
– No fault masking or aliasing CC
O
O
 Data and control signals M
M
PP
 EDT_Update AA
CC
 EDT_Clock TT
O
O
 Masking data (input only) RR
 Scan chain and channel outputs
 Routing and performance
characteristics
 Pipeline stages for increased speed
Tessent TestKompress
Industry Standard for Embedded Deterministic Test (EDT) Compression
 100X time and data compression PLL Controller

enables higher test quality
 No loss in coverage
D
 Automatically masks X states for E
C
effective at-speed test C
O
O
M
 Flexibility M
P
P
 Adaptable modular configurations A
R
C
 Optimize compression, routing and E
T
S
number of channels O
S
R
 Award-winning technology O
R
 2001 Product of the Year
 2002 Best-in-Test
 2006 Donald O. Pederson (IEEE) Best
Paper Award on EDT
ATE
Compressed Compacted
stimuli responses
Tessent TestKompress Flows and Usage
 Operating modes
 EDT logic creation
– Post-core-synthesis
• Automated integration with wrapper
• Automated integration without wrapper
– Pre-core-synthesis
• No automated integration
– Coverage and compression estimation
 Pattern generation
– Same as ATPG
• Tessent FastScan DFT libraries
• Tessent FastScan commands
• Output vector formats
– Differences
• Additional design rule checking
• Additional Tessent TestKompress commands
EDT Logic Creation
 6 EDT logic creation commands:
 SET EDt OFf | ON
 SET EDt Pins
 WRIte EDt Files

The above commands have many switches, allowing user to
fully define the required logic.
 REPort EDt Configuration
 REPort EDt Lockup_cells
 REPort EDt Pins
 Commands support ALL logic creation flows.
Default Flow: Post-Core-Synthesis With Wrapper
Core Scan Insertion Core

With Netlist
Scan
Create EDT Logic
RTL-Level
Top-level Integration EDT Logic
Netlist
EDT Logic
Core Test Logic synthesis

With
Scan
ATPG with Tessent
TestKompress Test Patterns
Summary: ATPG and EDT
 Everything applicable to ATPG is
applicable to EDT (TestKompress
logic).
 All fault models.
 At-speed test.
 All pattern types.
 Pattern compaction.
 ATPG methodology is a
prerequisite to EDT.
 Understanding the “basics”
enables you to understand EDT.
 For more information about EDT
refer to The Tessent TestKompress
User’s Guide or take the 2-day
Design-for-Test: Tessent
TestKompress and Advanced
Topics class offered by Mentor
Graphics Education Services.
http://www.mentor.com/training_and_services/training/centers/worldwide_training_centers.cfm
Lab Exercise 9: Exploring Compression Techniques
During this lab, you will
 Create Tessent TestKompress logic and insert it in a design.

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Tessent: Scan and ATPG

Upon completion of this module, you will be able to:

 Explain what ATPG compression is.

 Describe when you would use EDT compression techniques.

Target Testcube Test Pattern Fault Sim

 Lower pattern count, increased ATPG runtime

 Automatic in ATPG Expert

 Automatically reach higher test coverage with fewer patterns.

 Reduces test application time.

Length of Longest Scan Chains

Test Cycles = L x W Test Time = (L x W) / Frequency

EDT appears to the tester as

NOTE: Data is loaded cycle-by-cycle.

Test time decreases with EDT.

 100X time and data compression PLL Controller

 SET EDt Pins

 WRIte EDt Files

 REPort EDt Configuration

 REPort EDt Lockup_cells

 REPort EDt Pins

 Commands support ALL logic creation flows.

Core Scan Insertion Core

Create EDT Logic

Core Test Logic synthesis

 Create Tessent TestKompress logic and insert it in a design.

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