Vlsi Design Lab Manual: Department of Electronics & Communication Engineering

VLSI DESIGN LAB MANUAL
Department of Electronics & Communication Engineering

VEMU INSTITUTE OF TECHNOLOGY::P.KOTHAKOTA
NEAR PAKALA, CHITTOOR-517112
(Approved by AICTE, New Delhi & Affiliated to JNTUA, Anantapuramu)
VLSI DESIGN LAB MANUAL
Name:_____________________________________________
H.T.No:____________________________________________
Year/Semester:______________________________________
Department of Electronics & Communication Engineering

VEMU INSTITUTE OF TECHNOLOGY::P.KOTHAKOTA
NEAR PAKALA, CHITTOOR-517112
(Approved by AICTE, New Delhi & Affiliated to JNTUA, Anantapuramu)
VEMU Institute of Technology
Dept. of Electronics and Communication Engineering
Vision of the institute

To be one of the premier institutes for professional education producing dynamic
and vibrant force of technocrats with competent skills, innovative ideas and leadership qualities
to serve the society with ethical and benevolent approach.
Mission of the institute
Mission_1: To create a learning environment with state-of-the art infrastructure, well equipped
laboratories, research facilities and qualified senior faculty to impart high quality technical
education.
Mission_2: To facilitate the learners to inculcate competent research skills and innovative ideas
by Industry-Institute Interaction.
Mission_3: To develop hard work, honesty, leadership qualities and sense of direction in
learners by providing value based education.
Vision of the department

To develop as a center of excellence in the Electronics and Communication
Engineering field and produce graduates with Technical Skills, Competency, Quality, and
Professional Ethics to meet the challenges of the Industry and evolving Society.
Mission of the department
Mission_1: To enrich Technical Skills of students through Effective Teaching and Learning
practices to exchange ideas and dissemination of knowledge.
Mission_2: To enable students to develop skill sets through adequate facilities, training on core
and multidisciplinary technologies and Competency Enhancement Programs.
Mission_3: To provide training, instill creative thinking and research attitude to the students
through Industry-Institute Interaction along with Professional Ethics and values.
Programme Educational Objectives (PEOs)
PEO 1: To prepare the graduates to be able to plan, analyze and provide innovative ideas to
investigate complex engineering problems of industry in the field of Electronics and
Communication Engineering using contemporary design and simulation tools.
PEO-2: To provide students with solid fundamentals in core and multidisciplinary domain for
successful implementation of engineering products and also to pursue higher studies.
PEO-3: To inculcate learners with professional and ethical attitude, effective communication
skills, teamwork skills, and an ability to relate engineering issues to broader social context at
work place
Programme Outcomes(Pos)
PO_1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO_2 Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
PO_3 Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
PO_4 Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO_5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
PO_6 The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO_7 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
PO_8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
PO_9 Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO_10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
PO_11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
PO_12 Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Programme Specific Outcome(PSOs)
Electronic System Design/Analysis: Apply the fundamental concepts of Electronics and

Communication Engineering to design and analysis of Electronics Systems for applications
PSO_1
including Signal Processing, Communication & Networking, Embedded Systems, VLSI design and
Control Systems.
Software Tools: Proficiency in specialized software tools and computer programming useful for
PSO_2 the design and analysis of complex electronic systems to meet challenges in contemporary
business environment.
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR
IV B.Tech. I-Sem (ECE)
(19A04702P) VLSI DESIGN LABORATORY
Course Outcomes:
C418.1 Understand the physical design of digital integrated circuits.

C418.2 Describe procedure for designing of programmable circuits.
C418.3 Demonstrate the ability to use various EDA tool for digital system design.
C418.4 Implement various combinational and sequential circuits using VHDL on FPGA.
To analyze the result of logic and timing simulations and to use these simulation results to
C418.5
debug digital system.
PART A: FPGA Level Implementation (Any Seven Experiments)

1. Realization of Logic Gates.
2. 4-bit ripple carry and carry look ahead adder using behavioral, dataflow and
structural modeling
3. Design and Implementation of
a) 16:1 mux through 4:1 mux
b) 3:8 decoder realization through 2:4 decoder
4. Design and Implementation of 8:3 encoder
5. Design and Implementation of 8-bit parity generator checker
6. Design and Implementation of different Flip-Flops
7. Design and Implementation of 4-bit sequence detector through Mealy and
Moore state machine
PART B: Back-end Level Design and Implementation (Any Five Experiments)

8. Design and Implementation of Universal Gates
9. Design and Implementation of an Inverter
10. Design and Implementation of Full Adder
11. Design and Implementation of Full Subtractor
12. Design and Implementation of D latch
Advanced Experiments
13. Design and Implementation of differentitional amplifier
14. Design and Implementation of ALU

VEMU INSTITUTE OF TECHNOLOGY
P.KOTHAKOTA, NEAR PAKALA, CHITTOOR, AP
Department of Electronics &Communication Engineering

(19A04702P) VLSI DESIGN LABORATORY
IV B.Tech-II SEM
LIST OF EXPERIMENTS TO BE CONDUCTED
PART A: FPGA Level Implementation (Any Seven Experiments)

2. 4-bit ripple carry and carry look ahead adder using behavioral, dataflow and
structural modeling
a) 16:1 mux through 4:1 mux
b) 3:8 decoder realization through 2:4 decoder
5. Design and Implementation of 8-bit parity generator checker
7. Design and Implementation of 4-bit sequence detector through Mealy and
Moore state machine
PART B: Back-end Level Design and Implementation (Any Five Experiments)

PART C: Advanced Experiments

13. Design and Implementation of Differential Amplifier.

CONTENTS
S. NO. NAME OF THE EXPERIMENT PAGE NO
PART A
2. 4-bit ripple carry and carry look ahead adder using behavioral
dataflow and structural
modelling
A ) 16:1 MUX through 4:
B) 3:8 decoder realization 2:4 decoder
5. Design and Implementation of 8-bit parity generator and checker

7. Design and Implementation of 4-bit sequence detector through
Mealy and Moore state machine
PART B
13. Design and Implementation of Differential Amplifier

DOS & DONTS IN LABORATORY
1. While entering the Laboratory, the students should follow the dress code
Wear shoes, White Apron & Female students should tie their hair back).
2. The students should bring their observation note book, practical manual,
record note book, calculator, necessary stationary items and graph sheets if
any for the lab classes without which the students will not be allowed for
doing the practical.
3. All the equipments and components should be handled with utmost care.
Any breakage/damage will be charged.
4. If any damage/breakage is noticed, it should be reported to the instructor
immediately.
5. If a student notices any short circuits, improper wiring and unusual smells
immediately the same thing is to be brought to the notice of technician/lab in
charge.
6. At the end of practical class the apparatus should be returned to the lab
technician and take back the indent slip.
7. Each experiment after completion should be written in the observation note
book and should be corrected by the lab in charge on the same day of the
practical class.
8. Each experiment should be written in the record note book only after getting
signature from the lab in charge in the observation note book.
9. Record should be submitted in the successive lab session after completion of
the experiment.
10. 100% attendance should be maintained for the practical classes.
SCHEME OF EVALUATION
Marks Awarded
S.N Obs. Total
Program Date Record Viva Attd.
o (10M 30(M)
(10M) (5M) (5M)
)
PART-A
1 Realization of Logic Gates.
2 4-bit ripple carry and carry look ahead adder
Design and Implementation of

3. A ) 16:1 MUX through 4:1
B) 3:8 decoder realization 2:4 decoder
4. Design and Implementation of 8:3encoder

Design and Implementation of 8-bit parity
5.
generator and checker
Design and Implementation of different Flip-
6.
Flops
Design and Implementation of 4-bit sequence
7. detector through Mealy and Moore state
machine
PART-B
Design and Implementation of Universal
8. Gates
Design and Implementation of differentitional
13.
amplifier
Signature of Lab In-charge

VLSI DESIGN LAB (19A04702P) IV B.Tech I SEMESTER
PART A
(FPGA Level Implementation)
VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 1

CIRCUIT DIAGRAM & TRUTH TABLES
AND GATE TRUTH TABLE
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
OR GATE
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
NOT GATE
A Y
0 1
1 0
NAND GATE
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NOR GATE
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

EXP NO. DATE

REALIZATION OF ALL LOGIC GATES
1
AIM:
To write a VHDL/Verilog code for All Logic Gates and to generate
synthesis report, RTL schematic and to implement designs using FPGA (Spartan-3).
APPARATUS:
1. Synthesis Tool: Xilinx Project Navigator - ISE 9.1i.
2. Simulation Tool: Modelsim Simulator.
PROCEDURE:
1. Open Xilinx ISE 9.1i.
2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it and synthesize the process.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. Create another new source.
8. Select source type as Test bench wave form.
9. Associate the test bench to the source.
10. Assign clock and timing details.
11. Give the input waveforms for the source.
12. Save the input waveforms and perform behavioral simulation.
13. The simulated output waveforms window will be shown.
DUMPING PROCESS:
1. In the process window, go to ‘user constraints’ and select ‘assign package pins’ and after that
double click on ‘implement design’.
2. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’ clock in
startup options.
3. Select boundary scan in ‘impact window’ after double clicking on ‘configure Device’.
4. In ‘generate programming file’ double clicking on ‘programming file generation report. Bit
file will be generated.
5. Xilinx boundary scan window will appear when the bit file is selected. Right click on Xilinx
component and select program.
6. Programming properties will appear and finally program will be succeeded.
7. Thus the program can be dumped into FPGA kit and finally output can be seen on the kit.

SIMULATED MODEL OUTPUT WAVEFORMS
AND gate
OR gate
NOT GATE
NAND gate

VHDL CODE:
AND GATE :
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Andgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end Andgate ;
architecture Behavioral of Andgate is
begin
y <= a and b;
end Behavioral;
OR GATE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity orgate is
b : in STD_LOGIC;
y : out STD_LOGIC);
end orgate ;
architecture Behavioral of orgate is
begin
y <= a or b;
end Behavioral;

NOR gate
BLOCK DIAGRAM:

NOT GATE :
library IEEE;
entity notgate is
y : out STD_LOGIC);
end notgate ;
architecture Behavioral of notgate is
begin
y <= not a;
end Behavioral;
NAND GATE :
library IEEE;
entity nandgate is
b : in STD_LOGIC;
y : out STD_LOGIC);
end nandgate ;
architecture Behavioral of nandgate is
begin
y <= a nand b;
end Behavioral;
NOR GATE :
library IEEE;
entity norgate is
b : in STD_LOGIC;
y : out STD_LOGIC);
end norgate ;
architecture Behavioral of norgate is

begin
y <= a nor b;
end Behavioral;

T E C H NO L O G Y S C H EM A TI C :
R T L S C H EM A T IC :

DESIGN SUMMARY:
Number of Slices : 3 out of 960 0%

Number of 4 input LUTs : 5 out of 1920 0%
Number of IOs : 7
Number of bonded IOBs : 7 out of 66 10%
SYNTHESIS REPORT:
RTL Top Level Output File Name : allgates.ngr

Top Level Output File Name : allgates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :7
Cell Usage :
# BELS :5
# INV :1
# LUT2 :4
# IO Buffers :7
# IBUF :2
# OBUF :5
RESULT:
CONCLUSION:

VIVA QUESTIONS:
1. Design all basic gates using 2:1 multiplexer?
2. Write the dataflow code for the logic gates
3. What are logic gates why the called so?
4. Which gates are called as universal gates? What are its advantages?
5. What are the applications of logic gates?

CIRCUIT DIAGRAM:
4-BIT RIPPLE CARRY ADDER
4-BIT CARRY LOOK AHEAD ADDER:

EXP NO. 4- BIT RIPPLE CARRYAND CARRY LOOK DATE

AHEAD ADDER
2
AIM:
To write a VHDL/Verilog code for 4-bit ripple carry and carry look ahead adder and to
generate synthesis report, RTL schematic and to implement designs using FPGA (Spartan-3).
APPARATUS:
PROCEDURE:

6. Select Synthesize XST, check for syntax errors and generate report and RTL schematic.
DUMPING PROCESS:
1. In the process window, go to ‘user constraints’ and select ‘assign package pins’ and after
that double click on ‘implement design’.
startup options.
3. Select boundary scan in ‘impact window’ after double clicking on ‘configure device’.
4. In ‘generate programming file’ double clicking on ‘programming file generation report.
Bit file will be generated.
5. Xilinx boundary scan window will appear when the bit file is selected. Right click on
Xilinx component and select program.

SIMULATED MODEL OUTPUT WAVEFORM:
4-BIT RIPPLE CARRY ADDER:
4-BIT CARRY LOOK AHEAD ADDER:

4-BIT RIPPLE CARRY ADDER VHDL CODE:
library IEEE;
entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0); Cout : out STD_LOGIC);
end Ripple_Adder;
architecture Behavioral of Ripple_Adder is
component full_adder_vhdl_code Port ( A : in STD_LOGIC;

B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
signal c1,c2,c3: STD_LOGIC;
begin
FA1: full_adder_vhdl_code port map( A(0),B(0),Cin,S(0),c1);

FA2: full_adder_vhdl_code port map( A(1),B(1),c1,S(1),c2);
FA3: full_adder_vhdl_code port map( A(2),B(2),c2,S(2),c3);
FA4: full_adder_vhdl_code port map( A(3),B(3),c3,S(3),Cout);
end Behavioral;
4-BIT CARRY LOOK AHEAD ADDER VHDL CODE:
Partial Full Adder:

library IEEE;
entity Partial_Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
End Partial_Full_Adder;
Architecture Behavioral of Partial_Full_Adder is

begin S <= A xor B xor Cin;
P <= A xor B;
G <= A and B;
end Behavioral;

Carry Look Ahead Adder:
library IEEE;
entity Carry_Look_Ahead is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Carry_Look_Ahead;
architecture Behavioral of Carry_Look_Ahead is component Partial_Full_Adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
end component;
signal c1,c2,c3: STD_LOGIC;
signal P,G: STD_LOGIC_VECTOR(3 downto 0);
begin
PFA1: Partial_Full_Adder port map( A(0), B(0), Cin, S(0), P(0), G(0));
PFA2: Partial_Full_Adder port map( A(1), B(1), c1, S(1), P(1), G(1));
c1 <= G(0) OR (P(0) AND Cin);

c2 <= G(1) OR (P(1) AND G(0)) OR (P(1) AND P(0) AND Cin);
c3 <= G(2) OR (P(2) AND G(1)) OR (P(2) AND P(1) AND G(0)) OR (P(2) AND P(1)
AND P(0) AND Cin);
Cout <= G(3) OR (P(3) AND G(2)) OR (P(3) AND P(2) AND G(1)) OR (P(3) AND
P(2) AND P(1) AND G(0)) OR (P(3) AND P(2) AND P(1) AND P(0) AND Cin);
end Behavioral;



DEVICE UTILIZATION SUMMARY:

Selected Device: 3s400pq208-4
Number of Slices: 0 out of 3584 0%
Number of IOs: 14
Number of bonded IOBs: 14 out of 141 9%
SYNTHESIS REPORT:
RTL Top Level Output File Name : Carry_Look_Ahead.ngr
Top Level Output File Name : Carry_Look_Ahead
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 14
Cell Usage :
# BELS :4
# LUT3 :4
# IO Buffers : 14
# IBUF :9
# OBUF :5
# Others :4
# Partial_Full_Adder :4
Selected Device : 3s400pq208-4

Number of IOs : 14
SYNTHESIS REPORT
RTL Top Level Output File Name : Ripple_Adder.ngr

Top Level Output File Name : Ripple_Adder
Output Format : NGC
Keep Hierarchy : No
Design Statistics
# IOs : 14
Cell Usage :
# IO Buffers : 14
# IBUF :9
# OBUF :5
# Others :4
# full_adder_vhdl_code :4

RESULT:
CONCLUSION:
VIVA QUESTIONS:
1. Why we use ripple carry adder?
2. What is 4-bir carry look ahead adder?
3. What is delay of ripple carry adder?
4. Why CLA is better than RCA?
5. Is ripple carry adder and carry look ahead adder same?

CIRCUIT16:1 MUX USING 4:1MUX
TRUTH TABLE:
SIMULATED MODEL OUTPUT WAVEFORM

EXP NO. DATE

16:1 MUX USING 4:1MUX
3(a)
AIM:
To write a VHDL/Verilog code for 16:1 Mux generate synthesis report, RTL schematic
and to implement designs using FPGA (Spartan-2).
APPARATUS:
PROCEDURE:

DUMPING PROCESS:
startup options.

CIRCUIT DIAGRAM:
Y0_L
G1 Y1_L
G2A_L
Y2_L
G2B_L
Y3_L
Y4_L
A
Y5_L
B
Y6_L
C
Y7_L

VHDL CODE FOR 16:1 using 4:1 mux
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kanhe_4x1mux is
port(a,b,c,d : in std_logic;
S0,s1 : in std_logic;
q : out std_logic);
end kanhe_4x1mux;
Architecture kanhe_4x1mux1 of kanhe_4x1mux is

Begin
Process(a,b,c,d,s0,s1)
Begin
If s0 ='0' and s1 ='0' then q <= a;

Elsif s0 ='1' and s1 ='0' then q <= b;
elsif s0 ='0' and s1='1' then q <= c;
else q <=d;
end if;
End process;
End kanhe_4x1mux1;
Main program:
Library ieee;
use ieee.std_logic_arith.all;
entity kanhe_16x1mux is
port(a:in std_logic_vector(15 downto 0);
s: in std_logic_vector(3 downto 0);
Z :out st d_log i c );
End kanhe_1 6x1 mux ;
A rc hi tec ture kanh e_16x1 mu x1 of kanhe_16 x1m ux i s

s igna l z1, z2, z3, z4: std_ log ic;
component kanhe_4x1mux is
port(a,b,c,d,s0,s1:in std_logic;
Q:out std_logic);
End co mponen t;
Begin
M1 : kanhe_4x1mux po rt map (a (0 ),a (1 ) ,a( 2) ,a (3 ), s( 0) ,s (1 ), z1 );
m 2: kanhe_4x1mux po rt map (a (4 ),a (5 ) ,a( 6) ,a (7 ), s( 0) ,s (1 ), z2 );
m 3: kanhe_4x1mux po rt map (a (8 ),a (9 ) ,a( 10) ,a (11 ), s (0 ),s (1 ), z3 );
m 4: kanhe_4x1mux po rt map (a (12 ), a(1 3) ,a (14 ),a (15 ), s (0 ), s(1 ) ,z4 );
m 5: kanhe_4x1mux po rt map ( z1, z2, z3,z4 ,s (2 ), s (3) ,z );
End kanhe_1 6x1 mux1 ;

EXP NO. DATE

3:8 DECODER
3(b)
AIM:
To write a VHDL/Verilog code for 3x8 Decoder and to generate synthesis report, RTL
schematic and to implement designs using FPGA (Spartan-2).
APPARATUS:
PROCEDURE:

DUMPING PROCESS:
startup options.

TRUTH TABLE:
Selected enable inputs inputs outputs

G1 G2A_L G2B_L A(2) A(1) A(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1
SIMULATION MODEL OUTPUT WAVEFORM
BLOCK DIAGRAM:

VHDL CODE:
VHDL CODE FOR 3 t0 8 DECODER-BEHAVIORAL MODEL :
library IEEE;
entity dec3to8_beh is
port ( g1 : in STD_LOGIC;
g2a_l : in STD_LOGIC;
g2b_l : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(2 downto 0);
y_l : out STD_LOGIC_VECTOR(7 downto 0));
end dec3to8_beh;
architecture Behavioral of dec3to8_beh is
begin
process (g1,g2a_l,g2b_l,a)
begin
if (g1='0' and g2a_l='0' and g2b_l='0')then
y_l<= "11111111";
elsif(g1 ='1' and g2a_l='0' and g2b_l='0') then
if(a="000")then
y_l<="11111110";
elsif(a="001") then
y_l<="11111101";
elsif(a="010")then
y_l<="11111011";
elsif(a="011")then
y_l<="11110111";
elsif(a="100")then
y_l<="11101111";
elsif(a="101")then
y_l<="11011111";
elsif(a="110")then
y_l<="10111111";
elsif(a="111") then
y_l<="01111111";
end if;
end if;
end process;
end Behavioral;


D E VI C E U TI L I Z A TI O N S UM M A R Y:
Number of Slices: 8 out of 960 0%
Number of 4 input LUTs: 14 out of 1920 0%
Number of IOs: 14
Number of bonded IOBs: 14 out of 66 21%
IOB Flip Flops: 8
SYNTHESIS REPORT:
RTL Top Level Output File Name : decoder.ngr
Top Level Output File Name : decoder
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 14
Cell Usage:
# BELS : 14
# LUT2 :4
# LUT3 :2
# LUT4 :8
# FlipFlops/Latches :8
# LD :8
# IO Buffers : 14
# IBUF :6
# OBUF :8
RESULT:
CONCLUSION:

VIVA QUESTIONS:
1. Write the behavioral code for the IC 74x138.
2. Write the VHDL code for the IC 74x138 using CASE statement.
3. What does priority encoder mean?
4. How many outputs will a decimal-to-BCD encoder have?
5. Can an encoder be a transducer?

EXP NO. DATE

8:3 ENCODER
4
AIM:
To write a VHDL/Verilog code for 8:3 Encoder and to generate synthesis report, RTL schematic
APPARATUS:
PROCEDURE:

DUMPING PROCESS:
startup options.

VHDL CODE FOR 8 to 3 ENCODER:
l i brary i ee e;
use i ee e.st d_l ogi c_ 1164. al l ;
ent i t y e83 i s
port ( p: i n st d_l ogi c_ve ct or( 7 do w nt o 0);
y: out st d_l ogi c_ve ct or( 2 dow nt o 0));
end e8 3;
archi t ect ur e beh of e83 i s
begi n
proc ess (p )
begin
case p is
when "00000001"=>y<="000";
when "00000001"=>y<="001";
when "00000100"=>y<="010";
when "00001000"=>y<="011";
when "00010000"=>y<="100";
when "00100000"=>y<="101";
when "01000000"=>y<="110";
when "10000000"=>y<="111";
when others=>y<="UUU";
end ca se;
end p roce ss;

TRUTH TABLE:
INPUT OUTPUTS
S
P7 P6 P5 P P3 P2 P1 P0 Y(2) Y(1) Y(0)
4
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

SIMULATION MODEL OUTPUT WAVEFORM
RESULT:
CONCLUSION:

VIVA QUESTIONS:
1. what is the use of 8:3 encoder?
2. What are the types of encoder?
3. How is an encoder different from a decoder?
4. How many gates are required for a 8 to 3 encoder?
5. Where is encoder used?

CIRCUIT DIAGRAM:
The 8-bit parity generator
TRUTH TABLE:
SIMULATION MODEL OUTPUT WAVEFORM :

EXP NO. DATE

PARITY GENERATOR AND CHECKER
5
AIM:
To write a VHDL/Verilog code for Parity generator and checker synthesis report, RTL
APPARATUS:
PROCEDURE:

DUMPING PROCESS:
startup options.

CIRCUIT DIAGRAM:
TRUTH TABLE:
SIMULATION MODEL OUTPUT WAVEFORM :

VHDL CODE:
The 8-bit parity generator:
library ieee;
entity parity is
port( data:in bit_vector(7 downto 0);
even_p,odd_p: out bit);
end parity;
architecture parity_gen of parity is
signal temp : bit_vector(5 downto 0);
begin
temp(0)<=data(0) xor data(1);
temp(1)<=temp(0) xor data(2);
even_p <= temp(5) xor data(7);
odd_p <= not(temp(5) xor data(7);
end parity_gen;
The 8-bit parity checker :
library ieee;
entity parity is
port( data:in bit_vector(7 downto 0);
even_p,odd_p: out bit);
end parity;
architecture parity_gen of parity is
signal temp : bit_vector(5 downto 0);
begin
temp(0)<=data(0) xor data(1);
even_p <= temp(5) xor data(7);
odd_p <= not(temp(5) xor data(7);
end parity_arch;

RESULT:
CONCLUSION:
VIVA QUESTIONS:
1. What is parity generator and checker?
2. Which gate is ideal for checking the parity of data?
3. What is the purpose of parity checker?
4. What is a 3-bit parity checker?
5. How is parity calaculated?

FLIP FLOPS:
LOGIC DIAGRAM OF IC 74X74
TRUTH TABLE :
LOGIC DIARAM OF D FLIP FLOP
CLK PR_L CLR_L D Q QN
x 0 1 x 1 0
x 1 0 x 0 1
PR-L x 0 0 x 1 1
1 1 1 0 0 1
1 1 1 1 1 0
1 1 x Q QN
CLR-L Q
CLK QN

EXP NO. FLIP FLOPS DATE
AIM:
To write a VHDL/Verilog code for Flip Flop and to generate synthesis report, RTL schematic
APPARATUS:
PROCEDURE:

DUMPING PROCESS:
startup options.

TRUTH TABLE:
TRUTH TABLE :
CLK PR_L CLR_L D Q QN
x 0 1 x 1 0
x 1 0 x 0 1
x 0 0 x 1 1
1 1 1 0 0 1
1 1 1 1 1 0
1 1 x Q QN
BLOCK DIAGRAM:

VHDL CODE:
library IEEE;
entity dfff is
Port ( d: in STD_LOGIC_VECTOR(0 to 1);
clk : in STD_LOGIC_VECTOR;
pr : in STD_LOGIC_VECTOR(0 to 1);
clr : in STD_LOGIC_VECTOR(0 to 1);
q : inout STD_LOGIC_VECTOR(0 to 1);
nq :inout STD_LOGIC_VECTOR(0 to 1));
end DFFF;
architecture structural of DFFF is
component dff1
port(d1,clk1,pr1,clr1:in std_logic;
q1,nq1:inout std_logic);
end component;
begin
D1:dff1 port map(d(0),clk, pr(0),clr(0),q(0),nq(0));
D2:dff1 port map(d(1),clk, pr(1),clr(1),q(1),nq(1));
end structural;

R T LS C H EM A TI C :

VHDL CODE FOR COMPONENT D FLIPFLOP:
entity dff1 is
Port ( d1: in STD_LOGIC;
Clk1 : in STD_LOGIC;
Pr1 : in STD_LOGIC;
Clr1 : in STD_LOGIC;
Q1 : inout STD_LOGIC;
Nq1 :inout STD_LOGIC);
end dff1;
architecture Behavioral of dff1 is
begin
process(d1,pr1,clr1,clk1)
begin
if(pr1='0' and clr1='0')then
q1<='1';nq1<='1';
elsif(pr1='0' and clr1='1')then
q1<='1';nq1<='0';
elsif(pr1='1' and clr1='0')then
q1<='0';nq1<='1';
else
if(clk1='1' and clk1'event)then
q1<=d1;nq1<=not d1;
else
q1<=q1;nq1<=nq1;
end if;
end if;
end process;
end Behavioral;

D E VI C E U TI L I Z A TI O N S UM M A R Y:
Number of Slice Flip Flops : 2 out of 1920 0%
Number of IOs : 6
IOB Flip Flops : 2
Number of GCLKs : 1 out of 24 4%
SYNTHESIS REPORT:
RTL Top Level Output File Name : dff.ngr
Top Level Output File Name : dff
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :5
# INV :3
# LUT2 :2
# FDCP :2
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :3
# OBUF :2
RESULT:
CONCLUSION:

VIVA QUESTIONS:
1. What are the applications of Flip flops?
2. The truth table for an S-R flip-flop has how many VALID entries?
3. When both inputs of a J-K flip-flop cycle, the output will?
4. How many types of sequential circuits are?
5. In D flip-flop, if clock input is LOW, the D input?

TRUTH TABLE:
NEXT STATE OUTPUT(Z)

PRESENT
STATE
a=0 a=1 a=0 a=1
S0 S0 S1 0 0
S1 S0 S1 0
MEALY

EXP NO. 4 BIT SEQUENCE DETECTOR THROUGH DATE

MEALY &MOORE STATE MACHINES
AIM:
To write a VHDL/Verilog code and to generate synthesis report, RTL schematic and to
implement designs using FPGA (Spartan-2).
APPARATUS:
PROCEDURE:

DUMPING PROCESS:
startup options.

VHDL CODE FOR MEALY MACHINE:
libra ry ieee;
use ieee . std_logic _1164.all;
entity
meal yis
port(a, clk: in st d_logic;z: out std_logic );

end m ealy;
architecture beh of mealy is
type stat e i s( s0, s1);
signal p_state,n_state: state;
begi n
sm: process(clk)
begin
if rising_edge(clk) then
p_state <= n_state;

e nd if;
e nd pr oce ss sm;
cm: process(p_state,a)
begi n
case p_state i s
when s0=> if(a='0') then z<='0';
n_state <= p_state;
elsez <=' 0'; n_state < =s1;

end if;
whe ns1=>i f(a ='1' )the nz <=' 0';
n_state <= p_state;
elsez <=' 1';
n_state <= s0;

end if;
whe not her s=>z < ='0';
n_state <= s0;
end ca se;
endpr oce ss cm;
end beh;
TRUTH TABLE:
PRESENT NEXT STATE OUTPUT(Z)

STATE a=0 a=1 a=0 a=1
S0 S0 S1 0 0
S1 S2 S1 0 0
S2 S0 S1 1 0
RTL SCHEMATIC:
MOORE

VHDL CODE FOR MOORE MACHINE:
libra ry ieee; use iee e. std_l ogic _1164.all;
entity moor e is
port(a, clk:i nstd_l ogic ; z:out std_logic);
end m oore;
architecture beh of moore is
type state is(s0,s1,s2);
signal n_state,p_state: state;
be gin
s:process(clk)
begi n
if rising_edge(clk) then
p_state <= n_state;
end i f;end pr oce ss;
d: pr oce ss(a ,p_state)
begi n
case p_state is
when s0=>z<='0';
if(a='0') then
n_state<= p_state;
else
n_state<=s1;
end if;
when s1=>z<='0';
if(a='1') then
n_state <= s2;
else
n_state<=p_state;
end if;
when s2=>z<='1';
n_state <= s0;
end ca se;
end pr oce ss;
end beh;

RESULT:
CONCLUSION:
VIVA QUESTIONS:
1. What is the use of sequence detector?
2. What is sequence detector moore?
3. What is the differenc between mealy and moore?
4. What is VHDL?
5. What is overlapping sequence detector?

PART B
(Back-end Level Design and Implementation)

EXP NO. DATE

Design and Implementation Universal Gates
8
Aim: To design and implementation of universal gates
Software Required: Mentor Graphics-Pyxis, AMS, Calibre
(i). NAND Gate:
Circuit Diagram:

PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool
2. Enter into Simulation mode.
3. Setup the Analysis and library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
Testbench:

Output waveforms:
NOR Gate:

Testbench:
Output waveforms:

Result:
Conclusion:
Viva Questions:
1. How are universal gates implemented?
2. What is the difference between basic gates and universal gates?
3. What is the logic equation for a gate?
4. How many transistor are in Ex-or gate?
5. Which gate is known as equality detector?

EXP NO. DATE

Design and Implementation of an Inverter
9
AIM: To design and Implementation of an Inverter
Software Required: Mentor Graphics - Pyxis, AMS, Calibre.
CIRCUIT DIAGRAM:

PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool
2. Enter into Simulation mode.
3. Setup the Analysis and library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Pysis Layout.
9. Perform Routing using IRoute
10. Perform DRC, LVS, PEX.
OUTPUT WAVEFORMS:

Layout:
Result Verification Environment:

Result:
Conclusion:
Viva Questions:
1. why Ex-or gate called an inverter?
2. what is the principle of inverter?
3. What is the basic inverter circuit of CMOS?
4. What are the characteristics of a CMOS inverter?
5. What is threshold voltage of CMOS inverter?

EXP NO. DATE

Design and Implementation of Full Adder
10
AIM: To design and Implementation of an Fulladder
CIRCUIT DIAGRAM:

Testbench:
output Waveforms:

Result:
Conclusion:
Viva Questions:
1. Which gate is used to design full adder?
2. What are the types of adders ?
3. How many MUX are required for full adder?
4. How do you implement a full adder using half adder?
5. What are the advantages and disadvantages of full adder?

EXP NO. DATE

Design and Implementation of Full
Subtractor
11
AIM: To design and Implementation of an Full-subtractor
CIRCUIT DIAGRAM:

Testbench:

Output waveforms:

Result:
Conclusion:
Viva Questions:
1. What are the advantages and disadvantages of full subtractor?
2. What is the difference between a half and full subtractor?
3. Which decoder is needed for full subtractor?
4. How many NAND gates make a full subtractor and design it?
5. what is the expression for full subtractor?

EXP NO. DATE

Design and Implementation of D-Latch
12
AIM: To design and Implementation of an D-Latch
CIRCUIT DIAGRAM:

Testbench:
Output Waveform:

Result:
Conclusion:
Viva Questions:
1. What is latch and its types?
2. What are the applications of D-Latch?
3. Why d flip-flop called data latch?
4. How do you convert SR latch to D latch?
5. Write the differences between latch and flip-flop?

ADVANCED EXPERIMENT

EXP NO. DESIGN AND IMPLEMENTATION DATE

DIFFERENTIAL AMPLIFIER
13
AIM: To design and Implementation of an Differential Amplifier
CIRCUIT DIAGRAM:

Testbench:
OUTPUT WAVEFORMS:

Result:
Conclusion:
Viva Questions:
1. Abbreviate CMOS and NMOS?
2. What are applications of Difference amplifier?
3. What Does Differential amplifier do?
4. What are the types of differential amplifier?
5. What are the advantages of differential amplifier?

BLOCK DIAGRAM:
OUTPUT WAVEFORMS:

EXP NO. DESIGN AND IMPLEMENTATION OF ALU DATE
14
AIM:
To write a VHDL/Verilog code for ALU Design and to generate synthesis report, RTL
APPARATUS:
PROCEDURE:

DUMPING PROCESS:
1. In the process window, go to ‘user constraints’ and select ‘assign package

pins’ and after that double click on ‘implement design’.
2. Select properties by right clicking on ‘generate programming file’. Select
‘JTAG’ clock in startup options.
3. Select boundary scan in ‘impact window’ after double clicking on ‘configure
Device’.
4. In ‘generate programming file’ double clicking on ‘programming file
generation report. Bit file will be generated.
5. Xilinx boundary scan window will appear when the bit file is selected. Right
click on Xilinx component and select program.
7. Thus the program can be dumped into FPGA kit and finally output can be
seen on the kit.

RTL SCHEMATIC:
TRUTH TABLE:
m=0 Logic
s(2) s(1) s(0) Function Operation (bit wise)
0 0 0 ~a NOT
0 0 1 ~b NOT
0 1 0 a&b AND
0 1 1 a|b OR
1 0 0 ~(a&b) NAND
1 0 1 ~(a|b) NOR
1 1 0 a^b EXOR
1 1 1 ~(a^b) EXNOR
m=1 Arithmetic
0 0 0 a Transfer a
0 0 1 a+1 Increment a by 1
0 1 0 a+b Add a and b
0 1 1 a+b+1 Increment the sum of a and b by 1
1 0 0 a+(~b) a plus one’s complement of b
1 0 1 a-b Subtract b from a (i.e. ~b+a+1)
1 1 0 (~a)+b b plus one’s compliment of a
1 1 1 b-a Subtract a from b (i.e. ~a+b+1)

VHDL CODE:
library IEEE;
entity alu4b is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (2 downto 0);
m,clk : in STD_LOGIC;
y: out STD_LOGIC_VECTOR (3 downto 0));
end alu4b;
architectureBehavioral of alu4b is
begin
process(a,b,s,m)
begin
if(clk'event and clk='1')then
elsif(m='0')then
case s is
when"000"=>y<=not a;
when"001"=>y<=not b;
when"010"=>y<=a and b;
when"011"=>y<=a or b;
when"100"=>y<=a nand b;
when"101"=>y<=a nor b;
when"110"=>y<=a xor b;
when"111"=>y<=a xnor b;
when others=>null;
end case;
else
case s is
when"000"=>y<=a;
when"001"=>y<=a+1;
when"010"=>y<=a+b;
when"011"=>y<=a+b+1;
when"100"=>y<=a+(not b);
when"101"=>y<=a-b;
when"110"=>y<=(not a)+b;
when"111"=>y<=b-a;
when others=>y<=b;
end case;
end if;
end process;
end Behavioral;

EVICE UTILIZATION SUMMARY:

Number of Slice Flip Flops : 4 out of 1920 0%
Number of IOs : 6
Number of GCLKs : 1 out of 24 4%
SYNTHESIS REPORT:
RTL Top Level Output File Name : alu.ngr
Top Level Output File Name : alu
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :4
# INV :1
# LUT3 :1
# LUT4 :2
# FDC :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :1
# OBUF :4
RESULT:
CONCLUSION:

VIVA QUESTIONS:
1. What is the purpose of ALU?
2. What are the functional blocks of ALU?
3. In a 16-bit ALU, what does the number ‘16’ indicates?
4. Draw the schematic of Subtractor- using adder circuit.
5. What are the advantages of ALU Design?

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VLSI DESIGN LAB MANUAL

Department of Electronics & Communication Engineering

VLSI DESIGN LAB MANUAL

Department of Electronics & Communication Engineering

Vision of the institute

Vision of the department

Programme Educational Objectives (PEOs)

PO_1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering

Electronic System Design/Analysis: Apply the fundamental concepts of Electronics and

C418.1 Understand the physical design of digital integrated circuits.

PART A: FPGA Level Implementation (Any Seven Experiments)

PART B: Back-end Level Design and Implementation (Any Five Experiments)

14. Design and Implementation of ALU

Department of Electronics &Communication Engineering

LIST OF EXPERIMENTS TO BE CONDUCTED

PART A: FPGA Level Implementation (Any Seven Experiments)

PART B: Back-end Level Design and Implementation (Any Five Experiments)

PART C: Advanced Experiments

14. Design and Implementation of ALU

S. NO. NAME OF THE EXPERIMENT PAGE NO

B) 3:8 decoder realization 2:4 decoder

4. Design and Implementation of 8:3 encoder

5. Design and Implementation of 8-bit parity generator and checker

6. Design and Implementation of different Flip-Flops

9. Design and Implementation of an Inverter

10. Design and Implementation of Full Adder

11. Design and Implementation of Full Subtractor

12. Design and Implementation of D latch

14. Design and Implementation of ALU

2 4-bit ripple carry and carry look ahead adder

Design and Implementation of

4. Design and Implementation of 8:3encoder

9. Design and Implementation of an Inverter

10. Design and Implementation of Full Adder

11. Design and Implementation of Full Subtractor

12. Design and Implementation of D latch

14. Design and Implementation of ALU

Signature of Lab In-charge

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 1

CIRCUIT DIAGRAM & TRUTH TABLES

AND GATE TRUTH TABLE

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 2

EXP NO. DATE

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 3

SIMULATED MODEL OUTPUT WAVEFORMS

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 4

architecture Behavioral of Andgate is

architecture Behavioral of orgate is

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 5

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 6

architecture Behavioral of norgate is

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 7

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 8

Number of Slices : 3 out of 960 0%

RTL Top Level Output File Name : allgates.ngr

VEMU INSTITUTE OF TECHNOLOGY::DEPT OF ECE Page 9

1. Design all basic gates using 2:1 multiplexer?

2. Write the dataflow code for the logic gates

3. What are logic gates why the called so?