A B C D E

1 1

Compal Confidential
NIMUA/UB
2

Schematics Document 2

Arrandale
with Intel IBEX PEAK-M core logic
3 3

REV:0.3

4 4

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 1 of 50
A B C D E
 A B C D E

Compal confidential
File Name : CR BD:
Thermal-sensor POWER BD:
ZZZ
LS-5941P LS-5944P
EMC1403 page38
POWER BT
14.1W_PCB_LA5941P VRAM 64*16 Intel
DDR3*4 SW BD: Body-Detect BD:
1 DAZ0D500102
page20 PCI-E X16 Arrandale Clock Generator LS-5942P 1

(UMA/SG) LS-5947P
SLG8LV597VTR NOVO BT
page12

NVidia N11M-LP1 Socket-rPGA989 Finger Print BD:

page19~23
37.5mm*37.5mm DDR3-SO-DIMM X2 LS-5943P
BANK 0, 1, 2, 3 U-pek TCS5D
page5~9 page 10,11
level shift IC Dual Channel
HDMI ASM1442 UP TO 8G
CONN page25 100MHz FDI *8 DMI *4 DDR3-800(1.5V)
page24 2.7GT/s DDR3-1067(1.5V) 2Channel Speaker
page33
CRT Connector SW1
page26
Intel Ibex Peak M
2 DMIC_Int 2

LVDS Audio Codec page33

SW2 AZALIA ALC259
Connector page27
FCBGA 951 page33 Audio Jack CONN.
PCI Express page37

6*PCI-E BUS 25mm*25mm

Mini card Slot 2 14*USB2.0 CMOS Camera
page28
page27

USB(WLAN) SPI page 13~18

6*SATA serial BlueTooth CONN
page37

PCI Express SPI ROM USB1 CONN. page37

LPC BUS
Mini card Slot 3 BIOS+ME
3
page28 page13 USB2 CONN page37 3

Atheros 8131/32
EC USB3 CONN
ENE KB926E0 page37
SIM Card 10/100/1G LAN page34
page29
page28 USB(WWAN)
WWAN/3G page28
Card Reader
RJ45 CONN Touch Pad Int.KBD CONN
page30 page35 page38
page35
AD ESATA AND USB CONN
SPI ROM
G-sensor EC page37

page38 page36
CAP SENSOR BD: USB/JACK BD:
LS-5945P SATA HDD CONN
LS-5946P page32
4

USER/SG USB PORT1,2,3 4

MUTE HP JACK SSD Mini card Slot 1

page28
Power Saving MIC JACK
BUTTON & LED KILL SW Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 2 of 50
A B C D E
 A B C D E

DDR3 Voltage Rails

SMBUS Control Table
+5VS N11x
WLAN Thermal Cap sensor ALS PCH
+3VS SOURCE RAM BATT KB926 SODIMM CLK CHIP WWAN EMC1403
Sensor board
+1.5VS M2
SMB_EC_CK1
power +VCCP
SMB_EC_DA1
KB926 X V X X X X X X X X X
plane +3VALW +3VALW
+CPU_CORE
SMB_EC_CK2
1
+5VALW +1.5V
+VGA_CORE
SMB_EC_DA2
KB926 X X V X X X V
+3VS
V
+3VS
X
+3VS
V V 1

+1.8VS +3VALW +3VALW +3VALW

+B SMBCLK
+3VALW
+0.75VS
SMBDATA
PCH V X X V V X X X X X X
+3VALW +3VALW +3VS +3VS
+1.05VS
SML0CLK
State For SG SML0DATA
PCH
+3VALW
X X X X X X X X X X X
+3VS_DELAY SML1CLK
+1.8VS_VGA SML1DATA
PCH X X V X X X X X X X X
+3VALW
+1.5VS_VGA

S0
O O O O PCH, I2C / SMBUS ADDRESSING EC, I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS DEVICE HEX ADDRESS

S3
O O O X DDR SO-DIMM 0 A0 10100000 PCH 96/98,R/W 1001011X 1001100X
2
DDR SO-DIMM 1 A4 10100100 EMC1403 Thermal sensor 9A 1001101X 2
S5 S4/AC
O O X X CLOCK GENERATOR (EXT.) D2 11010010 N-vidia Thermal sensor 9E 1001111X
ALS 70/72,R/W 0111000X 0111001X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X

@ FUNCTION PCIE PORT LIST USB PORT LIST

PVT NON-USE
45@ (45 BOM) PORT DEVICE PORT DEVICE
100@ 10/100 LAN 1 NEW CARD 0 USB 1
GIGA@ GIGA LAN 2 WLAN 1 USB/ESATA
UMA_HDMI@ FOR UMA HDMI components 3 LAN 2 CMOS
HDMI@ FOR HDMI components 4 3G 3 USB 2
3
3G@ 3G(WWAN) function 5 4 3
X76@ (X76 BOM) 6 5 CARD READER
ESATA@ ESATA function 7 6 X HM55 disabled
CMOS@ Camera function 8 7 X HM55 disabled
SSD@ SSD w/ miniPCIE socket 8 WIRELESS
10M@ FOR 10M CHIP 9 USB 3
11M@ FOR 11M CHIP 10 FigerPrinter
UMA@ UMA only (Arranddale) SATA PORT LIST
11 BT
DIS@ DIS only (Arranddale) PORT DEVICE 12
VGA@ FOR NVIDIA PART 13 3G
HYBRID@ FOR SWITCHABLE 0 HDD
HU@ SWITCHABLE or UMA only 1 SSD
HD@ SWITCHABLE or DIS only 2,3 HM55 disabled
4 E-SATA
SKU 5

Arrandale(dGPU) DIS@ / 100@ for EVT

4 4
DIS only
Arrandale(iGPU) UMA@ / 100@ for EVT
UMA only
Arrandale(iGPU+dGPU) HYBRID@
SWITCHABLE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 3 of 50
A B C D E
 A B C D E

VGA and DDR3 Voltage Rails (N11M GPIO)

GPIO I/O ACTIVE Function Description

GPIO0 N/A N/A

GPIO1 IN - HDMI_DETECT_VGA

GPIO2 OUT H NV_INVTPWM

1 1

GPIO3 OUT H VGA_ENVDD_R The ramp time for any rail must be more than 40us
Power Sequence
GPIO4 OUT H VGA_ENABLT

GPIO5 OUT - GPU VID0

GPIO6 OUT - GPU VID1 (+3VS) VDD33

GPIO7 OUT -
PEX_VDD can ramp up any time
GPIO8 I/O L
(1.05VS)PEX_VDD
GPIO9 OUT L
tNVVDD
GPIO10 OUT

GPIO11 I/O L (+VGA_CORE) NVVDD

GPIO12 IN - tNV-IFPAB_IOVDD

2
GPIO13 OUT - (1.8VS)IFPAB_IOVDD 2

GPIO14 OUT -
tNV-FBVDDQ
GPIO15 IN -
(1.5VS) FBVDDQ
GPIO16 OUT -

GPIO17 IN -

GPIO18 IN -

GPIO19 IN -

GPIO20 IN -

GPIO21 IN -

GPIO22 IN -

GPIO23 I/O
3 3

GPIO5 GPIO6
Device ID GPU_VID0 GPU_VID1 VGA_CORE P-State
0 0 0.8V Deep P12
N11M-LP1
(40nm) 0x0A6E 0 1 0.85V P8
1 1 0.86V P0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 4 of 50
A B C D E
 5 4 3 2 1

DDR3 Compensation Signals

SM_RCOMP0 1 2
R567 100_0402_1%
SM_RCOMP1 1 2
R566 24.9_0402_1%
SM_RCOMP2 1 2
R565 130_0402_1%

D
Κ
Layout rule 10mil width trace
length < 0.5", spacing 20mil
Layout Note:Please these
resistors near Processor D

JCPU1B
20_0402_1% 1 R560 2COMP3 AT23 COMP3 CLK_CPU_BCLK
BCLK A16 CLK_CPU_BCLK 16 +VCCP

MISC
20_0402_1% 1 R558 2COMP2 AT24 COMP2 BCLK# B16 CLK_CPU_BCLK#
CLK_CPU_BCLK# 16
49.9_0402_1% 1 R548 2COMP1 CLK_CPU_ITP PM_EXTTS#0

CLOCKS
G16 COMP1 BCLK_ITP AR30 T17 PAD 1 2
AT30 CLK_CPU_ITP# T18 PAD R561 10K_0402_5%
49.9_0402_1% BCLK_ITP#
1 R557 2COMP0 AT26 COMP0
PM_EXTTS#1 1 2
E16 CLK_EXP R562 10K_0402_5%
PEG_CLK CLK_EXP 14
D16 CLK_EXP#
PEG_CLK# CLK_EXP# 14
TP_SKTOCC# AH24 SKTOCC#
DPLL_REF_SSCLK A18
DPLL_REF_SSCLK# A17
+VCCP 2 1 H_CATERR# AK14 XDP_PREQ# R136 1 @ 2 51_0402_1%
CATERR#

THERMAL
49.9_0402_1% R163
XDP_TMS R138 1 @ 2 51_0402_1%

16 H_PECI
R564
1
0_0402_5%
2 H_PECI_ISO AT15 PECI
SM_DRAMRST# F6 SM_DRAMRST# 3 only for Arrandale
XDP_TDI R556 1 @ 2 51_0402_1%
AL1 SM_RCOMP0 without EDP
SM_RCOMP[0]
+VCCP 2 R569 1 68_0402_5% SM_RCOMP[1] AM1 SM_RCOMP1 XDP_TDO R134 1 2 51_0402_5%
AN1 SM_RCOMP2
H_PROCHOT# SM_RCOMP[2]
34,48 H_PROCHOT# AN26 PROCHOT#
AN15 PM_EXTTS#0 XDP_TCK R57 1 @ 2 51_0402_1%
PM_EXT_TS#[0]

DDR3
MISC
AP15 PM_EXTTS#1 1 2
PM_EXT_TS#[1] PM_EXTTS#1_R 10,11
R563 0_0402_5% XDP_TRST# R133 1 2 51_0402_5%
H_THERMTRIP# AK15
16 H_THERMTRIP# THERMTRIP#

AT28 XDP_PRDY# T19 PAD R137

C PRDY# XDP_PREQ# XDP_DBRESET# @ C
PREQ# AP27 1 2 1K_0402_5% +3VS
SVT
@ AN28 XDP_TCK
TCK
2 1 H_CPURST#_R AP26 AP28 XDP_TMS
+VCCP RESET_OBS# TMS CHECK INTEL DOCUMENT #385422

PWR MANAGEMENT
68_0402_5% R135 AT27 XDP_TRST#
TRST#

JTAG & BPM

15 H_PM_SYNC 1 R187 2 H_PM_SYNC_R AL15 PM_SYNC TDI AT29 XDP_TDI Debug Port Design Guide Rev1.3
0_0402_5% AR27 XDP_TDO
TDO
TDI_M AR29
1 R190 2 VCCPWRGOOD_1 AN14 VCCPWRGOOD_1 TDO_M AP29 R555 2 1 0_0402_5%
0_0402_5%
AN25 XDP_DBRESET#
DBR#
16 H_CPUPWRGD 1 R139 2 VCCPWRGOOD_0 AN27 VCCPWRGOOD_0
0_0402_5%
AJ22 XDP_BPM#0
BPM#[0]
15 PM_DRAM_PWRGD 1 R191 2 VDDPWRGOOD_R AK13 SM_DRAMPWROK BPM#[1] AK22 XDP_BPM#1
0_0402_5% AK24 XDP_BPM#2
BPM#[2] XDP_BPM#3
BPM#[3] AJ24
46 VCCP_POK 2 1 VTT_POK AM15 AJ25 XDP_BPM#4
R184 VTTPWRGOOD BPM#[4] XDP_BPM#5
BPM#[5] AH22
FROM POWER VTT 1K_0402_1% AK23 XDP_BPM#6
BPM#[6]
2

AM26 AH23 XDP_BPM#7

POWER GOOD SIGNAL R183 TAPPWRGOOD BPM#[7]
R185
560_0402_5%
16,28,29 BUF_PLT_RST# 1 2 PLT_RST#_R AL14 RSTIN#
1

1.5K_0402_5%
1

R186 IC,AUB_CFD_rPGA,R1P0
750_0402_1% ME@
2

B B

For Intel S3 Power Reduction.

5 +1.5V +1.5V
For Intel S3 Power Reduction.
3
1

+3VALW

2
R193
1.1K_0402_1% R301
@ 1K_0402_1% @
5

U8
2

2 R195 1 2
P

1
VCCP_POK B DRAM_PWRGD VDDPWRGOOD_R 0_0402_5% R300
Y 4 1 2
1 A
G

1.5K_0402_1%
DDR3 CONNECTER
1

NC7SZ08P5X_NL_SC70-5 DRAMRST# SM_DRAMRST#

S
10,11 DRAMRST# 1 3
3

R194 R192
3K_0402_1% Q27
750_0402_1% 2N7002_SOT23 2 1

G
2
@ R283 100K_0402_5%
PCH GPIO CONTROL
2

16 DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL_R
R281 0_0402_5%

+5VALW
1
SVT
C338
2

0.047U_0402_16V7K
A R416 2 A
10K_0402_5% 6
1

S3_0.75V_EN 44
1

D
VCCP_POK 2 Q61
G 2N7002_SOT23
Security Classification Compal Secret Data Compal Electronics, Inc.
S Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(1/5)-Thermal/XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 5 of 50
5 4 3 2 1
 Κ
5 4 3 2 1

Layout rule trace

length < 0.5"

JCPU1A JCPU1E
B26 EXP_ICOMPI 1 R544 2 49.9_0402_1%
PEG_ICOMPI
PEG_ICOMPO A26 RSVD32 AJ13
15 DMI_CRX_PTX_N0 A24 DMI_RX#[0] PEG_RCOMPO B27 RSVD33 AJ12
15 DMI_CRX_PTX_N1 C23 A25 EXP_RBIAS 1 R545 2 750_0402_1%
DMI_RX#[1] PEG_RBIAS
15 DMI_CRX_PTX_N2 B22 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] 19 AP25 RSVD1
15 DMI_CRX_PTX_N3 A21 K35 PCIE_CRX_GTX_N15 AL25 AH25
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14 RSVD2 RSVD34
PEG_RX#[1] J34 AL24 RSVD3 RSVD35 AK26
15 DMI_CRX_PTX_P0 B24 J33 PCIE_CRX_GTX_N13 AL22
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12 RSVD4
15 DMI_CRX_PTX_P1 D23 DMI_RX[1] PEG_RX#[3] G35 AJ33 RSVD5 RSVD36 AL26

DMI
D B23 G32 PCIE_CRX_GTX_N11 AG9 AR2 D
15 DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] RSVD6 RSVD_NCTF_37
15 DMI_CRX_PTX_P3 A22 F34 PCIE_CRX_GTX_N10 M27
DMI_RX[3] PEG_RX#[5] PCIE_CRX_GTX_N9 RSVD7
PEG_RX#[6] F31 L28 RSVD8 RSVD38 AJ26
D24 D35 PCIE_CRX_GTX_N8 J17 AJ27
15 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] SA_DIMM_VREF RSVD39
G24 E33 PCIE_CRX_GTX_N7 H17
15 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] SB_DIMM_VREF
F23 C33 PCIE_CRX_GTX_N6 G25
15 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] RSVD11
H23 D32 PCIE_CRX_GTX_N5 G17
15 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] RSVD12
B32 PCIE_CRX_GTX_N4 E31 AP1
PEG_RX#[11] PCIE_CRX_GTX_N3 RSVD13 RSVD_NCTF_40
15 DMI_CTX_PRX_P0 D25 DMI_TX[0] PEG_RX#[12] C31 E30 RSVD14 RSVD_NCTF_41 AT2
F24 B28 PCIE_CRX_GTX_N2
15 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
E23 B30 PCIE_CRX_GTX_N1 AT3
15 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] RSVD_NCTF_42
G23 A31 PCIE_CRX_GTX_N0 AR1
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] RSVD_NCTF_43
PCIE_CRX_GTX_P[0..15] 19
J35 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] H34
H33 PCIE_CRX_GTX_P13 AL28
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_CRX_GTX_P12 CFG0 RSVD45
15 FDI_CTX_PRX_N0 E22 FDI_TX#[0] PEG_RX[3] F35 AM30 CFG[0] RSVD46 AL29
FDI_CTX_PRX_N1 D21 G33 PCIE_CRX_GTX_P11 AM28 AP30
15 FDI_CTX_PRX_N1 FDI_TX#[1] PEG_RX[4] CFG[1] RSVD47
FDI_CTX_PRX_N2 D19 E34 PCIE_CRX_GTX_P10 AP31 AP32
15 FDI_CTX_PRX_N2 FDI_TX#[2] PEG_RX[5] CFG[2] RSVD48
FDI_CTX_PRX_N3 D18 F32 PCIE_CRX_GTX_P9 CFG3 AL32 AL27
15 FDI_CTX_PRX_N3 FDI_TX#[3] PEG_RX[6] CFG[3] RSVD49
FDI_CTX_PRX_N4 G21 D34 PCIE_CRX_GTX_P8 CFG4 AL30 AT31
15 FDI_CTX_PRX_N4
FDI_CTX_PRX_N5 FDI_TX#[4] PEG_RX[7] PCIE_CRX_GTX_P7 PCIE Lane Numbers Reversed CFG[4] RSVD50

PCI EXPRESS -- GRAPHICS

15 FDI_CTX_PRX_N5 E19 FDI_TX#[5] PEG_RX[8] F33 AM31 CFG[5] RSVD51 AT32
FDI_CTX_PRX_N6 F21 B33 PCIE_CRX_GTX_P6 AN29 AP33
15 FDI_CTX_PRX_N6 FDI_TX#[6] PEG_RX[9] CFG[6] RSVD52
Intel(R) FDI
FDI_CTX_PRX_N7 G18 D31 PCIE_CRX_GTX_P5 @ R59 1 2 CFG7 AM32 AR33
15 FDI_CTX_PRX_N7 FDI_TX#[7] PEG_RX[10]
PEG_RX[11] A32
C30
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
CFG3-PCI Express Static Lane Reversal 3.01K_0402_1% AK32
AK31
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54 AT33
AT34

RESERVED
FDI_CTX_PRX_P0 PEG_RX[12] PCIE_CRX_GTX_P2 CFG[9] RSVD_NCTF_55
15 FDI_CTX_PRX_P0 D22 FDI_TX[0] PEG_RX[13] A28 AK28 CFG[10] RSVD_NCTF_56 AP35
FDI_CTX_PRX_P1 PCIE_CRX_GTX_P1
15 FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
C21 FDI_TX[1] PEG_RX[14] B29
PCIE_CRX_GTX_P0
FOR ES1 SAMPLE ONLY AJ28 CFG[11] RSVD_NCTF_57 AR35
15 FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
D20 FDI_TX[2] PEG_RX[15] A30 HYBRID@ AN30 CFG[12] RSVD58 AR32
15 FDI_CTX_PRX_P3 C18 FDI_TX[3] PCIE_CTX_GRX_N[0..15] 19 AN32 CFG[13]
FDI_CTX_PRX_P4 G22 L33 PCIE_CTX_GRX_C_N15 C527 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N15 AJ32
15 FDI_CTX_PRX_P4 FDI_TX[4] PEG_TX#[0] CFG[14]
FDI_CTX_PRX_P5 E20 M35 PCIE_CTX_GRX_C_N14 C540 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N14 AJ29 E15
C 15 FDI_CTX_PRX_P5 FDI_TX[5] PEG_TX#[1] CFG[15] RSVD_TP_59 C
FDI_CTX_PRX_P6 F20 M33 PCIE_CTX_GRX_C_N13 C529 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N13 AJ30 F15
15 FDI_CTX_PRX_P6 FDI_TX[6] PEG_TX#[2] CFG[16] RSVD_TP_60
FDI_CTX_PRX_P7 G19 M30 PCIE_CTX_GRX_C_N12 C542 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N12 AK30 A2
15 FDI_CTX_PRX_P7 FDI_TX[7] PEG_TX#[3] CFG[17] KEY
L31 PCIE_CTX_GRX_C_N11 C531 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N11 H16 D15 R189
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 C544 0.1U_0402_10V6K PCIE_CTX_GRX_N10 RSVD_TP_86 RSVD62 0_0402_5%
15 FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 1 2 RSVD63 C15
15 FDI_FSYNC1 FDI_FSYNC1 E17 M29 PCIE_CTX_GRX_C_N9 C533 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N9 AJ15 RSVD64_R 2 @ 1
FDI_FSYNC[1] PEG_TX#[6] PCIE_CTX_GRX_C_N8 C546 0.1U_0402_10V6K PCIE_CTX_GRX_N8 RSVD64 RSVD65_R 2 @
PEG_TX#[7] J31 1 2 RSVD65 AH15 1
15 FDI_INT FDI_INT C17 K29 PCIE_CTX_GRX_C_N7 C535 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N7 R188
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_C_N6 C562 0.1U_0402_10V6K PCIE_CTX_GRX_N6 0_0402_5%
PEG_TX#[9] H30 1 2 B19 RSVD15
15 FDI_LSYNC0 FDI_LSYNC0 F18 H29 PCIE_CTX_GRX_C_N5 C564 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N5 R547 A19
FDI_LSYNC1 FDI_LSYNC[0] PEG_TX#[10] PCIE_CTX_GRX_C_N4 C555 0.1U_0402_10V6K PCIE_CTX_GRX_N4 0_0402_5% RSVD16
15 FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29 1 2
E28 PCIE_CTX_GRX_C_N3 C557 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N3 1 @ 2 H_RSVD17_R A20
PEG_TX#[12] PCIE_CTX_GRX_C_N2 C561 0.1U_0402_10V6K PCIE_CTX_GRX_N2 @ H_RSVD18_R RSVD17
PEG_TX#[13] D29 1 2 1 2 B20 RSVD18
D27 PCIE_CTX_GRX_C_N1 C548 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N1 AA5
PEG_TX#[14] PCIE_CTX_GRX_C_N0 C559 0.1U_0402_10V6K PCIE_CTX_GRX_N0 R546 RSVD_TP_66
PEG_TX#[15] C26 1 2 U9 RSVD19 RSVD_TP_67 AA4
0_0402_5% T9 R8
PCIE_CTX_GRX_P[0..15] 19 RSVD20 RSVD_TP_68
L34 PCIE_CTX_GRX_C_P15 C528 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P15 AD3
PEG_TX[0] PCIE_CTX_GRX_C_P14 C541 0.1U_0402_10V6K PCIE_CTX_GRX_P14 RSVD_TP_69
PEG_TX[1] M34 1 2 AC9 RSVD21 RSVD_TP_70 AD2
M32 PCIE_CTX_GRX_C_P13 C530 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P13 AB9 AA2
PEG_TX[2] PCIE_CTX_GRX_C_P12 C543 0.1U_0402_10V6K PCIE_CTX_GRX_P12 RSVD22 RSVD_TP_71
PEG_TX[3] L30 1 2 RSVD_TP_72 AA1
M31 PCIE_CTX_GRX_C_P11 C532 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P11 R9
PEG_TX[4] PCIE_CTX_GRX_C_P10 C545 0.1U_0402_10V6K PCIE_CTX_GRX_P10 RSVD_TP_73
PEG_TX[5] K31 1 2 RSVD_TP_74 AG7
M28 PCIE_CTX_GRX_C_P9 C534 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P9 C1 AE3
PEG_TX[6] PCIE_CTX_GRX_C_P8 C547 0.1U_0402_10V6K PCIE_CTX_GRX_P8 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[7] H31 1 2 A3 RSVD_NCTF_24
K28 PCIE_CTX_GRX_C_P7 C536 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P7
PEG_TX[8] PCIE_CTX_GRX_C_P6 C563 0.1U_0402_10V6K PCIE_CTX_GRX_P6
PEG_TX[9] G30 1 2 RSVD_TP_76 V4
G29 PCIE_CTX_GRX_C_P5 C565 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P5 V5
PEG_TX[10]
PEG_TX[11] F28
E27
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
C556
C558
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
CFG Straps for PROCESSOR J29
RSVD_TP_77
RSVD_TP_78 N2
AD5
PEG_TX[12] PCIE_CTX_GRX_C_P2 C560 0.1U_0402_10V6K PCIE_CTX_GRX_P2 RSVD26 RSVD_TP_79
PEG_TX[13] D28 1 2 J28 RSVD27 RSVD_TP_80 AD7
C27 PCIE_CTX_GRX_C_P1 C549 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P1 W3
PEG_TX[14] PCIE_CTX_GRX_C_P0 C550 0.1U_0402_10V6K PCIE_CTX_GRX_P0 RSVD_TP_81
PEG_TX[15] C25 1 2 A34 RSVD_NCTF_28 RSVD_TP_82 W2
A33 RSVD_NCTF_29 RSVD_TP_83 N3
B CFG0 1 @ 2 AE5 B
R58 3.01K_0402_1% RSVD_TP_84
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
IC,AUB_CFD_rPGA,R1P0 B35
ME@ PCI-Express Configuration Select RSVD_NCTF_31
1: Single PEG AP34
CFG0 0: Bifurcation enabled VSS
Not applicable for Clarksfield Processor

CFG[1:0] 11=1*16 PEG

10=2*8 PEG IC,AUB_CFD_rPGA,R1P0
ME@

FDI_FSYNC0 R532 1 HYBRID@

2 1K_0402_5% CFG3 1 2
R61 3.01K_0402_1%
FDI_FSYNC1 R536 1 HYBRID@
2 1K_0402_5%
CFG3-PCI Express Static Lane Reversal
FDI_INT R534 1 HYBRID@
2 1K_0402_5% 1: Normal Operation
CFG3 0: Lane Numbers Reversed
FDI_LSYNC0 R533 1 HYBRID@
2 1K_0402_5% 15 -> 0, 14 ->1, .....

FDI_LSYNC1 R535 1 HYBRID@

2 1K_0402_5% @
CFG4 1 2
R60 3.01K_0402_1%

CFG4-Display Port Presence

1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
device is connected to the Embedded
Display Port
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(2/5)-DMI/PEG/FDI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 6 of 50
5 4 3 2 1
 5 4 3 2 1

JCPU1D
JCPU1C

11 DDR_B_D[0..63] SB_CK[0] W8 M_CLK_DDR2 11

D AA6 W9 D
SA_CK[0] M_CLK_DDR0 10 SB_CK#[0] M_CLK_DDR#2 11
AA7 DDR_B_D0 B5 M3
10 DDR_A_D[0..63] SA_CK#[0] M_CLK_DDR#0 10 SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB 11
P7 DDR_B_D1 A5
SA_CKE[0] DDR_CKE0_DIMMA 10 SB_DQ[1]
DDR_A_D0 A10 DDR_B_D2 C3
DDR_A_D1 SA_DQ[0] DDR_B_D3 SB_DQ[2]
C10 SA_DQ[1] B3 SB_DQ[3] SB_CK[1] V7 M_CLK_DDR3 11
DDR_A_D2 C7 DDR_B_D4 E4 V6
SA_DQ[2] SB_DQ[4] SB_CK#[1] M_CLK_DDR#3 11
DDR_A_D3 A7 Y6 DDR_B_D5 A6 M2
SA_DQ[3] SA_CK[1] M_CLK_DDR1 10 SB_DQ[5] SB_CKE[1] DDR_CKE3_DIMMB 11
DDR_A_D4 B10 Y5 DDR_B_D6 A4
SA_DQ[4] SA_CK#[1] M_CLK_DDR#1 10 SB_DQ[6]
DDR_A_D5 D10 P6 DDR_B_D7 C4
SA_DQ[5] SA_CKE[1] DDR_CKE1_DIMMA 10 SB_DQ[7]
DDR_A_D6 E10 DDR_B_D8 D1
DDR_A_D7 SA_DQ[6] DDR_B_D9 SB_DQ[8]
A8 SA_DQ[7] D2 SB_DQ[9]
DDR_A_D8 D8 DDR_B_D10 F2 AB8
SA_DQ[8] SB_DQ[10] SB_CS#[0] DDR_CS2_DIMMB# 11
DDR_A_D9 F10 AE2 DDR_B_D11 F1 AD6
SA_DQ[9] SA_CS#[0] DDR_CS0_DIMMA# 10 SB_DQ[11] SB_CS#[1] DDR_CS3_DIMMB# 11
DDR_A_D10 E6 AE8 DDR_B_D12 C2
SA_DQ[10] SA_CS#[1] DDR_CS1_DIMMA# 10 SB_DQ[12]
DDR_A_D11 F7 DDR_B_D13 F5
DDR_A_D12 SA_DQ[11] DDR_B_D14 SB_DQ[13]
E9 SA_DQ[12] F3 SB_DQ[14]
DDR_A_D13 B7 DDR_B_D15 G4 AC7
SA_DQ[13] SB_DQ[15] SB_ODT[0] M_ODT2 11
DDR_A_D14 E7 AD8 DDR_B_D16 H6 AD1
SA_DQ[14] SA_ODT[0] M_ODT0 10 SB_DQ[16] SB_ODT[1] M_ODT3 11
DDR_A_D15 C6 AF9 DDR_B_D17 G2
SA_DQ[15] SA_ODT[1] M_ODT1 10 SB_DQ[17]
DDR_A_D16 H10 DDR_B_D18 J6
DDR_A_D17 SA_DQ[16] DDR_B_D19 SB_DQ[18]
G8 SA_DQ[17] J3 SB_DQ[19]
DDR_A_D18 K7 DDR_B_D20 G1
SA_DQ[18] SB_DQ[20] DDR_B_DM[0..7] 11
DDR_A_D19 J8 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D20 SA_DQ[19] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
G7 SA_DQ[20] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D21 G10 DDR_B_D23 J1 H3 DDR_B_DM2
SA_DQ[21] DDR_A_DM[0..7] 10 SB_DQ[23] SB_DM[2]
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
J10 SA_DQ[23] SA_DM[1] D7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M6 SA_DQ[25] SA_DM[3] M7 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D28 K5 AT8 DDR_B_DM7
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D29 SB_DQ[28] SB_DM[7]
L9 SA_DQ[27] SA_DM[5] AM7 K4 SB_DQ[29]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D30 M4
C DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D31 SB_DQ[30] C
K8 SA_DQ[29] SA_DM[7] AN13 N5 SB_DQ[31]
DDR_A_D30 N8 DDR_B_D32 AF3
DDR_A_D31 SA_DQ[30] DDR_B_D33 SB_DQ[32]
P9 SA_DQ[31] AG1 SB_DQ[33] DDR_B_DQS#[0..7] 11
DDR_A_D32 AH5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
DDR_A_D33 SA_DQ[32] DDR_B_D35 SB_DQ[34] SB_DQS#[0] DDR_B_DQS#1
AF5 SA_DQ[33] DDR_A_DQS#[0..7] 10 AK1 SB_DQ[35] SB_DQS#[1] F4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D36 AG4 J4 DDR_B_DQS#2
SA_DQ[34] SA_DQS#[0] SB_DQ[36] SB_DQS#[2]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D37 AG3 L4 DDR_B_DQS#3

DDR_A_D36 SA_DQ[35] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D38 SB_DQ[37] SB_DQS#[3] DDR_B_DQS#4
AF6 SA_DQ[36] SA_DQS#[2] J9 AJ4 SB_DQ[38] SB_DQS#[4] AH2

DDR SYSTEM MEMORY - B

DDR_A_D37 AG5 N9 DDR_A_DQS#3 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D38 SA_DQ[37] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D40 SA_DQ[39] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AM6 SB_DQ[42]
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D43 AN2
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D44 SB_DQ[43]
AL10 SA_DQ[42] AK5 SB_DQ[44]
DDR_A_D43 AK12 DDR_B_D45 AK2
DDR_A_D44 SA_DQ[43] DDR_B_D46 SB_DQ[45]
AK8 SA_DQ[44] AM4 SB_DQ[46]
DDR_A_D45 AL7 DDR_B_D47 AM3
SA_DQ[45] DDR_A_DQS[0..7] 10 SB_DQ[47] DDR_B_DQS[0..7] 11
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AL8 SA_DQ[47] SA_DQS[1] F9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AM10 SA_DQ[49] SA_DQS[3] M9 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AL11 SA_DQ[51] SA_DQS[5] AK10 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AN9 SA_DQ[53] SA_DQS[7] AR13 AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D54 AT11 DDR_B_D56 AN7
DDR_A_D55 SA_DQ[54] DDR_B_D57 SB_DQ[56]
AP12 SA_DQ[55] AP6 SB_DQ[57]
DDR_A_D56 AM12 DDR_B_D58 AP8
DDR_A_D57 SA_DQ[56] DDR_B_D59 SB_DQ[58]
AN12 SA_DQ[57] DDR_A_MA[0..15] 10 AT9 SB_DQ[59]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D60 AT7
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D61 SB_DQ[60]
AT14 SA_DQ[59] SA_MA[1] W1 AP9 SB_DQ[61]
DDR_A_D60 AT12 AA8 DDR_A_MA2 DDR_B_D62 AR10
B SA_DQ[60] SA_MA[2] SB_DQ[62] DDR_B_MA[0..15] 11 B
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_DQ[63] SB_MA[0] DDR_B_MA1
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[1] V2
DDR_A_D63 AP14 AA9 DDR_A_MA5 T5 DDR_B_MA2
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[2] DDR_B_MA3
SA_MA[6] V8 SB_MA[3] V3
T1 DDR_A_MA7 R1 DDR_B_MA4
SA_MA[7] DDR_A_MA8 SB_MA[4] DDR_B_MA5
SA_MA[8] Y9 11 DDR_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
AC3 U6 DDR_A_MA9 W5 R2 DDR_B_MA6
10 DDR_A_BS0 SA_BS[0] SA_MA[9] 11 DDR_B_BS1 SB_BS[1] SB_MA[6]
AB2 AD4 DDR_A_MA10 R7 R6 DDR_B_MA7
10 DDR_A_BS1 SA_BS[1] SA_MA[10] 11 DDR_B_BS2 SB_BS[2] SB_MA[7]
U7 T2 DDR_A_MA11 R4 DDR_B_MA8
10 DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[8]
U3 DDR_A_MA12 R5 DDR_B_MA9
SA_MA[12] DDR_A_MA13 SB_MA[9] DDR_B_MA10
SA_MA[13] AG8 11 DDR_B_CAS# AC5 SB_CAS# SB_MA[10] AB5
T3 DDR_A_MA14 Y7 P3 DDR_B_MA11
SA_MA[14] 11 DDR_B_RAS# SB_RAS# SB_MA[11]
AE1 V9 DDR_A_MA15 AC6 R3 DDR_B_MA12
10 DDR_A_CAS# SA_CAS# SA_MA[15] 11 DDR_B_WE# SB_WE# SB_MA[12]
AB3 AF7 DDR_B_MA13
10 DDR_A_RAS# SA_RAS# SB_MA[13]
AE9 P5 DDR_B_MA14
10 DDR_A_WE# SA_WE# SB_MA[14]
N1 DDR_B_MA15
SB_MA[15]

IC,AUB_CFD_rPGA,R1P0
ME@

IC,AUB_CFD_rPGA,R1P0
ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(3/5)-DDR III
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 7 of 50
5 4 3 2 1
 5 4 3 2 1

AS NO CONNECT R132
GFX_IMON_R 2 1 1K_0402_5%
BUT A SMALL AMOUNT OF POWER
HYBRID@

1
D
+CPU_CORE
(~15MW) MAYBE WASTED
DGPU_SELECT 2 HYBRID@
G Q58
JCPU1F +GFX_CORE DESIGN GUIDE REV1.1 S 2N7002_SOT23

3
JCPU1G
22U_0805_6.3V6M 10U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 47
AT18 AT22

SENSE
LINES
1 1 1 1 1 1 1 1 1 VAXG3 VSSAXG_SENSE VSS_AXG_SENSE 47
+VCCP C161 C160 C191 C190 C189 C159 C591 C592
48A 18A + @ @ @ @
AT16 VAXG4 15A
AR21 VAXG5
D AG35 AH14 C673 AR19 D
VCC1 VTT0_1 2 2 2 2 2 2 2 2 VAXG6

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AG34 AH12 330U_D2E_2.5VM_LESR9M AR18
VCC2 VTT0_2 2 VAXG7 R140
AG33 VCC3 VTT0_3 AH11 1 AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 47

C201

C199

C198

C181
AG32 AH10 1 1 1 1 AP21 AP22 330_0402_5%
VCC4 VTT0_4 + VAXG9 GFX_VID[1] GFXVR_VID_1 47
22U_0805_6.3V6M 22U_0805_6.3V6M GFX_VR_EN

GRAPHICS VIDs
AG31 VCC5 VTT0_5 J14 AP19 VAXG10 GFX_VID[2] AN22 GFXVR_VID_2 47 1 2
AG30 J13 C554 22U_0805_6.3V6M 10U_0805_6.3V6M AP18 AP23
VCC6 VTT0_6 VAXG11 GFX_VID[3] GFXVR_VID_3 47
AG29 H14 330U_D2E_2.5VM_LESR9M AP16 AM23
VCC7 VTT0_7 2 2 2 2 2 VAXG12 GFX_VID[4] GFXVR_VID_4 47
AG28 VCC8 VTT0_8 H12 AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 47

GRAPHICS
AG27 VCC9 VTT0_9 G14 AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 47
AG26 VCC10 VTT0_10 G13 AN18 VAXG15
AF35 VCC11 VTT0_11 G12 AN16 VAXG16

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AF34 VCC12 VTT0_12 G11 AM21 VAXG17 GFX_VR_EN AR25 GFX_VR_EN 1 2 R141 0_0402_5%
GFXVR_EN 47
AF33 F14 AM19 AT25 @
VCC13 VTT0_13 VAXG18 GFX_DPRSLPVR PAD T16

C271

C270

C216

C182

C200
AF32 VCC14 VTT0_14 F13 1 1 1 1 1 AM18 VAXG19 GFX_IMON AM24 GFX_IMON_R GFXVR_IMON 47
AF31 F12 @ @ AM16
VCC15 VTT0_15 VAXG20
AF30 VCC16 VTT0_16 F11 AL21 VAXG21
AF29 VCC17 VTT0_17 E14 AL19 VAXG22
2 2 2 2 2 +1.5V_DDR3
AF28 E12 AL18
AF27
AF26
VCC18
VCC19
VCC20
VTT0_18
VTT0_19
VTT0_20
D14
D13
AL16
AK21
VAXG23
VAXG24
VAXG25 VDDQ1 AJ1
1
+VCCP

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K
AD35 D12 AK19 AF1
1.1V RAIL POWER

VCC21 VTT0_21 VAXG26 VDDQ2

C254

C256

C253

C255

C257
AD34 D11 AK18 AE7

- 1.5V RAILS
VCC22 VTT0_22 VAXG27 VDDQ3 1 1 1 1 1
AD33 VCC23 VTT0_23 C14 AK16 VAXG28 VDDQ4 AE4
AD32 VCC24 VTT0_24 C13 AJ21 VAXG29 VDDQ5 AC1

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AD31 VCC25 VTT0_25 C12 AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2
AD30 VCC26 VTT0_26 C11 AJ18 VAXG31 VDDQ7 AB4

C219

C217

C274

C207
AD29 VCC27 VTT0_27 B14 1 1 1 1 AJ16 VAXG32 VDDQ8 Y1
AD28 VCC28 VTT0_28 B12 AH21 VAXG33 VDDQ9 W7

POWER
AD27 VCC29 VTT0_29 A14 AH19 VAXG34 3A VDDQ10 W4
AD26 VCC30 VTT0_30 A13 AH18 VAXG35 VDDQ11 U1
2 2 2 2

220U_B2_2.5VM_R35

10U_0805_6.3V6M

10U_0805_6.3V6M
AC35 VCC31 VTT0_31 A12 AH16 VAXG36 VDDQ12 T7
AC34 VCC32 VTT0_32 A11 VDDQ13 T4 1

C268

C252

C258
C AC33 P1 C
VCC33 VDDQ14 1 1
AC32 +VCCP N7 +
VCC34 +VCCP VDDQ15
AC31 VCC35 VDDQ16 N4

DDR3
AC30 VCC36 VTT0_33 AF10 VDDQ17 L1
2 2 2
10U_0805_6.3V6M

10U_0805_6.3V6M

AC29 VCC37 VTT0_34 AE10 J24 VTT1_45 VDDQ18 H1

10U_0805_6.3V6M

10U_0805_6.3V6M

FDI
AC28 VCC38 VTT0_35 AC10 J23 VTT1_46
CPU CORE SUPPLY

C208

C209

AC27 AB10 1 1 R282 0_0402_5% H25

VCC39 VTT0_36 VTT1_47 +VCCP

C210

C211
AC26 Y10 SVT H_PSI#_R 2 1 1 1
VCC40 VTT0_37 STRIP PIN PSI# 48
AA35 VCC41 VTT0_38 W10

2
AA34 VCC42 VTT0_39 U10 VTT0_59 P10
2 2

10U_0805_6.3V6M

10U_0805_6.3V6M
AA33 T10 R551 @ R550 N10
VCC43 VTT0_40 1K_0402_1% 2 2 VTT0_60

C
AA32 VCC44 VTT0_41 J12 3 1 1K_0402_1% VTT0_61 L10

C273

C212
E
AA31 VCC45 VTT0_42 J11 @ VTT0_62 K10 1 1
AA30 J16 Q18
2

1
VCC46 VTT0_43 MMBT3906_SOT23-3

B
AA29 J15

2
VCC47 VTT0_44
AA28 VCC48

1
C +VCCP 2 2
AA27 VCC49

1.1V
AA26 VCC50 34 PSI_ON# 1 R182 2 2 Q51
VTT1_63 J22
Y35 B MMST3904-7-F_SOT323-3 K26 J20 +VCCP
VCC51 VTT1_48 VTT1_64

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
Y34 10K_0402_5% E @ J27 J18

3
VCC52 VTT1_49 VTT1_65

PEG & DMI

Y33 VCC53 @ J26 VTT1_50 VTT1_66 H21

C214

C215

C272

C240

10U_0805_6.3V6M

10U_0805_6.3V6M
Y32 VCC54 1 1 1 1 J25 VTT1_51 VTT1_67 H20
Y31 VCC55 H27 VTT1_52 VTT1_68 H19

C218

C213
Y30 VCC56 Lenovo Request G28 VTT1_53 1 1
Y29 VCC57 G27 VTT1_54
2 2 2 2
Y28 VCC58 G26 VTT1_55
Y27 VCC59 F26 VTT1_56 2 2
Y26 VCC60 E26 VTT1_57 VCCPLL1 L26

1.8V
V35 AN33 H_PSI#_R E25 L27
VCC61 PSI# VTT1_58 VCCPLL2 +1.8VS
V34 0.6A M26
POWER

VCC62 VCCPLL3
V33 VCC63
V32 AK35 H_VID0
VCC64 VID[0] H_VID0 48

1U_0603_10V6K

1U_0603_10V6K

2.2U_0603_6.3V6K

10U_0805_6.3V6M

4.7U_0603_6.3V6K
B V31 AK33 H_VID1 B
VCC65 VID[1] H_VID1 48

C167

C149

C168

C169

C170
V30 AK34 H_VID2 1 1 1 1 1
VCC66 VID[2] H_VID2 48
V29 AL35 H_VID3
VCC67 VID[3] H_VID3 48
CPU VIDS

V28 AL33 H_VID4

VCC68 VID[4] H_VID4 48
V27 AM33 H_VID5
VCC69 VID[5] H_VID5 48 2 2 2 2 2
V26 AM35 H_VID6 IC,AUB_CFD_rPGA,R1P0
VCC70 VID[6] H_VID6 48
U35 AM34 PM_DPRSLPVR_R 1 2 ME@
VCC71 PROC_DPRSLPVR PROC_DPRSLPVR 48
U34 R56 0_0402_5%
VCC72
U33 For Intel S3 Power Reduction.
U32
U31
VCC73
VCC74
VCC75 VTT_SELECT G15 VTT_SELECT VTT_SELECT 46
1 +1.5V
2
J3
2 1 1
+1.5V_DDR3

U30 VCC76

@
U29 JUMP_43X118
VCC77 J2
U28 VCC78
H_VTTVID1 = Low, 1.1V FOR Clarksfiel
U27 VCC79 2 2 1 1
U26 H_VTTVID1 = High, 1.05V FOR Auburndale +1.5V_DDR3
VCC80 +1.5V
2

@
R35 JUMP_43X118
VCC81
R34 VCC82
CPU

0.1U_0402_10V6K
C269
R33 VCC83 1

1
R32 AN35 IMVP_IMON 48 U11
VCC84 ISENSE @ R233
R31 VCC85 8 D S 1
R30 +5VALW 7 2 220_0402_5%
VCC86 D S 2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R29 VCC87 6 D S 3

C289

C288

C287

C286
R28 AJ34 VCCSENSE 5 4 1 1 1 1
SENSE LINES

VCCSENSE 48

1 2
VCC88 VCC_SENSE D G
1

R27 AJ35 VSSSENSE

VCC89 VSS_SENSE VSSSENSE 48 D
R26 R268 SI4800BDY-T1-E3_SO8
VCC90 SVT,timing 47K_0402_1% SUSP Q19
P35 VCC91 2
+1.5V_DDR3 2 2 2 2 G 2N7002_SOT23
P34 VCC92 VTT_SENSE B15 VTT_SENSE 46
P33 A15 R267 0_0402_5% S
2

3
VCC93 VSS_SENSE_VTT @ PAD T15 1.5_SUS- PVT
P32 VCC94 2 11.5V_DDR3_GATE
P31 VCC95 1
1

D
P30 VCC96
A P29 2 Q23 C325 A
VCC97 39,44,45 SUSP
P28 G 2N7002_SOT23 0.1U_0603_25V7K
VCC98 2
P27 S
3

VCC99
P26 VCC100 For Intel S3 Power Reduction.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(4/5)-PWR
IC,AUB_CFD_rPGA,R1P0 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ME@ Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 8 of 50
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
CPU CORE
JCPU1H JCPU1I

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AT20 VSS1 VSS81 AE34

C568

C585

C580

C579

C574

C573

C584

C578

C583

C577

C572

C571
AT17 AE33
AR31
VSS2
VSS3
VSS82
VSS83 AE32 K27 VSS161
1 1 1 1 1 1 1 1 1 1 1 1
Inside cavity
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163 2 2 2 2 2 2 2 2 2 2 2 2
AR24 VSS6 VSS86 AE29 K3 VSS164
AR23 VSS7 VSS87 AE28 J32 VSS165
AR20 VSS8 VSS88 AE27 J30 VSS166
D AR17 AE26 J21 D
VSS9 VSS89 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171

C147

C163

C162

C179

C193

C166

C148

C165

C194
AR3 VSS14 VSS94 AC2 H26 VSS172 1 1 1 1 1 1 1 1 1
AP20 AB35 H24
AP17
VSS15
VSS16
VSS95
VSS96 AB34 H22
VSS173
VSS174
between Inductor and socket
AP13 VSS17 VSS97 AB33 H18 VSS175 2 2 2 2 2 2 2 2 2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180

330U_D2E_2.5VM_LESR9M

330U_D2E_2.5VM_LESR9M

330U_D2E_2.5VM_LESR9M

330U_D2E_2.5VM_LESR9M
AN31 VSS23 VSS103 AB27 H2 VSS181

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
AN23 VSS24 VSS104 AB26 G34 VSS182
AN20 VSS25 VSS105 AB6 G31 VSS183 1 1 1 1

C195

C192

C88

C196

C180

C89

C197

C91

C90

C87

C129
AN17 VSS26 VSS106 AA10 G20 VSS184 1 1 1 1 1 1 1 1 1 1 1

C75

C76

C92

C164
AM29 Y8 G9 + + + +
VSS27 VSS107 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 W31 F19
AM5
VSS34
VSS35
VSS114
VSS115 W30 F16
VSS192
VSS193
Under cavity
AM2 VSS36 VSS116 W29 E35 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS PVT, change from 470uF 4.5mohm
to 330uF 6mohm and 2nd 470uF 7mohm by power;
AL20 VSS40 VSS120 W6 E21 VSS198 '10 1/8 update main to 330uF 9m ohm
C AL17 V10 E18 C
VSS41 VSS121 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 T34 E2 AT35 VSS_NCTF1_R
VSS46 VSS126 VSS204 VSS_NCTF1 VSS_NCTF2_R
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 T32 D30 AR34 VSS_NCTF3_R
VSS48 VSS128 VSS206 VSS_NCTF3 VSS_NCTF4_R
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
AK17 T30 D9 B2 VSS_NCTF5_R

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 VSS_NCTF6_R
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1
AJ23 T28 D3 A35 VSS_NCTF7_R
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
B AH9 L32 A27 B
VSS73 VSS153 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Arrandale(5/5)-GND/Bypass
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 9 of 50
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMA +1.5V +1.5V

4BA2/6W
7 DDR_A_D[0..63] +1.5V
DDR3 SO-DIMM A 7 DDR_A_DM[0..7]

1
JDIMM1
7 DDR_A_DQS[0..7]
+VREF_DQ_DIMMA 1 2 R297
VREF_DQ VSS1 DDR_A_D4 1K_0402_1%
3 VSS2 DQ4 4 7 DDR_A_DQS#[0..7] +VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C303

C347
1 1 DDR_A_D1 7 8 7 DDR_A_MA[0..15]

2
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS5 VSS6 14

1
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
D DDR_A_D3 17 18 DDR_A_D7 D
DQ3 DQ7 R305
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12 1K_0402_1%
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24

2
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DRAMRST#
29 DQS1 RESET# 30 DRAMRST# 5,11
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36 For Arranale only +VREF_DQ_DIMMA
37 VSS13 VSS14 38
DDR_A_D16 39 DQ16 DQ20 40 DDR_A_D20 supply from a external 1.5V voltage divide
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21 circuit.
43 VSS15 VSS16 44
DDR_A_DQS#2 45 DQS#2 DM2 46 DDR_A_DM2 07/17/2009
DDR_A_DQS2 47 48
DQS2 VSS17 DDR_A_D22
49 VSS18 DQ22 50
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_A_D28
DDR_A_D24 VSS20 DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60
DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

7 DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

C CKE0 CKE1 DDR_CKE1_DIMMA 7 C
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
7 DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
7 M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 7
7 M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 7
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 7
7 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# 7
111 VDD13 VDD14 112
7 DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA#
WE# S0# DDR_CS0_DIMMA# 7
7 DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 7
117 VDD15 VDD16 118
DDR_A_MA13 119 120 M_ODT1
A13 ODT1 M_ODT1 7 +VREF_DQ_DIMMA
7 DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2
123 VDD17 VDD18 124 Layout Note:
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128 Place near DIMM
0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

C346

C355
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 DDR_A_DM4
DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
B DDR_A_D38 2 2 B
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39 +1.5V
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_A_D44
VSS34 DQ44

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_D40 147 148 DDR_A_D45
DQ40 DQ45

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DDR_A_D41 149 150 1
DQ41 VSS35

C589

C588

C586

C581

C310

C309

C570

C308

C314

C315

C317

C316
151 152 DDR_A_DQS#5 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5 + C569
153 DM5 DQS5 154
155 156 VDDQ(1.5V) = 220U_B2_2.5VM_R35
DDR_A_D42 VSS37 VSS38 DDR_A_D46 @ @
157 DQ42 DQ46 158
DDR_A_D43 DDR_A_D47 2 2 2 2 2 2 2 2 2 2 2 2 2
159 DQ43 DQ47 160 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52 6*0603 10uf (PER CONNECTOR)
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6 VTT(0.75V) =
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54 3*0805 10uf 4*0402 1uf
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 VREF =
DQ51 VSS45 DDR_A_D60 +0.75VS
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 VDDSPD (3.3V)=
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188

C605

1U_0603_10V6K

C607

1U_0603_10V6K

C606

C300

1U_0603_10V6K

C301

10U_0603_6.3V6M
1U_0603_10V6K
189 VSS49 VSS50 190 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D58 191 192 DDR_A_D62 1 1 1 1 1
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
1 R570 2 195 VSS51 VSS52 196
10K_0402_5% 197 198 PM_EXTTS#1_R
SA0 EVENT# PM_EXTTS#1_R 5,11 2 2 2 2 2
199 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 11,12,14,28
2.2U_0603_6.3V6K

0.1U_0402_10V6K

201 202 SMB_CLK_S3

SA1 SCL SMB_CLK_S3 11,12,14,28
C608

C617

A 203 204 A
1 1 VTT1 VTT2 +0.75VS
1 10K_0402_5%
R571

205 206 1/76BA1/86W

G1 G2
2 2 FOX_AS0A626-U4SN-7F
ME@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 10 of 50
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ_DIMMB +1.5V 4BA2/6W +1.5V

7 DDR_B_DQS#[0..7]

7 DDR_B_D[0..63]
+1.5V
7 DDR_B_DM[0..7]
JDIMM2
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS1 7 DDR_B_DQS[0..7]

1
3 4 DDR_B_D4
VSS2 DQ4
2.2U_0603_6.3V6K

0.1U_0402_10V6K
DDR_B_D0 5 6 DDR_B_D5 R341
DQ0 DQ5 7 DDR_B_MA[0..15]
1 1 DDR_B_D1 7 8 1K_0402_1%
DQ1 VSS3 DDR_B_DQS#0 +VREF_DQ_DIMMB
9 VSS4 DQS#0 10
C382

C384
DDR_B_DM0 11 12 DDR_B_DQS0

2
DM0 DQS0
13 VSS5 VSS6 14
2 2 DDR_B_D2 DDR_B_D6
15 DQ2 DQ6 16
D DDR_B_D3 17 18 DDR_B_D7 D
DQ3 DQ7

1
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13 R340
23 DQ9 DQ13 24
25 26 1K_0402_1%
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
27 28

2
DDR_B_DQS1 DQS#1 DM1 DRAMRST#
29 DQS1 RESET# 30 DRAMRST# 5,10
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20 For Arranale only +VREF_DQ_DIMMB
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44 supply from a external 1.5V voltage divide
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2 circuit.
47 DQS2 VSS17 48
49 VSS18 DQ22 50 DDR_B_D22 07/17/2009
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_B_D28
DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 DQ24 DQ29 58
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

7 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

C CKE0 CKE1 DDR_CKE3_DIMMB 7 C
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
7 DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
7 M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 7
7 M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 7
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1 Layout Note:
A10/AP BA1 DDR_B_BS1 7
7 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# 7
111 112 Place near DIMM
DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB#
7 DDR_B_WE# 113 WE# S0# 114 DDR_CS2_DIMMB# 7
7 DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 7
117 VDD15 VDD16 118
DDR_B_MA13 119 120 M_ODT3
A13 ODT1 M_ODT3 7 +VREF_DQ_DIMMB
7 DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 VDD17 VDD18 124
125 126 +1.5V
NCTEST VREF_CA
0.1U_0402_10V6K

2.2U_0603_6.3V6K
127 VSS27 VSS28 128
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C385

C383

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
133 VSS29 VSS30 134

C582

C587

C576

C311

C313

C590

C575

C312

C307

C304

C305

C306
DDR_B_DQS#4 135 136 DDR_B_DM4 1 1 1 1 1 1 1 1 1 1 1 1
DDR_B_DQS4 DQS#4 DM4
137 DQS4 VSS31 138
B DDR_B_D38 2 2 B
139 VSS32 DQ38 140
DDR_B_D34 141 142 DDR_B_D39 @ @
DDR_B_D35 DQ34 DQ39 2 2 2 2 2 2 2 2 2 2 2 2
143 DQ35 VSS33 144
145 146 DDR_B_D44
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152
DDR_B_DM5 153 154 DDR_B_DQS5 VDDQ(1.5V) =
DM5 DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162 6*0603 10uf (PER CONNECTOR)
DDR_B_D48 163 164 DDR_B_D52 Layout Note:
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168 VTT(0.75V) = Place near DIMM
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172 3*0805 10uf 4*0402 1uf
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178 +0.75VS
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180 1*0402 0.1uf 1*0402 2.2uf
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184 VDDSPD (3.3V)=
185 186 DDR_B_DQS#7
VSS48 DQS#7

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K
DDR_B_DM7 187 188 DDR_B_DQS7 1*0402 0.1uf 1*0402 2.2uf
DM7 DQS7

C596

C595

C299

C598
189 VSS49 VSS50 190 1 1 1 1
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
2 2 2 2
1 R572 2 197 SA0 EVENT# 198 PM_EXTTS#1_R
PM_EXTTS#1_R 5,10
10K_0402_5% 199 200 SMB_DATA_S3
VDDSPD SDA SMB_DATA_S3 10,12,14,28
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 10,12,14,28
2.2U_0603_6.3V6K

0.1U_0402_10V6K

A R573 10K_0402_5% 203 204 A

VTT1 VTT2 +0.75VS
1/76BA1/86W
C618

C616

1 1
205 G1 G2 206

FOX_AS0A626-U4RN-7F
2 2 ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 11 of 50
5 4 3 2 1
 5 4 3 2 1

Reserve for Low Power CLK GEN.

RTM890N-632
SLG8LV597VTR
+3VS_CK505 VDD_3V3_1V5

1 2
0_0603_5% R278
+1.5VS @
D 1 PCS CAP(0.1u) BY 1 INPUT PIN D
1 2 VDD_3V3_1V5
0_0603_5% R269

10U_0805_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C336

C366

C334

C330
1 1 1 1

2 2 2 2

CLK GEN TO PCH CLK GEN TO VGA

1. CLK_DMI 1. 27M_CLK
2. CLK_BUF_BCLK 1. 27M_CLK_SS +3VS_CK505 +1.05VS_CK505 +3VS_CK505 +1.05VS_CK505
3. CLK_BUF_CKSSCD U14

4. CLK_BUF_DOT96 VDD_3V3_1V5 1 32 SMB_CLK_S3

VDD_USB_48 SCL SMB_CLK_S3 10,11,14,28
R318 0_0402_5% 2 31 SMB_DATA_S3
VSS_48M SDA SMB_DATA_S3 10,11,14,28
5. CLK_14M_PCH CLK_BUF_DOT96 1 2 L_CLK_BUF_DOT96 3 30 REF_0/CPU_SEL 2 1 R315 CLK_14M_PCH
14 CLK_BUF_DOT96 DOT_96 REF_0/CPU_SEL CLK_14M_PCH 14
CLK_BUF_DOT96# 1 2 L_CLK_BUF_DOT96# 4 29 33_0402_1%
14 CLK_BUF_DOT96# DOT_96# VDD_REF
R319 0_0402_5% 5 28 CLK_XTAL_IN
VDD_27 XTAL_IN CLK_XTAL_OUT
6 27MHZ XTAL_OUT 27
7 27MHZ_SS VSS_REF 26
CLK_48M_CR_R 8 25 CK_PWRGD
USB_48 CKPWRGD/PD#
CLOSE U27
9 24 VDD_3V3_1V5 R275 0_0402_5%
CLK_BUF_CKSSCD R324 VSS_27M VDD_CPU
14 CLK_BUF_CKSSCD 1 2 0_0402_5% CLK_BUF_CKSSCD_R 10 SATA CPU_0 23 R_CLK_BUF_BCLK 1 2 CLK_BUF_BCLK CLK_BUF_BCLK 14
CLK_BUF_CKSSCD# R308 1 2 CLK_BUF_CKSSCD#_R 11 22 R_CLK_BUF_BCLK# 1 2 CLK_BUF_BCLK#
C 14 CLK_BUF_CKSSCD# SATA# CPU_0# CLK_BUF_BCLK# 14 C
0_0402_5% 12 21 R276 0_0402_5%
CLK_DMI R307 VSS_SRC VSS_CPU
14 CLK_DMI 1 2 0_0402_5% L_CLK_DMI 13 SRC_1 CPU_1 20
CLK_DMI# R306 1 2 L_CLK_DMI# 14 19
14 CLK_DMI# SRC_1# CPU_1#
0_0402_5% 15 18
R299 CPU_STOP# VDD_SRC_IO VDD_CPU_IO VDD_3V3_1V5
+3VS_CK505 1 2 16 CPU_STOP# VDD_SRC 17
10K_0402_5%
33 TGND
RTM890N-631-VB-GRT_QFN32_5X5
CK_PWRGD R298 1 2 +3VS_CK505
10K_0402_5%
+1.05VS +1.05VS_CK505
SA00003HQ10 S IC RTM890N-631-VB-GRT QFN 32P CLK GEN

1
D
1 PCS CAP(0.1u) BY 1 INPUT PIN 2
1 2 (SA00003HR00)S IC ICS9LVS3199AKLFT MLF 32P CLK GEN G
CLK_EN# 48
0_0603_5% R277 Q25 S
S IC SLG8SP587VTR QFN 32P CLK GEN (SA00002XY00)

3
10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

2N7002_SOT23-3
C333

C331

C332

C343

C335

1 1 1 1 1 1
C1212 CLK_48M_CR_R 2 1
47P_0402_50V8J 0_0402_5% R323
2 2 2 2 2 2
@

PIN8 IS GND FOR ICS3197

RF 10/22 PIN8 IS 48MHz FOR ICS3199

B B
+3VS +3VS_CK505
C364 2 1 CLK_14M_PCH
1 PCS CAP(0.1u) BY 1 INPUT PIN @ 10P_0402_50V8J
1 2 CLK_XTAL_OUT
0_0603_5% R279
10U_0805_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

CLK_XTAL_IN
C344

C342

C350

C367

1 1 1 1 1
C1213 C365 2 1 REF_0/CPU_SEL
47P_0402_50V8J 10P_0402_50V8J
2 2 2 2 2 Y1
EMI Capacitor SVT RF 14.318MHZ_20PF_7A14300003
2 1

RF 10/22 1 1
C348 C349
27P_0402_50V8J 27P_0402_50V8J
2 2
+1.05VS

PIN 30 CPU_0 CPU_1 PVT, resize 5032, CL27pF

1 2 REF_0/CPU_SEL
R317 @ 10K_0402_5%
0 (Default) 133MHz 133MHz
1 2
R316 10K_0402_5%
1 100MHz 100MHz
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLOCK GENERATOR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 12 of 50
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2
R154 10M_0402_5%

1 4
X1
2 3 32.768KHZ_12.5P_MC-146

1 1
D C171 C183 D
15P_0402_50V8J 15P_0402_50V8J
2 EPSON Q13MC1461005000 2
6.9x1.4x1.3mm U7A

PVT +RTCVCC PCH_RTCX1 B13 D33

1 RTCX1 FWH0 / LAD0 LPC_AD0 28,34

1
PCH_RTCX2 D13 B33
RTCX2 FWH1 / LAD1 LPC_AD1 28,34
C184 CLRP3 C32
FWH2 / LAD2 LPC_AD2 28,34
1U_0603_10V6K SHORT PADS A32 LPC_AD3 28,34

2
2 PCH_RTCRST# FWH3 / LAD3
1 2 C14 RTCRST#
+RTCVCC R419 20K_0402_1% C34
+RTCBATT +RTCVCC FWH4 / LFRAME# LPC_FRAME# 28,34
1 2 PCH_SRTCRST# D17
R422 20K_0402_1% SRTCRST#
1 A34

RTC

LPC
LDRQ0#

1
R421 1 2 SM_INTRUDER# SM_INTRUDER# A16 F34 GPIO23 T7 PAD
R144 1M_0402_5% C202 CLRP2 INTRUDER# LDRQ1# / GPIO23 +3VS
GPIO23 = NATIVE,3.3V,CORE
1 2 R420 1 2 PCH_INTVRMEN 1U_0603_10V6K SHORT PADS PCH_INTVRMEN A14 AB9 SERIRQ
SERIRQ 34

2
330K_0402_5% 2 INTVRMEN SERIRQ
2
C441
100_0603_1%

* H
L
Κ
ΚIntegrated VRM enable
Integrated VRM disable R168 1 2 33_0402_5% BITCLK A30
2
10K_0402_5%
1
R479
33 HDA_BITCLK_CODEC HDA_BCLK
0.1U_0402_16V4Z AK7 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 32
1 R167 1 HDA_SYNC SATA0RXN SATA_DTX_C_IRX_P0
2 33_0402_5% D29 AK6

1 2 PCH_SPKR
33 HDA_SYNC_CODEC
PCH_SPKR P1
HDA_SYNC SATA0RXP
SATA0TXN AK11
AK9
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
0.01U_0402_16V7K
0.01U_0402_16V7K
2
2
1 C140
1 C141
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_DTX_C_IRX_P0 32
SATA_ITX_DRX_N0 32 HDD
+3VS 33 PCH_SPKR SPKR SATA0TXP SATA_ITX_DRX_P0 32
R452 @ 1K_0402_5%
RF 1103 add R169 1 2 33_0402_5% HDA_RST# C30
33 HDA_RST_CODEC# HDA_RST#
HDA_BITCLK_CODEC AH6 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 28
R676 0_0402_5% SATA1RXN SATA_DTX_C_IRX_P1
AH5
HDA_SDOUT_CODEC
R677
1 @
0_0402_5%
2 HDA_SDIN0 G30 HDA_SDIN0
SATA1RXP
SATA1TXN AH9
AH8
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1
SATA_DTX_C_IRX_P1
SATA_ITX_C_DRX_N1
28
28 SSD
1 1 SATA1TXP SATA_ITX_C_DRX_P1 28
33 HDA_SDIN1 HDA_SDIN1 1 2 HDA_SDIN1_R F30
C1221 C1222 HDA_SDIN1
SATA2RXN AF11
C 12P_0402_50V8J 12P_0402_50V8J SVT E32 AF9 C

IHDA
2 @ 2 @ HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6

SATA3RXN AH3
R166 1 2 33_0402_5% HDA_SDOUT B29 AH1
33 HDA_SDOUT_CODEC HDA_SDO SATA3RXP
SATA3TXN AF3
GPIO33 = GPO , internal pull-up,should not be pulled low R409 1 @ 2 1K_0402_5% AF1
R425 1 0_0402_5% SATA3TXP
34 ME_FLASH 2 H32

SATA
HDA_DOCK_EN# / GPIO33 SATA_DTX_C_IRX_N4
flash ME core of strap pin pull down SATA4RXN AD9 SATA_DTX_C_IRX_N4 37
+3VALW R424 1 2 10K_0402_5% GPIO13 J30 AD8 SATA_DTX_C_IRX_P4 SATA_DTX_C_IRX_P4 37
@ HDA_DOCK_RST# / GPIO13 SATA4RXP SATA_ITX_C_DRX_N4 0.01U_0402_16V7K C142 SATA_ITX_DRX_N4_CONN
GPIO13 = GPI,3.3V,SUS AD6 2 1
SATA4TXN
SATA4TXP AD5 SATA_ITX_C_DRX_P4 0.01U_0402_16V7K 2 1 C143 SATA_ITX_DRX_P4_CONN
SATA_ITX_DRX_N4_CONN
SATA_ITX_DRX_P4_CONN
37
37 E-SATA
PCH_JTAG_TCK M3 AD3
JTAG_TCK SATA5RXN
SATA5RXP AD1
PCH_JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
SATA5TXP AB1
PCH_JTAG_TDI K1 JTAG_TDI
(2009,07,07)

JTAG
PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO R500
+3VALW +3VALW +3VALW +3VALW PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2 +3VS
TRST# SATAICOMPI +1.05VS
37.4_0402_1%
1

@ @ @ @ R99
R74 R72 R73 R75 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R BA2 SPI_CLK

2
200_0402_5% 200_0402_5% 200_0402_5% 20K_0402_5% 1 2 +3VS
0_0402_5% SPI_SB_CS0# AV3 R453 10K_0402_5% R447 R482
SPI_CS0# 10K_0402_5% 10K_0402_5%
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_RST# AY3 T3

SPI_CS1# SATALED# HDD_LED# 38

1
1

B @ @ @ @ GPIO21 = GPI,3.3V,CORE B
R117 R115 R116 R118 SPI_SI AY1 Y9 GPIO21 GPIO21
10K_0402_5% SPI_MOSI SATA0GP / GPIO21
100_0402_1% 100_0402_1% 100_0402_1%

SPI
SPI_SO_R AV1 V1 GPIO19 GPIO19
SPI_MISO SATA1GP / GPIO19
GPIO19 = GPI,3.3V,CORE
2

IBEXPEAK-M_FCBGA1071 SPI_CLK_PCH

1
SA00003N7A0 (MP) R100
33_0402_5%
4M SPI ROM FOR HM55 @

(ME code & BIOS code)

2
+3VS
PCH JTAG PCH JTAG PCH_JTAG_TCK R114 1 2 51_0402_5% (2009,05,04)
Pre-Production Production SA000021A00 MXIC C138
PCH Pin RefDes 22P_0402_50V8J
ES1 ES2 MP R62 1 2 SPI_WP# SA00003K800 Winbond @
* FOR INTEL DPDG REV1.6 (MAY 2009) 3.3K_0402_5%
R591 No Install 200ohm No Install SA00003IN00 E-ON
R102 1 2SPI_HOLD#
PCH_JTAG_TDO R590 No Install 100ohm No Install 3.3K_0402_5% +3VS
C460
1 2
R103
R584 200ohm 200ohm No Install 15_0402_5% U3
SPI_SB_CS0# 0.1U_0402_16V4Z
1 2 1 CS# VCC 8
PCH_JTAG_TMS R583 100ohm 100ohm No Install SPI_SO_R 2 1 SPI_SO_L 2 7 SPI_HOLD#
R101 SPI_WP# SO HOLD# SPI_CLK_PCH
3 WP# SCLK 6
15_0402_5% 4 5 SPI_SI
A GND SI A
R587 200ohm 200ohm No Install MX25L3205DM2I-12G_SO8

PCH_JTAG_TDI R586 100ohm 100ohm No Install

PCH_JTAG_TCK R580 51ohm 51ohm 51ohm

R595 20Kohm 20Kohm No Install
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

PCH_JTAG_RST# R594 10Kohm 10Kohm No Install THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(1/6)-HDA/JTAG/SATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 13 of 50
5 4 3 2 1
 5 4 3 2 1

SMB_CLK_S3 1 2 SMBCLK 1 2
PCIE PORT LIST SMB_DATA_S3
R121
1
10K_0402_5%
2
+3VS
SMBDATA
R123
1
2.2K_0402_5%
2
+3VALW

R406 10K_0402_5% R78 2.2K_0402_5%

SML0CLK
PORT DEVICE 1
R148
2
2.2K_0402_5%
SML0DATA 1 2
R147 2.2K_0402_5%
1 NEW CARD SML1CLK 1 2
R404 2.2K_0402_5%
2 WLAN SML1DATA 1 2
R403 2.2K_0402_5%
3 LAN GPIO74 1 2
+3VS R399 10K_0402_5%
4 3G EC_LID_OUT# 34 LID_OUT# 1 2
D R145 10K_0402_5% D
5 X GPIO60 1 2
R400 10K_0402_5%
6 X
R407
7 X 0_0402_5%
8 X U7B

2
BG30 B9 LID_OUT# 6 1 SMB_CLK_S3
PERN1 SMBALERT# / GPIO11 SMB_CLK_S3 10,11,12,28
BJ30 PERP1 NEW CARD GPIO11 = NATIVE,3.3V,SUS

5
SMBCLK 2N7002DW-T/R7_SOT363-6
10/6 Remove Express card BF29 PETN1 SMBCLK H14
Q8A DDR3*2 AND CLK GEN
BH29 PETP1
C8 SMBDATA 3 4 SMB_DATA_S3
SMBDATA SMB_DATA_S3 10,11,12,28
28 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 AW30
PCIE_PRX_DTX_P2 BA30 PERN2 GPIO60 = NATIVE,3.3V,SUS 2N7002DW-T/R7_SOT363-6
28 PCIE_PRX_DTX_P2 PERP2 Q8B
WLAN C230 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_N2 BC30 WLAN J14 GPIO60
28 PCIE_PTX_C_DRX_N2 PETN2 SML0ALERT# / GPIO60
C229 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P2 BD30
28 PCIE_PTX_C_DRX_P2 PETP2
C6 SML0CLK
PCIE_PRX_DTX_N3 SML0CLK R122
29 PCIE_PRX_DTX_N3 AU30

SMBus
PCIE_PRX_DTX_P3 PERN3 SML0DATA 0_0402_5%
29 PCIE_PRX_DTX_P3 AT30 PERP3 SML0DATA G8
LAN C223 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_N3 AU32 LAN SMBCLK 1 @ 2 SMB_CLK_S3
29 PCIE_PTX_C_DRX_N3 PETN3 GPIO74 = NATIVE,3.3V,SUS
C222 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P3 AV32
29 PCIE_PTX_C_DRX_P3 PETP3
M14 GPIO74 SMBDATA 1 @ 2 SMB_DATA_S3
PCIE_PRX_DTX_N4 SML1ALERT# / GPIO74
28 PCIE_PRX_DTX_N4 BA32 PERN4
PCIE_PRX_DTX_P4 BB32 E10 SML1CLK R79 0_0402_5% EC_SMB_CK2 0_0402_5%
28 PCIE_PRX_DTX_P4 PERP4 SML1CLK / GPIO58 EC_SMB_CK2 31,34
3G C231 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_N4 BD32 MINI1 EC_THERMAL R119
28 PCIE_PTX_C_DRX_N4 PETN4
C232 1 2 0.1U_0402_10V6K PCIE_PTX_DRX_P4 BE32 G12 SML1DATA R80 0_0402_5% EC_SMB_DA2 EC_SMB_DA2 31,34
28 PCIE_PTX_C_DRX_P4 PETP4 SML1DATA / GPIO75
3G@

PCI-E*
3G@ BF33 DTS , read from EC
PERN5
BH33 PERP5 CL_CLK1 T13

Controller
BG32 PETN5
C BJ32 T11 C
PETP5 CL_DATA1

Link
BA34 PERN6 CL_RST1# T9
AW34 PERP6 PEG_CLKREQ# 19
BC34 PETN6
BD34 10K_0402_5% R412 @
PETP6 PEG_CLKREQ#
PEG_A_CLKRQ# / GPIO47 H1 1 2
AT34 PERN7 GPIO47 = 10Kohm PULL DOWN
AU34 PERP7
AU36 AD43 CLK_PCIE_VGA#_R R524 1 2 0_0402_5% CLK_PCIE_VGA#
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGA# 19
AV36 AD45 CLK_PCIE_VGA_R R525 1 2 0_0402_5% CLK_PCIE_VGA
PETP7 CLKOUT_PEG_A_P CLK_PCIE_VGA 19
BG34 AN4 CLK_EXP#_R R105 1 2 0_0402_5%
PERN8 CLKOUT_DMI_N CLK_EXP# 5

PEG
BJ34 AN2 CLK_EXP_R R106 1 2 0_0402_5%
PERP8 CLKOUT_DMI_P CLK_EXP 5
BG36 PETN8 +3VS_DELAY
BJ36 PETP8
AT1 CLKOUT_DP_N T24 PAD
Nvidia Thermal sensor
CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P T25 PAD +3VS_DELAY
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
10/6 Remove Express card CLK AK48 CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P

From CLK BUFFER

CLKIN_DMI_N AW24 CLK_DMI# 12
+3VALW R431 1 2 10K_0402_5% GPIO73 P9 BA24
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_DMI 12
R124 R82
GPIO73 = NATIVE,3.3V,SUS 2.2K_0402_5% 2.2K_0402_5%
28 CLK_PCIE_WLAN1#
R196 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_BCLK# 12
HYBRID@ HYBRID@

2
WLAN R197 1 2 0_0402_5% CLK_PCIE_WLAN1_R AM45 AP1 HYBRID@
28 CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK 12
Q7A
28 WLAN_CLKREQ1# U4 EC_SMB_DA2 6 1 SMB_EC_DA2_R
PCIECLKRQ1# / GPIO18 SMB_EC_DA2_R 19
+3VS R454 1 2 10K_0402_5% F18
CLKIN_DOT_96N CLK_BUF_DOT96# 12

5
GPIO18 = NATIVE,3.3V,CORE E18 HYBRID@ 2N7002DW-T/R7_SOT363-6
CLKIN_DOT_96P CLK_BUF_DOT96 12
R220 1 2 0_0402_5% CLK_PCIE_LAN#_R AM47 Q7B
29 CLK_PCIE_LAN# CLKOUT_PCIE2N
LAN R221 1 2 0_0402_5% CLK_PCIE_LAN_R AM48 EC_SMB_CK2 3 4 SMB_EC_CK2_R
B 29 CLK_PCIE_LAN CLKOUT_PCIE2P SMB_EC_CK2_R 19 B
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_CKSSCD# 12
N4 AH12 2N7002DW-T/R7_SOT363-6
29 CLKREQ_LAN# PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_CKSSCD 12
+3VS R113 1 2 10K_0402_5%
GPIO20 = NATIVE,3.3V,CORE
R223 1 3G@ 2 0_0402_5% CLK_PCIE_CARD_PCH#_R AH42 P41 CLK_14M_PCH
28 CLK_PCIE_CARD_PCH# CLKOUT_PCIE3N REFCLK14IN CLK_14M_PCH 12
3G R222 1 3G@ 2 0_0402_5% CLK_PCIE_CARD_PCH_R AH41
28 CLK_PCIE_CARD_PCH CLKOUT_PCIE3P

28 PCIECLKREQ3# A8 J42 CLK_PCI_FB

PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 16
+3VALW R120 1 2 10K_0402_5%
GPIO25 = NATIVE,3.3V,SUS
AM51 AH51 XTAL25_IN
CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53

+3VALW R435 1 2 10K_0402_5% GPIO26 M9 AF38 R491 1 2 90.9_0402_1% +1.05VS

PCIECLKRQ4# / GPIO26 XCLK_RCOMP
GPIO26 = NATIVE,3.3V,SUS
AJ50 T45 XTAL25_IN
AJ52
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUTFLEX0 / GPIO64
R198
EMI REQUEST 0303 XTAL25_OUT 1 2
+3VALW R434 1 2 10K_0402_5% GPIO44 H6 P43 CLK_PCI_DB_R 1 2 22_0402_5% R598 1M_0402_5%
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 CLK_PCI_DB 28

GPIO44 = NATIVE,3.3V,SUS @ CLK_PCI_FB CLK_14M_PCH
Y4
AK53 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 T42 1 2

2
AK51 CLKOUT_PEG_B_P R209 R413 25MHZ_20PF_7A25000012
+3VALW R457 1 2 10K_0402_5% GPIO56 P13 N50 GPIO67 T9 PAD 22_0402_5% 22_0402_5%
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 @
GPIO56 = NATIVE,3.3V,SUS SVT 1 1

1
IBEXPEAK-M_FCBGA1071 RF C630
For CR 48M CLK 2 2
27P_0402_50V8J C631
C263 C439 27P_0402_50V8J
2 2
10P_0402_50V8J 10P_0402_50V8J
A 1 @ 1 A
18->27pF, PVT
Y4 resize 5032

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(2/6)-PCI-E/SMBUS/CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 14 of 50
5 4 3 2 1
 5 4 3 2 1

D D

U7C U7D
BA18 FDI_CTX_PRX_N0 PCH_ENBKL T48 BJ46
FDI_RXN0 FDI_CTX_PRX_N0 6 27 PCH_ENBKL L_BKLTEN SDVO_TVCLKINN
6 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BH17 FDI_CTX_PRX_N1 PCH_ENVDD T47 BG46
DMI0RXN FDI_RXN1 FDI_CTX_PRX_N1 6 27 PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
6 DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BJ22 BD16 FDI_CTX_PRX_N2
DMI1RXN FDI_RXN2 FDI_CTX_PRX_N2 6
6 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 AW20 BJ16 FDI_CTX_PRX_N3 Y48 BJ48
DMI2RXN FDI_RXN3 FDI_CTX_PRX_N3 6 27 PCH_PWM L_BKLTCTL SDVO_STALLN
6 DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BJ20 BA16 FDI_CTX_PRX_N4 BG48
DMI3RXN FDI_RXN4 FDI_CTX_PRX_N4 6 SDVO_STALLP
BE14 FDI_CTX_PRX_N5 EDID_CLK AB48
FDI_RXN5 FDI_CTX_PRX_N5 6 27 PCH_EDID_CLK L_DDC_CLK
6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BD24 BA14 FDI_CTX_PRX_N6 EDID_DATA Y45 BF45
DMI0RXP FDI_RXN6 FDI_CTX_PRX_N6 6 27 PCH_EDID_DATA L_DDC_DATA SDVO_INTN
6 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BG22 BC12 FDI_CTX_PRX_N7 BH45
DMI1RXP FDI_RXN7 FDI_CTX_PRX_N7 6 SDVO_INTP
6 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BA20 1 R497 2 AB46
DMI_CTX_PRX_P3 DMI2RXP FDI_CTX_PRX_P0 L_CTRL_CLK
6 DMI_CTX_PRX_P3 BG20 DMI3RXP FDI_RXP0 BB18 FDI_CTX_PRX_P0 6 +3VS 1 2 10K_0402_5% V48 L_CTRL_DATA
BF17 FDI_CTX_PRX_P1 R496 10K_0402_5%
FDI_RXP1 FDI_CTX_PRX_P1 6
DMI_CRX_PTX_N0 BE22 BC16 FDI_CTX_PRX_P2 AP39 T51
6 DMI_CRX_PTX_N0 DMI0TXN FDI_RXP2 FDI_CTX_PRX_P2 6 LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_N1 BF21 BG16 FDI_CTX_PRX_P3 AP41 T53
6 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP3 FDI_CTX_PRX_P3 6 LVD_VBG SDVO_CTRLDATA

1
DMI_CRX_PTX_N2 BD20 AW16 FDI_CTX_PRX_P4 T10 PAD
6 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP4 FDI_CTX_PRX_P4 6
DMI_CRX_PTX_N3 BE18 BD14 FDI_CTX_PRX_P5 R502 AT43
6 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP5 FDI_CTX_PRX_P5 6 LVD_VREFH
BB14 FDI_CTX_PRX_P6 2.37K_0402_1% AT42 BG44
FDI_RXP6 FDI_CTX_PRX_P6 6 LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P0 BD22 BD12 FDI_CTX_PRX_P7 BJ44 R510 100K_0402_5%
6 DMI_CRX_PTX_P0 DMI0TXP FDI_RXP7 FDI_CTX_PRX_P7 6 DDPB_AUXP
DMI_CRX_PTX_P1 BH21 AU38 2 1

2
6 DMI_CRX_PTX_P1 DMI1TXP DDPB_HPD

LVDS
DMI_CRX_PTX_P2 BC20 LVDS_ACLK# AV53
6 DMI_CRX_PTX_P2 DMI2TXP 27 LVDS_ACLK# LVDSA_CLK# +3VS
DMI_CRX_PTX_P3 BD18 BJ14 FDI_INT LVDS_ACLK AV51 BD42
6 DMI_CRX_PTX_P3 DMI3TXP FDI_INT FDI_INT 6 27 LVDS_ACLK LVDSA_CLK DDPB_0N
BC42

DMI
FDI
FDI_FSYNC0 DDPB_0P
BF13 FDI_FSYNC0 6 27 LVDS_A0# BB47 BJ42
+1.05VS FDI_FSYNC0 LVDSA_DATA#0 DDPB_1N
BH25 27 LVDS_A1# BA52 BG42

Digital Display Interface

DMI_ZCOMP LVDSA_DATA#1 DDPB_1P

1
BH13 FDI_FSYNC1 AY48 BB40
FDI_FSYNC1 FDI_FSYNC1 6 27 LVDS_A2# LVDSA_DATA#2 DDPB_2N
1 2 DMI_IRCOMP BF25 AV47 BA40 R504 R503
R520 49.9_0402_1% DMI_IRCOMP FDI_LSYNC0 LVDSA_DATA#3 DDPB_2P 2.2K_0402_5% 2.2K_0402_5%
FDI_LSYNC0 BJ12 FDI_LSYNC0 6 DDPB_3N AW38
4mil width and place BB48 BA38 UMA@ UMA@
27 LVDS_A0 LVDSA_DATA0 DDPB_3P
BG14 FDI_LSYNC1 BA50
within 500mil of the PCH

2
FDI_LSYNC1 FDI_LSYNC1 6 27 LVDS_A1 LVDSA_DATA1
27 LVDS_A2 AY49 LVDSA_DATA2
AV48 Y49 HDMICLK_NB

Κ
+3VS LVDSA_DATA3 DDPC_CTRLCLK HDMICLK_NB 25
AB49 HDMIDAT_NB HDMIDAT_NB 25
DDPC_CTRLDATA
2

Checklist0.8 MEPWROK 1K_0402_5%

C C
can be connect to R448 1 2 +3VALW AP48
MP LVDSB_CLK#
PWROK if iAMT disable 10K_0402_5% AP47 BE44
R436 LVDS_ACLK# LVDSB_CLK DDPC_AUXN
BD44
R396 0.01U_0402_16V7K SYS_RST# PCIE_WAKE# LVDS_ACLK DDPC_AUXP
T6 J12 AY53 AV40
1

SYS_RESET# WAKE# PCIE_WAKE# 28 LVDSB_DATA#0 DDPC_HPD TMDS_B_HPD 25

2 1 1 1 AT49 LVDSB_DATA#1
GPIO32 = GPO,3.3V,CORE C1214 AU52 LVDSB_DATA#2 DDPC_0N BE40 TMDS_B_DATA2#_PCH C638 1 2UMA@ 0.1U_0402_10V6K TMDS_B_DATA2# 25
34,48 VGATE R398 1 @ 2 0_0402_5% SYS_PWROK M6 Y1 1 2 SVT
+3VS 12P_0402_50V8J C1215 AT53 BD40 TMDS_B_DATA2_PCH C639 1 2UMA@ 0.1U_0402_10V6K
SYS_PWROK CLKRUN# / GPIO32 12P_0402_50V8J LVDSB_DATA#3 DDPC_0P TMDS_B_DATA2 25
R108 10K_0402_5% @ @
DDPC_1N BF41 TMDS_B_DATA1#_PCH C640 1 2UMA@ 0.1U_0402_10V6K TMDS_B_DATA1# 25
2

R397 1 @ 2 0_0402_5% 1 2 2 2 @ AY51 BH41 TMDS_B_DATA1_PCH C641 1 2UMA@ 0.1U_0402_10V6K

34 ICH_POK CLKRUN# 34 LVDSB_DATA0 DDPC_1P TMDS_B_DATA1 25
R180 0_0402_5% BD38 TMDS_B_DATA0#_PCH C642 2UMA@ 0.1U_0402_10V6K
System Power Management

B17 AT48 1 TMDS_B_DATA0# 25

PWROK LVDSB_DATA1 DDPC_2N
R455 PVT RF 10/22 AU50 BC38 TMDS_B_DATA0_PCH C643 1 2UMA@ 0.1U_0402_10V6K TMDS_B_DATA0 25
LVDSB_DATA2 DDPC_2P
(2009,05,04) 0_0402_5% AT51 LVDSB_DATA3 DDPC_3N BB36 TMDS_B_CLK#_PCH C644 1 2UMA@ 0.1U_0402_10V6K TMDS_B_CLK# 25
K5 P8 GPIO61 GPIO61 = NATIVE,3.3V,SUS BA36 TMDS_B_CLK_PCH C645 1 2UMA@ 0.1U_0402_10V6K
1

MEPWROK SUS_STAT# / GPIO61 DDPC_3P TMDS_B_CLK 25

GPIO62 = NATIVE,3.3V,SUS
R146 1 2 10K_0402_5%A10 F3 SUSCLK DAC_BLU AA52 U50
LAN_RST# SUSCLK / GPIO62 SUSCLK 34 26 DAC_BLU
26 DAC_GRN
DAC_GRN AB53
CRT_BLUE
CRT_GREEN
DDPD_CTRLCLK
DDPD_CTRLDATA
U52 HDMI
DAC_RED AD53
26 DAC_RED CRT_RED
PM_DRAM_PWRGD D9 E4 SVT
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 34
BC46
CRT_DDC_CLK DDPD_AUXN R675 100K_0402_5%
26 CRT_DDC_CLK V51 BD46
R401 2 PM_RSMRST# CRT_DDC_DATA CRT_DDC_CLK DDPD_AUXP
1 C16 H7 PM_SLP_S4# 34 26 CRT_DDC_DATA V53 AT38 2 1
+3VALW 10K_0402_5% RSMRST# SLP_S4# CRT_DDC_DATA DDPD_HPD
R688 UMA@ 33_0402_1% BJ40
DDPD_0N
R437 1 2 10K_0402_5% SUS_PWR_DN_ACK_R M1 SUS_PWR_DN_ACK / GPIO30 SLP_S3# P12 PM_SLP_S3# 34 26 CRT_HSYNC 2 1 HSYNC Y53 CRT_HSYNC DDPD_0P BG40
1 2 2 1 VSYNC Y51 BJ38
34 SUS_PWR_DN_ACK 26 CRT_VSYNC CRT_VSYNC DDPD_1N
R599 0_0402_5% R687 UMA@ 33_0402_1% BG38
+3VALW DDPD_1P

CRT
34 PBTN_OUT# PBTN_OUT#P5 K8 Can be left NC when IAMT is BF37
PWRBTN# SLP_M# SVT CRT_IREF AD48 DDPD_2N
not support on the platfrom DAC_IREF DDPD_2P BH37

1K_0402_0.5%
R450 1 2 10K_0402_5% AB51 BE36
R688 R687 CRT_IRTN DDPD_3N

1
R492
34 AC_PRESENT 1 2 AC_PRESENT_R P7 N2 BD36
R451 0_0402_5% ACPRESENT / GPIO31 TP23 DDPD_3P
GPIO31 = GPI,3.3V,SUS IBEXPEAK-M_FCBGA1071
+3VALW R77 1 2 8.2K_0402_1% GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
B If CRT DAC is not used then B

2
GPIO30 = GPI,3.3V,SUS GPIO29 = GPO,3.3V,SUS
R165 1 2 10K_0402_5% F14 F6 If not using integrated a 5% resistor can be used.
RI# SLP_LAN# / GPIO29 22_0402_5% 22_0402_5%
LAN,signal may be left as NC.
HYBRID@ HYBRID@
(checklist 1.6)
IBEXPEAK-M_FCBGA1071 SD028220A80 SD028220A80

NC7SZ08P5X_NL_SC70-5
CRT OUT
3

VGATE 1 DAC_BLU R493 1 2 150_0402_1%

G

A SYS_PWROK
4
ICH_POK 2
B
Y RSMRST circuit DAC_GRN R495 1 2 150_0402_1%
P

U28 @ R402 DAC_RED R494 1 2 150_0402_1%

5

0_0402_5%
1 2

+3VS
PM_RSMRST# +3VS
C

34 EC_RSMRST# 3 1
Q14
E

Reserved BAV99DW-7_SOT363 MMBT3906_SOT23-3 LVDS EDID

B

1 2 +3VALW
1 2

(2009,09,08) R176 4.7K_0402_5% EDID_CLK R458 2.2K_0402_5%

5

D8B EDID_DATA R498 2.2K_0402_5%

D8A
BAV99DW-7_SOT363
R175
3

A A
1 2

4.7K_0402_5%

PVT, Common design

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(3/6)-DMI/LVDS/DP/PM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 15 of 50
5 4 3 2 1
 5 4 3 2 1

U7E U7F
H40 AD0 NV_CE#0 AY9 GPIO8 GPIO0 = GPI,3.3V,CORE
N34 BD1 Weak internal PU, don't PD +3VS 1 2 GPIO0 Y3 AH45
AD1 NV_CE#1 10K_0402_5% R483 BMBUSY# / GPIO0 CLKOUT_PCIE6N
C44 AD2 NV_CE#2 AP15 CLKOUT_PCIE6P AH46
A38 BD8 1 2 GPIO1 C38 +3VS
AD3 NV_CE#3 10K_0402_5% R428 TACH1 / GPIO1
C36 AD4
J34 AV9 Check list Rev0.8 section1.23.2 1 2 GPIO6 D37
AD5 NV_DQS0 TACH2 / GPIO6

2
A40 BG8 10K_0402_5% R427 AF48
AD6 NV_DQS1 If not implemented, the CLKOUT_PCIE7N

MISC
D45 EC_SCI# J32 AF47 R110
AD7 Braidwood 34 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
E36 AD8 NV_DQ0 / NV_IO0 AP7 10K_0402_5%
H48 AP6 interface signals can be EC_SMI# F10
AD9 NV_DQ1 / NV_IO1 34 EC_SMI# GPIO8
E40 AT6
left as No Connect (NC).

1
AD10 NV_DQ2 / NV_IO2 T20
C40 AD11 NV_DQ3 / NV_IO3 AT9 K9 LAN_PHY_PWR_CTRL / GPIO12 A20GATE U2 GATEA20 34
M48 BB1 PAD
AD12 NV_DQ4 / NV_IO4 GPIO15
M45 AV6 1 2 T7
*Κ
AD13 NV_DQ5 / NV_IO5 +3VALW GPIO15
F53 BB3 GPIO15 1K_0402_5% R433
AD14 NV_DQ6 / NV_IO6 GPIO16 +3VS
D M40 AD15 NV_DQ7 / NV_IO7 BA4 L Intel ME Crypto Transport AA2 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# 5 D

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4 Layer Security(TLS) chiper suite

1
J36 BB6 DGPU_PWROK F38 AM1

Κ
AD17 NV_DQ9 / NV_IO9 with no confidentiality TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 5
K48 BD6 R111
AD18 NV_DQ10 / NV_IO10
F40 AD19 NV_DQ11 / NV_IO11 BB7 H Intel ME Crypto Transport 1 2 GPIO22 Y7 SCLOCK / GPIO22 PECI BG10 H_PECI
H_PECI 5 10K_0402_5%

GPIO
C42 BC8 Layer Security(TLS) chiper suite 10K_0402_5% R449
AD20 NV_DQ12 / NV_IO12 KB_RST# KB_RST#
K46 BJ8 with confidentiality H10 T1 KB_RST# 34

2
AD21 NV_DQ13 / NV_IO13 GPIO27 if pull down to turn off 1.8V VR GPIO24 RCIN#
M51 AD22 NV_DQ14 / NV_IO14 BJ6
J52 BG6 2 @ 1 AB12 BE10
AD23 NV_DQ15 / NV_IO15 GPIO27 PROCPWRGD H_CPUPWRGD 5

CPU
K51 it have weak internal PU 20K 10K_0402_5% R507
AD24 NV_ALE
L34 AD25 NV_ALE BD3 +3VALW 1 2 GPIO28 V13 GPIO28 THRMTRIP# BD10 H_THERMTRIP#_L 1 R518 2 H_THERMTRIP# 5
F42 AY6 NV_CLE 10K_0402_5% R446 56_0402_5%

ΚDo not connect(floating)

AD26 NV_CLE

1
J40 AD27 within 500mil GPIO27 2 1 GPIO34 M11 STP_PCI# / GPIO34
56 5%-->checklist 1.6
G46 Default 10K_0402_5% R432 54.9 1%-->CRB 1.0 R519

Κ
AD28 NV_RCOMP 1 R104
F44 AD29 NV_RCOMP AU2 2 2 1 GPIO35 V6 SATACLKREQ# / GPIO35
56_0402_5%
M47 32.4_0402_1% High Enables the internal VccVRM 10K_0402_5% R456
AD30 GPIO36

PCI
H36 AV7 @ to have a clean supply for analog AB7 BA22

2
AD31 NV_RB# SATA2GP / GPIO36 TP1
rails. no need to use on board +VCCP
J50 AY8 1 2 GPIO37 AB13 AW22
C/BE0# NV_WR#0_RE# filter circuit. 10K_0402_5% R481 SATA3GP / GPIO37 TP2
G42 C/BE1# NV_WR#1_RE# AY5
H47 1 2 GPIO38 V3 BB22
C/BE2# 10K_0402_5% R109 SLOAD / GPIO38 TP3
G34 C/BE3# NV_WE#_CK0 AV11 GPIO1 = GPI,3.3V,CORE
BF5 GPIO6 = GPI,3.3V,CORE 1 2 GPIO39 P3 AY45
NV_WE#_CK1 SDATAOUT0 / GPIO39 TP4

GPIO18 = NATIVE,5V,CORE
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
G38
H51
B37
PIRQA#
PIRQB#
H18 USB20_N0
GPIO7 = GPI,3.3V,CORE
GPIO8 = GPO,3.3V,SUS
GPIO12 = GPI,3.3V,SUS
6 +3VALW
10K_0402_5%

10K_0402_5%
R112
1
R76
2 GPIO45 H3 PCIECLKRQ6# / GPIO45 TP5 AY46
2 1 DRAMRST_CNTRL_PCH
PIRQC# USBP0N USB20_N0 37 +3VALW
GPIO52 = NATIVE,5V,CORE PCI_PIRQD# A44 J18 USB20_P0 USB1 DRAMRST_CNTRL_PCH GPIO46 F1 AV43 R405 10K_0402_5%
PIRQD# USBP0P USB20_P0 37 5 DRAMRST_CNTRL_PCH PCIECLKRQ7# / GPIO46 TP6
GPIO54 = NATIVE,5V,CORE A18 USB20_N1
USBP1N USB20_N1 37
PCI_REQ0# F51 C18 USB20_P1 LEFT USB (COMBO) 1 2 GPIO48 AB6 AV45
REQ0# USBP1P USB20_P1 37 SDATAOUT1 / GPIO48 TP7
PCI_REQ1# A46 N20 USB20_N2 10K_0402_5% R480
REQ1# / GPIO50 USBP2N USB20_N2 27
B45 P20 USB20_P2 USB Camera PCH_TEMP_ALERT# AA4 AF13
26,27 DGPU_SELECT# REQ2# / GPIO52 USBP2P USB20_P2 27 34 PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8
PCI_REQ3# M53 J20 USB20_N3
REQ3# / GPIO54 USBP3N USB20_N3 37
L20 USB20_P3 USB2 +3VALW 1 2 GPIO57 F8 M18
USBP3P USB20_P3 37 GPIO57 TP9
PCI_GNT0# F48 F20 R415 10K_0402_5%
PCI_GNT1# GNT0# USBP4N
C
K45 GNT1# / GPIO51 USBP4P G20 TP10 N18 C
F36 A20 USB20_N5 HYBRID@
27 DGPU_PWMSEL# GNT2# / GPIO53 USBP5N USB20_N5 37
PCI_GNT3# H53 C20 USB20_P5 CARD READER R614 0_0402_5% A4 AJ24
GNT3# / GPIO55 USBP5P USB20_P5 37 VSS_NCTF_1 TP11
M22 1 2 GPIO36 A49

NCTF
USBP6N 22,39,45 DGPU_PWR_EN VSS_NCTF_2

RSVD
GPIO2 = GPI,5V,CORE PCI_PIRQE# B41 N22 A5 AK41
PCI_PIRQF# PIRQE# / GPIO2 USBP6P @ VSS_NCTF_3 TP12
GPIO3 = GPI,5V,CORE K53 PIRQF# / GPIO3 USBP7N B21 A50 VSS_NCTF_4
GPIO4 = GPI,5V,CORE PCI_PIRQG# A36 D21 R627 0_0402_5% A52 AK42
PCI_PIRQH# PIRQG# / GPIO4 USBP7P USB20_N8 GPIO0 VSS_NCTF_5 TP13
GPIO5 = GPI,5V,CORE A48 PIRQH# / GPIO5 USBP8N H22 USB20_N8 28 1 2 A53 VSS_NCTF_6
J22 USB20_P8 WLAN B2 M32
USBP8P USB20_P8 28 VSS_NCTF_7 TP14
USB

K6 E22 USB20_N9 HYBRID@ B4

28,34 PCI_RST# PCIRST# USBP9N USB20_N9 37 VSS_NCTF_8
F22 USB20_P9 USB3 R613 0_0402_5% B52 N32
USBP9P USB20_P9 37 VSS_NCTF_9 TP15
R408 2 1 100K_0402_1% PCI_SERR# E44 A22 DGPU_HOLD_RST# 1 2 GPIO16 B53
SERR# USBP10N USB20_N10 38 VSS_NCTF_10
PCI_PERR# E50 C22 FP BE1 M30
PERR# USBP10P USB20_P10 38 VSS_NCTF_11 TP16
G24 USB20_N11 @ BE53
USBP11N USB20_N11 37 VSS_NCTF_12
GNT2 H24 USB20_P11 Bluetooth R628 0_0402_5% BF1 N30
USBP11P USB20_P11 37 VSS_NCTF_13 TP17
PCI_IRDY# A42 L24 1 2 GPIO35 BF53
IRDY# USBP12N VSS_NCTF_14
Default-Internal pull up H44 M24 BH1 H12
* PCI_DEVSEL# F46
PAR
DEVSEL#
USBP12P
USBP13N A24 USB20_N13
USB20_N13 28 BH2
VSS_NCTF_15
VSS_NCTF_16
TP18
Low=Configures DMI for ESI PCI_FRAME# C46 C24 USB20_P13 3G CARD BH52 AA23
FRAME# USBP13P USB20_P13 28 VSS_NCTF_17 TP19
compatible operation(for BH53 VSS_NCTF_18
servers only.Not for PCI_LOCK# D49 HYBRID@ BJ1 AB45
PLOCK# USBRBIAS R609 0_0402_5% VSS_NCTF_19 NC_1
mobile/desktops) USBRBIAS# B25 1 2 BJ2 VSS_NCTF_20
PCI_STOP# D41 R164 22.6_0402_1% 1 2 GPIO6 BJ4 AB38
STOP# 24 DGPU_HPD_INT# VSS_NCTF_21 NC_2
PCI_TRDY# C48 D25 Within 500 mils minimum spacing to other BJ49
TRDY# USBRBIAS @ VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
INTERNAL pull -H T26 M7 signal is 15mil R611 0_0402_5% BJ50
PAD PME# USB_OC#0 GPIO15 VSS_NCTF_24
OC0# / GPIO59 N16 USB_OC#0 37 1 2 BJ52 VSS_NCTF_25 NC_4 AB41
PLT_RST# D5 J16 USB_OC#1 USB_OC#1 37 BJ53
PLTRST# OC1# / GPIO40 USB_OC#2 VSS_NCTF_26
OC2# / GPIO41 F16 D1 VSS_NCTF_27 NC_5 T39
USB_OC#3_R
N52
P53
CLKOUT_PCI0 OC3# / GPIO42 L16
E14 USB_OC#4
1
R625
2
0_0402_5% HDMI HPD FOR PCH D2
D53
VSS_NCTF_28
R199 22_0402_5% CLKOUT_PCI1 OC4# / GPIO43 USB_OC#5_R VSS_NCTF_29 INT3_3V#
P46 G16 1 2 E1 P6
34 CLK_PCI_LPC 1
1
2
2
CLK_PCI_LPC_R
CLK_PCI_FB_R
P51
P48
CLKOUT_PCI2
CLKOUT_PCI3
OC5# / GPIO9
OC6# / GPIO10 F12
T15
USB_OC#6
USB_OC#7
R626 0_0402_5%
USB_OC#5 37
EDIDSEL# R612
HYBRID@
0_0402_5%
E53
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V#
C10 TP24
USB PORT LIST
14 CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 TP24
1 2 GPIO1
26,27 DGPU_EDIDSEL#
R211 22_0402_5% IBEXPEAK-M_FCBGA1071
B
IBEXPEAK-M_FCBGA1071 Default-Internal pull up PORT DEVICE B

+3VALW
+3VS +3VS PCI_GNT0# R212 1 @ 2 1K_0402_5% RP1 DGPU_PWROK
USB_OC#0 1 8
1
R429
2
10K_0402_5% 0 USB1
RP5 RP3 PCI_GNT1# R210 1 @ 2 1K_0402_5% Intel Anti-Theft Techonlogy USB_OC#1 PVT, timing
PCI_REQ0# 1 8 PCI_PIRQG# 1 8 USB_OC#2
2
3
7
6 1 2 GPIO36 1 USB/ESATA
PCI_PIRQB# PCI_PIRQC# High=Enabled USB_OC#3_R R485 1K_0402_1%
PCI_PIRQF#
2
3
7
6 PCI_PIRQA#
2
3
7
6 Boot BIOS Strap NV_ALE
4 5
2 CMOS
PCI_REQ3# PCI_PIRQE# Low=Disable(floating) 8.2K_0804_8P4R_5% PCH_TEMP_ALERT#
4 5 4 5
PCI_GNT0# PCI_GNT1# Boot BIOS * +3VS 1
R484
2
10K_0402_5% 3 USB2
8.2K_0804_8P4R_5% 8.2K_0804_8P4R_5%
Location +1.8VS RP2 2 1 GPIO16 4
RP7 RP6 0 0 LPC USB_OC#4 R107 10K_0402_5%
PCI_REQ1# 1 8 PCI_DEVSEL# 1 8 NV_ALE @ R515 1 2 1K_0402_5% USB_OC#5_R
1
2
8
7
5 CARD READER
PCI_FRAME# PCI_LOCK# 0 1 Reserved(NAND) USB_OC#6
PCI_TRDY#
2
3
7
6 PCI_SERR#
2
3
7
6 USB_OC#7
3
4
6
5
6 X
PCI_PIRQH# PCI_PERR# 1 0 PCI DMI Termination Voltage
4 5 4 5
8.2K_0804_8P4R_5% 7 X
8.2K_0804_8P4R_5% 8.2K_0804_8P4R_5% 1 1 SPI Set to Vcc when HIGH
* NV_CLE NV_ALE 8 WIRELESS
PCI_STOP#
PCI_IRDY#
1
RP4
8 1
R149

@
2
22_0402_5% Set to Vss when LOW
Weak internal
Κ
Enable Intel Anti-Theft
Technology 8.2K PU to +3VS
9 USB3
2 7
10 FingerPrint
Κ
PCI_PIRQD# 3 6 PU,Do not pull low +3VS Disable Intel Anti-Theft 1 @ 2 EC_SCI#
+3VS
DGPU_SELECT# R426 10K_0402_5%
4 5
NV_CLE @ R98 1 2 1K_0402_5%
Technology floating(internal PD) 11 BT
8.2K_0804_8P4R_5% NV_CLE @ EC_SMI#
NC7SZ08P5X_NL_SC70-5
+3VALW 1
R414
2
10K_0402_5% 12
3

PCI_GNT3# @ R200 1 2 1K_0402_5% DMI termination voltage.

1 PLT_RST# weak internal PU, don't PD
13 3G
G

A
5,28,29 BUF_PLT_RST# 4 Y
A16 swap overide Strap/Top-Block 2 PVT
B
P

Swap Override jumper

1

1 U5 0_0402_5% 2 1 R580 DGPU_PWROK

45 VGA_PWROK
5

A A
Low=A16 swap 0.1U_0402_16V4Z
override/Top-Block C646 R155 1
PCI_GNT3# Swap Override enabled 100K_0402_5% 0.1U_0402_16V4Z
2 @ +3VS +3VS C687
High=Default *
2

@
2
5

U15
2
P

B
4
19 PLTRST_VGA# Y
A 1 DGPU_HOLD_RST# Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

HYBRID@
IBEX-M(4/6)-PCI/USB/GPIO
3

R173 NC7SZ08P5X_NL_SC70-5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100K_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HYBRID@ Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-5941P
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 16 of 50
5 4 3 2 1
 5 4 3 2 1

+1.05VS
DG1.1 no M3 U7J POWER +3VS_DAC PVT +3VS
support and not AP51 V24 +1.05VS R208
Intel LAN, VCCLAN VCCACLK[1] VCCIO[5] U7G POWER

1U_0402_6.3V6K
0.052A VCCIO[6] V26 1 2

C466

0.01U_0402_16V7K

10U_0805_6.3V6M

0.1U_0402_16V4Z

0.01U_0402_16V7K
+1.05VS
Source=>GND AP53 VCCACLK[2] VCCIO[7] Y24 1 AB24 VCCCORE[1] VCCADAC[1] AE50

1U_0402_6.3V6K

10U_0603_6.3V6M
Y26 AB26 1_0603_5%
VCCIO[8] VCCCORE[2]

C470

C502

C477

C262

C478

C490
R527 0_0402_5% 1 1 AB28 0.069A AE52 1 1 1 1
VCCCORE[3] VCCADAC[2]
1 2 AF23 VCCLAN[1] VCCSUS3_3[1] V28
2
AD26 VCCCORE[4] 1.524A

CRT
0.344A U28 AD28 AF53 @
VCCSUS3_3[2] VCCCORE[5] VSSA_DAC[1]
1

D @ AF24 U26 AF26 D

1 VCCLAN[2] VCCSUS3_3[3] 2 2 VCCCORE[6] 2 2 2 2
R486 @ C469

VCC CORE
PAD T8 VCCSUS3_3[4] U24 AF28 VCCCORE[7] VSSA_DAC[2] AF51
0_0402_5% 1U_0402_6.3V4Z P28 AF30 +3VS
VCCSUS3_3[5] VCCCORE[8]
1 2 Y20 DCPSUSBYP VCCSUS3_3[6] P26 AF31 VCCCORE[9]
2 C461 0.1U_0402_16V4Z N28 AH26
2

VCCSUS3_3[7] VCCCORE[10] +VCCA_LVDS R213

VCCSUS3_3[8] N26 AH28 VCCCORE[11] 1 2 0.022_0805_1%
AD38 VCCME[1] VCCSUS3_3[9] M28 AH30 VCCCORE[12]

1
+3VALW
VCCSUS3_3[10] M26 AH31 VCCCORE[13] 0.030A VCCALVDS AH38
R214
AD39 L28 AJ30

USB
+1.05VS VCCME[2] VCCSUS3_3[11] VCCCORE[14] 0_0402_5%
VCCSUS3_3[12] L26 AJ31 VCCCORE[15] VSSA_LVDS AH39

0.1U_0402_16V4Z
AD41 J28 @
VCCME[3] VCCSUS3_3[13]

C224
J26 1

2
VCCSUS3_3[14]
0.1uH inductor, 200mA +1.8VS
1U_0402_6.3V6K
AF43 VCCME[4] VCCSUS3_3[15] H28 VCCTX_LVDS[1] AP43
+1.05VS
C471
1 VCCSUS3_3[16] H26 0.059A VCCTX_LVDS[2] AP45
L28
AF41 0.163AVCCSUS3_3[17] G28 AT46

LVDS
VCCME[5] 2 VCCTX_LVDS[3] +VCCTX_LVDS 0.01U_0402_16V7K
VCCSUS3_3[18] G26 AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
AF42 F28 C485 1 1 1 1 0.1UH_MLF1608DR10KT_10%_1608
2 VCCME[6] VCCSUS3_3[19]
1.998A VCCSUS3_3[20] F26

1
0.01U_0402_16V7K C486 C505 SVT C492
UPDATE 0210 V39 VCCME[7] VCCSUS3_3[21] E28 BJ24 VCCAPLLEXP0.042A R528
E26 AB34

Clock and Miscellaneous

VCCSUS3_3[22] VCC3_3[2] 2 2 2 2
V41 VCCME[8] VCCSUS3_3[23] C28 0_0402_5%
+3VS
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

VCCSUS3_3[24] C26 AN20 VCCIO[25] VCC3_3[3] AB35 @

V42 B27 AN22 10U_0603_6.3V6M 10U_0603_6.3V6M

HVCMOS

2
VCCME[9] VCCSUS3_3[25] VCCIO[26]
C516

C503

C515

C504

C475

1 1 1 1 1 VCCSUS3_3[26] A28 AN23 VCCIO[27] VCC3_3[4] AD35 1 2

Y39 A26 +3VALW AN24 C456 0.1U_0402_16V4Z
VCCME[10] VCCSUS3_3[27] VCCIO[28]
AN26 VCCIO[29] check
Y41 VCCME[11] VCCSUS3_3[28] U23 AN28 VCCIO[30]
2 2 2 2 2

0.1U_0402_16V4Z
BJ26 VCCIO[31]

C455
Y42 VCCME[12] VCCIO[56] V23 +1.05VS 1 BJ28 VCCIO[32]
AT26 VCCIO[33]
PCH_V5REF_SUS +1.05VS
C452
>1mA V5REF_SUS F24 AT28 VCCIO[34]
AU26 VCCIO[35]
C +VCCRTCEXT 2 +PCH_VRM +1.8VS C
1 2 V9 DCPRTC AU28 VCCIO[36]

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_16V4Z AV26 R509
VCCIO[37]

C464

C462
1 1 AV28 VCCIO[38] VCCVRM[2] AT24 1 2 0_0402_5%
PCH_V5REF_RUN +1.5VS
0.035A >1mA V5REF K49 AW26 VCCIO[39]
+PCH_VRM AU24 VCCVRM[3] AW28 VCCIO[40]
PCI/GPIO/LPC

+VCCP

DMI
BA26 AT16 R514 1 @ 2 0_0402_5%
+VCCADPLLA +3VS 2 2 VCCIO[41] VCCDMI[1]
0.072A VCC3_3[8] J38 BA28 VCCIO[42] 0.061A
lsolate AF32,AF34,AH34 BB51 VCCADPLLA[1] BB26 VCCIO[43] VCCDMI[2] AU16 1 2
BB53 L38 BB28 C491 1U_0402_6.3V6K
from AH35,AJ35 VCCADPLLA[2] VCC3_3[9] VCCIO[44]
1 BC26 VCCIO[45]
for Intel request 09.09.08 +VCCADPLLB

PCI E*
0.073A M36 C476 BC28
VCC3_3[10] VCCIO[46]

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
BD51 0.357A 0.1U_0402_16V4Z BD26
VCCADPLLB[1] VCCIO[47]
BD53 VCCADPLLB[2] VCC3_3[11] N36 BD28 VCCIO[48]
+1.05VS 2

C473

C474

C514
1 1 1 BE26 AM16 R508 1 2 0_0402_5% +1.8VS
VCCIO[49] VCCPNAND[1]
AH23 VCCIO[21] VCC3_3[12] P36 BE28 VCCIO[50] VCCPNAND[2] AK16

C468

0.1U_0402_16V4Z
AJ35 VCCIO[22] BG26 VCCIO[51] VCCPNAND[3] AK20 1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AH35 U35 BG28 AK19 R501 1 2 0_0402_5% +3VS

VCCIO[23] VCC3_3[13] +3VS 2 2 2 VCCIO[52] VCCPNAND[4]
C472

C465

C484

1 1 1 BH27 VCCIO[53] 0.156A VCCPNAND[5] AK15

@
AF34 VCCIO[2] 3.208A VCCPNAND[6] AK13
2
VCC3_3[14] AD13 1 2 AN30 VCCIO[54] VCCPNAND[7] AM12
C457 0.1U_0402_16V4Z

NAND / SPI
AH34 VCCIO[3] AN31 VCCIO[55] VCCPNAND[8] AM13
2 2 2
VCCPNAND[9] AM15
AF32 VCCIO[4]
VCCSATAPLL[1] AK3 +3VS AN35 VCC3_3[1]
1 2 +VCCSST V12 0.032A AK1
0.1U_0402_16V4Z DCPSST VCCSATAPLL[2]
C453 +3VS
+PCH_VRM AT22 VCCVRM[1] 0.035A
1 2 +V1.1A_INT_VCCSUS Y22 BJ18 6mA AM8
DCPSUS VCCFDIPLL VCCME3_3[1]

0.1U_0402_16V4Z
0.1U_0402_16V4Z AH22 AM9
VCCIO[9] VCCME3_3[2]

C467
FDI
C463 +1.05VS AM23 0.085A AP11 1
VCCIO[1] VCCME3_3[3]
VCCME3_3[4] AP9
B +3VALW P18 AT20 B
VCCSUS3_3[29] VCCVRM[4] +PCH_VRM
1 2 1/3BA4/4W U19
2
SATA

0.1U_0402_16V4Z VCCSUS3_3[30] +1.05VS IBEXPEAK-M_FCBGA1071

PCI/GPIO/LPC

VCCIO[10] AH19
C454 U20 VCCSUS3_3[31]
VCCIO[11] AD20
1U_0402_6.3V6K

U22 VCCSUS3_3[32]
C483

VCCIO[12] AF22 1
+3VS

VCCIO[13] AD19
1 2 1/5BA4/4W V15 AF20
0.1U_0402_16V4Z VCC3_3[5] VCCIO[14] 2 +1.05VS +VCCADPLLA
VCCIO[15] AF19
C139 V16 AH20
VCC3_3[6] VCCIO[16]
Y16 AB19 10uH inductor, 120mA
VCC3_3[7] VCCIO[17] L26
VCCIO[18] AB20 1 2
+VCCP AB22 10UH_LB2012T100MR_20% +5VALW +3VALW +5VS +3VS
VCCIO[19] +1.05VS
VCCIO[20] AD22 1 1
1/2BA2/2W AT18 R521
V_CPU_IO[1]

2
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AA34 +PCH_VCC1_1_20 1 R488 2 0_0402_5% C507 + C494 0_0402_5%

CPU

VCCME[13]
C500

C501

C489

1 1 1 >1mA Y34 +PCH_VCC1_1_21 1 R487 2 0_0402_5% 220U_B2_2.5VM_R35 1U_0402_6.3V4Z @ R423 D6 R438 D9

VCCME[14] +PCH_VCC1_1_22 R489 0_0402_5% 2 10_0402_1% 10_0402_1%
AU18 V_CPU_IO[2] VCCME[15] Y35 1 2
+PCH_VCC1_1_23 R490 0_0402_5% 2 CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
VCCME[16] AA35 1 2

1
2 2 2 +VCCADPLLB
RTC

A12 2mA 6mA L30 R410 1 2 0_0402_5% +3VALW PCH_V5REF_SUS PCH_V5REF_RUN

+RTCVCC VCCRTC VCCSUSHDA
1U_0402_6.3V6K
HDA

10uH inductor, 120mA 20 mils 20 mils

C435

1 R411 1 2 0_0402_5% +1.5V L25 1 2 1 1

3nBA4/4W IBEXPEAK-M_FCBGA1071 @ 10UH_LB2012T100MR_20% C447
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1U_0603_10V6K SVT C448

C442

C440

1 1 1U_0603_10V6K
2 C506 + C493 2 2
A 220U_B2_2.5VM_R35 1U_0402_6.3V4Z A
2
2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(5/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 17 of 50
5 4 3 2 1
 5 4 3 2 1

U7I
U7H
AY7 VSS[159] VSS[259] H49
B11 VSS[160] VSS[260] H5 AB16 VSS[0]
B15 VSS[161] VSS[261] J24
B19 VSS[162] VSS[262] K11 AA19 VSS[1] VSS[80] AK30
D B23 K43 AA20 AK31 D
VSS[163] VSS[263] VSS[2] VSS[81]
B31 VSS[164] VSS[264] K47 AA22 VSS[3] VSS[82] AK32
B35 VSS[165] VSS[265] K7 AM19 VSS[4] VSS[83] AK34
B39 VSS[166] VSS[266] L14 AA24 VSS[5] VSS[84] AK35
B43 VSS[167] VSS[267] L18 AA26 VSS[6] VSS[85] AK38
B47 VSS[168] VSS[268] L2 AA28 VSS[7] VSS[86] AK43
B7 VSS[169] VSS[269] L22 AA30 VSS[8] VSS[87] AK46
BG12 VSS[170] VSS[270] L32 AA31 VSS[9] VSS[88] AK49
BB12 VSS[171] VSS[271] L36 AA32 VSS[10] VSS[89] AK5
BB16 VSS[172] VSS[272] L40 AB11 VSS[11] VSS[90] AK8
BB20 VSS[173] VSS[273] L52 AB15 VSS[12] VSS[91] AL2
BB24 VSS[174] VSS[274] M12 AB23 VSS[13] VSS[92] AL52
BB30 VSS[175] VSS[275] M16 AB30 VSS[14] VSS[93] AM11
BB34 VSS[176] VSS[276] M20 AB31 VSS[15] VSS[94] BB44
BB38 VSS[177] VSS[277] N38 AB32 VSS[16] VSS[95] AD24
BB42 VSS[178] VSS[278] M34 AB39 VSS[17] VSS[96] AM20
BB49 VSS[179] VSS[279] M38 AB43 VSS[18] VSS[97] AM22
BB5 VSS[180] VSS[280] M42 AB47 VSS[19] VSS[98] AM24
BC10 VSS[181] VSS[281] M46 AB5 VSS[20] VSS[99] AM26
BC14 VSS[182] VSS[282] M49 AB8 VSS[21] VSS[100] AM28
BC18 VSS[183] VSS[283] M5 AC2 VSS[22] VSS[101] BA42
BC2 VSS[184] VSS[284] M8 AC52 VSS[23] VSS[102] AM30
BC22 VSS[185] VSS[285] N24 AD11 VSS[24] VSS[103] AM31
BC32 VSS[186] VSS[286] P11 AD12 VSS[25] VSS[104] AM32
BC36 VSS[187] VSS[287] AD15 AD16 VSS[26] VSS[105] AM34
BC40 VSS[188] VSS[288] P22 AD23 VSS[27] VSS[106] AM35
BC44 VSS[189] VSS[289] P30 AD30 VSS[28] VSS[107] AM38
BC52 VSS[190] VSS[290] P32 AD31 VSS[29] VSS[108] AM39
BH9 VSS[191] VSS[291] P34 AD32 VSS[30] VSS[109] AM42
BD48 VSS[192] VSS[292] P42 AD34 VSS[31] VSS[110] AU20
BD49 VSS[193] VSS[293] P45 AU22 VSS[32] VSS[111] AM46
BD5 VSS[194] VSS[294] P47 AD42 VSS[33] VSS[112] AV22
C BE12 R2 AD46 AM49 C
VSS[195] VSS[295] VSS[34] VSS[113]
BE16 VSS[196] VSS[296] R52 AD49 VSS[35] VSS[114] AM7
BE20 VSS[197] VSS[297] T12 AD7 VSS[36] VSS[115] AA50
BE24 VSS[198] VSS[298] T41 AE2 VSS[37] VSS[116] BB10
BE30 VSS[199] VSS[299] T46 AE4 VSS[38] VSS[117] AN32
BE34 VSS[200] VSS[300] T49 AF12 VSS[39] VSS[118] AN50
BE38 VSS[201] VSS[301] T5 Y13 VSS[40] VSS[119] AN52
BE42 VSS[202] VSS[302] T8 AH49 VSS[41] VSS[120] AP12
BE46 VSS[203] VSS[303] U30 AU4 VSS[42] VSS[121] AP42
BE48 VSS[204] VSS[304] U31 AF35 VSS[43] VSS[122] AP46
BE50 VSS[205] VSS[305] U32 AP13 VSS[44] VSS[123] AP49
BE6 VSS[206] VSS[306] U34 AN34 VSS[45] VSS[124] AP5
BE8 VSS[207] VSS[307] P38 AF45 VSS[46] VSS[125] AP8
BF3 VSS[208] VSS[308] V11 AF46 VSS[47] VSS[126] AR2
BF49 VSS[209] VSS[309] P16 AF49 VSS[48] VSS[127] AR52
BF51 VSS[210] VSS[310] V19 AF5 VSS[49] VSS[128] AT11
BG18 VSS[211] VSS[311] V20 AF8 VSS[50] VSS[129] BA12
BG24 VSS[212] VSS[312] V22 AG2 VSS[51] VSS[130] AH48
BG4 VSS[213] VSS[313] V30 AG52 VSS[52] VSS[131] AT32
BG50 VSS[214] VSS[314] V31 AH11 VSS[53] VSS[132] AT36
BH11 VSS[215] VSS[315] V32 AH15 VSS[54] VSS[133] AT41
BH15 VSS[216] VSS[316] V34 AH16 VSS[55] VSS[134] AT47
BH19 VSS[217] VSS[317] V35 AH24 VSS[56] VSS[135] AT7
BH23 VSS[218] VSS[318] V38 AH32 VSS[57] VSS[136] AV12
BH31 VSS[219] VSS[319] V43 AV18 VSS[58] VSS[137] AV16
BH35 VSS[220] VSS[320] V45 AH43 VSS[59] VSS[138] AV20
BH39 VSS[221] VSS[321] V46 AH47 VSS[60] VSS[139] AV24
BH43 VSS[222] VSS[322] V47 AH7 VSS[61] VSS[140] AV30
BH47 VSS[223] VSS[323] V49 AJ19 VSS[62] VSS[141] AV34
BH7 VSS[224] VSS[324] V5 AJ2 VSS[63] VSS[142] AV38
C12 VSS[225] VSS[325] V7 AJ20 VSS[64] VSS[143] AV42
C50 VSS[226] VSS[326] V8 AJ22 VSS[65] VSS[144] AV46
B D51 W2 AJ23 AV49 B
VSS[227] VSS[327] VSS[66] VSS[145]
E12 VSS[228] VSS[328] W52 AJ26 VSS[67] VSS[146] AV5
E16 VSS[229] VSS[329] Y11 AJ28 VSS[68] VSS[147] AV8
E20 VSS[230] VSS[330] Y12 AJ32 VSS[69] VSS[148] AW14
E24 VSS[231] VSS[331] Y15 AJ34 VSS[70] VSS[149] AW18
E30 VSS[232] VSS[332] Y19 AT5 VSS[71] VSS[150] AW2
E34 VSS[233] VSS[333] Y23 AJ4 VSS[72] VSS[151] BF9
E38 VSS[234] VSS[334] Y28 AK12 VSS[73] VSS[152] AW32
E42 VSS[235] VSS[335] Y30 AM41 VSS[74] VSS[153] AW36
E46 VSS[236] VSS[336] Y31 AN19 VSS[75] VSS[154] AW40
E48 VSS[237] VSS[337] Y32 AK26 VSS[76] VSS[155] AW52
E6 VSS[238] VSS[338] Y38 AK22 VSS[77] VSS[156] AY11
E8 VSS[239] VSS[339] Y43 AK23 VSS[78] VSS[157] AY43
F49 VSS[240] VSS[340] Y46 AK28 VSS[79] VSS[158] AY47
F5 VSS[241] VSS[341] P49
G10 Y5 IBEXPEAK-M_FCBGA1071
VSS[242] VSS[342]
G14 VSS[243] VSS[343] Y6
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
A A

IBEXPEAK-M_FCBGA1071

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IBEX-M(6/6)-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 18 of 50
5 4 3 2 1
 5 4 3 2 1

U22A
6 PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_N[0..15] Part 1 of 5 10/01 Add GPIO5 GPIO6
PCIE_CTX_GRX_P0 AE12 N1
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 PEX_RX0 GPIO0
6 PCIE_CTX_GRX_P[0..15] AF12 PEX_RX0_N GPIO1 G1 HDMI_DETECT_VGA 24 Device ID GPU_VID0 GPU_VID1 VGA_CORE P-State
PCIE_CTX_GRX_P1 AG12 C1
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N1 PEX_RX1 GPIO2 NV_INVTPWM 27
6 PCIE_CRX_GTX_N[0..15] AG13
PEX_RX1_N GPIO3
M2 VGA_ENVDD_R 27 0 0 0.8V Deep P12
PCIE_CTX_GRX_P2 AF13 M3 N11M-GE1/LP1
PCIE_CRX_GTX_P[0..15] PEX_RX2 GPIO4 VGA_ENABLT 27
PCIE_CTX_GRX_N2 AE13 K3 1 2 GPU_VID0 0x0A7D 0.85V P8
6 PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_P3 AE15
PEX_RX2_N GPIO5
K2 R511 1 2 0_0402_5% HYBRID@ GPU_VID1 GPU_VID0 45 (40nm) 0 1
PCIE_CTX_GRX_N3 PEX_RX3 GPIO6 GPU_VID1 45
AF15 J2 R512 0_0402_5% HYBRID@ 0.9V P0
PCIE_CTX_GRX_P4 AG15
PEX_RX3_N GPIO7
C2 1 2
1 1

GPIO
PCIE_CTX_GRX_N4 PEX_RX4 GPIO8 R577 1
AG16 PEX_RX4_N GPIO9 M1 2 0_0402_5% HYBRID@ +3VS_DELAY
PCIE_CTX_GRX_P5 AF16 D2 R579 0_0402_5% HYBRID@
PCIE_CTX_GRX_N5 PEX_RX5 GPIO10 VGA_GPIO11 VGA_GPIO11
AE16 D1
PCIE_CTX_GRX_P6 PEX_RX5_N GPIO11 VGA_GPIO14
AE18 PEX_RX6 GPIO12 J3

1
D PCIE_CTX_GRX_N6 D
AF18 J1
PEX_RX6_N GPIO13

1
PCIE_CTX_GRX_P7 AG18 K1 VGA_GPIO14
PCIE_CTX_GRX_N7 PEX_RX7 GPIO14 R513 R505
AG19 F3
PCIE_CTX_GRX_P8 PEX_RX7_N GPIO15 10K_0402_5%
AF19 PEX_RX8 GPIO16 G3 10K_0402_5%
PCIE_CTX_GRX_N8 AE19 G2 @ @

2
PCIE_CTX_GRX_P9 PEX_RX8_N GPIO17
AE21 F1

2
PCIE_CTX_GRX_N9 PEX_RX9 GPIO18
AF21 PEX_RX9_N GPIO19 F2
PCIE_CTX_GRX_P10 AG21
PCIE_CTX_GRX_N10 PEX_RX10
AG22 AD2 VGA_HSYNC 26
PCIE_CTX_GRX_P11 PEX_RX10_N DACA_HSYNC
AF22 PEX_RX11 DACA_VSYNC AD1 VGA_VSYNC 26

DACA
PCIE_CTX_GRX_N11 AE22
PCIE_CTX_GRX_P12 PEX_RX11_N VGA_CRT_R
AE24 AE2 VGA_CRT_R 26
PCIE_CTX_GRX_N12 PEX_RX12 DACA_RED VGA_CRT_B VGA_CRT_R R537
AF24 AD3 1 HYBRID@
2 150_0402_1%
PCIE_CTX_GRX_P13 AG24
PEX_RX12_N DACA_BLUE
AE3 VGA_CRT_G
VGA_CRT_B 26
VGA_CRT_G 26
CRT OUT VGA_CRT_G R538 1 HYBRID@
2 150_0402_1%
PCIE_CTX_GRX_N13 PEX_RX13 DACA_GREEN VGA_CRT_B R530
AF25 PEX_RX13_N 1 HYBRID@
2 150_0402_1%
PCIE_CTX_GRX_P14 AG25 AF1 DACA_VREF 2 1
PCIE_CTX_GRX_N14 PEX_RX14 DACA_VREF DACA_RSET

PCI EXPRESS
AG26 AE1 C81 0.1U_0402_16V4Z
PCIE_CTX_GRX_P15 PEX_RX14_N DACA_RSET HYBRID@
HYBRID@ PCIE_CTX_GRX_N15
AF27
PEX_RX15
AE27 U6
PEX_RX15_N DACB_HSYNC R48 HYBRID@ 124_0402_1%
DACB_VSYNC U4
PCIE_CRX_GTX_P0 C120 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_P0 AD10

DACB
PCIE_CRX_GTX_N0 C119 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N0 PEX_TX0
1 2 AD11 PEX_TX0_N DACB_RED T5
PCIE_CRX_GTX_P1 C118 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_P1 AD12 R4
PCIE_CRX_GTX_N1 C117 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N1 PEX_TX1 DACB_BLUE
1 2 AC12 T4
PCIE_CRX_GTX_P2 C80 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P2 PEX_TX1_N DACB_GREEN
1 2 AB11 PEX_TX2
PCIE_CRX_GTX_N2 C79 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_N2 AB12 R6
PCIE_CRX_GTX_P3 C78 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P3 PEX_TX2_N DACB_VREF
1 2 AD13 PEX_TX3 DACB_RSET V6
PCIE_CRX_GTX_N3 C77 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_N3 AD14
PCIE_CRX_GTX_P4 C116 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P4 PEX_TX3_N
1 2 AD15
PCIE_CRX_GTX_N4 C115 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N4 PEX_TX4
1 2 AC15
PCIE_CRX_GTX_P5 C114 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P5 PEX_TX4_N JTAG_TCK
1 2 AB14 PEX_TX5 JTAG_TCK AF3 PAD T14
PCIE_CRX_GTX_N5 C113 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_N5 AB15 AG4 JTAG_TDI
C PEX_TX5_N JTAG_TDI PAD T13 C
PCIE_CRX_GTX_P6 C112 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_P6 AC16 AE4 JTAG_TDO

TEST
PEX_TX6 JTAG_TDO PAD T12
PCIE_CRX_GTX_N6 C111 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_N6 AD16 AF4 JTAG_TMS PAD
PCIE_CRX_GTX_P7 PCIE_CRX_C_GTX_P7 PEX_TX6_N JTAG_TMS JTAG_TRST_N T11
C109 HYBRID@
1 2 0.1U_0402_16V7K AD17 AG3 1 2
PCIE_CRX_GTX_N7 C110 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N7 PEX_TX7 JTAG_TRST_N R539 HYBRID@ 10K_0402_5%
1 2 AD18 PEX_TX7_N
PCIE_CRX_GTX_P8 C108 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_P8 AC18 AD25 TESTMODE 1 2
PCIE_CRX_GTX_N8 C107 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N8 PEX_TX8 TESTMODE R24 HYBRID@ 10K_0402_5% +3VS_DELAY
1 2 AB18 PEX_TX8_N
PCIE_CRX_GTX_P9 C105 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_P9 AB19 1 2
PCIE_CRX_GTX_N9 C106 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N9 PEX_TX9 10K_0402_5% @ R25
1 2 AB20 +3VS_DELAY
PCIE_CRX_GTX_P10 C104 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P10 PEX_TX9_N VGA_DDCCLK_C +3VS_DELAY
1 2 AD19 R1
PCIE_CRX_GTX_N10 C103 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N10 PEX_TX10 I2CA_SCL VGA_DDCDATA_C
1 2 AD20 PEX_TX10_N I2CA_SDA T3
PCIE_CRX_GTX_P11 C102 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_P11 AD21
PCIE_CRX_GTX_N11 C101 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N11 PEX_TX11 I2CB_SCL R517 1 HYBRID@ 2.2K_0402_5%
1 2 AC21 R2 2
PCIE_CRX_GTX_P12 C100 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P12 PEX_TX11_N I2CB_SCL I2CB_SDA R516 1 2.2K_0402_5% R499 R478 +3VS_DELAY
1 2 AB21
PEX_TX12 I2CB_SDA
R3 2
PCIE_CRX_GTX_N12 C99 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_N12 AB22 HYBRID@ 2.2K_0402_5% 2.2K_0402_5%
PCIE_CRX_GTX_P13 C98 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P13 PEX_TX12_N VGA_LVDS_SCL_C HYBRID@ HYBRID@
1 2 AC22 A2

I2C
PCIE_CRX_GTX_N13 C97 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N13 PEX_TX13 I2CC_SCL VGA_LVDS_SDA_C VGA_LVDS_SCL_C R64
1 2 AD22 B1 2 HYBRID@
1 2.2K_0402_5%
PCIE_CRX_GTX_P14 C96 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_P14 PEX_TX13_N I2CC_SDA
1 2 AD23
PCIE_CRX_GTX_N14 C95 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N14 PEX_TX14 HDCP_SMB_CK1 VGA_LVDS_SDA_C R63
1 2 AD24 PEX_TX14_N I2CH_SCL A3 2 HYBRID@
1 2.2K_0402_5%
PCIE_CRX_GTX_P15 C94 HYBRID@
1 2 0.1U_0402_16V7K PCIE_CRX_C_GTX_P15 AE25 A4 HDCP_SMB_DAI
PCIE_CRX_GTX_N15 C93 HYBRID@ 0.1U_0402_16V7K PCIE_CRX_C_GTX_N15 PEX_TX15 I2CH_SDA
1 2 AE26 PEX_TX15_N
T1 SMB_EC_CK2_R I2CS is VDD33 power plane
I2CS_SCL SMB_EC_CK2_R 14
CLK_PCIE_VGA AB10 T2 SMB_EC_DA2_R
14 CLK_PCIE_VGA
CLK_PCIE_VGA# AC10
PEX_REFCLK I2CS_SDA SMB_EC_DA2_R 14 same as EC +3.3VS.
14 CLK_PCIE_VGA# PEX_REFCLK_N
I2CS is internal thermal sensor.
AF10
PEX_TSTCLK_OUT
1 2 AE10
PEX_TSTCLK_OUT_N XTAL_SSIN
D11 Removed external HDCP.
R540 200_0402_5% @
1 2 AG10 E9 07/17/2009
R541 2.49K_0402_1% HYBRID@ PEX_TERMP XTAL_OUTBUFF

1
PLTRST_VGA# AD9 E10 XTALOUT
CLK

16 PLTRST_VGA# PEX_RST_N XTAL_OUT

1
R42
1

AE9 D10 XTALIN 10K_0402_5% R34

B R46 PEX_CLKREQ_N XTAL_IN HYBRID@ 10K_0402_5% B

10K_0402_5% HYBRID@

2
@ HYBRID@ N11M-LP1_BGA533

2
+3VS_DELAY 1 2 10K_0402_5% HYBRID@
2

R542

+3VS
PVT, org SM010010710 121T03
2

L17 HYBRID@ 0_0603_5%

R543 VGA_DDCCLK_C 1 2
Q50 VGA_DDCCLK 26
10K_0402_5% Y2 VGA_DDCDATA_C 1 2
2N7002_SOT23 VGA_DDCDATA 26
4 3 L18 HYBRID@ 0_0603_5%
GND OUT HYBRID@ 0_0603_5%
1

PEG_CLKREQ# 1 3 1 2 VGA_LVDS_SCL_C L8 1 2
D

14 PEG_CLKREQ# IN GND VGA_LVDS_SCL 27

VGA_LVDS_SDA_C 1 2 VGA_LVDS_SDA 27
27MHZ_16PF_X7S027000BG1H-U L7 HYBRID@ 0_0603_5%
1 HYBRID@ 1
G
2

1 1 1 1
C69 C56 C450 C451 C86 C85
20P_0402_50V8 20P_0402_50V8
+3VS_DELAY
HYBRID@2 2 HYBRID@ @ @ @ @
2 2 2 2

12P_0402_50V8J 12P_0402_50V8J 12P_0402_50V8J 12P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M-GE1 PCIE,GPIO,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-5941P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 19 of 50
5 4 3 2 1
 5 4 3 2 1

FBAA[0..13]
23 FBAA[0..13]
FBBA[2..5]
23 FBBA[2..5]
FBADQM[0..7] VGA_LVDS_ACLK#
23 FBADQM[0..7] VGA_LVDS_ACLK
FBADQS[0..7] 1 1
23 FBADQS[0..7]
C1216
FBADQS#[0..7] 12P_0402_50V8J C1217
23 FBADQS#[0..7] 12P_0402_50V8J
@
FBA_D[0..63] 2 2 @
23 FBAD[0..63]
RF 10/22
U22B
D Part 2 of 5 D
FBA_D0 FBAA4
FBA_D1
D22
E24
FBA_D0 FBA_CMD0 F26
J24 FBARAS#
LVDS U22C
FBA_D1 FBA_CMD1 FBARAS# 23
FBA_D2 E22 F25 FBAA5 Part 3 of 5
FBA_D3 FBA_D2 FBA_CMD2 FBA_BA1 VGA_LVDS_ACLK AC4
D24 M23 FBA_BA1 23 27 VGA_LVDS_ACLK C15
FBA_D4 FBA_D3 FBA_CMD3 FBBA2 VGA_LVDS_ACLK# AD4 IFPA_TXC NC
D26 N27 D15

NC
FBA_D4 FBA_CMD4 27 VGA_LVDS_ACLK# IFPA_TXC_N NC
FBA_D5 D27 M27 FBBA4 VGA_LVDS_A0 V5 J5
FBA_D5 FBA_CMD5 27 VGA_LVDS_A0 IFPA_TXD0 NC
FBA_D6 C27 K26 FBBA3 VGA_LVDS_A0# V4
FBA_D6 FBA_CMD6 27 VGA_LVDS_A0# IFPA_TXD0_N
FBA_D7 B27 J25 FBBA_CKE VGA_LVDS_A1 AA5
FBA_D7 FBA_CMD7 FBBA_CKE 23 27 VGA_LVDS_A1 IFPA_TXD1

1
FBA_D8 A21 J27 FBBACS0# VGA_LVDS_A1# AA4
FBA_D8 FBA_CMD8 FBBACS0# 23 27 VGA_LVDS_A1# IFPA_TXD1_N
FBA_D9 B21 G23 FBAA11 R22 27 VGA_LVDS_A2 VGA_LVDS_A2 W4
FBA_D10 FBA_D9 FBA_CMD9 FBACAS# 10K_0402_5% VGA_LVDS_A2# IFPA_TXD2
C21 G26 FBACAS# 23 27 VGA_LVDS_A2# Y4 T6
FBA_D11 FBA_D10 FBA_CMD10 FBAWE# HYBRID@ IFPA_TXD2_N RFU_1
C19 J23 AB4 W6

RFU
FBA_D12 FBA_D11 FBA_CMD11 FBA_BA0 FBAWE# 23 IFPA_TXD3 RFU_2
C18 M25 AB5 Y6

2
FBA_D13 FBA_D12 FBA_CMD12 FBBA5 FBA_BA0 23 IFPA_TXD3_N RFU_3
D18 FBA_D13 FBA_CMD13 K27 RFU_4 AA6
FBA_D14 B18 G25 FBAA12 N3
FBA_D14 FBA_CMD14 FBAA12 23 RFU_5
FBA_D15 C16 FBA_D15 FBA_CMD15 L24 FBA_RST
FBA_RST 23 +3VS_DELAY AB3 IFPB_TXC

1
FBA_D16 E21 K23 FBAA7 AB2
MEMORY INTERFACE

FBA_D17 FBA_D16 FBA_CMD16 FBAA10 R16 IFPB_TXC_N

F21 K24 W1
FBA_D18 FBA_D17 FBA_CMD17 FBAA_CKE 10K_0402_5% IFPB_TXD4 STRAP0
D20 FBA_D18 FBA_CMD18 G22 FBAA_CKE 23 V1 IFPB_TXD4_N STRAP0 C7 STRAP0 22
FBA_D19 FBAA0 HYBRID@

STRAP
F20 K25 W3

LVDS / TMDS
FBA_D19 FBA_CMD19 IFPB_TXD5

2
FBA_D20 D17 H22 FBAA9 W2 B9 STRAP1

2
FBA_D21 FBA_D20 FBA_CMD20 FBAA6 IFPB_TXD5_N STRAP1 STRAP1 22
F18 M26 R23 R526 R531 AA2
FBA_D22 FBA_D21 FBA_CMD21 FBAA2 10K_0402_5% IFPB_TXD6 STRAP2
D16 H24 4.7K_0402_5% 4.7K_0402_5% AA3 A9 STRAP2 22
FBA_D23 FBA_D22 FBA_CMD22 FBAA8 HYBRID@ HYBRID@ HYBRID@ IFPB_TXD6_N STRAP2
E16 FBA_D23 FBA_CMD23 F27 AB1 IFPB_TXD7
FBA_D24 A22 J26 FBAA3 AA1

1
FBA_D25 FBA_D24 FBA_CMD24 FBAA1 IFPB_TXD7_N
FBA_D26
C24
D21
FBA_D25 FBA_CMD25 G24
G27 FBAA13
HDMI
FBA_D27 FBA_D26 FBA_CMD26 FBA_BA2
B22 M24 FBA_BA2 23 24 VGA_HDMI_SCL G4 N5
FBA_D28 FBA_D27 FBA_CMD27 FBBAODT0 IFPC_AUX_I2CW_SCL BUFRST_N
C22 K22 FBBAODT0 23 24 VGA_HDMI_SDA G5
FBA_D29 FBA_D28 FBA_CMD28 FBAACS0# IFPC_AUX_I2CW_SDA_N +3VS_DELAY
A25 FBA_D29 FBA_CMD29 J22 FBAACS0# 23 24 VGA_HDMI_TX2+ P4 IFPC_L0
FBA_D30 B25 L22 FBAAODT0 N4
24 VGA_HDMI_TX2-

GENERAL
FBA_D30 FBA_CMD30 FBAAODT0 23 IFPC_L0_N

1
C FBA_D31 C
A26 FBA_D31 24 VGA_HDMI_TX1+ M5 IFPC_L1 THERMDN D8 PAD T2

1
FBA_D32 U24 C26 FBADQM0 R18 24 VGA_HDMI_TX1- M4
FBA_D32 FBA_DQM0 IFPC_L1_N

1
FBA_D33 V24 B19 FBADQM1 10K_0402_5% 24 VGA_HDMI_TX0+ L4 D9 PAD R445
FBA_D34 FBA_D33 FBA_DQM1 FBADQM2 IFPC_L2 THERMDP T3
V23 D19 R15 HYBRID@ 24 VGA_HDMI_TX0- K4 10K_0402_5%
FBA_D35 FBA_D34 FBA_DQM2 FBADQM3 10K_0402_5% IFPC_L2_N HYBRID@
R24 D23 24 VGA_HDMI_CLK+ H4

2
FBA_D36 FBA_D35 FBA_DQM3 FBADQM4 HYBRID@ IFPC_L3 +3VS_DELAY
T23 T24 24 VGA_HDMI_CLK- J4

2
FBA_D37 FBA_D36 FBA_DQM4 FBADQM5 IFPC_L3_N
R23 AA23 N2
2

FBA_D37 FBA_DQM5 CEC

1
FBA_D38 P24 AB27 FBADQM6
FBA_D39 FBA_D38 FBA_DQM6 FBADQM7 SPDIF_IN
P22 T26 D3 F9 1 HYBRID@2 R468
FBA_D40 FBA_D39 FBA_DQM7 IFPD_AUX_I2CX_SCL SPDIF R32 36K_0402_5% 10K_0402_5%
AC24 FBA_D40 D4 IFPD_AUX_I2CX_SDA_N
FBA_D41 AB23 D25 FBADQS#0 F5 HYBRID@
FBA_D42 FBA_D41 FBA_DQS_RN0 FBADQS#1 IFPD_L0
AB24 A18 F4

2
FBA_D43 FBA_D42 FBA_DQS_RN1 FBADQS#2 IFPD_L0_N
W24 E18 E4 B10
FBA_D44 FBA_D43 FBA_DQS_RN2 FBADQS#3 IFPD_L1 ROM_CS_N
AA22 B24 D5

SERIAL
FBA_D45 FBA_D44 FBA_DQS_RN3 FBADQS#4 IFPD_L1_N ROM_SCLK
W23 FBA_D45 FBA_DQS_RN4 R22 C3 IFPD_L2 ROM_SCLK C9 ROM_SCLK 22
FBA_D46 W22 Y24 FBADQS#5 C4
FBA_D47 FBA_D46 FBA_DQS_RN5 FBADQS#6 IFPD_L2_N ROM_SI
V22 AA27 B3 A10 ROM_SI 22
FBA_D48 FBA_D47 FBA_DQS_RN6 FBADQS#7 IFPD_L3 ROM_SI
AA25 FBA_D48 FBA_DQS_RN7 R27 B4 IFPD_L3_N
FBA_D49 W27 C10 ROM_SO
FBA_D50 FBA_D49 FBADQS0 ROM_SO ROM_SO 22
W26 FBA_D50 FBA_DQS_WP0 C25
FBA_D51 W25 A19 FBADQS1 +1.5VS_VGA F7
FBA_D52 FBA_D51 FBA_DQS_WP1 FBADQS2 IFPE_AUX_I2CY_SCL
AB25 E19 G6
FBA_D53 FBA_D52 FBA_DQS_WP2 FBADQS3 IFPE_AUX_I2CY_SDA_N
AB26 A24 D6
FBA_D53 FBA_DQS_WP3 IFPE_L0

1
FBA_D54 AD26 T22 FBADQS4 C6 AB6 1 2
FBA_D55 FBA_D54 FBA_DQS_WP4 FBADQS5 R30 IFPE_L0_N IFPAB_RSET R44 @ 1K_0402_1%
AD27 AA24 A6
FBA_D56 FBA_D55 FBA_DQS_WP5 FBADQS6 1.3K_0402_1% IFPE_L1
V25 AA26 A7 R5 1 2
FBA_D57 FBA_D56 FBA_DQS_WP6 FBADQS7 @ IFPE_L1_N IFPC_RSET R39 HYBRID@ 1K_0402_1%
R25 FBA_D57 FBA_DQS_WP7 T27 B6 IFPE_L2
FBA_D58 V26 B7 M6 1 2
1.27V~0.9V
2

FBA_D59 FBA_D58 FB_VREF1 10mil IFPE_L2_N IFPD_RSET R40 @ 1K_0402_1%

V27 A16 E6
FBA_D60 FBA_D59 FB_VREF IFPE_L3
R26 E7 F8 1 2
FBA_D61 FBA_D60 IFPE_L3_N IFPE_RSET R477 @ 1K_0402_1%
T25 F24 FBACLK0 23
FBA_D61 FBA_CLK0
1

FBA_D62 N25 F23 1

B FBA_D63 FBA_D62 FBA_CLK0_N FBACLK0# 23 B
N26 C43 R29 N11M-LP1_BGA533
FBA_D63 0.01U_0402_16V7K 1.3K_0402_1% HYBRID@
N24 FBACLK1 23
FBA_CLK1 @ @
N23 FBACLK1# 23
FBA_CLK1_N 2
2

M22 1 R26 2 +1.5VS_VGA

FBA_DEBUG 10K_0402_5%HYBRID@

N11M-LP1_BGA533
HYBRID@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M-GE1 LVDS,Memory Bus
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-5941P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 20 of 50
5 4 3 2 1
 5 4 3 2 1

+1.5VS_VGA
NEAR BGA PLACE UNDER GPU CLOSE TO GPU
0.01U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
+VGA_CORE 4.7U 6.3V K X5R 0603

NEAR BALL U22D

1 1 1 1 1 1
1 N11M-GE1:2.55A
Part 4 of 5 C53 C28 C27 C42 C32 C31 C24
4.7U 6.3V K X5R 0603 0.047U_0402_16V7K 0.01U_0402_16V7K J9 A13 HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@
VDD FBVDDQ 2 2 2 2 2 2
J10 VDD FBVDDQ B13
J12 C13 2
1 1 1 1 VDD FBVDDQ
1 J13 D13 0.01U_0402_16V7K 0.01U_0402_16V7K 0.047U_0402_16V7K
C26 C50 C38 C39 C40 VDD FBVDDQ
L9 VDD FBVDDQ D14
HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ M9 E13
2 2 2 2 VDD FBVDDQ
D M11 VDD FBVDDQ F13 D
2 M17 F14
VDD FBVDDQ
0.1U_0402_10V7K 0.01U_0402_16V7K N9 VDD FBVDDQ F15 +1.05VS_VGA
N11 F16
N12
VDD
VDD
FBVDDQ
FBVDDQ F17
NEAR BALL NEAR BGA 2A
0.047U_0402_16V7K 0.01U_0402_16V7K N13 F19
VDD FBVDDQ 0.1U_0402_10V7K 1U_0402_6.3V6K 4.7U 6.3V K X5R 0603 22U_0805_6.3V6M
N14 VDD FBVDDQ F22
N15 H23
N10M-GS: 15.8A 1 1 1
N16
VDD
VDD
FBVDDQ
FBVDDQ H26 1 1 1 1 1 1 1
C41 C37 C29 N17 J15
N11M-GE1:16.7A 2
HYBRID@
2
HYBRID@
2
HYBRID@ N19
P11
VDD
VDD
FBVDDQ
FBVDDQ J16
J18
C46
HYBRID@
C58
HYBRID@
C83
HYBRID@
C35 C537 C538 C552
HYBRID@ HYBRID@ HYBRID@ HYBRID@
VDD FBVDDQ 2 2 2 2 2 2 2
P12 VDD FBVDDQ J19
0.01U_0402_16V7K P13 L19
VDD FBVDDQ 0.1U_0402_10V7K 1U_0402_6.3V6K 10U_0805_6.3V6M
P14 VDD FBVDDQ L23
0.047U_0402_16V7K 0.01U_0402_16V7K P15 L26
VDD FBVDDQ
P16 VDD FBVDDQ M19
P17 N22
1 1 1
R9
VDD
VDD
FBVDDQ
FBVDDQ U22 NEAR BALL NEAR BGA +1.05VS_VGA
C36 C52 C51 R11 Y22 0.1U_0402_10V7K 1U_0402_6.3V6K 4.7U 6.3V K X5R 0603

POWER
HYBRID@ HYBRID@ HYBRID@ VDD FBVDDQ
R12 VDD
2 2 2 R13 AG6
VDD PEX_IOVDDQ 1 1 1 1 1 1 1
R14 VDD PEX_IOVDDQ AF6
0.01U_0402_16V7K R15 AE6 C47 C60 C59 C49 C48 C551 C553
VDD PEX_IOVDDQ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@
R16 VDD PEX_IOVDDQ AD6
R17 AC13 2 2 2 2 2 2 2
VDD PEX_IOVDDQ
T9 VDD PEX_IOVDDQ AC7
T11 AB17 0.1U_0402_10V7K 0.1U_0402_10V7K 1U_0402_6.3V6K 10U_0805_6.3V6M
VDD PEX_IOVDDQ
T17 VDD PEX_IOVDDQ AB16 +1.05VS_VGA
+3VS_DELAY U9 AB13
NEAR BGA NEAR BALL U19
VDD
VDD
PEX_IOVDDQ
PEX_IOVDDQ AB9 NEAR BGA 120mA
W9 AB8 L3
C 1U_0402_6.3V6K 0.1U_0402_10V7K VDD PEX_IOVDDQ 1U_0402_6.3V6K C
W 10 VDD PEX_IOVDDQ AB7 1 2
W 12 MBK1608121YZF_0603
VDD
W 13 AG7
120mA 1 1 1 1 1
W 18
VDD
VDD
PEX_IOVDD
PEX_IOVDD AF7
1 1
HYBRID@
C84 C459 C44 C55 C54 W 19 AE7 C45 C57
HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ VDD PEX_IOVDD HYBRID@ HYBRID@
PEX_IOVDD AD8
2 2 2 2 2 AD7 2 2
PEX_IOVDD
A12 VDD33 PEX_IOVDD AC9
4.7U 6.3V K X5R 0603 0.1U_0402_10V7K 0.1U_0402_10V7K B12 4.7U 6.3V K X5R 0603
VDD33 +PEX_PLLVDD
C12 VDD33 PEX_PLLVDD AF9
D12 VDD33
E12 K6
F12
VDD33
VDD33
VID_PLLVDD NEAR BALL NEAR BGA +1.05VS_VGA
L6 +SP_PLLVDD
SP_PLLVDD 0.1U_0402_10V7K 1U_0402_6.3V6K MBK1608121YZF_0603
+1.8VS_VGA NEAR BGA +PEX_SVDD_3V3 +1.05VS_PLL
AG9 K5 2 1
L27 NEAR BALL PEX_SVDD_3V3 PLLVDD
12~16mil 1 1 1 1 L21 VID_PLLVDD=45mA
MBK1608121YZF_0603 1U_0402_6.3V6K R19 HYBRID@
FB_PLLAVDD
1
HYBRID@
2
1 1 1
0.1U_0402_10V7K
1
+IFPA_IOVDD V3 IFPA_IOVDD
AC19
C480 C481
HYBRID@ HYBRID@
C65 C482
HYBRID@ HYBRID@
SP_PLLVDD=45mA
FB_PLLAVDD 2 2 2 2
300mA C512 C499 C510 C511
V2 IFPB_IOVDD
FB_DLLAVDD T19 +FB_PLLAVDD PLLVDD=60mA
HYBRID@ HYBRID@ HYBRID@ HYBRID@ +IFPC_IOVDD J6 0.1U_0402_10V7K 4.7U 6.3V K X5R 0603
2 2 2 2 IFPC_IOVDD
4.7U 6.3V K X5R 0603 2 1 H6 AG2 +DACA_VDD
IFPDE_IOVDD DACA_VDD
0.1U_0402_10V7K 10K_0402_5% R41 +1.05VS_VGA
HYBRID@ W5 +DACB_VDD 1 2
+IFPAB_PLLVDD DACB_VDD R45 HYBRID@ 10K_0402_5% L24
AD5 IFPAB_PLLVDD +SP_PLLVDD 1U_0402_6.3V6K 1 2
+IFPC_PLLVDD P6 B15 MBK1608121YZF_0603
IFPC_PLLVDD FB_CAL_PD_VDDQ +1.5VS_VGA
R465 HYBRID@
40.2_0402_1% 1 1 HYBRID@
B 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2 N6 W 15 The power is base on VRAM type. B
R49 0_0402_5% IFPD_PLLVDD VDD_SENSE C64 C488
1 1 1
HYBRID@ D7 E15 +VGASENSE +VGASENSE 45 HYBRID@ HYBRID@
C498 C497 C496 IFPE_PLLVDD VDD_SENSE 2 2
HYBRID@ HYBRID@ HYBRID@ 4.7U 6.3V K X5R 0603
2 2 2 N11M-LP1_BGA533
HYBRID@
0.1U_0402_10V7K 2 1 @ +1.05VS_VGA
10K_0402_5% R47 NEAR BALL L30 +3VS_DELAY
2 1 HYBRID@
NEAR BGA 10K_0402_5% R43 MBK1608121YZF_0603 NEAR BGA L1
+1.05VS_VGA +PEX_SVDD_3V3 2 1 +FB_PLLAVDD 1U_0402_6.3V6K 1 2
L4 HYBRID@ MBK1608121YZF_0603
MBK1608121YZF_0603 HYBRID@
NEAR BALL 1
C458 120mA 1 1

1 2 1U_0402_6.3V6K 0.1U_0402_10V7K HYBRID@ C30 C23 FB_PLLVDD=100mA

HYBRID@ HYBRID@ HYBRID@

285mA 1 1 1 1
2 2 2
FB_DLLVDD=100mA
C68 C67 C74 C66 0.1U_0402_10V7K 4.7U 6.3V K X5R 0603
HYBRID@ HYBRID@ HYBRID@ HYBRID@
2 2 2 2
L29
4.7U 6.3V K X5R 0603 0.1U_0402_10V7K +1.05VS_VGA NEAR BGA NEAR BALL NEAR BGAMBK1608121YZF_0603
+3VS_DELAY

L5 HYBRID@ 1U_0402_6.3V6K +DACA_VDD 4700P_0402_25V7K 0.1U_0402_10V7K 1U_0402_6.3V6K 2 1

1 2 +IFPAB_PLLVDD HYBRID@

NEAR BGA MBK1608121YZF_0603

1 1 1 1 1 1 1 1 1
120mA
C82 C71 C523 C522 C520 C513 C521 C519 C524
+3VS_DELAY 220mA 2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@HYBRID@
2 2
HYBRID@
2
HYBRID@
A
L6 HYBRID@ NEAR BALL A

1 2 1U_0402_6.3V6K 0.1U_0402_10V7K +IFPC_PLLVDD 4.7U 6.3V K X5R 0603 470P_0402_50V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 4.7U 6.3V K X5R 0603

MBK1608121YZF_0603
1 1 1 1 1
220mA C73 C72 C62 C63 C61
HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@
2 2 2 2 2
0.1U_0402_10V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
4.7U 6.3V K X5R 0603 0.1U_0402_10V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M-GE1 PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5941P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 21 of 50
5 4 3 2 1
 5 4 3 2 1

A total of 8 signals are required for GB1 strapping this includes

2 reference signals
6 physical strapping pins
4 logical strapping bits
U22E A total of 24 logical strapping bits are available
B2 Part 5 of 5 U2
GND GND
B5 GND GND U5
B8 GND GND U11
B11 U12
GND GND
B14 U13
GND GND +3VS
B17 GND GND U14
D D
B20 U15
GND GND
B23 GND GND U16
B26 U17
GND GND
E2 GND GND U23

1
E5 U26 R472 R473
GND GND

1
E8 V9 R474 R51 R469 R467
GND GND

34.8K_0402_1%

45.3K_0402_1%
PVT 34.8K_0402_1% @ @ @

HYBRID@

HYBRID@
E11 GND GND V19

2K_0402_5%
4.99K_0402_1%
E17 W11 DeviceID 0A6E HYBRID@
GND GND

2K_0402_5%
E20 W14

2
GND GND
E23 W17

2
GND GND STRAP2
E26 Y2 20 STRAP2
GND GND STRAP1
H2 Y5 20 STRAP1
GND GND

GND
H5 Y23 STRAP0
GND GND 20 STRAP0 ROM_SCLK
J11 GND GND Y26 20 ROM_SCLK
J14 AC2 ROM_SI
GND GND 20 ROM_SI
J17 AC5 ROM_SO
GND GND 20 ROM_SO
K9 GND GND AC6
K19 AC8
GND GND

1
L2 AC11
GND GND R475 R471 R476 R50 R470 R466
L5 GND GND AC14
@ @ @ X76@

HYBRID@

HYBRID@
L11 GND GND AC17

10K_0402_5%

15K_0402_1%

20K_0402_1%

10K_0402_5%
24.9K_0402_1%

34.8K_0402_1%
L12 GND GND AC20
L13 AC23

2
GND GND
L14 AC26
GND GND
L15 GND GND AF2
L16 GND GND AF5
L17 GND GND AF8
M12 GND GND AF11
M13 AF14
GND GND
M14 AF17
GND GND
M15 GND GND AF20
M16 GND GND AF23
C C
P2 GND GND AF26
P5 GND GND T16
P9 T15
GND GND
P19 GND GND T14
P23 GND GND F6
P26 GND
T12 A15 R28 1 HYBRID@
2 40.2_0402_1%
GND FB_CAL_PU_GND
T13
GND R27
B16 1 2 60.4_0402_1% STRAP1 use for 3GIO_PADCFG to set 35K pull up.
FB_CAL_TERM_GND HYBRID@
W16 F11
(PUN-04335-001_V10 HW9 update)
GND_SENSE MULTI_STRAP_REF1_GND
E14 F10
GND_SENSE MULTI_STRAP_REF0_GND
1

1
R463 R464 GPU FB Memory (DDR3) ROM_SO ROM_SCLK ROM_SI STRAP2 STRAP1 STRAP0
N11M-LP1_BGA533 40.2K_0402_1% 40.2K_0402_1%
HYBRID@ HYBRID@ HYBRID@
Place Components Close to BGA Samsung K4W1G1646E-HC12
2

800MHz
N11M-GE1 (defaul) 64Mx16 PD 10K PD 15K PD 20K PU 30K PU 35K PU 45K
LP1
(0x0A7D) Hynix H5TQ1G63BFR-12C
40nm 800MHz
Memory/PKG FBVDDQ FB_CAL_PU_GND FBCAL_PD_VDDQ FBCAL_TERM_GND 64Mx16 PD 10K PD 15K PD 15K PU 30K PU 35K PU 45K
N11M-GE1
LP1 X76
DDR3 +1.5VS 40.2 ohm 40.2 ohm 40.2/60.4 ohm
B B

Must be used 1% resister for driver calibration DG-04642-001-V01(May 22, 2009)

HYBRID@ 1021 add
+1.8VS_VGA
+5VALW DGPU_PWR_RC_EN# +1.8VS
HYBRID@ W=60mils

2
+3VS_DELAY
R86 @ R911 R156
+5VALW 150_0603_1% 100K_0402_5% 0_0402_5%
HYBRID@ @ 1
R17 @ +3VS C628 @
W=60mils 2

1
1

150_0603_1% 4.7U_0805_10V4Z

3
S
R910 HYBRID@ PVT,timing
100K_0402_5% VGA1.8EN- 1 2 2
G 2
3

1
3

C597 @ Q59B R959

2

Q36B 4.7U_0805_10V4Z 2N7002DW-T/R7_SOT363-6 100K_0402_1% 1 Q75 HYBRID@

3

S D
2N7002DW-T/R7_SOT363-6 PVT,timing 5 HYBRID@ SI2301BDS-T1-E3_SOT23-3
HYBRID@

1
3VDELAY- DGPU_PWR_RC_EN# 2
G 2
HYBRID@ 5 1 2
C1209 HYBRID@
+1.8VS_VGA
4

R958 2 0.1U_0402_16V4Z
4

33K_0402_1% 1 Q73 HYBRID@ R762

6

D
SI2301BDS-T1-E3_SOT23-3 +1.8VS_DELAY_R2 1
HYBRID@
1

+3VS_DELAY Q59A 0_0603_5%

C1208 HYBRID@ 2N7002DW-T/R7_SOT363-6 PVT,chg AO3413 main
2 0.1U_0402_16V4Z DGPU_PWR_EN
16,39,45 DGPU_PWR_EN 2 2 HYBRID@ HYBRID@
R761
Q36A +3VS_DELAY_R 2 1
1

A 0_0603_5% A
2N7002DW-T/R7_SOT363-6
PVT,chg AO3413 main
HYBRID@
HYBRID@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N10M-GE1 GND & STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-5941P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 22 of 50
5 4 3 2 1
 5 4 3 2 1

+VRAM_VREFB +VRAM_VREFB +VRAM_VREFD +VRAM_VREFD

N10x 40nm DDR3 MAPPING +VRAM_VREFC +VRAM_VREFC

+VRAM_VREFA +VRAM_VREFA
NVIDIA COCUMENT FOR DA-3978-001
U21 U2 U1 U23

FBAA[0..13] M9 E4 FBAD9 M9 E4 FBAD21 M9 E4 FBAD37 M9 E4 FBAD42

20 FBAA[0..13] VREFCA DQL0 FBAD14 VREFCA DQL0 FBAD17 VREFCA DQL0 FBAD36 VREFCA DQL0 FBAD46
H2 F8 H2 F8 H2 F8 H2 F8
FBBA[2..5] VREFDQ DQL1 FBAD8 VREFDQ DQL1 FBAD20 VREFDQ DQL1 FBAD35 VREFDQ DQL1 FBAD40
F3 F3 F3 F3
20 FBBA[2..5] FBAA0 DQL2 FBAD12 FBAA0 DQL2 FBAD16 FBAA0 DQL2 FBAD32 FBAA0 DQL2 FBAD45
FBADQM[0..7]
N4
A0 DQL3
F9 1 N4
A0 DQL3
F9 2 N4
A0 DQL3
F9 N4
A0 DQL3
F9
FBAA1 P8 H4 FBAD10 FBAA1 P8 H4 FBAD22 FBAA1 P8 H4 FBAD39 4 FBAA1 P8 H4 FBAD41 5
20 FBADQM[0..7] A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
FBAA2 P4 H9 FBAD13 FBAA2 P4 H9 FBAD18 FBBA2 P4 H9 FBAD34 FBBA2 P4 H9 FBAD47
FBADQS[0..7] FBAA3 A2 DQL5 FBAD11 FBAA3 A2 DQL5 FBAD23 FBBA3 A2 DQL5 FBAD38 FBBA3 A2 DQL5 FBAD44
20 FBADQS[0..7] N3 G3 N3 G3 N3 G3 N3 G3
FBAA4 A3 DQL6 FBAD15 FBAA4 A3 DQL6 FBAD19 FBBA4 A3 DQL6 FBAD33 FBBA4 A3 DQL6 FBAD43
P9 H8 P9 H8 P9 H8 P9 H8
FBADQS#[0..7] FBAA5 A4 DQL7 FBAA5 A4 DQL7 FBBA5 A4 DQL7 FBBA5 A4 DQL7
20 FBADQS#[0..7] P3 P3 P3 P3
FBAA6 A5 FBAA6 A5 FBAA6 A5 FBAA6 A5
R9 R9 R9 R9
FBAA7 A6 FBAD26 FBAA7 A6 FBAD4 FBAA7 A6 FBAD61 FBAA7 A6 FBAD50
R3 D8 R3 D8 R3 D8 R3 D8
D FBAD[0..63] FBAA8 A7 DQU0 FBAD29 FBAA8 A7 DQU0 FBAD1 FBAA8 A7 DQU0 FBAD57 FBAA8 A7 DQU0 FBAD52 D
20 FBAD[0..63] T9 C4 T9 C4 T9 C4 T9 C4
FBAA9 A8 DQU1 FBAD24 FBAA9 A8 DQU1 FBAD7 FBAA9 A8 DQU1 FBAD56 FBAA9 A8 DQU1 FBAD49
R4 C9 R4 C9 R4 C9 R4 C9
FBAA10 A9 DQU2 FBAD25 FBAA10 A9 DQU2 FBAD0 FBAA10 A9 DQU2 FBAD62 FBAA10 A9 DQU2 FBAD53
L8
A10/AP DQU3
C3 3 L8
A10/AP DQU3
C3 L8
A10/AP DQU3
C3 L8
A10/AP DQU3
C3
FBAA11 R8 A8 FBAD28 FBAA11 R8 A8 FBAD5 0 FBAA11 R8 A8 FBAD58 7 FBAA11 R8 A8 FBAD48 6
FBAA12 A11 DQU4 FBAD31 FBAA12 A11 DQU4 FBAD2 FBAA12 A11 DQU4 FBAD63 FBAA12 A11 DQU4 FBAD54
N8 A3 N8 A3 N8 A3 N8 A3
FBAA13 A12 DQU5 FBAD27 FBAA13 A12 DQU5 FBAD6 FBAA13 A12 DQU5 FBAD59 FBAA13 A12 DQU5 FBAD51
T4 B9 T4 B9 T4 B9 T4 B9
A13 DQU6 FBAD30 A13 DQU6 FBAD3 A13 DQU6 FBAD60 A13 DQU6 FBAD55
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8
A15/BA3 +1.5VS_VGA M8
A15/BA3 +1.5VS_VGA M8
A15/BA3 +1.5VS_VGA M8
A15/BA3 +1.5VS_VGA

FBA_BA0 M3 B3 FBA_BA0 M3 B3 FBA_BA0 M3 B3 FBA_BA0 M3 B3

20 FBA_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
FBA_BA1 N9 D10 FBA_BA1 N9 D10 FBA_BA1 N9 D10 FBA_BA1 N9 D10
20 FBA_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
FBA_BA2 M4 G8 FBA_BA2 M4 G8 FBA_BA2 M4 G8 FBA_BA2 M4 G8
20 FBA_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
K3 K3 K3 K3
VDD VDD VDD VDD
K9 K9 K9 K9
VDD VDD VDD VDD
N2 N2 N2 N2
VDD FBACLK0 VDD FBACLK1 VDD FBACLK1 VDD
20 FBACLK0 J8 N10 J8 N10 20 FBACLK1 J8 N10 J8 N10
CK VDD FBACLK0# CK VDD FBACLK1# CK VDD FBACLK1# CK VDD
20 FBACLK0# K8 R2 K8 R2 20 FBACLK1# K8 R2 K8 R2
FBAA_CKE CK VDD FBAA_CKE CK VDD CK VDD FBBA_CKE CK VDD
20 FBAA_CKE K10
CKE/CKE0 VDD
R10 +1.5VS_VGA K10
CKE/CKE0 VDD
R10 +1.5VS_VGA FBBA_CKE
K10
CKE/CKE0 VDD
R10 +1.5VS_VGA K10
CKE/CKE0 VDD
R10 +1.5VS_VGA
20 FBBA_CKE
FBAAODT0 K2 A2 FBAAODT0 K2 A2 FBBAODT0 K2 A2 FBBAODT0 K2 A2
20 FBAAODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 20 FBBAODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBAACS0# L3 A9 FBAACS0# L3 A9 FBBACS0# L3 A9 FBBACS0# L3 A9
20 FBAACS0# CS VDDQ CS VDDQ 20 FBBACS0# CS VDDQ CS VDDQ
FBARAS# J4 C2 FBARAS# J4 C2 FBARAS# J4 C2 FBARAS# J4 C2
20 FBARAS# RAS VDDQ RAS VDDQ RAS VDDQ RAS VDDQ
FBACAS# K4 C10 FBACAS# K4 C10 FBACAS# K4 C10 FBACAS# K4 C10
20 FBACAS# CAS VDDQ CAS VDDQ CAS VDDQ CAS VDDQ
FBAWE# L4 D3 FBAWE# L4 D3 FBAWE# L4 D3 FBAWE# L4 D3
20 FBAWE# WE VDDQ WE VDDQ WE VDDQ WE VDDQ
E10 E10 E10 E10
VDDQ VDDQ VDDQ VDDQ
F2 F2 F2 F2
FBADQS1 VDDQ FBADQS2 VDDQ FBADQS4 VDDQ FBADQS5 VDDQ
F4 H3 F4 H3 F4 H3 F4 H3
FBADQS3 DQSL VDDQ FBADQS0 DQSL VDDQ FBADQS7 DQSL VDDQ FBADQS6 DQSL VDDQ
C8 H10 C8 H10 C8 H10 C8 H10
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

FBADQM1 E8 A10 FBADQM2 E8 A10 FBADQM4 E8 A10 FBADQM5 E8 A10

FBADQM3 DML VSS FBADQM0 DML VSS FBADQM7 DML VSS FBADQM6 DML VSS
D4 B4 D4 B4 D4 B4 D4 B4
DMU VSS DMU VSS DMU VSS DMU VSS
E2 E2 E2 E2
VSS VSS VSS VSS
G9 G9 G9 G9
FBADQS#1 VSS FBADQS#2 VSS FBADQS#4 VSS FBADQS#5 VSS
G4 J3 G4 J3 G4 J3 G4 J3
FBADQS#3 DQSL VSS FBADQS#0 DQSL VSS FBADQS#7 DQSL VSS FBADQS#6 DQSL VSS
C B8 J9 B8 J9 B8 J9 B8 J9 C
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
M2 M2 M2 M2
VSS VSS VSS VSS
M10 M10 M10 M10
VSS VSS VSS VSS
P2 P2 P2 P2
FBA_RST VSS FBA_RST VSS FBA_RST VSS FBA_RST VSS
20 FBA_RST T3 P10 T3 P10 T3 P10 T3 P10
RESET VSS RESET VSS RESET VSS RESET VSS
T2 T2 T2 T2
VSS VSS VSS VSS
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J2 B2 J2 B2 J2 B2 J2 B2
R12 NC/ODT1 VSSQ R21 NC/ODT1 VSSQ R7 NC/ODT1 VSSQ R523 NC/ODT1 VSSQ
L2 B10 L2 B10 L2 B10 L2 B10
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2 240_0402_1% J10 D2
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L10 D9 L10 D9 L10 D9 L10 D9
HYBRID@ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ HYBRID@ NCZQ1 VSSQ
E3 E3 E3 E3
2

2
VSSQ HYBRID@ VSSQ HYBRID@ VSSQ VSSQ
A1 E9 A1 E9 A1 E9 A1 E9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
A11 F10 A11 F10 A11 F10 A11 F10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T1 G2 T1 G2 T1 G2 T1 G2
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3

K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100 K4B1G1646D-HCF8_FBGA100

X76@ X76@ X76@ X76@

FBACLK0
2

HYBRID@
+1.5VS_VGA
243_0402_1% +1.5VS_VGA +1.5VS_VGA
R442
FBACLK0# 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
1

1
1 1 1 1 1 1
R20 R11
B +VRAM_VREFA +VRAM_VREFB B
FBACLK1 C21 C518 C444 C3 C6 C7 10U_0603_6.3V6M 1.33K_0402_1% 1.33K_0402_1%
1

HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@

R14 2 2 2 2 2 2

2
243_0402_1% 10U_0603_6.3V6M
HYBRID@ 10U_0603_6.3V6M
12MIL 12MIL
FBACLK1#
2

C4
C22
1 1

0.1U_0402_10V6K

0.1U_0402_10V6K
R19 R10
1.33K_0402_1% HYBRID@ 1.33K_0402_1% HYBRID@
+1.5VS_VGA HYBRID@ HYBRID@
2 2

2
1U_0402_6.3V6K 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1
C517

C509

C128

C5

C20

C487

C479

C437

C445

C446

C525
HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@
2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1U_0402_6.3V6K 1U_0402_6.3V6K +1.5VS_VGA +1.5VS_VGA

+1.5VS_VGA

1
+1.5VS_VGA
220U_B2_2.5VM_R35

R9 R529
1.33K_0402_1% +VRAM_VREFC 1.33K_0402_1% +VRAM_VREFD
1
C436

1U_0402_6.3V6K 1U_0402_6.3V6K HYBRID@ HYBRID@

+ 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K

2
12MIL 12MIL
2 1 1 1 1 1 1 1 1 1 1
C526

C438

C10

C9

C18

C17

C12

C11

C16

C19

1
C8

C495
1 1

0.1U_0402_10V6K

0.1U_0402_10V6K
HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ HYBRID@ R8 R522
2 2 2 2 2 2 2 2 2 2 1.33K_0402_1% 1.33K_0402_1%
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K HYBRID@ HYBRID@ HYBRID@ HYBRID@
A HYBRID@ 1U_0402_6.3V6K 1U_0402_6.3V6K 2 2 A

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDR3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-5941P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 23 of 50
5 4 3 2 1
 5 4 3 2 1

From VGA
C284 1 2 0.1U_0402_16V7K HYBRID@ HDMI_CLK+_CK
20 VGA_HDMI_CLK+ +3VS_DELAY
C283 1 2 0.1U_0402_16V7K HYBRID@ HDMI_CLK-_CK
20 VGA_HDMI_CLK-
C282 1 2 0.1U_0402_16V7K HYBRID@ HDMI_TX0+_CK
20 VGA_HDMI_TX0+
C281 1 2 0.1U_0402_16V7K HYBRID@ HDMI_TX0-_CK
20 VGA_HDMI_TX0-
C601 1 2 0.1U_0402_16V7K HYBRID@ HDMI_TX1+_CK
20 VGA_HDMI_TX1+
C600 1 2 0.1U_0402_16V7K HYBRID@ HDMI_TX1-_CK
20 VGA_HDMI_TX1-
D C614 1 2 0.1U_0402_16V7K HYBRID@ HDMI_TX2+_CK D
20 VGA_HDMI_TX2+

5
C599 1 2 0.1U_0402_16V7K HYBRID@ HDMI_TX2-_CK
20 VGA_HDMI_TX2-
4 3 HDMIDAT_R
Near L33,L34,L35,L36 20 VGA_HDMI_SDA
Q84B HYBRID@

2
2N7002DW -T/R7_SOT363-6

1 6 HDMICLK_R
From Level Shiftter 20 VGA_HDMI_SCL
Q84A HYBRID@ 1 1
2N7002DW -T/R7_SOT363-6 C611 C603
25 HDMI_CLK+_CK HDMI_CLK+_CK
25 HDMI_CLK-_CK HDMI_CLK-_CK HYBRID@ HYBRID@
HDMI_TX0+_CK 2 2
25 HDMI_TX0+_CK
25 HDMI_TX0-_CK HDMI_TX0-_CK 12P_0402_50V8J 12P_0402_50V8J
25 HDMI_TX1+_CK HDMI_TX1+_CK
25 HDMI_TX1-_CK HDMI_TX1-_CK
25 HDMI_TX2+_CK HDMI_TX2+_CK
25 HDMI_TX2-_CK HDMI_TX2-_CK
+3VS

25 HP_DET#

2
R615
10K_0402_1%
UMA@

1
C DGPU_HPD_INT# R618 1 2 0_0402_5% HP_DET# C
16 DGPU_HPD_INT#

1
D
HYBRID@
2 HP_DET
G

2
+3VS_DELAY S 1 C678

3
Q53 0.1U_0402_16V4Z R616
2N7002W -T/R7_SOT323-3 100K_0402_5%

2
R617 2

1
10K_0402_1%
HDMI_CLK+_CONN 1 2 HYBRID@
R585 HYBRID@ 499_0402_1%

1
HDMI_CLK-_CONN 1 2 HDMI_DETECT_VGA
19 HDMI_DETECT_VGA
R583 HYBRID@ 499_0402_1%

1
HDMI_TX0+_CONN D
1 2
R589 HYBRID@ 499_0402_1% 2
W=40mils
HDMI_TX0-_CONN 1 2 G R581 0_0805_5%
R587 HYBRID@ 499_0402_1% HYBRID@S

3
HDMI_TX1+_CONN 1 2 Q52 +5VS @
D28 F2
R593 HYBRID@ 499_0402_1% 2N7002W -T/R7_SOT323-3
1

HDMI_TX1-_CONN D
1 2 2 1+5VS_HDMI_R 2 1
R591 HYBRID@ 499_0402_1% 2 +3VS
HDMI_TX2+_CONN 1 2 G PMEG2010ET SOT23
R597 HYBRID@ 499_0402_1% HYBRID@ 1.1A_6V_SMD1812P110TF
S
3

HDMI_TX2-_CONN 1 2 Q41 R603 0_0805_5%

R595 HYBRID@ 499_0402_1% 2N7002W -T/R7_SOT323-3
@
B
NEAR CONNECT +5VS_HDMI B
L33 @ 1 C627
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN 0.1U_0402_16V4Z
1 2

2
HDMI_CLK-_CK HDMI_CLK-_CONN R249 R257 2
4 4 3 3
2.2K_0402_5% 2.2K_0402_5%
W CM-2012-900T_4P

1
PVT
L34 @ JHDMI1 DIP type
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN HP_DET 19
1 2 25 HP_DET HP_DET
18 +5V
17 DDC/CEC_GND
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN 25 HDMIDAT_R HDMIDAT_R 16
4 3 HDMICLK_R SDA
25 HDMICLK_R 15 SCL
W CM-2012-900T_4P 14 Reserved
13 CEC
L35 @ HDMI_CLK-_CONN 12 20
HDMI_TX1+_CK HDMI_TX1+_CONN CK- GND1
1 1 2 2 11 CK_shield GND2 21
HDMI_CLK+_CONN 10
HDMI_TX0-_CONN CK+
9 D0-
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN 8
4 3 HDMI_TX0+_CONN D0_shield
7 D0+
W CM-2012-900T_4P +5VS +5VS HDMI_TX1-_CONN 6 D1-
5 D1_shield
L36 @ 3 3 HDMI_TX1+_CONN 4
HDMI_TX2+_CK HDMI_TX2+_CONN HDMI_TX2-_CONN D1+
1 1 2 2 3 D2-
1 HDMIDAT_R 1 HDMICLK_R 2
HDMI_TX2+_CONN D2_shield
A 1 D2+ A
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 2 @ 2 @
4 3 D24 D25 FOX_QJ1119L-NVBT-7H
W CM-2012-900T_4P BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
ME@
HDMI_CLK+_CK R584 1 2 0_0402_5% HDMI_CLK+_CONN
HDMI_CLK-_CK R582 1 2 0_0402_5% HDMI_CLK-_CONN
HDMI_TX0+_CK R588 1 2 0_0402_5% HDMI_TX0+_CONN Security Classification Compal Secret Data Compal Electronics, Inc.
HDMI_TX0-_CK R586 1 2 0_0402_5% HDMI_TX0-_CONN 2010/01/13 2011/01/13 Title
Issued Date Deciphered Date
HDMI_TX1+_CK R592 1 2 0_0402_5% HDMI_TX1+_CONN
HDMI_TX1-_CK R590 1 2 0_0402_5% HDMI_TX1-_CONN HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_TX2+_CK R596 1 2 0_0402_5% HDMI_TX2+_CONN Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HDMI_TX2-_CK R594 1 2 0_0402_5% HDMI_TX2-_CONN Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 24 of 50
5 4 3 2 1
 5 4 3 2 1

P/N:SA00003GT00 (ASM1442)

FOR asmedia R428 STUFF

RESERVE THE R668 PULL UP TO 3VS
D RESERVE THE R670 PULL DOWN TO GND +3VS
D

1442_VCC
CHANGE R245 FROM 499 TO 3.4K OHM 1442_VCC 1 R559 2 0_0805_5%
1 1 1 1
U12 UMA@ UMA@ UMA@ UMA@
C280 C602 C604 C285
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
HP_DET# 2 2 2 2
24 HP_DET# 25 OE#
1442_VCC 2
HDMICLK_R VCC
24 HDMICLK_R 28 SCL_SINK VCC 11 2R332 0_0402_5%
1 1442_VCC
15 2R333 0_0402_5%
1
output VCC
1

24 HDMIDAT_R HDMIDAT_R 29 21
R242 SDA_SINK VCC
VCC 26
4.7K_0402_5% 33 4.7K_0402_5%
VCC R247 1 @
UMA@ 24 HP_DET 30 HPD_SINK VCC 40 2
46 4.7K_0402_5%
2

VCC R334 1 @
32 DDC_EN 2
1442_VCC
1

4.7K_0402_5%
@ R254 1 2 @ 34 R246 1 2 UMA@ 4.7K_0402_5%
R243
1442_VCC
R255 1 CFG0 PC1 4
2 @ 35 CFG1 3
PC0 internal
R248 1 2 @ 4.7K_0402_5%
0_0402_5% 4.7K_0402_5% pull down
internal pull down
2

6 R245 1 2 UMA@ 3.4K_0402_1%

REXT

2
R674 100K_0402_5%
R244 R256 7 TMDS_B_HPD TMDS_B_HPD 2 1
C internal pull down HPD# TMDS_B_HPD 15 C
4.7K_0402_5% 4.7K_0402_5%
8 SVT HYBRID@
@ @ SDA HDMIDAT_NB 15
CLOSE ASM1442
input
1

1
SCL 9 HDMICLK_NB 15

10 R232 1 @ 2 4.7K_0402_5% 1442_VCC

RT_EN#

48 13 HDMI_CLK+_CK
15 TMDS_B_CLK IN_D4+ OUT_D4+ HDMI_CLK+_CK 24
47 14 HDMI_CLK-_CK
15 TMDS_B_CLK# IN_D4- OUT_D4- HDMI_CLK-_CK 24
45 16 HDMI_TX0+_CK
15 TMDS_B_DATA0 IN_D3+ OUT_D3+ HDMI_TX0+_CK 24
44 17 HDMI_TX0-_CK
15 TMDS_B_DATA0# IN_D3- OUT_D3- HDMI_TX0-_CK 24
42 19 HDMI_TX1+_CK
15 TMDS_B_DATA1 IN_D2+ OUT_D2+ HDMI_TX1+_CK 24
41 20 HDMI_TX1-_CK
15 TMDS_B_DATA1# IN_D2- OUT_D2- HDMI_TX1-_CK 24
15 TMDS_B_DATA2 39 22 HDMI_TX2+_CK
IN_D1+ OUT_D1+ HDMI_TX2-_CK HDMI_TX2+_CK 24
15 TMDS_B_DATA2# 38 IN_D1- OUT_D1- 23 HDMI_TX2-_CK 24

GND 1
TMDS_B_CLK# 5
GND
GND 12
1

GND 18
R670 24
GND
2.2K_0402_5% GND 27
B B
UMA@ GND 31

2
36
2

SVT GND R280 R331

GND 37
43 R261 0_0402_5% 0_0402_5%
GND
PAD 49 0_0402_5% FOR PS8171

1
ASM1442_QFN48_7X7
UMA@
Pin1 R331 NC
Pin3 R248,R334 NC
Pin4 R246,R247 NC
Pin6 R245 499ohm
Pin11 R332 NC
Pin12 R280 NC
Pin27 R261 NC
Pin33 R333 NC
Pin34 R254 4.7K ohm
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
Level Shiftter_ASM1442
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 25 of 50
5 4 3 2 1
 A B C D E

+5VS +5VS

3 3

1 JVGA_HS 1 JVGA_VS

2 2
@ @
D27 D26
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
UMA ONLY BYPASS
DAC_RED 1 2 CRT_R
1 R92 UMA@ 0_0402_5% 1
DAC_GRN 1 2 CRT_G FCM1608CF-121T03 0603 R682 0_0603_5%
R91 UMA@ 0_0402_5% CRT_R 1 2 R_L 1 2 RED
DAC_BLU 1 2 CRT_B L11
R93 UMA@ 0_0402_5% FCM1608CF-121T03 0603 R683 0_0603_5%
CRT_HSYNC 1 2 HSYNC_G CRT_G 1 2 G_L 1 2 GREEN
SVT R129 UMA@ 33_0402_1% L10
CRT_VSYNC 1 2 VSYNC_G FCM1608CF-121T03 0603 R684 0_0603_5%
R130 UMA@ 33_0402_1% CRT_B 1 2 B_L 1 2 BLUE
CRT_DDC_DATA 1 2 CRT_DAT L9

1
R322 UMA@ 0_0402_5% 1 1 1 1 1 1 1 1 1
CRT_DDC_CLK 1 2 CRT_CLK C136
R328 UMA@ 0_0402_5% R153 R131 R90 C158 C146 C137 C145 10P_0402_50V8J
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J SVT C157 10P_0402_50V8J
PVT 2 2 2 2 2 2 2 10P_0402_50V8J
2 2

2
10P_0402_50V8J 10P_0402_50V8J C809@
CLOSE TO CONN 22P_0402_50V8J
C808@ C810 @ +5VS +CRT_VCC
+3VS D21
U38 HYBRID@ 22P_0402_50V8J22P_0402_50V8J
2 1
4 1 CRT_R
VDD A0 CRT_G PMEG2010ET SOT23
16 VDD A1 2
23 5 CRT_B Trace length <3.6' from switch to conn.
VDD A2

2
29 6 HSYNC_G
VDD A3 VSYNC_G F1
From VGA 32 VDD A4 7
W=40mils 1.1A_6V_SMD1812P110TF
27 8 DGPU_SELECT# L: A -> B1(VGA)
19 VGA_CRT_R 0B1 SEL1 DGPU_SELECT# 16,27
25
19 VGA_CRT_G H: A -> B2(PCH)

1
2 1B1 2
19 VGA_CRT_B 22 2B1
20 9 CRT_DAT
19 VGA_HSYNC 3B1 A5
18 10 CRT_CLK 1
19 VGA_VSYNC 4B1 A6
19 VGA_DDCDATA VGA_DDCDATA 12 +3VS +CRT_VCC
VGA_DDCCLK 5B1 DGPU_DDC_SEL# C629
19 VGA_DDCCLK 14 6B1 SEL2 30
0.1U_0402_16V4Z
2

1
15 DAC_RED DAC_RED 26
DAC_GRN 0B2
15 DAC_GRN 24 1B2
15 DAC_BLU DAC_BLU 21 3 R157 R158
2B2 GND

5
CRT_HSYNC 19 11 2.2K_0402_5% 2.2K_0402_5%
15 CRT_HSYNC 3B2 GND
CRT_VSYNC 17 28
15 CRT_VSYNC

2
CRT_DDC_DATA 4B2 GND CRT_DDC_DAT_CONN JCRT1
15 CRT_DDC_DATA 13 5B2 GND 31 4 3
15 CRT_DDC_CLK CRT_DDC_CLK 15 33 +CRT_VCC_F 1
6B2 GPAD Q99B RED 1
2 2

2
2N7002DW -T/R7_SOT363-6 3
PI3V712-AZLEX_TQFN32_6X3~D GREEN 3
From PCH 4 4
1 6 CRT_DDC_CLK_CONN 5
BLUE 5
6 6
Q99A 1 1 7
2N7002DW -T/R7_SOT363-6 @ @ JVGA_VS 7
8 8
C178 C177 9
100P_0402_50V8J 68P_0402_50V8K JVGA_HS 9
10 10
+3VS 2 2 CRT_DDC_DAT_CONN 11 11
CRT_DDC_CLK_CONN 12 12
13 G1
+CRT_VCC 14 G2
1

R381 R610 E&T_3703-E12N-03R

3 2.2K_0402_5% 2.2K_0402_5% ME@ 3
1
PVT R441 0_0402_5% C619
CRT Connector
2

CRT_DDC_DATA 1 2 DGPU_SELECT# 0.1U_0402_16V4Z

CRT_DDC_CLK @ 2

1
R443 0_0402_5%
DGPU_DDC_SEL# 1 2

OE#
P
DGPU_EDIDSEL# 16,27
HSYNC_G 2 4 CRT_HSYNC_1 1 2 JVGA_HS
+3VS_DELAY A Y L32

G
U26 FCM1608CF-121T03 0603
SN74AHCT1G125DCKR_SC70-5 1

3
@
1

C626
R159 R162 10P_0402_50V8J
2.2K_0402_5% 2.2K_0402_5% +CRT_VCC 2
HYBRID@ HYBRID@

2
2

VGA_DDCDATA 1 R956
VGA_DDCCLK 1K_0402_5%
C620
0.1U_0402_16V4Z

1
2

1
OE#
P
VSYNC_G 2 4 CRT_VSYNC_1 1 2 JVGA_VS
A Y L31

G
U25 FCM1608CF-121T03 0603 1
SN74AHCT1G125DCKR_SC70-5

3
4
@ C625 4
10P_0402_50V8J
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 26 of 50
A B C D E
 5 4 3 2 1

470P_0402_50V7K
+LCDVDD +5VALW LCD POWER CIRCUIT LCD_COLOR_1 +LEDVDD B+

1 @ 1 R549 2 0_0805_5%

1
SVT +3VS C370
R13 R31
W=60mils C567
1 1
150_0603_1% 1K_0402_1% D36 CH751H-40PT_SOD323-2 JLVDS1 680P_0402_50V7K C566
2 1 2 @ 4.7U_0805_25V6-K
1 1
C539 2 2

2
4.7U_0805_10V4Z 2

3
D R38 220K_0402_5%
S 3
G 2 34 DCR_EN 4
2 ENVDD# 1 2 ENVDD#_R 2 DISPOFF#
Q3 G SVT INVPWM 5
2N7002_SOT23 S +3VS R370 1 6
34 LCD_COLOR_EN 2 680_0402_5% LCD_COLOR_1 INVPWM

3
Q4 CONN_LVDS_ACLK 7
1

1
C34
D
SI2301BDS-T1-E3_SOT23-3 +3VS CONN_LVDS_ACLK# 8 DCR_EN

1
D 9 D

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
OUT
0.1U_0402_16V4Z CONN_LVDS_A2 10 DISPOFF#
1 11
2 680P_0402_50V7K CONN_LVDS_A2# C15
C14 12
15 PCH_ENVDD 2
IN 13 1 @ 1 @ 1 @
PVT,chg AO3413 main @ R392 R395 CONN_LVDS_A1 C13 C296

GND
2 2.2K_0402_5% CONN_LVDS_A1# 14
2.2K_0402_5%

1
Q95 15
16 2 2 2
For EMI
DTC124EKAT146_SC59-3 W=60mils CONN_LVDS_A0

3
R37 @ +LCDVDD +LCDVDD_CONN CONN_LVDS_A0# 17
L2 +LCDVDD_CONN 18
100K_0402_5% CONN_LVDS_SDA
CONN_LVDS_SCL 19
1 2
2

1
20
FBMA-L11-201209-221LMA30T_0805
W=60mils 21 +3VS
1 1

OUT
C33 C25 22
23
+3VS

1
4.7U_0805_10V4Z 0.1U_0402_16V4Z 24
19 VGA_ENVDD_R 2
IN 2 2 DMIC 33 INT_MIC_DATA 25 R250

GND
1 33 INT_MIC_CLK 26
Q12 USB20_P2 27 4.7K_0402_5%
16 USB20_P2 28 D12
R65 @ DTC124EKAT146_SC59-3 CMOS 16 USB20_N2 USB20_N2

2
100K_0402_5% 29 BKOFF# DISPOFF#
+CMOS_PW 34 BKOFF# 1 2
30
2

ACES_88341-3000B001 CH751H-40PT_SOD323-2

ME@

DGPU_EDID_SEL +3VS
LVDS switch1 +3VS EDIDSEL# PWMSEL#

1
PVT, change TI to ST main
U42 L: VGA R35 PVT
C FROM VGA LVDS 4 1K_0402_1% C
VCC
10
H: PCH

5
VGA_LVDS_A0# VCC HYBRID@ 1 HYBRID@
48 18

2
20 VGA_LVDS_A0# VGA_LVDS_A0 0B1 VCC DGPU_PWMSEL
20 VGA_LVDS_A0 47 27
VGA_LVDS_ACLK 1B1 VCC C898 C899 VGA_LVDS_SCL CONN_LVDS_SCL
20 VGA_LVDS_ACLK 43 38 4 3

1
VGA_LVDS_ACLK# 2B1 VCC 0.1U_0402_16V4Z 4.7U_0805_10V4Z D
20 VGA_LVDS_ACLK# 42 50
VGA_LVDS_A2 3B1 VCC 2 Q46B @
20 VGA_LVDS_A2 37 56 2 DGPU_PWMSEL# 16

2
VGA_LVDS_A2# 4B1 VCC 2N7002DW-T/R7_SOT363-6 Q43 G
20 VGA_LVDS_A2# 36
VGA_LVDS_A1# 5B1 CONN_LVDS_A0# 2N7002_SOT23 S
20 VGA_LVDS_A1# 32 2

3
VGA_LVDS_A1 6B1 A0 CONN_LVDS_A0 VGA_LVDS_SDA CONN_LVDS_SDA R260 0_0402_5%
20 VGA_LVDS_A1 31 3 1 6
VGA_LVDS_SCL 7B1 A1 CONN_LVDS_ACLK
19 VGA_LVDS_SCL 22 7 1 2
VGA_LVDS_SDA 8B1 A2 CONN_LVDS_ACLK# Q46A @ @
19 VGA_LVDS_SDA 23 8
9B1 A3 CONN_LVDS_A2 2N7002DW-T/R7_SOT363-6 R259 0_0402_5%
A4
11
12 CONN_LVDS_A2#
TO LVDS Connector 1 2 DGPU_PWMSEL#
A5 19 NV_INVTPWM +3VS
CONN_LVDS_A1# DGPU_EDID_SEL# @
FROM PCH LVDS 14

1
A6 CONN_LVDS_A1
15
LVDS_A0# A7 CONN_LVDS_SCL R207 0_0402_5%
46 19

OE#
P
15 LVDS_A0# 0B2 A8
15 LVDS_A0 LVDS_A0 45 20 CONN_LVDS_SDA 34 INVT_PWM 1 2 2 4
LVDS_ACLK 1B2 A9 HYBRID@ A Y
15 LVDS_ACLK 41
2B2

G
15 LVDS_ACLK# LVDS_ACLK# 40 17 DGPU_SELECT# U17
LVDS_A2 3B2 SEL 74AHC1G125GW_SOT353
15 LVDS_A2 35 L: B1 -> A (VGA)

3
5
LVDS_A2# 4B2 HYBRID@
15 LVDS_A2# 34 1 H: B2 -> A (PCH)
LVDS_A1# 5B2 GND SVT LOW COST
15 LVDS_A1# 30 6
LVDS_A1 6B2 GND PCH_EDID_CLK CONN_LVDS_SCL DGPU_PWMSEL 3V Vcc 1G125 BUFFER
15 LVDS_A1 29 9 4 3 +3VS
PCH_EDID_CLK 7B2 GND OE# A Y
15 PCH_EDID_CLK 25 13

1
PCH_EDID_DATA 8B2 GND Q47B @ L L L
15 PCH_EDID_DATA 26 16

2
9B2 GND 2N7002DW-T/R7_SOT363-6 L H H
21

OE#
P
DGPU_EDID_SEL# GND H X Z
54 24 15 PCH_PWM 2 4
SEL2 GND PCH_EDID_DATA CONN_LVDS_SDA A Y
28 1 6
GND

G
33 U6
GND Q47A @ 74AHC1G125GW_SOT353
52 39

3
NC GND 2N7002DW-T/R7_SOT363-6 HYBRID@
5 44
NC GND
51 49
B NC GND R161 0_0402_5% B
53
GND INVPWM
57 55 1 2
Thermal_GND GND UMA@
ST3DV520EQTR_QFN_56P_11X5
HYBRID@

+3VS SVT DGPU_SELECT#

+3VS
CMOS Camera
5

1
1

+CMOS_PW +5VALW

OE#
R33 @ PVT
+3VS P ENBKL
1 19 VGA_ENABLT 2 4
1K_0402_1% A Y ENBKL 34 +3VS
W=40mils

1
G

@ C260 U18

2
R372 0_0402_5% 0.1U_0402_16V4Z U16 @ 74AHC1G125GW_SOT353 R66 @ R270 CMOS@
2

3
5

DGPU_EDID_SEL 1 2 2 NC7SZ14P5X_NL_SC70-5 HYBRID@ R970 150_0603_1% 100K_0402_5%

DGPU_SELECT# 16,26
@ 100K_0402_1% 1
P

NC
1

D R371 0_0402_5% DGPU_EDID_SEL# 2 DGPU_EDID_SEL DGPU_BKL_SEL C609 @

4 +3VS

2
@ Q42 A Y 4.7U_0805_10V4Z
2 DGPU_EDID_SEL# 1 2 DGPU_EDIDSEL# 16,26

1
5

3
G

2N7002W-T/R7_SOT323-3 G D S

S 2CAM_EN- 1 2 CMOS_EN_RC# 2
G 2
OE#
P
3

Replace FET inverter Q42

15 PCH_ENBKL 2 4 Q38 @ G
A Y 2N7002_SOT23 S R54 CMOS@

1
G

U19 220K_0402_5% 1 Q74 CMOS@

D
74AHC1G125GW_SOT353 C326 CMOS@ SI2301BDS-T1-E3_SOT23-3

OUT
3

1
HYBRID@ +CMOS_PW
0.1U_0402_16V4Z
UMA SW BYPASS DGPU_SELECT#
34 CMOS_EN 2
IN
2

GND
PCH_ENBKL 0_0402_5% 2 UMA@ 1 R575 ENBKL +CMOS_PW_R 1 2
2

1
Q21 CMOS@
G

R440 1K_0402_1% DTC124EKAT146_SC59-3 PVT,chg AO3413 main R304 CMOS@ 1

3
PCH_EDID_CLK 0_0402_5% 2 UMA@ 1 R393 CONN_LVDS_SCL +3VS 1 2 1 3 R69 @ 0_0603_5%
PCH_EDID_DATA 0_0402_5% 2 UMA@ 1 R394 CONN_LVDS_SDA HYBRID@ 100K_0402_5% C337 CMOS@
D

A Q64 10U_0805_10V4Z A

2
DGPU_BKL_SEL 2N7002W-T/R7_SOT323-3 2
HYBRID@
LVDS_A0 0_0402_5% 2 UMA@ 1 R383 CONN_LVDS_A0
LVDS_A0# 0_0402_5% 2 UMA@ 1 R382 CONN_LVDS_A0#

LVDS_A1 0_0402_5% 2 UMA@ 1 R389 CONN_LVDS_A1

LVDS_A1# 0_0402_5% 2 UMA@ 1 R388 CONN_LVDS_A1#

LVDS_A2
LVDS_A2#
0_0402_5%
0_0402_5%
2 UMA@ 1 R386 CONN_LVDS_A2 Security Classification Compal Secret Data Compal Electronics, Inc.
2 UMA@ 1 R387 CONN_LVDS_A2#
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

LVDS_ACLK 0_0402_5% 2 UMA@ 1 R384 CONN_LVDS_ACLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
LVDS_ACLK# 0_0402_5% 2 UMA@ 1 R385 CONN_LVDS_ACLK# Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 27 of 50
5 4 3 2 1
 A B C D E

+3VS

Mini-Express Card for WLAN/WiMAX(Half) R68

+1.5VS
+3VALW +JPCIE3_3.3
2 1
0_0603_5% R352
Mini-Express Card(WLAN/WiMAX) JPCIE3_1.5 2
0_0603_5%
1 1 1
1 1
JPCIE3 C422 @ C425
15 PCIE_WAKE# PCIE_WAKE# 1 2 +JPCIE3_3.3 C421 C423 0.1U_0402_16V4Z 10U_0805_10V4Z
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2
3 4
3 4 2 2
5 6
14 WLAN_CLKREQ1# WLAN_CLKREQ1# 7
5 6
8 LPC_FRAME#_R Reserve for SW mini-pcie debug card.
7 8 LPC_AD3_R
9
11
9 10
10
12 LPC_AD2_R Series resistors closed to KBC side.
14 CLK_PCIE_WLAN1# 11 12
13 14 LPC_AD1_R
14 CLK_PCIE_WLAN1 13 14 D31
15 16 LPC_AD0_R LPC_FRAME#_R R284 1 @ 2 0_0402_5% LPC_FRAME#
15 16 LPC_FRAME# 13,34
WLAN_LED_R1# 1 2 WLAN_LED# WLAN_LED# 34,38 LPC_AD3_R R285 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 13,34
LPC_AD2_R R286 1 @ 2 0_0402_5% LPC_AD2
1 LPC_AD2 13,34 1
PCI_RST#_R 17 18 LPC_AD1_R R287 1 @ 2 0_0402_5% LPC_AD1
17 18 CH751H-40PT_SOD323-2 LPC_AD1 13,34
CLK_PCI_DB 19 20 R377 1 2 0_0402_5% LPC_AD0_R R288 1 @ 2 0_0402_5% LPC_AD0
19 20 WL_OFF# 34 LPC_AD0 13,34
21 22 @ PCI_RST#_R R290 1 @ 2 0_0402_5% PCI_RST#
21 22 BUF_PLT_RST# 5,16,29 PCI_RST# 16,34
23 24 R376 1 2 @ 0_0402_5% +3VALW CLK_PCI_DB CLK_PCI_DB 14
14 PCIE_PRX_DTX_N2 23 24
25 26 R375 1 2 0_0402_5% +3VS
14 PCIE_PRX_DTX_P2 25 26
27 28
27 28 R374 1
29 30 2 @ 0_0402_5% SMB_CLK_S3 10,11,12,14 D32
29 30 R373 1
14 PCIE_PTX_C_DRX_N2 31 32 2 @ 0_0402_5% SMB_DATA_S3 10,11,12,14
31 32 WIMAX_LED1# WLAN_LED#
14 PCIE_PTX_C_DRX_P2 33 34 1 2
33 34
35 36 USB20_N8 16
+JPCIE3_3.3 35 36
37 38 USB20_P8 16
37 38 CH751H-40PT_SOD323-2
39 40
39 40 WIMAX_LED1# @
41 42
41 42 WLAN_LED_R1#
43 44
100_0402_1% 43 44 MINIBT_LED1#
45 46
R274 45 46 SVT SVT
47 48
EC_TX_P80_DATA 1 47 48
34,35 EC_TX_P80_DATA 2 49 50
EC_RX_P80_CLK 1 49 50 R672
34,35 EC_RX_P80_CLK 2 51 52 D33
R273 51 52 WLAN_LED#
53 55 37 BT_LED# 1 2
100_0402_1% G1 G3 MINIBT_LED1# WLAN_LED#
54 56 1 2
G2 G4 0_0402_5%
PVT R336 BELLW_80052-1021 @
100K_0402_5% CH751H-40PT_SOD323-2
1 2 ME@ @
H=1.7mm, P/N : DC040006S00

+3VS
Mini-Express Card(WWAN 3G) R353 3G@
2 1
0_0603_5%
JPCIE2 D4 @
PCIE_WAKE# 1 +1.5VS CM1293-04SO_SOT23-6
1 +JPCIE2_3.3 @
3 2
3 2 UIM_DATA
5 4 R88 3G@ 1 4 2 1 +UIM_PWR
PCIECLKREQ3# 5 4 JPCIE2_1.5 CH1 CH4 R152
14 PCIECLKREQ3# 7 6 2 1
7 6 +UIM_PWR 0_0603_5% 10K_0402_5%
2 9 8 1 1 2
9 8 UIM_DATA +3VS
14 CLK_PCIE_CARD_PCH# 11 10
11 10 UIM_CLK C417 C419
14 CLK_PCIE_CARD_PCH 13 12 D34 2 5
13 12 UIM_RST 0.1U_0402_16V4Z 0.1U_0402_16V4Z Vn Vp
15 14
15 14 UIM_VPP 2 3G@ 2 3G@ WLAN_LED_R2# WLAN_LED#
16 1 2
16
3 6
CH751H-40PT_SOD323-2 CH2 CH3 +3VS
17
17 @ DAN217T146_SC59-3
19 18
19 18 R368 1 3G@ 0_0402_5% JSIM1
21
21 20
20 2
BUF_PLT_RST#
3G_OFF# 34
+UIM_PWR
40mil 3
14 PCIE_PRX_DTX_N4 23 22 4 1 1
23 22 R367 1 SVT UIM_VPP GND VCC UIM_RST
14 PCIE_PRX_DTX_P4 25 24 2 @ 0_0402_5% +3VALW 5 2 2
25 24 R369 1 VPP RST
27 26 2 @ 0_0402_5% +3VS D35
UIM_DATA 6 3 UIM_CLK
27 26 I/O CLK @ D5
29 28 7
29 28 R366 1 SMB_CLK_S3 WIMAX_WWAN_LED2# WLAN_LED# DET
31 30 2 @ 0_0402_5% 1 2

4.7U_0805_10V4Z
14 PCIE_PTX_C_DRX_N4 31 30
33 32 R365 1 2 @ 0_0402_5% SMB_DATA_S3 1 1
14 PCIE_PTX_C_DRX_P4

1
33 32

C188
35 34

10K_0402_5%
+JPCIE2_3.3 35 34 CH751H-40PT_SOD323-2

R151
37 36 USB20_N13 8 C176
37 36 USB20_N13 16 GND
39 38 USB20_P13 @ 9 0.1U_0402_16V4Z
39 38 USB20_P13 16 GND 2 2
41 40
41 40 WIMAX_WWAN_LED2#
43 42

2
43 42 WLAN_LED_R2# 3G@
45 44
45 44 3G@ 3G@
47 46
47 46 +UIM_PWR
49 48
49 48 +JPCIE2_3.3 TAITW_PMPAT6-06GLBS7N14N0
51 50
51 50 ME@
52
52
53
GND1
54 1
GND2
BELLW_80053-1021 C418 3G@
ME@ 10U_0805_10V4Z
2
H=4.0mm, P/N : DC020910200

3 +3VS 3

Mini-Express Card( Only for SSD) JPCIE1

R128 SSD@ +1.5VS
1
1 +JPCIE1_3.3 2
3 2 1
3 2 0_0603_5% R177 SSD@
5 4
5 4 JPCIE1_1.5
7 6 2 1
7 6 0_0603_5%
9 8 1 1
9 8
11 10
11 10 C386 C431
13 12
13 12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
15 14
15 14 2 SSD@ 2 SSD@
16
16

17
19
21
17
19 18
18
20
SSD Pin Table
SATA_DTX_C_IRX_P1 C426 1 1B+ 21 20
2 0.01U_0402_16V7K 23 22
13 SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_N1 C424 1 23 22
2 0.01U_0402_16V7K 1B# 25 24 R380 1 SSD@ 2 0_0402_5% +3VS Pin Number SATA Assignment
13 SATA_DTX_C_IRX_N1 SSD@ 25 24
27 26
SSD@ 27 26
29
29 28
28 11
13 SATA_ITX_C_DRX_N1 0.01U_0402_16V7K 2 1 C427 SATA_ITX_DRX_N1 31 30 DA/DSS T27
0.01U_0402_16V7K SATA_ITX_DRX_P1 31 30 +JPCIE1_3.3
13 SATA_ITX_C_DRX_P1 2 1 C428 33 32 13
SSD@ 33 32
35 34
SSD@ +JPCIE1_3.3 35 34
37
37 36
36 17
39 38
T28 39 38
41
41 40
40 1 1 1 19
R506 SSD@ 43 42 C388 C387 C372
0_0402_5% DA/DSS_NEW 43 42
34 SSD_DET#
45
45 44
44 23 +B (port 1)
2 1 SSD_DET#_NEW 47 46 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
EC_TX_P80_DATA 1 47 46 2 2 2
2 SSD_P80_DAT 49 48 25 -B (port 1)
EC_RX_P80_CLK 1 SSD@ 2 SSD_P80_CLK 49 48
51 50
SSD@ R339 0_0402_5% 51 50 SSD@ SSD@ SSD@
52
52 30 45 DA/DSS DA/DSS (NEW)
R343 0_0402_5% 53
PVT GND
54
GND 31 -A (port 1)
EVT 0324 SSD Pin Define 32 47 SSD_DET# SSD_DET# (NEW)
P-TWO_A54402-A0G16-N
please pull high by EC internal
4 ME@ 33 +A (port 1) 4

R578 1 @ 2 SSD_DET#
+3VS
100K_0402_5% STD H=4.0mm, P/N : SP01000KQ00

Security Classification
2010/01/13
Compal Secret Data
2011/01/13 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Nwe Card/SIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 28 of 50
A B C D E
 A B C D

+3V_LAN +5VALW

+3VALW
W=60mils

1
R973
@ R972 100K_0402_5%
150_0603_1%
1
C1210 @

2
4.7U_0805_10V4Z

3
D R974
S

2 LAN_EN- 1 2 WOL_EN_RC#
G
2 2
1 1

Q96 @ G
2N7002_SOT23 S 220K_0402_5% SI2301BDS-T1-E3_SOT23-3

3
1

1
C1211 Q97 D +3V_LAN

1
OUT
0.1U_0402_16V4Z 3VLANOUT W=60mils
2
34 WOL_EN 2 IN
1 R726 2 0_0805_5%

GND
1
Q5 PVT,chg AO3413 main 1 1 1 1 1
DTC124EKAT146_SC59-3 C748 C749 C750 C751

3
R975 @ C1218
100K_0402_5% 10U_0805_10V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
2 2
10U_0805_10V4Z 2 2 2

2
1000P_0402_50V7K

RF 10/22
LAN Power Circuit & Soft start Place Close to Pin 2
+AVDD_CEN close to L48
L48 S INDUC_ 4.7UH +-20% SIA4012-4R7M
1 2 +1.8_VDD/LX
1 1
C676 C594 close to pin1
0.1U_0402_16V4Z 10U_0805_10V4Z
U30 +3V_LAN
2 2
D30 CH751H-40PT_SOD323-2 PVT

1
1 30 SVT 10/100_LINK_LED 1 2
VDDHO/VDD18O/VDD18O TW SI_DATA R654
TW SI_CLK 29 LAN_SK# 30
2
48 10/100_LINK_LED 4.7K_0402_5% 1000_LINK_LED 1 2 2

LED_LINK10_100n
+3V_LAN 2 VDD3V LED_ACTn 47 ACTIVITY# 30 @
D29 CH751H-40PT_SOD323-2

2
close to pin6 27 1 2 CLKREQ_LAN# 14
+AVDD_CEN SPI_CS/LED_DUPLEXn/LED_DUPLEXn R601 0_0402_5%
2 1 6 VDD3V/VDDHO/VDDHO
C667 0.1U_0402_16V4Z
26 1000_LINK_LED
CTR12 SPI_DI/NC/LED_Link1000n C663
1 2 5 VDDLO/CTR12/CTR12
C656 0.1U_0402_16V4Z close to pin5 REFCLKN 0.1U_0402_16V4Z
REFCLKN 40
41 REFCLKP
1
1
2
2 CLK_PCIE_LAN# 14 Place Close to LAN chip
REFCLKP C664 0.1U_0402_16V4Z CLK_PCIE_LAN 14
5,16,28 BUF_PLT_RST# 3 PERSTn
14 MDI0- close to pin40,41 R150 49.9_0402_1%
TXN0/TXN0/TRXN0 MDI0- 30
13 MDI0+ MDI0+ 1 2
TXP0/TXP0/TRXP0 MDI0+ 30
1 R656 2 7 18 MDI1- R94 49.9_0402_1% 1 2 C245 0.1U_0402_16V4Z
+3V_LAN VAUX_AVL/VBG1P18/VBG1P18 RXN1/RXN1/TRXN1 MDI1- 30
17 MDI1+ MDI0- 1 2
RXP1/RXP1/TRXP1 MDI2- MDI1+ 30
4.7K_0402_5% 4 21 R84 49.9_0402_1%
34 LAN_WAKE# W AKEn NC/NC/TRXN2 MDI2- 30

㪘㫋㪿㪼㫉㫆㫊
14 PCIE_PRX_DTX_N3 C246 1 2 0.1U_0402_16V7K PCIE_IRX_C_PTX_N3 37 20 MDI2+ MDI1+ 1 2
TX_N NC/NC/TRXP2 MDI2+ 30
C247 1 2 0.1U_0402_16V7K PCIE_IRX_C_PTX_P3 38 24 MDI3- R36 49.9_0402_1% 1 2 C243 0.1U_0402_16V4Z
14 PCIE_PRX_DTX_P3 TX_P NC/NC/TRXN3 MDI3- 30
PCIE_PTX_C_DRX_N3 44 23 MDI3+ MDI1- 1 2
14 PCIE_PTX_C_DRX_N3 RX_N NC/NC/TRXP3 MDI3+ 30
PCIE_PTX_C_DRX_P3 43 R171 49.9_0402_1%
14 PCIE_PTX_C_DRX_P3 RX_P MDI2+
XTALO
AR8121/8131 +AVDDVCO2
1
R85
2
49.9_0402_1%
9 XTLO AVDDL0 42 1 2 C658 0.1U_0402_16V4Z
LAN_XTALI 10 39 +1.2_AVDDL MDI2- 1 2
XTLI AVDDL1 R170 49.9_0402_1%
AVDDL2 36
22 MDI3+ 1 2
DVDDL/AVDDL/AVDDL R172 49.9_0402_1%
34 TESTMODE AVDDL3 16 1 2 C238 0.1U_0402_16V4Z
35 11 +AVDDVCO1 MDI3- 1 2
NC AVDDL4 +1.2_AVDDL
AVDDL5 8

31 46 +1.2_DVDDL close to pin19

SMCLK DVDDL0
3 33 SMDATA AVDDL/DVDDL/DVDDL 45 3

DVDDL1 32
SPI_CLK/DVDDL/DVDDL 28
C654
49 0.1U_0402_16V4Z
GND CTR12 +1.2_AVDDL
SPI_DO/AVDDH/AVDDH 25
AVDDH0 19 1 1 1
R67 1 2 2.37K_0402_1% 12 15 C674 C650
RBIAS AVDDH1 1U_0402_6.3V4Z 0.1U_0402_16V4Z close to pin11
close to pin15 2 2 2
AR8131L-AL1E_QFN48_6X6 GIGA@
SA000038N00 S IC AR8131L-AL1E QFN 48P E-LAN CTRL PVT
close to pin25 R602 0_0603_5%
1 2 1 2 +AVDDVCO1
SA000031Z00 @ 1 1
R390 C653
0_0603_5% C655 1U_0402_6.3V4Z
close to pin36 1000P_0402_50V7K
close to pin16 2 2

C648 C657
+1.2_AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z

LAN_XTALI C248 C244 1 1 1 1 1 1

+1.2_DVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z GIGA@ 1 2 +AVDDVCO2
XTALO 1 1 1 1 C659 C647 1
1U_0402_6.3V4Z 0.1U_0402_16V4Z L37 0_0603_5%
2

C251 C652 2 2 2 2 2 2 C660

R391 1U_0402_6.3V4Z 0.1U_0402_16V4Z C661 C662 0.1U_0402_16V4Z
2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
NBLG0_DVT 0_0402_5%
close to pin8
4

Y3
close to pin28 If overclocking, R602 , L37 stuffed and R390 removed. 4
1

close to pin46
1 2 LAN_XTALO close to pin22 If not overclocking, R390 , L37 suffed and R602 removed.
AR8131:L37=0ohm (more power saving mode)
1 25MHZ_20PF_7A25000012 1
C665 C649
27P_0402_50V8J 27P_0402_50V8J
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AR8131/ AR8132
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 29 of 50
A B C D
 5 4 3 2 1

+AVDD_CEN
C666
1 2 1 2

R430
1U_0402_6.3V4Z 0_0603_5%

Close to T20
D D

GIGA@ T22
C669 2 1 0.01U_0402_16V7K 1 24 MCT3 R97 2 GIGA@ 1 75_0402_5%
TCT1 MCT1
MDI3+ 2 1:1 23 MDO3+
29 MDI3+ TD1+ MX1+

MDI3- 3 22 MDO3-
29 MDI3- TD1- MX1-
GIGA@
C671 2 1 0.01U_0402_16V7K 4 21 MCT2 R126 2 GIGA@ 1 75_0402_5%
TCT2 MCT2
MDI2+ 5 1:1 20 MDO2+
29 MDI2+ TD2+ MX2+

MDI2- 6 19 MDO2-
29 MDI2- TD2- MX2-
C672 2 1 0.01U_0402_16V7K 7 18 MCT1 R95 2 1 75_0402_5%
TCT3 MCT3
MDI1+ 8 1:1 17 MDO1+
29 MDI1+ TD3+ MX3+

C MDI1- 9 16 MDO1- C
29 MDI1- TD3- MX3-
C668 2 1 0.01U_0402_16V7K 10 15 MCT0 R96 2 1 75_0402_5%
TCT4 MCT4
MDI0+ 1:1 MDO0+
40mil
29 MDI0+ 11 TD4+ MX4+ 14
1
Place close to TCT pin C670

1000P_1206_2KV7K
MDI0- MDO0- 2
29 MDI0- 12 TD4- MX4- 13

350uH_NS892406
GIGA@

T22
RJ45 Conn.
SANTA_130452-D
29 ACTIVITY# ACTIVITY# R179 2 1 300_0402_5% 12
NS892404 Yellow LED+
100@ 1 11 Yellow LED-

1
C249 MDO3- 8 13
R125 @ 68P_0402_50V8K PR4- G1
2 MDO3+
5.1K_0402_5% 7 PR4+ G2 14
B B
MDO1- 6

2
PR2-
MDO2- 5 PR3-
MDO2+ 4 PR3+
MDO1+ 3 PR2+
close to LED
MDO0- 2 PR1-
MDO0+ 1 PR1+
+3V_LAN 10 Green LED+
29 LAN_SK# LAN_SK# R600 2 1 300_0402_5% 9 Green LED-
1 JRJ45
ME@
C613
68P_0402_50V8K
2
@ DC020910220

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 30 of 50
5 4 3 2 1
 5 4 3 2 1

SMSC thermal sensor +3VS +3VS

REMOTE1+
Close to DDR
placed near by VRAM 1

1
@ C
D R460 R461 C508 2 Q39 D
10K_0402_5% 10K_0402_5% 100P_0402_50V8J B MMST3904-7-F_SOT323-3
+3VS @ @ 2 E

3
U20 REMOTE1-

2
1 VDD SMCLK 10 EC_SMB_CK2 14,34

2 REMOTE1+ 2 9
DP1 SMDATA EC_SMB_DA2 14,34
C443 REMOTE1- 3 8 REMOTE2+
Under WWAN
0.1U_0402_16V4Z DN1 ALERT#
1

1
1 REMOTE2+ @ C
4 DP2 THERM# 7
C324 2 Q22
REMOTE2- 5 6 100P_0402_50V8J B MMST3904-7-F_SOT323-3
DN2 GND 2 E
Close U20

3
REMOTE2-
REMOTE1+
1 EMC1403-2-AIZL-TR_MSOP10

C449
2200P_0402_50V7K Address 1001_101xb REMOTE1,2+/-:
2 REMOTE1-
P/N SA000029210 Trace width/space:10/10 mil
Trace length:<8"
REMOTE2+
1
C C
C651
2200P_0402_50V7K
2 REMOTE2-

FAN1 Conn
+5VS

JFAN1
1 1
EC_TACH 2
34 EC_TACH 2
34 EC_FAN_PW M EC_FAN_PW M 3 3
4 4
2 2 5 G1
6 G2
C714 C593
10U_0805_10V4Z 10U_0805_10V4Z ACES_85204-04001
1 1
ME@

B B
SP02000CW00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
EMC1403_Thermal sensor/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-5941P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 31 of 50
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

JHDD1
1 GND
13 SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 2
SATA_ITX_DRX_N0 RX+
13 SATA_ITX_DRX_N0 3 RX-
4
SATA_DTX_C_IRX_N0 C434 1 SATA_DTX_IRX_N0 GND
2 0.01U_0402_16V7K 5
TX-
13 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C433 1 SATA_DTX_IRX_P0
2 0.01U_0402_16V7K 6 TX+
1 13 SATA_DTX_C_IRX_P0 1
7
GND

1 R574 2 +3VS_HDD 8
+3VS 3.3V
9 3.3V
0_0805_5% 10 3.3V
11
GND
12 GND
13
GND
+5VS_HDD 14 23
5V GND
15
5V
16 5V GND 24
+5VS 17 GND
18 Reserved
19 GND
+3VS 20
12V
21
+5VS_HDD 12V
1 R576 2 0_0805_5% 22 12V
1 1 1 1 1 1
@ SUYIN_127043FB022G272ZR
C125 C126 C124 C123 C122 C121
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V6K 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 ME@

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 32 of 50
A B C D E F G H
 5 4 3 2 1

RA2
+PVDD1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VS
1 1 0_0603_5% 1 1
CA57 CA44
CA56 CA43

2
RA1 JA1 2 2 2 2

2
+3VS 2 1 0.1U_0402_16V4Z JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
0_0603_5%

1
1 1 @ place close to chip
CA2 CA1

1
D 10U_0805_10V4Z +3VS_DVDD RA11 D
2 2 +PVDD2 0.1U_0402_16V4Z
2 1 +5VS
1 1 0_0603_5% 1 1
0.1U_0402_16V4Z CA61 @ CA59
@ CA60 @ @ CA58
1 1 0.1U_0402_16V4Z
2 2 2 2
CA8 CA7 +AVDD 10U_0805_10V4Z 10U_0805_10V4Z
10U_0805_10V4Z RA3
2 2 10U_0805_10V4Z 0.1U_0402_16V4Z 2
+MIC1_VREFO_L 1 +5VS
0_0603_5%
ESD 1102 +MIC1_VREFO_R

39

46

25

38
1 1 1 1

9
place close to chip U43 CA3 CA4 CA5 CA6
near pin

DVDD

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
1103 add place close to chip

2
+3VS 2 2 2 2
RA12 RA8 10U_0805_10V4Z 0.1U_0402_16V4Z
4.7K_0402_5% 4.7K_0402_5%
2

23 40 SPK_L2+
RA7 LINE1_L SPK_OUT_L+ SPK_L1-
24 41

1
LINE1_R SPK_OUT_L-
4.7K_0402_5%
@ SPK_R2+
Internal SPEAKER
14 45
LINE2_L SPK_OUT_R+ SPK_R1-
15 44
1

4.7U_0805_10V4Z CA21 LINE2_R SPK_OUT_R-

2 1 MIC1_L 21 32 HP_OUT_L RA4 75_0402_1%
37 EXT_MIC_L MIC1_L HP_OUT_L HP_OUTL 37
HDA_RST_CODEC# External MIC 37 2 1 MIC1_R 22 33 HP_OUT_R RA5 75_0402_1% Headphone
13 HDA_RST_CODEC# EXT_MIC_R MIC1_R HP_OUT_R HP_OUTR 37

2 4.7U_0805_10V4Z CA22 16 MIC2_L

17
CA13 MIC2_R
10 HDA_SYNC_CODEC 13
SYNC
100P_0402_50V8J
1 @ 2 6
27 INT_MIC_DATA GPIO0/DMIC_DATA BCLK HDA_BITCLK_CODEC 13
C
Internal MIC C
27 INT_MIC_CLK 2 1 3 1
0_0402_5% RA24 GPIO1/DMIC_CLK
5 HDA_SDOUT_CODEC 13
INT_MIC_CLK SVT SDATA_OUT C1219
PVT EC_MUTE# 1 2 259PD# 4 8 AZ_SDIN0_HD_R 2 1 22PF_0402_50V9
34 EC_MUTE# PD# SDATA_IN HDA_SDIN1 13 2
2 CH751H-40PT_SOD323-2 D7 RA6 33_0402_5% @
EMI PVT,realtek AP note.
@
CA18 HDA_RST_CODEC# 11 47 RA22 2 1 0_0402_5% Near PIN
RESET# EAPD EAPD 34
100P_0402_50V8J
1
PC_BEEP SPDIFO
48 RF 1022
1 2 12
CA12 100P_0402_50V8J PCBEEP
20
MONO_OUT
SENSE_A
place close to chip 13
SENSE A
29
SVT,add PVT MIC2_VREFO
18
SENSE_A SENSE B CA23 10U_0805_10V4Z
37 MIC_JD 2 1 30 +MIC1_VREFO_R
RA10 20K_0402_1% RA23 MIC1_VREFO_R LDO_CAP
1 2 36 28 1 2
EC_MUTE# 259PD# CA15 CBP LDO_CAP
2 1
37 PLUG_IN 0_0402_5% 2.2U_0603_6.3V6K 35 27 AC_VREF2.5V
RA21 39.2K_0402_1% CBN VREF
+MIC1_VREFO_L 31 19 AC_JDREF 2 RA9 1 20K_0402_1%
MIC1_VREFO_L JDREF
1 1
43 34 A_RVO 1 2
PVSS2 CPVEE CA14 2.2U_0603_6.3V6K CA17 CA16
42
PVSS1 10U_0805_10V4Z
Sense Pin Impedance Codec Signals Function 49
7
DVSS2 AVSS1
26
37 2 2
DVSS1 AVSS2 0.1U_0402_16V4Z
39.2K PORT-I (PIN 32, 33) Headphone out ALC259-GR_QFN48_7X7
place close to chip
20K PORT-B (PIN 21, 22) Ext. MIC CA47 1 2 0.1U_0603_50V7K
DGND SVT change to SA00003QR10 AGND
SENSE A
B
10K PORT-C (PIN 23, 24) B

5.1K (PIN 48) CA50 1 2 0.1U_0603_50V7K

1 2
RA18 0_0603_5%

PC Beep +5VS

+3VS
wide 20MIL
2

R326
20K_0402_5% JSPK1
1

SPK_R1- L19 1 2 FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 1

D16 10K_0402_5% SPK_R2+ L20 FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 1
1 2 2
1

SPK_L1- L22 FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 2

RB751V_SOD323 R309 1 2 3 5
SPK_L2+ L23 FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 3 G1
@ 1 2 4 6
4 G2

1000PF_0402_25V7

1000PF_0402_25V7

1000PF_0402_25V7

1000PF_0402_25V7
2

C374 1U_0603_10V6K EMI 1030 ACES_88266-04001

PC_BEEP1 2 1 PC_BEEP ME@
1 1 1 1

C632

C633

C634

C635
EC Beep SP02000K200
1

C351 R310 C
2

Q30 2 2 2 2
34 BEEP# 2 1 1 2 2
1 B 2SC2411KT146_SOT23-3 R335 @ @ @ @
560_0402_5% E 2.4K_0402_1%
3

A C345 1U_0603_10V6K A
@ 0.1U_0402_16V4Z
1

2
C352 EMI 1030 SE074102K80
R311
13 PCH_SPKR 2 1 1 2
1

1U_0603_10V6K 560_0402_5%
ICH Beep D15 @
RB751V_SOD323
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
ALC259 Codec
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 33 of 50
5 4 3 2 1
 LED1 +5VS
+3VALW R357 560_0402_5%
+EC_AVCC TP_LOCK# 1 2 1 2 TP_CLK R236 1 2 4.7K_0402_5%
+5VS
1 1 1 1 1 1

0.1U_0402_16V4Z
C290

0.1U_0402_16V4Z
C319

0.1U_0402_16V4Z
C339

0.1U_0402_16V4Z
C329

1000P_0402_50V7K
C341

1000P_0402_50V7K
C327
L14 1 2 TP_DATA R235 1 2 4.7K_0402_5%
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1 LTW-C193TS5 0603 WHITE SC500005I00
EC_TACH 1 2
C293 2 2 2 2 2 2
0.1U_0402_16V4Z C294 C297 100P_0402_50V8J

111
125
1000P_0402_50V7K Touch Pad lock LED 10/20 add BATT_TEMP

22
33
96

67
1 2

9
1 2 1 ECAGND 2 U13 C298 100P_0402_50V8J
L13 FBM-11-160808-601-T_0603 ACIN 1 2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
C328 100P_0402_50V8J

GATEA20 1 21 GEN_EN
16 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F GEN_EN 38
KB_RST# 2 23 BEEP#
16 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 33
SERIRQ 3 26 EC_FAN_PWM FAN control by EC 09.09.08 +3VALW
13 SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF EC_FAN_PWM 31
13,28 LPC_FRAME# 4 27 ACOFF 40,42
LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13
13,28 LPC_AD3 5
LPC_AD2 LAD3 FRD#SPI_SI
13,28 LPC_AD2 7 LAD2 PWM Output 2 1
LPC_AD1 8 63 BATT_TEMP R262 @
13,28 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 41
LPC_AD0 100K_0402_1%
LAD0 LPC & MISC
13,28 LPC_AD0 10 64 SSD_DET# 28
BATT_OVP/AD1/GPIO39 ADP_I FSEL#SPICS#
2 1 2 1 ADP_I/AD2/GPIO3A 65 ADP_I 42 2 1
@ C340 22P_0402_50V8J @ R289 10_0402_5% 12 AD Input 66 R271 @
16 CLK_PCI_LPC PCI_RST# PCICLK AD3/GPIO3B VOUTX 38
13 75 100K_0402_1%
16,28 PCI_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 KILL_SW# VOUTY 38 EC_SMB_CK1
+3VALW 1 2 37 76 KILL_SW# 37
R266 47K_0402_5% EC_SCI# ECRST# SELIO2#/AD5/GPIO43 R240
16 EC_SCI# 20 SCI#/GPIO0E
2 38 2.2K_0402_5%
T23 PAD CLKRUN#/GPIO1D DCR_EN EC_SMB_DA1
DAC_BRIG/DA0/GPIO3C 68 DCR_EN 27
C323 70 R239
15 CLKRUN# EN_DFAN1/DA1/GPIO3D IREF PSI_ON# 8
0.1U_0402_16V4Z DA Output 71 2.2K_0402_5%
1 IREF/DA2/GPIO3E IREF 42
1 2 CLKRUN# KSI0 55 72 CHGVADJ
CHGVADJ 42
EC_USB_ON# 1 2
R671 SVT KSI1 KSI0/GPIO30 DA3/GPIO3F R237
56 KSI1/GPIO31
10K_0402_5% KSI2 57 10K_0402_5%
KSI3 KSI2/GPIO32 EC_MUTE#
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# 33
KSI4 59 84 EC_USB_ON# LID_SW# 2 1
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B NOVO# R325
60 85 NOVO# 38
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C BT_EN
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 BT_EN 37
100K_0402_1%
KSO[0..15] KSI7 62 87 TP_CLK
35 KSO[0..15] KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 35 EC_MUTE#
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 35 1 2
KSI[0..7] KSO1 40 R238 @
35 KSI[0..7] KSO2 KSO1/GPIO21 10K_0402_5%
41
KSO3 KSO2/GPIO22 926C-STRAP T21 PAD
42 97
KSO4 KSO3/GPIO23 SDICS#/GPXOA00 WOL_EN
43 KSO4/GPIO24 SDICLK/GPXOA01 98 WOL_EN 29
KSO5 ME_FLASH
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
ME_FLASH 13
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 38
+3VALW KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27
47
KSO9 KSO8/GPIO28 FRD#SPI_SI PVT, for EC ROM fail +3VS
48 KSO9/GPIO29 SPIDI/RD# 119 FRD#SPI_SI 36
R265 1 2 47K_0402_5% KSO1 KSO10 49 KSO10/GPIO2A SPIDO/WR# 120 FWR#SPI_SO
FWR#SPI_SO 36
R978 0_0402_5%
KSO11 50 SPI Flash ROM 126 SPI_CLK 1 2 1 2 R291 ESB_CLK
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK_R 36
R263 1 2 47K_0402_5% KSO2 KSO12 51 KSO12/GPIO2C SPICS# 128 FSEL#SPICS#
FSEL#SPICS# 36
4.7K_0402_5%
KSO13 52 1
KSO14 KSO13/GPIO2D ESB_DAT
53 1 2 R294
ENE UPDATE 08/10/21 KSO15 54
KSO14/GPIO2E
KSO15/GPIO2F CIR_RX/GPIO40 73 BATT_SEL_EC
BATT_SEL_EC 42
C1220
22P_0402_50V8J
4.7K_0402_5%
1 2 EC_RF_LED# 81 74 CAP_INT
28,38 WLAN_LED# KSO16/GPIO48 CIR_RLC_TX/GPIO41 CAP_INT 38 2
G_SELFTEST 82 89 FSTCHG @ 1 2 R241 CAP_INT
SVT 38 G_SELFTEST KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHG_LED# FSTCHG 42
R685 0_0402_5% 90 10K_0402_5%
BATT_CHGI_LED#/GPIO52 TP_LOCK# BATT_CHG_LED# 38
CAPS_LED#/GPIO53 91
EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED# RF 1103 add ESB Bus for ENE cap. sensor only,
41 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_LOW_LED# 38
EC_SMB_DA1 78 93 PWR_LED#
41 EC_SMB_DA1
EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON
PWR_LED# 38 not compatible with SMB bus
14,31 EC_SMB_CK2 79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95 SYSON 39,44
EC_SMB_DA2 80 121 VR_ON
14,31 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN VR_ON 48
+3VS 127
AC_IN/GPIO59 ACIN 40
PVT R344 +5VALW
PM_SLP_S3# 6 100 EC_RSMRST# 10K_0402_5%
15 PM_SLP_S3# PM_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT# EC_RSMRST# 15
15 PM_SLP_S5# 14 101 EC_LID_OUT# 14 1 2
R226 R227 EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON
16 EC_SMI# 15 102 EC_ON 38
PCH_TEMP_ALERT# EC_SMI#/GPIO08 EC_ON/GPXO05 CMOS_EN Q63
2.2K_0402_5% 2.2K_0402_5% 16 PCH_TEMP_ALERT# 16 103 CMOS_EN 27
@ @ ESB_CLK LID_SW#/GPIO0A EC_SWI#/GPXO06 ICH_POK_EC ICH_POK 2N7002W-T/R7_SOT323-3
38 ESB_CLK 17 104 1 2 ICH_POK 15
ESB_DAT SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# R258 0_0402_5%
38 ESB_DAT 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 27
EC_SMB_CK2 SUS_PWR_DN_ACK GPIO WL_OFF# EC_USB_ON#

S
15 SUS_PWR_DN_ACK 19 106 WL_OFF# 28 1 2 37 USB_ON# 1 3
EC_SMB_DA2 INVT_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 AC_PRESENT R251 100K_0402_1%
27 INVT_PWM 25 EC_THERM#/GPIO11 GPXO10 107 AC_PRESENT 15
1 1 28 108 CAP_RST# @
31 EC_TACH FAN_SPEED1/FANFB1/GPIO14 GPXO11 CAP_RST# 38
@ @ 3G_OFF# 29 +3VALW

G
2
28 3G_OFF# FANFB2/GPIO15
C291 C292 EC_TX_P80_DATA 30
28,35 EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16 PM_SLP_S4#
100P_0402_50V8J 100P_0402_50V8J 31 110 PM_SLP_S4# 15
2 2 28,35 EC_RX_P80_CLK ON/OFF# EC_RX/GPIO17 PM_SLP_S4#/GPXID1 ENBKL
38 ON/OFF# 32 112 ENBKL 27
SUSP_LED# ON_OFF/GPIO18 ENBKL/GPXID2 EAPD
38 SUSP_LED# 34 114 EAPD 33
LCD_COLOR_EN PWR_LED#/GPIO19 GPXID3 EC_PROCHOT
27 LCD_COLOR_EN 36
NUMLED#/GPIO1A GPI GPXID4
115
+3V_LAN
116 SUSP#
GPXID5 SUSP# 39,42,46
+3VS 117 PBTN_OUT#
GPXID6 EC_PME# PBTN_OUT# 15
118
GPXID7

2
PVT, Fan FB pull-up PVT, EC AP note @ XCLKI 122
XCLK1
1

1 2 XCLKO 123 124 SUSP# R292

15 SUSCLK XCLK0 V18R
R345 R327 0_0402_5% 1 1 10K_0402_5%
AGND

10K_0402_5% C320 @ @
GND
GND
GND
GND
GND

C318

1
1 2 4.7U_0603_6.3V6K 1000P_0402_50V7K
2

C322 15P_0402_50V8J KB926QFA1_LQFP128 2 2 place it nearby Lan

11
24
35
94
113

69

EC_TACH XCLKO
1 2 EC_PME#
29 LAN_WAKE#
1

ECAGND

EPSON Q13MC1461005000 R293 0_0402_5%

3

6.9x1.4x1.3mm R264
PVT X2 10M_0402_5%
32.768KHZ_12.5P_MC-146
2

XCLKI
ENE926E0 SA00001J5A0
1 2 H_PROCHOT#
H_PROCHOT# 5,48
C321 15P_0402_50V8J
PIN91 change to TP_LOCK#

1
D
PIN36 change to LCD_COLOR_EN
EC_PROCHOT 2
G Q17
S 2N7002_SOT23
11/09 change EC pin

3
R459 @ PVT, pull cpu_core nearby
1 2 EC_SMB_CK2 10K_0402_5%
38 ALS_CLK
R3291 20_0402_5% EC_SMB_DA2 VR_ON 1 2
38 ALS_DATA VGATE 15,48
R330 0_0402_5%

10/17 add Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 34 of 50
 5 4 3 2 1

KB Matrix 10/30
JKB1
INT_KBD Conn. KSI1
KSI7
1 1 EC DEBUG PORT
2 2
KSI[0..7] KSI6 3
KSI[0..7] 34 3
KSO9 4
KSO[0..15] KSI4 4
D KSO[0..15] 34 5 5 D
KSI5 6
KSO0 6 JP11
7 7
KSI2 8 +3VALW 1
KSO2 C203 1 8 1
2 @ 100P_0402_50V8J KSO1 C205 1 2 @ 100P_0402_50V8J KSI3 9 9 28,34 EC_TX_P80_DATA
EC_TX_P80_DATA 2 2
KSO5 10 EC_RX_P80_CLK 3
10 28,34 EC_RX_P80_CLK 3
KSO15 C153 1 2 @ 100P_0402_50V8J KSO7 C186 1 2 @ 100P_0402_50V8J KSO1 11 4
KSI0 11 4
12 12
KSO6 C175 1 2 @ 100P_0402_50V8J KSI2 C226 1 2 @ 100P_0402_50V8J KSO2 13 ACES_85205-0400
KSO4 13
14 14 ME@
KSO8 C185 1 2 @ 100P_0402_50V8J KSO5 C206 1 2 @ 100P_0402_50V8J KSO7 15
KSO8 15
16 16
KSO13 C172 1 2 @ 100P_0402_50V8J KSI3 C225 1 2 @ 100P_0402_50V8J KSO6 17
KSO3 17
18 18
KSO12 C173 1 2 @ 100P_0402_50V8J KSO14 C156 1 2 @ 100P_0402_50V8J KSO12 19
KSO13 19
20 20
KSO11 C155 1 2 @ 100P_0402_50V8J KSI7 C236 1 2 @ 100P_0402_50V8J KSO14 21
KSO11 21
22 22
KSO10 C154 1 2 @ 100P_0402_50V8J KSI6 C235 1 2 @ 100P_0402_50V8J KSO10 23
KSO15 23
24 24
KSO3 C174 1 2 @ 100P_0402_50V8J KSI5 C228 1 2 @ 100P_0402_50V8J

KSO4 C187 1 2 @ 100P_0402_50V8J KSI4 C233 1 2 @ 100P_0402_50V8J 26

GND2
GND1 25
KSI0 C204 1 2 @ 100P_0402_50V8J KSO9 C234 1 2 @ 100P_0402_50V8J

KSO0 C227 1 2 @ 100P_0402_50V8J KSI1 C241 1 2 @ 100P_0402_50V8J E-T_6905-E24N-01R

ME@

C C

To TP/B Conn.
+5VS

C150
ME@
0.1U_0402_16V4Z
ACES_85201-04051
4 4 GND 6
TP_CLK 3 3 GND 5
34 TP_CLK
TP_DATA 2 2
34 TP_DATA
1 1 1 1
@ @
C151 C152 JTP1
100P_0402_50V8J 100P_0402_50V8J
2 2
SP01000KC00
3

B D22 B

PACDN042Y3R_SOT23-3
@
1

SCA00000G00

ESD 1104 CHANGE

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 35 of 50
5 4 3 2 1
 FOR EC 256KB SPI ROM
(150mil PACKAGE)
+3VALW 20mils

1
1
C265 R217
0.1U_0402_16V4Z 10K_0402_5%
2

2
U9
FSEL#SPICS# 1 8
34 FSEL#SPICS# CS# VCC
Changed to BEAD for EMI.
FRD#SPI_SI R218 1 2 15_0402_5% SPI_SI_R 2 7 HOLD#
34 FRD#SPI_SI SO HOLD# Close to EC after C1220
R215 FBMA-10-100505-101T 0402 SPI_CLK_L
3 6 SPI_CLK_L 1 2
WP# SCLK SPI_CLK_R 34

1
R216
4 5 SPI_SO_EC 1 2 15_0402_5% FWR#SPI_SO 0_0402_5%
GND SI FWR#SPI_SO 34
R201 @
Colse to EC

2
W25X20BVSNIG_SO8 1 1
C266 C264
SA00003GM10 10P_0402_50V8J 12P_0402_50V8J
2 @ 2

EMI 3G

FD1 FD4 FD2 FD3

1 1 1 1

A:H_2P8

H1 H2 H3 H4 H5 H6 H7 H8 H10 H11 H12

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

1
G:H_3P2 X6
H13 H14 H15 H16 H17
HOLEA HOLEA HOLEA HOLEA HOLEA

1
1030 change to H_3P8
for thermal

H_4P5X3P0N I:H_3P0 X1
H18
HOLEA
H19 H20
HOLEA HOLEA

1
1

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC SPI ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 36 of 50
 A B C D E

SVT EMI request

@
TO USB BOARD/Audio Jet CONN USB20_N0 R680 1 2 0_0402_5% L_USB20_N0 ESATA and USB Conn.
16 USB20_N0
USB20_P0 R681 1 2 0_0402_5% L_USB20_P0
+USB_VCCB 16 USB20_P0 +USB_VCCA
@
P-TWO_196054-30041 L39 W=80mils

1P_0402

1P_0402
C802

C803
32 30 1 1 2 1 1 +USB_VCCA
G2 30 2
31 G1 29 29 USB POWER 1
28 28 1
27 4 3 @ @ C615 + C622 JESAT1
27 4 3 2 2 150U_B2_6.3VM_R35M 470P_0402_50V7K USB
26 26 1 VBUS
25 L_USB20_N0 WCM-2012-900T_4P L_USB20_N1 2
1
25
24 24 L_USB20_P0 USB20_N3
USB20_P3
2 2 L_USB20_P1 3
D-
D+
USB 1
23 4
23
22 22 USB20_N3
USB20_P3
USB20_N3 16
GND0
A+ = RXP
21 21 USB20_P3 16 5 GND1

1P_0402

1P_0402
C804

C805
20 SATA_ITX_DRX_P4_CONN 6
20
19 19
+USB_VCCC
EMI request
1 1 13 SATA_ITX_DRX_P4_CONN
13 SATA_ITX_DRX_N4_CONN SATA_ITX_DRX_N4_CONN 7
A+
A-
ESATA A- = RXN
18 18 8 GND2
17 @ @ SATA_DTX_C_IRX_N4 0.01U_0402_16V7K 2 1 C624 SATA_DTX_IRX_N4 9
17 2 2 13 SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4 B-
16 16 13 SATA_DTX_C_IRX_P4 2 1 C623 SATA_DTX_IRX_P4 10 B+
15 0.01U_0402_16V7K 11
15 USB20_N9 USB20_N9 GND3
14
14
13 13 USB20_P9
USB20_N9 16
USB20_P9 16
USB20_P9
+5VALW
12 GNDS1
B- = TXN
12 12 13 GNDS2
11 14
11 +USB_VCCA GNDS3
B+ = TXP

1P_0402

1P_0402
C806

C807
10 10
EMI request
1 1 E-SATA COMBO 15 GNDS4
9 U27
9
8 1 8
LEFT USB PORT TAIWI_EU091-117CRL-T
8 MIC_JD 33 GND OUT
7 PLUG_IN 33 @ @ C621 0.1U_0402_16V4Z 2 7 ME@
7 KILL_SW# 2 2 IN OUT
6 6 2 1 3 IN OUT 6
5 5 HP_OUTR 33 Audio Jet 4 EN OC# 5 USB_OC#1 16
4 4 HP_OUTL 33
3 APL3510BKI_SO8
3 GNDA
2 2 EXT_MIC_L 33 Low Active
1 1 EXT_MIC_R 33 1
C610 SVT EMI request
JUSB1 @ 1000P_0402_50V7K @
ME@ USB20_N1 R678 1 2 0_0402_5% L_USB20_N1
2 16 USB20_N1
2 USB20_P1 R679 1 2 0_0402_5% L_USB20_P1 2
16 USB20_P1
SP010804150 34 USB_ON# USB_ON# @
WCM-2012-900T_4P
Kill

1P_0402

1P_0402
C800

C801
+3VALW 4 3 1 1
4 3
2 R295 1 STATUS
100K_0402_5%
@ @
KILL_SW# 1,2(LOW) OFF 1 1 2 2
2 2
KILL_SW# 34 L38
2,3(HI) ON

+5VALW +USB_VCCB +3VS_BT +5VALW

U29
+3VS
1 GND OUT 8 W=40mils

1
C637 0.1U_0402_16V4Z 2 7
IN OUT R70 @ R979 BT@
2 1 3 IN OUT 6
USB_ON# 4 5 USB_OC#0 150_0603_1% 100K_0402_5%
EN OC# USB_OC#0 16
1 1
APL3510BKI_SO8 C636 C612 @

2
Low Active @ 1000P_0402_50V7K 4.7U_0805_10V4Z

3
D S
2 2 BTEN- 1 2 BT_EN_RC#
G
2 2
3 Q54 @
2N7002_SOT23 S
G
R55 BT@
Blue Tooth Moudle 3

1
220K_0402_5% 1 Q32 BT@
+5VALW +USB_VCCC C353 BT@
D
SI2301BDS-T1-E3_SOT23-3

OUT

1
U31 +3VS_BT
1 8 0.1U_0402_16V4Z
C677 0.1U_0402_16V4Z GND OUT 2
2 IN OUT 7 34 BT_EN 2 IN
2 1 3 6

GND
USB_ON# IN OUT USB_OC#5 +3VS_BT_R
4 EN OC# 5 USB_OC#5 16 1 2

1
1 Q31 BT@
APL3510BKI_SO8 C675 DTC124EKAT146_SC59-3 PVT,chg AO3413 main R321 BT@ 1

3
@ 1000P_0402_50V7K R71 @ 0_0603_5% PVT
Low Active 100K_0402_5%
2 C354 BT@

2
2 0.1U_0402_16V4Z
28 BT_LED#
JBT1

1
1 1
2

OUT
USB20_P11 2
16 USB20_P11 3 3
16 USB20_N11 USB20_N11 4
+3VS BTON_LED 4
IN 2 5 5 G1 7
BT_PRESENCE 6 8
CARD READER CONN

GND
R234 6 G2
1 2 BT_PRESENCE Q29 ACES_87213-0600G
DTC124EKAT146_SC59-3 ME@

3
+3VALW @
10K_0402_5%
JCR1 @
4 4
1 1
USB20_N5 2
16 USB20_N5 2
USB20_P5 3 5
16 USB20_P5 3 GND
4 4 GND 6

ACES_85201-04051 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
ME@
SP01000KC00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB ports/BT/E-SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 37 of 50
A B C D E
 ON/OFF switch FOR DEBUG Power Bottom Board Conn.4pin
SW 1 +5VALW Cap Sensor Board Conn. 8pin
1 3
Power Button 2 4
JPW 1
ENE SB3534
SMT1-05_4P 1 1
34 PW R_LED# 2

6
5
+3VALW ON/OFFBTN# 2
3 3 GND 5
4 6 1 2
TOP Side @ 4 GND +3VS
R349 0_0402_5%

2
ACES_85201-04051 1 2 +5VS_CAP +3VS_CAP JCAP1
+5VS
R351 0_0402_5% 1
R272 ME@ 1
2
Bottom Side 100K_0402_5% SP01000KC00 3
2
D14 NOVOBottom/ALS Board Conn.6pin 13 HDD_LED#
4
3
34 CAP_RST#

1
ON/OFF# R3 4
2 ON/OFF# 34 34 CAP_INT 1 2 0_0402_5% I2C_INT_R 5 5
ON/OFFBTN# 1 +3VALW JFB1 6
51_ON# NOVO_BTN# R2 6
3 51_ON# 40 1 1 34 ESB_DAT 1 2 0_0402_5% 7 7
2 R1 1 2 0_0402_5% 8
2 34 ESB_CLK 8
BAV70W _SOT323-3 3 9
3 GND
34 ALS_CLK 4 4 2 2 10 GND
PVT 5 @ @
34 ALS_DATA 5

1
D C1 C2 ACES_85201-0805N
34 LID_SW # 6 6
EC_ON 2 Q28 7 33P_0402_50V8J 33P_0402_50V8J ME@
34 EC_ON GND 1 1
G 2N7002_SOT23-3 8
2 GND
S

3
R302 ACES_85201-06051
10K_0402_5% ME@ SP01000H200
PIN adjust
SP01000B000
1

NOVO_BTN# ON/OFFBTN#

2
+3VALW D19 D20
PJSOT24C 3P C/A SOT-23 PJSOT24C 3P C/A SOT-23
@ @
2

R296
FP Board Conn 4 pin

1
100K_0402_5% PVT

D13
1

NOVO# 2
34 NOVO#
1 NOVO_BTN#
51_ON# 3
EMI REQUEST 1ST = SCA00000E00 +3VS

BAV70W _SOT323-3 2ST = SCA00000R00 JFP1

1 1
USB20_N10 2
16 USB20_N10 2
USB20_P10 3 5
16 USB20_P10 3 GND
4 4 GND 6

+3VS_GEN +5VALW
APS G-Sensor ACES_85201-04051

ME@
+3VS
W=20mils SP01000KC00
1
RG7 @ RG2 GEN@
150_0603_1% 100K_0402_5%
1
CG9 @
2

4.7U_0805_10V4Z
LED CONN 8 pin
1

3
D S
+3VALW
GENEN- GEN_EN_RC# 2
G 2 +5VALW
2 1 2
+3VS_GEN QG2 @ G
+5VS
2N7002_SOT23 S RG8 GEN@ JLED
3

RG1 GEN@ 220K_0402_5% 1 QG1 GEN@ 1

+3VS_GEN_R CG4 GEN@
D
SI2301BDS-T1-E3_SOT23-3 1
1 2 2
OUT

1
47_0402_5% 2
3 3
1 1 1 0.1U_0402_16V4Z 4
2 34 SUSP_LED# 4
CG3 34 GEN_EN 2 +3VS_GEN_R Amber 34 BATT_LOW _LED# 5
CG1 GEN@ 10U_0805_10V4Z IN 5
6
GND

34 BATT_CHG_LED# 6
0.1U_0402_16V4Z GEN@ Blue W LAN_LED# 7
28,34 W LAN_LED# 7
1

2 2 2 QG3 GEN@ PVT,chg AO3413 main 8 8

DTC124EKAT146_SC59-3 9
3

RG9 @ GND
10 GND
100K_0402_5%
1

CG2 GEN@ ACES_85201-0805N

2

1U_0603_10V6K RG3 @ ME@

10K_0402_5%

UG1 GEN@ RG4 GEN@ SP01000H200

2

56K_0402_5%
ST 2 12 X 1 2 VOUTX VOUTX 34
34 G_SELFTEST ST Xout
10 Y 1 2 VOUTY VOUTY 34
Yout RG5 GEN@
1

14 56K_0402_5%
RG6 GEN@ Vs
15 Vs
100K_0402_5% 1 PVT
NC
NC 4
8
2

NC
3 COM NC 9
5 COM NC 11
6 COM NC 13 1 1 +1.5VS_VGA +3VS +3VS +3VS
7 COM NC 16 1 1 1 1
CG7 GEN@ CG8 GEN@
0.1U_0402_16V4Z 0.1U_0402_16V4Z C723 C724 C725 C729
S IC LIS244ALTR LGA 16P G-SENSOR 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
+5VALW +5VALW +5VALW +3VALW

+3VS
1
+3VS
1
+3VS
1
+3VS
1
+3VS
1
+1.5VS_VGA
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
C720 C721 C722 C726 C727 C728
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
Audio Jack & SW connector
2 2 2 2 2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VS +5VS +1.05VS +5VS +VGA_CORE +VGA_CORE Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 38 of 50
 A B C D E

+5VALW TO +5VS +3VALW TO +3VS +1.5V to +1.5VS

+1.5VS +5VALW
+5VALW +5VS +3VALW +3VS
U10 SI4800BDY-T1-E3_SO8 U4 SI4800BDY-T1-E3_SO8 +1.5V
W=60mils

1
8 1 8 1
1 7 2 1 1 1 7 2 1 1

1
C279 6 3 6 3 R337 R178
10U_0805_10V4Z 5 C277 C276 C127 5 C134 C135 470_0603_5% 100K_0402_5% 1
10U_0805_10V4Z 1U_0603_10V6K R202 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V6K R87 C389 @

1 2

2
2 2 2 470_0603_5% 2 2 2 470_0603_5% SVT,discharge 4.7U_0805_10V4Z

3
D PVT,timing
S

1 2

1 2
1 B+ B+ 2 1.5VS_EN- 1 2 R_1.5VS_EN-
G
2 2 1
D D Q34 G
2 SUSP 2 SUSP 2N7002_SOT23 S R312 SI2301BDS-T1-E3_SOT23-3

3
1
G G 15K_0402_1% 1

1
S Q16 S Q6 C361 Q33 D

1
R229 2N7002_SOT23 R89 2N7002_SOT23

OUT
20K_0402_5% 47K_0402_5% 0.1U_0402_16V4Z
2 +1.5VS
W=60mils

2
5VS_GATE 2 R228 15VS_GATE_R SVT,discharge 3VS_GATE SVT,discharge SUSP# 2
IN
1 1

GND
1

1
D 10K_0402_5% D

1
SUSP 2 Q20 C278 SUSP 2 Q9 C144 Q13 PVT,chg AO3413 main
G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K DTC124EKAT146_SC59-3 1 1

3
S 2 S 2 R181
3

3
100K_0402_5% C362 C363
10U_0805_10V4Z 1U_0603_10V6K

2
2 2

+1.8VS +1.5V +VCCP +0.75VS +1.05VS

SYSON 1 2 +5VALW
R673 RTCVREF +5VALW
1

1
SVT 10K_0402_5%

1
MUST CLOSE PR501,1.5V_EN

1
R142 R342 R174 R568 R143 @ MP
470_0603_5% 470_0603_5% 470_0603_5% 22_0603_5% 470_0603_5% R6
@ @ @ 100K_0402_5% @ R4 R5
1 2

1 2

1 2

1 2

1 2
100K_0402_5% 100K_0402_5%

2
D D D D D SYSON#

2
2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 SUSP Q2
8,44,45 SUSP
SUSP

1
G G G G G DTC124EKAT146_SC59-3
S Q10 S Q35 S Q15 S Q40 S Q11 @ Q1

OUT
3

1
2 2
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 DTC124EKAT146_SC59-3
@ @ @

OUT
SYSON 2
34,44 SYSON IN
SVT,add

GND
SVT,discharge 2
34,42,46 SUSP# IN

GND
For Intel S3 Power Reduction.

3
+1.05VS to +1.05VS_VGA Transfer +1.5V to +1.5VS_VGA Transfer
+1.5V +1.5VS_VGA

1
+1.05VS_VGA C706
+VGA_1.05VS 10U_0805_10V4Z
SVT HYBRID@
2
HYBRID@ U33 250mil(6A)
AO4430L_SO8
8 1
HYBRID@ 7 2
U34 SI4800BDY-T1-E3_SO8 100mil(1.5A) 1 1 6 3

2
8 1 C686 C705 5 1 1
3 1 7 2 10U_0805_10V4Z 10U_0805_10V4Z C685 C684 R624 3
2

C681 6 3 1 1 HYBRID@ HYBRID@ 10U_0805_10V4Z 0.1U_0402_16V4Z 470_0603_5%

4
10U_0805_10V4Z 5 C680 C679 R621 2 2 HYBRID@ HYBRID@ HYBRID@
HYBRID@ HYBRID@ 0.1U_0402_16V4Z 470_0603_5% 2 2

1
2 10U_0805_10V4Z HYBRID@ HYBRID@
4

2 2
1

B+
B+

6
HYBRID@ PVT,timing
6

1 2 1.05VSDGPU_GATE 1 2 1.5VSDGPU_GATE Q57A

R622 510K_0402_1% Q24A 2N7002DW-T/R7_SOT363-6
1 2N7002DW-T/R7_SOT363-6 R623 1 HYBRID@ 2 DGPU_PWR_EN#
C682 HYBRID@ 2 DGPU_PWR_EN# 200K_0402_1% C683
3

3
0.1U_0603_25V7K HYBRID@ 0.1U_0603_25V7K

1
Q24B HYBRID@ Q57B HYBRID@
1

2
2N7002DW-T/R7_SOT363-6 2
2N7002DW-T/R7_SOT363-6
DGPU_PWR_EN# 5 HYBRID@ DGPU_PWR_EN# 5 HYBRID@
4

4
+5VALW
1

R52
100K_0402_5%
HYBRID@
2

DGPU_PWR_EN#
4 4

R127
1

0_0402_5% D
2 1 2 Q56
16,22,45 DGPU_PWR_EN
G 2N7002W-T/R7_SOT323-3
HYBRID@ S HYBRID@
3
1

Security Classification Compal Secret Data Compal Electronics, Inc.

R53 2010/01/13 2011/01/13 Title
100K_0402_5%
Issued Date Deciphered Date
HYBRID@ DC Interface
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5941P
Date: Thursday, April 08, 2010 Sheet 39 of 50
A B C D E
 A B C D

ACIN BATT ONLY

Precharge detector Precharge detector
VIN
Min. typ. Max. Min. typ. Max.
PF101 PL101 L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
JDCIN1 7A_24VDC_429007.W RML SMB3025500YA_2P
1 APDIN 1 2 APDIN1 1 2
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V
1

2 2

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
@ 0.1U_0603_25V7K

@ 0.1U_0603_25V7K
1
3 3 1

PR102

1
4 1K_1206_5%
4 PQ102
1 2

PC104
5 TP0610K-T1-E3_SOT23-3

2
GND

PC101

PC102

PC103

PC105

PC106
PR103
6 1K_1206_5%
GND
VIN 2 1 1 2 3 1
ACES_87302-0401-003
PD102 PR104
RLS4148_LL34-2 1K_1206_5%
1 2

100K_0402_1%
1

1
100K_0402_1%
PR105

PR106

2
Vin Detector

2
Min. typ. Max.
L-->H 17.430V 17.901V 18.384V

100K_0402_1%
H-->L 16.976V 17.262V 17.728V

PR107
1
PR101
1M_0402_1%

1 2
1 2
VINDE-2 VIN 2
VS 34,42 ACOFF PQ103
VIN
2
DTC115EUA_SC70-3 2
0.01U_0402_25V7K

B+

10K_0805_5%
2

3
1
PQ104
1

PC107

PR109
PR108 PR110 DTC115EUA_SC70-3
84.5K_0402_1% 10K_0402_1%
2

3
2 1 2 ACIN 34
PR111
2

22K_0402_1%
VINDE-1 1 2 3
P

+ PACIN PR113
0.068U_0603_16V7K

O 1 PACIN 42
VINDE-3 2 -
VL 2.2M_0402_5%
G
1

20K_0402_1%

10K_0402_5%
PU102A
0.1U_0402_16V7K

2 1
1

LM393DG_SO8 1
4
PC108

PR112

PC109

PR114
PD101
2

499K_0402_1%
LLZ4V3B_LL34-2
2

1
PR115 VS
2

PR116
10K_0402_5%

0.01U_0402_25V7K
100K_0402_1%
2 1 RTCVREF 3.3V

1
PR117

PC110

2
2
PD103

8
RB715F_SOT323-3
41,43 MAINPWON 2 5 PRG+

P
+
VIN 1 PRG-1 7 O PRG-

205K_0402_1%

499K_0402_1%
42 ACON

0.01U_0402_25V7K
3 6

G
-

1
PU102B

1
PR118

PR119

PC112
LM393DG_SO8

1000P_0402_50V7K
4
2

1
3 3

PC111
PD104

0.1U_0603_25V7K

2
LL4148_LL34-2

PRG++ 2

2
1

PC113
PD105
1

LL4148_LL34-2 51ON-1

2
BATT+ 2 1
1

PQ105
PR120 PR121 PR122 2N7002KW _SOT323-3 PR123

1
PQ101 68_1206_5% 68_1206_5% 10K_0402_5% D 47K_0402_5%
TP0610K-T1-E3_SOT23-3 2 1 2 2 1 PACIN
PR124 RTCVREF G
2

1
200_0603_5% S

3
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1

2 +5VALW
2

1
PC114

PR125 PC115
100K_0402_1% 0.1U_0603_25V7K
1

PR126 PQ106
2

3
22K_0402_1% DTC115EUA_SC70-3
1 2 51ON-3
38 51_ON# - JRTC1 + PR128
560_0603_5%
2 1+RTCBATT-1 1 2 +RTCBATT

RTCVREF PD106
1

@ MAXEL_ML1220T10 1 2
PU101 PR127 +CHGRTC
+CHGRTC 200_0603_5% RB751V-40_SOD323-2
4
PR129 APL5156-33DI-TRL_SOT89-3 4

560_0603_5% 3.3V
RTC Battery
2

RTCVREF-1
1 2 3 2CHGRTCIN
VOUT VIN
1

GND PC117
PC116 1U_0805_25V6K
10U_0603_6.3V6M 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 40 of 50
A B C D
 A B C D

1 1

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

VMB2 VMB VL
PF201 PL201
JBATT 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2 VL
1 BATT+
2 2
3 EC_SMCA
3

1
4 EC_SMDA
4

2
2
5 TS PC203 PR203 PR204 2

1
6 0.1U_0603_25V7K 10K_0402_1% 21.5K_0402_1% PR205

2
6
1

7 PC201 PC202 @ 100K_0402_1%

7 0.01U_0402_25V7K
100_0402_1%

100_0402_1%

8 1000P_0402_50V7K

2
GND PU201
9

1
GND G718_TMSNS1
1 8

2G718_TMSNS2
VCC TMSNS1
PR201

PR202

@ SUYIN_200082MR007G100ZR
2

2
2 7 G718_RHYST1
GND RHYST1 PR206
3 6 9.76K_0402_1%
OT1 TMSNS2

@ 47K_0402_1%
4 5

1
G718_RHYST2
OT2 RHYST2

1
PR207
G718TM1U_SOT23-8
PH201
100K_0402_1%_TSM0B104F4251RZ
EC_SMB_CK1 34

2
EC_SMB_DA1 34 MAINPW ON 40,43

1
1 2 +3VALW PH202
PR208 @ 100K_0402_1%_TSM0B104F4251RZ
6.49K_0402_1%

2
1
PR209
2 BATT_TEMP 34 A/D
10K_0402_5%

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 41 of 50
A B C D
 5 4 3 2 1

P3
B+
P2
PQ301 PQ302
FDS6675BZ_SO8 FDS6675BZ_SO8
PR302
VIN 8
7
1
2
1
2
8
7 0.02_1206_1% CHG_B+
6 3 3 6 PJ301
PQ303
5 5 1 4 2 2 1 1
FDS6675BZ_SO8

@ 470P_0603_50V8J

0.1U_0603_25V7K
2 3 @ JUMP_43X118 1 8

1
47K_0402_5%

2 7
1

PC302
3 6

2200P_0402_50V7K
PR301

PC324

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5

2
D D

2
200K_0402_1%
DTA144EUA_SC70-3

0.1U_0603_25V7K

PC306

4
1

PC304

PC305

PC303
CSIN DISCHG_G
2

PC301

PR303
PQ304 CSIP

1
PR304
47K_0402_1%

2
2 1 2

2
VIN

2
1

PR305

1DISCHG_G-1
PD301 10K_0402_1% 3 ACOFF
1

RB751V-40TE17_SOD323-2 1
P2-1 1 2 6251_VDD 2

1
2 PR307

2.2U_0603_6.3V6K
PC307
PQ305 PR306 PD302 200K_0402_1%

1
10K_0402_1% RB715F_SOT323-3 1 2 VIN
DTC115EUA_SC70-3 FSTCHG 2 1 PU301 PC309
34 FSTCHG 0.1U_0603_25V7K
3

2
1 2 1 24 6251_DCIN2 1 PQ306
VDD DCIN

100K_0402_1%
PC308 DTC115EUA_SC70-3 2
PQ307 0.1U_0402_16V7K
1

D 2N7002KW _SOT323-3

PR308
150K_0402_1%

2 ACSET ACPRN 23
PR309

2 PR310

SIS412DN-T1-GE3 _PAK1212-8
G 20_0402_5%

0.1U_0603_25V7K
2

3
5

1
6251_EN 6251_CSON CSON D
S 3 22 1 2
3

EN CSON

1
PC311
PC310 2 PACIN
P2-2 2

0.047U_0402_16V7K G

PQ308
CELLS 4 21 6251_CSOP 1 2 CSOP S

3
CELLS CSOP PR311 PQ309
PC312 6800P_0402_25V7K 20_0402_5% 4 2N7002KW _SOT323-3
C PR313 PQ310 6251_ICOMP 6251_CSIN C
1 2 5 ICOMP CSIN 20 2 1
1

2
3K_0402_1% D 2N7002KW _SOT323-3 PC314 PR312
PACIN 1 2 2 PC313 PR314 6.81K_0402_1% 0.1U_0402_16V7K 20_0402_5%
40 PACIN
G 1 26251_VCOMP-1
1 2 6251_VCOMP 6 19 6251_CSIP 1 2 PL301 PR317

3
2
1
VCOMP CSIP PR315 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%
S
3

0.01U_0402_25V7K 1 2 2.2_0402_5% BATT+

PC315 1 26251_ICM 7 ICM PHASE 18 LX_CHG 1 2 CHG 1 4
40 ACON @ 100P_0402_50V8J PR316

5
34 ADP_I 100_0402_1% 2 3

SI7716ADN-T1-GE3 _PAK1212-8

1
6251_VREF DH_CHG

4.7_1206_5%
8 VREF UGATE 17
1

PR318
PQ311 PR319 1 2 PR320 PC317
DTC115EUA_SC70-3 154K_0402_1% PC316 2.2_0402_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PQ312

16251_SN
2 1 0.1U_0402_16V7K 6251_CHLIM 9 16 BST_CHG 1 2 BST_CHGA 2 1
34 IREF CHLIM BOOT

1
PR321 4

1
PC318

PC319

PC320
ACOFF 2 16.9K_0402_1% PD303
0.01U_0402_25V7K

34,40 ACOFF
6251_VREF 1 2 6251_ACLIM 10 15 6251_VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

2
1
PC321

PR322 26251_VDD

680P_0603_50V7K
1

3
2
1
1

PC322
100K_0402_1% 6251_VADJ
11 14 DL_CHG
3

2
VADJ LGATE

1
PR324 PR323
2

2K_0402_1% 4.7_0402_5%
2

12 13 PC323

2
GND PGND 4.7U_0805_6.3V6K
2

ISL6251AHAZ-T_QSOP24
PR325
Connect to EC A/D Pin. 15.4K_0402_1%
1 2
34 CHGVADJ
CHGVADJ=(Vcell-4)/0.10627
1

B 6251_VDD 6251_VDD B
Vcell CHGVADJ
PR326
4V 0V DIS/UMA CP mode (55W) 31.6K_0402_1%
4cell : PR327

2
4.2V 1.882V Vaclim=2.39*(2K/(2K+16.9K))=0.253V PR327 PR328
3cell : PR330
2

100K_0402_1% @ 100K_0402_1%
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
4.35V 3.2935V
where Vaclim=0.253V, Iinput=2.76A

1
CELLS

3
CC=0.25A~3A
IREF=1.016*Icharge PR330
@ 0_0402_5% 2 5 2 1
IREF=0.254V~3.048V PR331

2
@ 0_0402_5%

4
VCHLIM need over 95mV 34 BATT_SEL_EC
PQ314 TP0610K-T1-E3_SOT23-3 PR333
10_0603_5% PQ313A PQ313B
3 1 P3-1 1 2 6251_DCIN @ 2N7002KDW -2N_SOT363-6 @ 2N7002KDW -2N_SOT363-6
P3
1
100K_0402_1%
PR335

PR337
2

P3-2 2 1 P3-3

100K_0402_1%
A A
1

PQ315
DTC115EUA_SC70-3 2 FSTCHG
2P3-41
3 SUSP#
SUSP# 34,39,46 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
PD304
CHARGER
3

RB715F_SOT323-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 42 of 50

5 4 3 2 1
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJ401 PR401
@ JUMP_43X118 0_0402_5%
2 2 1 1 1 2

330P_0402_50V7K

10U_1206_25V6M

2200P_0402_50V7K
D D

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6
1

1
PC401

PC402

PC403

PC404

PC406

PC407
5

PC405
1U_0603_10V6K
VL

2
2
2

PC409
PC408
PQ401 0.1U_0603_25V7K 4

4.7U_0805_6.3V6K
3/5V_VCC
1

1
3/5V_VIN
4 SIS412DN-T1-GE3_PAK1212-8 PQ402

PC410
SIS412DN-T1-GE3_PAK1212-8
+5VALWP

3
2
1
PL402

1
2
3
PL401 4.7UH_FMJ-0630T-4R7 HF_5.5A_20%

7
4.7UH_FMJ-0630T-4R7 HF_5.5A_20% PU401 PC411 2 1
1 2 1U_0603_10V6K

VIN

VCC

LDO
+3VALWP 33 19 1 2
TP PVCC

1
1

5
UG3 26 15 HG5
PR402 UGATE2 UGATE1 PR405
0_0402_5%

4.7_1206_5% BST3A-1 2 1 BST3A 24 17 BST5A2 1BST5A-1 4.7_1206_5% 1

BOOT2 BOOT1
2

PR403 PR406

15V_SNB
1

2
2

2
+
PR404

2.2_0603_5% 2.2_0603_5% PC415

@ 61.9K_0402_1%
4

13V_SNB
2
PC412 + 4 PC413 150U_B2_6.3VM_R45M

2
150U_B2_6.3VM_R45M 0.1U_0603_25V7K

1
2

PR407
SW 3 25 16 SW 5 PC416
1

2 PC417 PHASE2 PHASE1 PC414 680P_0603_50V7K

3
2
1
680P_0603_50V7K 0.1U_0603_25V7K

1
2
3

2
LG3 23 18 LG5
2

1
PQ403 LGATE2 LGATE1
10K_0402_1%

SI7716ADN-T1-GE3_PAK1212-8
2

C C
PGND 22

2
PR408

FB3 30 PQ404
OUT2

PR409
0_0402_5%
SI7716ADN-T1-GE3_PAK1212-8
OUT1 10
VL 32
1

@ FB2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC418
0.22U_0603_25V7K 9
BYP
8 NC
PD401 29 5V_SKIP 2 1
SKIP PR410
VL
1 2
@ 0_0402_5%
RB751V-40_SOD323-2 1 2
20 28 PR411
PR412 SECFB POK2 0_0402_5%
VS PD402 100K_0402_1% 2 1 2VREF_ISL6237
1 2 EN_LDO-1 1 2 EN_LDO 4 13 PR413
EN_LDO POK1 @ 0_0402_5%
2
200K_0402_1%

LLZ5V1B_LL34-2
2
PR414

PC419 3/5V_EN1 14 12 ILM1 2 1

0.22U_0603_25V7K EN1 ILIM1 PR415
301K_0402_1%
1

3/5V_EN2 27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
PR416
2
B RT8206BGQW _QFN32_5X5 301K_0402_1% B

21
VL
806K_0603_1%

PD403

13/5V_NC
2

1 2 PR417

13/5V_TON
PR418

0_0402_5%
1

RB751V-40_SOD323-2 PR420
1U_0603_10V6K
PC420

@ 47K_0402_1%
2VREF_ISL6237

PR419
1

2 1 1 2
2

40,41 MAINPW ON
0_0402_5% PR421
0.047U_0402_16V7K

0.047U_0402_16V7K

0_0402_5% PJ402
1

+3VALWP 2 1 +3VALW
2

2 1
PC421

PC422

@ JUMP_43X118
2

2VREF_ISL6237

@ PJ403
+5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2010/01/13 2011/01/13 Title
Issued Date Deciphered Date 3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 43 of 50
5 4 3 2 1
 5 4 3 2 1

PJ501
1.5V_IN 2 1 B+
2 1
@ JUMP_43X79

5
6
7
8

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6
D D

1
PC502

PC503

PC504

PC505
PR502

2
240K_0402_1% 4
1.5V_TON 1 2
PR501
0_0402_5%
1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2 PQ501
34,39 SYSON

3
2
1
PR503 PC506 SI4172DY-T1-GE3_SO8
2.2_0603_5% 0.1U_0603_25V7K

1
PL501

15

14
1
PC501 PU501 1.0UH_PCMC104T-1R0MN_20A_20%
@0.1U_0402_16V7K 1 2

ΚΚ

EN/DEM

NC

BOOT
+1.5VP

220U_B2_2.5VM_R15M
1
2 13 UG_1.5V

TPCA8028-H_SOP-ADVANCE8-5
TON UGATE
Imax 13A

Κ
PR505 3 12 SW _1.5V PR504
VOUT PHASE

5
100_0603_1% 4.7_1206_5% Ipeak 16.2A

10U_0603_6.3V6M
1
+5VALW 1 2 1.5V_V5FILT 4 11 1.5V_TRIP
1 2 +5VALW

1.5V_SNB 2
VDD CS

1
+ OCP 30A

PC507
PR506
1.5V_FB 5 10 7.15K_0402_1%
FB VDDP

PC508
2
1

LG_1.5V 2
6 PGOOD LGATE 9 4

PGND

PQ502
PC509

GND
4.7U_0603_6.3V6K PC510
2

1
@ 47P_0402_50V8J PC513
1 2 RT8209BGQW _W QFN14_3P5X3P5 PC512 680P_0603_50V7K

3
2
1
4.7U_0805_6.3V6K

2
PR508
C 31.6K_0402_1% C

1 2
1

PR509
30.1K_0402_1%
2

PJ504
+1.5VP 2 2 1 1 +1.5V
@ JUMP_43X118

PJ506
+0.75VSP 2 2 1 1 +0.75VS
+1.5V
@ JUMP_43X79
B B
1

PJ503
1

@ JUMP_43X79
2

PU503
2

0.75V_IN 1 6 +3VALW
VIN VCNTL
2 GND NC 5
1

1
PC525
1

4.7U_0805_6.3V6K 3 7 PC526
PR519 VREF NC 1U_0402_6.3V6K
2

2
1K_0402_1% 4 8
VOUT NC
PR523 9
2

0_0402_5% TP
1 2 0.75V_REF G2992F1U_SO8
5 S3_0.75V_EN
1

PR521 +0.75VSP
1

@ 0_0402_5% D PR522
0.75V_EN 2 1K_0402_1% PC527
10U_0603_6.3V6M

10U_0603_6.3V6M

8,39,45 SUSP 1 2
1

1
PC529

PC530

G 0.1U_0402_16V7K
2
1

S PQ505
3

PC528 SSM3K7002FU_SC70-3
2

@ 0.1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V/0.75VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 44 of 50
5 4 3 2 1
 5 4 3 2 1

PJ601
VGA_IN 2 1 B+
2 1
@ JUMP_43X79
PR601

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
205K_0402_1%

0.1U_0402_25V6
1

1
VGA_TON 1 2

5
6
7
8

PC601

PC602

PC603

PC604
2

2
PR603 PC605

ΚΚ
D
2.2_0402_5% 0.1U_0603_25V7K PQ601 D
1 2 VGA_EN 1 2 BST_VGA-1 1 2 4 AO4466_SO8
16,22,39 DGPU_PW R_EN
PR602 BST_VGA Imax 8.89A

Κ
33K_0402_1%

1
PC606
Ipeak 9.88A

3
2
1
0.1U_0402_16V7K PL601 OCP 12.19~15.21A

15

14
2

1
PU601 0.82UH_PCMC063T-R82MN_13A_20%
1 2

EN/DEM

NC

BOOT
+VGA_COREP
PR604 2 13 UG_VGA
@ 0_0402_5% TON UGATE
PR605 +VGA_COREP 1 2 VGA_VOUT 3 12 SW _VGA
VOUT PHASE

5
6
7
8

1
100_0603_1%

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

330U_D2_2.5VY_R9M
1 2 VGA_V5FILT 4 11 VGA_TRIP
1 2 +5VALW
+5VALW VDD CS

1
PR606 PR607 +

1VGA_SNB

1
VGA_FB 5 10 7.68K_0402_1% 4.7_1206_5%
FB VDDP

PC607

PC609

PC610

PC611
PQ602 PR608

2
1 LG_VGA SI4634DY-T1-E3_SO8 100_0402_5% 2
6 PGOOD LGATE 9 4

PGND
PC612

GND
PR609
0_0402_5%
4.7U_0603_6.3V6K PC613
2

2
1
680P_0603_50V7K
RT8209BGQW _W QFN14_3P5X3P5 PC614

3
2
1

2
4.7U_0805_6.3V6K

2
PC615
@ 47P_0402_50V8J
2 1
Rds=5.5~6.7mȍ
PR610 PR611
VGA_PW ROK 16
6.81K_0402_1% 0_0402_5%
C VGA_FB1 C
2 1 1 2 +VGASENSE 21

PR612 PR613
84.5K_0402_1% 84.5K_0402_1%
GVID1-2 1 2 1 2

VFB=0.75V
6

PR615 PJ602
2 1GVID1-1 2 PQ603A @ 100K_0402_1%
+VGA_COREP 2 1 +VGA_CORE
19 GPU_VID1 PR614 2N7002KDW -2N_SOT363-6 2 1
1

10K_0402_1% @ JUMP_43X118
1

2
1

PR616
10K_0402_5%
GVID0-2
2

PC616 PJ603
2

0.01UF_0402_25V7K 1 2
+1.8VSP 1 2 +1.8VS
@ JUMP_43X39
3

2 1GVID0-1 5 PQ603B
19 GPU_VID0 PR617 2N7002KDW -2N_SOT363-6
1

@ 10K_0402_1%
4
1

PR618
B @ 10K_0402_5% PC617 +3VS B
@0.01UF_0402_25V7K
2
2

1
PJ604

1
@ JUMP_43X39

2
PU602
LDO_1.8V_IN 1 6
GPIO5 GPIO6 +5VS

2
VIN VCNTL

N11M-GE1/LP1 GPU_VID0 GPU_VID1 VGA_CORE 2 GND NC 5

1
PC618

1
0 0 0.8V 4.7U_0805_6.3V6K 3 VREF NC 7 PC619
PR619 1U_0402_6.3V6K

2
0 1 0.86V 1K_0402_1% 4 8
VOUT NC
1 1 0.86V 9

2
TP
LDO_1.8V_REF G2992F1U_SO8

1
PR620 +1.8VSP
1

1
33K_0402_1% D PR621
2LDO_1.8V_EN 1.24K_0402_1% PC620

10U_0603_6.3V6M

10U_0603_6.3V6M
8,39,44 SUSP 1 2

1
PC621

PC623
G 0.1U_0402_16V7K

2
1

S
3

PC622 PQ604 2

2
0.1U_0402_16V7K SSM3K7002FU_SC70-3
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE/1.8VS/1.1VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 45 of 50
5 4 3 2 1
 5 4 3 2 1

PJ701
2 1 VTT_B+
B+ 2 1
@ JUMP_43X118
D D

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
PR701 SW _VTT

0.1U_0402_25V6
1

1
1K_0402_5%

PC701

PC702
+5VS 1 2 UG_VTT PR702

PC703

PC704
2.2_0603_5%

1.1VS_PGOOD
2

2
VTT_BOOT1 2 VTT_BOOT-1 1 2
PR703
0_0402_5% PC705
1 2 +5VALW 0.1U_0603_25V7K
5 VCCP_POK

5
PR704
0_0603_5%

PR705

16

15
8

1
PU701 4.7_0603_5% PQ701

ΚΚ

2
1 2 VTT_VCC 4 TPCA8030-H_SOP-ADV8-5

GND

PGOOD

PHASE

UG

BOOT
Imax 20A

Κ
3 14 VTT_PVCC
1 2
VIN PVCC
Ipeak 22A

3
2
1
PC706
2.2U_0603_6.3V6K OCP 30A
VTT_VCC 4 13 LG_VTT PL701
PD701 VCC LG 0.36UH_PCMC104T-R36MN1R17_30A_20%
@ RB751V-40_SOD323-2 1 2 +1.1V_VCCPP
1

1 2 APW 7138NITRL_SSOP16

1
PC707 12

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
2.2U_0603_6.3V6K PGND
2

PR706 PR707

330U_D2E_2VM_R6M
1
47K_0402_1% 4.7_1206_5%
+

PQ702

PQ703
1 2 VTT_EN-1 5 11 VTT_ISEN 1 2
34,39,42 SUSP#

1 2
C EN ISEN VTT_SNB C
4 4

PC709
FSET
PR709
1

NC

VO
2.21K_0402_1% PC711

FB
PC710 1000P_0603_50V7K

2
0.1U_0402_16V7K
2

10

3
2
1

3
2
1
1 VTT_FSET
VTT_FB
VTT_COMP @ 22.1K_0402_1%
1

42.2K_0402_1%
Rds=1.15~1.6mȍ

2
PR710
VTT_COMP-1

1
PR712
PR711 PC712 10_0402_5%
2

@0.01U_0402_25V7K
@ 22P_0402_50V8J

2
1

@ 6800P_0402_25V7K

1
PC713

316KHz
1
PC714

PR715
0_0402_5%
1 2 1 2 VTT_FB-1 2 1
8 VTT_SELECT PR713 PR714 VTT_SENSE 8
35.7K_0402_1% VFB=0.6V 1.58K_0402_1%
1

H_VTTVID1= Low, 1.1V PR716

B 1.96K_0402_1% B
H_VTTVID1= High, 1.05V PJ702
2

+1.1V_VCCPP 2 2 1 1 +VCCP
@ JUMP_43X118

PJ703
2 2 1 1

@ JUMP_43X118

PJ705
2 2 1 1 +VGA_1.05VS
@ JUMP_43X118

PJ704
+VCCP 2 2 1 1 +1.05VS
@ JUMP_43X118

330U_D2E_2VM_R6M
1
+

PC708
2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VS_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 46 of 50
5 4 3 2 1
 5 4 3 2 1

8
GFXVR_EN

GFXVR_VID_48

GFXVR_VID_58

GFXVR_VID_68
8

8
GFXVR_VID_0

GFXVR_VID_1

GFXVR_VID_2

GFXVR_VID_3
D D

0_0402_5%
2
+3VS

@ PR814

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1
1
+5VS

PR801 +GFX_B+ PL801

10K_0402_1% FBMA-L11-201209-121LMA50T_0805

2
PR802

2
0_0402_5%

PR803

PR804

PR805

PR806

PR807

PR808

PR809

PR810
1 2 B+
2 1GFX_PWRGD PR811

10U_1206_25V6M
GFXVR_PWRGD
10_0603_1%

2200P_0402_50V7K

10U_1206_25V6M
0.1U_0603_25V7K
1

1
+VCCP

PC802

PC803
PC819

PC818
GFX_EN

31 GFX_VID0

30 GFX_VID1

29 GFX_VID2

28 GFX_VID3

27 GFX_VID4

26 GFX_VID5

25 GFX_VID6

5
6
7
8

SI4172DY-T1-GE3_SO8

2
1

1
PR812

GFX_VCC
@ 300K_0402_1% PC804
1U_0603_16V6K

PQ801
32

2
8 GFXVR_IMON GFX_IMON 4
1 2

VID0

VID1

VID2

VID3

VID4

VID5

VID6
EN
0.056U_0402_16V7K

PR813 24 PR815 PC805

1

6.98K_0402_1% VCC 2.2_0603_5% 0.22U_0603_25V7K

PC801

3
2
1
PWRGD
23 GFX_BOOST 1 2GFX_BOOST-1
1 2
BST
1

GFX_IMON 2
2

PC806 IMON GFX_DRVH

22 PL802
1000P_0402_50V7K DRVH
3
2

CLKEN# GFX_SW
21 1 4
GFX_FBRTN 4
SW +GFX_COREP
FBRTN

1
C ADP3211AMNR2G_QFN32_5X5 20 +5VS 2 3 C

5
GFX_FB PVCC
1 2 5 1
FB

330U_D2_2.5VY_R9M
PU801 19 GFX_DRVL 2 1 PR816

1
PC807 PC809 GFX_COMP DRVL 4.7_1206_5% 0.36UH_PCMC104T-R36MN1R17_30A_20% +

PC811
6

TPCA8028_PSO8
220P_0402_50V7K 47P_0402_50V8J COMP PC808
18 LL=7m ohm

1GFX_SNB2
GFX_VCC 7 PGND 2.2U_0603_10V6K
2
GPU 2 OCP=26A
2GFX_COMP-1

PQ802
1 2 1 1 2 17 4
GFX_ILIM 8 AGND
VID:0.3~1.25V

CSCOMP
PR817 PC810 PR818 ILIM
33

CSREF
AGND Io(max)=22A

RAMP

LLINE

CSFB
1K_0402_1% 470P_0402_50V8J 20K_0402_1%

IREF

RPM
PC812

RT

3
2
1
680P_0603_50V7K

2
9

10

11

12

13

14

15

16
2
GFX_FB-1

PR819
10.7K_0402_1%
GFX_IREF

GFX_CSCOMP

GFX_CSCOMP
GFX_RAMP

GFX_CSFB
GFX_RT
2 GFX_RPM

GFX_CSREF
GFX_CSCOMP 1

PH801

GFX_CSCOMP-1
1 2
80.6K_0402_1%

237K_0402_1%

340K_0402_1%
2

2 220K_0402_5%_ERTJ0EV224J~D
PR820

Avoid high dV/dt

PR821

PR822

Place RTH1 close to inductor

PR826
71.5K_0402_1% on the same layer
1

2 1
422K_0402_1%
1

1
2

PR825

1
PR823 PR824

1
0_0402_5% 0_0402_5% PC814
560P_0402_50V7K PR827
2

PC813 165K_0402_1%
1

2
1000P_0402_50V7K

2
PR829 2 1 GFX_CSFB-1
1K_0402_1%
+GFX_B+ 2 1 GFX_RAMP-1 PR828
1

39K_0603_1%
PR831 PR830
B B
100_0402_1% 100_0402_1%

Connect to input caps

2

PC815 PC816
1000P_0402_50V7K 1000P_0402_50V7K
2

2
+GFX_CORE
8

8
VSS_AXG_SENSE

VCC_AXG_SENSE

Shortest the
net trace

PJ801
+GFX_COREP 2 1 +GFX_CORE
2 1
@ JUMP_43X118

PJ802
2 1
2 1
@ JUMP_43X118

(15A,600mils ,Via NO.= 30)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GFX_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 47 of 50
5 4 3 2 1
 8 7 6 5 4 3 2 1

8 PROC_DPRSLPVR HFM_VID HFM_Icc LL Icc_TDC Icc_Dyn

8 PSI#
Auburndale 45W 0.85 50 1.9m 37 35
H
8 H_VID6 H

8 H_VID5 Auburndale 35W 0.85 38 1.9m 29 27

8 H_VID4
PH0 PH1 # of PH
Clarksfield SV 0.95 52 1.9m 38 39
8 H_VID3 +5VS
8 H_VID2
0 0 1
Clarksfield XE 0.95 65 TBD 48 TBD
8 H_VID1
0 1 2

1
8 H_VID0 PR902
+CPU_B+ PL901
10_0603_5% 1 1 3
FBMA-L18-453215-900LMA90T_1812

2
2 1

499_0402_1%
34 VR_ON B+

2200P_0402_50V7K
0.1U_0603_25V7K
1
1
G G

10U_1206_25VAK

10U_1206_25VAK

68U_25V_M_R0.36
1

1
PC902 +

PC903
1U_0603_16V6K

PC904

PC905

PC906

PC907
+3VS

3212_DPRSLP 2

2
5
@ 2

PR911
+3VS

3212_VID0

3212_VID1

3212_VID2

3212_VID3

3212_VID4

3212_VID5

3212_VID6

3212_PSI#

3212_VCC
1

PR901 PQ902
1

3K_0402_5% 3K_0402_5% 3212_DRVH1 4 TPCA8030-H_SOP-ADV8-5

PR912

DCR=1.1mȍ ±7%

1
PU901

0_0402_5%
2

PR914 PL902

PR913
Layout note:

48

47

46

45

44

43

42

41

40

39

38

37
+CPU_CORE
0_0402_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
2

3
2
1
2 1 3212_CLK_EN# Boost Parts close 3212_SW1 1 4

VID0

VID1

VID2

VID3

VID4

VID5

VID6

PH0

PH1
PSI

VCC
DPRSLP
12 CLK_EN#
PR915
2
+VCCP 0_0402_5% PR917 PC908 2 3CSREF-1

4.7_1206_5%
5

1
2.2_0603_5% 0.1U_0603_25V7K

PR918
15,34 VGATE 2 1
3212_EN 1 36 3212_BST1 2 13212_BST1-1
2 1
1

1
F EN BST1 PQ903 F
PQ904 PR919
@ PR916 3212_PWRGD 2 35 3212_DRVH1 TPCA8028-H_SOP-ADVANCE8-5

1CPU_SNB1
10_0402_5%

2
0_0402_5% PWRGD DRVH1 3212_DRVL1 3212_DRVL1 TPCA8028-H_SOP-ADVANCE8-5
4 4
2

2
IMVP_IMON 3 34 3212_SW1
8 IMVP_IMON IMON SW1
2

680P_0603_50V8J
3
2
1

3
2
1

3212_CS_PH1
PR920 PC901 3212_CLK_EN# 3212_SWFB1
1 PR921 3212_CS_PH1

PC909
4 33 2
4.99K_0402_1% CLKEN SWFB1
0.082U_0402_16V7K
2

CSREF
100_0402_1%
1

2 1 3212_FBRTN 5 32 +5VS
FBRTN PVCC
PC910 PC912 150P_0402_50V8J 12P_0402_50V8J

1
1000P_0402_50V7K 3212_FB PC913 3212_DRVL1 +CPU_B+
1 2 6
FB DRVL1
31 Close IC
$'3015*B4)1B;
PC911
1

4.7U_0603_6.3V6M

2
PR922 PR923 7 30
1.65K_0402_1% 39.2K_0402_1% COMP PGND
2

E E
1 2 1 23212_COMP-1
1 23212_COMP

10U_1206_25VAK

10U_1206_25VAK
2200P_0402_50V7K
0.1U_0603_25V7K
2 13212_TRDET#
8 29 3212_DRVL2
VCCSENSE-1

5.11K_0402_1% TRDET DRVL2

1
PC914 PR924
150P_0402_50V8J PR925

@ PC916

PC917

PC918

PC915
+5VS 9 28 3212_SWFB2
1 2 3212_CS_PH2

2
VARFR SWFB2 100_0402_1%

3212_VRTT 10 27 3212_SW2 3212_DRVH2 4

VRTT SW2 PQ906
DCR=1.1mȍ ±7%
2

+3VS TPCA8030-H_SOP-ADV8-5
PR926 PR927 TTSENSE 11 26 3212_DRVH2 PL903
0_0402_5% 0_0402_5% TTSNS DRVH2 PC919 0.36UH_PCMC104T-R36MN1R17_30A_20%
PR929

3
2
1
0.1U_0603_25V7K 3212_SW2 1 4
1

12 25 3212_BST2 2 13212_BST2-2
2 1

4.7_1206_5%
1

GND BST2
@ PR928 3CSREF-2

PR931
2
CSCOMP

1
PR930 499_0402_1%
CSSUM

SWFB3
CSREF

PWM3
2.2_0603_5%
RAMP

LLINE

@ 0_0402_5% 49
IREF

RPM

OD3
ILIM

AGND PQ907
RT
2

1
3212_VRTT-1

D 2 1 Layout note: PQ908 D

5,34 H_PROCHOT#
TPCA8028-H_SOP-ADVANCE8-5

1CPU_SNB2
13212_IREF13

13212_RPM14

13212_RT 15

16

17

18

19

20

21

22

23

24

2
Boost Parts close
1 3212_RAMP

3212_DRVL2 4 3212_DRVL2 4 TPCA8028-H_SOP-ADVANCE8-5 PR932

2N7002W-T/R7_SOT323-3

10_0402_5%
1

D
@ PQ909

2
3212_ILIM

2 3212_VRTT

680P_0603_50V8J
3212_CSCOMP

3212_CSCOMP

3212_CS_PH2
PC920
G
3212_CSSUM
162K_0402_1%
80.6K_0402_1%

69.8K_0402_1%

3
2
1

3
2
1
S
3

PR933

PR934

PR935

Avoid high dV/dt

CSREF
+5VS
1
2

2
1

PR936 PR938
3212_RAMP-1 2

PR937 649K_0402_1% 1.91K_0402_1%

7.32K_0402_1% Connect to input caps
2
2

TTSENSE 2 PR939 1 Layout note:

C
+CPU_B+ LL=1.9m ohm C
1200P_0402_50V7K
1

1K_0402_1% Close to PHASE 1 OCP=60A

71.5K_0402_1%
390P_0402_50V7K
1

PC921
inductor on the same layer
1

PR940 @ 0.01U_0402_50V7K PH902 VID:0.8~0.85V

PR941
2

@ 0_0402_5% PC922
PC923

PC924

1000P_0402_50V7K 220K_0402_5%_ERTJ0EV224J~D Io(max)=48A

2

PR942
1TTSENSE-12

165K_0402_1%
CSREF 1 2 3212_CSCOMP-1

Layout note:
1

PC925 +VCCP
Close Phase 1 MOS 1U_0603_16V6K PR943 137K_0603_1%
@ PH901 2 1 3212_CS_PH1 H_VID0 2 1PR947 @ 1K_0402_5% H_VID0 2 1PR955 1K_0402_5%
2

100K +-1% NCP15WF104F03RC 0402

H_VID1 2 1PR948 @ 1K_0402_5% H_VID1 2 1PR956 1K_0402_5%
2 1 3212_CS_PH2
2

H_VID2 2 1PR949 1K_0402_5% H_VID2 2 1PR957 @ 1K_0402_5%

PR944 137K_0603_1%
B H_VID3 H_VID3 B
2 1PR950 @ 1K_0402_5% 2 1PR958 1K_0402_5%

PR945 H_VID4 2 1PR951 @ 1K_0402_5% H_VID4 2 1PR959 1K_0402_5%

100_0402_1%
2 1 +CPU_CORE H_VID5 2 1PR952 1K_0402_5% H_VID5 2 1PR960 @ 1K_0402_5%
Shortest the 0603 package
H_VID6 2 1PR953 @ 1K_0402_5% H_VID6 2 1PR961 1K_0402_5%
VCCSENSE net trace at least
VCCSENSE 8
PROC_DPRSLPVR 2 1PR954 10K_0402_5% PROC_DPRSLPVR 2 1PR962 @ 1K_0402_5%

VSSSENSE
VSSSENSE 8
Auburndale SV: VID(0-5):001001
2 1
ULV: VID(0-5):001010
PR946
100_0402_1%
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title
Layout note: CPU_CORE
Close CPU pin THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 08, 2010 Sheet 48 of 50
8 7 6 5 4 3 2 1
 5 4 3 2 1

9HUVLRQFKDQJHOLVW 3,5/LVW 3DJHRI

IRU3:5
,WHP 5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH

D
 Add S3_0.75V_EN for 0.75 enable singal 44 Add PR523 and reserve PR521 11/09 Before A D

Reserve PR615, PR617, PR618 and PC617

 Modify VGA GPIO table for NVIDIA SPEC. 45
PR612, PR613 change to 84.5K from 100K
11/09 Before A


C C



B B












A
 20081022 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/06 Deciphered Date 2009/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
<Doc>
Date: Thursday, April 08, 2010 Sheet 49 of 50
5 4 3 2 1
 5 4 3 2 1

OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!QVSQPTF OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!QVSQPTF
........................................................................ ..................................................................................
WFS/!S1`2141
2 41 SK56!DPOOFDUPS 2 QWU 35 IENJ!dpoofdups!dibohf!up!EJQ!uzqf EGC!sfrvftu
3 46 LC!Nbusjy!dibohf 3 QWU 39 S447!dibohf!up!211Lpin CPN!fssps
4 42 FND2514.2!dibohf!up!FND2514.3 4 QWU 49 E24-E25!dibohf!up!qbokju dptu!epxo
5 51-53 QPXFS!npejgz!QR424-QV213 5 QWU 49 SH5-SH6!dibhof!67l!pin SD!gjmufs!gps!H.tfotps!pvuqvu-!FD!sfrvftu/

D
6 dibohf!VTC!qpsu!!!!!!!!GQ!!;!qpsu21 6 QWU 48 KCU2!dibohf!up!7!qjo Gps!7!qjo!CU!npevmf
D
7 !!!!!!!!!!!!!!!!!!!!!!VTC4!;!qpsu!: 7 QWU 45 TVTDML!dpoofdu!up!dmpdl!pvu FD!jttvfe!dibohf!opuf/
dibohf!VTC!qpxfs!!!!
8 8 QWU 45 S:89!56!up!1!pin Gps!FDSPN!dbo(u!gmbti
2213E!NPEJGZ 9 QWU 45 Bee!R74!3O8113-!S455!21L VTC!Qpxfs!qvmtf!xifo!BD!jo-!cvh
: QWU 45 Bee!ofu!DMLSVO$!po!qjo49 sftfswf!gps!qpxfs!tbwjoh
9 44 Bee!!SB8-DB24 GPS!FTE 21 QWU 45 43/879LI{!dibohf!up!81y26y2/5 dptu!epxo
: 46 Bee!!E33 22 QWU 24 43/879LI{!dibohf!up!81y26y2/5 dptu!epxo
21 49 KGJS!DPOO/!DIBOHF!UP!23!QJO 23 QWU 44 JOU`NJD`DML!bee!DB29!211qG!dbq/ FNJ!sfrvftu
22 47 DIBOHF!OFU!OBNF 24 QWU 44 Bvejp!qjo5!bee!E8 Sfbmufl!dibohf!opuf!gps!cvh
23 38 KMWET2!DPOO/!QJO!TXBQ/ 25 QWU 39 Bee!R56!3O8113 Gps!Xjnby!MFE!op!gvodujpo-!cvh
24 24 EFM!DMSQ2 26 QWU 38 dibohf!V53!up!TU dptu!epxo
25 2215ENPEJGZ 27 QWU 38 Bee!R75-R48-S551 dptu!epxo-!fobcmf!clm!djsdvju
26 27 Bee!!V26-S284-S288-S289-S738-S739 28 QWU 37 Bee!S433-S439!1!pin Gps!#opo.QoQ!efwjdf#!cvh
27 2216ENPEJGZ 29 QWU 33 Bee!S585!45/9L!pin O.wjejb!O22N.MQ2!efwjdf!JE
28 39 Bee!!R55-R56-R5:-R66-R71-R73-S447 2: QWU 2: M8-M9-M28-M29!dibohf!up!1!pin gps!FEJE!dbo(u!efufdu!tpnfujnf-!dptu!epxo
C
29 37 Bee!!R72-R74 31 QWU 28 S319!dibohf!up!2!pin DSU!hbscfhf!jo!vnb!npef C

2: 3: S837!dibohf!up!1916 32 QWU 27 S691!bee!1!pin gps!cvh-!vnb!txjudi!up!ejt!xjmm!iboh!vq

31 36 Bee!S66: 33 QWU 26 S286!3/3l!up!5/8l!pin dpnnpo!eftjho!vqebuf
32 26 Bee!S291 34 QWU 23 Z2!25/429NI{!dibohf!up!6143!tj{f dpnnpo!eftjho
33 25 Bee!U35!QBE-U36!QBE 35 QWU 1: D86-D87-D:3-D275!dibohf!up!444vG!7n!pin dptu!epxo
34 9 Bee!S393 36 QWU Y R5-RH2-R43-R44-R84-R85-R86-R:8!dibohf!up!BP4524 dptu!epxo
35 25 Bee!S438-S436-U32!QBE 37 QWU 45 Bee!S456!21Lpin FD`UBDI!qvmm!vq
221:ENPEJGZ
OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!QVSQPTF
36 25 Efm!S92-S94 ..................................................................................
37 27 Bee!U37!QBE-D798 2 TWU 4: Bee!S679-!R51 ,1/86WT!ejtdibshf
38 38 Bee!S482-S483 3 TWU 4: Bee!S784!21L ,2/6W!FO!qjo!qvmm!epxo
39 45 Efm!R37-S414!U32QBE 4 TWU 4: Dibohf!V44!up!Mpx!Set.po!uzqf WSBN!wpmubhf!espq
Bee!S341-R28 5 TWU 48 Bee!FNJ!dpnnpo!dipdl!po!VTC!q2-q1<M49-M4: FNJ
3: 37 Efm!R72-R74!!Bee!R::B-R::C 6 TWU 45 DMLSVO$!qvmm!epxo-!S782!21L dpnnpo!eftjho
6 Bee!R72-S527 7 TWU 45 Sftfswf!S796!gps!XMBO`MFE!cz!FD!dpouspm XMBO!MFE
B B

KGJS!DPOO!dibohf!KMFE!DPOO 8 TWU 44 BMD36:!dibohf!up!WC Wfstjpo!dibohf

45 bee!UQ3:-S431-S439-S341 9 TWU 3: efm!S765!mfblbhf mfblbhf
: TWU 39 XMBO!MFE!dpouspm!dibohf!up!EUM!BOE!hbuf Gps!tpnf!dbse!eftjho
21 TWU 38 Bee!V7-V28-V29-V2:!gps!CLM!boe!QXN!dpouspm tjhobm!tfmfdu!txjudi
22 TWU 38 Bee!S481!791pin tvqqpsu!Op!dpmps!fohjof!qbofm
23 TWU 38 Bee!E47 MDFWEE!ejtdibshf
24 TWU 37 Sftfswf!DSU!epvcmf!qj!gjmufs Wjejp!Gjmufs
25 TWU 36 Bee!S781!3/3L IENJ!dpnnpo!eftjho
26 TWU 26-36 Bee!S786-S785!211L Izcsje!npef!ejtbcmf!QDI!IENJ
27 TWU 28 D616-D5:3!dibohf!tj{f!1714 NF!efnfoe
28 TWU 28 D558!dibohf!up!2vG dpnnpo!eftjho
OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!QVSQPTF 29 TWU 24 Bee!S788 IEB!TEJO2
.................................................................................. 2: TWU 9 Dibohf!S379!up!58L ujnjoh
A 2 NQ 26 Bee!S798-S799 Joufm!EH 31 TWU 9 Bee!S662!2L QTJ$!qvmm!epxo-!tusjq!qjo A

3 NQ 4: Bee!S6-!Efm!S5 T6!qpxfs!mptu 32 TWU 6 D449!dibohf!up!1/158vG dpnnpo!eftjho-!T4!tivuepxo

33 TWU 6 S246!sfnpwf xbsn!cppu!jttvf
34 TWU 23 Bee!D476 21qG!gps!SG
35 TWU 25 Bee!S524-D54:!33pin-21qG Gps!SG Title

HW PIR
Size Document Number Rev
A3 LA-5941P 0.3

Date: Thursday, April 08, 2010 Sheet 50 of 50

5 4 3 2 1
www.s-manuals.com