MEL G642: VLSI

Architecture

Feedback on controller design Level 2 flowchart for all instructions

Flowchart to control word

 Feedback on Controller Design
Instruction Set summary
Instruction Format

Operation First Second Second

Code Operand Operand Operand
Reg Address Reg
Mode
 K- Operands

 a - addressing modes

 If any addressing mode is valid for any instruction, we will have k*a instructions
 Addressing
mode

Address mode sequences do

address calculations, fetch
operand and place in Di
Level 1 Flowcharts  Level 2 Flowcharts

Reduce the number of states from 42 to 35

If we can not able to reduce the number of states as per our expectation, we may
explore the possibility of improving execution unit.
 Adding more information to Level 2 Flowcharts
To make easier to use and easier for translating flowchart to hardware, we
will add more description to level 2 flowchart

Label A Label B

Access Type

TASKS ALU and CC

duplicates

Page & Location

State ID Synonym Access width Next state

Level 2 Flowcharts with added information
Level 2 Flowcharts with added information
Level 2 Flowcharts with added information
Identifying duplicate states in Level 2 Flowcharts
Identifying duplicate states in Level 2 Flowcharts
Eliminate the duplicate states at the end of sequences
by specifying a direct branch to common sequences.
 BZ

edb  irf ir
add-n
ry  a  alu,ao
+1  alu
brzz1 bc

Z=1 Z=0

na ir
irf  ire x-n edb  irf add-n
t1  a  pc pc  a  alu, ao
+1  alu
brzz2 ib brzz3 brzz4
na
irf  ire x-n
t1  b  pc
brzz4 ib
 BZ

edb  irf ir
add-n
ry  a  alu,ao
+1  alu
brzz1 bc

Z=1 Z=0

na ir
irf  ire x-n edb  irf add-n
t1  a  pc pc  a  alu, ao
+1  alu
brzz2 ib brzz3 brzz2
MEM RX LOAD RY  RX LOAD

di  b  rx, t2 ir edb  irf ir

edb  irf add-x pc  a  alu , ao add-n

pc  a  alu , ao ry  b  rx, t2
+1  alu +1  alu
ldrm1 ldrm2 ldrr1 ldrr2
irf  ire na irf  ire na
t1  b  pc add-s t1  b  pc add-s
t2  a  alu t2  a  alu
0  alu 0  alu
ib ldrr2 ib
ldrm2

RY  RX LOAD
edb  irf ir
pc  a  alu , ao add-n
ry  b  rx, t2
+1  alu
ldrr1 ldrm2
RY  RX STORE
edb  irf ir
pc  a  alu , ao add-x
RY  RX STORE
rx  b  ry, t2
+1  alu edb  irf ir
strr1 strr2 pc  a  alu , ao add-x
irf  ire na rx  b  ry, t2
t1  b  pc add-s +1  alu
strr1 ldrm2
t2  a  alu
0  alu
strr2 ib
RX MEM STORE
RX MEM STORE
rx  a  alu, do dw
t2  b  ao add-s rx  a  alu, do dw
0  alu t2  b  ao add-s
0  alu
strm1 strm2
ir strm1 brzz3
edb  irf
pc  a  alu , ao add-n
+1  alu
strm2 strm3
na
irf  ire x-n
t1  b  pc

strm3 ib
RX OP RY RY ADD,AND,SUB RX OP RY RY ADD,AND,SUB
na na
rx  a  alu op-s rx  a  alu op-s
ry  b  alu ry  b  alu
oprr1 oprr2 oprr1 oprr2
edb  irf ir edb  irf ir
pc  a  alu , ao add-n pc  a  alu , ao add-n
t1  b  ry t1  b  ry
+1  alu +1  alu
oprr2 oprr3 oprr2 brzz2
na
irf  ire x-n
t1  b  pc

oprr3 ib
RX OP MEM MEM ADD,AND,SUB RX OP MEM MEM ADD,AND,SUB
na na
di  b  alu op-s di  b  alu op-s
rx  a  alu rx  a  alu
oprm1 oprm2 oprm1 oprm2
dw dw
t1  a  do x-n t1  a  do x-n
t2  b  ao t2  b  ao
oprm2 oprm3 oprm2 brzz3
edb  irf ir
add-n
pc  a  alu,ao
+1  alu
oprm3 oprm4
na
irf  ire x-n
t1  b  pc
oprm4 ib
MEM  ALU TEST MEM  ALU TEST
di  b  t2 ir
di  b  t2 ir
edb  irf add-x
edb  irf add-x
pc  a  alu,ao pc  a  alu,ao
+1  alu +1  alu
test1 test2 test1 ldrm2
irf  ire na
t1  b  pc add-s
t2  a  alu
0  alu
test2 ib
Level 2 Flowcharts after elimination of duplicate states
Level 2 Flowcharts after elimination of duplicate states
Level 2 Flowcharts after elimination of duplicate states
 Level 1 Flowcharts  Level 2 Flowcharts

Reduce the number of states from 42 to 35

After the Elimination of the duplicate states in Level 2

Reduced the number of states to 22

Implementing from Flowchart
 Implementing Flowcharts
 How to convert flow charts in to Control Words ?

control fields

OP TY NA
Execution unit control Control store Next
Address Address
Select

State sequencer Control

Control Fields: Small fields of bits which are decoded to drive

control lines in the execution unit and the controller
Control Store Address Select: Next Address type BC, DB, IB, SB

Next (State) Address: DB

 Implementing Flowcharts
 How to convert flow charts in to Control Words ?

control fields

OP TY NA
Execution unit control Control store Next
Address Address
Select
bits
State sequencer Control

RX MEM STORE

rx  a  alu, do dw
t2  b  ao add-s
0  alu
Transform all the states
strm1 brzz3 into control word bit
Location of patterns
Control Word
 Implementing Flowcharts
 How to convert flow charts in to Control Words ?

control fields

OP TY NA
Execution unit control Control store Next
Address Address
Select

State sequencer Control

Control Fields: Small fields of bits which are decoded to drive

control lines in the execution unit and the controller
Control Store Address Select: Next Address type BC, DB, IB, SB

Next (State) Address: DB

TY Field

Control Store Address Select: Next Address type BC, DB, IB, SB

BC : Branch conditionally
NA modified by condition code from EU

DB: Direct Branch

Next control store address is NA

IB: Instruction branch- next control store address is from the

control word decoders using IRE (for next instruction)

SB: Sequence Branch : Next control store address is from

control word decoders using IRE (for next sequence)
Can you identify DB, BC, IB, SB??
 Implementing Flowcharts
 Block Diagram
Control
Word Instruction  Instruction
Flowchart Address
State Address Mode  Execution
Control Word

Instruction
 Addressing
mode

Address mode sequences do

address calculations, fetch
operand and place in Di
Instruction decoders: It translate
instruction bit pattern to control
store address. For MIN two
decoders needed.
First decoder translates the
instruction into address mode
sequence (IB decoder)
Second decoder translates
the instruction into Execution
sequence (SB decoder)
If no address mode, then
IB decoder points to
execution sequence
Instructions without address mode seq do not use SB decoder
What will be IB instruction decoder address
output

abdm1

What will be SB instruction decoder output.

oprm1
Assume two instructed need to be executed are

POP

ADD RX (RY+d)@

Can U write the following

Instruction Control Next IB SB

word control Instruction Instruction
sequence word Decoder Decoder
address
Instruction Control Next IB SB
word control Instruction Instruction
sequence word Decoder Decoder
address
POP popr1 popr2
popr2 brzz3
brzz3 brzz2
brzz2 - abdm1 oprm1
ADD RX (RY+d)@ abdm1 abdm2 oprm1
abdm2 abdm3 oprm1
abdm3 abdm4 oprm1
abdm4 - oprm1
oprm1 oprm2
oprm2 brzz3
brzz3 brzz2
brzz2 oprr1