Pic18F6390/6490/8390/8490 Data Sheet: 64/80-Pin Flash Microcontrollers With LCD Driver and Nanowatt Technology

PIC18F6390/6490/8390/8490
Data Sheet
64/80-Pin Flash Microcontrollers
with LCD Driver and nanoWatt Technology
© 2007 Microchip Technology Inc. DS39629C

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DS39629C-page ii © 2007 Microchip Technology Inc.

PIC18F6390/6490/8390/8490
64/80-Pin Flash Microcontrollers with LCD Driver
and nanoWatt Technology
LCD Driver Module Features: Peripheral Highlights:
• Direct Driving of LCD Panel • High-Current Sink/Source 25 mA/25 mA
• Up to 48 Segments: Software Selectable • Four External Interrupts
• Programmable LCD Timing module: • Four Input Change Interrupts
- Multiple LCD timing sources available • Four 8-Bit/16-Bit Timer/Counter modules
- Up to 4 commons: Static, 1/2, 1/3 or 1/4 multiplex • Real-Time Clock (RTC) Software module:
- Static, 1/2 or 1/3 bias configuration - Configurable 24-hour clock, calendar, automatic
100-year or 12800-year, day-of-week calculator
• Can drive LCD Panel while in Sleep mode
- Uses Timer1
Power-Managed Modes: • Up to 2 Capture/Compare/PWM (CCP) modules
• Master Synchronous Serial Port (MSSP) module
• Run: CPU On, Peripherals On supporting 3-Wire SPI (all 4 modes) and I2C™
• Idle: CPU Off, Peripherals On Master and Slave modes
• Sleep: CPU Off, Peripherals Off • Addressable USART module:
• Run mode Currents Down to 14.0 μA Typical - Supports RS-485 and RS-232
• Idle mode Currents Down to 5.8 μA Typical • Enhanced Addressable USART module:
• Sleep Current Down to 0.1 μA Typical - Supports RS-485, RS-232 and LIN 1.2
• Timer1 Oscillator: 1.8 μA, 32 kHz, 2V - Auto-wake-up on Start bit
• Watchdog Timer: 2.1 μA - Auto-Baud Detect
• Two-Speed Oscillator Start-up • 10-Bit, up to 12-Channel Analog-to-Digital (A/D)
Converter module:
Flexible Oscillator Structure: - Auto-acquisition capability
- Conversion available during Sleep
• Four Crystal modes:
• Dual Analog Comparators with Input Multiplexing
- LP: up to 200 kHz
- XT: up to 4 MHz Special Microcontroller Features:
- HS: up to 40 MHz
• C Compiler Optimized Architecture:
- HSPLL: 4-10 MHz (16-40 MHz internal)
- Optional extended instruction set designed to
• 4x Phase Lock Loop (available for crystal and optimize re-entrant code
internal oscillators) • 1000 Erase/Write Cycle Flash Program Memory Typical
• Two External RC modes, up to 4 MHz • Flash Retention: 100 Years Typical
• Two External Clock modes, up to 40 MHz • Priority Levels for Interrupts
• Internal Oscillator Block: • 8 x 8 Single-Cycle Hardware Multiplier
- 8 user-selectable frequencies, from 31 kHz to 8 MHz • Extended Watchdog Timer (WDT):
- Provides a complete range of clock speeds - Programmable period from 4 ms to 132s
from 31 kHz to 32 MHz when used with PLL - 2% stability over VDD and temperature
- User-tunable to compensate for frequency drift • In-Circuit Serial Programming™ (ICSP™) via Two Pins
• Secondary Oscillator using Timer1 @ 32 kHz • In-Circuit Debug (ICD) via Two Pins
• Fail-Safe Clock Monitor: • Wide Operating Voltage Range: 2.0V to 5.5V
- Allows for safe shut down of device if primary
or secondary clock fails
Data
EUSART/
Program Memory MSSP

AUSART
Memory LCD 10-Bit CCP Timers

Device I/O Comparators
Flash # Single-Word SRAM (pixel) A/D (ch) (PWM) Master 8/16-Bit
SPI
(bytes) Instructions (bytes) I2C™
PIC18F6390 8K 4096 768 50 128 12 2 Y Y 1/1 2 1/3
PIC18F6490 16K 8192 768 50 128 12 2 Y Y 1/1 2 1/3
PIC18F8390 8K 4096 768 66 192 12 2 Y Y 1/1 2 1/3
PIC18F8490 16K 8192 768 66 192 12 2 Y Y 1/1 2 1/3
© 2007 Microchip Technology Inc. DS39629C-page 1

PIC18F6390/6490/8390/8490
Pin Diagrams
64-Pin TQFP
RE7/CCP2(1)/SEG31
RE4/COM1
RE5/COM2
RE6/COM3
RD0/SEG0
RD1/SEG1
RD2/SEG2
RD3/SEG3
RD4/SEG4
RD5/SEG5
RD6/SEG6
RD7/SEG7
LCDBIAS3
COM0
VDD
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
LCDBIAS2 1 48 RB0/INT0
LCDBIAS1 2 47 RB1/INT1/SEG8
RG0/SEG30 3 46 RB2/INT2/SEG9
RG1/TX2/CK2/SEG29 4 45 RB3/INT3/SEG10
RG2/RX2/DT2/SEG28 5 44 RB4/KBI0/SEG11
RG3/SEG27 6 43 RB5/KBI1
MCLR/VPP/RG5 RB6/KBI2/PGC
7 PIC18F6390 42
RG4/SEG26 8 41 VSS
VSS 9
PIC18F6490 40 OSC2/CLKO/RA6
VDD 10 39 OSC1/CLKI/RA7
RF7/SS/SEG25 11 38 VDD
RF6/AN11/SEG24 12 37 RB7/KBI3/PGD
RF5/AN10/CVREF/SEG23 13 36 RC5/SDO/SEG12
RF4/AN9/SEG22 14 35 RC4/SDI/SDA
RF3/AN8/SEG21 15 34 RC3/SCK/SCL
RF2/AN7/C1OUT/SEG20 33 RC2/CCP1/SEG13
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1/AN6/C2OUT/SEG19
RF0/AN5/SEG18
RA3/AN3/VREF+/SEG17
RA2/AN2/VREF-/SEG16
RA5/AN4/HLVDIN/SEG15
RC0/T1OSO/T13CKI
RC6/TX1/CK1
RC7/RX1/DT1
AVSS
VSS
AVDD
RA1/AN1
RA0/AN0
VDD
RA4/T0CKI/SEG14
RC1/T1OSI/CCP2(1)
Note 1: RE7 is the alternate pin for CCP2 multiplexing.
DS39629C-page 2 © 2007 Microchip Technology Inc.

PIC18F6390/6490/8390/8490
Pin Diagrams (Continued)
80-Pin TQFP
RE7/CCP2(1)/SEG31
RH0/SEG47
RH1/SEG46
RJ0/SEG32
RJ1/SEG33
RE4/COM1
RE5/COM2
RE6/COM3
RD0/SEG0
RD1/SEG1
RD2/SEG2
RD3/SEG3
RD4/SEG4
RD5/SEG5
RD6/SEG6
RD7/SEG7
LCDBIAS3
COM0
VDD
VSS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/SEG45 1 60 RJ2/SEG34
LCDBIAS2 3 58 RB0/INT0
LCDBIAS1 4 57 RB1/INT1/SEG8
RG0/SEG30 5 56 RB2/INT2/SEG9
RG1/TX2/CK2/SEG29 6 55 RB3/INT3/SEG10
RG2/RX2/DT2/SEG28 7 54 RB4/KBI0/SEG11
RG3/SEG27 8 53 RB5/KBI1
MCLR/VPP/RG5 9 52 RB6/KBI2/PGC
RG4/SEG26 PIC18F8390 51 VSS
10
VSS 11 PIC18F8490 50 OSC2/CLKO/RA6
VDD 12 49 OSC1/CLKI/RA7
RF7/SS/SEG25 13 48 VDD
RF6/AN11/SEG24 14 47 RB7/KBI3/PGD
RF5/AN10/CVREF/SEG23 15 46 RC5/SDO/SEG12
RF4/AN9/SEG22 16 45 RC4/SDI/SDA
RF3/AN8/SEG21 17 44 RC3/SCK/SCL
RF2/AN7/C1OUT/SEG20 43 RC2/CCP1/SEG13
18
RH6/SEG42 41 RJ6/SEG37
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RF1/AN6/C2OUT/SEG19
RF0/AN5/SEG18
RJ4/SEG39
RJ5/SEG38
RC1/T1OSI/CCP2(1)
RA3/AN3/VREF+/SEG17
RA2/AN2/VREF-/SEG16
RC6/TX1/CK1
RC7/RX1/DT1
RC0/T1OSO/T13CKI
RH5/SEG41
RH4/SEG40
AVSS
VSS
AVDD
RA1/AN1
RA0/AN0
VDD
RA4/T0CKI/SEG14
Note 1: RE7 is the alternate pin for CCP2 multiplexing.

PIC18F6390/6490/8390/8490
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 31
3.0 Power-Managed Modes ............................................................................................................................................................. 41
4.0 Reset .......................................................................................................................................................................................... 51
5.0 Memory Organization ................................................................................................................................................................. 65
6.0 Flash Program Memory .............................................................................................................................................................. 87
7.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 91
8.0 Interrupts .................................................................................................................................................................................... 93
9.0 I/O Ports ................................................................................................................................................................................... 109
10.0 Timer0 Module ......................................................................................................................................................................... 131
11.0 Timer1 Module ......................................................................................................................................................................... 135
12.0 Timer2 Module ......................................................................................................................................................................... 141
13.0 Timer3 Module ......................................................................................................................................................................... 143
14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 147
15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 157
16.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 197
17.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 217
18.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 231
19.0 Comparator Module.................................................................................................................................................................. 241
20.0 Comparator Voltage Reference Module ................................................................................................................................... 247
21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 251
22.0 Liquid Crystal Display (LCD) Driver Module ............................................................................................................................. 257
23.0 Special Features of the CPU .................................................................................................................................................... 281
24.0 Instruction Set Summary .......................................................................................................................................................... 295
25.0 Development Support............................................................................................................................................................... 345
26.0 Electrical Characteristics .......................................................................................................................................................... 349
27.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 387
28.0 Packaging Information.............................................................................................................................................................. 389
Appendix A: Revision History............................................................................................................................................................. 395
Appendix B: Device Differences......................................................................................................................................................... 395
Appendix C: Conversion Considerations ........................................................................................................................................... 396
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 396
Appendix E: migration from Mid-Range to Enhanced Devices .......................................................................................................... 397
Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 397
Index .................................................................................................................................................................................................. 399
The Microchip Web Site ..................................................................................................................................................................... 409
Customer Change Notification Service .............................................................................................................................................. 409
Customer Support .............................................................................................................................................................................. 409
Reader Response .............................................................................................................................................................................. 410
PIC18F6390/6490/8390/8490 Product Identification System ............................................................................................................ 411

PIC18F6390/6490/8390/8490
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PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
1.0 DEVICE OVERVIEW 1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
This document contains device-specific information for
the following devices: All of the devices in the PIC18F6390/6490/8390/8490
family offer ten different oscillator options, allowing
• PIC18F6390 • PIC18F8390 users a wide range of choices in developing application
• PIC18F6490 • PIC18F8490 hardware. These include:
This family offers the advantages of all PIC18 • Four Crystal modes using crystals or ceramic
microcontrollers – namely, high computational resonators.
performance at an economical price. In addition to • Two External Clock modes offering the option of
these features, the PIC18F6390/6490/8390/8490 using two pins (oscillator input and a divide-by-4
family introduces design enhancements that make clock output) or one pin (oscillator input, with the
these microcontrollers a logical choice for many second pin reassigned as general I/O).
high-performance, power-sensitive applications. • Two External RC Oscillator modes with the same
pin options as the External Clock modes.
1.1 New Core Features • An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC
1.1.1 nanoWatt TECHNOLOGY source (approximately 31 kHz, stable over
All of the devices in the PIC18F6390/6490/8390/8490 temperature and VDD), as well as a range of six
family incorporate a range of features that can user-selectable clock frequencies between
significantly reduce power consumption during 125 kHz to 4 MHz for a total of eight clock
operation. Key items include: frequencies. This option frees the two oscillator
pins for use as additional general purpose I/O.
• Alternate Run Modes: By clocking the controller
• A Phase Lock Loop (PLL) frequency multiplier,
from the Timer1 source or the internal oscillator
available to both the High-Speed Crystal and
block, power consumption during code execution
Internal Oscillator modes, which allows clock
can be reduced by as much as 90%.
speeds of up to 40 MHz. Used with the internal
• Multiple Idle Modes: The controller can also run oscillator, the PLL gives users a complete
with its CPU core disabled, but the peripherals still selection of clock speeds from 31 kHz to
active. In these states, power consumption can be 32 MHz – all without using an external crystal or
reduced even further – to as little as 4% of normal clock circuit.
operation requirements.
Besides its availability as a clock source, the internal
• On-the-Fly Mode Switching: The
oscillator block provides a stable reference source that
power-managed modes are invoked by user code
gives the family additional features for robust
during operation, allowing the user to incorporate
operation:
power-saving ideas into their application’s
software design. • Fail-Safe Clock Monitor: This option constantly
• Lower Consumption in Key Modules: The monitors the main clock source against a
power requirements for both Timer1 and the reference signal provided by the internal
Watchdog Timer have been reduced by up to oscillator. If a clock failure occurs, the controller is
80%, with typical values of 1.1 μA and 2.1 μA, switched to the internal oscillator block, allowing
respectively. for continued low-speed operation or a safe
application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset or wake-up from Sleep
mode until the primary clock source is available.

PIC18F6390/6490/8390/8490
1.2 Other Special Features 1.3 Details on Individual Family
• Memory Endurance: The Flash cells for program
Members
memory are rated to last for approximately a Devices in the PIC18F6390/6490/8390/8490 family are
thousand erase/write cycles. Data retention available in 64-pin (PIC18F6X90) and 80-pin
without refresh is conservatively estimated to be (PIC18F8X90) packages. Block diagrams for the two
greater than 100 years. groups are shown in Figure 1-1 and Figure 1-2,
• Extended Instruction Set: The respectively.
PIC18F6390/6490/8390/8490 family introduces The devices are differentiated from each other in three
an optional extension to the PIC18 instruction set, ways:
which adds 8 new instructions and an Indexed
Addressing mode. This extension, enabled as a 1. I/O Ports: 7 bidirectional ports on 64-pin
device configuration option, has been specifically devices; 9 bidirectional ports on 80-pin devices.
designed to optimize re-entrant application code 2. LCD Pixels: 128 (32 SEGs x 4 COMs) pixels can
originally developed in high-level languages such be driven by 64-pin devices; 192 (48 SEGs x
as C. 4 COMs) pixels can be driven by 80-pin devices.
• Enhanced Addressable USART: This serial 3. Flash Program Memory: 8 Kbytes for
communication module is capable of standard PIC18FX390 devices; 16 Kbytes for PIC18FX490.
RS-232 operation and provides support for the LIN All other features for devices in this family are identical.
bus protocol. Other enhancements include These are summarized in Table 1-1.
Automatic Baud Rate Detection and a 16-bit Baud
Rate Generator for improved resolution. When the The pinouts for all devices are listed in Table 1-2 and
microcontroller is using the internal oscillator Table 1-3.
block, the EUSART provides stable operation for Like all Microchip PIC18 devices, members of the
applications that talk to the outside world, without PIC18F6390/6490/8390/8490 family are available as
using an external crystal (or its accompanying both standard and low-voltage devices. Standard
power requirement). devices with Flash memory, designated with an “F” in
• 10-Bit A/D Converter: This module incorporates the part number (such as PIC18F6390), accommodate
programmable acquisition time, allowing for a an operating VDD range of 4.2V to 5.5V. Low-voltage
channel to be selected and a conversion to be parts, designated by “LF” (such as PIC18LF6490),
initiated without waiting for a sampling period and function over an extended VDD range of 2.0V to 5.5V.
thus, reduces code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing a time-out range from 4 ms to over
10 minutes that is stable across operating voltage
and temperature.

PIC18F6390/6490/8390/8490
TABLE 1-1: DEVICE FEATURES
Features PIC18F6390 PIC18F6490 PIC18F8390 PIC18F8490
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 8K 16K 8K 16K
Program Memory (Instructions) 4096 8192 4096 8192
Data Memory (Bytes) 768 768 768 768
Interrupt Sources 22 22 22 22
I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G F, G F, G, H, J F, G, H, J
Number of Pixels the LCD Driver 128 (32 SEGs x 128 (32 SEGs x 192 (48 SEGs x 192 (48 SEGs x
can Drive 4 COMs) 4 COMs) 4 COMs) 4 COMs)
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications MSSP, AUSART MSSP, AUSART MSSP, AUSART MSSP, AUSART
Enhanced USART Enhanced USART Enhanced USART Enhanced USART
10-Bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels
Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR,
RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction,
Stack Full, Stack Full, Stack Full, Stack Full,
Stack Underflow Stack Underflow Stack Underflow Stack Underflow
(PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST),
MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional),
WDT WDT WDT WDT
Programmable Low-Voltage Detect Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions; 75 Instructions; 75 Instructions; 75 Instructions;
83 with Extended 83 with Extended 83 with Extended 83 with Extended
Instruction Set Instruction Set Instruction Set Instruction Set
Enabled Enabled Enabled Enabled
Packages 64-Pin TQFP 64-Pin TQFP 80-Pin TQFP 80-Pin TQFP

PIC18F6390/6490/8390/8490
FIGURE 1-1: PIC18F6X90 (64-PIN) BLOCK DIAGRAM
Data Bus<8> PORTA
Table Pointer<21> RA0/AN0
RA1/AN1
Data Latch RA2/AN2/VREF-/SEG16
inc/dec logic 8 8
RA3/AN3/VREF+/SEG17
Data Memory
RA4/T0CKI/SEG14
PCLATU PCLATH (3.9 Kbytes) RA5/AN4/HLVDIN/SEG15
21
Address Latch OSC2/CLKO(3)/RA6
20
PCU PCH PCL OSC1/CLKI(3)/RA7
Program Counter 12 PORTB
Data Address<12> RB0/INT0
RB1/INT1/SEG8
31 Level Stack RB2/INT2/SEG9
Address Latch 4 12 4 RB3/INT3/SEG10
BSR FSR0 Access RB4/KBI0/SEG11
Program Memory STKPTR Bank
(48/64 Kbytes) FSR1 RB5/KBI1
FSR2 RB6/KBI2/PGC
Data Latch 12
RB7/KBI3/PGD
inc/dec PORTC
8 logic
Table Latch RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/SEG13
ROM Latch
Address RC3/SCK/SCL
Instruction Bus <16> Decode RC4/SDI/SDA
RC5/SDO/SEG12
IR RC6/TX1/CK1
RC7/RX1/DT1
8 PORTD
Instruction State Machine
Decode and Control Signals
Control RD7/SEG7:RD0/SEG0
PRODH PRODL
8 x 8 Multiply
3
8 PORTE
LCDBIAS1
BITOP W LCDBIAS2
8 8
8 LCDBIAS3
Internal COM0
OSC1(3) Power-up 8 RE4/COM1
Oscillator 8
Block Timer RE5/COM2
(3) Oscillator RE6/COM3
OSC2 ALU<8>
INTRC Start-up Timer RE7/CCP2(1)/SEG31
T1OSI Oscillator Power-on 8
Reset PORTF
8 MHz RF0/AN5/SEG18
T1OSO Oscillator Watchdog RF1/AN6/C2OUT/SEG19
Timer
Precision RF2/AN7/C1OUT/SEG20
Single-Supply Brown-out Band Gap RF3/AN8/SEG21
MCLR(2)
Programming Reset Reference RF4/AN9/SEG22
In-Circuit Fail-Safe RF5/AN10/CVREF/SEG23
VDD, VSS Debugger Clock Monitor RF6/AN11/SEG24
RF7/SS/SEG25
PORTG
BOR ADC
Timer0 Timer1 Timer2 Timer3 RG0/SEG30
HLVD 10-Bit RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28
RG3/SEG27
RG4/SEG26
MCLR/VPP/RG5(2)
Comparators CCP1 CCP2 MSSP EUSART1 AUSART2 LCD

Driver
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RE7 when CCP2MX is not set.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.

PIC18F6390/6490/8390/8490
FIGURE 1-2: PIC18F8X90 (80-PIN) BLOCK DIAGRAM
PORTA
Data Bus<8> RA0/AN0
Table Pointer<21> RA1/AN1
RA2/AN2/VREF-/SEG16
Data Latch RA3/AN3/VREF+/SEG17
inc/dec logic 8 8
RA4/T0CKI/SEG14
Data Memory
(3.9 Kbytes)
21 PCLATU PCLATH OSC2/CLKO(3)/RA6
20 Address Latch OSC1/CLKI(3)/RA7
PCU PCH PCL PORTB
Program Counter RB0/INT0
12
RB1/INT1/SEG8
Data Address<12> RB2/INT2/SEG9
31 Level Stack RB3/INT3/SEG10
Address Latch 4 12 4 RB4/KBI0/SEG11
BSR Access RB5/KBI1
Program Memory STKPTR FSR0 Bank RB6/KBI2/PGC
(48/64 Kbytes) FSR1
RB7/KBI3/PGD
Data Latch FSR2 12 PORTC
RC0/T1OSO/T13CKI
inc/dec RC1/T1OSI/CCP2(1)
8 logic RC2/CCP1/SEG13
Table Latch
RC3/SCK/SCL
RC4/SDI/SDA
ROM Latch
Address RC5/SDO/SEG12
Instruction Bus <16> Decode RC6/TX1/CK1
RC7/RX1/DT1
IR PORTD
8 RD7/SEG7:RD0/SEG0
Instruction State Machine
Decode and Control Signals
Control PRODH PRODL PORTE
LCDBIAS1
LCDBIAS2
8 x 8 Multiply LCDBIAS3
3 8
COM0
BITOP W RE4/COM1
8 8 8 RE5/COM2
RE6/COM3
OSC1(3) Internal RE7/CCP2(1)/SEG31
Oscillator Power-up 8
Timer 8
Block PORTF
(3) Oscillator RF0/AN5/SEG18
OSC2 ALU<8>
INTRC Start-up Timer RF1/AN6/C2OUT/SEG19
Oscillator Power-on 8 RF2/AN7/C1OUT/SEG20
T1OSI
Reset RF3/AN8/SEG21
8 MHz RF4/AN9/SEG22
T1OSO Oscillator Watchdog
Timer RF5/AN10/CVREF/SEG23
Precision RF6/AN11/SEG24
Single-Supply Brown-out Band Gap
MCLR(2) RF7/SS/SEG25
Programming Reset Reference
In-Circuit Fail-Safe PORTG
VDD, VSS Debugger Clock Monitor RG0/SEG30
RG1/TX2/CK2/SEG29
RG2/RX2/DT2/SEG28
RG3/SEG27
RG4/SEG26
MCLR/VPP/RG5(2)
PORTH
BOR ADC
10-Bit Timer0 Timer1 Timer2 Timer3 RH3/SEG47:RH0/SEG44
HLVD
RH7/SEG40:RH4/SEG43
PORTJ
RJ3/SEG35:RJ0/SEG32
CCP2 LCD MSSP RJ7/SEG36:RJ4/SEG39
Comparators CCP1 EUSART1 AUSART2
Driver
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set and RE7 when CCP2MX is not set.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.

PIC18F6390/6490/8390/8490
TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS
Pin Number Pin Buffer
Pin Name Description
TQFP Type Type
MCLR/VPP/RG5 7 Master Clear (input) or programming voltage (input).

MCLR I ST Master Clear (Reset) input. This pin is an active-low
Reset to the device.
VPP P Programming voltage input.
RG5 I ST Digital input.
OSC1/CLKI/RA7 39 Oscillator crystal or external clock input.
OSC1 I ST Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
CLKI I CMOS External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7 I/O TTL General purpose I/O pin.
OSC2/CLKO/RA6 40 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
CLKO O — In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F6390/6490/8390/8490
TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED)
TQFP Type Type
PORTA is a bidirectional I/O port.

RA0/AN0 24
RA0 I/O TTL Digital I/O.
AN0 I Analog Analog input 0.
RA1/AN1 23
RA2/AN2/VREF-/SEG16 22
VREF- I Analog A/D reference voltage (Low) input.
SEG16 O Analog SEG16 output for LCD.
RA3/AN3/VREF+/SEG17 21
VREF+ I Analog A/D reference voltage (High) input.
RA4/T0CKI/SEG14 28
RA4 I/O ST/OD Digital I/O. Open-drain when configured as output.
T0CKI I ST Timer0 external clock input.
RA5/AN4/HLVDIN/SEG15 27
HLVDIN I Analog Low-Voltage Detect input.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.
RB0/INT0 48
RB0 I/O TTL Digital I/O.
INT0 I ST External interrupt 0.
RB1/INT1/SEG8 47
RB2/INT2/SEG9 46
RB3/INT3/SEG10 45
RB4/KBI0/SEG11 44
KBI0 I TTL Interrupt-on-change pin.
RB5/KBI1 43
RB6/KBI2/PGC 42
PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD 37
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI 30
RC0 I/O ST Digital I/O.
T1OSO O — Timer1 oscillator output.
T13CKI I ST Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2 29
T1OSI I CMOS Timer1 oscillator input.
CCP2(1) I/O ST Capture 2 input/Compare 2 output/PWM2 output.
RC2/CCP1/SEG13 33
CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK/SCL 34
SCK I/O ST Synchronous serial clock input/output for SPI mode.
SCL I/O ST Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA 35
SDI I ST SPI data in.
SDA I/O ST I2C data I/O.
RC5/SDO/SEG12 36
SDO O — SPI data out.
RC6/TX1/CK1 31
TX1 O — EUSART1 asynchronous transmit.
CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1 32
RX1 I ST EUSART1 asynchronous receive.
DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1).

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTD is a bidirectional I/O port.

RD0/SEG0 58
RD0 I/O ST Digital I/O.
RD1/SEG1 55
RD2/SEG2 54
RD3/SEG3 53
RD4/SEG4 52
RD5/SEG5 51
RD6/SEG6 50
RD7/SEG7 49

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTE is a bidirectional I/O port.

LCDBIAS1 2
LCDBIAS1 I Analog BIAS1 input for LCD.
LCDBIAS2 1
LCDBIAS3 64
COM0 63
COM0 O Analog COM0 output for LCD.
RE4/COM1 62
RE4 I/O ST Digital I/O.
RE5/COM2 61
RE6/COM3 60
RE7/CCP2/SEG31 59

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTF is a bidirectional I/O port.

RF0/AN5/SEG18 18
RF0 I/O ST Digital I/O.
RF1/AN6/C2OUT/SEG19 17
C2OUT O — Comparator 2 output.
RF3/AN8/SEG21 15
RF4/AN9/SEG22 14
RF5/AN10/CVREF/SEG23 13
CVREF O Analog Comparator reference voltage output.
RF6/AN11/SEG24 12
RF7/SS/SEG25 11
SS I TTL SPI slave select input.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTG is a bidirectional I/O port.

RG0/SEG30 3
RG0 I/O ST Digital I/O.
RG1/TX2/CK2/SEG29 4
TX2 O — AUSART2 asynchronous transmit.
CK2 I/O ST AUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/SEG28 5
RX2 I ST AUSART2 asynchronous receive.
DT2 I/O ST AUSART2 synchronous data (see related TX2/CK2).
RG3/SEG27 6
RG4/SEG26 8
RG5 See MCLR/VPP/RG5 pin.
VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.
AVDD 19 P — Positive supply for analog modules.

PIC18F6390/6490/8390/8490
TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS
TQFP Type Type
MCLR/VPP/RG5 9 Master Clear (input) or programming voltage (input).

MCLR I ST Master Clear (Reset) input. This pin is an active-low
Reset to the device.
VPP P Programming voltage input.
RG5 I ST Digital input.
OSC1/CLKI/RA7 49 Oscillator crystal or external clock input.
OSC1 I ST Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
CLKI I CMOS External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
OSC2/CLKO/RA6 50 Oscillator crystal or clock output.
OSC2 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
CLKO O — In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTA is a bidirectional I/O port.

RA0/AN0 30
RA1/AN1 29
RA2/AN2/VREF-/SEG16 28
VREF- I Analog A/D reference voltage (Low) input.
RA3/AN3/VREF+/SEG17 27
VREF+ I Analog A/D reference voltage (High) input.
RA4/T0CKI/SEG14 34
RA4 I/O ST/OD Digital I/O. Open-drain when configured as output.
T0CKI I ST Timer0 external clock input.
RA5/AN4/HLVDIN/SEG15 33
HLVDIN I Analog Low-Voltage Detect input.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.
RB0/INT0 58
RB1/INT1/SEG8 57
RB2/INT2/SEG9 56
RB3/INT3/SEG10 55
RB4/KBI0/SEG11 54
RB5/KBI1 53
RB6/KBI2/PGC 52
PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD 47
PGD I/O ST In-Circuit Debugger and ICSP programming data pin.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI 36
T1OSO O — Timer1 oscillator output.
T13CKI I ST Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2 35
T1OSI I CMOS Timer1 oscillator input.
RC2/CCP1/SEG13 43
CCP1 I/O ST Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK/SCL 44
SCK I/O ST Synchronous serial clock input/output for SPI mode.
SCL I/O ST Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA 45
SDI I ST SPI data in.
SDA I/O ST I2C data I/O.
RC5/SDO/SEG12 46
SDO O — SPI data out.
RC6/TX1/CK1 37
TX1 O — EUSART1 asynchronous transmit.
CK1 I/O ST EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1 38
RX1 I ST EUSART1 asynchronous receive.
DT1 I/O ST EUSART1 synchronous data (see related TX1/CK1).

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTD is a bidirectional I/O port.

RD0/SEG0 72
RD1/SEG1 69
RD2/SEG2 68
RD3/SEG3 67
RD4/SEG4 66
RD5/SEG5 65
RD6/SEG6 64
RD7/SEG7 63

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTE is a bidirectional I/O port.

LCDBIAS1 4
LCDBIAS2 3
LCDBIAS3 78
COM0 77
RE4/COM1 76
RE5/COM2 75
RE6/COM3 74
RE7/CCP2/SEG31 73

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTF is a bidirectional I/O port.

RF0/AN5/SEG18 24
RF3/AN8/SEG21 17
RF4/AN9/SEG22 16
RF5/AN10/CVREF/SEG23 15
CVREF O Analog Comparator reference voltage output.
RF6/AN11/SEG24 14
RF7/SS/SEG25 13
SS I TTL SPI slave select input.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTG is a bidirectional I/O port.

RG0/SEG30 5
RG1/TX2/CK2/SEG29 6
TX2 O — AUSART2 asynchronous transmit.
CK2 I/O ST AUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/SEG28 7
RX2 I ST AUSART2 asynchronous receive.
DT2 I/O ST AUSART2 synchronous data (see related TX2/CK2).
RG3/SEG27 8
RG4/SEG26 10
RG5 See MCLR/VPP/RG5 pin.

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTH is a bidirectional I/O port.

RH0/SEG47 79
RH0 I/O ST Digital I/O.
RH1/SEG46 80
RH2/SEG45 1
RH3/SEG44 2
RH4/SEG40 22
RH5/SEG41 21
RH6/SEG42 20
RH7/SEG43 19

PIC18F6390/6490/8390/8490
TQFP Type Type
PORTJ is a bidirectional I/O port.

RJ0/SEG32 62
RJ0 I/O ST Digital I/O.
RJ1/SEG33 61
RJ2/SEG34 60
RJ3/SEG35 59
RJ4/SEG39 39
RJ5/SEG38 40
RJ5 I/O ST Digital I/O
RJ6/SEG37 41
RJ7/SEG36 42
VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.
VDD 12, 32, 48, 71 P — Positive supply for logic and I/O pins.
AVSS 26 P — Ground reference for analog modules.
AVDD 25 P — Positive supply for analog modules.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
2.0 OSCILLATOR FIGURE 2-1: CRYSTAL/CERAMIC
CONFIGURATIONS RESONATOR OPERATION
(XT, LP, HS OR HSPLL
2.1 Oscillator Types CONFIGURATION)
PIC18F6390/6490/8390/8490 devices can be operated C1(1) OSC1
in ten different oscillator modes. The user can program
To
the Configuration bits, FOSC3:FOSC0, in Configuration Internal
Register 1H to select one of these ten modes: XTAL RF(3)
Logic
1. LP Low-Power Crystal
Sleep
2. XT Crystal/Resonator RS(2)
3. HS High-Speed Crystal/Resonator C2(1) PIC18FXXXX
OSC2
4. HSPLL
High-Speed Crystal/Resonator
with PLL Enabled Note 1: See Table 2-1 and Table 2-2 for initial values of
5. RC External Resistor/Capacitor with C1 and C2.
FOSC/4 Output on RA6 2: A series resistor (RS) may be required for AT
6. RCIO External Resistor/Capacitor with I/O strip cut crystals.
on RA6 3: RF varies with the oscillator mode chosen.
7. INTIO1 Internal Oscillator with FOSC/4 Output
on RA6 and I/O on RA7
8. INTIO2 Internal Oscillator with I/O on RA6
TABLE 2-1: CAPACITOR SELECTION FOR
and RA7 CERAMIC RESONATORS
9. EC External Clock with FOSC/4 Output Typical Capacitor Values Used:
10. ECIO External Clock with I/O on RA6 Mode Freq OSC1 OSC2
2.2 Crystal Oscillator/Ceramic XT 455 kHz 56 pF 56 pF

2.0 MHz 47 pF 47 pF
Resonators
4.0 MHz 33 pF 33 pF
In XT, LP, HS or HSPLL Oscillator modes, a crystal or HS 8.0 MHz 27 pF 27 pF
ceramic resonator is connected to the OSC1 and 16.0 MHz 22 pF 22 pF
OSC2 pins to establish oscillation. Figure 2-1 shows
Capacitor values are for design guidance only.
the pin connections.
These capacitors were tested with the resonators
The oscillator design requires the use of a parallel cut
listed below for basic start-up and operation. These
crystal.
values are not optimized.
Note: Use of a series cut crystal may give a fre- Different capacitor values may be required to produce
quency out of the crystal manufacturer’s acceptable oscillator operation. The user should test
specifications. the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.
Resonators Used:
455 kHz 4.0 MHz
2.0 MHz 8.0 MHz
16.0 MHz

PIC18F6390/6490/8390/8490
TABLE 2-2: CAPACITOR SELECTION FOR An external clock source may also be connected to the
CRYSTAL OSCILLATOR OSC1 pin in the HS mode, as shown in Figure 2-2.
Typical Capacitor Values
Crystal FIGURE 2-2: EXTERNAL CLOCK
Osc Type Tested:
Freq INPUT OPERATION
C1 C2 (HS CONFIGURATION)
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF Clock from OSC1
XT 1 MHz 33 pF 33 pF Ext. System PIC18FXXXX
(HS Mode)
4 MHz 27 pF 27 pF Open OSC2
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF 2.3 External Clock Input
Capacitor values are for design guidance only. The EC and ECIO Oscillator modes require an external
These capacitors were tested with the crystals listed clock source to be connected to the OSC1 pin. There is
below for basic start-up and operation. These values no oscillator start-up time required after a Power-on
are not optimized. Reset or after an exit from Sleep mode.
Different capacitor values may be required to produce In the EC Oscillator mode, the oscillator frequency
acceptable oscillator operation. The user should test divided by 4 is available on the OSC2 pin. This signal
the performance of the oscillator over the expected may be used for test purposes or to synchronize other
VDD and temperature range for the application. logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
See the notes following this table for additional
information.
FIGURE 2-3: EXTERNAL CLOCK
Crystals Used: INPUT OPERATION
32 kHz 4 MHz (EC CONFIGURATION)
200 kHz 8 MHz
1 MHz 20 MHz Clock from OSC1/CLKI
Ext. System PIC18FXXXX
FOSC/4 OSC2/CLKO
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the
start-up time.
The ECIO Oscillator mode functions like the EC mode,
2: When operating below 3V VDD, or when except that the OSC2 pin becomes an additional gen-
using certain ceramic resonators at any eral purpose I/O pin. The I/O pin becomes bit 6 of
voltage, it may be necessary to use the PORTA (RA6). Figure 2-4 shows the pin connections
HS mode or switch to a crystal oscillator. for the ECIO Oscillator mode.
3: Since each resonator/crystal has its own
characteristics, the user should consult FIGURE 2-4: EXTERNAL CLOCK
the resonator/crystal manufacturer for INPUT OPERATION
appropriate values of external (ECIO CONFIGURATION)
components.
4: Rs may be required to avoid overdriving
crystals with low drive level specification. Clock from OSC1/CLKI
Ext. System PIC18FXXXX
5: Always verify oscillator performance over
the VDD and temperature range that is RA6 I/O (OSC2)
expected for the application.

PIC18F6390/6490/8390/8490
2.4 RC Oscillator 2.5 PLL Frequency Multiplier
For timing insensitive applications, the “RC” and A Phase Locked Loop (PLL) circuit is provided as an
“RCIO” device options offer additional cost savings. option for users who want to use a lower frequency
The actual oscillator frequency is a function of several oscillator circuit, or to clock the device up to its highest
factors: rated frequency from a crystal oscillator. This may be
• Supply voltage useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
• Values of the external resistor (REXT) and
clock speeds from an internal oscillator.
capacitor (CEXT)
• Operating temperature 2.5.1 HSPLL OSCILLATOR MODE
Given the same device, operating voltage and The HSPLL mode makes use of the HS mode oscillator
temperature and component values, there will also be for frequencies up to 10 MHz. A PLL then multiplies the
unit-to-unit frequency variations. These are due to oscillator output frequency by 4 to produce an internal
factors such as: clock frequency up to 40 MHz.
• Normal manufacturing variation The PLL is only available to the crystal oscillator when
• Difference in lead frame capacitance between the FOSC3:FOSC0 Configuration bits are programmed
package types (especially for low CEXT values) for HSPLL mode (= 0110).
• Variations within the tolerance of limits of REXT
and CEXT FIGURE 2-7: PLL BLOCK DIAGRAM
In the RC Oscillator mode, the oscillator frequency (HS MODE)
divided by 4 is available on the OSC2 pin. This signal
HS Oscillator Enable
may be used for test purposes or to synchronize other PLL Enable
logic. Figure 2-5 shows how the R/C combination is (from Configuration Register 1H)
connected.
OSC2
FIGURE 2-5: RC OSCILLATOR MODE Phase
HS Mode FIN Comparator
VDD
OSC1 Crystal FOUT
Oscillator
REXT
OSC1 Internal Loop
Clock Filter
CEXT
PIC18FXXXX
VSS
÷4 VCO
OSC2/CLKO SYSCLK
FOSC/4
MUX
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
The RCIO Oscillator mode (Figure 2-6) functions like

the RC mode, except that the OSC2 pin becomes an 2.5.2 PLL AND INTOSC
additional general purpose I/O pin. The I/O pin The PLL is also available to the internal oscillator block
becomes bit 6 of PORTA (RA6). in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock
FIGURE 2-6: RCIO OSCILLATOR MODE output of up to 32 MHz. The operation of INTOSC with
VDD the PLL is described in Section 2.6.4 “PLL in INTOSC
Modes”.
REXT
Internal
OSC1
Clock
CEXT
PIC18FXXXX
VSS
RA6 I/O (OSC2)
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

PIC18F6390/6490/8390/8490
2.6 Internal Oscillator Block When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
The PIC18F6390/6490/8390/8490 devices include an frequency. The INTRC clock will reach the new
internal oscillator block, which generates two different frequency within 8 clock cycles (approximately
clock signals; either can be used as the micro- 8 * 32 μs = 256 μs). The INTOSC clock will stabilize
controller’s clock source. This may eliminate the need within 1 ms. Code execution continues during this shift.
for external oscillator circuits on the OSC1 and/or There is no indication that the shift has occurred.
OSC2 pins.
The OSCTUNE register also implements the INTSRC
The main output (INTOSC) is an 8 MHz clock source, and PLLEN bits, which control certain features of the
which can be used to directly drive the device clock. It internal oscillator block. The INTSRC bit allows users
also drives a postscaler, which can provide a range of to select which internal oscillator provides the clock
clock frequencies from 31 kHz to 4 MHz. The INTOSC source when the 31 kHz frequency option is selected.
output is enabled when a clock frequency from 125 kHz This is covered in greater detail in Section 2.7.1
to 8 MHz is selected. “Oscillator Control Register”.
The other clock source is the internal RC oscillator The PLLEN bit controls the operation of the frequency
(INTRC), which provides a nominal 31 kHz output. multiplier, PLL, in internal oscillator modes.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the 2.6.4 PLL IN INTOSC MODES
following are enabled:
The 4x frequency multiplier can be used with the inter-
• Power-up Timer nal oscillator block to produce faster device clock
• Fail-Safe Clock Monitor speeds than are normally possible with an internal
• Watchdog Timer oscillator. When enabled, the PLL produces a clock
• Two-Speed Start-up speed of up to 32 MHz.
• LCD with INTRC as its clock source Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
These features are discussed in greater detail in
used to enable or disable its operation.
Section 23.0 “Special Features of the CPU”.
The PLL is available when the device is configured to use
The clock source frequency (INTOSC direct, INTRC
the internal oscillator block as its primary clock source
direct or INTOSC postscaler) is selected by configuring
(FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL
the IRCF bits of the OSCCON register (Register 2-2).
will only function when the selected output frequency is
either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If
2.6.1 INTIO MODES
both of these conditions are not met, the PLL is disabled.
Using the internal oscillator as the clock source elimi-
The PLLEN control bit is only functional in those inter-
nates the need for up to two external oscillator pins,
nal oscillator modes where the PLL is available. In all
which can then be used for digital I/O. Two distinct
other modes, it is forced to ‘0’ and is effectively
configurations are available:
unavailable.
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and 2.6.5 INTOSC FREQUENCY DRIFT
output.
The factory calibrates the internal oscillator block
• In INTIO2 mode, OSC1 functions as RA7 and output (INTOSC) for 8 MHz. However, this frequency
OSC2 functions as RA6, both for digital input and may drift as VDD or temperature changes, which can
output. affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
2.6.2 INTOSC OUTPUT FREQUENCY the value in the OSTUNE register. This has no effect on
The internal oscillator block is calibrated at the factory the INTRC clock source frequency.
to produce an INTOSC output frequency of 8.0 MHz. Tuning the INTOSC source requires knowing when to
The INTRC oscillator operates independently of the make the adjustment, in which direction it should be
INTOSC source. Any changes in INTOSC across made and in some cases, how large a change is
voltage and temperature are not necessarily reflected needed. Three compensation techniques are
by changes in INTRC and vice versa. discussed in Section 2.6.5.1 “Compensating with
the AUSART”, Section 2.6.5.2 “Compensating with
2.6.3 OSCTUNE REGISTER the Timers” and Section 2.6.5.3 “Compensating
The internal oscillator’s output has been calibrated at with the Timers”, but other techniques may be used.
the factory, but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.

PIC18F6390/6490/8390/8490
2.6.5.1 Compensating with the AUSART is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
An adjustment may be required when the AUSART
the OSCTUNE register.
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
2.6.5.3 Compensating with the Timers
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSTUNE to A CCP module can use free-running Timer1 (or
reduce the clock frequency. On the other hand, errors Timer3), clocked by the internal oscillator block and an
in data may suggest that the clock speed is too low. To external event with a known period (i.e., AC power
compensate, increment OSTUNE to increase the clock frequency). The time of the first event is captured in the
frequency. CCPRxH:CCPRxL registers and is recorded. When the
second event causes a capture, the time of the first
2.6.5.2 Compensating with the Timers event is subtracted from the time of the second event.
Since the period of the external event is known, the
This technique compares device clock speed to some
time difference between events can be calculated.
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is If the measured time is much greater than the
clocked by a fixed reference source, such as the calculated time, then the internal oscillator block is
Timer1 oscillator. running too fast. To compensate, decrement the
OSTUNE register. If the measured time is much less
Both timers are cleared, but the timer clocked by the
than the calculated time, then the internal oscillator
reference generates interrupts. When an interrupt
block is running too slow. To compensate, increment
occurs, the internally clocked timer is read and both
the OSTUNE register.
timers are cleared. If the internally clocked timer value
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)
1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled
bit 5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
• •
• •
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
• •
• •
10000 = Minimum frequency
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. See
Section 2.6.4 “PLL in INTOSC Modes” for details.

PIC18F6390/6490/8390/8490
2.7 Clock Sources and The secondary oscillators are those external sources
Oscillator Switching not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
Like previous PIC18 devices, the controller is placed in a power-managed mode.
PIC18F6390/6490/8390/8490 family includes a feature
PIC18F6390/6490/8390/8490 devices offer the Timer1
that allows the device clock source to be switched from
oscillator as a secondary oscillator. This oscillator, in all
the main oscillator to an alternate low-frequency clock
power-managed modes, is often the time base for
source. PIC18F6390/6490/8390/8490 devices offer
functions such as a Real-Time Clock.
two alternate clock sources. When an alternate clock
source is enabled, the various power-managed Most often, a 32.768 kHz watch crystal is connected
operating modes are available. between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Like the LP Oscillator mode circuit, loading
Essentially, there are three clock sources for these
capacitors are also connected from each pin to ground.
devices:
The Timer1 oscillator is discussed in greater detail in
• Primary oscillators
Section 11.3 “Timer1 Oscillator”.
• Secondary oscillators
In addition to being a primary clock source, the internal
• Internal oscillator block
oscillator block is available as a power-managed
The primary oscillators include the External Crystal mode clock source. The INTRC source is also used as
and Resonator modes, the External RC modes, the the clock source for several special features, such as
External Clock modes and the internal oscillator block. the WDT and Fail-Safe Clock Monitor.
The particular mode is defined by the FOSC3:FOSC0
The clock sources for the PIC18F6390/6490/8390/8490
Configuration bits. The details of these modes are
devices are shown in Figure 2-8. See Section 23.0
covered earlier in this chapter.
“Special Features of the CPU” for Configuration
register details.
FIGURE 2-8: PIC18F6390/6490/8390/8490 CLOCK DIAGRAM
PIC18F6X90/8X90
Primary Oscillator LP, XT, HS, RC, EC
OSC2
Sleep HSPLL, INTOSC/PLL

4 x PLL
OSC1
OSCTUNE<6>
Secondary Oscillator T1OSC Peripherals
MUX
T1OSO
T1OSCEN
Enable
T1OSI Oscillator OSCCON<6:4> Internal Oscillator
OSCCON<6:4> 8 MHz CPU
111
4 MHz
Internal 110
Oscillator 2 MHz IDLEN
Block 101
Clock
Postscaler
1 MHz
8 MHz 100 Control
MUX
Source 500 kHz

8 MHz 011
(INTOSC) 250 kHz
INTRC 010 FOSC3:FOSC0 OSCCON<1:0>
Source 125 kHz
001
1 31 kHz Clock Source Option
31 kHz (INTRC) 000 for Other Modules
0
OSCTUNE<7>
WDT, PWRT, FSCM
and Two-Speed Start-up

PIC18F6390/6490/8390/8490
2.7.1 OSCILLATOR CONTROL REGISTER The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
The OSCCON register (Register 2-2) controls several
instruction is executed.
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes. The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
The System Clock Select bits, SCS1:SCS0, select the
“Power-Managed Modes”.
clock source. The available clock sources are the pri-
mary clock (defined by the FOSC:FOSC0 Configuration Note 1: The Timer1 oscillator must be enabled to
bits), the secondary clock (Timer1 oscillator) and the select the secondary clock source. The
internal oscillator block. The clock source changes Timer1 oscillator is enabled by setting the
immediately after one or more of the bits is written to, T1OSCEN bit in the Timer1 Control regis-
following a brief clock transition interval. The SCS bits ter (T1CON<3>). If the Timer1 oscillator is
are cleared on all forms of Reset. not enabled, then any attempt to select a
The Internal Oscillator Frequency Select bits, secondary clock source when executing a
IRCF2:IRCF0, select the frequency output of the SLEEP instruction will be ignored.
internal oscillator block to drive the device clock. The 2: It is recommended that the Timer1
choices are the INTRC source, the INTOSC source oscillator be operating and stable before
(8 MHz) or one of the frequencies derived from the executing the SLEEP instruction, or a very
INTOSC postscaler (31.25 kHz to 4 MHz). If the long delay may occur while the Timer1
internal oscillator block is supplying the device clock, oscillator starts.
changing the states of these bits will have an
immediate change on the internal oscillator’s output. 2.7.2 OSCILLATOR TRANSITIONS
When an output frequency of 31 kHz is selected PIC18F6390/6490/8390/8490 devices contain circuitry
(IRCF2:IRCF0 = 000), users may choose which inter- to prevent clock “glitches” when switching between
nal oscillator acts as the source. This is done with the clock sources. A short pause in the device clock occurs
INTSRC bit in the OSCTUNE register (OSCTUNE<7>). during the clock switch. The length of this pause is the
Setting this bit selects INTOSC as a 31.25 kHz clock sum of two cycles of the old clock source and three to
source by enabling the divide-by-256 output of the four cycles of the new clock source. This formula
INTOSC postscaler. Clearing INTSRC selects INTRC assumes that the new clock source is stable.
(nominally 31 kHz) as the clock source.
Clock transitions are discussed in greater detail in
This option allows users to select the tunable and more Section 3.1.2 “Entering Power-Managed Modes”.
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has
stabilized and is providing the device clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock, or the internal oscillator block has just started
and is not yet stable.

PIC18F6390/6490/8390/8490
REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
bit 7 bit 0
Legend:
bit 7 IDLEN: Idle Enable bit

1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz(3)
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)
bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x = Internal oscillator block
01 = Timer1 oscillator
00 = Primary oscillator
Note 1: Depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see Section 2.6.3 “OSCTUNE Register”.
3: Default output frequency of INTOSC on Reset.

PIC18F6390/6490/8390/8490
2.8 Effects of Power-Managed Modes 2.9 Power-up Delays
on the Various Clock Sources Power-up delays are controlled by two timers, so that no
When PRI_IDLE mode is selected, the designated pri- external Reset circuitry is required for most applications.
mary oscillator continues to run without interruption. The delays ensure that the device is kept in Reset until
For all other power-managed modes, the oscillator the device power supply is stable under normal circum-
using the OSC1 pin is disabled. The OSC1 pin (and stances and the primary clock is operating and stable.
OSC2 pin, if used by the oscillator) will stop oscillating. For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and The first timer is the Power-up Timer (PWRT), which
providing the device clock. The Timer1 oscillator may provides a fixed delay on power-up (parameter 33,
also run in all power-managed modes if required to Table 26-10). It is enabled by clearing (= 0) the
clock Timer1 or Timer3. PWRTEN Configuration bit.
In internal oscillator modes (RC_RUN and RC_IDLE), The second timer is the Oscillator Start-up Timer
the internal oscillator block provides the device clock (OST), intended to keep the chip in Reset until the
source. The 31 kHz INTRC output can be used directly crystal oscillator is stable (LP, XT and HS modes). The
to provide the clock and may be enabled to support var- OST does this by counting 1024 oscillator cycles
ious special features, regardless of the power-managed before allowing the oscillator to clock the device.
mode (see Section 23.2 “Watchdog Timer (WDT)” When the HSPLL Oscillator mode is selected, the
through Section 23.4 “Fail-Safe Clock Monitor” for device is kept in Reset for an additional 2 ms, following
more information on WDT, Fail-Safe Clock Monitor and the HS mode OST delay, so the PLL can lock to the
Two-Speed Start-up). The INTOSC output at 8 MHz may incoming clock frequency.
be used directly to clock the device, or may be divided
There is a delay of interval TCSD (parameter 38,
down by the postscaler. The INTOSC output is disabled
Table 26-10) following POR while the controller
if the clock is provided directly from the INTRC output.
becomes ready to execute instructions. This delay runs
If the Sleep mode is selected, all clock sources are concurrently with any other delays. This may be the
stopped. Since all the transistor switching currents only delay that occurs when any of the EC, RC or INTIO
have been stopped, Sleep mode achieves the lowest modes are used as the primary clock source.
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-Time Clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
INTx pins and others). Peripherals that may add signif-
icant current consumption are listed in Section 26.2
“DC Characteristics: Power-Down and Supply
Current”.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent
voltage level voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES
PIC18F6390/6490/8390/8490 devices offer a total of The SCS1:SCS0 bits allow the selection of one of three
seven operating modes for more efficient power clock sources for power-managed modes. They are:
management. These modes provide a variety of • the primary clock, as defined by the
options for selective power conservation in applications FOSC3:FOSC0 Configuration bits
where resources may be limited (i.e., battery-powered • the secondary clock (the Timer1 oscillator)
devices). • the internal oscillator block (for RC modes)
There are three categories of power-managed modes:
3.1.2 ENTERING POWER-MANAGED
• Sleep mode
MODES
• Idle modes
• Run modes Entering power-managed Run mode, or switching from
one power-managed mode to another, begins by
These categories define which portions of the device loading the OSCCON register. The SCS1:SCS0 bits
are clocked and sometimes, what speed. The Run and select the clock source and determine which Run or
Idle modes may use any of the three available clock Idle mode is being used. Changing these bits causes
sources (primary, secondary or INTOSC multiplexer); an immediate switch to the new clock source,
the Sleep mode does not use a clock source. assuming that it is running. The switch may also be
The power-managed modes include several subject to clock transition delays. These are discussed
power-saving features. One of these is the clock in Section 3.1.3 “Clock Transitions and Status
switching feature, offered in other PIC18 devices, Indicators” and subsequent sections.
allowing the controller to use the Timer1 oscillator in Entry to the power-managed Idle or Sleep modes is
place of the primary oscillator. Also included is the triggered by the execution of a SLEEP instruction. The
Sleep mode, offered by all PIC® devices, where all actual mode that results depends on the status of the
device clocks are stopped. IDLEN bit.
Depending on the current mode and the mode being
3.1 Selecting Power-Managed Modes switched to, a change to a power-managed mode does
Selecting a power-managed mode requires deciding if not always require setting all of these bits. Many transi-
the CPU is to be clocked or not and selecting a clock tions may be done by changing the oscillator select
source. The IDLEN bit controls CPU clocking, while the bits, or changing the IDLEN bit prior to issuing a SLEEP
SCS1:SCS0 bits select a clock source. The individual instruction. If the IDLEN bit is already configured
modes, bit settings, clock sources and affected correctly, it may only be necessary to perform a SLEEP
modules are summarized in Table 3-1. instruction to switch to the desired mode.
TABLE 3-1: POWER-MANAGED MODES

OSCCON<7,1:0> Module Clocking
Mode Available Clock and Oscillator Source
IDLEN(1) SCS1:SCS0 CPU Peripherals
Sleep 0 N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(2):
This is the normal, full-power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)
PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

PIC18F6390/6490/8390/8490
3.1.3 CLOCK TRANSITIONS AND 3.2 Run Modes
STATUS INDICATORS
In the Run modes, clocks to both the core and
The length of the transition between clock sources is peripherals are active. The difference between these
the sum of two cycles of the old clock source and three modes is the clock source.
to four cycles of the new clock source. This formula
assumes that the new clock source is stable. 3.2.1 PRI_RUN MODE
Three bits indicate the current clock source and its The PRI_RUN mode is the normal, full-power
status. They are: execution mode of the microcontroller. This is also the
• OSTS (OSCCON<3>) default mode upon a device Reset unless Two-Speed
Start-up is enabled (see Section 23.3 “Two-Speed
• IOFS (OSCCON<2>)
Start-up” for details). In this mode, the OSTS bit is set.
• T1RUN (T1CON<6>) The IOFS bit may be set if the internal oscillator block
In general, only one of these bits will be set while in a is the primary clock source (see Section 2.7.1
given power-managed mode. When the OSTS bit is “Oscillator Control Register”).
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output provides 3.2.2 SEC_RUN MODE
a stable, 8 MHz clock source to a divider that actually The SEC_RUN mode is the compatible mode to the
drives the device clock. When the T1RUN bit is set, the “clock switching” feature offered in other PIC18
Timer1 oscillator provides the clock. If none of these devices. In this mode, the CPU and peripherals are
bits are set, then either the INTRC clock source clocks clocked from the Timer1 oscillator. This gives users the
the device, or the INTOSC source is not yet stable. option of lower power consumption while still using a
If the internal oscillator block is configured as the high-accuracy clock source.
primary clock source by the FOSC3:FOSC0 SEC_RUN mode is entered by setting the SCS1:SCS0
Configuration bits, then both the OSTS and IOFS bits bits to ‘01’. The device clock source is switched to the
may be set when in PRI_RUN or PRI_IDLE modes. Timer1 oscillator (see Figure 3-1), the primary
This indicates that the primary clock (INTOSC output) oscillator is shut down, the T1RUN bit (T1CON<6>) is
is generating a stable 8 MHz output. Entering another set and the OSTS bit is cleared.
power-managed RC mode at the same frequency
would clear the OSTS bit. Note: The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
Note 1: Caution should be used when modifying a If the T1OSCEN bit is not set when the
single IRCF bit. If VDD is less than 3V, it is SCS1:SCS0 bits are set to ‘01’, entry to
possible to select a higher clock speed SEC_RUN mode will not occur. If the
than is supported by the low VDD. Timer1 oscillator is enabled, but not yet
Improper device operation may result if running, peripheral clocks will be delayed
the VDD/FOSC specifications are violated. until the oscillator has started. In such
2: Executing a SLEEP instruction does not situations, initial oscillator operation is far
necessarily place the device into Sleep from stable and unpredictable operation
mode. It acts as the trigger to place the may result.
controller into either the Sleep mode or On transitions from SEC_RUN mode to PRI_RUN, the
one of the Idle modes, depending on the peripherals and CPU continue to be clocked from the
setting of the IDLEN bit. Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
3.1.4 MULTIPLE SLEEP COMMANDS back to the primary clock occurs (see Figure 3-2).
The power-managed mode that is invoked with the When the clock switch is complete, the T1RUN bit is
SLEEP instruction is determined by the setting of the cleared, the OSTS bit is set and the primary clock
IDLEN bit at the time the instruction is executed. If provides the clock. The IDLEN and SCS bits are not
another SLEEP instruction is executed, the device will affected by the wake-up; the Timer1 oscillator
enter the power-managed mode specified by IDLEN at continues to run.
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.

PIC18F6390/6490/8390/8490
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI 1 2 3 n-1 n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
TOST(1) TPLL(1)
PLL Clock
Output 1 2
n-1 n
Clock
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
SCS1:SCS0 bits Changed OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

PIC18F6390/6490/8390/8490
3.2.3 RC_RUN MODE If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
In RC_RUN mode, the CPU and peripherals are
remain clear; there will be no indication of the current
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut clock source. The INTRC source provides the device
down. When using the INTRC source, this mode clocks.
provides the best power conservation of all the Run If the IRCF bits are changed from all clear (thus
modes, while still executing code. It works well for user enabling the INTOSC output), or if INTSRC is set, the
applications which are not highly timing-sensitive, or do IOFS bit becomes set after the INTOSC output
not require high-speed clocks at all times. becomes stable. Clocks to the device continue while
If the primary clock source is the internal oscillator block the INTOSC source stabilizes after an interval of
(either INTRC or INTOSC), there are no distinguishable TIOBST.
differences between PRI_RUN and RC_RUN modes If the IRCF bits were previously at a non-zero value, or
during execution. However, a clock switch delay will occur if INTSRC was set before setting SCS1 and the
during entry to and exit from RC_RUN mode. Therefore, INTOSC source was already stable, the IOFS bit will
if the primary clock source is the internal oscillator block, remain set.
the use of RC_RUN mode is not recommended.
On transitions from RC_RUN mode to PRI_RUN, the
This mode is entered by setting the SCS1 bit to ‘1’. device continues to be clocked from the INTOSC
Although it is ignored, it is recommended that the SCS0 multiplexer while the primary clock is started. When the
bit also be cleared; this is to maintain software primary clock becomes ready, a clock switch to the
compatibility with future devices. When the clock primary clock occurs (see Figure 3-4). When the clock
source is switched to the INTOSC multiplexer (see switch is complete, the IOFS bit is cleared, the OSTS
Figure 3-3), the primary oscillator is shut down and the bit is set and the primary clock provides the device
OSTS bit is cleared. The IRCF bits may be modified at clock. The IDLEN and SCS bits are not affected by the
any time to immediately change the clock speed. switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
Note: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTRC 1 2 3 n-1 n
Clock Transition
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter PC PC + 2 PC + 4
FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4
Counter
SCS1:SCS0 bits Changed OSTS bit Set

PIC18F6390/6490/8390/8490
3.3 Sleep Mode 3.4 Idle Modes
The power-managed Sleep mode in the The Idle modes allow the controller’s CPU to be
PIC18F6390/6490/8390/8490 devices is identical to selectively shut down while the peripherals continue to
the legacy Sleep mode offered in all other PIC devices. operate. Selecting a particular Idle mode allows users
It is entered by clearing the IDLEN bit (the default state to further manage power consumption.
on device Reset) and executing the SLEEP instruction. If the IDLEN bit is set to a ‘1’ when a SLEEP instruction
This shuts down the selected oscillator (see is executed, the peripherals will be clocked from the
Figure 3-5). All clock source status bits are cleared. clock source selected using the SCS1:SCS0 bits;
Entering the Sleep mode from any other mode does not however, the CPU will not be clocked. The clock source
require a clock switch. This is because no clocks are status bits are not affected. Setting IDLEN and execut-
needed once the controller has entered Sleep. If the ing SLEEP provides a quick method of switching from a
WDT is selected, the INTRC source will continue to given Run mode to its corresponding Idle mode.
operate. If the Timer1 oscillator is enabled, it will also If the WDT is selected, the INTRC source will continue
continue to run. to operate. If the Timer1 oscillator is enabled, it will also
When a wake event occurs in Sleep mode (by interrupt, continue to run.
Reset or WDT time-out), the device will not be clocked Since the CPU is not executing instructions, the only
until the primary clock source becomes ready (see exits from any of the Idle modes are by interrupt, WDT
Figure 3-6), or it will be clocked from the internal oscil- time-out or a Reset. When a wake event occurs, CPU
lator block if either the Two-Speed Start-up or the execution is delayed by an interval of TCSD
Fail-Safe Clock Monitor are enabled (see Section 23.0 (parameter 38, Table 26-10) while it becomes ready to
“Special Features of the CPU”). In either case, the execute code. When the CPU begins executing code,
OSTS bit is set when the primary clock provides the it resumes with the same clock source for the current
device clocks. The IDLEN and SCS bits are not Idle mode. For example, when waking from RC_IDLE
affected by the wake-up. mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter PC PC + 2
FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(1) TPLL(1)
PLL Clock
Output
CPU Clock
Peripheral
Clock
Program
PC PC + 2 PC + 4 PC + 6
Counter
Wake Event OSTS bit Set

PIC18F6390/6490/8390/8490
3.4.1 PRI_IDLE MODE When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
This mode is unique among the three low-power Idle
required between the wake event and when code
modes, in that it does not disable the primary device
execution starts. This is required to allow the CPU to
clock. For timing-sensitive applications, this allows for
become ready to execute instructions. After the
the fastest resumption of device operation with its more
wake-up, the OSTS bit remains set. The IDLEN and
accurate primary clock source, since the clock source
SCS bits are not affected by the wake-up (see
does not have to “warm up” or transition from another
Figure 3-8).
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).
FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO PRI_IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program PC PC + 2
Counter
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
TCSD
CPU Clock
Peripheral
Clock
Program PC
Counter
Wake Event

PIC18F6390/6490/8390/8490
3.4.2 SEC_IDLE MODE 3.4.3 RC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the In RC_IDLE mode, the CPU is disabled but the periph-
peripherals continue to be clocked from the Timer1 erals continue to be clocked from the internal oscillator
oscillator. This mode is entered from SEC_RUN by set- block using the INTOSC multiplexer. This mode allows
ting the IDLEN bit and executing a SLEEP instruction. If for controllable power conservation during Idle periods.
the device is in another Run mode, set IDLEN first, then From RC_RUN, this mode is entered by setting the
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the IDLEN bit and executing a SLEEP instruction. If the
clock source is switched to the Timer1 oscillator, the device is in another Run mode, first set IDLEN, then set
primary oscillator is shut down, the OSTS bit is cleared the SCS1 bit and execute SLEEP. Although its value is
and the T1RUN bit is set. ignored, it is recommended that SCS0 also be cleared;
When a wake event occurs, the peripherals continue to this is to maintain software compatibility with future
be clocked from the Timer1 oscillator. After an interval devices. The INTOSC multiplexer may be used to
of TCSD following the wake event, the CPU begins select a higher clock frequency by modifying the IRCF
executing code being clocked by the Timer1 oscillator. bits before executing the SLEEP instruction. When the
The IDLEN and SCS bits are not affected by the clock source is switched to the INTOSC multiplexer, the
wake-up; the Timer1 oscillator continues to run (see primary oscillator is shut down and the OSTS bit is
Figure 3-8). cleared.
If the IRCF bits are set to any non-zero value, or the
Note: The Timer1 oscillator should already be
INTSRC bit is set, the INTOSC output is enabled. The
running prior to entering SEC_IDLE mode.
IOFS bit becomes set after the INTOSC output
If the T1OSCEN bit is not set when the
becomes stable after an interval of TIOBST
SLEEP instruction is executed, the SLEEP
(parameter 39, Table 26-10). Clocks to the peripherals
instruction will be ignored and entry to
continue while the INTOSC source stabilizes. If the
SEC_IDLE mode will not occur. If the
IRCF bits were previously at a non-zero value, or
Timer1 oscillator is enabled, but not yet
INTSRC was set before the SLEEP instruction was
running, peripheral clocks will be delayed
executed and the INTOSC source was already stable,
until the oscillator has started. In such
the IOFS bit will remain set. If the IRCF bits and
situations, initial oscillator operation is far
INTSRC are all clear, the INTOSC output will not be
from stable and unpredictable operation
enabled; the IOFS bit will remain clear and there will be
may result.
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wake event, the CPU begins
executing code being clocked by the INTOSC multi-
plexer. The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.

PIC18F6390/6490/8390/8490
3.5 Exiting Idle and Sleep Modes 3.5.3 EXIT BY RESET
An exit from Sleep mode or any of the Idle modes is Normally, the device is held in Reset by the Oscillator
triggered by an interrupt, a Reset or a WDT time-out. Start-up Timer (OST) until the primary clock becomes
This section discusses the triggers that cause exits ready. At that time, the OSTS bit is set and the device
from power-managed modes. The clocking subsystem begins executing code. If the internal oscillator block is
actions are discussed in each of the power-managed the new clock source, the IOFS bit is set instead.
modes (see Section 3.2 “Run Modes” through The exit delay time from Reset to the start of code
Section 3.4 “Idle Modes”). execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
3.5.1 EXIT BY INTERRUPT new clock source is the primary clock. Exit delays are
Any of the available interrupt sources can cause the summarized in Table 3-2.
device to exit from an Idle or Sleep mode to a Run Code execution can begin before the primary clock
mode. To enable this functionality, an interrupt source becomes ready. If either the Two-Speed Start-up (see
must be enabled by setting its enable bit in one of the Section 23.3 “Two-Speed Start-up”) or Fail-Safe
INTCON or PIE registers. The exit sequence is initiated Clock Monitor (see Section 23.4 “Fail-Safe Clock
when the corresponding interrupt flag bit is set. Monitor”) is enabled, the device may begin execution
On all exits from Idle or Sleep modes by interrupt, code as soon as the Reset source has cleared. Execution is
execution branches to the interrupt vector if the clocked by the INTOSC multiplexer driven by the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code internal oscillator block. Execution is clocked by the
execution continues or resumes without branching internal oscillator block until either the primary clock
(see Section 8.0 “Interrupts”). becomes ready, or a power-managed mode is entered
before the primary clock becomes ready; the primary
A fixed delay of interval, TCSD, following the wake
clock is then shut down.
event, is required when leaving Sleep and Idle modes.
This delay is required for the CPU to prepare for 3.5.4 EXIT WITHOUT AN OSCILLATOR
execution. Instruction execution resumes on the first
START-UP DELAY
clock cycle following this delay.
Certain exits from power-managed modes do not
3.5.2 EXIT BY WDT TIME-OUT invoke the OST at all. There are two cases:
A WDT time-out will cause different actions depending • PRI_IDLE mode, where the primary clock source
on which power-managed mode the device is in when is not stopped; and
the time-out occurs. • the primary clock source is not any of the LP, XT,
If the device is not executing code (all Idle modes and HS or HSPLL modes.
Sleep mode), the time-out will result in an exit from the In these instances, the primary clock source either
power-managed mode (see Section 3.2 “Run does not require an oscillator start-up delay since it is
Modes” and Section 3.3 “Sleep Mode”). If the device already running (PRI_IDLE), or normally does not
is executing code (all Run modes), the time-out will require an oscillator start-up delay (RC, EC and INTIO
result in a WDT Reset (see Section 23.2 “Watchdog Oscillator modes). However, a fixed delay of interval,
Timer (WDT)”). TCSD, following the wake event, is still required when
The WDT timer and postscaler are cleared by execut- leaving Sleep and Idle modes to allow the CPU to
ing a SLEEP or CLRWDT instruction, losing a currently prepare for execution. Instruction execution resumes
selected clock source (if the Fail-Safe Clock Monitor is on the first clock cycle following this delay.
enabled) and modifying the IRCF bits in the OSCCON
register if the internal oscillator block is the device clock
source.

PIC18F6390/6490/8390/8490
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source Clock Source Clock Ready Status
Exit Delay
before Wake-up after Wake-up Bit (OSCCON)
LP, XT, HS
OSTS
Primary Device Clock HSPLL
TCSD(2)
(PRI_IDLE mode) EC, RC, INTRC(1) —
INTOSC(3) IOFS
LP, XT, HS TOST(4)
OSTS
HSPLL TOST + trc(4)
T1OSC or INTRC(1)
EC, RC, INTRC(1) TCSD(2) —
(3)
INTOSC TIOBST(5) IOFS
LP, XT, HS TOST(5)
OSTS
HSPLL TOST + trc(4)
INTOSC(3)
EC, RC, INTRC(1) TCSD(2) —
(3)
INTOSC None IOFS
LP, XT, HS TOST(4)
OSTS
None HSPLL TOST + trc(4)
(Sleep mode) EC, RC, INTRC(1) TCSD(2) —
INTOSC(3) TIOBST(5) IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is
also designated as TPLL.
5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
4.0 RESET 4.1 RCON Register
The PIC18F6390/6490/8390/8490 devices differentiate Device Reset events are tracked through the RCON
between various kinds of Reset: register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
a) Power-on Reset (POR)
occurred. In most cases, these bits can only be set by
b) MCLR Reset during normal operation the event and must be cleared by the application after
c) MCLR Reset during power-managed modes the event. The state of these flag bits, taken together,
d) Watchdog Timer (WDT) Reset (during can be read to indicate the type of Reset that just
execution) occurred. This is described in more detail in
e) Programmable Brown-out Reset (BOR) Section 4.6 “Reset State of Registers”.
f) RESET Instruction The RCON register also has control bits for setting
g) Stack Full Reset interrupt priority (IPEN) and software control of the
h) Stack Underflow Reset BOR (SBOREN). Interrupt priority is discussed in
Section 8.0 “Interrupts”. BOR is covered in
This section discusses Resets generated by MCLR, Section 4.4 “Brown-out Reset (BOR)”.
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET
Instruction
Stack Stack Full/Underflow Reset

Pointer
External Reset
MCLRE
MCLR ( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse

Detect
VDD
Brown-out
Reset
BOREN S
OST/PWRT
OST 1024 Cycles
Chip_Reset
10-Bit Ripple Counter R Q
OSC1
32 μs
PWRT 65.5 ms
INTRC(1) 11-Bit Ripple Counter
Enable PWRT
Enable OST(2)
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.

PIC18F6390/6490/8390/8490
REGISTER 4-1: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
Legend:
bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).

PIC18F6390/6490/8390/8490
4.2 Master Clear (MCLR) FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
The MCLR pin provides a method for triggering a hard
SLOW VDD POWER-UP)
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 Extended MCU devices
have a noise filter in the MCLR Reset path which VDD VDD
detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets, D R
including the WDT. R1
MCLR
In PIC18F6390/6490/8390/8490 devices, the MCLR
input can be disabled with the MCLRE Configuration C PIC18FXXXX
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 9.7 “PORTG, TRISG and LATG
Registers” for more information.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
4.3 Power-on Reset (POR) The diode D helps discharge the capacitor
quickly when VDD powers down.
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This 2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
allows the device to start in the initialized state when
the device’s electrical specification.
VDD is adequate for operation.
3: R1 ≥ 1 kΩ will limit any current flowing into
To take advantage of the POR circuitry, tie the MCLR MCLR from external capacitor C, in the event
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will of MCLR/VPP pin breakdown, due to
eliminate external RC components usually needed to Electrostatic Discharge (ESD) or Electrical
create a Power-on Reset delay. A minimum rise rate for Overstress (EOS).
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.

PIC18F6390/6490/8390/8490
4.4 Brown-out Reset (BOR) Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
PIC18F6390/6490/8390/8490 devices implement a environment without having to reprogram the device to
BOR circuit that provides the user with a number of change the BOR configuration. It also allows the user
configuration and power-saving options. The BOR is to tailor device power consumption in software by
controlled by the BORV1:BORV0 and eliminating the incremental current that the BOR
BOREN1:BOREN0 Configuration bits. There are a total consumes. While the BOR current is typically very
of four BOR configurations, which are summarized in small, it may have some impact in low-power
Table 4-1. applications.
The BOR threshold is set by the BORV1:BORV0 bits. If
Note: Even when BOR is under software control,
BOR is enabled (any values of BOREN1:BOREN0
the BOR Reset voltage level is still set by
except ‘00’), any drop of VDD below VBOR (parameter
the BORV1:BORV0 Configuration bits. It
D005) for greater than TBOR (parameter 35) will reset
cannot be changed in software.
the device. A Reset may or may not occur if VDD falls
below VBOR for less than TBOR. The chip will remain in
4.4.2 DETECTING BOR
Brown-out Reset until VDD rises above VBOR.
When BOR is enabled, the BOR bit always resets to ‘0’
If the Power-up Timer is enabled, it will be invoked after
on any BOR or POR event. This makes it difficult to
VDD rises above VBOR; it then will keep the chip in
determine if a BOR event has occurred just by reading
Reset for an additional time delay, TPWRT
the state of BOR alone. A more reliable method is to
(parameter 33). If VDD drops below VBOR while the
simultaneously check the state of both POR and BOR.
Power-up Timer is running, the chip will go back into a
This assumes that the POR bit is reset to ‘1’ in software
Brown-out Reset and the Power-up Timer will be
immediately after any POR event. IF BOR is ‘0’ while
initialized. Once VDD rises above VBOR, the Power-up
POR is ‘1’, it can be reliably assumed that a BOR event
Timer will execute the additional time delay.
has occurred.
BOR and the Power-up Timer (PWRT) are
independently configured. Enabling the BOR Reset 4.4.3 DISABLING BOR IN SLEEP MODE
does not automatically enable the PWRT. When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
4.4.1 SOFTWARE ENABLED BOR
described. Whenever the device enters Sleep mode,
When BOREN1:BOREN0 = 01, the BOR can be however, the BOR is automatically disabled. When the
enabled or disabled by the user in software. This is device returns to any other operating mode, BOR is
done with the control bit, SBOREN (RCON<6>). automatically re-enabled.
Setting SBOREN enables the BOR to function as
This mode allows for applications to recover from
previously described. Clearing SBOREN disables the
brown-out situations while actively executing code,
BOR entirely. The SBOREN bit operates only in this
when the device requires BOR protection the most. At
mode; otherwise it is read as ‘0’.
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 4-1: BOR CONFIGURATIONS

BOR Configuration Status of
SBOREN BOR Operation
BOREN1 BOREN0 (RCON<6>)
0 0 Unavailable BOR is disabled; must be enabled by reprogramming the Configuration
bits.
0 1 Available BOR is enabled in software; operation controlled by SBOREN.
1 0 Unavailable BOR is enabled in hardware and active during the Run and Idle modes,
disabled during Sleep mode.
1 1 Unavailable BOR is enabled in hardware; must be disabled by reprogramming the
Configuration bits.

PIC18F6390/6490/8390/8490
4.5 Device Reset Timers 4.5.3 PLL LOCK TIME-OUT
PIC18F6390/6490/8390/8490 devices incorporate With the PLL enabled in its PLL mode, the time-out
three separate on-chip timers that help regulate the sequence following a Power-on Reset is slightly
Power-on Reset process. Their main function is to different from other oscillator modes. A separate timer
ensure that the device clock is stable before code is is used to provide a fixed time-out that is sufficient for
executed. These timers are: the PLL to lock to the main oscillator frequency. This
PLL lock time-out (TPLL) is typically 2 ms and follows
• Power-up Timer (PWRT) the oscillator start-up time-out.
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out 4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
4.5.1 POWER-UP TIMER (PWRT)
1. After the POR pulse has cleared, PWRT
The Power-up Timer (PWRT) of time-out is invoked (if enabled).
PIC18F6390/6490/8390/8490 devices is an 11-bit
2. Then, the OST is activated.
counter which uses the INTRC source as the clock
input. This yields an approximate time interval of The total time-out will vary based on oscillator
2048 x 32 μs = 65.6 ms. While the PWRT is counting, configuration and the status of the PWRT. Figure 4-3,
the device is held in Reset. Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
The power-up time delay depends on the INTRC clock
Power-up Timer enabled and the device operating in
and will vary from chip-to-chip due to temperature and
HS Oscillator mode. Figures 4-3 through 4-6 also apply
process variation. See DC parameter 33 for details.
to devices operating in XT or LP modes. For devices in
The PWRT is enabled by clearing the PWRTEN RC mode and with the PWRT disabled, on the other
Configuration bit. hand, there will be no time-out at all.
4.5.2 OSCILLATOR START-UP Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire.
TIMER (OST)
Bringing MCLR high will begin execution immediately
The Oscillator Start-up Timer (OST) provides a (Figure 4-5). This is useful for testing purposes, or to
1024 oscillator cycle (from OSC1 input) delay after the synchronize more than one PIC18FXXXX device
PWRT delay is over (parameter 33). This ensures that operating in parallel.
the crystal oscillator or resonator has started and is
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power-managed modes.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS

Oscillator Power-up(2) and Brown-out Exit from
Configuration PWRTEN = 0 PWRTEN = 1 Power-Managed Mode
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) — —
RC, RCIO 66 ms(1) — —
INTIO1, INTIO2 66 ms(1) — —
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.

PIC18F6390/6490/8390/8490
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET

PIC18F6390/6490/8390/8490
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD 0V 1V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT TPLL
PLL TIME-OUT
INTERNAL RESET
Note: TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the PWRT timer.

PIC18F6390/6490/8390/8490
4.6 Reset State of Registers Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Most registers are unaffected by a Reset. Their status Power-on and Brown-out Resets, Master Clear and
is unknown on POR and unchanged by all other WDT Resets and WDT wake-ups.
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used in software to determine the nature
of the Reset.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program RCON Register STKPTR Register
Condition
Counter SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET Instruction 0000h u(2) 0 u u u u u u
Brown-out Reset 0000h u(2) 1 1 1 u 0 u u
MCLR Reset during 0000h u(2) u 1 u u u u u
power-managed Run modes
MCLR Reset during 0000h u(2) u 1 0 u u u u
power-managed Idle modes and
Sleep
WDT time-out during full power 0000h u(2) u 0 u u u u u
or power-managed Run modes
MCLR during full-power 0000h u(2) u u u u u u u
execution
Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u
Stack Underflow Reset 0000h u(2) u u u u u u 1
(STVREN = 1)
Stack Underflow Error (not an 0000h u(2) u u u u u u 1
actual Reset, STVREN = 0)
WDT time-out during PC + 2(1) u(2) u 0 0 u u u u
power-managed Idle or
Sleep modes
Interrupt exit from PC + 2(1) u(2) u u 0 u u u u
power-managed modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

PIC18F6390/6490/8390/8490
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
Applicable Power-on Reset, WDT Reset Wake-up via WDT
Register
Devices Brown-out Reset RESET Instruction or Interrupt
Stack Resets
TOSU 6X90 8X90 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 6X90 8X90 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 6X90 8X90 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 6X90 8X90 00-0 0000 00-0 0000 uu-u uuuu(3)
PCLATU 6X90 8X90 ---0 0000 ---0 0000 ---u uuuu
PCLATH 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
PCL 6X90 8X90 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 6X90 8X90 --00 0000 --00 0000 --uu uuuu
TBLPTRH 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TABLAT 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
PRODH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 6X90 8X90 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 6X90 8X90 1111 1111 1111 1111 uuuu uuuu(1)
INTCON3 6X90 8X90 1100 0000 1100 0000 uuuu uuuu(1)
INDF0 6X90 8X90 N/A N/A N/A
POSTINC0 6X90 8X90 N/A N/A N/A
POSTDEC0 6X90 8X90 N/A N/A N/A
PREINC0 6X90 8X90 N/A N/A N/A
PLUSW0 6X90 8X90 N/A N/A N/A
FSR0H 6X90 8X90 ---- xxxx ---- uuuu ---- uuuu
FSR0L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: These registers are cleared on POR and unchanged on BOR.

PIC18F6390/6490/8390/8490
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Register
Stack Resets
BSR 6X90 8X90 ---- 0000 ---- 0000 ---- uuuu
STATUS 6X90 8X90 ---x xxxx ---u uuuu ---u uuuu
TMR0H 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TMR0L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
OSCCON 6X90 8X90 0100 q000 0100 00q0 uuuu uuqu
HLVDCON 6X90 8X90 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 6X90 8X90 ---- ---0 ---- ---0 ---- ---u
RCON(4) 6X90 8X90 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 6X90 8X90 0000 0000 u0uu uuuu uuuu uuuu
TMR2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
PR2 6X90 8X90 1111 1111 1111 1111 1111 1111
T2CON 6X90 8X90 -000 0000 -000 0000 -uuu uuuu
SSPBUF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
SSPCON1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
SSPCON2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
hardware stack.

PIC18F6390/6490/8390/8490
MCLR Resets
Register
Stack Resets
ADRESH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 6X90 8X90 --00 0000 --00 0000 --uu uuuu
ADCON1 6X90 8X90 --00 0000 --00 0000 --uu uuuu
ADCON2 6X90 8X90 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 6X90 8X90 --00 0000 --00 0000 --uu uuuu
CCPR2H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 6X90 8X90 --00 0000 --00 0000 --uu uuuu
CVRCON 6X90 8X90 000- 0000 000- 0000 uuu- uuuu
CMCON 6X90 8X90 0000 0111 0000 0111 uuuu uuuu
TMR3H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 6X90 8X90 0000 0000 uuuu uuuu uuuu uuuu
SPBRG1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
RCREG1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXREG1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXSTA1 6X90 8X90 0000 0010 0000 0010 uuuu uuuu
RCSTA1 6X90 8X90 0000 000x 0000 000x uuuu uuuu
IPR3 6X90 8X90 -111 ---- -111 ---- -uuu ----
PIR3 6X90 8X90 -000 ---- -000 ---- -uuu ----(1)
PIE3 6X90 8X90 -000 ---- -000 ---- -uuu ----
IPR2 6X90 8X90 11-- 1111 11-- 1111 uu-- uuuu
PIR2 6X90 8X90 00-- 0000 00-- 0000 uu-- uuuu(1)
PIE2 6X90 8X90 00-- 0000 00-- 0000 uu-- uuuu
IPR1 6X90 8X90 -111 1111 -111 1111 -uuu uuuu
PIR1 6X90 8X90 -000 0000 -000 0000 -uuu uuuu(1)
PIE1 6X90 8X90 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 6X90 8X90 00-0 0000 00-0 0000 uu-u uuuu
hardware stack.

PIC18F6390/6490/8390/8490
MCLR Resets
Register
Stack Resets
TRISJ 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISH 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISG 6X90 8X90 ---1 1111 ---1 1111 ---u uuuu
TRISF 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISE 6X90 8X90 1111 ---- 1111 ---- uuuu ----
TRISD 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISC 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISB 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
(5)
TRISA 6X90 8X90 1111 1111(5) 1111 1111(5) uuuu uuuu(5)
LATJ 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATG 6X90 8X90 ---x xxxx ---u uuuu ---u uuuu
LATF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATE 6X90 8X90 xxxx ---- uuuu ---- uuuu ----
LATD 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 6X90 8X90 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)
PORTJ 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTG 6X90 8X90 --xx xxxx --uu uuuu --uu uuuu
PORTF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 6X90 8X90 xxxx ---- uuuu ---- uuuu ----
PORTD 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
(5) (5) (5)
PORTA 6X90 8X90 xx0x 0000 uu0u 0000 uuuu uuuu(5)
SPBRGH1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 6X90 8X90 01-0 0-00 01-0 0-00 uu-u u-uu
hardware stack.

PIC18F6390/6490/8390/8490
MCLR Resets
Register
Stack Resets
LCDDATA23 6X90 8X90 xxxx xxxx 0000 0000 uuuu uuuu
SPBRG2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
RCREG2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXREG2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TXSTA2 6X90 8X90 0000 -010 0000 -010 uuuu -uuu
RCSTA2 6X90 8X90 0000 000x 0000 000x uuuu uuuu
hardware stack.

PIC18F6390/6490/8390/8490
MCLR Resets
Register
Stack Resets
LCDSE5 6X90 8X90 0000 0000 0000 0000(6) uuuu uuuu
(6)
LCDSE3 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
LCDCON 6X90 8X90 000- 0000 000- 0000 uuu- uuuu
LCDPS 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
hardware stack.

PIC18F6390/6490/8390/8490
5.0 MEMORY ORGANIZATION 5.1 Program Memory Organization
There are two types of memory in PIC18 Flash PIC18 microcontrollers implement a 21-bit program
microcontroller devices: counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
• Program Memory
the upper boundary of the physically implemented
• Data RAM memory and the 2-Mbyte address will return all ‘0’s (a
As Harvard architecture devices, the data and program NOP instruction).
memories use separate busses; this allows for The PIC18FX390 have 8 Kbytes of Flash memory and
concurrent access of the two memory spaces. can store up to 4,096 single-word instructions and the
Additional detailed information on the operation of the PIC18FX490 have 16 Kbytes of Flash memory and can
Flash program memory is provided in Section 6.0 store up to 8,192 single-word instructions.
“Flash Program Memory”. PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory maps for
PIC18F6390/6490/8390/8490 devices are shown in
Figure 5-1.
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F6390/6490/8390/8490 DEVICES
PIC18F6390/8390 PIC18F6490/8490
PC<20:0> PC<20:0>
CALL,RCALL,RETURN 21 CALL,RCALL,RETURN 21
RETFIE,RETLW RETFIE,RETLW
Stack Level 1 Stack Level 1
• •
• •
• •
Stack Level 31 Stack Level 31
Reset Vector 0000h Reset Vector 0000h
High-Priority Interrupt Vector 0008h High-Priority Interrupt Vector 0008h
Low-Priority Interrupt Vector 0018h Low-Priority Interrupt Vector 0018h
On-Chip
Program Memory On-Chip
1FFFh Program Memory
2000h
3FFFh
4000h
User Memory Space
User Memory Space
Read ‘0’ Read ‘0’
1FFFFFh 1FFFFFh

PIC18F6390/6490/8390/8490
5.1.1 PROGRAM COUNTER The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer. The stack space is not part of either
The Program Counter (PC) specifies the address of the
program or data space. The Stack Pointer is readable
instruction to fetch for execution. The PC is 21 bits wide
and writable and the address on the top of the stack is
and is contained in three separate 8-bit registers. The
readable and writable through the top-of-stack Special
low byte, known as the PCL register, is both readable
Function Registers. Data can also be pushed to, or
and writable. The high byte, or PCH register, contains
popped from the stack using these registers.
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the A CALL type instruction causes a push onto the stack;
PCLATH register. The upper byte is called PCU. This the Stack Pointer is first incremented and the location
register contains the PC<20:16> bits; it is also not pointed to by the Stack Pointer is written with the
directly readable or writable. Updates to the PCU contents of the PC (already pointing to the instruction
register are performed through the PCLATU register. following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
The contents of PCLATH and PCLATU are transferred
pointed to by the STKPTR register are transferred to
to the program counter by any operation that writes
the PC and then the Stack Pointer is decremented.
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an The Stack Pointer is initialized to ‘00000’ after all
operation that reads PCL. This is useful for computed Resets. There is no RAM associated with the location
offsets to the PC (see Section 5.1.4.1 “Computed corresponding to a Stack Pointer value of ‘00000’; this
GOTO”). is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
5.1.2.1 Top-of-Stack Access
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address Only the top of the return address stack (TOS) is read-
sequential instructions in the program memory. able and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack
The CALL, RCALL, GOTO and program branch
location pointed to by the lower five bits of the STKPTR
instructions write to the program counter directly. For
register (Figure 5-2). This allows users to implement a
these instructions, the contents of PCLATH and
software stack if necessary. After a CALL, RCALL or
PCLATU are not transferred to the program counter.
interrupt, the software can read the pushed value by
reading the TOSU:TOSH:TOSL registers. These
5.1.2 RETURN ADDRESS STACK
values can be placed on a user-defined software stack.
The return address stack allows any combination of up At return time, the software can return these values to
to 31 program calls and interrupts to occur. The PC is TOSU:TOSH:TOSL and do a return.
pushed onto the stack when a CALL or RCALL instruc-
The user must disable the global interrupt enable bits
tion is executed, or an interrupt is Acknowledged. The
while accessing the stack to prevent inadvertent stack
PC value is pulled off the stack on a RETURN, RETLW
corruption.
or a RETFIE instruction. PCLATU and PCLATH are not
affected by any of the RETURN or CALL instructions.
FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack <20:0>
11111
11110
Top-of-Stack Registers 11101 Stack Pointer
TOSU TOSH TOSL STKPTR<4:0>

00h 1Ah 34h 00010
00011
Top-of-Stack 001A34h 00010
000D58h 00001
00000

PIC18F6390/6490/8390/8490
5.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
The STKPTR register (Register 5-1) contains the Stack
to the PC and sets the STKUNF bit, while the Stack
Pointer value, the STKFUL (Stack Full) status bit and
Pointer remains at zero. The STKUNF bit will remain
the STKUNF (Stack Underflow) status bits. The value
set until cleared by software, or until a POR occurs.
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the Note: Returning a value of zero to the PC on an
stack and decrements after values are popped off the underflow has the effect of vectoring the
stack. On Reset, the Stack Pointer value will be zero. program to the Reset vector where the
The user may read and write the Stack Pointer value. stack conditions can be verified and
This feature can be used by a Real-Time Operating appropriate actions can be taken. This is
System (RTOS) for return stack maintenance. not the same as a Reset, as the contents
After the PC is pushed onto the stack 31 times (without of the SFRs are not affected.
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a 5.1.2.3 PUSH and POP Instructions
POR. Since the Top-of-Stack is readable and writable, the
The action that takes place when the stack becomes ability to push values onto the stack and pull values off
full depends on the state of the STVREN (Stack Over- the stack, without disturbing normal program execu-
flow Reset Enable) Configuration bit. (Refer to tion, is a desirable feature. The PIC18 instruction set
Section 23.1 “Configuration Bits” for a description of includes two instructions, PUSH and POP, that permit
the device Configuration bits.) If STVREN is set the TOS to be manipulated under software control.
(default), the 31st push will push the (PC + 2) value TOSU, TOSH and TOSL can be modified to place data
onto the stack, set the STKFUL bit and reset the or a return address on the stack.
device. The STKFUL bit will remain set and the Stack The PUSH instruction places the current PC value onto
Pointer will be set to zero. the stack. This increments the Stack Pointer and loads
If STVREN is cleared, the STKFUL bit will be set on the the current PC value onto the stack.
31st push and the Stack Pointer will increment to 31. The POP instruction discards the current TOS by
Any additional pushes will not overwrite the 31st push decrementing the Stack Pointer. The previous value
and STKPTR will remain at 31. pushed onto the stack then becomes the TOS value.
REGISTER 5-1: STKPTR: STACK POINTER REGISTER

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend: C = Clearable only bit

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

PIC18F6390/6490/8390/8490
5.1.2.4 Stack Full and Underflow Resets 5.1.4 LOOK-UP TABLES IN PROGRAM
Device Resets on stack overflow and stack underflow MEMORY
conditions are enabled by setting the STVREN bit in There may be programming situations that require the
Configuration Register 4L. When STVREN is set, a full creation of data structures, or look-up tables, in
or underflow will set the appropriate STKFUL or program memory. For PIC18 devices, look-up tables
STKUNF bit and then cause a device Reset. When can be implemented in two ways:
STVREN is cleared, a full or underflow condition will set
• Computed GOTO
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are • Table Reads
cleared by the user software or a Power-on Reset.
5.1.4.1 Computed GOTO
5.1.3 FAST REGISTER STACK A computed GOTO is accomplished by adding an offset
A Fast Register Stack is provided for the STATUS, to the program counter. An example is shown in
WREG and BSR registers, to provide a “fast return” Example 5-2.
option for interrupts. This stack is only one level deep A look-up table can be formed with an ADDWF PCL
and is neither readable nor writable. It is loaded with the instruction and a group of RETLW nn instructions. The
current value of the corresponding register when the W register is loaded with an offset into the table before
processor vectors for an interrupt. All interrupt sources executing a call to that table. The first instruction of the
will push values into the stack registers. The values in called routine is the ADDWF PCL instruction. The next
the registers are then loaded back into the working instruction executed will be one of the RETLW nn
registers if the RETFIE, FAST instruction is used to instructions that returns the value ‘nn’ to the calling
return from the interrupt. function.
If both low and high-priority interrupts are enabled, the The offset value (in WREG) specifies the number of
stack registers cannot be used reliably to return from bytes that the program counter should advance and
low-priority interrupts. If a high-priority interrupt occurs should be multiples of 2 (LSb = 0).
while servicing a low-priority interrupt, the Stack In this method, only one data byte may be stored in
register values stored by the low-priority interrupt will each instruction location and room on the return
be overwritten. In these cases, users must save the key address stack is required.
registers in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the EXAMPLE 5-2: COMPUTED GOTO USING
Fast Register Stack for returns from interrupt. If no AN OFFSET VALUE
interrupts are used, the Fast Register Stack can be MOVF OFFSET, W
used to restore the STATUS, WREG and BSR registers CALL TABLE
at the end of a subroutine call. To use the Fast Register ORG nn00h
Stack for a subroutine call, a CALL label, FAST TABLE ADDWF PCL
instruction must be executed to save the STATUS, RETLW nnh
WREG and BSR registers to the Fast Register Stack. A RETLW nnh
RETURN, FAST instruction is then executed to restore RETLW nnh
these registers from the Fast Register Stack. .
.
Example 5-1 shows a source code example that uses .
the Fast Register Stack during a subroutine call and
return.
5.1.4.2 Table Reads
EXAMPLE 5-1: FAST REGISTER STACK A better method of storing data in program memory
CODE EXAMPLE allows two bytes of data to be stored in each instruction
location.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER Look-up table data may be stored two bytes per
;STACK program word while programming. The Table Pointer
• register (TBLPTR) specifies the byte address and the
• Table Latch register (TABLAT) contains the data that is
read from the program memory. Data is transferred
SUB1 •
from program memory one byte at a time.
•
RETURN FAST ;RESTORE VALUES SAVED Table read operation is discussed further in
;IN FAST REGISTER STACK Section 6.1 “Table Reads”.

PIC18F6390/6490/8390/8490
5.2 PIC18 Instruction Cycle 5.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
5.2.1 CLOCKING SCHEME through Q4. The instruction fetch and execute are pipe-
The microcontroller clock input, whether from an lined in such a manner that a fetch takes one instruction
internal or external source, is internally divided by four cycle, while the decode and execute take another
to generate four non-overlapping quadrature clocks instruction cycle. However, due to the pipelining, each
(Q1, Q2, Q3 and Q4). Internally, the program counter is instruction effectively executes in one cycle. If an
incremented on every Q1; the instruction is fetched instruction causes the program counter to change (e.g.,
from the program memory and latched into the Instruc- GOTO), then two cycles are required to complete the
tion Register (IR) during Q4. The instruction is decoded instruction (Example 5-3).
and executed during the following Q1 through Q4. The A fetch cycle begins with the Program Counter (PC)
clocks and instruction execution flow are shown in incrementing in Q1.
Figure 5-3.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKO
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5

1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

PIC18F6390/6490/8390/8490
5.2.3 INSTRUCTIONS IN PROGRAM number of single-word instructions that the PC will be
MEMORY offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction set.
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program 5.2.4 TWO-WORD INSTRUCTIONS
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location The standard PIC18 instruction set has four two-word
with an even address (LSB = 0). To maintain alignment instructions: CALL, MOVFF, GOTO and LSFR. In all
with instruction boundaries, the PC increments in steps cases, the second word of the instructions always has
of 2 and the LSB will always read ‘0’ (see Section 5.1.1 ‘1111’ as its four Most Significant bits; the other 12 bits
“Program Counter”). are literal data, usually a data memory address.
Figure 5-4 shows an example of how instruction words The use of ‘1111’ in the 4 MSbs of an instruction
are stored in the program memory. specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
The CALL and GOTO instructions have the absolute pro- first word – the data in the second word is accessed
gram memory address embedded into the instruction. and used by the instruction sequence. If the first word
Since instructions are always stored on word bound- is skipped for some reason and the second word is
aries, the data contained in the instruction is a word executed by itself, a NOP is executed instead. This is
address. The word address is written to PC<20:1>, necessary for cases when the two-word instruction is
which accesses the desired byte address in program preceded by a conditional instruction that changes the
memory. Instruction #2 in Figure 5-4 shows how the PC. Example 5-4 shows how this works.
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a Note: See Section 5.5 “Program Memory and
relative address offset, operate in the same manner. The the Extended Instruction Set” for
offset value stored in a branch instruction represents the information on two-word instructions in the
extended instruction set.
FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY

Word Address
LSB = 1 LSB = 0 ↓
Program Memory 000000h
Byte Locations → 000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
EXAMPLE 5-4: TWO-WORD INSTRUCTIONS

CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F6390/6490/8390/8490
5.3 Data Memory Organization 5.3.1 BANK SELECT REGISTER
Large areas of data memory require an efficient
Note: The operation of some aspects of data
addressing scheme to make rapid access to any
memory are changed when the PIC18
address possible. Ideally, this means that an entire
extended instruction set is enabled. See
address does not need to be provided for each read or
Section 5.6 “Data Memory and the
write operation. For PIC18 devices, this is accom-
Extended Instruction Set” for more
plished with a RAM banking scheme. This divides the
information.
memory space into 16 contiguous banks of 256 bytes.
The data memory in PIC18 devices is implemented as Depending on the instruction, each location can be
static RAM. Each register in the data memory has a addressed directly by its full 12-bit address, or an 8-bit
12-bit address, allowing up to 4096 bytes of data low-order address and a 4-bit Bank Pointer.
memory. The memory space is divided into as many Most instructions in the PIC18 instruction set make use
as 16 banks that contain 256 bytes each; of the Bank Pointer, known as the Bank Select Register
PIC18F6390/6490/8390/8490 devices implement (BSR). This SFR holds the 4 Most Significant bits of a
only 4 banks. Figure 5-5 shows the data memory location’s address; the instruction itself includes the
organization for the PIC18F6390/6490/8390/8490 8 Least Significant bits. Only the four lower bits of the
devices. BSR are implemented (BSR3:BSR0). The upper four
The data memory contains Special Function Registers bits are unused; they will always read ‘0’ and cannot be
(SFRs) and General Purpose Registers (GPRs). The written to. The BSR can be loaded directly by using the
SFRs are used for control and status of the controller MOVLB instruction.
and peripheral functions, while GPRs are used for data The value of the BSR indicates the bank in data
storage and scratchpad operations in the user’s memory; the 8 bits in the instruction show the location
application. Any read of an unimplemented location will in the bank and can be thought of as an offset from the
read as ‘0’s. bank’s lower boundary. The relationship between the
The instruction set and architecture allow operations BSR’s value and the bank division in data memory is
across all banks. The entire data memory may be shown in Figure 5-6.
accessed by Direct, Indirect or Indexed Addressing Since up to 16 registers may share the same low-order
modes. Addressing modes are discussed later in this address, the user must always be careful to ensure that
section. the proper bank is selected before performing a data
To ensure that commonly used registers (SFRs and read or write. For example, writing what should be
select GPRs) can be accessed in a single cycle, PIC18 program data to an 8-bit address of F9h, while the BSR
devices implement an Access Bank. This is a 256-byte is 0Fh will end up resetting the program counter.
memory space that provides fast access to SFRs and While any bank can be selected, only those banks that
the lower portion of GPR Bank 0 without using the are actually implemented can be read or written to.
BSR. Section 5.3.2 “Access Bank” provides a Writes to unimplemented banks are ignored, while
detailed description of the Access RAM. reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.

PIC18F6390/6490/8390/8490
FIGURE 5-5: DATA MEMORY MAP FOR PIC18F6390/6490/8390/8490 DEVICES
When a = 0:
BSR<3:0> Data Memory Map
The BSR is ignored and the
00h 000h Access Bank is used.
= 0000 Access RAM 05Fh The first 128 bytes are
Bank 0 060h
GPR general purpose RAM
FFh 0FFh (from Bank 0).
00h 100h
= 0001 The second 128 bytes are
Bank 1 GPR Special Function Registers
FFh 1FFh (from Bank 15).
= 0010 00h 200h
Bank 2 GPR When a = 1:
FFh 2FFh The BSR specifies the bank
300h used by the instruction.
= 0011
Bank 3
Access Bank
00h
Access RAM Low
5Fh
Access RAM High 60h
(SFRs) FFh
Unused
to Read as 00h
= 1110
Bank 14
EFFh
00h Unimplemented F00h
= 1111 F58h
Bank 15 F60h Banked SFRs
FFh SFR
FFFh

PIC18F6390/6490/8390/8490
FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1)
Data Memory From Opcode(2)
7 0 000h 00h 7 0
0 0 0 0 0 0 1 0 Bank 0 11 11 11 11 11 1 1 1
FFh
100h 00h
Bank 1
Bank Select(2) 200h FFh
00h
Bank 2
300h FFh
00h
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
5.3.2 ACCESS BANK Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
While the use of the BSR with an embedded 8-bit
updating the BSR first. For 8-bit addresses of 80h and
address allows users to address the entire range of
above, this means that users can evaluate and operate
data memory, it also means that the user must always
on SFRs more efficiently. The Access RAM below 60h
ensure that the correct bank is selected. Otherwise,
is a good place for data values that the user might need
data may be read from or written to the wrong location.
to access rapidly, such as immediate computational
This can be disastrous if a GPR is the intended target
results or common program variables. Access RAM
of an operation but an SFR is written to instead.
also allows for faster and more code efficient context
Verifying and/or changing the BSR for each read or
saving and switching of variables.
write to data memory can become very inefficient.
The mapping of the Access Bank is slightly different
To streamline access for the most commonly used data
when the extended instruction set is enabled (XINST
memory locations, the data memory is configured with
Configuration bit = 1). This is discussed in more detail
an Access Bank, which allows users to access a
in Section 5.6.3 “Mapping the Access Bank in
mapped block of memory without specifying a BSR.
Indexed Literal Offset Mode”.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
5.3.3 GENERAL PURPOSE
memory (60h-FFh) in Block 15. The lower half is known
REGISTER FILE
as the “Access RAM” and is composed of GPRs. This
upper half is where the device’s SFRs are mapped. PIC18 devices may have banked memory in the GPR
These two areas are mapped contiguously in the area. This is data RAM, which is available for use by all
Access Bank and can be addressed in a linear fashion instructions. GPRs start at the bottom of Bank 0
by an 8-bit address (Figure 5-5). (address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
The Access Bank is used by core PIC18 instructions
Power-on Reset and are unchanged on all other
that include the Access RAM bit (the ‘a’ parameter in
Resets.
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.

PIC18F6390/6490/8390/8490
5.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
The Special Function Registers (SFRs) are registers Resets and interrupts) and those related to the
used by the CPU and peripheral modules for controlling peripheral functions. The Reset and Interrupt registers
the desired operation of the device. These registers are are described in their respective chapters, while the
implemented as static RAM. SFRs start at the top of ALU’s STATUS register is described later in this
data memory (FFFh) and extend downward to occupy section. Registers related to the operation of the
three-quarters of Bank 15 (from F40h to FFFh). A list of peripheral features are described in the chapter for that
these registers is given in Table 5-1 and Table 5-2. peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES
Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1
(1)
FFEh TOSH FDEh POSTINC2 FBEh CCPR1L F9Eh PIR1
FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1
FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch MEMCON(3)
FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3)
(2)
FF9h PCL FD9h FSR2L FB9h — F99h TRISH(3)
(2)
FF8h TBLPTRU FD8h STATUS FB8h — F98h TRISG
FF7h TBLPTRH FD7h TMR0H FB7h —(2) F97h TRISF
(2)
FF6h TBLPTRL FD6h TMR0L FB6h — F96h TRISE
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD
FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3)
FF0h INTCON3 FD0h RCON FB0h —(2) F90h LATH(3)
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF
FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE
FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC
(2)
FEAh FSR0H FCAh T2CON FAAh — F8Ah LATB
FE9h FSR0L FC9h SSPBUF FA9h —(2) F89h LATA
FE8h WREG FC8h SSPADD FA8h —(2) F88h PORTJ(3)
FE7h INDF1(1) FC7h SSPSTAT FA7h —(2) F87h PORTH(3)
(1) (2)
FE6h POSTINC1 FC6h SSPCON1 FA6h — F86h PORTG
FE5h POSTDEC1(1) FC5h SSPCON2 FA5h IPR3 F85h PORTF
FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE
FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA
Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.
3: This register is not available on 64-pin devices.
4: This register is implemented but unused on 64-pin devices.

PIC18F6390/6490/8390/8490
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES
(CONTINUED)
Address Name Address Name Address Name Address Name

(3)
F7Fh SPBRGH1 F6Fh SPBRG2 F5Fh LCDSE5 F4Fh —(2)
(3)
F7Eh BAUDCON1 F6Eh RCREG2 F5Eh LCDSE4 F4Eh —(2)
F7Dh —(2) F6Dh TXREG2 F5Dh LCDSE3 F4Dh —(2)
(4)
F7Ch LCDDATA23 F6Ch TXSTA2 F5Ch LCDSE2 F4Ch —(2)
F7Bh LCDDATA22(4) F6Bh RCSTA2 F5Bh LCDSE1 F4Bh —(2)
(4)
F7Ah LCDDATA21 F6Ah LCDDATA10 F5Ah LCDSE0 F4Ah —(2)
F79h LCDDATA20 F69h LCDDATA9 F59h LCDCON F49h —(2)
F78h LCDDATA19 F68h LCDDATA8 F58h LCDPS F48h —(2)
(2)
F77h LCDDATA18 F67h LCDDATA7 F57h — F47h —(2)
(4) (2)
F75h LCDDATA16(4) F65h LCDDATA5(4) F55h —(2) F45h —(2)
(4) (2)
(2)
F72h LCDDATA13 F62h LCDDATA2 F52h —(2) F42h —(2)
F71h LCDDATA12 F61h LCDDATA1 F51h —(2) F41h —(2)
(4) (2)
Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.
3: This register is not available on 64-pin devices.
4: This register is implemented but unused on 64-pin devices.

PIC18F6390/6490/8390/8490
TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY
Value on Details
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR on page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 59, 66

TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 59, 66
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 59, 66
STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 59, 67
PCLATU — — — Holding Register for PC<20:16> ---0 0000 59, 66
PCLATH Holding Register for PC<15:8> 0000 0000 59, 66
PCL PC Low Byte (PC<7:0>) 0000 0000 59, 66
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 59, 88
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 59, 88
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 59, 88
TABLAT Program Memory Table Latch 0000 0000 59, 88
PRODH Product Register High Byte xxxx xxxx 59, 91
PRODL Product Register Low Byte xxxx xxxx 59, 91
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 59, 95
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 59, 96
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 59, 97
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 59, 82
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 59, 83
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 59, 83
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 59, 83
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register), N/A 59, 83
value of FSR0 offset by W
FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 59, 82
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 59, 82
WREG Working Register xxxx xxxx 59
BSR — — — — Bank Select Register ---- 0000 60, 71
STATUS — — — N OV Z DC C ---x xxxx 60, 80
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.

PIC18F6390/6490/8390/8490
TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)
Value on Details
POR, BOR on page:
TMR0H Timer0 Register High Byte 0000 0000 60, 132

TMR0L Timer0 Register Low Byte xxxx xxxx 60, 132
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 60, 131
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 38, 60
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 60, 251
WDTCON — — — — — — — SWDTEN --- ---0 60, 288
(1)
RCON IPEN SBOREN — RI TO PD POR BOR 0q-1 11q0 52, 60,
107
TMR1H Timer1 Register High Byte xxxx xxxx 60, 137
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 60, 135
TMR2 Timer2 Register 0000 0000 60, 141
PR2 Timer2 Period Register 1111 1111 60, 141
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 60, 141
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 60, 158,
166
SSPADD MSSP Address Register in I2C™ Slave Mode. MSSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 60, 166
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 60, 158,
167
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 60, 159,
168
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 60, 169
ADRESH A/D Result Register High Byte xxxx xxxx 61, 240
ADRESL A/D Result Register Low Byte xxxx xxxx 61, 240
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 61, 231
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 61, 232
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 61, 233
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 61, 152,
155
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 61, 152,
155
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 61, 147
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 61, 152,
155
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 61, 152,
155
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 61, 147
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 61, 247
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 61, 241
TMR3H Timer3 Register High Byte xxxx xxxx 61, 145
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 61, 143
INTOSC Modes”.
read-only.

PIC18F6390/6490/8390/8490
Value on Details
POR, BOR on page:
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 61, 201
RCREG1 EUSART1 Receive Register 0000 0000 61, 208
TXREG1 EUSART1 Transmit Register 0000 0000 61, 206
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 61, 198
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 61, 199
IPR3 — LCDIP RC2IP TX2IP — — — — -111 ---- 61, 106
PIR3 — LCDIF RC2IF TX2IF — — — — -000 ---- 61, 100
PIE3 — LCDIE RC2IE TX2IE — — — — -000 ---- 61, 103
IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 11-- 1111 61, 105
PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 00-- 0000 61, 99
PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 00-- 0000 61, 102
IPR1 — ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 61, 104
PIR1 — ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 61, 98
PIE1 — ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 61, 101
OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 35, 61
TRISJ(2) PORTJ Data Direction Register 1111 1111 62, 130
TRISH(2) PORTH Data Direction Register 1111 1111 62, 128
TRISG — — — PORTG Data Direction Register ---1 1111 62, 126
TRISF PORTF Data Direction Register 1111 1111 62, 124
TRISE PORTE Data Direction Register — — — — 1111 ---- 62, 121
TRISD PORTD Data Direction Register 1111 1111 62, 119
TRISC PORTC Data Direction Register 1111 1111 62, 117
TRISB PORTB Data Direction Register 1111 1111 62, 114
TRISA TRISA7(5) TRISA6(5) PORTA Data Direction Register 1111 1111 62, 111
LATJ(2) LATJ Data Output Register xxxx xxxx 62, 130
LATH(2) LATH Data Output Register xxxx xxxx 62, 128
LATG — — — LATG Data Output Register ---x xxxx 62, 126
LATF LATF Data Output Register xxxx xxxx 62, 124
LATE LATE Data Output Register — — — — xxxx ---- 62, 121
LATD LATD Data Output Register xxxx xxxx 62, 119
LATC LATC Data Output Register xxxx xxxx 62, 117
LATB LATB Data Output Register xxxx xxxx 62, 114
LATA LATA7(5) LATA6(5) LATA Data Output Register xxxx xxxx 62, 111
PORTJ(2) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 62, 130
PORTH(2) Read PORTH pins, Write PORTH Data Latch xxxx xxxx 62, 128
PORTG — — RG5(4) Read PORTG pins <4:0>, Write PORTG Data Latch <4:0> --xx xxxx 62, 126
PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 62, 124
PORTE Read PORTE pins, Write PORTE Data Latch — — — — xxxx ---- 62, 121
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 62, 119
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 62, 117
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 62, 114
PORTA RA7(5) RA6(5) Read PORTA pins, Write PORTA Data Latch xx0x 0000 62, 111
INTOSC Modes”.
read-only.

PIC18F6390/6490/8390/8490
Value on Details
POR, BOR on page:
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 62, 201
BAUDCON1 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 62, 200
LCDDATA23(6) S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 xxxx xxxx 63, 261
LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 xxxx xxxx 63, 261
SPBRG2 AUSART2 Baud Rate Generator Register 0000 0000 63, 220
RCREG2 AUSART2 Receive Register 0000 0000 63, 224
TXREG2 AUSART2 Transmit Register 0000 0000 63, 222
TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 63, 218
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 63, 219
LCDSE5(2) SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 0000 0000 64, 261
LCDSE4(2) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 64, 260
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 64, 260
LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 000- 0000 64, 258
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 64, 259
INTOSC Modes”.
read-only.

PIC18F6390/6490/8390/8490
5.3.5 STATUS REGISTER It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
The STATUS register, shown in Register 5-2, contains
register, because these instructions do not affect the Z,
the arithmetic status of the ALU. As with any other SFR,
C, DC, OV or N bits in the STATUS register.
it can be the operand for any instruction.
For other instructions that do not affect Status bits, see
If the STATUS register is the destination for an instruc-
the instruction set summaries in Table 24-2 and
tion that affects the Z, DC, C, OV or N bits, the results of
Table 24-3.
the instruction are not written; instead, the status is
updated according to the instruction performed. There- Note: The C and DC bits operate as a borrow and
fore, the result of an instruction with the STATUS register digit borrow bit respectively, in subtraction.
as its destination may be different than intended. As an
example, CLRF STATUS will set the Z bit and leave the
remaining Status bits unchanged (‘000u u1uu’).
REGISTER 5-2: STATUS REGISTER

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC(1) C(2)
bit 7 bit 0
Legend:
bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.

PIC18F6390/6490/8390/8490
5.4 Data Addressing Modes Purpose Register File”), or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
Note: The execution of some instructions in the source for the instruction.
core PIC18 instruction set are changed
The Access RAM bit ‘a’ determines how the address is
when the PIC18 extended instruction set is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
enabled. See Section 5.6 “Data Memory
(Section 5.3.1 “Bank Select Register”) are used with
and the Extended Instruction Set” for
the address to determine the complete 12-bit address
more information.
of the register. When ‘a’ is ‘0’, the address is interpreted
While the program memory can be addressed in only as being a register in the Access Bank. Addressing that
one way – through the program counter – information uses the Access RAM is sometimes also known as
in the data memory space can be addressed in several Direct Forced Addressing mode.
ways. For most instructions, the addressing mode is A few instructions, such as MOVFF, include the entire
fixed. Other instructions may use up to three modes, 12-bit address (either source or destination) in their
depending on which operands are used and whether or op codes. In those cases, the BSR is ignored entirely.
not the extended instruction set is enabled.
The destination of the operation’s results is determined
The addressing modes are: by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
• Inherent stored back in the source register, overwriting its origi-
• Literal nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
• Direct
have a destination that is implicit in the instruction; their
• Indirect destination is either the target register being operated
An additional addressing mode, Indexed Literal Offset, on, or the W register.
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is 5.4.3 INDIRECT ADDRESSING
discussed in greater detail in Section 5.6.1 “Indexed Indirect Addressing allows the user to access a location
Addressing With Literal Offset”. in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
5.4.1 INHERENT AND LITERAL (FSRs) as pointers to the locations to be read or written
ADDRESSING to. Since the FSRs are themselves located in RAM as
Many PIC18 control instructions do not need any Special Function Registers, they can also be directly
argument at all; they either perform an operation that manipulated under program control. This makes FSRs
globally affects the device, or they operate implicitly on very useful in implementing data structures, such as
one register. This addressing mode is known as tables and arrays in data memory.
Inherent Addressing. Examples include SLEEP, RESET The registers for Indirect Addressing are also
and DAW. implemented with Indirect File Operands (INDFs) that
Other instructions work in a similar way but require an permit automatic manipulation of the pointer value with
additional explicit argument in the opcode. This is auto-incrementing, auto-decrementing or offsetting
known as Literal Addressing mode, because they with another value. This allows for efficient code using
require some literal value as an argument. Examples loops, such as the example of clearing an entire RAM
include ADDLW and MOVLW, which respectively add or bank in Example 5-5. It also enables users to perform
move a literal value to the W register. Other examples Indexed Addressing and other Stack Pointer
include CALL and GOTO, which include a 20-bit operations for program memory in data memory.
program memory address.
EXAMPLE 5-5: HOW TO CLEAR RAM
5.4.2 DIRECT ADDRESSING (BANK 1) USING
Direct Addressing specifies all or part of the source INDIRECT ADDRESSING
and/or destination address of the operation within the LFSR FSR0, 100h ;
opcode itself. The options are specified by the NEXT CLRF POSTINC0 ; Clear INDF
arguments accompanying the instruction. ; register then
; inc pointer
In the core PIC18 instruction set, bit-oriented and BTFSS FSR0H, 1 ; All done with
byte-oriented instructions use some version of Direct ; Bank1?
Addressing by default. All of these instructions include BRA NEXT ; NO, clear next
some 8-bit literal address as their Least Significant CONTINUE ; YES, continue
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General

PIC18F6390/6490/8390/8490
5.4.3.1 FSR Registers and the mapped in the SFR space but are not physically
INDF Operand implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
At the core of Indirect Addressing are three sets of
register pair. A read from INDF1, for example, reads
registers: FSR0, FSR1 and FSR2. Each represents a
the data at the address indicated by FSR1H:FSR1L.
pair of 8-bit registers, FSRnH and FSRnL. The four
Instructions that use the INDF registers as operands
upper bits of the FSRnH register are not used, so each
actually use the contents of their corresponding FSR as
FSR pair holds a 12-bit value. This represents a value
a pointer to the instruction’s target. The INDF operand
that can address the entire range of the data memory
is just a convenient way of using the pointer.
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations. Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
Indirect Addressing is accomplished with a set of
contents of the BSR and the Access RAM bit have no
Indirect File Operands, INDF0 through INDF2. These
effect on determining the target address.
can be thought of as “virtual” registers: they are
FIGURE 5-7: INDIRECT ADDRESSING

000h
Using an instruction with one of the ADDWF, INDF1, 1 Bank 0
Indirect Addressing registers as the 100h
operand.... Bank 1
200h
Bank 2
300h
...uses the 12-bit address stored in FSR1H:FSR1L
the FSR pair associated with that
7 0 7 0
register.... Bank 3
x x x x 1 1 1 1 1 1 0 0 1 1 0 0 through
Bank 13
...to determine the data memory

location to be used in that operation.
In this case, the FSR1 pair contains E00h
FCCh. This means the contents of Bank 14
location FCCh will be added to that F00h
of the W register and stored back in Bank 15
FCCh. FFFh
Data Memory

PIC18F6390/6490/8390/8490
5.4.3.2 FSR Registers and POSTINC, 5.4.3.3 Operations by FSRs on FSRs
POSTDEC, PREINC and PLUSW Indirect Addressing operations that target other FSRs
In addition to the INDF operand, each FSR register pair or virtual registers represent special cases. For exam-
also has four additional indirect operands. Like INDF, ple, using an FSR to point to one of the virtual registers
these are “virtual” registers that cannot be indirectly will not result in successful operations. As a specific
read or written to. Accessing these registers actually case, assume that FSR0H:FSR0L contains FE7h, the
accesses the associated FSR register pair, but also address of INDF1. Attempts to read the value of the
performs a specific action on its stored value. They are: INDF1, using INDF0 as an operand, will return 00h.
Attempts to write to INDF1, using INDF0 as the
• POSTDEC: accesses the FSR value, then
operand, will result in a NOP.
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then On the other hand, using the virtual registers to write to
automatically increments it by ‘1’ afterwards an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair, but without any
• PREINC: increments the FSR value by ‘1’, then
incrementing or decrementing. Thus, writing to INDF2
uses it in the operation
or POSTDEC2 will write the same value to the
• PLUSW: adds the signed value of the W register FSR2H:FSR2L.
(range of -127 to 128) to that of the FSR and uses
the new value in the operation. Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
In this context, accessing an INDF register uses the operations. Users should proceed cautiously when
value in the FSR registers without changing them. working on these registers, particularly if their code
Similarly, accessing a PLUSW register gives the FSR uses Indirect Addressing.
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the Similarly, operations by Indirect Addressing are gener-
other virtual registers changes the value of the FSR ally permitted on all other SFRs. Users should exercise
registers. the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
Operations on the FSRs with POSTDEC, POSTINC device.
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.

PIC18F6390/6490/8390/8490
5.5 Program Memory and the When using the extended instruction set, this
Extended Instruction Set addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
The operation of program memory is unaffected by the
and
use of the extended instruction set.
• The file address argument is less than or equal to
Enabling the extended instruction set adds five addi- 5Fh.
tional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and Under these conditions, the file address of the
SUBFSR. These instructions are executed as described instruction is not interpreted as the lower byte of an
in Section 5.2.4 “Two-Word Instructions”. address (used with the BSR in Direct Addressing), or
as an 8-bit address in the Access Bank. Instead, the
value is interpreted as an offset value to an Address
5.6 Data Memory and the Extended Pointer specified by FSR2. The offset and the contents
Instruction Set of FSR2 are added to obtain the target address of the
Enabling the PIC18 extended instruction set (XINST operation.
Configuration bit = 1) significantly changes certain
5.6.2 INSTRUCTIONS AFFECTED BY
aspects of data memory and its addressing.
Specifically, the use of the Access Bank for many of the INDEXED LITERAL OFFSET MODE
core PIC18 instructions is different; this is due to the Any of the core PIC18 instructions that can use Direct
introduction of a new addressing mode for the data Addressing are potentially affected by the Indexed
memory space. This mode also alters the behavior of Literal Offset Addressing mode. This includes all
Indirect Addressing using FSR2 and its associated byte-oriented and bit-oriented instructions, or almost
operands. one-half of the standard PIC18 instruction set. Instruc-
What does not change is just as important. The size of tions that only use Inherent or Literal Addressing
the data memory space is unchanged, as well as its modes are unaffected.
linear addressing. The SFR map remains the same. Additionally, byte-oriented and bit-oriented instructions
Core PIC18 instructions can still operate in both Direct are not affected if they use the Access Bank (Access
and Indirect Addressing mode; inherent and literal RAM bit is ‘1’), or include a file address of 60h or above.
instructions do not change at all. Indirect Addressing Instructions meeting these criteria will continue to
with FSR0 and FSR1 also remains unchanged. execute as before. A comparison of the different
possible addressing modes when the extended
5.6.1 INDEXED ADDRESSING WITH instruction set is enabled is shown in Figure 5-8.
LITERAL OFFSET Those who desire to use byte-oriented or bit-oriented
Enabling the PIC18 extended instruction set changes instructions in the Indexed Literal Offset mode should
the behavior of Indirect Addressing using the FSR2 note the changes to assembler syntax for this mode.
register pair and its associated file operands. Under the This is described in more detail in Section 24.2.1
proper conditions, instructions that use the Access “Extended Instruction Syntax”.
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.

PIC18F6390/6490/8390/8490
FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0 and f ≥ 60h:
The instruction executes in 060h
Direct Forced mode. ‘f’ is Bank 0
interpreted as a location in the 100h
Access RAM between 060h 00h
Bank 1
and FFFh. This is the same as through 60h
locations F60h to FFFh Bank 14
Valid range
(Bank 15) of data memory. for ‘f’
Locations below 060h are not FFh
F00h Access RAM
available in this addressing
Bank 15
mode.
F40h
SFRs
FFFh
Data Memory
When a = 0 and f ≤ 5Fh: 000h

The instruction executes in Bank 0
Indexed Literal Offset mode. ‘f’ 060h
is interpreted as an offset to the

100h 001001da ffffffff
address value in FSR2. The
two are added together to Bank 1
obtain the address of the target through
Bank 14
register for the instruction. The
address can be anywhere in FSR2H FSR2L
the data memory space.
F00h
Note that in this mode, the Bank 15
correct syntax is now: F40h
ADDWF [k], d SFRs
where ‘k’ is the same as ‘f’. FFFh
Data Memory
BSR
When a = 1 (all values of f): 000h 00000000
Bank 0
The instruction executes in
060h
Direct mode (also known as
Direct Long mode). ‘f’ is 100h
interpreted as a location in
one of the 16 banks of the data Bank 1 001001da ffffffff
memory space. The bank is through
Bank 14
designated by the Bank Select
Register (BSR). The address
can be in any implemented F00h
bank in the data memory Bank 15
space. F40h
SFRs
FFFh
Data Memory

PIC18F6390/6490/8390/8490
5.6.3 MAPPING THE ACCESS BANK IN Remapping of the Access Bank applies only to opera-
INDEXED LITERAL OFFSET MODE tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
The use of Indexed Literal Offset Addressing mode
to use Direct Addressing as before. Any indirect or
effectively changes how the lower part of Access RAM
indexed operation that explicitly uses any of the indirect
(00h to 5Fh) is mapped. Rather than containing just the
file operands (including FSR2) will continue to operate
contents of the bottom part of Bank 0, this mode maps
as standard Indirect Addressing. Any instruction that
the contents from Bank 0 and a user-defined “window”
uses the Access Bank, but includes a register address
that can be located anywhere in the data memory
of greater than 05Fh, will use Direct Addressing and
space. The value of FSR2 establishes the lower bound-
the normal Access Bank map.
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh). 5.6.4 BSR IN INDEXED LITERAL
Addresses in the Access RAM above 5Fh are mapped
OFFSET MODE
as previously described (see Section 5.3.2 “Access
Bank”). An example of Access Bank remapping in this Although the Access Bank is remapped when the
addressing mode is shown in Figure 5-9. extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 5-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL

OFFSET ADDRESSING
Example Situation:
ADDWF f, d, a 000h
Not Accessible
FSR2H:FSR2L = 120h 05Fh
Locations in the region Bank 0

from the FSR2 Pointer 100h
(120h) to the pointer plus 120h
05Fh (17Fh) are mapped Window
17Fh 00h
to the bottom of the
Bank 1 Bank 1 “Window”
Access RAM (000h-05Fh). 200h
Special File Registers at 5Fh
60h
F60h through FFFh are
mapped to 60h through Bank 2
FFh, as usual. through SFRs
Bank 0 addresses below Bank 14
5Fh are not available in FFh
this mode. They can still Access Bank
be addressed by using the F00h
BSR. Bank 15
F60h
SFRs
FFFh
Data Memory

PIC18F6390/6490/8390/8490
6.0 FLASH PROGRAM MEMORY Table reads work with byte entities. A table block
containing data, rather than program instructions, is not
In PIC18F6390/6490/8390/8490 devices, the program required to be word-aligned. Therefore, a table block can
memory is implemented as read-only Flash memory. It start and end at any byte address.
is readable over the entire VDD range during normal
Because the program memory cannot be written to or
operation. A read from program memory is executed on
erased under normal operation, the TBLWT operation is
one byte at a time.
not discussed here.
6.1 Table Reads Note 1: Although it cannot be used in

PIC18F6390/6490/8390/8490 devices in
For PIC18 devices, there are two operations that allow normal operation, the TBLWT instruction
the processor to move bytes between the program is still implemented in the instruction set.
memory space and the data RAM: table read (TBLRD) Executing the instruction takes two
and table write (TBLWT). instruction cycles, but effectively results
Table read operations retrieve data from program in a NOP.
memory and place it into the data RAM space. 2: The TBLWT instruction is available only in
Figure 6-1 shows the operation of a table read with programming modes and is used during
program memory and data RAM. In-Circuit Serial Programming™ (ICSP™).
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register, TABLAT.
FIGURE 6-1: TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.

PIC18F6390/6490/8390/8490
6.2 Control Registers TABLE 6-1: TABLE POINTER
OPERATIONS WITH TBLRD
Two control registers are used in conjunction with the
INSTRUCTIONS
TBLRD instruction: the TABLAT register and the
TBLPTR register set. Example Operation on Table Pointer
6.2.1 TABLE LATCH REGISTER (TABLAT) TBLRD* TBLPTR is not modified

TBLRD*+ TBLPTR is incremented after the read
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to TBLRD*- TBLPTR is decremented after the read
hold 8-bit data during data transfers between program TBLRD+* TBLPTR is incremented before the read
memory and data RAM.
6.2.2 TABLE POINTER REGISTER

6.3 Reading the Flash Program
(TBLPTR) Memory
The Table Pointer register (TBLPTR) addresses a byte The TBLRD instruction is used to retrieve data from
within the program memory. It is comprised of three program memory and places it into data RAM. Table
SFR registers: Table Pointer Upper Byte, Table Pointer reads from program memory are performed one byte at
High Byte and Table Pointer Low Byte a time.
(TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six TBLPTR points to a byte address in program space.
bits of TBLPTRU are used with TBLPTRH and Executing TBLRD places the byte pointed to into
TBLPTRL to form a 22-bit wide pointer. TABLAT. In addition, TBLPTR can be modified
The contents of TBLPTR indicates a location in automatically for the next table read operation.
program memory space. The low-order 21 bits allow The internal program memory is typically organized by
the device to address the full 2 Mbytes of program words. The Least Significant bit of the address selects
memory space. The 22nd bit allows access to the between the high and low bytes of the word. Figure 6-2
configuration space, including the device ID, user ID shows the interface between the internal program
locations and the Configuration bits. memory and the TABLAT.
The TBLPTR register set is updated when executing a A typical method for reading data from program memory
TBLRD in one of four ways, based on the instruction’s is shown in Example 6-1.
arguments. These are detailed in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
FIGURE 6-2: READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address) (Odd Byte Address)
TBLPTR = xxxxx1 TBLPTR = xxxxx0
Instruction Register TABLAT

FETCH TBLRD
(IR) Read Register

PIC18F6390/6490/8390/8490
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_ODD
TABLE 6-2: REGISTERS ASSOCIATED WITH READING PROGRAM FLASH MEMORY

Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
Page
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte 59
(TBLPTR<20:16>)
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 59
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 59
TABLAT Program Memory Table Latch 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
7.0 8 x 8 HARDWARE MULTIPLIER EXAMPLE 7-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
7.1 Introduction MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
All PIC18 devices include an 8 x 8 hardware multiplier
; PRODH:PRODL
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY
register. ROUTINE
Making multiplication a hardware operation allows it to MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
be completed in a single instruction cycle. This has the
; PRODH:PRODL
advantages of higher computational throughput and
BTFSC ARG2, SB ; Test Sign Bit
reduced code size for multiplication algorithms and SUBWF PRODH, F ; PRODH = PRODH
allows the PIC18 devices to be used in many ; - ARG1
applications previously reserved for digital signal MOVF ARG2, W
processors. A comparison of various hardware and BTFSC ARG1, SB ; Test Sign Bit
software multiply operations, along with the savings in SUBWF PRODH, F ; PRODH = PRODH
memory and execution time, is shown in Table 7-1. ; - ARG2
7.2 Operation
Example 7-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 7-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the signed bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
TABLE 7-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Program Time
Cycles
Routine Multiply Method Memory
(Max) @ 40 MHz @ 10 MHz @ 4 MHz
(Words)
Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs
8 x 8 unsigned
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed
Hardware multiply 6 6 600 ns 2.4 μs 6 μs
16 x 16 unsigned
Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs
16 x 16 signed
Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs

PIC18F6390/6490/8390/8490
Example 7-3 shows the sequence to do a 16 x 16 EQUATION 7-2: 16 x 16 SIGNED
unsigned multiplication. Equation 7-1 shows the MULTIPLICATION
algorithm that is used. The 32-bit result is stored in four ALGORITHM
registers (RES3:RES0).
RES3:RES0= ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
EQUATION 7-1: 16 x 16 UNSIGNED (ARG1H • ARG2L • 28) +
MULTIPLICATION (ARG1L • ARG2H • 28) +
ALGORITHM (ARG1L • ARG2L) +
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L (-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
= (ARG1H • ARG2H • 216) + (-1 • ARG1H<7> • ARG2H:ARG2L • 216)
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
EXAMPLE 7-4: 16 x 16 SIGNED
(ARG1L • ARG2L)
MULTIPLY ROUTINE
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
EXAMPLE 7-3: 16 x 16 UNSIGNED ; PRODH:PRODL
MULTIPLY ROUTINE MOVFF PRODH, RES1 ;
MOVF ARG1L, W MOVFF PRODL, RES0 ;
MULWF ARG2L ; ARG1L * ARG2L-> ;
; PRODH:PRODL MOVF ARG1H, W
MOVFF PRODH, RES1 ; MULWF ARG2H ; ARG1H * ARG2H ->
MOVFF PRODL, RES0 ; ; PRODH:PRODL
; MOVFF PRODH, RES3 ;
MOVF ARG1H, W MOVFF PRODL, RES2 ;
MULWF ARG2H ; ARG1H * ARG2H-> ;
; PRODH:PRODL MOVF ARG1L, W
MOVFF PRODH, RES3 ; MULWF ARG2H ; ARG1L * ARG2H ->
MOVFF PRODL, RES2 ; ; PRODH:PRODL
; MOVF PRODL, W ;
MOVF ARG1L, W ADDWF RES1, F ; Add cross
MULWF ARG2H ; ARG1L * ARG2H-> MOVF PRODH, W ; products
; PRODH:PRODL ADDWFC RES2, F ;
MOVF PRODL, W ; CLRF WREG ;
ADDWF RES1, F ; Add cross ADDWFC RES3, F ;
MOVF PRODH, W ; products ;
ADDWFC RES2, F ; MOVF ARG1H, W ;
CLRF WREG ; MULWF ARG2L ; ARG1H * ARG2L ->
ADDWFC RES3, F ; ; PRODH:PRODL
; MOVF PRODL, W ;
MOVF ARG1H, W ; ADDWF RES1, F ; Add cross
MULWF ARG2L ; ARG1H * ARG2L-> MOVF PRODH, W ; products
; PRODH:PRODL ADDWFC RES2, F ;
MOVF PRODL, W ; CLRF WREG ;
ADDWF RES1, F ; Add cross ADDWFC RES3, F ;
MOVF PRODH, W ; products ;
ADDWFC RES2, F ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
CLRF WREG ; BRA SIGN_ARG1 ; no, check ARG1
ADDWFC RES3, F ; MOVF ARG1L, W ;
SUBWF RES2 ;
Example 7-4 shows the sequence to do a 16 x 16 MOVF ARG1H, W ;
signed multiply. Equation 7-2 shows the algorithm SUBWFB RES3
;
used. The 32-bit result is stored in four registers
SIGN_ARG1
(RES3:RES0). To account for the signed bits of the
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
arguments, the MSb for each argument pair is tested BRA CONT_CODE ; no, done
and the appropriate subtractions are done. MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:

PIC18F6390/6490/8390/8490
8.0 INTERRUPTS When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
The PIC18F6390/6490/8390/8490 devices have compatible with PIC® mid-range devices. In
multiple interrupt sources and an interrupt priority fea- Compatibility mode, the interrupt priority bits for each
ture that allows most interrupt sources to be assigned source have no effect. INTCON<6> is the PEIE bit,
a high-priority level or a low-priority level. The high- which enables/disables all peripheral interrupt sources.
priority interrupt vector is at 0008h and the low-priority INTCON<7> is the GIE bit, which enables/disables all
interrupt vector is at 0018h. High-priority interrupt interrupt sources. All interrupts branch to address
events will interrupt any low-priority interrupts that may 0008h in Compatibility mode.
be in progress.
When an interrupt is responded to, the global interrupt
There are thirteen registers which are used to control enable bit is cleared to disable further interrupts. If the
interrupt operation. These registers are: IPEN bit is cleared, this is the GIE bit. If interrupt priority
• RCON levels are used, this will be either the GIEH or GIEL bit.
• INTCON High-priority interrupt sources can interrupt a low-
priority interrupt. Low-priority interrupts are not
• INTCON2
processed while high-priority interrupts are in progress.
• INTCON3
The return address is pushed onto the stack and the
• PIR1, PIR2, PIR3
PC is loaded with the interrupt vector address (0008h
• PIE1, PIE2, PIE3 or 0018h). Once in the Interrupt Service Routine, the
• IPR1, IPR2, IPR3 source(s) of the interrupt can be determined by polling
It is recommended that the Microchip header files the interrupt flag bits. The interrupt flag bits must be
supplied with MPLAB® IDE be used for the symbolic bit cleared in software before re-enabling interrupts to
names in these registers. This allows the assembler/ avoid recursive interrupts.
compiler to automatically take care of the placement of The “return from interrupt” instruction, RETFIE, exits
these bits within the specified register. the interrupt routine and sets the GIE bit (GIEH or GIEL
In general, interrupt sources have three bits to control if priority levels are used), which re-enables interrupts.
their operation. They are: For external interrupt events, such as the INTx pins or
• Flag bit to indicate that an interrupt event the PORTB input change interrupt, the interrupt latency
occurred will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
• Enable bit that allows program execution to
Individual interrupt flag bits are set, regardless of the
branch to the interrupt vector address when the
status of their corresponding enable bit or the GIE bit.
flag bit is set
• Priority bit to select high priority or low priority Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers while
The interrupt priority feature is enabled by setting the
any interrupt is enabled. Doing so may
IPEN bit (RCON<7>). When interrupt priority is
cause erratic microcontroller behavior.
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.

PIC18F6390/6490/8390/8490
FIGURE 8-1: PIC18F6X90/8X90 INTERRUPT LOGIC
TMR0IF Wake-up if in
TMR0IE Idle or Sleep modes
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE Interrupt to CPU
INT1IP Vector to Location
INT2IF
INT2IE 0008h
PIR1<6:0>
PIE1<6:0> INT2IP
IPR1<6:0> INT3IF
INT3IE
INT3IP
PIR2<7:6, 3:0> GIE/GIEH
PIE2<7:6, 3:0>
IPR2<7:6, 3:0> IPEN
PIR3<6:4> IPEN
PIE3<6:4>
IPR3<6:4> PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1<6:0>
PIE1<6:0>
IPR1<6:0>
PIR2<7:6, 3:0>
PIE2<7:6, 3:0>
IPR2<7:6, 3:0> Interrupt to CPU
TMR0IF Vector to Location
TMR0IE IPEN
PIR3<6:4> 0018h
PIE3<6:4> TMR0IP
IPR3<6:4>
RBIF
RBIE
RBIP GIEH/GIE
GIEL/PEIE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
INT3IF
INT3IE
INT3IP

PIC18F6390/6490/8390/8490
8.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt
The INTCON registers are readable and writable condition occurs, regardless of the state of
registers which contain various enable, priority and flag its corresponding enable bit or the global
bits. interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)
bit 7 bit 0
Legend:
bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and
allow the bit to be cleared.

PIC18F6390/6490/8390/8490
REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP
bit 7 bit 0
Legend:
bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 INT3IP: INT3 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F6390/6490/8390/8490
REGISTER 8-3: INTCON3: INTERRUPT CONTROL REGISTER 3
INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
bit 7 bit 0
Legend:

1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F6390/6490/8390/8490
8.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt
The PIR registers contain the individual flag bits for the condition occurs, regardless of the state of
peripheral interrupts. Due to the number of peripheral its corresponding enable bit or the global
interrupt sources, there are three Peripheral Interrupt interrupt enable bit, GIE (INTCON<7>).
Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:

bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RC1IF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART receive buffer is empty
bit 4 TX1IF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
1 = TMR1 register overflowed (must be cleared in software)

PIC18F6390/6490/8390/8490
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF
bit 7 bit 0
Legend:
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock operating
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low-Voltage Detect trip point
1 = TMR3 register overflowed (must be cleared in software)
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:

PIC18F6390/6490/8390/8490
U-0 R/W-0 R-0 R/W-0 U-0 U-0 U-0 U-0
— LCDIF RC2IF TX2IF — — — —
bit 7 bit 0
Legend:

bit 6 LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected)
1 = LCD data of all COMs is output (must be cleared in software)
0 = LCD data of all COMs is not yet output
bit 5 RC2IF: AUSART Receive Interrupt Flag bit
1 = The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The AUSART receive buffer is empty
bit 4 TX2IF: AUSART Transmit Interrupt Flag bit
1 = The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The AUSART transmit buffer is full

PIC18F6390/6490/8390/8490
8.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 8-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:

bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RC1IE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TX1IE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

PIC18F6390/6490/8390/8490
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE
bit 7 bit 0
Legend:
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 BCL1IE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
1 = Enabled
0 = Disabled
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled

PIC18F6390/6490/8390/8490
U-0 R/W-0 R-0 R-0 U-0 U-0 U-0 U-0
— LCDIE RC2IE TX2IE — — — —
bit 7 bit 0
Legend:

bit 6 LCDIE: LCD Interrupt Enable bit (valid when Type-B waveform with Non-Static mode is selected)
1 = Enabled
0 = Disabled
bit 5 RC2IE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TX2IE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled

PIC18F6390/6490/8390/8490
8.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 8-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

— ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
Legend:

bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RC1IP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TX1IP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority

PIC18F6390/6490/8390/8490
R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP
bit 7 bit 0
Legend:
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 = High priority
0 = Low priority
bit 6 CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority

PIC18F6390/6490/8390/8490
U-0 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
— LCDIP RC2IP TX2IP — — — —
bit 7 bit 0
Legend:

bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected)
1 = High priority
0 = Low priority
bit 5 RC2IP: AUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TX2IP: AUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority

PIC18F6390/6490/8390/8490
8.5 RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 8-13: RCON: RESET CONTROL REGISTER

R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
Legend:
bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: Software BOR Enable bit
For details of bit operation and Reset state, see Register 4-1.
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3 TO: Watchdog Timer Time-out Flag bit
bit 2 PD: Power-Down Detection Flag bit
bit 1 POR: Power-on Reset Status bit
bit 0 BOR: Brown-out Reset Status bit

PIC18F6390/6490/8390/8490
8.6 INTx Pin Interrupts 8.7 TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1, RB2/ In 8-bit mode (which is the default), an overflow in the
INT2 and RB3/INT3 pins are edge-triggered. If the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
corresponding INTEDGx bit in the INTCON2 register is 16-bit mode, an overflow in the TMR0H:TMR0L regis-
set (= 1), the interrupt is triggered by a rising edge; if the ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt
bit is clear, the trigger is on the falling edge. When a valid can be enabled/disabled by setting/clearing enable bit,
edge appears on the RBx/INTx pin, the corresponding TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
flag bit INTxIF is set. This interrupt can be disabled by determined by the value contained in the interrupt
clearing the corresponding enable bit, INTxIE. The priority bit, TMR0IP (INTCON2<2>). See Section 10.0
interrupt flag bit must be cleared in software in the “Timer0 Module” for further details on the Timer0
Interrupt Service Routine before re-enabling the module.
interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can 8.8 PORTB Interrupt-on-Change
wake-up the processor from the power-managed
An input change on PORTB<7:4> sets flag bit, RBIF
modes if bit INTxIE was set prior to going into the
(INTCON<0>). The interrupt can be enabled/disabled
power-managed modes. If the Global Interrupt Enable
by setting/clearing enable bit, RBIE (INTCON<3>).
bit, GIE, is set, the processor will branch to the interrupt
Interrupt priority for PORTB interrupt-on-change is
vector following wake-up.
determined by the value contained in the interrupt
Interrupt priority for INT1, INT2 and INT3 is determined priority bit, RBIP (INTCON2<0>).
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and 8.9 Context Saving During Interrupts
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority During interrupts, the return PC address is saved on
interrupt source. the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 8-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS

PIC18F6390/6490/8390/8490
9.0 I/O PORTS 9.1 PORTA, TRISA and
LATA Registers
Depending on the device selected and features
enabled, there are up to nine ports available. Some PORTA is an 8-bit wide, bidirectional port. The corre-
pins of the I/O ports are multiplexed with an alternate sponding Data Direction register is TRISA. Setting a
function from the peripheral features on the device. In TRISA bit (= 1) will make the corresponding PORTA pin
general, when a peripheral is enabled, that pin may not an input (i.e., put the corresponding output driver in a
be used as a general purpose I/O pin. high-impedance mode). Clearing a TRISA bit (= 0) will
Each port has three registers for its operation. These make the corresponding PORTA pin an output (i.e., put
registers are: the contents of the output latch on the selected pin).
• TRIS register (data direction register) Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
• PORT register (reads the levels on the pins of the
device) The Data Latch register (LATA) is also memory mapped.
• LAT register (output latch) Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The Data Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O The RA4 pin is multiplexed with the Timer0 module
pins are driving. clock input and the LCD segment drive to become the
RA4/T0CKI/SEG14 pin. Pins RA6 and RA7 are
A simplified model of a generic I/O port, without the multiplexed with the main oscillator pins; they are
interfaces to other peripherals, is shown in Figure 9-1. enabled as oscillator or I/O pins by the selection of the
main oscillator in the Configuration register (see
FIGURE 9-1: GENERIC I/O PORT Section 23.1 “Configuration Bits” for details). When
OPERATION they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
RD LAT
inputs and the analog VREF+ and VREF- inputs. The
Data operation of pins RA3:RA0 and RA5 as A/D converter
Bus D Q inputs is selected by clearing or setting the control bits
WR LAT I/O pin(1)
in the ADCON1 register (A/D Control Register 1).
or PORT
CK The RA4/T0CKI/SEG14 pin is a Schmitt Trigger input
Data Latch and an open-drain output. All other PORTA pins have
TTL input levels and full CMOS output drivers.
D Q
The TRISA register controls the direction of the PORTA
WR TRIS pins, even when they are being used as analog inputs.
CK
The user must ensure the bits in the TRISA register are
TRIS Latch Input maintained set when using them as analog inputs.
Buffer
RA5:RA2 are also multiplexed with LCD segment
RD TRIS
drives controlled by bits in the LCDSE1 and
LCDSE2 registers. I/O port functions are only
Q D available when the segments are disabled.
ENEN EXAMPLE 9-1: INITIALIZING PORTA

RD PORT CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
Note 1: I/O pins have diode protection to VDD and VSS. CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 07h ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVWF 07h ; Configure comparators
MOVWF CMCON ; for digital input
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs

PIC18F6390/6490/8390/8490
TABLE 9-1: PORTA FUNCTIONS
TRIS
Pin Name Function I/O Buffer Description
Setting
RA0/AN0 RA0 0 O DIG LATA<0> data output. Not affected by analog pin setting.
1 I TTL PORTA<0> data input. Reads ‘0’ on POR.
AN0 1 I ANA A/D input channel 0. Default configuration on POR.
RA1/AN1 RA1 0 O DIG LATA<1> data output. Not affected by analog pin setting.
RA2/AN2/VREF-/ RA2 0 O DIG LATA<2> data output. Not affected by analog pin setting; disabled
SEG16 when LCD segment enabled.
VREF- 1 I ANA A/D low reference voltage input.
SEG16 x O ANA Segment 16 analog output for LCD.
RA3/AN3/VREF+/ RA3 0 O DIG LATA<3> data output. Output is unaffected by analog pin setting;
SEG17 disabled when LCD segment enabled.
VREF+ 1 I ANA A/D high reference voltage input.
SEG17 x O ANA Segment 17 analog output for LCD. Disables all other digital outputs.
RA4/T0CKI/ RA4 0 O DIG LATA<4> data output; disabled when LCD segment enabled.
SEG14 1 I ST PORTA<4> data input.
T0CKI I ST Timer0 clock input.
RA5/AN4/ RA5 0 O DIG LATA<5> data output. Not affected by analog pin setting; disabled
HLVDIN/SEG15 when LCD segment enabled.
HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input.
OSC2/CLKO/RA6 OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKO x O DIG System cycle clock output (FOSC/4) in all oscillator modes except
RCIO, INTIO2 and ECIO.
RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
OSC1/CLKI/RA7 OSC1 x I ANA Main oscillator input connection, all modes except INTIO.
CLKI x I ANA Main clock input connection, all modes except INTIO.
RA7 0 O DIG LATA<7> data output. Available only in INTIO modes; otherwise reads
as ‘0’.
1 I TTL PORTA<7> data input. Available only in INTIO modes; otherwise reads
as ‘0’.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

PIC18F6390/6490/8390/8490
TABLE 9-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values
on Page
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 62
(1)
LATA LATA7 LATA6(1) LATA Data Output Register 62
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 62
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 61
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.

PIC18F6390/6490/8390/8490
9.2 PORTB, TRISB and Four of the PORTB pins (RB7:RB4) have an
LATB Registers interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
PORTB is an 8-bit wide, bidirectional port. The corre- RB7:RB4 pin configured as an output is excluded from
sponding Data Direction register is TRISB. Setting a the interrupt-on-change comparison). The input pins (of
TRISB bit (= 1) will make the corresponding PORTB RB7:RB4) are compared with the old value latched on
pin an input (i.e., put the corresponding output driver in the last read of PORTB. The “mismatch” outputs of
a high-impedance mode). Clearing a TRISB bit (= 0) RB7:RB4 are ORed together to generate the RB Port
will make the corresponding PORTB pin an output (i.e., Change Interrupt with Flag bit, RBIF (INTCON<0>).
put the contents of the output latch on the selected pin).
This interrupt can wake the device from
The Data Latch register (LATB) is also memory power-managed modes. The user, in the Interrupt
mapped. Read-modify-write operations on the LATB Service Routine, can clear the interrupt in the following
register read and write the latched output value for manner:
PORTB.
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
EXAMPLE 9-2: INITIALIZING PORTB end the mismatch condition.
CLRF PORTB ; Initialize PORTB by b) Clear flag bit, RBIF.
; clearing output
; data latches A mismatch condition will continue to set flag bit, RBIF.
CLRF LATB ; Alternate method Reading PORTB will end the mismatch condition and
; to clear output allow flag bit RBIF to be cleared.
; data latches
The interrupt-on-change feature is recommended for
; initialize data wake-up on key depression operation and operations
; direction where PORTB is only used for the interrupt-on-change
MOVWF TRISB ; Set RB<3:0> as inputs feature. Polling of PORTB is not recommended while
; RB<5:4> as outputs using the interrupt-on-change feature.
; RB<7:6> as inputs
RB4:RB1 are also multiplexed with LCD segment
drives controlled by bits in the LCDSE1 register. I/O
Each of the PORTB pins has a weak internal pull-up. A
port functions are only available when the segments
single control bit can turn on all the pull-ups. This is
are disabled.
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.

PIC18F6390/6490/8390/8490
TABLE 9-3: PORTB FUNCTIONS
TRIS
Setting
RB0/INT0 RB0 0 O DIG LATB<0> data output.

1 I TTL PORTB<0> data input; programmable weak pull-up.
INT0 1 I ST External interrupt 0 input.
RB1/INT1/SEG8 RB1 0 O DIG LATB<1> data output; disabled when LCD segment enabled.
1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
SEG8 x O ANA Segment 8 analog output for LCD. Disables digital output.
RB2/INT2/SEG9 RB2 0 O DIG LATB<2> data output; disabled when LCD segment enabled.
SEG9 x O ANA Segment 9 analog output for LCD
RB3/INT3/ RB3 0 O DIG LATB<3> data output; disabled when LCD segment enabled.
SEG10
RB4/KBI0/ RB4 0 O DIG LATB<4> data output; disabled when LCD segment enabled.
SEG11
KBI0 1 I TTL Interrupt-on-pin change.
RB5/KBI1 RB5 0 O DIG LATB<5> data output; disabled when LCD segment enabled.
KBI1 1 I TTL Interrupt-on-pin change.
RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output; unavailable when ICD or ICSP™ enabled.
1 I TTL PORTB<6> data input; unavailable when ICD or ICSP enabled.
KBI2 1 I TTL Interrupt-on-pin change; unavailable when ICD or ICSP enabled.
PGC x I ST Serial execution (ICSP) clock input for ICSP and ICD operation.(1)
RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output; unavailable when ICD or ICSP enabled.
1 I TTL PORTB<7> data input; unavailable when ICD or ICSP enabled.
KBI3 1 I TTL Interrupt-on-pin change; unavailable when ICD or ICSP enabled.
PGD x O DIG Serial execution data output for ICSP and ICD operation.(1)
x I ST Serial execution data input for ICSP and ICD operation.(1)
Note 1: All other pin functions are disabled when ICSP or ICD are enabled.

PIC18F6390/6490/8390/8490
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Reset
on Page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 62
LATB LATB Data Output Register 62
TRISB PORTB Data Direction Register 62
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 59
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 59
Legend: Shaded cells are not used by PORTB.

PIC18F6390/6490/8390/8490
9.3 PORTC, TRISC and Note: On a Power-on Reset, these pins are
LATC Registers configured as digital inputs.
PORTC is an 8-bit wide, bidirectional port. The corre- The contents of the TRISC register are affected by
sponding Data Direction register is TRISC. Setting a peripheral overrides. Reading TRISC always returns
TRISC bit (= 1) will make the corresponding PORTC the current contents, even though a peripheral device
pin an input (i.e., put the corresponding output driver in may be overriding one or more of the pins.
a high-impedance mode). Clearing a TRISC bit (= 0)
RC2 and RC5 are also multiplexed with LCD segment
will make the corresponding PORTC pin an output (i.e.,
drives controlled by bits in the LCDSE1 register. I/O
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory are disabled.
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for EXAMPLE 9-3: INITIALIZING PORTC
PORTC.
CLRF PORTC ; Initialize PORTC by
PORTC is multiplexed with several peripheral functions ; clearing output
(Table 9-5). The pins have Schmitt Trigger input ; data latches
buffers. RC1 is normally configured by Configuration CLRF LATC ; Alternate method
bit, CCP2MX, as the default peripheral pin of the CCP2 ; to clear output
module (default/erased state, CCP2MX = 1). ; data latches
When enabling peripheral functions, care should be ; initialize data
taken in defining TRIS bits for each PORTC pin. Some ; direction
peripherals override the TRIS bit to make a pin an output, MOVWF TRISC ; Set RC<3:0> as inputs
while other peripherals override the TRIS bit to make a ; RC<5:4> as outputs
pin an input. The user should refer to the corresponding ; RC<7:6> as inputs
peripheral section for the correct TRIS bit settings.

PIC18F6390/6490/8390/8490
TABLE 9-5: PORTC FUNCTIONS
TRIS
Setting
RC0/T1OSO/ RC0 0 O DIG LATC<0> data output; disabled when Timer1 oscillator is used.
T13CKI/ 1 I ST PORTC<0> data input; disabled when Timer1 oscillator is used.
T1OSO x O ANA Timer1 oscillator output.
T13CKI x I ST Timer1/Timer3 clock input.
RC1/T1OSI/ RC1 0 O DIG LATC<1> data output; disabled when Timer1 oscillator is used.
CCP2 1 I ST PORTC<1> data input; disabled when Timer1 oscillator is used.
T1OSI x I ANA Timer1 oscillator input.
CCP2(1) 0 O DIG CCP2 compare output or PWM output; takes priority over digital I/O data.
1 I ST CCP2 capture input.
RC2/CCP1/ RC2 0 O DIG LATC<2> data output; disabled when LCD segment enabled.
SEG13 1 I ST PORTC<2> data input.
CCP1 0 O DIG CCP1 compare output or PWM output; takes priority over digital I/O data.
RC3/SCK/SCL RC3 0 O DIG LATC<3> data output.
1 I ST PORTC<3> data input.
SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data.
1 I ST SPI clock input (MSSP module).
SCL 0 O DIG I2C™ clock output (MSSP module); takes priority over port data.
1 I ST I2C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA RC4 0 O DIG LATC<4> data output.
SDI 1 I ST SPI data input (MSSP module).
SDA 1 O DIG I2C data output (MSSP module); takes priority over port data.
1 I ST I2C data input (MSSP module); input type depends on module setting.
RC5/SDO/ RC5 0 O DIG LATC<5> data output; disabled when LCD segment enabled.
SEG12 1 I ST PORTC<5> data input.
SDO 0 O DIG SPI data output (MSSP module); takes priority over port data.
RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output.
TX1 1 O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
CK1 1 O DIG Synchronous serial data input (EUSART module). User must configure
as an input.
1 I ST Synchronous serial clock input (EUSART module).
RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output.
RX1 1 I ST Asynchronous serial receive data input (EUSART module).
DT1 1 O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
1 I ST Synchronous serial data input (EUSART module). User must configure
as an input.
Note 1: Default assignment for CCP2 (CCP2MX Configuration bit = 1).

PIC18F6390/6490/8390/8490
TABLE 9-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Reset
on Page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 62
LATC LATC Data Output Register 62
TRISC PORTC Data Direction Register 62
Legend: Shaded cells are not used by PORTC.

PIC18F6390/6490/8390/8490
9.4 PORTD, TRISD and PORTD is also multiplexed with LCD segment drives
LATD Registers controlled by the LCDSE0 register. I/O port functions
are only available when the segments are disabled.
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISD. Setting a EXAMPLE 9-4: INITIALIZING PORTD
TRISD bit (= 1) will make the corresponding PORTD
CLRF PORTD ; Initialize PORTD by
pin an input (i.e., put the corresponding output driver in ; clearing output
a high-impedance mode). Clearing a TRISD bit (= 0) ; data latches
will make the corresponding PORTD pin an output (i.e., CLRF LATD ; Alternate method
put the contents of the output latch on the selected pin). ; to clear output
The Data Latch register (LATD) is also memory ; data latches
mapped. Read-modify-write operations on the LATD
; initialize data
register read and write the latched output value for ; direction
PORTD. MOVWF TRISD ; Set RD<3:0> as inputs
All pins on PORTD are implemented with Schmitt ; RD<5:4> as outputs
Trigger input buffers. Each pin is individually ; RD<7:6> as inputs
configurable as an input or output.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
TABLE 9-7: PORTD FUNCTIONS

TRIS
Setting
RD0/SEG0 RD0 0 O DIG LATD<0> data output; disabled when LCD segment enabled.
1 I ST PORTD<0> data input.
SEG4 x O ANA Segment 4 analog output for LCD module.

PIC18F6390/6490/8390/8490
TABLE 9-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Reset
on Page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 62
LATD LATD Data Output Register 62
TRISD PORTD Data Direction Register 62

PIC18F6390/6490/8390/8490
9.5 PORTE, TRISE and RE7 also can be configured as the alternate peripheral
LATE Registers pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
PORTE is a 4-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISE. Setting a TABLE 9-9: PORTE PINS AVAILABLE IN
TRISE bit (= 1) will make the corresponding PORTE DIFFERENT LCD DRIVE
pin an input (i.e., put the corresponding output driver in
CONFIGURATIONS
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e., LCDCON Active LCD PORTE Available
put the contents of the output latch on the selected pin). <1:0> Commons for I/O
The Data Latch register (LATE) is also memory 00 COM0 RE6, RE5, RE4
mapped. Read-modify-write operations on the LATE 01 COM0, COM1 RE6, RE5
register read and write the latched output value for
PORTE. 10 COM0, COM1 RE6
and COM2
All pins on PORTE are implemented with Schmitt
11 All (COM0 None
Trigger input buffers. Each pin is individually
through COM3)
configured as digital inputs. EXAMPLE 9-5: INITIALIZING PORTE
CLRF PORTE ; Initialize PORTE by
Pins RE6:RE4 are multiplexed with three of the LCD ; clearing output
common drives. I/O port functions are only available on ; data latches
those PORTE pins, depending on which commons are CLRF LATE ; Alternate method
active. The configuration is determined by the ; to clear output
LMUX1:LMUX0 control bits (LCDCON<1:0>). The ; data latches
MOVLW 30h ; Value used to
availability is summarized in Table 9-9.
; initialize data
RE7 is also multiplexed with LCD segment drive ; direction
(SEG31) controlled by the LCDSE3<7> bit. I/O port MOVWF TRISE ; Set RE<5:4> as inputs
function is only available when the segment is disabled. ; RE<7:6> as outputs
Note: The pins corresponding to RE2:RE0 of

other PIC18F parts have the function of
LCDBIAS3:LCDBIAS1 and the pin
corresponding to RE3 of other PIC18F
parts has the function of COM0. These four
pins cannot be used as digital I/O.

PIC18F6390/6490/8390/8490
TABLE 9-10: PORTE FUNCTIONS
TRIS
Pad Name Function I/O Buffer Description
Setting
RE4/COM1 RE4 0 O DIG LATE<4> data output; disabled when LCD common enabled.
1 I ST PORTE<4> data input.
COM1 x O ANA Common 1 analog output for LCD.
RE5/COM2 RE5 0 O DIG LATE<5> data output; disabled when LCD common enabled.
RE6/COM3 RE6 0 O DIG LATE<6> data output; disabled when LCD segment enabled.
RE7/CCP2/ RE7 0 O DIG LATE<7> data output; disabled when LCD segment enabled.
SEG31 1 I ST PORTE<7> data input.
CCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data.
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit = 0.
TABLE 9-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Reset
on Page
PORTE RE7 RE6 RE5 RE4 — — — — 62
LATE LATE Data Output Register — — — — 62
TRISE PORTE Data Direction Register — — — — 62
LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

PIC18F6390/6490/8390/8490
9.6 PORTF, LATF and TRISF Registers EXAMPLE 9-6: INITIALIZING PORTF
CLRF PORTF ; Initialize PORTF by
PORTF is an 8-bit wide, bidirectional port. The corre- ; clearing output
sponding Data Direction register is TRISF. Setting a ; data latches
TRISF bit (= 1) will make the corresponding PORTF pin CLRF LATF ; Alternate method
an input (i.e., put the corresponding output driver in a ; to clear output
high-impedance mode). Clearing a TRISF bit (= 0) will ; data latches
make the corresponding PORTF pin an output (i.e., put MOVLW 0x07 ;
the contents of the output latch on the selected pin). MOVWF CMCON ; Turn off comparators
MOVLW 0x0F ;
The Data Latch register (LATF) is also memory MOVWF ADCON1 ; Set PORTF as digital I/O
mapped. Read-modify-write operations on the LATF MOVLW 0xCF ; Value used to
register read and write the latched output value for ; initialize data
PORTF. ; direction
MOVWF TRISF ; Set RF3:RF0 as inputs
All pins on PORTF are implemented with Schmitt
; RF5:RF4 as outputs
Trigger input buffers. Each pin is individually ; RF7:RF6 as inputs
PORTF is multiplexed with several analog peripheral
functions, including the A/D converter inputs and
comparator inputs, outputs and voltage reference.
Note 1: On a Power-on Reset, the RF6:RF0 pins
are configured as inputs and read as ‘0’.
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
PORTF is also multiplexed with LCD segment drives
controlled by bits in the LCDSE2 and LCDSE3
registers. I/O port functions are only available when the
segments are disabled.

PIC18F6390/6490/8390/8490
TABLE 9-12: PORTF FUNCTIONS
TRIS
Setting
RF0/AN5/ RF0 0 O DIG LATF<0> data output. Output is unaffected by analog input; disabled
SEG18 when LCD segment is enabled.
1 I ST PORTF<0> data input. Reads ‘0’ on POR.
C2OUT/SEG19 when LCD segment is enabled.
C2OUT 0 O DIG Comparator 2 output; takes priority over port data.
C1OUT/SEG20 when LCD segment is enabled.
C1OUT 0 O TTL Comparator 1 output; takes priority over port data.
AN8 1 I ANA A/D input channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
AN9 1 I ANA A/D input channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RF5/AN10/ RF5 0 O DIG LATF<5> data output. Output unaffected by analog input; disabled
CVREF/SEG23 when either LCD segment or CVREF is enabled.
AN10 1 I ANA A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR.
CVREF 0 O ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
AN11 1 I ANA A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
RF7/SS/SEG25 RF7 0 O DIG LATF<7> data output; disabled when LCD segment is enabled.
1 I ST PORTF<7> data input.
SS 1 I TTL Slave select input for MSSP module.

PIC18F6390/6490/8390/8490
TABLE 9-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Reset Values
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
TRISF PORTF Data Direction Register 62
PORTF Read PORTF Data Latch/Write PORTF Data Latch 62
LATF LATF Data Output Register 62
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 61
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.

PIC18F6390/6490/8390/8490
9.7 PORTG, TRISG and PORTG<4:0> are also multiplexed with LCD segment
LATG Registers drives controlled by bits in the LCDSE3 register. I/O
PORTG is a 6-bit wide, bidirectional port. The corre- are disabled.
sponding Data Direction register is TRISG. Setting a
The sixth pin of PORTG (MCLR/VPP/RG5) is an input
TRISG bit (= 1) will make the corresponding PORTG only pin. Its operation is controlled by the MCLRE
pin an input (i.e., put the corresponding output driver in Configuration bit. When selected as a port pin
a high-impedance mode). Clearing a TRISG bit (= 0) (MCLRE = 0), it functions as a digital input only pin; as
will make the corresponding PORTG pin an output (i.e., such, it does not have TRIS or LAT bits associated with
put the contents of the output latch on the selected pin). its operation. Otherwise, it functions as the device’s
The Data Latch register (LATG) is also memory Master Clear input. In either configuration, RG5 also
mapped. Read-modify-write operations on the LATG functions as the programming voltage input during
register read and write the latched output value for programming.
PORTG. Note: On a Power-on Reset, RG5 is enabled as
PORTG is multiplexed with both USART and LCD a digital input only if Master Clear
functions (Table 9-14). PORTG pins have Schmitt functionality is disabled. All other 5 pins
Trigger input buffers. are configured as digital inputs.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some EXAMPLE 9-7: INITIALIZING PORTG
peripherals override the TRIS bit to make a pin an CLRF PORTG ; Initialize PORTG by
output, while other peripherals override the TRIS bit to ; clearing output
make a pin an input. The user should refer to the ; data latches
CLRF LATG ; Alternate method
corresponding peripheral section for the correct TRIS
; to clear output
bit settings. The pin override value is not loaded into ; data latches
the TRIS register. This allows read-modify-write of the MOVLW 0x04 ; Value used to
TRIS register without concern due to peripheral ; initialize data
overrides. ; direction
MOVWF TRISG ; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs

PIC18F6390/6490/8390/8490
TABLE 9-14: PORTG FUNCTIONS
TRIS
Setting
RG0/SEG30 RG0 0 O DIG LATG<0> data output; disabled when LCD segment enabled.
1 I ST PORTG<0> data input.
RG1/TX2/CK2/ RG1 0 O DIG LATG<1> data output; disabled when LCD segment enabled.
SEG29 1 I ST PORTG<1> data input.
TX2 1 O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
CK2 1 O DIG Synchronous serial data input (AUSART module). User must configure
as an input.
1 I ST Synchronous serial clock input (AUSART module).
RG2/RX2/DT2/ RG2 0 O DIG LATG<2> data output; disabled when LCD segment enabled.
SEG28 1 I ST PORTG<2> data input.
RX2 1 I ST Asynchronous serial receive data input (AUSART module).
DT2 1 O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
1 I ST Synchronous serial data input (AUSART module). User must configure
as an input.
SEG27 0 O ANA Segment 27 analog output for LCD.
MCLR/VPP/RG5 MCLR —(1) I ST External Master Clear input; enabled when MCLRE Configuration bit is set.
VPP —(1) I ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RG5 —(1) I ST PORTG<5> data input; enabled when MCLRE Configuration bit is clear.
Note 1: RG5 does not have a corresponding TRISG bit.
TABLE 9-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Reset Values
on Page
PORTG — — RG5(1) Read PORTG pin/Write PORTG Data Latch 62
LATG — — — LATG Data Output Register 62
TRISG — — — PORTG Data Direction Register 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: RG5 is available as an input only when MCLR is disabled.

PIC18F6390/6490/8390/8490
9.8 PORTH, LATH and EXAMPLE 9-8: INITIALIZING PORTH
TRISH Registers CLRF PORTH ; Initialize PORTH by
; clearing output
Note: PORTH is available only on 80-pin ; data latches
devices. CLRF LATH ; Alternate method
; to clear output
PORTH is an 8-bit wide, bidirectional I/O port. The cor- ; data latches
responding Data Direction register is TRISH. Setting a MOVLW 0CFh ; Value used to
TRISH bit (= 1) will make the corresponding PORTH ; initialize data
pin an input (i.e., put the corresponding output driver in ; direction
a high-impedance mode). Clearing a TRISH bit (= 0) MOVWF TRISH ; Set RH3:RH0 as inputs
will make the corresponding PORTH pin an output (i.e., ; RH5:RH4 as outputs
put the contents of the output latch on the selected pin). ; RH7:RH6 as inputs
The Data Latch register (LATH) is also memory

mapped. Read-modify-write operations on the LATH
PORTH.
All pins on PORTH are implemented with Schmitt
PORTH is also multiplexed with LCD segment drives
controlled by the LCDSE5 register. I/O port functions

PIC18F6390/6490/8390/8490
TABLE 9-16: PORTH FUNCTIONS
TRIS
Setting
RH0/SEG47 RH0 0 O DIG-4 LATH<0> data output; disabled when LCD segment enabled.
1 I ST PORTH<0> data input.
RH1/SEG46 RH1 0 O DIG LATH<1> data output; disabled when LCD segment enabled.
SEG40 x O ANA Segment 40 analog output for LCD
TABLE 9-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH

Reset Values
on Page
TRISH PORTH Data Direction Register 62
PORTH Read PORTH pin/Write PORTH Data Latch 62
LATH LATH Data Output Register 62

PIC18F6390/6490/8390/8490
9.9 PORTJ, TRISJ and EXAMPLE 9-9: INITIALIZING PORTJ
LATJ Registers CLRF PORTJ ; Initialize PORTG by
; clearing output
Note: PORTJ is available only on 80-pin devices. ; data latches
CLRF LATJ ; Alternate method
PORTJ is an 8-bit wide, bidirectional port. The corre- ; to clear output
sponding Data Direction register is TRISJ. Setting a ; data latches
TRISJ bit (= 1) will make the corresponding PORTJ pin MOVLW 0xCF ; Value used to
an input (i.e., put the corresponding output driver in a ; initialize data
high-impedance mode). Clearing a TRISJ bit (= 0) will ; direction
make the corresponding PORTJ pin an output (i.e., put MOVWF TRISJ ; Set RJ3:RJ0 as inputs
the contents of the output latch on the selected pin). ; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
PORTJ.
All pins on PORTJ are implemented with Schmitt
PORTJ is also multiplexed with LCD segment drives
controlled by the LCDSE4 register. I/O port functions

PIC18F6390/6490/8390/8490
TABLE 9-18: PORTJ FUNCTIONS
TRIS
Setting
RJ0/SEG32 RJ0 0 O DIG LATJ<0> data output; disabled when LCD segment enabled.
1 I ST PORTJ<0> data input.
TABLE 9-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ

Reset Values
on Page
PORTJ Read PORTJ pin/Write PORTJ Data Latch 62
LATJ LATJ Data Output Register 62
TRISJ PORTJ Data Direction Register 62

PIC18F6390/6490/8390/8490
10.0 TIMER0 MODULE The T0CON register (Register 10-1) controls all
aspects of the module’s operation, including the
The Timer0 module incorporates the following features: prescale selection. It is both readable and writable.
• Software selectable operation as a timer or A simplified block diagram of the Timer0 module in
counter in both 8-bit or 16-bit modes 8-bit mode is shown in Figure 10-1. Figure 10-2
• Readable and writable registers shows a simplified block diagram of the Timer0
• Dedicated 8-bit software programmable prescaler module in 16-bit mode.
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
REGISTER 10-1: T0CON: TIMER0 CONTROL REGISTER

TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value

PIC18F6390/6490/8390/8490
10.1 Timer0 Operation internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
Timer0 can operate as either a timer or a counter; the timer/counter.
mode is selected by clearing the T0CS bit (T0CON<5>).
In Timer mode (T0CS = 0), the module increments on 10.2 Timer0 Reads and Writes in
every clock by default, unless a different prescaler value 16-Bit Mode
is selected (see Section 10.3 “Prescaler”). If the TMR0
register is written to, the increment is inhibited for the TMR0H is not the actual high byte of Timer0 in 16-bit
following two instruction cycles. The user can work mode; it is actually a buffered version of the real high
around this by writing an adjusted value to the TMR0 byte of Timer0, which is not directly readable nor
register. writable (refer to Figure 10-2). TMR0H is updated with
The Counter mode is selected by setting the T0CS bit the contents of the high byte of Timer0 during a read of
(= 1). In Counter mode, Timer0 increments either on TMR0L. This provides the ability to read all 16 bits of
every rising or falling edge of pin RA4/T0CKI. The Timer0, without having to verify that the read of the high
incrementing edge is determined by the Timer0 Source and low byte were valid, due to a rollover between
Edge Select bit, T0SE (T0CON<4>); clearing this bit successive reads of the high and low byte.
selects the rising edge. Restrictions on the external Similarly, a write to the high byte of Timer0 must also
clock input are discussed below. take place through the TMR0H Buffer register. The high
An external clock source can be used to drive Timer0; byte is updated with the contents of TMR0H when a
however, it must meet certain requirements to ensure write occurs to TMR0L. This allows all 16 bits of Timer0
that the external clock can be synchronized with the to be updated at once.
FIGURE 10-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4 0
1 Sync with Set
1 Internal TMR0L TMR0IF
T0CKI pin Programmable Clocks on Overflow
0
Prescaler
T0SE (2 TCY Delay)
3 8
T0CS
T0PS2:T0PS0 8
Internal Data Bus
PSA
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 10-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4 0
1 Sync with TMR0 Set
1 Internal TMR0L High Byte TMR0IF
T0CKI pin Programmable Clocks on Overflow
Prescaler 0 8
T0SE (2 TCY Delay)
T0CS 3 Read TMR0L
T0PS2:T0PS0
Write TMR0L
PSA 8
8
TMR0H
8
8
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.

PIC18F6390/6490/8390/8490
10.3 Prescaler 10.3.1 SWITCHING PRESCALER
ASSIGNMENT
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable; The prescaler assignment is fully under software
its value is set by the PSA and T0PS2:T0PS0 bits control and can be changed “on-the-fly” during program
(T0CON<3:0>), which determine the prescaler execution.
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the 10.4 Timer0 Interrupt
Timer0 module. When it is assigned, prescale values The TMR0 interrupt is generated when the TMR0
from 1:2 through 1:256 in power-of-2 increments are register overflows from FFh to 00h in 8-bit mode, or
selectable. from FFFFh to 0000h in 16-bit mode. This overflow sets
When assigned to the Timer0 module, all instructions the TMR0IF flag bit. The interrupt can be masked by
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF clearing the TMR0IE bit (INTCON<5>). Before
TMR0, BSF TMR0, etc.) clear the prescaler count. re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler Since Timer0 is shut down in Sleep mode, the TMR0
count, but will not change the prescaler interrupt cannot awaken the processor from Sleep.
assignment.
TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0

Reset
on Page
TMR0L Timer0 Register Low Byte 60
TMR0H Timer0 Register High Byte 60
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 60
TRISA PORTA Data Direction Register 62
Legend: Shaded cells are not used by Timer0.

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NOTES:

PIC18F6390/6490/8390/8490
11.0 TIMER1 MODULE A simplified block diagram of the Timer1 module is
shown in Figure 11-1. A block diagram of the module’s
The Timer1 timer/counter module incorporates these operation in Read/Write mode is shown in Figure 11-2.
features:
The module incorporates its own low-power oscillator
• Software selectable operation as a 16-bit timer or to provide an additional clocking option. The Timer1
counter oscillator can also be used as a low-power clock source
• Readable and writable 8-bit registers (TMR1H for the microcontroller in power-managed operation.
and TMR1L) Timer1 can also be used to provide Real-Time Clock
• Selectable clock source (internal or external) with (RTC) functionality to applications with only a minimal
device clock or Timer1 oscillator internal options addition of external components and code overhead.
• Interrupt-on-overflow Timer1 is controlled through the T1CON Control
• Reset on CCP Special Event Trigger register (Register 11-1). It also contains the Timer1
• Device clock status flag (T1RUN) Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1

PIC18F6390/6490/8390/8490
11.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
Timer1 can operate in one of these modes: or the Timer1 oscillator, if enabled.
• Timer When Timer1 is enabled, the RC1/T1OSI and
• Synchronous Counter RC0/T1OSO/T13CKI pins become inputs. This means
• Asynchronous Counter the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 11-1: TIMER1 BLOCK DIAGRAM

Timer1 Oscillator
On/Off 1
T1OSO/T13CKI 1
Prescaler Synchronize
FOSC/4 Detect 0
1, 2, 4, 8
Internal
Clock 0
T1OSI 2
Sleep Input
T1OSCEN (1) TMR1CS Timer1
On/Off
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
Note 1: When T1OSCEN is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 11-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator
1
T1OSO/T13CKI 1
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
T1OSCEN(1) TMR1CS Timer1
T1CKPS1:T1CKPS0 On/Off
T1SYNC
TMR1ON
TMR1 Set
Clear TMR1 TMR1L TMR1IF
High Byte
(CCP Special Event Trigger) on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR1H
8
8
Internal Data Bus

PIC18F6390/6490/8390/8490
11.2 Timer1 16-Bit Read/Write Mode TABLE 11-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR(2,3,4)
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit Osc Type Freq C1 C2
(T1CON<7>) is set, the address for TMR1H is mapped LP 32 kHz 27 pF(1) 27 pF(1)
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of Note 1: Microchip suggests these values as a
Timer1 into the Timer1 High Byte Buffer register. This starting point in validating the oscillator
provides the user with the ability to accurately read all circuit.
16 bits of Timer1 without having to determine whether
2: Higher capacitance increases the stability
a read of the high byte, followed by a read of the low
of the oscillator, but also increases the
byte, has become invalid due to a rollover between
start-up time.
reads.
3: Since each resonator/crystal has its own
A write to the high byte of Timer1 must also take place
characteristics, the user should consult
through the TMR1H Buffer register. The Timer1 high
the resonator/crystal manufacturer for
byte is updated with the contents of TMR1H when a
appropriate values of external
write occurs to TMR1L. This allows a user to write all
components.
16 bits to both the high and low bytes of Timer1 at once.
4: Capacitor values are for design guidance
The high byte of Timer1 is not directly readable or
only.
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register. 11.3.1 USING TIMER1 AS A CLOCK
Writes to TMR1H do not clear the Timer1 prescaler.
SOURCE
The prescaler is only cleared on writes to TMR1L.
The Timer1 oscillator is also available as a clock source
11.3 Timer1 Oscillator in power-managed modes. By setting the clock select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
An on-chip crystal oscillator circuit is incorporated switches to SEC_RUN mode; both the CPU and
between pins T1OSI (input) and T1OSO (amplifier peripherals are clocked from the Timer1 oscillator. If the
output). It is enabled by setting the Timer1 Oscillator IDLEN bit (OSCCON<7>) is cleared and a SLEEP
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a instruction is executed, the device enters SEC_IDLE
low-power circuit rated for 32 kHz crystals. It will mode. Additional details are available in Section 3.0
continue to run during all power-managed modes. The “Power-Managed Modes”.
circuit for a typical LP oscillator is shown in Figure 11-3. Whenever the Timer1 oscillator is providing the clock
Table 11-1 shows the capacitor selection for the Timer1 source, the Timer1 system clock status flag, T1RUN
oscillator. (T1CON<6>), is set. This can be used to determine the
The user must provide a software time delay to ensure controller’s current clocking mode. It can also indicate
proper start-up of the Timer1 oscillator. the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
FIGURE 11-3: EXTERNAL Timer1 oscillator fails while providing the clock, polling
COMPONENTS FOR THE the T1RUN bit will indicate whether the clock is being
TIMER1 LP OSCILLATOR provided by the Timer1 oscillator or another source.
C1
PIC18FXXXX
11.3.2 LOW-POWER TIMER1 OPTION
33 pF
The Timer1 oscillator can operate at two distinct levels
T1OSI
of power consumption based on device configuration.
When the LPT1OSC Configuration bit is set, the Timer1
XTAL
32.768 kHz oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
T1OSO level. Power consumption for a particular mode is
C2 relatively constant, regardless of the device’s operating
33 pF mode. The default Timer1 configuration is the higher
power mode.
Note: See the Notes with Table 11-1 for additional
information about capacitor selection. As the Low-Power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option
is therefore best suited for low noise applications where
power conservation is an important design
consideration.

PIC18F6390/6490/8390/8490
11.3.3 TIMER1 OSCILLATOR LAYOUT 11.5 Resetting Timer1 Using the CCP
CONSIDERATIONS Special Event Trigger
The Timer1 oscillator circuit draws very little power If either of the CCP modules is configured in Compare
during operation. Due to the low-power nature of the mode to generate a Special Event Trigger
oscillator, it may also be sensitive to rapidly changing (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011),
signals in close proximity. this signal will reset Timer1. The trigger from CCP2 will
The oscillator circuit, shown in Figure 11-3, should be also start an A/D conversion if the A/D module is
located as close as possible to the microcontroller. enabled (see Section 14.3.4 “Special Event Trigger”
There should be no circuits passing within the oscillator for more information.).
circuit boundaries other than VSS or VDD. The module must be configured as either a timer or a
If a high-speed circuit must be located near the synchronous counter to take advantage of this feature.
oscillator (such as the CCP1 pin in Output Compare or When used this way, the CCPRH:CCPRL register pair
PWM mode, or the primary oscillator using the OSC2 effectively becomes a period register for Timer1.
pin), a grounded guard ring around the oscillator circuit, If Timer1 is running in Asynchronous Counter mode,
as shown in Figure 11-4, may be helpful when used on this Reset operation may not work.
a single sided PCB or in addition to a ground plane.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
FIGURE 11-4: OSCILLATOR CIRCUIT precedence.
WITH GROUNDED
GUARD RING Note: The Special Event Triggers from the CCP2
module will not set the TMR1IF interrupt
VDD flag bit (PIR1<0>).
VSS
11.6 Using Timer1 as a
OSC1 Real-Time Clock
OSC2 Adding an external LP oscillator to Timer1 (such as the
one described in Section 11.3 “Timer1 Oscillator”,
above) gives users the option to include RTC function-
ality to their applications. This is accomplished with an
RC0
inexpensive watch crystal to provide an accurate time
RC1 base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
RC2 completely eliminate the need for a separate RTC
device and battery backup.
Note: Not drawn to scale.
The application code routine, RTCisr, shown in
Example 11-1, demonstrates a simple method to
11.4 Timer1 Interrupt increment a counter at one-second intervals using an
The TMR1 register pair (TMR1H:TMR1L) increments Interrupt Service Routine. Incrementing the TMR1
from 0000h to FFFFh and rolls over to 0000h. The register pair to overflow, triggers the interrupt and calls
Timer1 interrupt, if enabled, is generated on overflow, the routine, which increments the seconds counter by
which is latched in interrupt flag bit, TMR1IF one; additional counters for minutes and hours are
(PIR1<0>). This interrupt can be enabled or disabled incremented as the previous counter overflows.
by setting or clearing the Timer1 Interrupt Enable bit, Since the register pair is 16 bits wide, counting up to
TMR1IE (PIE1<0>). overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it. The simplest method is to set the Most Sig-
nificant bit of TMR1H with a BSF instruction. Note that
the TMR1L register is never preloaded or altered; doing
so may introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.

PIC18F6390/6490/8390/8490
EXAMPLE 11-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1OSC ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
MOVLW .01 ; Reset hours to 1
MOVWF hours
RETURN ; Done
TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Reset
on Page
PIR1 — ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 61
PIE1 — ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 61
IPR1 — ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 61
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
12.0 TIMER2 MODULE 12.1 Timer2 Operation
The Timer2 timer module incorporates the following In normal operation, TMR2 is incremented from 00h on
features: each clock (FOSC/4). A 2-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
• 8-bit Timer and Period registers (TMR2 and PR2,
divide-by-16 prescale options; these are selected by
respectively)
the prescaler control bits, T2CKPS1:T2CKPS0
• Readable and writable (both registers) (T2CON<1:0>). The value of TMR2 is compared to that
• Software programmable prescaler (1:1, 1:4 and of the Period register, PR2, on each clock cycle. When
1:16) the two values match, the comparator generates a
• Software programmable postscaler (1:1 through match signal as the timer output. This signal also resets
1:16) the value of TMR2 to 00h on the next cycle and drives
• Interrupt on TMR2 to PR2 match the output counter/postscaler (see Section 12.2
• Optional use as the shift clock for the MSSP “Timer2 Interrupt”).
module The TMR2 and PR2 registers are both directly readable
The module is controlled through the T2CON register and writable. The TMR2 register is cleared on any
(Register 12-1), which enables or disables the timer device Reset, while the PR2 register initializes at FFh.
and configures the prescaler and postscaler. Timer2 Both the prescaler and postscaler counters are cleared
can be shut off by clearing control bit, TMR2ON on the following events:
(T2CON<2>), to minimize power consumption. • a write to the TMR2 register
A simplified block diagram of the module is shown in • a write to the T2CON register
Figure 12-1. • any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
•
•
•
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

PIC18F6390/6490/8390/8490
12.2 Timer2 Interrupt 12.3 TMR2 Output
Timer2 also can generate an optional device interrupt. The unscaled output of TMR2 is available primarily to
The Timer2 output signal (TMR2 to PR2 match) the CCP modules, where it is used as a time base for
provides the input for the 4-bit output operations in PWM mode.
counter/postscaler. This counter generates the TMR2 Timer2 can be optionally used as the shift clock source
match interrupt flag which is latched in TMR2IF for the MSSP module operating in SPI mode.
(PIR1<1>). The interrupt is enabled by setting the Additional information is provided in Section 15.0
TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). “Master Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
4 1:1 to 1:16
T2OUTPS3:T2OUTPS0 Set TMR2IF
Postscaler
2
T2CKPS1:T2CKPS0 TMR2 Output
(to PWM or MSSP)
TMR2/PR2
Reset Match
1:1, 1:4, 1:16
FOSC/4 TMR2 Comparator PR2
Prescaler
8 8
8
Internal Data Bus

Reset
on Page
TMR2 Timer2 Register 60
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 60
PR2 Timer2 Period Register 60

PIC18F6390/6490/8390/8490
13.0 TIMER3 MODULE A simplified block diagram of the Timer3 module is
shown in Figure 13-1. A block diagram of the module’s
The Timer3 timer/counter module incorporates these operation in Read/Write mode is shown in Figure 13-2.
features:
The Timer3 module is controlled through the T3CON
• Software selectable operation as a 16-bit timer or register (Register 13-1). It also selects the clock source
counter options for the CCP modules (see Section 14.1.1
• Readable and writable 8-bit registers (TMR3H “CCP Modules and Timer Resources” for more
and TMR3L) information).
• Selectable clock source (internal or external), with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on CCP Special Event Trigger

RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
Legend:
bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for the CCPx modules
01 = Timer3 is the capture/compare clock source for the CCP2 module;
Timer1 is the capture/compare clock source for the CCP1 module
00 = Timer1 is the capture/compare clock source for the CCPx modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
1 = Enables Timer3
0 = Stops Timer3

PIC18F6390/6490/8390/8490
13.1 Timer3 Operation cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
Timer3 can operate in one of three modes: or the Timer1 oscillator, if enabled.
• Timer As with Timer1, the RC1/T1OSI and
• Synchronous counter RC0/T1OSO/T13CKI pins become inputs when the
• Asynchronous counter Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction

Timer1 Oscillator
1
T1OSO/T13CKI 1
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
T1OSCEN (1) TMR3CS Timer3
On/Off
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
CCP Special Event Trigger Clear TMR3 TMR3 Set

T3CCPx TMR3L TMR3IF
High Byte
on Overflow
FIGURE 13-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator Timer1 Clock Input
1
T1OSO/T13CKI 1
FOSC/4 1, 2, 4, 8 Detect 0
Internal
Clock 0
T1OSI 2
Sleep Input
(1) TMR3CS Timer3
T1OSCEN
T3CKPS1:T3CKPS0 On/Off
T3SYNC
TMR3ON
CCP Special Event Trigger Clear TMR3 TMR3 Set

T3CCPx TMR3L High Byte TMR3IF
on Overflow
8
Read TMR3L
Write TMR3L
8
8
TMR3H
8
8
Internal Data Bus

PIC18F6390/6490/8390/8490
13.2 Timer3 16-Bit Read/Write Mode 13.4 Timer3 Interrupt
Timer3 can be configured for 16-bit reads and writes The TMR3 register pair (TMR3H:TMR3L) increments
(see Figure 13-2). When the RD16 control bit from 0000h to FFFFh and overflows to 0000h. The
(T3CON<7>) is set, the address for TMR3H is mapped Timer3 interrupt, if enabled, is generated on overflow
to a buffer register for the high byte of Timer3. A read and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
from TMR3L will load the contents of the high byte of This interrupt can be enabled or disabled by setting or
Timer3 into the Timer3 High Byte Buffer register. This clearing the Timer3 Interrupt Enable bit, TMR3IE
provides the user with the ability to accurately read all (PIE2<1>).
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low 13.5 Resetting Timer3 Using the CCP
byte, has become invalid due to a rollover between Special Event Trigger
reads.
A write to the high byte of Timer3 must also take place If either of the CCP modules is configured in Compare
through the TMR3H Buffer register. The Timer3 high mode to generate a Special Event Trigger
byte is updated with the contents of TMR3H when a (CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011),
write occurs to TMR3L. This allows a user to write all this signal will reset Timer1. The trigger from CCP2 will
16 bits to both the high and low bytes of Timer3 at once. also start an A/D conversion if the A/D module is
enabled (see Section 14.3.4 “Special Event Trigger”
The high byte of Timer3 is not directly readable or for more information.).
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register. The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
Writes to TMR3H do not clear the Timer3 prescaler. When used this way, the CCPR2H:CCPR2L register
The prescaler is only cleared on writes to TMR3L. pair effectively becomes a Period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
13.3 Using the Timer1 Oscillator as the the Reset operation may not work.
Timer3 Clock Source
In the event that a write to Timer3 coincides with a
The Timer1 internal oscillator may be used as the clock Special Event Trigger from a CCP module, the write will
source for Timer3. The Timer1 oscillator is enabled by take precedence.
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Note: The Special Event Triggers from the CCP2
Timer3 clock source, the TMR3CS bit must also be set.
module will not set the TMR3IF interrupt
As previously noted, this also configures Timer3 to
flag bit (PIR2<1>).
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 11.0
“Timer1 Module”.

Reset
on Page
PIR2 OSCFIF CMIF — — BCLIF HLVDIF TMR3IF CCP2IF 61
PIE2 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE 61
IPR2 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP 61
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 61

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
14.0 CAPTURE/COMPARE/PWM Each CCP module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
(CCP) MODULES
register or a PWM Master/Slave Duty Cycle register.
PIC18F6390/6490/8390/8490 devices have two CCP For the sake of clarity, all CCP module operation in the
(Capture/Compare/PWM) modules, designated CCP1 following sections is described with respect to CCP2,
and CCP2. Both modules implement standard capture, but is equally applicable to CCP1.
compare and Pulse-Width Modulation (PWM) modes.
REGISTER 14-1: CCPxCON: CCPx CONTROL REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
Legend:

bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most
Significant bits (DCxB9:DCxB2) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match (CCPxIF
bit is set)(1)
11xx = PWM mode
Note 1: CCPxM3:CCPxM0 = 1011 will only reset the timer and not start the A/D conversion on the CCPx match.

PIC18F6390/6490/8390/8490
14.1 CCP Module Configuration The assignment of a particular timer to a module is
determined by the Timer to CCP enable bits in the
Each Capture/Compare/PWM module is associated T3CON register (Register 13-1). Both modules may be
with a control register (generically, CCPxCON) and a active at any given time and may share the same timer
data register (CCPRx). The data register in turn is com- resource if they are configured to operate in the same
prised of two 8-bit registers: CCPRxL (low byte) and mode (capture/compare or PWM) at the same time.
CCPRxH (high byte). All registers are both readable The interactions between the two modules are
and writable. summarized in Table 14-2.
14.1.1 CCP MODULES AND TIMER Depending on the configuration selected, up to four
RESOURCES timers may be active at once, with modules in the same
configuration (capture/compare or PWM) sharing timer
The CCP modules utilize Timers 1, 2 or 3, depending resources. The possible configurations are shown in
on the mode selected. Timer1 and Timer3 are available Figure 14-1.
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode. 14.1.2 CCP2 PIN ASSIGNMENT
The pin assignment for CCP2 (capture input, compare
TABLE 14-1: CCP MODE – TIMER and PWM output) can change based on device config-
RESOURCE uration. The CCP2MX Configuration bit determines
CCP Mode Timer Resource which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the Configuration bit
Capture Timer1 or Timer3 is cleared, CCP2 is multiplexed with RE7.
Compare Timer1 or Timer3
Changing the pin assignment of CCP2 does not
PWM Timer2
automatically change any requirements for configuring
the port pin. Users must always verify that the appropri-
ate TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
FIGURE 14-1: CCP AND TIMER INTERCONNECT CONFIGURATIONS

T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 1x
TMR1 TMR3 TMR1 TMR3 TMR1 TMR3
CCP1 CCP1 CCP1

CCP2 CCP2 CCP2
TMR2 TMR2 TMR2
Timer1 is used for all capture Timer1 is used for capture Timer3 is used for all capture
and compare operations for and compare operations for and compare operations for
all CCP modules. Timer2 is CCP1 and Timer 3 is used for all CCP modules. Timer2 is
used for PWM operations for CCP2. used for PWM operations for
all CCP modules. Modules Both the modules use Timer2 all CCP modules. Modules
may share either timer as a common time base if they may share either timer
resource as a common time are in PWM modes. resource as a common time
base. base.

PIC18F6390/6490/8390/8490
TABLE 14-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode Interaction
Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture PWM* None
Compare PWM* None
PWM* Capture None
PWM* Compare None
PWM* PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
* Includes standard and Enhanced PWM operation.

PIC18F6390/6490/8390/8490
14.2 Capture Mode 14.2.3 SOFTWARE INTERRUPT
In Capture mode, the CCPR2H:CCPR2L register pair When the Capture mode is changed, a false capture
captures the 16-bit value of the TMR1 or TMR3 interrupt may be generated. The user should keep bit
registers when an event occurs on the CCP2 pin (RC1 CCP2IE (PIE2<0>) clear to avoid false interrupts and
or RE7, depending on device configuration). An event should clear the flag bit, CCP2IF, following any such
is defined as one of the following: change in operating mode.
• every falling edge 14.2.4 CCP PRESCALER

• every rising edge
There are four prescaler settings in Capture mode; they
• every 4th rising edge are specified as part of the operating mode selected by
• every 16th rising edge the mode select bits (CCP2M3:CCP2M0). Whenever
The event is selected by the mode select bits, the CCP module is turned off, or the CCP module is not
CCP2M3:CCP2M0 (CCP2CON<3:0>). When a in Capture mode, the prescaler counter is cleared. This
capture is made, the interrupt request flag bit, CCP2IF means that any Reset will clear the prescaler counter.
(PIR2<0>), is set; it must be cleared in software. If Switching from one capture prescaler to another may
another capture occurs before the value in register generate an interrupt. Also, the prescaler counter will
CCPR2 is read, the old captured value is overwritten by not be cleared; therefore, the first capture may be from
the new captured value. a non-zero prescaler. Example 14-1 shows the
recommended method for switching between capture
14.2.1 CCP PIN CONFIGURATION prescalers. This example also clears the prescaler
In Capture mode, the appropriate CCPx pin should be counter and will not generate the “false” interrupt.
configured as an input by setting the corresponding
TRIS direction bit. EXAMPLE 14-1: CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If RC1/CCP2 or RE7/CCP2 is configured
as an output, a write to the port can cause CLRF CCP2CON ; Turn CCP module off
a capture condition. MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
14.2.2 TIMER1/TIMER3 MODE SELECTION MOVWF CCP2CON ; Load CCP2CON with
The timers that are to be used with the capture feature ; this value
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 14.1.1 “CCP Modules and Timer
Resources”).
FIGURE 14-2: CAPTURE MODE OPERATION BLOCK DIAGRAM

TMR3H TMR3L
Set CCP1IF
T3CCP2 TMR3
CCP1 pin Enable
Prescaler and CCPR1H CCPR1L
÷ 1, 4, 16 Edge Detect
TMR1
T3CCP2 Enable
4 TMR1H TMR1L
CCP1CON<3:0> Set CCP2IF
4
Q1:Q4
4
CCP2CON<3:0>
T3CCP1 TMR3H TMR3L
T3CCP2
TMR3
Enable
CCP2 pin
Prescaler and CCPR2H CCPR2L
÷ 1, 4, 16 Edge Detect
TMR1
Enable
T3CCP2
TMR1H TMR1L
T3CCP1

PIC18F6390/6490/8390/8490
14.3 Compare Mode 14.3.3 SOFTWARE INTERRUPT MODE
In Compare mode, the 16-bit CCPR2 register value is When the Generate Software Interrupt mode is chosen
constantly compared against either the TMR1 or TMR3 (CCP2M3:CCP2M0 = 1010), the CCP2 pin is not
register pair value. When a match occurs, the CCP2 affected. Only a CCP interrupt is generated if enabled
pin can be: and the CCP2IE bit is set.
• driven high 14.3.4 SPECIAL EVENT TRIGGER

• driven low
Both CCP modules are equipped with a Special Event
• toggled (high-to-low or low-to-high) Trigger. This is an internal hardware signal generated
• remain unchanged (that is, reflects the state of the in Compare mode to trigger actions by other modules.
I/O latch) The Special Event Trigger is enabled by selecting
The action on the pin is based on the value of the mode the Compare Special Event Trigger mode
select bits (CCP2M3:CCP2M0). At the same time, the (CCP2M3:CCP2M0 = 1011).
interrupt flag bit, CCP2IF, is set. For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
14.3.1 CCP PIN CONFIGURATION currently assigned as the module’s time base. This
The user must configure the CCPx pin as an output by allows the CCPRx registers to serve as a programmable
clearing the appropriate TRIS bit. Period register for either timer.
Note: Clearing the CCP2CON register will force The Special Event Trigger for CCP2 can also start an
the RC1 or RE7 compare output latch A/D conversion. In order to do this, the A/D converter
(depending on device configuration) to the must already be enabled.
default low level. This is not the PORTC or Note: The Special Event Trigger of CCP1 only
PORTE I/O data latch. resets Timer1/Timer3 and cannot start an
A/D conversion even when the A/D
14.3.2 TIMER1/TIMER3 MODE SELECTION converter is enabled.
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
FIGURE 14-3: COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger

Set CCP1IF (Timer1 Reset)
CCPR1H CCPR1L
CCP1 pin
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCP1CON<3:0>
0 TMR1H TMR1L 0
1 TMR3H TMR3L 1 Special Event Trigger

(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
T3CCP2
Set CCP2IF CCP2 pin
Compare Output S Q
Comparator
Match Logic
R
TRIS
4 Output Enable
CCPR2H CCPR2L
CCP2CON<3:0>

PIC18F6390/6490/8390/8490
TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
on Page
RCON IPEN SBOREN — RI TO PD POR BOR 60
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 61
CCPR1L Capture/Compare/PWM Register 1 Low Byte 61
CCPR1H Capture/Compare/PWM Register 1 High Byte 61
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture/compare, Timer1 or Timer3.

PIC18F6390/6490/8390/8490
14.4 PWM Mode A PWM output (Figure 14-5) has a time base (period)
and a time that the output stays high (duty cycle). The
In Pulse-Width Modulation (PWM) mode, the CCP2 pin frequency of the PWM is the inverse of the period
produces up to a 10-bit resolution PWM output. Since (1/period).
the CCP2 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
FIGURE 14-5: PWM OUTPUT
make the CCP2 pin an output.
Period
Note: Clearing the CCP2CON register will force
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE Duty Cycle
I/O data latch.
TMR2 = PR2
Figure 14-4 shows a simplified block diagram of the
TMR2 = Duty Cycle
CCP2 module in PWM mode.
For a step-by-step procedure on how to set up the CCP TMR2 = PR2
module for PWM operation, see Section 14.4.3
“Setup for PWM Operation”. 14.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
FIGURE 14-4: SIMPLIFIED PWM BLOCK
register. The PWM period can be calculated using the
DIAGRAM
following formula:
Duty Cycle Registers CCP2CON<5:4>
CCPR2L EQUATION 14-1:

PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
CCPR2H (Slave) PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events
Comparator R Q occur on the next increment cycle:
CCP2 • TMR2 is cleared
TMR2 (Note 1) • The CCP2 pin is set (exception: if PWM duty
S
cycle = 0%, the CCP2 pin will not be set)
Comparator TRISC<2> • The PWM duty cycle is latched from CCPR2L into
Clear Timer, CCPR2H
CCP2 pin and
PR2
latch D.C. Note: The Timer2 postscalers (see Section 12.0
“Timer2 Module”) are not used in the
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit determination of the PWM frequency. The
internal Q clock, or 2 bits of the prescaler, to create the postscaler could be used to have a servo
10-bit time base.
update rate at a different frequency than
the PWM output.

PIC18F6390/6490/8390/8490
14.4.2 PWM DUTY CYCLE The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
The PWM duty cycle is specified by writing to the
double-buffering is essential for glitchless PWM
CCPR2L register and to the CCP2CON<5:4> bits. Up
operation.
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON<5:4> bits contain When the CCPR2H and 2-bit latch match TMR2,
the two LSbs. This 10-bit value is represented by concatenated with an internal 2-bit Q clock or 2 bits of
CCPR2L:CCP2CON<5:4>. The following equation is the TMR2 prescaler, the CCP2 pin is cleared.
used to calculate the PWM duty cycle in time: The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 14-2:
PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) • EQUATION 14-3:
TOSC • (TMR2 Prescale Value) F OSC
log ⎛ ---------------⎞
⎝ F PWM⎠
CCPR2L and CCP2CON<5:4> can be written to at any PWM Resolution (max) = -----------------------------bits
log ( 2 )
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode, Note: If the PWM duty cycle value is longer than
CCPR2H is a read-only register. the PWM period, the CCP2 pin will not be
cleared.
TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 14 12 10 8 7 6.58

PIC18F6390/6490/8390/8490
14.4.3 SETUP FOR PWM OPERATION 3. Make the CCP2 pin an output by clearing the
appropriate TRIS bit.
The following steps should be taken when configuring
the CCP2 module for PWM operation: 4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
1. Set the PWM period by writing to the PR2
5. Configure the CCP2 module for PWM operation.
register.
2. Set the PWM duty cycle by writing to the
CCPR2L register and CCP2CON<5:4> bits.
TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Reset
on Page
TMR2 Timer2 Register 60
PR2 Timer2 Period Register 60
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
15.0 MASTER SYNCHRONOUS 15.3 SPI Mode
SERIAL PORT (MSSP) The SPI mode allows 8 bits of data to be synchronously
MODULE transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
15.1 Master SSP (MSSP) Module communication, typically three pins are used:
Overview • Serial Data Out (SDO) – RC5/SDO/SEG12
• Serial Data In (SDI) – RC4/SDI/SDA
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other • Serial Clock (SCK) – RC3/SCK/SCL
peripheral or microcontroller devices. These peripheral Additionally, a fourth pin may be used when in a Slave
devices may be serial EEPROMs, shift registers, mode of operation:
display drivers, A/D converters, etc. The MSSP module • Slave Select (SS) – RF7/SS/SEG25
can operate in one of two modes:
Figure 15-1 shows the block diagram of the MSSP
• Serial Peripheral Interface (SPI) module when operating in SPI mode.
• Inter-Integrated Circuit (I2C)
- Full Master mode FIGURE 15-1: MSSP BLOCK DIAGRAM
- Slave mode (with general address call) (SPI MODE)
The I2C interface supports the following modes in Internal
hardware: Data Bus
• Master mode Read Write

• Multi-Master mode
SSPBUF reg
• Slave mode
15.2 Control Registers RC4/SDI/SDA

The MSSP module has three associated registers. SSPSR reg
These include a status register (SSPSTAT) and two RC5/SDO/SEG12 bit 0 Shift
Clock
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual Configuration bits
differ significantly depending on whether the MSSP
module is operated in SPI or I2C mode. RF7/SS/
Additional details are provided under the individual SEG25 SS Control
sections. Enable
Edge
Select
2
Clock Select
SSPM3:SSPM0
RC3/SCK/
SCL
SMP:CKE 4
2 2
(
TMR2 Output )
Edge
Select Prescaler TOSC
4, 16, 64
Data to TXx/RXx in SSPSR

TRIS bit

PIC18F6390/6490/8390/8490
15.3.1 REGISTERS SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
The MSSP module has four registers for SPI mode
are written to or read from.
operation. These are:
In receive operations, SSPSR and SSPBUF together
• MSSP Control Register 1 (SSPCON1)
create a double-buffered receiver. When SSPSR
• MSSP Status Register (SSPSTAT) receives a complete byte, it is transferred to SSPBUF
• Serial Receive/Transmit Buffer Register (SSPBUF) and the SSPIF interrupt is set.
• MSSP Shift Register (SSPSR) – Not directly During transmission, the SSPBUF is not double-
accessible buffered. A write to SSPBUF will write to both SSPBUF
SSPCON1 and SSPSTAT are the control and status and SSPSR.
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper 2 bits of the
SSPSTAT are read/write.
REGISTER 15-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
bit 7 SMP: Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Edge Select bit
When CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
When CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5 D/A: Data/Address bit
Used in I2C™ mode only.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write Information bit
bit 1 UA: Update Address bit
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty

PIC18F6390/6490/8390/8490
REGISTER 15-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3)
bit 7 bit 0
Legend:
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
Note 1: In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as inputs or outputs.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

PIC18F6390/6490/8390/8490
15.3.2 OPERATION reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
When initializing the SPI, several options need to be
will be ignored and the Write Collision Detect bit,
specified. This is done by programming the appropriate
WCOL (SSPCON1<7>), will be set. User software
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
must clear the WCOL bit so that it can be determined if
These control bits allow the following to be specified:
the following write(s) to the SSPBUF register
• Master mode (SCK is the clock output) completed successfully.
• Slave mode (SCK is the clock input) When the application software is expecting to receive
• Clock Polarity (Idle state of SCK) valid data, the SSPBUF should be read before the next
• Data Input Sample Phase (middle or end of data byte of data to transfer is written to the SSPBUF. The
output time) Buffer Full bit, BF (SSPSTAT<0>), indicates when
• Clock Edge (output data on rising/falling edge of SSPBUF has been loaded with the received data
SCK) (transmission is complete). When the SSPBUF is read,
• Clock Rate (Master mode only) the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
• Slave Select mode (Slave mode only)
is used to determine when the transmission/reception
The MSSP consists of a Transmit/Receive Shift regis- has completed. The SSPBUF must be read and/or
ter (SSPSR) and a Buffer register (SSPBUF). The written. If the interrupt method is not going to be used,
SSPSR shifts the data in and out of the device, MSb then software polling can be done to ensure that a write
first. The SSPBUF holds the data that was written to the collision does not occur. Example 15-1 shows the
SSPSR until the received data is ready. Once the 8 bits loading of the SSPBUF (SSPSR) for data transmission.
of data have been received, that byte is moved to the
The SSPSR is not directly readable or writable and can
SSPBUF register. Then, the Buffer Full detect bit, BF
only be accessed by addressing the SSPBUF register.
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
Additionally, the MSSP Status register (SSPSTAT)
set. This double-buffering of the received data
indicates the various status conditions.
(SSPBUF) allows the next byte to start reception before
EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit

PIC18F6390/6490/8390/8490
15.3.3 ENABLING SPI I/O 15.3.4 TYPICAL CONNECTION
To enable the serial port, MSSP Enable bit, SSPEN Figure 15-2 shows a typical connection between two
(SSPCON1<5>), must be set. To reset or reconfigure microcontrollers. The master controller (Processor 1)
SPI mode, clear the SSPEN bit, reinitialize the initiates the data transfer by sending the SCK signal.
SSPCONx registers and then set the SSPEN bit. This Data is shifted out of both shift registers on their
configures the SDI, SDO, SCK and SS pins as serial programmed clock edge and latched on the opposite
port pins. For the pins to behave as the serial port func- edge of the clock. Both processors should be
tion, some must have their data direction bits (in the programmed to the same Clock Polarity (CKP), then
TRIS register) appropriately programmed as follows: both controllers would send and receive data at the
• SDI is automatically controlled by the SPI module same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
• SDO must have TRISC<5> bit cleared
to three scenarios for data transmission:
• SCK (Master mode) must have TRISC<3> bit
cleared • Master sends data – Slave sends dummy data
• SCK (Slave mode) must have TRISC<3> bit set • Master sends data – Slave sends data
• SS must have TRISF<7> bit set • Master sends dummy data – Slave sends data
Any serial port function that is not desired may be

overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value.
FIGURE 15-2: SPI MASTER/SLAVE CONNECTION
SPI Master (SSPM3:SSPM0 = 00xx) SPI Slave (SSPM3:SSPM0 = 010x)
SDO SDI
Serial Input Buffer Serial Input Buffer

(SSPBUF) (SSPBUF)
Shift Register SDI SDO Shift Register

(SSPSR) (SSPSR)
MSb LSb MSb LSb

Serial Clock
SCK SCK
PROCESSOR 1 PROCESSOR 2

PIC18F6390/6490/8390/8490
15.3.5 MASTER MODE The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This then,
The master can initiate the data transfer at any time
would give waveforms for SPI communication, as
because it controls the SCK. The master determines
shown in Figure 15-3, Figure 15-5 and Figure 15-6,
when the slave (Processor 2, Figure 15-2) is to
where the MSB is transmitted first. In Master mode, the
broadcast data by the software protocol.
SPI clock rate (bit rate) is user programmable to be one
In Master mode, the data is transmitted/received as of the following:
soon as the SSPBUF register is written to. If the SPI is
• FOSC/4 (or TCY)
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR regis- • FOSC/16 (or 4 • TCY)
ter will continue to shift in the signal present on the SDI • FOSC/64 (or 16 • TCY)
pin at the programmed clock rate. As each byte is • Timer2 output/2
received, it will be loaded into the SSPBUF register as
This allows a maximum data rate (at 40 MHz) of
if a normal received byte (interrupts and status bits
10.00 Mbps.
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode. Figure 15-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 15-3: SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDI
(SMP = 1) bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 Cycle
SSPSR to after Q2↓
SSPBUF

PIC18F6390/6490/8390/8490
15.3.6 SLAVE MODE even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
In Slave mode, the data is transmitted and received as
may be desirable depending on the application.
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set. Note 1: When the SPI is in Slave mode with SS pin
While in Slave mode, the external clock is supplied by control enabled (SSPCON<3:0> = 0100),
the external clock source on the SCK pin. This external the SPI module will reset if the SS pin is set
clock must meet the minimum high and low times as to VDD.
specified in the electrical specifications. 2: If the SPI is used in Slave mode with CKE
While in Sleep mode, the slave can transmit/receive set, then the SS pin control must be
data. When a byte is received, the device will wake-up enabled.
from Sleep. When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
15.3.7 SLAVE SELECT a high level or clearing the SSPEN bit.
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
The SS pin allows a Synchronous Slave mode. The be connected to the SDI pin. When the SPI needs to
SPI must be in Slave mode with SS pin control enabled operate as a receiver, the SDO pin can be configured
(SSPCON1<3:0> = 04h). The pin must not be driven as an input. This disables transmissions from the SDO.
low for the SS pin to function as an input. The data latch The SDI can always be left as an input (SDI function)
must be high. When the SS pin is low, transmission and since it cannot create a bus conflict.
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
FIGURE 15-4: SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO bit 7 bit 6 bit 7 bit 0
SDI bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPBUF

PIC18F6390/6490/8390/8490
FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
SSPBUF
FIGURE 15-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2↓
SSPSR to
SSPBUF

PIC18F6390/6490/8390/8490
15.3.8 SLEEP OPERATION 15.3.9 EFFECTS OF A RESET
In SPI Master mode, module clocks may be operating A Reset disables the MSSP module and terminates the
at a different speed than when in Full-Power mode; in current transfer.
the case of Sleep mode, all clocks are halted.
15.3.10 BUS MODE COMPATIBILITY
In most power-managed modes, a clock is provided to
the peripherals. That clock should be from the primary Table 15-1 shows the compatibility between the
clock source, the secondary clock (Timer1 oscillator at standard SPI modes and the states of the CKP and
32.768 kHz) or the INTOSC source. See Section 2.7 CKE control bits.
“Clock Sources and Oscillator Switching” for
additional information. TABLE 15-1: SPI BUS MODES
In most cases, the speed that the master clocks SPI Control Bits State
Standard SPI Mode
data is not important; however, this should be
Terminology CKP CKE
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con- 0, 0 0 1
troller from Sleep mode, or one of the Idle modes, when 0, 1 0 0
the master completes sending data. If an exit from
1, 0 1 1
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled. 1, 1 1 0
If the Sleep mode is selected, all module clocks are There is also an SMP bit which controls when the data
halted and the transmission/reception will remain in is sampled.
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
TABLE 15-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Reset
on Page
SSPBUF MSSP Receive Buffer/Transmit Register 60
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 60
SSPSTAT SMP CKE D/A P S R/W UA BF 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

PIC18F6390/6490/8390/8490
15.4 I2C Mode 15.4.1 REGISTERS
The MSSP module in I 2C mode fully implements all The MSSP module has six registers for I2C operation.
master and slave functions (including general call These are:
support) and provides interrupts on Start and Stop bits • MSSP Control Register 1 (SSPCON1)
in hardware to determine a free bus (multi-master • MSSP Control Register 2 (SSPCON2)
function). The MSSP module implements the standard
• MSSP Status Register (SSPSTAT)
mode specifications, as well as 7-bit and 10-bit
addressing. • Serial Receive/Transmit Buffer Register
(SSPBUF)
Two pins are used for data transfer:
• MSSP Shift Register (SSPSR) – Not directly
• Serial clock (SCL) – RC3/SCK/SCL accessible
• Serial data (SDA) – RC4/SDI/SDA • MSSP Address Register (SSPADD)
The user must configure these pins as inputs by setting SSPCON1, SSPCON2 and SSPSTAT are the control
the TRISC<4:3> bits. and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
FIGURE 15-7: MSSP BLOCK DIAGRAM writable. The lower 6 bits of the SSPSTAT are read-only.
(I2C™ MODE) The upper 2 bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
Internal out. SSPBUF is the buffer register to which data bytes
Data Bus
are written to, or read from.
Read Write
SSPADD register holds the slave device address
when the MSSP is configured in I2C Slave mode.
SSPBUF reg
RC3/SCK/SCL When the MSSP is configured in Master mode, the
lower 7 bits of SSPADD act as the Baud Rate
Shift
Clock Generator reload value.
SSPSR reg In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
RC4/ MSb LSb
SDI/ receives a complete byte, it is transferred to SSPBUF
SDA and the SSPIF interrupt is set.
Match Detect Addr Match
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
SSPADD reg and SSPSR.
Start and Set, Reset

Stop bit Detect S, P bits
(SSPSTAT reg)

PIC18F6390/6490/8390/8490
REGISTER 15-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P(1) S(1) R/W(2,3) UA BF
bit 7 bit 0
Legend:
bit 7 SMP: Slew Rate Control bit

In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit(2,3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1 UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Note 1: This bit is cleared on Reset and when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.

PIC18F6390/6490/8390/8490
REGISTER 15-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
(1) (2) (2) (2)
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0(2)
bit 7 bit 0
Legend:
bit 7 WCOL: Write Collision Detect bit

In Master Transmit mode:
1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit(1)
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Releases clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits(2)
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note 1: When enabled, the SDA and SCL pins must be configured as inputs.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

PIC18F6390/6490/8390/8490
REGISTER 15-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE)
GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2)
bit 7 bit 0
Legend:
bit 7 GCEN: General Call Enable bit (Slave mode only)

1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(2)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only)(2)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)(2)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(2)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit(2)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is not in the Idle mode, these bits may not be set (no spooling) and the SSPBUF may not
be written (or writes to the SSPBUF are disabled).

PIC18F6390/6490/8390/8490
15.4.2 OPERATION 15.4.3.1 Addressing
The MSSP module functions are enabled by setting Once the MSSP module has been enabled, it waits for
MSSP Enable bit, SSPEN (SSPCON1<5>). a Start condition to occur. Following the Start condition,
The SSPCON1 register allows control of the I 2C the 8 bits are shifted into the SSPSR register. All
operation. Four mode selection bits (SSPCON1<3:0>) incoming bits are sampled with the rising edge of the
allow one of the following I 2C modes to be selected: clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
• I2C Master mode, clock = (FOSC/4) x (SSPADD + 1) address is compared on the falling edge of the eighth
• I 2C Slave mode (7-bit address) clock (SCL) pulse. If the addresses match and the BF
• I 2C Slave mode (10-bit address) and SSPOV bits are clear, the following events occur:
• I 2C Slave mode (7-bit address) with Start and 1. The SSPSR register value is loaded into the
Stop bit interrupts enabled SSPBUF register.
• I 2C Slave mode (10-bit address) with Start and 2. The Buffer Full bit, BF, is set.
Stop bit interrupts enabled 3. An ACK pulse is generated.
• I 2C Firmware Controlled Master mode, slave is 4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
Idle set (interrupt is generated, if enabled) on the
Selection of any I 2C mode with the SSPEN bit set, falling edge of the ninth SCL pulse.
forces the SCL and SDA pins to be open-drain, In 10-Bit Addressing mode, two address bytes need to
provided these pins are programmed to inputs by be received by the slave. The five Most Significant bits
setting the appropriate TRISC bits. To ensure proper (MSbs) of the first address byte specify if this is a 10-bit
operation of the module, pull-up resistors must be address. Bit R/W (SSPSTAT<2>) must specify a write
provided externally to the SCL and SDA pins. so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
15.4.3 SLAVE MODE ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the
In Slave mode, the SCL and SDA pins must be config- two MSbs of the address. The sequence of events for
ured as inputs (TRISC<4:3> set). The MSSP module 10-Bit Addressing mode is as follows, with steps 7
will override the input state with the output data when through 9 for the slave-transmitter:
required (slave-transmitter). 1. Receive first (high) byte of address (bits SSPIF,
The I 2C Slave mode hardware will always generate an BF and UA (SSPSTAT<1>) are set).
interrupt on an address match. Through the mode 2. Update the SSPADD register with second (low)
select bits, the user can also choose to interrupt on byte of address (clears bit UA and releases the
Start and Stop bits SCL line).
When an address is matched, or the data transfer after 3. Read the SSPBUF register (clears bit, BF) and
an address match is received, the hardware auto- clear flag bit, SSPIF.
matically will generate the Acknowledge (ACK) pulse 4. Receive second (low) byte of address (bits
and load the SSPBUF register with the received value SSPIF, BF and UA are set).
currently in the SSPSR register. 5. Update the SSPADD register with the first (high)
Any combination of the following conditions will cause byte of address. If match releases SCL line, this
the MSSP module not to give this ACK pulse: will clear bit, UA.
• The Buffer Full bit, BF (SSPSTAT<0>), was set 6. Read the SSPBUF register (clears bit, BF) and
before the transfer was received. clear flag bit, SSPIF.
• The overflow bit, SSPOV (SSPCON1<6>), was 7. Receive Repeated Start condition.
set before the transfer was received. 8. Receive first (high) byte of address (SSPIF and
In this case, the SSPSR register value is not loaded BF bits are set).
into the SSPBUF, but the SSPIF bit (PIR1<3>) is set. 9. Read the SSPBUF register (clears bit, BF) and
The BF bit is cleared by reading the SSPBUF register, clear flag bit, SSPIF.
while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification, as well as the requirement of
the MSSP module, are shown in timing parameter #100
and parameter #101.

PIC18F6390/6490/8390/8490
15.4.3.2 Reception 15.4.3.3 Transmission
When the R/W bit of the address byte is clear and an When the R/W bit of the incoming address byte is set
address match occurs, the R/W bit of the SSPSTAT and an address match occurs, the R/W bit of the
register is cleared. The received address is loaded into SSPSTAT register is set. The received address is
the SSPBUF register and the SDA line is held low loaded into the SSPBUF register. The ACK pulse will
(ACK). be sent on the ninth bit and pin RC3/SCK/SCL is held
When the address byte overflow condition exists, then low regardless of SEN (see Section 15.4.4 “Clock
the no Acknowledge (ACK) pulse is given. An overflow Stretching” for more detail). By stretching the clock,
condition is defined as either bit BF (SSPSTAT<0>) is the master will be unable to assert another clock pulse
set, or bit SSPOV (SSPCON1<6>) is set. until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
An MSSP interrupt is generated for each data transfer which also loads the SSPSR register. Then, pin RC3/
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in SCK/SCL should be enabled by setting bit, CKP
software. The SSPSTAT register is used to determine (SSPCON1<4>). The 8 data bits are shifted out on the
the status of the byte. falling edge of the SCL input. This ensures that the
If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL SDA signal is valid during the SCL high time
will be held low (clock stretch) following each data (Figure 15-9).
transfer. The clock must be released by setting bit The ACK pulse from the master-receiver is latched on
CKP (SSPCON1<4>). See Section 15.4.4 “Clock the rising edge of the ninth SCL input pulse. If the SDA
Stretching” for more detail. line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset and the slave monitors for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, pin RC3/SCK/SCL must
be enabled by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.

FIGURE 15-8:
DS39629C-page 172
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
PIC18F6390/6490/8390/8490
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP (SSPCON1<4>)
(CKP does not reset to ‘0’ when SEN = 0)
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
© 2007 Microchip Technology Inc.

FIGURE 15-9:
Receiving Address R/W = 1 Transmitting Data Transmitting Data

ACK ACK

SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCL held low P
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Cleared in software Cleared in software
From SSPIF ISR From SSPIF ISR
SSPBUF is written in software SSPBUF is written in software
Clear by reading
CKP (SSPCON1<4>)
CKP is set in software CKP is set in software

I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
PIC18F6390/6490/8390/8490
DS39629C-page 173
FIGURE 15-10:
DS39629C-page 174
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF (PIR1<3>) transfer
Cleared in software Cleared in software Cleared in software

Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with Dummy read of SSPBUF

contents of SSPSR to clear BF flag
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
PIC18F6390/6490/8390/8490
UA (SSPSTAT<1>)
UA is set indicating that Cleared by hardware Cleared by hardware when

the SSPADD needs to be when SSPADD is updated SSPADD is updated with high
updated with low byte of address byte of address
UA is set indicating that

SSPADD needs to be
updated
CKP (SSPCON1<4>)
(CKP does not reset to ‘0’ when SEN = 0)

FIGURE 15-11:
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPADD has update of SSPADD has Clock is held low until

taken place taken place CKP is set to ‘1’
R/W = 0
Receive First Byte of Address Receive Second Byte of Address Receive First Byte of Address R/W=1 Transmitting Data Byte ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
SSPIF (PIR1<3>)
Cleared in software Cleared in software Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF

contents of SSPSR to clear BF flag BF flag is clear Write of SSPBUF Completion of
to clear BF flag initiates transmit data transmission
at the end of the
UA (SSPSTAT<1>) third address sequence clears BF flag
UA is set indicating that Cleared by hardware when Cleared by hardware when

the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high
updated byte of address byte of address.

SSPADD needs to be
updated
CKP (SSPCON1<4>)
CKP is set in software
CKP is automatically cleared in hardware, holding SCL low

I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
PIC18F6390/6490/8390/8490
DS39629C-page 175
PIC18F6390/6490/8390/8490
15.4.4 CLOCK STRETCHING 15.4.4.3 Clock Stretching for 7-Bit Slave
Both 7 and 10-Bit Slave modes implement automatic Transmit Mode
clock stretching during a transmit sequence. 7-Bit Slave Transmit mode implements clock stretching
The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the ninth
be enabled during receives. Setting SEN will cause clock, if the BF bit is clear. This occurs regardless of the
the SCL pin to be held low at the end of each data state of the SEN bit.
receive sequence. The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
15.4.4.1 Clock Stretching for 7-Bit Slave low, the user has time to service the ISR and load the
Receive Mode (SEN = 1) contents of the SSPBUF before the master device can
In 7-Bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure 15-9).
ninth clock at the end of the ACK sequence, if the BF Note 1: If the user loads the contents of SSPBUF,
bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of
automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be
held low. The CKP being cleared to ‘0’ will assert the cleared and clock stretching will not occur.
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding 2: The CKP bit can be set in software
the SCL line low, the user has time to service the ISR regardless of the state of the BF bit.
and read the contents of the SSPBUF before the
15.4.4.4 Clock Stretching for 10-Bit Slave
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see Transmit Mode
Figure 15-13). In 10-Bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
Note 1: If the user reads the contents of the
the state of the UA bit, just as it is in 10-Bit Slave
SSPBUF before the falling edge of the
Receive mode. The first two addresses are followed
ninth clock, thus clearing the BF bit, the
by a third address sequence which contains the high-
CKP bit will not be cleared and clock
order bits of the 10-bit address and the R/W bit set to
stretching will not occur.
‘1’. After the third address sequence is performed, the
2: The CKP bit can be set in software UA bit is not set, the module is now configured in
regardless of the state of the BF bit. The Transmit mode and clock stretching is controlled by
user should be careful to clear the BF bit the BF flag as in 7-Bit Slave Transmit mode (see
in the ISR before the next receive Figure 15-11).
sequence in order to prevent an overflow
condition.
15.4.4.2 Clock Stretching for 10-Bit Slave

Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.

PIC18F6390/6490/8390/8490
15.4.4.5 Clock Synchronization and already asserted the SCL line. The SCL output will
the CKP bit remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
When the CKP bit is cleared, the SCL output is forced
ensures that a write to the CKP bit will not violate the
to ‘0’. However, setting the CKP bit will not assert the
minimum high time requirement for SCL (see
SCL output low until the SCL output is already sam-
Figure 15-12).
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
FIGURE 15-12: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX – 1
SCL
Master device
CKP asserts clock
Master device
deasserts clock
WR
SSPCON

FIGURE 15-13:
DS39629C-page 178
Clock is not held low
because buffer full bit is
clear prior to falling edge Clock is held low until Clock is not held low
of 9th clock CKP is set to ‘1’ because ACK = 1
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
PIC18F6390/6490/8390/8490
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
CKP (SSPON1<4>)
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the 9th clock, software
CKP will not be reset BF is set after falling
to ‘0’ and no clock edge of the 9th clock,
stretching will occur CKP is reset to ‘0’ and
clock stretching occurs

FIGURE 15-14:
Clock is held low until Clock is held low until

update of SSPADD has update of SSPADD has Clock is not held low
Clock is held low until
taken place taken place because ACK = 1
CKP is set to ‘1’
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
ACK ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF (PIR1<3>)
Bus master
terminates
Cleared in software Cleared in software Cleared in software transfer
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF

contents of SSPSR to clear BF flag to clear BF flag
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
UA (SSPSTAT<1>)
UA is set indicating that Cleared by hardware when Cleared by hardware when

the SSPADD needs to be SSPADD is updated with low SSPADD is updated with high
updated byte of address after falling edge byte of address after falling edge
of ninth clock of ninth clock

SSPADD needs to be
updated
CKP (SSPCON1<4>)
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will CKP written to ‘1’
have no effect on UA and in software
UA will remain set.
Note: An update of the SSPADD register before

the falling edge of the ninth clock will have
no effect on UA and UA will remain set.
PIC18F6390/6490/8390/8490
DS39629C-page 179
PIC18F6390/6490/8390/8490
15.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is
SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
The addressing procedure for the I2C bus is such that
SSPIF interrupt flag bit is set.
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the When the interrupt is serviced, the source for the inter-
master. The exception is the general call address which rupt can be checked by reading the contents of the
can address all devices. When this address is used, all SSPBUF. The value can be used to determine if the
devices should, in theory, respond with an address was device specific or a general call address.
Acknowledge. In 10-bit mode, the SSPADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match and the UA
reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is
consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
The general call address is recognized when the
half of the address is not necessary, the UA bit will not
General Call Enable bit (GCEN) is enabled
be set and the slave will begin receiving data after the
(SSPCON2<7> set). Following a Start bit detect, 8 bits
Acknowledge (Figure 15-15).
are shifted into the SSPSR and the address is
compared against the SSPADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 15-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESSING MODE)
Address is compared to General Call Address

after ACK, set interrupt
R/W = 0 Receiving Data ACK

SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>) ‘0’
GCEN (SSPCON2<7>)
‘1’

PIC18F6390/6490/8390/8490
15.4.6 MASTER MODE Note: The MSSP module, when configured in
Master mode is enabled by setting and clearing the I2C Master mode, does not allow queueing
appropriate SSPM bits in SSPCON1 and by setting the of events. For instance, the user is not
SSPEN bit. In Master mode, the SCL and SDA lines allowed to initiate a Start condition and
are manipulated by the MSSP hardware. immediately write the SSPBUF register to
initiate transmission before the Start condi-
Master mode of operation is supported by interrupt
tion is complete. In this case, the SSPBUF
generation on the detection of the Start and Stop
will not be written to and the WCOL bit will
conditions. The Stop (P) and Start (S) bits are cleared
be set, indicating that a write to the
from a Reset or when the MSSP module is disabled.
SSPBUF did not occur.
Control of the I 2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear. The following events will cause the MSSP Interrupt
In Firmware Controlled Master mode, user code Flag bit, SSPIF, to be set (MSSP interrupt, if enabled):
conducts all I 2C bus operations based on Start and • Start condition
Stop bit conditions.
• Stop condition
Once Master mode is enabled, the user has six • Data transfer byte transmitted/received
options.
• Acknowledge transmit
1. Assert a Start condition on SDA and SCL. • Repeated Start
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
FIGURE 15-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal SSPM3:SSPM0
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA In Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Start bit, Stop bit,

Clock Cntl
Acknowledge
Generate
SCL
Start bit Detect

Stop bit Detect
SCL In Write Collision Detect Set/Reset, S, P, WCOL (SSPSTAT),
Clock Arbitration Set SSPIF, BCLIF,
Bus Collision State Counter for Reset ACKSTAT, PEN (SSPCON2)
end of XMIT/RCV

PIC18F6390/6490/8390/8490
15.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows:
The master device generates all of the serial clock 1. The user generates a Start condition by setting
pulses and the Start and Stop conditions. A transfer is the Start Enable bit, SEN (SSPCON2<0>).
ended with a Stop condition or with a Repeated Start 2. SSPIF is set. The MSSP module will wait the
condition. Since the Repeated Start condition is also required start time before any other operation
the beginning of the next serial transfer, the I2C bus will takes place.
not be released. 3. The user loads the SSPBUF with the slave
In Master Transmitter mode, serial data is output address to transmit.
through SDA, while SCL outputs the serial clock. The 4. Address is shifted out the SDA pin until all 8 bits
first byte transmitted contains the slave address of the are transmitted.
receiving device (7 bits) and the Read/Write (R/W) bit. 5. The MSSP module shifts in the ACK bit from the
In this case, the R/W bit will be logic ‘0’. Serial data is slave device and writes its value into the
transmitted 8 bits at a time. After each byte is transmit- SSPCON2 register (SSPCON2<6>).
ted, an Acknowledge bit is received. Start and Stop
6. The MSSP module generates an interrupt at the
conditions are output to indicate the beginning and the
end of the ninth clock cycle by setting the SSPIF
end of a serial transfer.
bit.
In Master Receive mode, the first byte transmitted 7. The user loads the SSPBUF with 8 bits of data.
contains the slave address of the transmitting device
8. Data is shifted out the SDA pin until all 8 bits are
(7 bits) and the R/W bit. In this case, the R/W bit will be
transmitted.
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address, followed by a ‘1’ to indicate the receive bit. 9. The MSSP module shifts in the ACK bit from the
Serial data is received via SDA, while SCL outputs the slave device and writes its value into the
serial clock. Serial data is received 8 bits at a time. After SSPCON2 register (SSPCON2<6>).
each byte is received, an Acknowledge bit is transmit- 10. The MSSP module generates an interrupt at the
ted. Start and Stop conditions indicate the beginning end of the ninth clock cycle by setting the SSPIF
and end of transmission. bit.
The Baud Rate Generator used for the SPI mode 11. The user generates a Stop condition by setting
operation is used to set the SCL clock frequency for the Stop Enable bit, PEN (SSPCON2<2>).
either 100 kHz, 400 kHz or 1 MHz I2C operation. See 12. Interrupt is generated once the Stop condition is
Section 15.4.7 “Baud Rate” for more detail. complete.

PIC18F6390/6490/8390/8490
15.4.7 BAUD RATE Once the given operation is complete (i.e., transmis-
2 sion of the last data bit is followed by ACK), the internal
In I C Master mode, the Baud Rate Generator (BRG)
clock will automatically stop counting and the SCL pin
reload value is placed in the lower 7 bits of the
will remain in its last state.
SSPADD register (Figure 15-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically Table 15-3 demonstrates clock rates based on
begin counting. The BRG counts down to 0 and stops instruction cycles and the BRG value loaded into
until another reload has taken place. The BRG count is SSPADD.
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
FIGURE 15-17: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0 SSPADD<6:0>
SSPM3:SSPM0 Reload Reload

SCL Control
CLKO BRG Down Counter FOSC/4
TABLE 15-3: I2C™ CLOCK RATE w/BRG

FSCL
FCY FCY * 2 BRG Value
(2 Rollovers of BRG)
10 MHz 20 MHz 19h 400 kHz(1)
10 MHz 20 MHz 20h 312.5 kHz
10 MHz 20 MHz 3Fh 100 kHz
4 MHz 8 MHz 0Ah 400 kHz(1)
4 MHz 8 MHz 0Dh 308 kHz
4 MHz 8 MHz 28h 100 kHz
1 MHz 2 MHz 03h 333 kHz(1)
1 MHz 2 MHz 0Ah 100 kHz
1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.

PIC18F6390/6490/8390/8490
15.4.7.1 Clock Arbitration SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
Clock arbitration occurs when the master, during any
begins counting. This ensures that the SCL high time
receive, transmit or Repeated Start/Stop condition,
will always be at least one BRG rollover count in the
deasserts the SCL pin (SCL allowed to float high).
event that the clock is held low by an external device
When the SCL pin is allowed to float high, the Baud
(Figure 15-18).
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 15-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA DX DX – 1
SCL deasserted but slave holds SCL allowed to transition high

SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload

PIC18F6390/6490/8390/8490
15.4.8 I2C MASTER MODE START Note: If at the beginning of the Start condition,
CONDITION TIMING the SDA and SCL pins are already sam-
To initiate a Start condition, the user sets the Start pled low, or if during the Start condition, the
Condition Enable bit, SEN (SSPCON2<0>). If the SDA SCL line is sampled low before the SDA
and SCL pins are sampled high, the Baud Rate Gener- line is driven low, a bus collision occurs,
ator is reloaded with the contents of SSPADD<6:0> the Bus Collision Interrupt Flag, BCLIF, is
and starts its count. If SCL and SDA are both sampled set, the Start condition is aborted and the
high when the Baud Rate Generator times out (TBRG), I2C module is reset into its Idle state.
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the Start condition and 15.4.8.1 WCOL Status Flag
causes the S bit (SSPSTAT<3>) to be set. Following If the user writes the SSPBUF when a Start sequence
this, the Baud Rate Generator is reloaded with the is in progress, the WCOL is set and the contents of the
contents of SSPADD<6:0> and resumes its count. buffer are unchanged (the write doesn’t occur).
When the Baud Rate Generator times out (TBRG), the
Note: Because queueing of events is not
SEN bit (SSPCON2<0>) will be automatically cleared
allowed, writing to the lower 5 bits of
by hardware, the Baud Rate Generator is suspended,
SSPCON2 is disabled until the Start
leaving the SDA line held low and the Start condition is
condition is complete.
complete.
FIGURE 15-19: FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here
SDA = 1,
At completion of Start bit,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG TBRG Write to SSPBUF occurs here
1st bit 2nd bit

SDA
TBRG
SCL
TBRG
S

PIC18F6390/6490/8390/8490
15.4.9 I2C MASTER MODE REPEATED Note 1: If RSEN is programmed while any other
START CONDITION TIMING event is in progress, it will not take effect.
A Repeated Start condition occurs when the RSEN bit 2: A bus collision during the Repeated Start
(SSPCON2<1>) is programmed high and the I2C logic condition occurs if:
module is in the Idle state. When the RSEN bit is set, • SDA is sampled low when SCL goes
the SCL pin is asserted low. When the SCL pin is from low-to-high.
sampled low, the Baud Rate Generator is loaded with
• SCL goes low before SDA is
the contents of SSPADD<5:0> and begins counting.
asserted low. This may indicate that
The SDA pin is released (brought high) for one Baud
another master is attempting to
Rate Generator count (TBRG). When the Baud Rate
transmit a data ‘1’.
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is Immediately following the SSPIF bit getting set, the user
sampled high, the Baud Rate Generator is reloaded may write the SSPBUF with the 7-bit address in 7-bit
with the contents of SSPADD<6:0> and begins count- mode, or the default first address in 10-bit mode. After
ing. SDA and SCL must be sampled high for one TBRG. the first 8 bits are transmitted and an ACK is received,
This action is then followed by assertion of the SDA pin the user may then transmit an additional eight bits of
(SDA = 0) for one TBRG while SCL is high. Following address (10-bit mode) or 8 bits of data (7-bit mode).
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be 15.4.9.1 WCOL Status Flag
reloaded, leaving the SDA pin held low. As soon as a If the user writes the SSPBUF when a Repeated Start
Start condition is detected on the SDA and SCL pins, sequence is in progress, the WCOL is set and the
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will contents of the buffer are unchanged (the write doesn’t
not be set until the Baud Rate Generator has timed out. occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
FIGURE 15-20: REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
occurs here. At completion of Start bit,
SDA = 1, SCL = 1
hardware clears RSEN bit
SCL (no change). and sets SSPIF
TBRG TBRG TBRG
SDA 1st bit
Falling edge of ninth clock, Write to SSPBUF occurs here

end of Xmit
TBRG
SCL
TBRG
Sr = Repeated Start

PIC18F6390/6490/8390/8490
15.4.10 I2C MASTER MODE 15.4.10.3 ACKSTAT Status Flag
TRANSMISSION In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
Transmission of a data byte, a 7-bit address or the cleared when the slave has sent an Acknowledge
other half of a 10-bit address is accomplished by simply (ACK = 0) and is set when the slave does not Acknowl-
writing a value to the SSPBUF register. This action will edge (ACK = 1). A slave sends an Acknowledge when
set the Buffer Full flag bit, BF, and allow the Baud Rate it has recognized its address (including a general call),
Generator to begin counting and start the next trans- or when the slave has properly received its data.
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is 15.4.11 I2C MASTER MODE RECEPTION
asserted (see data hold time specification parameter Master mode reception is enabled by programming the
#106). SCL is held low for one Baud Rate Generator Receive Enable bit, RCEN (SSPCON2<3>).
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification Note: The MSSP module must be in an Idle state
parameter #107). When the SCL pin is released high, it before the RCEN bit is set or the RCEN bit
is held that way for TBRG. The data on the SDA pin will be disregarded.
must remain stable for that duration and some hold The Baud Rate Generator begins counting and on each
time after the next falling edge of SCL. After the eighth rollover, the state of the SCL pin changes (high-to-low/
bit is shifted out (the falling edge of the eighth clock), low-to-high) and data is shifted into the SSPSR. After
the BF flag is cleared and the master releases SDA. the falling edge of the eighth clock, the receive enable
This allows the slave device being addressed to flag is automatically cleared, the contents of the
respond with an ACK bit during the ninth bit time if an SSPSR are loaded into the SSPBUF, the BF flag bit is
address match occurred, or if data was received set, the SSPIF flag bit is set and the Baud Rate
properly. The status of ACK is written into the ACKDT Generator is suspended from counting, holding SCL
bit on the falling edge of the ninth clock. If the master low. The MSSP is now in Idle state awaiting the next
receives an Acknowledge, the Acknowledge Status bit, command. When the buffer is read by the CPU, the BF
ACKSTAT, is cleared. If not, the bit is set. After the ninth flag bit is automatically cleared. The user can then
clock, the SSPIF bit is set and the master clock (Baud send an Acknowledge bit at the end of reception by
Rate Generator) is suspended until the next data byte setting the Acknowledge Sequence Enable bit, ACKEN
is loaded into the SSPBUF, leaving SCL low and SDA (SSPCON2<4>).
unchanged (Figure 15-21).
After the write to the SSPBUF, each bit of address will 15.4.11.1 BF Status Flag
be shifted out on the falling edge of SCL until all In receive operation, the BF bit is set when an address
7 address bits and the R/W bit are completed. On the or data byte is loaded into SSPBUF from SSPSR. It is
falling edge of the eighth clock, the master will deassert cleared when the SSPBUF register is read.
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the 15.4.11.2 SSPOV Status Flag
master will sample the SDA pin to see if the address In receive operation, the SSPOV bit is set when 8 bits
was recognized by a slave. The status of the ACK bit is are received into the SSPSR and the BF flag bit is
loaded into the ACKSTAT status bit (SSPCON2<6>). already set from a previous reception.
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is 15.4.11.3 WCOL Status Flag
cleared and the Baud Rate Generator is turned off until
If the user writes the SSPBUF when a receive is
another write to the SSPBUF takes place, holding SCL
already in progress (i.e., SSPSR is still shifting in a data
low and allowing SDA to float.
byte), the WCOL bit is set and the contents of the buffer
15.4.10.1 BF Status Flag are unchanged (the write doesn’t occur).
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
15.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.

FIGURE 15-21:
DS39629C-page 188
Write SSPCON2<0> SEN = 1 ACKSTAT in
Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit Address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
SSPBUF written with 7-bit address and R/W

start transmit
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCL held low
while CPU
responds to SSPIF
SSPIF
Cleared in software service routine
Cleared in software from MSSP interrupt
Cleared in software
BF (SSPSTAT<0>)
SSPBUF written SSPBUF is written in software

PIC18F6390/6490/8390/8490
SEN
After Start condition, SEN cleared by hardware
PEN
R/W
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

FIGURE 15-22:
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
begin Start Condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)

PEN bit = 1
Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave R/W = 1 Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive
at end of Acknowledge
SSPIF sequence
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
SSPOV is set because

SSPBUF is still full
ACKEN
I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
PIC18F6390/6490/8390/8490
DS39629C-page 189
PIC18F6390/6490/8390/8490
15.4.12 ACKNOWLEDGE SEQUENCE 15.4.13 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/
(SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge
pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master
are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is
erate an Acknowledge, then the ACKDT bit should be sampled low, the Baud Rate Generator is reloaded and
cleared. If not, the user should set the ACKDT bit before counts down to ‘0’. When the Baud Rate Generator
starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one
Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the
and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is sam-
SCL pin is sampled high (clock arbitration), the Baud pled high while SCL is high, the P bit (SSPSTAT<4>) is
Rate Generator counts for TBRG. The SCL pin is then set. A TBRG later, the PEN bit is cleared and the SSPIF
pulled low. Following this, the ACKEN bit is automatically bit is set (Figure 15-24).
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 15-23). 15.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
15.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the
If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t
sequence is in progress, then WCOL is set and the occur).
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPIF
Cleared in
Set SSPIF at the end software
of receive Cleared in
software Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 15-24: STOP CONDITION RECEIVE OR TRANSMIT MODE

Write to SSPCON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG
set PEN after SDA sampled high. P bit (SSPSTAT<4>) is set.
Falling edge of PEN bit (SSPCON2<2>) is cleared by

9th clock hardware and the SSPIF bit is set
TBRG
SCL
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.

PIC18F6390/6490/8390/8490
15.4.14 SLEEP OPERATION 15.4.17 MULTI-MASTER COMMUNICATION,
2
While in Sleep mode, the I C module can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from Sleep (if the MSSP interrupt is enabled). tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
15.4.15 EFFECT OF A RESET outputs a ‘1’ on SDA, by letting SDA float high and
A Reset disables the MSSP module and terminates the another master asserts a ‘0’. When the SCL pin floats
current transfer. high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
15.4.16 MULTI-MASTER MODE then a bus collision has taken place. The master will set
In Multi-Master mode, the interrupt generation on the the Bus Collision Interrupt Flag, BCLIF and reset the
detection of the Start and Stop conditions allows the I2C port to its Idle state (Figure 15-25).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSP module is disabled. Control of the I 2C bus may cleared, the SDA and SCL lines are deasserted and the
be taken when the P bit (SSPSTAT<4>) is set, or the SSPBUF can be written to. When the user services the
bus is Idle, with both the S and P bits clear. When the bus collision Interrupt Service Routine and if the I2C
bus is busy, enabling the MSSP interrupt will generate bus is free, the user can resume communication by
the interrupt when the Stop condition occurs. asserting a Start condition.
In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge
monitored for arbitration to see if the signal level is the condition was in progress when the bus collision
expected output level. This check is performed in occurred, the condition is aborted, the SDA and SCL
hardware with the result placed in the BCLIF bit. lines are deasserted and the respective control bits in
The states where arbitration can be lost are: the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine and if
• Address Transfer the I2C bus is free, the user can resume communication
• Data Transfer by asserting a Start condition.
• A Start Condition The master will continue to monitor the SDA and SCL
• A Repeated Start Condition pins. If a Stop condition occurs, the SSPIF bit will be set.
• An Acknowledge Condition A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 15-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,
Data changes SDA line pulled low data doesn’t match what is driven
while SCL = 0 by another source by the master.
Bus collision has occurred.
SDA released
by master
SDA
SCL Set bus collision

interrupt (BCLIF)
BCLIF

PIC18F6390/6490/8390/8490
15.4.17.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the
Condition BRG is reset and the SDA line is asserted early
(Figure 15-28). If, however, a ‘1’ is sampled on the SDA
During a Start condition, a bus collision occurs if:
pin, the SDA pin is asserted low at the end of the BRG
a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and
the Start condition (Figure 15-26). counts down to 0 and during this time, if the SCL pins
b) SCL is sampled low before SDA is asserted low are sampled as ‘0’, a bus collision does not occur. At
(Figure 15-27). the end of the BRG count, the SCL pin is asserted low.
During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a factor
pins are monitored. during a Start condition is that no two bus
If the SDA pin is already low, or the SCL pin is already masters can assert a Start condition at the
low, then all of the following occur: exact same time. Therefore, one master
will always assert SDA before the other.
• the Start condition is aborted,
This condition does not cause a bus
• the BCLIF flag is set and collision because the two masters must be
• the MSSP module is reset to its Idle state allowed to arbitrate the first address follow-
(Figure 15-26). ing the Start condition. If the address is the
The Start condition begins with the SDA and SCL pins same, arbitration must be allowed to
deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated
Baud Rate Generator is loaded from SSPADD<6:0> Start or Stop conditions.
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 15-26: BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 MSSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF
SSPIF and BCLIF are

cleared in software

PIC18F6390/6490/8390/8490
FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG TBRG
SDA
SCL Set SEN, enable Start

sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S ‘0’ ‘0’
SSPIF ‘0’ ‘0’
FIGURE 15-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG TBRG
SDA SDA pulled low by other master.

Reset BRG and assert SDA.
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
BCLIF ‘0’
SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF in software

PIC18F6390/6490/8390/8490
15.4.17.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another
Start Condition master is attempting to transmit a data ‘0’, Figure 15-29).
If SDA is sampled high, the BRG is reloaded and begins
During a Repeated Start condition, a bus collision
counting. If SDA goes from high-to-low before the BRG
occurs if:
times out, no bus collision occurs because no two
a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time.
from low level to high level.
If SCL goes from high-to-low before the BRG times out
b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision
indicating that another master is attempting to occurs. In this case, another master is attempting to
transmit a data ‘1’. transmit a data ‘1’ during the Repeated Start condition
When the user deasserts SDA and the pin is allowed to (see Figure 15-30).
float high, the BRG is loaded with SSPADD<6:0> and If, at the end of the BRG time-out, both SCL and SDA
counts down to 0. The SCL pin is then deasserted and are still high, the SDA pin is driven low and the BRG is
when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 15-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
S ‘0’
SSPIF ‘0’
FIGURE 15-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA
SCL
SCL goes low before SDA,

BCLIF set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
RSEN
S ‘0’
SSPIF

PIC18F6390/6490/8390/8490
15.4.17.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low.
Condition When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSPADD<6:0>
a) After the SDA pin has been deasserted and and counts down to 0. After the BRG times out, SDA is
allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has
the BRG has timed out. occurred. This is due to another master attempting to
b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure 15-31). If the SCL pin is
low before SDA goes high. sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 15-32).
FIGURE 15-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDA sampled

low after TBRG,
set BCLIF
SDA
SDA asserted low

SCL
PEN
BCLIF
P ‘0’
SSPIF ‘0’
FIGURE 15-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA
Assert SDA SCL goes low before SDA goes high,

set BCLIF
SCL
PEN
BCLIF
P ‘0’
SSPIF ‘0’

PIC18F6390/6490/8390/8490
TABLE 15-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Page
SSPBUF MSSP Receive Buffer/Transmit Register 60
2 2
SSPADD MSSP Address Register in I C Slave Mode. MSSP Baud Rate Reload Register in I C Slave Mode. 60
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 60
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 60
SSPSTAT SMP CKE D/A P S R/W UA BF 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

PIC18F6390/6490/8390/8490
16.0 ENHANCED UNIVERSAL The pins of the EUSART are multiplexed with the
functions of PORTC (RC6/TX1/CK1 and
SYNCHRONOUS
RC7/RX1/DT1). In order to configure these pins as an
ASYNCHRONOUS RECEIVER EUSART:
TRANSMITTER (EUSART) • bit SPEN (RCSTA1<7>) must be set (= 1)
PIC18F6390/6490/8390/8490 devices have three • bit TRISC<7> must be set (= 1)
serial I/O modules: the MSSP module, discussed in the • bit TRISC<6> must be set (= 1)
previous chapter and two Universal Synchronous
Note: The USART control will automatically
Asynchronous Receiver Transmitter (USART) mod-
reconfigure the pin from input to output as
ules. (Generically, the USART is also known as a Serial
needed.
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that The operation of the Enhanced USART module is
can communicate with peripheral devices, such as controlled through three registers:
CRT terminals and personal computers. It can also be • Transmit Status and Control Register 1 (TXSTA1)
configured as a half-duplex synchronous system that • Receive Status and Control Register 1 (RCSTA1)
can communicate with peripheral devices, such as A/D
• Baud Rate Control Register 1 (BAUDCON1)
or D/A integrated circuits, serial EEPROMs, etc.
The registers are described in Register 16-1,
There are two distinct implementations of the USART
Register 16-2 and Register 16-3.
module in these devices: the Enhanced USART
(EUSART) discussed here and the Addressable
USART discussed in the next chapter. For this device
family, USART1 always refers to the EUSART, while
USART2 is always the AUSART.
The EUSART and AUSART modules implement the
same core features for serial communications; their
basic operation is essentially the same. The EUSART
module provides additional features, including
Automatic Baud Rate Detection (ABD) and calibration,
automatic wake-up on Sync Break reception and 12-bit
Break character transmit. These features make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity

PIC18F6390/6490/8390/8490
REGISTER 16-1: TXSTA1: EUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC18F6390/6490/8390/8490
REGISTER 16-2: RCSTA1: EUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX1/DT1 and TX1/CK1 pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-Bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG1 register and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit, CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC18F6390/6490/8390/8490
REGISTER 16-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1
R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit

1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Synchronous mode:
1 = Idle state for clock (CK1) is a high level
0 = Idle state for clock (CK1) is a low level
bit 3 BRG16: 16-Bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH1 and SPBRG1
0 = 8-bit Baud Rate Generator – SPBRG1 only (Compatible mode), SPBRGH1 value ignored
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX1 pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0 = RX1 pin not monitored or rising edge detected
Synchronous mode:
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0 = Baud rate measurement disabled or completed
Synchronous mode:

PIC18F6390/6490/8390/8490
16.1 EUSART Baud Rate Generator geous to use the high baud rate (BRGH = 1) or the 16-bit
(BRG) BRG to reduce the baud rate error, or achieve a slow
baud rate for a fast oscillator frequency.
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous Writing a new value to the SPBRGH1:SPBRG1 regis-
modes of the EUSART. By default, the BRG operates ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode. before outputting the new baud rate.
The SPBRGH1:SPBRG1 register pair controls the period 16.1.1 OPERATION IN POWER-MANAGED
of a free-running timer. In Asynchronous mode, the MODES
BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits
also control the baud rate. In Synchronous mode, BRGH The device clock is used to generate the desired baud
is ignored. Table 16-1 shows the formula for computation rate. When one of the power-managed modes is
of the baud rate for different EUSART modes that only entered, the new clock source may be operating at a
apply in Master mode (internally generated clock). different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH1:SPBRG1 registers can 16.1.2 SAMPLING
be calculated using the formulas in Table 16-1. From
this, the error in baud rate can be determined. An exam- The data on the RX1 pin is sampled three times by a
ple calculation is shown in Example 16-1. Typical baud majority detect circuit to determine if a high or a low
rates and error values for the various Asynchronous level is present at the RX1 pin.
modes are shown in Table 16-3. It may be advanta-
TABLE 16-1: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-Bit/Asynchronous FOSC/[64 (n + 1)]
0 0 1 8-Bit/Asynchronous
FOSC/[16 (n + 1)]
1 0 x 8-Bit/Synchronous FOSC/[4 (n + 1)]
1 1 x 16-Bit/Synchronous
Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
EXAMPLE 16-1: CALCULATING BAUD RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1))
Solving for SPBRGH1:SPBRG1:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
TABLE 16-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Reset Values
on Page
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 61
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 61
BAUDCON1 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 62
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 62
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

PIC18F6390/6490/8390/8490
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
Rate (K) value Rate (K) value Rate (K) value Rate (K) value
Error Error Error Error
(decimal) (decimal) (decimal) (decimal)
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
SYNC = 0, BRGH = 0, BRG16 = 0

BAUD FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
(K) Actual SPBRG Actual SPBRG Actual SPBRG
% % %
Rate (K) value Rate (K) value Rate (K) value
Error Error Error
(decimal) (decimal) (decimal)
0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51
1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12
2.4 2.404 0.16 25 2.403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
% % % %
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
RATE
% % %
Error Error Error
0.3 — — — — — — 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —

PIC18F6390/6490/8390/8490
TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
% % % %
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
SYNC = 0, BRGH = 0, BRG16 = 1

BAUD
RATE
% % %
Error Error Error
0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD
RATE
% % % %
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD
RATE
% % %
Error Error Error
0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832
1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207
2.4 2.404 0.16 415 2.403 -0.16 207 2403 -0.16 103
9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25
19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12
57.6 58.824 2.12 16 55.555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —

PIC18F6390/6490/8390/8490
16.1.3 AUTO-BAUD RATE DETECT Note 1: If the WUE bit is set with the ABDEN bit,
The Enhanced USART module supports the automatic Auto-Baud Rate Detection will occur on
detection and calibration of baud rate. This feature is the byte following the Break character.
active only in Asynchronous mode and while the WUE 2: It is up to the user to determine that the
bit is clear. incoming character baud rate is within the
The automatic baud rate measurement sequence range of the selected BRG clock source.
(Figure 16-1) begins whenever a Start bit is received Some combinations of oscillator frequency
and the ABDEN bit is set. The calculation is and EUSART baud rates are not possible
self-averaging. due to bit error rates. Overall system
timing and communication baud rates
In the Auto-Baud Rate Detect (ABD) mode, the clock to
must be taken into consideration when
the BRG is reversed. Rather than the BRG clocking the
using the Auto-Baud Rate Detection
incoming RX1 signal, the RX1 signal is timing the BRG.
feature.
In ABD mode, the internal Baud Rate Generator is
used as a counter to time the bit period of the incoming 3: When the auto-baud feature is enabled,
serial byte stream. the BRG16 bit (BAUDCON<3>) must be
set.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value, 55h (ASCII TABLE 16-4: BRG COUNTER CLOCK
“U”, which is also the LIN bus Sync character), in order RATES
to calculate the proper bit rate. The measurement is
taken over both a low and a high bit time in order to BRG16 BRGH BRG Counter Clock
minimize any effects caused by asymmetry of the 0 0 FOSC/512
incoming signal. After a Start bit, the SPBRG1 begins
0 1 FOSC/128
counting up, using the preselected clock source on the
first rising edge of RX1. After eight bits on the RX1 pin 1 0 FOSC/128
or the fifth rising edge, an accumulated value totalling 1 1 FOSC/32
the proper BRG period is left in the
SPBRGH1:SPBRG1 register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the 16.1.3.1 ABD and EUSART Transmission
ABDEN bit is automatically cleared. Since the BRG clock is reversed during ABD acquisi-
If a rollover of the BRG occurs (an overflow from FFFFh tion, the EUSART transmitter cannot be used during
to 0000h), the event is trapped by the ABDOVF status bit ABD. This means that whenever the ABDEN bit is set,
(BAUDCON1<7>). It is set in hardware by BRG rollovers TXREG1 cannot be written to. Users should also
and can be set or cleared by the user in software. ABD ensure that ABDEN does not become set during a
mode remains active after rollover events and the transmit sequence. Failing to do this may result in
ABDEN bit remains set (Figure 16-2). unpredictable EUSART operation.
While calibrating the baud rate period, the BRG regis-

ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. This allows the user to verify
that no carry occurred for 8-bit modes by checking for
00h in the SPBRGH1 register. Refer to Table 16-4 for
counter clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RC1IF interrupt is set
once the fifth rising edge on RX1 is detected. The value
in the RCREG1 needs to be read to clear the RC1IF
interrupt. The contents of RCREG1 should be
discarded.

PIC18F6390/6490/8390/8490
FIGURE 16-1: AUTOMATIC BAUD RATE CALCULATION
BRG Value XXXXh 0000h 001Ch
Edge #1 Edge #2 Edge #3 Edge #4 Edge #5

RX1 pin Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop Bit
BRG Clock
Set by User Auto-Cleared

ABDEN bit
RC1IF bit
(Interrupt)
Read
RCREG1
SPBRG1 XXXXh 1Ch
SPBRGH1 XXXXh 00h
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 16-2: BRG OVERFLOW SEQUENCE
BRG Clock
ABDEN bit
RX1 pin Start Bit 0
ABDOVF bit
FFFFh
BRG Value XXXXh 0000h 0000h

PIC18F6390/6490/8390/8490
16.2 EUSART Asynchronous Mode Once the TXREG1 register transfers the data to the
TSR register (occurs in one TCY), the TXREG1 register
The Asynchronous mode of operation is selected by is empty and the TX1IF flag bit (PIR1<4>) is set. This
clearing the SYNC bit (TXSTA1<4>). In this mode, the interrupt can be enabled or disabled by setting or clear-
EUSART uses standard Non-Return-to-Zero (NRZ) for- ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF
mat (one Start bit, eight or nine data bits and one Stop will be set regardless of the state of TX1IE; it cannot be
bit). The most common data format is 8 bits. An cleared in software. TX1IF is also not cleared immedi-
on-chip, dedicated 8-bit/16-bit Baud Rate Generator ately upon loading TXREG1, but becomes valid in the
can be used to derive standard baud rate frequencies second instruction cycle following the load instruction.
from the oscillator. Polling TX1IF immediately following a load of TXREG1
The EUSART transmits and receives the LSb first. The will return invalid results.
EUSART’s transmitter and receiver are functionally While TX1IF indicates the status of the TXREG1 regis-
independent, but use the same data format and baud ter, another bit, TRMT (TXSTA1<1>), shows the status
rate. The Baud Rate Generator produces a clock, either of the TSR register. TRMT is a read-only bit which is set
x16 or x64 of the bit shift rate, depending on the BRGH when the TSR register is empty. No interrupt logic is
and BRG16 bits (TXSTA1<2> and BAUDCON1<3>). tied to this bit so the user has to poll this bit in order to
Parity is not supported by the hardware but can be determine if the TSR register is empty.
implemented in software and stored as the 9th data bit.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the EUSART
memory so it is not available to the user.
module consists of the following important elements:
2: Flag bit, TX1IF, is set when enable bit
• Baud Rate Generator
TXEN is set.
• Sampling Circuit
To set up an Asynchronous Transmission:
• Asynchronous Transmitter
• Asynchronous Receiver 1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
• Auto-Wake-up on Sync Break Character
BRGH and BRG16 bits, as required, to achieve
• 12-Bit Break Character Transmit the desired baud rate.
• Auto-Baud Rate Detection 2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
16.2.1 EUSART ASYNCHRONOUS
3. If interrupts are desired, set enable bit, TX1IE.
TRANSMITTER
4. If 9-bit transmission is desired, set transmit bit,
The EUSART transmitter block diagram is shown in TX9; can be used as address/data bit.
Figure 16-3. The heart of the transmitter is the Transmit 5. Enable the transmission by setting bit, TXEN,
(Serial) Shift Register (TSR). The Shift register obtains
which will also set bit, TX1IF.
its data from the Read/Write Transmit Buffer register,
TXREG1. The TXREG1 register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit
software. The TSR register is not loaded until the Stop should be loaded in bit, TX9D.
bit has been transmitted from the previous load. As 7. Load data to the TXREG1 register (starts
soon as the Stop bit is transmitted, the TSR is loaded transmission).
with new data from the TXREG1 register (if available). 8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-3: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TX1IF TXREG1 Register

TX1IE
8
MSb LSb
(8) • • • 0 Pin Buffer
and Control
TSR Register TX1 pin
Interrupt
TXEN Baud Rate CLK
TRMT SPEN
BRG16 SPBRGH1 SPBRG1
TX9
Baud Rate Generator TX9D

PIC18F6390/6490/8390/8490
FIGURE 16-4: ASYNCHRONOUS TRANSMISSION
Write to TXREG1
Word 1
BRG Output
(Shift Clock)
TX1 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TX1IF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
FIGURE 16-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG1
Word 1 Word 2
BRG Output
(Shift Clock)
TX1 (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TX1IF bit 1 TCY Word 1 Word 2

(Interrupt Reg. Flag)
1 TCY
Word 1 Word 2
TRMT bit Transmit Shift Reg. Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 16-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Reset
on Page
TXREG1 EUSART1 Transmit Register 61
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

PIC18F6390/6490/8390/8490
16.2.2 EUSART ASYNCHRONOUS 16.2.3 SETTING UP 9-BIT MODE WITH
RECEIVER ADDRESS DETECT
The receiver block diagram is shown in Figure 16-6. This mode would typically be used in RS-485 systems.
The data is received on the RX1 pin and drives the data To set up an Asynchronous Reception with Address
recovery block. The data recovery block is actually a Detect Enable:
high-speed shifter operating at x16 times the baud rate, 1. Initialize the SPBRGH1:SPBRG1 registers for
whereas the main receive serial shifter operates at the the appropriate baud rate. Set or clear the
bit rate or at FOSC. This mode would typically be used BRGH and BRG16 bits, as required, to achieve
in RS-232 systems. the desired baud rate.
To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing
1. Initialize the SPBRGH1:SPBRG1 registers for the SYNC bit and setting the SPEN bit.
the appropriate baud rate. Set or clear the 3. If interrupts are required, set the RCEN bit and
BRGH and BRG16 bits, as required, to achieve select the desired priority level with the RC1IP
the desired baud rate. bit.
2. Enable the asynchronous serial port by clearing 4. Set the RX9 bit to enable 9-bit reception.
bit, SYNC, and setting bit, SPEN. 5. Set the ADDEN bit to enable address detect.
3. If interrupts are desired, set enable bit, RC1IE. 6. Enable reception by setting the CREN bit.
4. If 9-bit reception is desired, set bit, RX9. 7. The RC1IF bit will be set when reception is
5. Enable the reception by setting bit, CREN. complete. The interrupt will be Acknowledged if
6. Flag bit, RC1IF, will be set when reception is the RC1IE and GIE bits are set.
complete and an interrupt will be generated if 8. Read the RCSTA1 register to determine if any
enable bit, RC1IE, was set. error occurred during reception, as well as read
7. Read the RCSTA1 register to get the 9th bit (if bit 9 of data (if applicable).
enabled) and determine if any error occurred 9. Read RCREG1 to determine if the device is
during reception. being addressed.
8. Read the 8-bit received data by reading the 10. If any error occurred, clear the CREN bit.
RCREG1 register. 11. If the device has been addressed, clear the
9. If any error occurred, clear the error by clearing ADDEN bit to allow all received data into the
enable bit, CREN. receive buffer and interrupt the CPU.
10. If using interrupts, ensure that the GIE and PEIE
set.
FIGURE 16-6: EUSART RECEIVE BLOCK DIAGRAM
CREN OERR FERR
x64 Baud Rate CLK

÷ 64 MSb RSR Register LSb
BRG16 SPBRGH1 SPBRG1 or
÷ 16
or Stop (8) 7 • • • 1 0 Start
Baud Rate Generator ÷4
RX9
Pin Buffer Data

and Control Recovery
RX1 RX9D RCREG1 Register
FIFO
SPEN
8
Interrupt RC1IF Data Bus

RC1IE

PIC18F6390/6490/8390/8490
FIGURE 16-7: ASYNCHRONOUS RECEPTION
Start Start Start
RX1 (pin) bit bit
bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit 7/8 Stop
bit bit bit
Rcv Shift Reg
Rcv Buffer Reg
Word 1 Word 2
RCREG1 RCREG1 RCREG1
Read Rcv
Buffer Reg
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Reset
on Page
RCREG1 EUSART1 Receive Register 61
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

PIC18F6390/6490/8390/8490
16.2.4 AUTO-WAKE-UP ON SYNC BREAK End-Of-Character (EOC) and cause data or framing
CHARACTER errors. Therefore, to work properly, the initial character
in the transmission must be all ‘0’s. This can be 00h
During Sleep mode, all clocks to the EUSART are (8 bytes) for standard RS-232 devices, or 000h
suspended. Because of this, the Baud Rate Generator (12 bits) for LIN bus.
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller Oscillator start-up time must also be considered,
to wake-up, due to activity on the RX1/DT1 line, while especially in applications using oscillators with longer
the EUSART is operating in Asynchronous mode. start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
The auto-wake-up feature is enabled by setting the sufficient length and be followed by a sufficient interval
WUE bit (BAUDCON<1>). Once set, the typical receive to allow enough time for the selected oscillator to start
sequence on RX1/DT1 is disabled and the EUSART and provide proper initialization of the EUSART.
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event 16.2.4.2 Special Considerations Using
consists of a high-to-low transition on the RX1/DT1 the WUE Bit
line. (This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.) The timing of WUE and RC1IF events may cause some
confusion when it comes to determining the validity of
Following a wake-up event, the module generates an
received data. As noted, setting the WUE bit places the
RC1IF interrupt. The interrupt is generated synchro-
EUSART in an Idle mode. The wake-up event causes
nously to the Q clocks in normal operating modes
a receive interrupt by setting the RC1IF bit. The WUE
(Figure 16-8) and asynchronously, if the device is in
bit is cleared after this when a rising edge is seen on
Sleep mode (Figure 16-9). The interrupt condition is
RX1/DT1. The interrupt condition is then cleared by
cleared by reading the RCREG1 register.
reading the RCREG1 register. Ordinarily, the data in
The WUE bit is automatically cleared once a low-to-high RCREG1 will be dummy data and should be discarded.
transition is observed on the RX1 line following the
The fact that the WUE bit has been cleared (or is still
wake-up event. At this point, the EUSART module is in
set), and the RC1IF flag is set, should not be used as
Idle mode and returns to normal operation. This signals
an indicator of the integrity of the data in RCREG1.
to the user that the Sync Break event is over.
Users should consider implementing a parallel method
in firmware to verify received data integrity.
16.2.4.1 Special Considerations Using
Auto-Wake-up To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
Since auto-wake-up functions by sensing rising edge a receive operation is not occurring, the WUE bit may
transitions on RX1/DT1, information with any state then be set just prior to entering the Sleep mode.
changes before the Stop bit may signal a false
FIGURE 16-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto-Cleared
WUE bit
RX1/DT1 Line
RC1IF
Cleared due to user read of RCREG1
Note: The EUSART remains in Idle while the WUE bit is set.
FIGURE 16-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto-Cleared
WUE bit
RX1/DT1 Line Note 1

RC1IF
SLEEP Command Executed Sleep Ends Cleared due to user read of RCREG1
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

PIC18F6390/6490/8390/8490
16.2.5 BREAK CHARACTER SEQUENCE 3. Load the TXREG1 with a dummy character to
initiate transmission (the value is ignored).
The Enhanced USART module has the capability of
sending the special Break character sequences that are 4. Write ‘55h’ to TXREG1 to load the Sync
required by the LIN bus standard. The Break character character into the transmit FIFO buffer.
transmit consists of a Start bit, followed by twelve ‘0’ bits 5. After the Break has been sent, the SENDB bit is
and a Stop bit. The Frame Break character is sent reset by hardware. The Sync character now
whenever the SENDB and TXEN bits (TXSTA<3> and transmits in the preconfigured mode.
TXSTA<5>) are set while the Transmit Shift Register is When the TXREG1 becomes empty, as indicated by the
loaded with data. Note that the value of data written to TX1IF, the next data byte can be written to TXREG1.
TXREG1 will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after 16.2.6 RECEIVING A BREAK CHARACTER
the corresponding Stop bit is sent. This allows the user The Enhanced USART module can receive a Break
to preload the transmit FIFO with the next transmit byte character in two ways.
following the Break character (typically, the Sync
The first method forces configuration of the baud rate
character in the LIN specification).
at a frequency of 9/13 the typical speed. This allows for
Note that the data value written to the TXREG1 for the the Stop bit transition to be at the correct sampling
Break character is ignored. The write simply serves the location (13 bits for Break versus Start bit and 8 data
purpose of initiating the proper sequence. bits for typical data).
The TRMT bit indicates when the transmit operation is The second method uses the auto-wake-up feature
active or Idle, just as it does during normal transmis- described in Section 16.2.4 “Auto-Wake-up on Sync
sion. See Figure 16-10 for the timing of the Break Break Character”. By enabling this feature, the
character sequence. EUSART will sample the next two transitions on
RX1/DT1, cause an RC1IF interrupt and receive the
16.2.5.1 Break and Sync Transmit Sequence next data byte followed by another interrupt.
The following sequence will send a message frame Note that following a Break character, the user will
header made up of a Break, followed by an Auto-Baud typically want to enable the Auto-Baud Rate Detect
Sync byte. This sequence is typical of a LIN bus master. feature. For both methods, the user can set the ABD bit
1. Configure the EUSART for the desired mode. once the TX1IF interrupt is observed.
2. Set the TXEN and SENDB bits to set up the
Break character.
FIGURE 16-10: SEND BREAK CHARACTER SEQUENCE
Write to TXREG1
Dummy Write
BRG Output
(Shift Clock)
TX1 (pin) Start bit bit 0 bit 1 bit 11 Stop bit
Break
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
SENDB
(Transmit Shift
Reg. Empty Flag)

PIC18F6390/6490/8390/8490
16.3 EUSART Synchronous Once the TXREG1 register transfers the data to the
Master Mode TSR register (occurs in one TCYCLE), the TXREG1 is
empty and the TX1IF flag bit (PIR1<4>) is set. The
The Synchronous Master mode is entered by setting interrupt can be enabled or disabled by setting or clear-
the CSRC bit (TXSTA<7>). In this mode, the data is ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is
transmitted in a half-duplex manner (i.e., transmission set regardless of the state of enable bit, TX1IE; it
and reception do not occur at the same time). When cannot be cleared in software. It will reset only when
transmitting data, the reception is inhibited and vice new data is loaded into the TXREG1 register.
versa. Synchronous mode is entered by setting bit,
While flag bit, TX1IF, indicates the status of the TXREG1
SYNC (TXSTA<4>). In addition, enable bit, SPEN
register, another bit, TRMT (TXSTA<1>), shows the
(RCSTA1<7>), is set in order to configure the TX1 and
status of the TSR register. TRMT is a read-only bit which
RX1 pins to CK1 (clock) and DT1 (data) lines,
is set when the TSR is empty. No interrupt logic is tied to
respectively.
this bit so the user has to poll this bit in order to deter-
The Master mode indicates that the processor trans- mine if the TSR register is empty. The TSR is not
mits the master clock on the CK1 line. Clock polarity is mapped in data memory so it is not available to the user.
selected with the SCKP bit (BAUDCON<4>); setting
To set up a Synchronous Master Transmission:
SCKP sets the Idle state on CK1 as high, while clearing
the bit sets the Idle state as low. This option is provided 1. Initialize the SPBRGH1:SPBRG1 registers for
to support Microwire devices with this module. the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
16.3.1 EUSART SYNCHRONOUS MASTER baud rate.
TRANSMISSION 2. Enable the synchronous master serial port by
The EUSART transmitter block diagram is shown in setting bits, SYNC, SPEN and CSRC.
Figure 16-3. The heart of the transmitter is the Transmit 3. If interrupts are desired, set enable bit, TX1IE.
(Serial) Shift Register (TSR). The Shift register obtains 4. If 9-bit transmission is desired, set bit, TX9.
its data from the Read/Write Transmit Buffer register, 5. Enable the transmission by setting bit, TXEN.
TXREG1. The TXREG1 register is loaded with data in 6. If 9-bit transmission is selected, the ninth bit
software. The TSR register is not loaded until the last should be loaded in bit, TX9D.
bit has been transmitted from the previous load. As
7. Start transmission by loading data to the
soon as the last bit is transmitted, the TSR is loaded
TXREG1 register.
with new data from the TXREG1 (if available).
set.
FIGURE 16-11: SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
TXREG1 Reg
Write Word 1 Write Word 2
TX1IF bit
(Interrupt Flag)
TRMT bit
TXEN bit ‘1’ ‘1’
Note: Sync Master mode, SPBRG1 = 0, continuous transmission of two 8-bit words.

PIC18F6390/6490/8390/8490
FIGURE 16-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7
RC6/TX1/CK1 pin
Write to
TXREG1 Reg
TX1IF bit
TRMT bit
TXEN bit
TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

PIC18F6390/6490/8390/8490
16.3.2 EUSART SYNCHRONOUS 3. Ensure bits, CREN and SREN, are clear.
MASTER RECEPTION 4. If interrupts are desired, set enable bit, RC1IE.
Once Synchronous mode is selected, reception is 5. If 9-bit reception is desired, set bit, RX9.
enabled by setting either the Single Receive Enable bit, 6. If a single reception is required, set bit, SREN.
SREN (RCSTA1<5>), or the Continuous Receive For continuous reception, set bit, CREN.
Enable bit, CREN (RCSTA1<4>). Data is sampled on 7. Interrupt flag bit, RC1IF, will be set when recep-
the RX1 pin on the falling edge of the clock. tion is complete and an interrupt will be generated
If enable bit, SREN, is set, only a single word is if the enable bit, RC1IE, was set.
received. If enable bit, CREN, is set, the reception is 8. Read the RCSTA1 register to get the 9th bit (if
continuous until CREN is cleared. If both bits are set, enabled) and determine if any error occurred
then CREN takes precedence. during reception.
To set up a Synchronous Master Reception: 9. Read the 8-bit received data by reading the
RCREG1 register.
1. Initialize the SPBRGH1:SPBRG1 registers for the
10. If any error occurred, clear the error by clearing
appropriate baud rate. Set or clear the BRG16 bit,
bit, CREN.
as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
set.
FIGURE 16-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
SREN bit
SREN bit
CREN bit ‘0’ ‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with SREN bit = 1 and BRGH bit = 0.
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

PIC18F6390/6490/8390/8490
16.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission:
Synchronous Slave mode is entered by clearing bit, 1. Enable the synchronous slave serial port by
CSRC (TXSTA1<7>). This mode differs from the setting bits, SYNC and SPEN, and clearing bit,
Synchronous Master mode in that the shift clock is CSRC.
supplied externally at the CK1 pin (instead of being 2. Clear bits, CREN and SREN.
supplied internally in Master mode). This allows the 3. If interrupts are desired, set enable bit, TX1IE.
device to transfer or receive data while in any 4. If 9-bit transmission is desired, set bit, TX9.
low-power mode. 5. Enable the transmission by setting enable bit,
TXEN.
16.4.1 EUSART SYNCHRONOUS SLAVE
6. If 9-bit transmission is selected, the ninth bit
TRANSMIT
should be loaded in bit, TX9D.
The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the
modes are identical except in the case of the Sleep TXREG1 register.
mode.
If two words are written to the TXREG1, and then the bits in the INTCON register (INTCON<7:6>) are
SLEEP instruction is executed, the following will occur: set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG1
register.
c) Flag bit, TX1IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
e) If enable bit, TX1IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC18F6390/6490/8390/8490
16.4.2 EUSART SYNCHRONOUS SLAVE To set up a Synchronous Slave Reception:
RECEPTION 1. Enable the synchronous master serial port by
The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit,
modes is identical except in the case of Sleep or any CSRC.
Idle mode and bit, SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RC1IE.
Slave mode. 3. If 9-bit reception is desired, set bit, RX9.
If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN.
entering Sleep or any Idle mode, then a word may be 5. Flag bit, RC1IF, will be set when reception is
received while in this low-power mode. Once the word complete. An interrupt will be generated if
is received, the RSR register will transfer the data to the enable bit, RC1IE, was set.
RCREG1 register. If the RC1IE enable bit is set, the 6. Read the RCSTA1 register to get the 9th bit (if
interrupt generated will wake the chip from the enabled) and determine if any error occurred
low-power mode. If the global interrupt is enabled, the during reception.
program will branch to the interrupt vector.
7. Read the 8-bit received data by reading the
RCREG1 register.
bit, CREN.
set.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

PIC18F6390/6490/8390/8490
17.0 ADDRESSABLE UNIVERSAL The pins of the AUSART module are multiplexed with
the functions of PORTG (RG1/TX2/CK2/SEG29 and
SYNCHRONOUS
RG2/RX2/DT2/SEG28, respectively). In order to
ASYNCHRONOUS RECEIVER configure these pins as an AUSART:
TRANSMITTER (AUSART) • SPEN bit (RCSTA2<7>) must be set (= 1)
The Addressable Universal Synchronous Asynchro- • TRISG<2> bit must be set (= 1)
nous Receiver Transmitter (AUSART) module is very • TRISG<1> bit must be cleared (= 0) for
similar in function to the Enhanced USART module, Asynchronous and Synchronous Master modes
discussed in the previous chapter. It is provided as an • TRISG<1> bit must be set (= 1) for Synchronous
additional channel for serial communication, with Slave mode
external devices, for those situations that do not require
Auto-Baud Detection or LIN bus support. Note: The AUSART control will automatically
reconfigure the pin from input to output as
The AUSART can be configured in the following modes: needed.
• Asynchronous (full-duplex) The operation of the Addressable USART module is
• Synchronous – Master (half-duplex) controlled through two registers, TXSTA2 and
• Synchronous – Slave (half-duplex) RXSTA2. These are detailed in Register 17-1 and
Register 17-2 respectively.

PIC18F6390/6490/8390/8490
REGISTER 17-1: TXSTA2: AUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D
bit 7 bit 0
Legend:
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: AUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC18F6390/6490/8390/8490
REGISTER 17-2: RCSTA2: AUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX2/DT2 and TX2/CK2 pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG2 register and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit, CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC18F6390/6490/8390/8490
17.1 AUSART Baud Rate Generator geous to use the high baud rate (BRGH = 1) to reduce
(BRG) the baud rate error, or achieve a slow baud rate for a
fast oscillator frequency.
The BRG is a dedicated 8-bit generator that supports Writing a new value to the SPBRG2 register causes the
both the Asynchronous and Synchronous modes of the BRG timer to be reset (or cleared). This ensures the
AUSART. BRG does not wait for a timer overflow before outputting
The SPBRG2 register controls the period of a the new baud rate.
free-running timer. In Asynchronous mode, bit BRGH
(TXSTA<2>) also controls the baud rate. In Synchro- 17.1.1 OPERATION IN POWER-MANAGED
nous mode, BRGH is ignored. Table 17-1 shows the MODES
formula for computation of the baud rate for different
The device clock is used to generate the desired baud
AUSART modes, which only apply in Master mode
rate. When one of the power-managed modes is
(internally generated clock).
entered, the new clock source may be operating at a
Given the desired baud rate and FOSC, the nearest different frequency. This may require an adjustment to
integer value for the SPBRG2 register can be calcu- the value in the SPBRG2 register.
lated using the formulas in Table 17-1. From this, the
error in baud rate can be determined. An example 17.1.2 SAMPLING
calculation is shown in Example 17-1. Typical baud
The data on the RX2 pin is sampled three times by a
rates and error values for the various Asynchronous
majority detect circuit to determine if a high or a low
modes are shown in Table 17-3. It may be advanta- level is present at the RX2 pin.
TABLE 17-1: BAUD RATE FORMULAS

Configuration Bits
BRG/AUSART Mode Baud Rate Formula
SYNC BRGH
0 0 Asynchronous FOSC/[64 (n + 1)]
0 1 Asynchronous FOSC/[16 (n + 1)]
1 x Synchronous FOSC/[4 (n + 1)]
Legend: x = Don’t care, n = Value of SPBRG2 register
EXAMPLE 17-1: CALCULATING BAUD RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
Desired Baud Rate = FOSC/(64 ([SPBRG2] + 1))
Solving for SPBRG2:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
TABLE 17-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

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Page
TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 63
SPBRG2 AUSART2 Baud Rate Generator Register 63
Legend: Shaded cells are not used by the BRG.

PIC18F6390/6490/8390/8490
TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES
BRGH = 0
BAUD Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG
% % % %
RATE Rate (K) value Rate (K) value Rate (K) value Rate (K) value
(K) (decimal) (decimal) (decimal) (decimal)
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
BRGH = 0
BAUD Actual SPBRG Actual SPBRG Actual SPBRG
% % %
RATE Rate (K) value Rate (K) value Rate (K) value
Error Error Error
(K) (decimal) (decimal) (decimal)
0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51
1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12
2.4 2.404 0.16 25 2.403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
BRGH = 1
BAUD FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
RATE
% % % %
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BRGH = 1
BAUD
RATE
% % %
Error Error Error
0.3 — — — — — — 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —

PIC18F6390/6490/8390/8490
17.2 AUSART Asynchronous Mode Once the TXREG2 register transfers the data to the
TSR register (occurs in one TCY), the TXREG2 register
The Asynchronous mode of operation is selected by is empty and the TX2IF flag bit (PIR3<4>) is set. This
clearing the SYNC bit (TXSTA2<4>). In this mode, the interrupt can be enabled or disabled by setting or
AUSART uses standard Non-Return-to-Zero (NRZ) clearing the interrupt enable bit, TX2IE (PIE3<4>).
format (one Start bit, eight or nine data bits and one TX2IF will be set regardless of the state of TX2IE; it
Stop bit). The most common data format is 8 bits. An cannot be cleared in software. TX2IF is also not
on-chip, dedicated 8-bit Baud Rate Generator can be cleared immediately upon loading TXREG2, but
used to derive standard baud rate frequencies from the becomes valid in the second instruction cycle following
oscillator. the load instruction. Polling TX2IF immediately
The AUSART transmits and receives the LSb first. The following a load of TXREG2 will return invalid results.
AUSART’s transmitter and receiver are functionally While TX2IF indicates the status of the TXREG2
independent but use the same data format and baud register, another bit, TRMT (TXSTA2<1>), shows the
rate. The Baud Rate Generator produces a clock, status of the TSR register. TRMT is a read-only bit
either x16 or x64 of the bit shift rate, depending on the which is set when the TSR register is empty. No inter-
BRGH bit (TXSTA2<2>). Parity is not supported by the rupt logic is tied to this bit, so the user has to poll this
hardware but can be implemented in software and bit in order to determine if the TSR register is empty.
stored as the 9th data bit.
Note 1: The TSR register is not mapped in data
When operating in Asynchronous mode, the AUSART
memory, so it is not available to the user.
module consists of the following important elements:
2: Flag bit, TX2IF, is set when enable bit,
• Baud Rate Generator
TXEN is set.
• Sampling Circuit
• Asynchronous Transmitter To set up an Asynchronous Transmission:
• Asynchronous Receiver 1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
17.2.1 AUSART ASYNCHRONOUS to achieve the desired baud rate.
TRANSMITTER 2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
The AUSART transmitter block diagram is shown in
Figure 17-1. The heart of the transmitter is the Transmit 3. If interrupts are desired, set enable bit, TX2IE.
(Serial) Shift Register (TSR). The Shift register obtains 4. If 9-bit transmission is desired, set transmit bit,
its data from the Read/Write Transmit Buffer register, TX9. Can be used as address/data bit.
TXREG2. The TXREG2 register is loaded with data in 5. Enable the transmission by setting bit, TXEN,
software. The TSR register is not loaded until the Stop which will also set bit, TX2IF.
bit has been transmitted from the previous load. As 6. If 9-bit transmission is selected, the ninth bit
soon as the Stop bit is transmitted, the TSR is loaded should be loaded in bit, TX9D.
with new data from the TXREG2 register (if available).
7. Load data to the TXREG2 register (starts
transmission).
set.
FIGURE 17-1: AUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TX2IF TXREG2 Register

TX2IE
8
MSb LSb
(8) 0 Pin Buffer
• • •
and Control
TSR Register TX2 pin
Interrupt
TXEN Baud Rate CLK
TRMT SPEN
SPBRG2
TX9
Baud Rate Generator
TX9D

PIC18F6390/6490/8390/8490
FIGURE 17-2: ASYNCHRONOUS TRANSMISSION
Write to TXREG2
Word 1
BRG Output
(Shift Clock)
TX2 (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TX2IF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit
Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
FIGURE 17-3: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG2
Word 1 Word 2
BRG Output
(Shift Clock)
TX2 (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TX2IF bit 1 TCY Word 1 Word 2

(Interrupt Reg. Flag)
1 TCY
Word 1 Word 2
TRMT bit Transmit Shift Reg. Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 17-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Reset
on Page
PIR3 — LCDIF RC2IF TX2IF — — — — 61
PIE3 — LCDIE RC2IE TX2IE — — — — 61
IPR3 — LCDIP RC2IP TX2IP — — — — 61
TXREG2 AUSART2 Transmit Register 63
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

PIC18F6390/6490/8390/8490
17.2.2 AUSART ASYNCHRONOUS 17.2.3 SETTING UP 9-BIT MODE WITH
RECEIVER ADDRESS DETECT
The receiver block diagram is shown in Figure 17-4. This mode would typically be used in RS-485 systems.
The data is received on the RX2 pin and drives the data To set up an Asynchronous Reception with Address
recovery block. The data recovery block is actually a Detect Enable:
high-speed shifter, operating at x16 times the baud 1. Initialize the SPBRG2 register for the appropriate
rate, whereas the main receive serial shifter operates baud rate. Set or clear the BRGH and BRG16
at the bit rate or at FOSC. This mode would typically be bits, as required, to achieve the desired baud
used in RS-232 systems. rate.
To set up an Asynchronous Reception: 2. Enable the asynchronous serial port by clearing
1. Initialize the SPBRG2 register for the appropriate the SYNC bit and setting the SPEN bit.
baud rate. Set or clear the BRGH bit, as required, 3. If interrupts are required, set the RCEN bit and
to achieve the desired baud rate. select the desired priority level with the RC2IP
2. Enable the asynchronous serial port by clearing bit.
bit, SYNC, and setting bit, SPEN. 4. Set the RX9 bit to enable 9-bit reception.
3. If interrupts are desired, set enable bit, RC2IE. 5. Set the ADDEN bit to enable address detect.
4. If 9-bit reception is desired, set bit, RX9. 6. Enable reception by setting the CREN bit.
5. Enable the reception by setting bit, CREN. 7. The RC2IF bit will be set when reception is
6. Flag bit, RC2IF, will be set when reception is complete. The interrupt will be Acknowledged if
complete and an interrupt will be generated if the RC2IE and GIE bits are set.
enable bit, RC2IE, was set. 8. Read the RCSTA2 register to determine if any
7. Read the RCSTA2 register to get the 9th bit (if error occurred during reception, as well as read
enabled) and determine if any error occurred bit 9 of data (if applicable).
during reception. 9. Read RCREG2 to determine if the device is
8. Read the 8-bit received data by reading the being addressed.
RCREG2 register. 10. If any error occurred, clear the CREN bit.
9. If any error occurred, clear the error by clearing 11. If the device has been addressed, clear the
enable bit, CREN. ADDEN bit to allow all received data into the
10. If using interrupts, ensure that the GIE and PEIE receive buffer and interrupt the CPU.
set.
FIGURE 17-4: AUSART RECEIVE BLOCK DIAGRAM
CREN OERR FERR
x64 Baud Rate CLK

÷ 64 MSb RSR Register LSb
SPBRG2 or
÷ 16
or Stop (8) 7 • • • 1 0 Start
Baud Rate Generator ÷4
RX9
Pin Buffer Data

and Control Recovery
RX2 RX9D RCREG2 Register
FIFO
SPEN
8
Interrupt RC2IF Data Bus

RC2IE

PIC18F6390/6490/8390/8490
FIGURE 17-5: ASYNCHRONOUS RECEPTION
Start Start Start
RX2 (pin) bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift Reg
Rcv Buffer Reg
Word 1 Word 2
RCREG2 RCREG2
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third
word causing the OERR (Overrun) bit to be set.
TABLE 17-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Reset
on Page
RCREG2 AUSART2 Receive Register 63
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

PIC18F6390/6490/8390/8490
17.3 AUSART Synchronous Once the TXREG2 register transfers the data to the
Master Mode TSR register (occurs in one TCYCLE), the TXREG2 is
empty and the TX2IF flag bit (PIR3<4>) is set. The
The Synchronous Master mode is entered by setting interrupt can be enabled or disabled by setting or clear-
the CSRC bit (TXSTA2<7>). In this mode, the data is ing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is
transmitted in a half-duplex manner (i.e., transmission set regardless of the state of enable bit, TX2IE; it
and reception do not occur at the same time). When cannot be cleared in software. It will reset only when
transmitting data, the reception is inhibited and vice new data is loaded into the TXREG2 register.
versa. Synchronous mode is entered by setting bit,
While flag bit, TX2IF, indicates the status of the TXREG2
SYNC (TXSTA2<4>). In addition, enable bit, SPEN
register, another bit, TRMT (TXSTA2<1>), shows the
(RCSTA2<7>), is set in order to configure the TX2 and
status of the TSR register. TRMT is a read-only bit which
RX2 pins to CK2 (clock) and DT2 (data) lines,
is set when the TSR is empty. No interrupt logic is tied to
respectively.
this bit so the user has to poll this bit in order to deter-
The Master mode indicates that the processor transmits mine if the TSR register is empty. The TSR is not
the master clock on the CK2 line. mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
17.3.1 AUSART SYNCHRONOUS MASTER
TRANSMISSION 1. Initialize the SPBRG2 register for the appropriate
baud rate.
The AUSART transmitter block diagram is shown in
Figure 17-1. The heart of the transmitter is the Transmit 2. Enable the synchronous master serial port by
(Serial) Shift Register (TSR). The Shift register obtains setting bits, SYNC, SPEN and CSRC.
its data from the Read/Write Transmit Buffer register, 3. If interrupts are desired, set enable bit, TX2IE.
TXREG2. The TXREG2 register is loaded with data in 4. If 9-bit transmission is desired, set bit, TX9.
software. The TSR register is not loaded until the last 5. Enable the transmission by setting bit, TXEN.
bit has been transmitted from the previous load. As 6. If 9-bit transmission is selected, the ninth bit
soon as the last bit is transmitted, the TSR is loaded should be loaded in bit, TX9D.
with new data from the TXREG2 (if available).
7. Start transmission by loading data to the
TXREG2 register.
set.
FIGURE 17-6: SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RX2/DT2 pin
bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TX2/CK2 pin
Write to
TXREG2 Reg
Write Word 1 Write Word 2
TX2IF bit
(Interrupt Flag)
TRMT bit
TXEN bit ‘1’ ‘1’
Note: Sync Master mode, SPBRG2 = 0, continuous transmission of two 8-bit words.

PIC18F6390/6490/8390/8490
FIGURE 17-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX2/DT2 pin bit 0 bit 1 bit 2 bit 6 bit 7
TX2/CK2 pin
Write to
TXREG2 Reg
TX2IF bit
TRMT bit
TXEN bit
TABLE 17-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

PIC18F6390/6490/8390/8490
17.3.2 AUSART SYNCHRONOUS 4. If interrupts are desired, set enable bit, RC2IE.
MASTER RECEPTION 5. If 9-bit reception is desired, set bit, RX9.
Once Synchronous mode is selected, reception is 6. If a single reception is required, set bit, SREN.
enabled by setting either the Single Receive Enable bit, For continuous reception, set bit, CREN.
SREN (RCSTA2<5>), or the Continuous Receive 7. Interrupt flag bit, RC2IF, will be set when recep-
Enable bit, CREN (RCSTA2<4>). Data is sampled on tion is complete and an interrupt will be generated
the RX2 pin on the falling edge of the clock. if the enable bit, RC2IE, was set.
If enable bit, SREN, is set, only a single word is 8. Read the RCSTA2 register to get the 9th bit (if
received. If enable bit, CREN, is set, the reception is enabled) and determine if any error occurred
continuous until CREN is cleared. If both bits are set, during reception.
then CREN takes precedence. 9. Read the 8-bit received data by reading the
RCREG2 register.
To set up a Synchronous Master Reception:
1. Initialize the SPBRG2 register for the appropriate bit, CREN.
baud rate.
2. Enable the synchronous master serial port by bits in the INTCON register (INTCON<7:6>) are
setting bits, SYNC, SPEN and CSRC. set.
3. Ensure bits, CREN and SREN, are clear.
FIGURE 17-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RX2/DT2 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX2/CK2 pin
Write to
SREN bit
SREN bit
CREN bit ‘0’ ‘0’
RC2IF bit
(Interrupt)
Read
RCREG2
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

PIC18F6390/6490/8390/8490
17.4 AUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission:
Synchronous Slave mode is entered by clearing bit, 1. Enable the synchronous slave serial port by
CSRC (TXSTA2<7>). This mode differs from the setting bits, SYNC and SPEN, and clearing bit,
Synchronous Master mode in that the shift clock is CSRC.
supplied externally at the CK2 pin (instead of being 2. Clear bits, CREN and SREN.
supplied internally in Master mode). This allows the 3. If interrupts are desired, set enable bit, TX2IE.
device to transfer or receive data while in any 4. If 9-bit transmission is desired, set bit, TX9.
low-power mode. 5. Enable the transmission by setting enable bit,
TXEN.
17.4.1 AUSART SYNCHRONOUS
6. If 9-bit transmission is selected, the ninth bit
SLAVE TRANSMIT
should be loaded in bit, TX9D.
The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the
modes are identical except in the case of the Sleep TXREG2 register.
mode.
If two words are written to the TXREG2 and then the bits in the INTCON register (INTCON<7:6>) are
SLEEP instruction is executed, the following will occur: set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG2
register.
c) Flag bit, TX2IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG2 register will transfer the second
word to the TSR and flag bit, TX2IF, will now be
set.
e) If enable bit, TX2IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC18F6390/6490/8390/8490
17.4.2 AUSART SYNCHRONOUS To set up a Synchronous Slave Reception:
SLAVE RECEPTION 1. Enable the synchronous master serial port by
The operation of the Synchronous Master and Slave setting bits, SYNC and SPEN, and clearing bit,
modes is identical except in the case of Sleep, or any CSRC.
Idle mode and bit SREN, which is a “don’t care” in 2. If interrupts are desired, set enable bit, RC2IE.
Slave mode. 3. If 9-bit reception is desired, set bit, RX9.
If receive is enabled by setting the CREN bit prior to 4. To enable reception, set enable bit, CREN.
entering Sleep, or any Idle mode, then a word may be 5. Flag bit, RC2IF, will be set when reception is
received while in this low-power mode. Once the word complete. An interrupt will be generated if
is received, the RSR register will transfer the data to the enable bit, RC2IE, was set.
RCREG2 register; if the RC2IE enable bit is set, the 6. Read the RCSTA2 register to get the 9th bit (if
interrupt generated will wake the chip from low-power enabled) and determine if any error occurred
mode. If the global interrupt is enabled, the program will during reception.
branch to the interrupt vector.
7. Read the 8-bit received data by reading the
RCREG2 register.
bit, CREN.
set.
TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Reset
on Page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

PIC18F6390/6490/8390/8490
18.0 10-BIT ANALOG-TO-DIGITAL The module has five registers:
CONVERTER (A/D) MODULE • A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
The Analog-to-Digital (A/D) converter module has
12 inputs for the PIC18F6X90/8X90 devices. This • A/D Control Register 0 (ADCON0)
module allows conversion of an analog input signal to • A/D Control Register 1 (ADCON1)
a corresponding 10-bit digital number. • A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 18-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 18-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 18-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 18-1: ADCON0: A/D CONTROL REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:

bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Unimplemented(1)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
Note 1: Performing a conversion on unimplemented channels will return a floating input measurement.

PIC18F6390/6490/8390/8490
U-0 U-0 R/W-0 R/W-0 R/W-q R/W-q R/W-q R/W-q
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:

bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = AVSS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = AVDD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
AN10
AN11
PCFG3:
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCFG0
0000 A A A A A A A A A A A A
0100 D A A A A A A A A A A A
0101 D D A A A A A A A A A A
0110 D D D A A A A A A A A A
0111 D D D D A A A A A A A A
1000 D D D D D A A A A A A A
1001 D D D D D D A A A A A A
1010 D D D D D D D A A A A A
1011 D D D D D D D D A A A A
1100 D D D D D D D D D A A A
1101 D D D D D D D D D D A A
1110 D D D D D D D D D D D A
1111 D D D D D D D D D D D D
A = Analog input D = Digital I/O

PIC18F6390/6490/8390/8490
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
bit 7 ADFM: A/D Result Format Select bit

1 = Right justified
0 = Left justified
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

PIC18F6390/6490/8390/8490
The analog reference voltage is software selectable to A device Reset forces all registers to their Reset state.
either the device’s positive and negative supply voltage This forces the A/D module to be turned off and any
(AVDD and AVSS), or the voltage level on the conversion in progress is aborted.
RA3/AN3/VREF+/SEG17 and RA2/AN2/VREF-/SEG16 Each port pin associated with the A/D converter can be
pins. configured as an analog input or as a digital I/O. The
The A/D converter has a unique feature of being able ADRESH and ADRESL registers contain the result of
to operate while the device is in Sleep mode. To oper- the A/D conversion. When the A/D conversion is com-
ate in Sleep, the A/D conversion clock must be derived plete, the result is loaded into the ADRESH/ADRESL
from the A/D’s internal RC oscillator. registers, the GO/DONE bit (ADCON0<1>) is cleared
The output of the sample and hold is the input into the and the A/D Interrupt Flag bit, ADIF, is set. The block
converter, which generates the result via successive diagram of the A/D module is shown in Figure 18-1.
approximation.
FIGURE 18-1: A/D BLOCK DIAGRAM
CHS3:CHS0
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
(Input Voltage) 0011
10-Bit AN3
A/D
Converter 0010
AN2
0001
VCFG1:VCFG0 AN1
AVDD(1) 0000
AN0
X0
VREF+ X1
Reference 1X
Voltage VREF- 0X
AVSS(1)
Note 1: I/O pins have diode protection to VDD and VSS.

PIC18F6390/6490/8390/8490
The value in the ADRESH:ADRESL registers is not 5. Wait for A/D conversion to complete, by either:
modified for a Power-on Reset. The ADRESH:ADRESL • Polling for the GO/DONE bit to be cleared
registers will contain unknown data after a Power-on
OR
Reset.
• Waiting for the A/D interrupt
After the A/D module has been configured as desired,
the selected channel must be acquired before the con- 6. Read A/D Result registers (ADRESH:ADRESL);
version is started. The analog input channels must clear ADIF bit, if required.
have their corresponding TRIS bits selected as an 7. For next conversion, go to step 1 or step 2, as
input. To determine acquisition time, see Section 18.1 required. The A/D conversion time per bit is
“A/D Acquisition Requirements”. After this acquisi- defined as TAD. A minimum wait of 3 TAD is
tion time has elapsed, the A/D conversion can be required before the next acquisition starts.
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual FIGURE 18-2: A/D TRANSFER FUNCTION
start of the conversion.
The following steps should be followed to perform an 3FFh
A/D conversion:
1. Configure the A/D module: 3FEh
Digital Code Output

• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2) 003h
• Select A/D conversion clock (ADCON2)

002h
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired): 001h
• Clear ADIF bit
• Set ADIE bit 000h
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
3 LSB
1022 LSB
1022.5 LSB
1023 LSB
1023.5 LSB
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
Analog Input Voltage
• Set GO/DONE bit (ADCON0<1>)
FIGURE 18-3: ANALOG INPUT MODEL

VDD
Sampling
Switch
VT = 0.6V
ANx RIC ≤ 1k SS RSS
Rs
VAIN CPIN ILEAKAGE

VT = 0.6V CHOLD = 25 pF
5 pF ±100 nA
VSS
Legend: CPIN = Input Capacitance

VT = Threshold Voltage 6V
ILEAKAGE = Leakage Current at the pin due to 5V
VDD 4V
various junctions 3V
RIC = Interconnect Resistance 2V
SS = Sampling Switch
CHOLD = Sample/Hold Capacitance (from DAC) 1 2 3 4
RSS = Sampling Switch Resistance Sampling Switch (kΩ)

PIC18F6390/6490/8390/8490
18.1 A/D Acquisition Requirements To calculate the minimum acquisition time,
Equation 18-1 may be used. This equation assumes
For the A/D converter to meet its specified accuracy, that 1/2 LSb error is used (1024 steps for the A/D). The
the charge holding capacitor (CHOLD) must be allowed 1/2 LSb error is the maximum error allowed for the A/D
to fully charge to the input channel voltage level. The to meet its specified resolution.
analog input model is shown in Figure 18-3. The
source impedance (RS) and the internal sampling Example 18-3 shows the calculation of the minimum
switch (RSS) impedance directly affect the time required acquisition time, TACQ. This calculation is
required to charge the capacitor CHOLD. The sampling based on the following application system
switch (RSS) impedance varies over the device voltage assumptions:
(VDD). The source impedance affects the offset voltage CHOLD = 25 pF
at the analog input (due to pin leakage current). The Rs = 2.5 kΩ
maximum recommended impedance for analog Conversion Error ≤ 1/2 LSb
sources is 2.5 kΩ. After the analog input channel is VDD = 5V → Rss = 2 kΩ
selected (changed), the channel must be sampled for Temperature = 85°C (system max.)
at least the minimum acquisition time before starting a
conversion.
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 18-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
EQUATION 18-2: A/D MINIMUM CHARGING TIME

VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 18-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ = TAMP + TC + TCOFF
TAMP = 0.2 μs
TCOFF = (Temp – 25°C)(0.02 μs/°C)
(50°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
5.03 μs
TACQ = 0.2 μs + 5 μs + 1.2 μs
6.4 μs

PIC18F6390/6490/8390/8490
18.2 Selecting and Configuring 18.3 Selecting the A/D Conversion
Automatic Acquisition Time Clock
The ADCON2 register allows the user to select an The A/D conversion time per bit is defined as TAD. The
acquisition time that occurs each time the GO/DONE A/D conversion requires 11 TAD per 10-bit conversion.
bit is set. The source of the A/D conversion clock is software
When the GO/DONE bit is set, sampling is stopped and selectable. There are seven possible options for TAD:
a conversion begins. The user is responsible for ensur- • 2 TOSC
ing the required acquisition time has passed between • 4 TOSC
selecting the desired input channel and setting the • 8 TOSC
GO/DONE bit. This occurs when the ACQT2:ACQT0
• 16 TOSC
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer • 32 TOSC
programmable acquisition times. • 64 TOSC
If desired, the ACQT bits can be set to select a • Internal RC Oscillator
programmable acquisition time for the A/D module. For correct A/D conversions, the A/D conversion clock
When the GO/DONE bit is set, the A/D module contin- (TAD) must be as short as possible, but greater than the
ues to sample the input for the selected acquisition minimum TAD (approximately 2 μs, see parameter 130
time, then automatically begins a conversion. Since the for more information).
acquisition time is programmed, there may be no need
Table 18-1 shows the resultant TAD times derived from
to wait for an acquisition time between selecting a
the device operating frequencies and the A/D clock
channel and setting the GO/DONE bit.
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 18-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS2:ADCS0 PIC18F6X90/8X90 PIC18LF6X90/8X90(4)

2 TOSC 000 1.25 MHz 666 kHz
4 TOSC 100 2.50 MHz 1.33 MHz
8 TOSC 001 5.00 MHz 2.66 MHz
16 TOSC 101 10.0 MHz 5.33 MHz
32 TOSC 010 20.0 MHz 10.65 MHz
64 TOSC 110 40.0 MHz 21.33 MHz
RC(3) x11 1.00 MHz(1) 1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 4 μs.
2: The RC source has a typical TAD time of 6 μs.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
4: Low-power (PIC18LFXXXX) devices only.

PIC18F6390/6490/8390/8490
18.4 Operation in Power-Managed 18.5 Configuring Analog Port Pins
Modes The ADCON1, TRISA and TRISF registers all
The selection of the automatic acquisition time and A/D configure the A/D port pins. The port pins needed as
conversion clock is determined in part by the clock analog inputs must have their corresponding TRIS bits
source and frequency while in a power-managed set (input). If the TRIS bit is cleared (output), the digital
mode. output level (VOH or VOL) will be converted.
If the A/D is expected to operate while the device is in The A/D operation is independent of the state of the
a power-managed mode, the ACQT2:ACQT0 and CHS3:CHS0 bits and the TRIS bits.
ADCS2:ADCS0 bits in ADCON2 should be updated in Note 1: When reading the PORT register, all pins
accordance with the power-managed mode clock that configured as analog input channels will
will be used. After the power-managed mode is read as cleared (a low level). Pins config-
entered, an A/D acquisition or conversion may be ured as digital inputs will convert an
started. Once an acquisition or conversion is started, analog input. Analog levels on a digitally
the device should continue to be clocked by the same configured input will be accurately
power-managed mode clock source until the conver- converted.
sion has been completed. If desired, the device may be
placed into the corresponding power-managed Idle 2: Analog levels on any pin defined as a
mode during the conversion. digital input may cause the digital input
buffer to consume current out of the
If the power-managed mode clock frequency is less device’s specification limits.
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D FRC
clock to be selected. If bits, ACQT2:ACQT0, are set to
‘000’ and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
and SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.

PIC18F6390/6490/8390/8490
18.6 A/D Conversions After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can be
Figure 18-4 shows the operation of the A/D converter started. After this wait, acquisition on the selected
after the GO/DONE bit has been set and the channel is automatically started.
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into Note: The GO/DONE bit should NOT be set in
Sleep mode before the conversion begins. the same instruction that turns on the A/D.
Figure 18-5 shows the operation of the A/D converter
after the GO/DONE bit has been set, the 18.7 Discharge
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acqui- The discharge phase is used to initialize the value of
sition time has been selected before the conversion the capacitor array. The array is discharged before
starts. every sample. This feature helps to optimize the
Clearing the GO/DONE bit during a conversion will unity-gain amplifier as the circuit always needs to
abort the current conversion. The A/D Result register charge the capacitor array, rather than
pair will NOT be updated with the partially completed charge/discharge based on previous measure values.
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
FIGURE 18-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts Discharge

Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit

On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
FIGURE 18-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQT Cycles TAD Cycles
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 TAD1
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Automatic
Acquisition Conversion starts Discharge
Time (Holding capacitor is disconnected)
Set GO/DONE bit

(Holding capacitor continues On the following cycle:
acquiring input) ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

PIC18F6390/6490/8390/8490
18.8 Use of the CCP2 Trigger software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input chan-
An A/D conversion can be started by the “Special Event nel must be selected and the minimum acquisition
Trigger” of the CCP2 module. This requires that the period is either timed by the user, or an appropriate
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- TACQ time selected before the “Special Event Trigger”
grammed as ‘1011’ and that the A/D module is enabled sets the GO/DONE bit (starts a conversion).
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition If the A/D module is not enabled (ADON is cleared), the
and conversion and the Timer1 (or Timer3) counter will “Special Event Trigger” will be ignored by the A/D
be reset to zero. Timer1 (or Timer3) is reset to automat- module, but will still reset the Timer1 (or Timer3)
ically repeat the A/D acquisition period with minimal counter.
TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Reset
on Page
ADRESH A/D Result Register High Byte 61
ADRESL A/D Result Register Low Byte 61
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 61
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 61
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 62
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 62
PORTF Read PORTF pins, Write LATF Latch 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These pins may be configured as port pins depending on the oscillator mode selected.

PIC18F6390/6490/8390/8490
19.0 COMPARATOR MODULE The CMCON register (Register 19-1) selects the
comparator input and output configuration. Block
The analog comparator module contains two diagrams of the various comparator configurations are
comparators that can be configured in a variety of shown in Figure 19-1.
ways. The inputs can be selected from the analog
inputs multiplexed with pins RF3 through RF6, as well
as the on-chip voltage reference (see Section 20.0
“Comparator Voltage Reference Module”). The digi-
tal outputs (normal or inverted) are available at the pin
level and can also be read through the control register.
REGISTER 19-1: CMCON: COMPARATOR CONTROL REGISTER

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
Legend:
bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3 CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RF5/AN10
C2 VIN- connects to RF3/AN8
0 = C1 VIN- connects to RF6/AN11
C2 VIN- connects to RF4/AN9
bit 2-0 CM2:CM0: Comparator Mode bits
Figure 19-1 shows the Comparator modes and the CM2:CM0 bit settings.

PIC18F6390/6490/8390/8490
19.1 Comparator Configuration mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
There are eight modes of operation for the compara- Section 26.0 “Electrical Characteristics”.
tors, shown in Figure 19-1. Bits, CM2:CM0 of the
CMCON register, are used to select these modes. The Note: Comparator interrupts should be disabled
TRISF register controls the data direction of the during a Comparator mode change;
comparator pins for each mode. If the Comparator otherwise, a false interrupt may occur.
FIGURE 19-1: COMPARATOR I/O OPERATING MODES

Comparators Reset (POR Default Value) Comparators Off
CM2:CM0 = 000 CM2:CM0 = 111
RF6/AN11/ A VIN- RF6/AN11/ D VIN-
SEG24 SEG24
VIN+ C1 Off (Read as ‘0’) VIN+ C1 Off (Read as ‘0’)
RF5/AN10/ A RF5/AN10/ D
CVREF/SEG23 CVREF/SEG23
RF4/AN9/ A VIN- RF4/AN9/ D VIN-

SEG22 SEG22
RF3/AN8/ A VIN+ C2 Off (Read as ‘0’) RF3/AN8/ D VIN+ C2 Off (Read as ‘0’)
SEG21 SEG21
Two Independent Comparators Two Independent Comparators with Outputs

CM2:CM0 = 010 CM2:CM0 = 011
RF6/AN11/ A VIN- RF6/AN11/ A VIN-
SEG24 SEG24
RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A VIN+ C1 C1OUT
RF2/AN7/C1OUT*/SEG20
RF4/AN9/ A VIN-
SEG22 RF4/AN9/ A VIN-
RF3/AN8/ A VIN+ C2 C2OUT SEG22
SEG21 RF3/AN8/ A VIN+ C2 C2OUT
SEG21
Two Common Reference Comparators Two Common Reference Comparators with Outputs
CM2:CM0 = 100 CM2:CM0 = 101
RF6/AN11/ A VIN- RF6/AN11/ A VIN-
SEG24 SEG24
RF5/AN10/ A VIN+ C1 C1OUT A VIN+ C1 C1OUT
RF5/AN10/
RF4/AN9/ A VIN-
SEG22 RF4/AN9/
RF3/AN8/ C2 C2OUT A VIN-
D VIN+ SEG22
SEG21 RF3/AN8/ C2 C2OUT
D VIN+
SEG21
One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 001 CM2:CM0 = 110
RF6/AN11/ A VIN- RF6/AN11/ A
SEG24 SEG24 CIS = 0 VIN-
RF5/AN10/ A VIN+ C1 C1OUT RF5/AN10/ A CIS = 1
VIN+ C1 C1OUT
RF2/AN7/C1OUT*/SEG20 RF4/AN9/ A
SEG22 CIS = 0 VIN-
RF3/AN8/ A CIS = 1
RF4/AN9/ D VIN- SEG21 VIN+ C2 C2OUT
SEG22
RF3/AN8/ D VIN+ C2 Off (Read as ‘0’)
SEG21 CVREF
From VREF Module
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
* Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs.

PIC18F6390/6490/8390/8490
19.2 Comparator Operation 19.3.2 INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 19-2, along with The comparator module also allows the selection of an
the relationship between the analog input levels and internally generated voltage reference from the com-
the digital output. When the analog input at VIN+ is less parator voltage reference module. This module is
than the analog input VIN-, the output of the comparator described in more detail in Section 20.0 “Comparator
is a digital low level. When the analog input at VIN+ is Voltage Reference Module”.
greater than the analog input VIN-, the output of the The internal reference is only available in the mode
comparator is a digital high level. The shaded areas of where four inputs are multiplexed to two comparators
the output of the comparator in Figure 19-2 represent (CM2:CM0 = 110). In this mode, the internal voltage
the uncertainty, due to input offsets and response time. reference is applied to the VIN+ pin of both comparators.
19.3 Comparator Reference 19.4 Comparator Response Time

Depending on the comparator operating mode, either Response time is the minimum time, after selecting a
an external or internal voltage reference may be used. new reference voltage or input source, before the
The analog signal present at VIN- is compared to the comparator output has a valid level. If the internal ref-
signal at VIN+ and the digital output of the comparator erence is changed, the maximum delay of the internal
is adjusted accordingly (Figure 19-2). voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
FIGURE 19-2: SINGLE COMPARATOR the comparators should be used (see Section 26.0
“Electrical Characteristics”).
VIN+
19.5 Comparator Outputs
+
Output The comparator outputs are read through the CMCON
VIN- –
register. These bits are read-only. The comparator
outputs may also be directly output to the RF2 and RF1
I/O pins. When enabled, multiplexers in the output path
of the RF2 and RF1 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
VIN- comparators is related to the input offset voltage and
the response time given in the specifications.
VIN+ Figure 19-3 shows the comparator output block
diagram.
The TRISF bits will still function as an output enable/
Output disable for the RF2 and RF1 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
19.3.1 EXTERNAL REFERENCE SIGNAL Note 1: When reading the PORT register, all pins
When external voltage references are used, the configured as analog inputs will read as a
comparator module can be configured to have the com- ‘0’. Pins configured as digital inputs will
parators operate from the same, or different reference convert an analog input according to the
sources. However, threshold detector applications may Schmitt Trigger input specification.
require the same reference. The reference signal must 2: Analog levels on any pin defined as a
be between VSS and VDD and can be applied to either digital input may cause the input buffer to
pin of the comparator(s). consume more current than is specified.

PIC18F6390/6490/8390/8490
FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM
MULTIPLEX
+
Port pins
To RF2 or
RF1 pin
- D Q Bus
CxINV Data
Read CMCON EN
D Q Set
CMIF
bit
EN CL
From
Other
Reset Comparator
19.6 Comparator Interrupts 19.7 Comparator Operation During

The comparator interrupt flag is set whenever there is
Sleep
a change in the output value of either comparator. When a comparator is active and the device is placed
Software will need to maintain information about the in Sleep mode, the comparator remains active and the
status of the output bits, as read from CMCON<7:6>, to interrupt is functional, if enabled. This interrupt will
determine the actual change that occurred. The CMIF wake-up the device from Sleep mode, when enabled.
bit (PIR2<6>) is the Comparator Interrupt Flag. The While the comparator is powered up, higher Sleep
CMIF bit must be reset by clearing it. Since it is also currents than shown in the power-down current
possible to write a ‘1’ to this register, a simulated specification will occur. Each operational comparator
interrupt may be initiated. will consume additional current, as shown in the
Both the CMIE bit (PIE2<6>) and the PEIE bit comparator specifications. To minimize power
(INTCON<6>) must be set to enable the interrupt. In consumption while in Sleep mode, turn off the
addition, the GIE bit (INTCON<7>) must also be set. If comparators (CM2:CM0 = 111) before entering Sleep.
any of these bits are clear, the interrupt is not enabled, If the device wakes up from Sleep, the contents of the
though the CMIF bit will still be set if an interrupt CMCON register are not affected.
condition occurs.
19.8 Effects of a Reset
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a A device Reset forces the CMCON register to its Reset
read operation is being executed (start of state, causing the comparator module to be in the
the Q2 cycle), then the CMIF (PIR2<6>) Comparator Reset mode (CM2:CM0 = 000). This
interrupt flag may not get set. ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
The user, in the Interrupt Service Routine, can clear the
present at Reset time. The comparators are powered
interrupt in the following manner:
down during the Reset interval.
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit, CMIF.
A mismatch condition will continue to set flag bit, CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit, CMIF, to be cleared.

PIC18F6390/6490/8390/8490
19.9 Analog Input Connection range by more than 0.6V in either direction, one of the
Considerations diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
A simplified circuit for an analog input is shown in recommended for the analog sources. Any external
Figure 19-4. Since the analog pins are connected to a component connected to an analog input pin, such as
digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little
and VSS. The analog input, therefore, must be between leakage current.
VSS and VDD. If the input voltage deviates from this
FIGURE 19-4: COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V RIC
RS < 10k
Comparator
AIN Input
CPIN ILEAKAGE
VA VT = 0.6V ±500 nA
5 pF
VSS
Legend: CPIN = Input Capacitance

VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Reset
on Page
PORTF Read PORTF pins, Write LATF Latch 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
20.0 COMPARATOR VOLTAGE used is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of the
REFERENCE MODULE
steps selected by the CVREF selection bits
The comparator voltage reference is a 16-tap resistor (CVR3:CVR0), with one range offering finer resolution.
ladder network that provides a selectable reference The equations used to calculate the output of the
voltage. Although its primary purpose is to provide a comparator voltage reference are as follows:
reference for the analog comparators, it may also be If CVRR = 1:
used independently of them. CVREF = ((CVR3:CVR0)/24) x CVRSRC
A block diagram of the module is shown in Figure 20-1. If CVRR = 0:
The resistor ladder is segmented to provide two ranges
CVREF = (CVDD x 1/4) + (((CVR3:CVR0)/32) x
of CVREF values and has a power-down function to
CVRSRC)
conserve power when the reference is not being used.
The module’s supply reference can be provided from The comparator reference supply voltage can come
either device VDD/VSS, or an external voltage from either VDD and VSS, or the external VREF+ and
reference. VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
20.1 Configuring the Comparator (CVRCON<4>).
Voltage Reference The settling time of the comparator voltage reference
must be considered when changing the CVREF
The voltage reference module is controlled through the output (see Table 26-3 in Section 26.0 “Electrical
CVRCON register (Register 20-1). The comparator Characteristics”).
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be
REGISTER 20-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:
bit 7 CVREN: Comparator Voltage Reference Enable bit

1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RF5/AN10/CVREF/SEG23 pin
0 = CVREF voltage is disconnected from the RF5/AN10/CVREF/SEG23 pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = VDD – VSS
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Note 1: CVROE overrides the TRISF<5> bit setting if enabled for output; RF5 must also be configured as an input
by setting TRISF<5> to ‘1’.

PIC18F6390/6490/8390/8490
FIGURE 20-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
VDD
CVRSS = 0 8R
CVR3:CVR0
CVREN R
16-to-1 MUX
16 Steps
CVREF
R
R
R
CVRR 8R
CVRSS = 1
VREF-
CVRSS = 0
20.2 Voltage Reference Accuracy/Error 20.4 Effects of a Reset

The full range of voltage reference cannot be realized A device Reset disables the voltage reference by
due to the construction of the module. The transistors clearing bit, CVREN (CVRCON<7>). This Reset also dis-
on the top and bottom of the resistor ladder network connects the reference from the RA2 pin by clearing bit,
(Figure 20-1) keep CVREF from approaching the refer- CVROE (CVRCON<6>), and selects the high-voltage
ence source rails. The voltage reference is derived range by clearing bit, CVRR (CVRCON<5>). The CVR
from the reference source; therefore, the CVREF output value select bits are also cleared.
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be 20.5 Connection Considerations
found in Section 26.0 “Electrical Characteristics”.
The voltage reference module operates independently
20.3 Operation During Sleep of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
When the device wakes up from Sleep through an TRISF<5> bit and the CVROE bit are both set.
interrupt or a Watchdog Timer time-out, the contents of Enabling the voltage reference output onto the RF5 pin,
the CVRCON register are not affected. To minimize with an input signal present, will increase current
current consumption in Sleep mode, the voltage consumption. Connecting RF5 as a digital output with
reference should be disabled. CVRSS enabled will also increase current
consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 20-2 shows an example buffering technique.

PIC18F6390/6490/8390/8490
FIGURE 20-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18FXXXX
CVREF
R(1)
Module
+
Voltage RF5 CVREF Output
–
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
TABLE 20-1: REGISTERS ASSOCIATED WITH THE COMPARATOR VOLTAGE REFERENCE

Reset
on Page
Legend: Shaded cells are not used with the comparator voltage reference.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
21.0 HIGH/LOW-VOLTAGE The High/Low-Voltage Detect Control register
(Register 21-1) completely controls the operation of the
DETECT (HLVD)
HLVD module. This allows the circuitry to be “turned
PIC18F6390/6490/8390/8490 devices have a off” by the user under software control, which
High/Low-Voltage Detect module (HLVD). This is a pro- minimizes the current consumption for the device.
grammable circuit that allows the user to specify both a The block diagram for the HLVD module is shown in
device voltage trip point and the direction of change Figure 21-1.
from that point. If the device experiences an excursion
past the trip point in that direction, an interrupt flag is
set. If the interrupt is enabled, the program execution
will branch to the interrupt vector address and the
software can then respond to the interrupt.
REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1)
bit 7 bit 0
Legend:
bit 7 VDIRMAG: Voltage Direction Magnitude Select bit

1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLVDL0)
0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD disabled
bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits(1)
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = 4.41V-4.87V
1101 = 4.11V-4.55V
1100 = 3.92V-4.34V
1011 = 3.72V-4.12V
1010 = 3.53V-3.91V
1001 = 3.43V-3.79V
1000 = 3.24V-3.58V
0111 = 2.95V-3.26V
0110 = 2.75V-3.03V
0101 = 2.64V-2.92V
0100 = 2.43V-2.69V
0011 = 2.35V-2.59V
0010 = 2.16V-2.38V
0001 = 1.96V-2.16V
0000 = Reserved
Note 1: HLVDL3:HLVDL0 modes that result in a trip point below the valid operating voltage of the device are not
tested.

PIC18F6390/6490/8390/8490
The module is enabled by setting the HLVDEN bit. event, depending on the configuration of the module.
Each time that the HLVD module is enabled, the cir- When the supply voltage is equal to the trip point, the
cuitry requires some time to stabilize. The IRVST bit is voltage tapped off of the resistor array is equal to the
a read-only bit and is used to indicate when the circuit internal reference voltage generated by the voltage
is stable. The module can only generate an interrupt reference module. The comparator then generates an
after the circuit is stable and IRVST is set. interrupt signal by setting the HLVDIF bit.
The VDIRMAG bit determines the overall operation of The trip point voltage is software programmable to any
the module. When VDIRMAG is cleared, the module one of 16 values. The trip point is selected by
monitors for drops in VDD below a predetermined set programming the HLVDL3:HLVDL0 bits
point. When the bit is set, the module monitors for rises (HLVDCON<3:0>).
in VDD above the set point. The HLVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
21.1 Operation external source. This mode is enabled when bits,
HLVDL3:HLVDL0, are set to ‘1111’. In this state, the
When the HLVD module is enabled, a comparator uses
comparator input is multiplexed from the external input
an internally generated reference voltage as the set
pin, HLVDIN. This gives users flexibility because it
point. The set point is compared with the trip point
allows them to configure the High/Low-Voltage Detect
where each node in the resistor divider represents a
interrupt to occur at any voltage in the valid operating
trip point voltage. The “trip point” voltage is the voltage
range.
level at which the device detects a high or low-voltage
FIGURE 21-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)

Externally Generated
Trip Point
VDD
VDD HLVDL3:HLVDL0 HLVDCON

Register
HLVDIN HLVDEN VDIRMAG

HLVDIN
16-to-1 MUX
Set
HLVDIF
HLVDEN
Internal Voltage
BOREN Reference

PIC18F6390/6490/8390/8490
21.2 HLVD Setup Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
The following steps are needed to set up the HLVD current requirements, the HLVD circuitry may only
module: need to be enabled for short periods where the voltage
1. Disable the module by clearing the HLVDEN bit is checked. After doing the check, the HLVD module
(HLVDCON<4>). may be disabled.
2. Write the value to the HLVDL3:HLVDL0 bits that
selects the desired HLVD trip point. 21.4 HLVD Start-up Time
3. Set the VDIRMAG bit to detect high voltage The internal reference voltage of the HLVD module,
(VDIRMAG = 1) or low voltage (VDIRMAG = 0). specified in electrical specification parameter #D423,
4. Enable the HLVD module by setting the may be used by other internal circuitry, such as the
HLVDEN bit. programmable Brown-out Reset. If the HLVD or other
5. Clear the HLVD interrupt flag (PIR2<2>), which circuits using the voltage reference are disabled to
may have been set from a previous interrupt. lower the device’s current consumption, the reference
6. Enable the HLVD interrupt, if interrupts are voltage circuit will require time to become stable before
desired, by setting the HLVDIE and GIE bits a low or high-voltage condition can be reliably
(PIE<2> and INTCON<7>). An interrupt will not detected. This start-up time, TIRVST, is an interval that
be generated until the IRVST bit is set. is independent of device clock speed. It is specified in
electrical specification parameter 36 (Table 26-10).
21.3 Current Consumption The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
When the module is enabled, the HLVD comparator this reason, brief excursions beyond the set point may
and voltage divider are enabled and will consume static not be detected during this interval. Refer to
current. The total current consumption, when enabled, Figure 21-2 or Figure 21-3.
is specified in electrical specification parameter
#D022B.
FIGURE 21-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)

CASE 1:
HLVDIF may not be set
VDD
VLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
HLVDIF cleared in software
Internal Reference is stable
CASE 2:
VDD
VLVD
HLVDIF
Enable HLVD
TIRVST
IRVST
HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists

PIC18F6390/6490/8390/8490
FIGURE 21-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
CASE 1:
HLVDIF may not be set
VLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST

CASE 2:
VLVD
VDD
HLVDIF
Enable HLVD
IRVST TIRVST

HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists
21.5 Applications FIGURE 21-4: TYPICAL LOW-VOLTAGE

DETECT APPLICATION
In many applications, the ability to detect a drop below,
or rise above a particular threshold, is desirable. For
example, the HLVD module could be periodically
enabled to detect USB attach or detach. This assumes
the device is powered by a lower voltage source than
the Universal Serial Bus when detached. An attach VA
would indicate a high-voltage detect from, for example, VB
3.3V to 5V (the voltage on USB) and vice versa for a
Voltage
detach. This feature could save a design a few extra

components and an attach signal (input pin).
For general battery applications, Figure 21-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage,
VA, the HLVD logic generates an interrupt at time, TA.
The interrupt could cause the execution of an ISR, TA TB
Time
which would allow the application to perform “house-
keeping tasks” and perform a controlled shutdown Legend: VA = HLVD trip point
before the device voltage exits the valid operating VB = Minimum valid device
range at TB. The HLVD, thus, would give the operating voltage
application a time window, represented by the
difference between TA and TB, to safely exit.

PIC18F6390/6490/8390/8490
21.6 Operation During Sleep 21.7 Effects of a Reset
When enabled, the HLVD circuitry continues to operate A device Reset forces all registers to their Reset state.
during Sleep. If the device voltage crosses the trip This forces the HLVD module to be turned off.
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
TABLE 21-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Reset
on Page
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
22.0 LIQUID CRYSTAL DISPLAY The LCD driver module supports:
(LCD) DRIVER MODULE • Direct driving of LCD panel
• Three LCD clock sources with selectable prescaler
The Liquid Crystal Display (LCD) driver module
generates the timing control to drive a static or • Up to four commons:
multiplexed LCD panel. In the 80-pin devices - Static
(PIC18F8390/8490), the module drives the panels of - 1/2 multiplex
up to four commons and up to 48 segments and in the - 1/3 multiplex
64-pin devices (PIC18F6390/6490), the module drives - 1/4 multiplex
the panels of up to four commons and up to
• Up to 48 (in 80-pin devices)/32 (in 64-pin devices)
32 segments. It also provides control of the LCD pixel
segments
data.
• Static, 1/2 or 1/3 LCD bias
A simplified block diagram of the module is shown in
Figure 22-1.
FIGURE 22-1: LCD DRIVER MODULE BLOCK DIAGRAM
LCDDATAx SE<47:0>
Data Bus Registers 192-to-48
24 x 8 MUX To I/O Pads
(= 4 x 48)
Timing Control
LCDCON COM3:COM0
To I/O Pads
LCDPS
LCDSEx
FOSC/4
T13CKI Clock Source

Select and
Prescaler
INTRC Oscillator

PIC18F6390/6490/8390/8490
22.1 LCD Registers used to enable or disable the LCD module. The LCD
panel can also operate during Sleep by clearing the
The LCD driver module has 32 registers: SLPEN (LCDCON<6>) bit.
• LCD Control Register (LCDCON) The LCDPS register, shown in Register 22-2,
• LCD Phase Register (LCDPS) configures the LCD clock source prescaler and the type
• Six LCD Segment Enable Registers of waveform, Type-A or Type-B. Details on these
(LCDSE5:LCDSE0) features are provided in Section 22.2 “LCD Clock
• 24 LCD Data Registers Source Selection”, Section 22.3 “LCD Bias Types”
(LCDDATA23:LCDDATA0) and Section 22.8 “LCD Waveform Generation”.
The LCDCON register, shown in Register 22-1,
controls the overall operation of the module. Once the
module is configured, the LCDEN (LCDCON<7>) bit is
REGISTER 22-1: LCDCON: LCD CONTROL REGISTER

R/W-0 R/W-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0
bit 7 bit 0
Legend: C = Clearable Only bit

bit 7 LCDEN: LCD Driver Enable bit

1 = LCD driver module is enabled
0 = LCD driver module is disabled
bit 6 SLPEN: LCD Driver Enable in Sleep mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5 WERR: LCD Write Failed Error bit
1 = LCDDATAx register written while LCDPS<WA> = 0 (must be cleared in software)
0 = No LCD write error
bit 3-2 CS1:CS0: Clock Source Select bits
00 = (FOSC/4)/8192
01 = T13CKI (Timer1)/32
1x = INTRC (31.25 kHz)/32
bit 1-0 LMUX1:LMUX0: Commons Select bits
Maximum Maximum
Number of Number of
LMUX1:LMUX0 Multiplex Bias
Pixels Pixels
(PIC18F6X90) (PIC18F8X90)
00 Static (COM0) 32 48 Static
01 1/2 (COM1:COM0) 64 96 1/2 or 1/3
10 1/3 (COM2:COM0) 96 144 1/2 or 1/3
11 1/4 (COM3:COM0) 128 192 1/3

PIC18F6390/6490/8390/8490
REGISTER 22-2: LCDPS: LCD PHASE REGISTER
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
WFT BIASMD LCDA WA LP3 LP2 LP1 LP0
bit 7 bit 0
Legend:
bit 7 WFT: Waveform Type Select bit

1 = Type-B waveform (phase changes on each frame boundary)
0 = Type-A waveform (phase changes within each common type)
bit 6 BIASMD: Bias Mode Select bit
When LMUX1:LMUX0 = 00:
0 = Static Bias mode (do not set this bit to ‘1’)
1 = 1/2 Bias mode
0 = 1/3 Bias mode
1 = 1/2 Bias mode
0 = 1/3 Bias mode
0 = 1/3 Bias mode (do not set this bit to ‘1’)
bit 5 LCDA: LCD Active Status bit
1 = LCD driver module is active
0 = LCD driver module is inactive
bit 4 WA: LCD Write Allow Status bit
1 = Write into the LCDDATAx registers is allowed
0 = Write into the LCDDATAx registers is not allowed
bit 3-0 LP3:LP0: LCD Prescaler Select bits
1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1

PIC18F6390/6490/8390/8490
The LCDSE5:LCDSE0 registers configure the Once the module is initialized for the LCD panel, the
functions of the port pins. Setting the segment enable individual bits of the LCDDATA23:LCDDATA0 registers
bit for a particular segment configures that pin as an are cleared or set to represent a clear or dark pixel,
LCD driver. There are six LCD Segment Enable respectively. Specific sets of LCDDATA registers are
registers listed in Table 22-1. The prototype LCDSEx used with specific segments and common signals.
register is shown in Register 22-3. Each bit represents a unique combination of a specific
segment connected to a specific common. Individual
TABLE 22-1: LCDSE REGISTERS AND LCDDATA bits are named by the convention “SxxCy”,
ASSOCIATED SEGMENTS with “xx” as the segment number and “y” as the
common number. The relationship is summarized in
Register Segments Table 22-2. The prototype LCDDATAx register is
LCDSE0 7:0 shown in Register 22-4.
LCDSE1 15:8 Note: Writing into the registers, LCDDATA4,
LCDSE2 23:16 LCDDATA5, LCDDATA10, LCDDATA11,
LCDDATA16, LCDDATA17, LCDDATA22
LCDSE3 31:24
and LCDDATA23, in PIC18F6X90 devices
LCDSE4 39:32 will not affect the status of any pixel and
LCDSE5 47:40 these registers can be used as General
Purpose Registers.
.
Note: The LCDSE5:LCDSE4 registers are not
implemented in PIC18F6X90 devices.
REGISTER 22-3: LCDSEx: LCD SEGMENTx ENABLE REGISTER

SE(n + 7) SE(n + 6) SE(n + 5) SE(n + 4) SE(n + 3) SE(n + 2) SE(n + 1) SE(n)
bit 7 bit 0
Legend:
bit 7-0 SE(n + 7):SE(n): Segment Enable bits

For LCDSE0: n = 0
For LCDSE1: n = 8
For LCDSE2: n = 16
For LCDSE3: n = 24
For LCDSE4: n = 32
For LCDSE5: n = 40
1 = Segment function of the pin is enabled, digital I/O is disabled
0 = I/O function of the pin is enabled

PIC18F6390/6490/8390/8490
TABLE 22-2: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
COM Lines
Segments
0 1 2 3
LCDDATA0 LCDDATA6 LCDDATA12 LCDDATA18
0 through 7
S00C0:S07C0 S00C1:S07C1 S00C2:S07C2 S00C3:S07C3
8 through 15
16 through 23
24 through 31
LCDDATA4(1) LCDDATA10(1) LCDDATA16(1) LCDDATA22(1)
32 through 39
LCDDATA5(1) LCDDATA11(1) LCDDATA17(1) LCDDATA23(1)
40 through 47
Note 1: These registers are implemented but not used as LCD data registers in 64-pin devices. They may be used
as general purpose data memory.
REGISTER 22-4: LCDDATAx: LCD DATAx REGISTER

S(n + 7)Cy S(n + 6)Cy S(n + 5)Cy S(n + 4)Cy S(n + 3)Cy S(n + 2)Cy S(n + 1)Cy S(n)Cy
bit 7 bit 0
Legend:
bit 7-0 S(n + 7)Cy:S(n)Cy: Pixel On bits

For LCDDATA0 through LCDDATA5: n = (8x), y = 0
For LCDDATA6 through LCDDATA11: n = (8(x – 6)), y = 1
1 = Pixel on (dark)
0 = Pixel off (clear)

PIC18F6390/6490/8390/8490
22.2 LCD Clock Source Selection The third clock source is a 31.25 kHz internal RC
oscillator/32, which provides approximately 1 kHz
The LCD driver module has 3 possible clock sources: output.
• (FOSC/4)/8192 The second and third clock sources may be used to
• T13CKI Clock/32 continue running the LCD while the processor is in
• INTRC/32 Sleep.
The first clock source is the system clock divided by Using the bits, CS1:CS0 (LCDCON<3:2>), any of these
8192 ((FOSC/4)/8192). This divider ratio is chosen to clock sources can be selected.
provide about 1 kHz output when the system clock is
8 MHz. The divider is not programmable. Instead, the 22.2.1 LCD PRESCALER
LCD prescaler bits, LCDPS<3:0>, are used to set the A 16-bit counter is available as a prescaler for the LCD
LCD frame clock rate. clock. The prescaler is not directly readable or writable;
The second clock source is the Timer1 oscillator/32. its value is set by the LP3:LP0 bits (LCDPS<3:0>), which
This also gives about 1 kHz when a 32.768 kHz crystal determine the prescaler assignment and prescale ratio.
is used with the Timer1 oscillator. To use the Timer1 The prescale values from 1:1 through 1:32768 in
oscillator as a clock source, the T1OSCEN power-of-2 increments are selectable.
(T1CON<3>) bit should be set.
FIGURE 22-2: LCD CLOCK GENERATION
COM0
COM1
COM2
COM3
System Clock
(FOSC/4) ÷8192
÷4 STAT
TMR1 32 kHz ÷32 ÷1, 2, 3, 4
Crystal Oscillator ÷2 DUP 4-Bit Prog Prescaler
Ring Counter
TRIP
Internal RC Oscillator QUAD
÷32
Nom FRC = 31.25 kHz LP3:LP0
LMUX1:LMUX0
(LCDPS<3:0>)
(LCDCON<1:0>)
CS1:CS0 LMUX1:LMUX0
(LCDCON<3:2>) (LCDCON<1:0>)

PIC18F6390/6490/8390/8490
22.3 LCD Bias Types If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
The LCD driver module can be configured into three then the TRIS setting of that pin is overridden.
bias types:
Note: On a Power-on Reset, the LMUX1:LMUX0
• Static Bias (2 voltage levels: AVSS and AVDD)
bits are ‘00’.
• 1/2 Bias (3 voltage levels: AVSS, 1/2 AVDD and
AVDD)
TABLE 22-3: PORTE<6:4> FUNCTION
• 1/3 Bias (4 voltage levels: AVSS, 1/3 AVDD, 2/3 AVDD
and AVDD) LMUX1:
PORTE<6> PORTE<5> PORTE<4>
LMUX0
This module uses an external resistor ladder to
generate the LCD bias voltages. 00 Digital I/O Digital I/O Digital I/O
The external resistor ladder should be connected to the 01 Digital I/O Digital I/O COM1 Driver
Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 3 10 Digital I/O COM2 Driver COM1 Driver
pin should also be connected to AVDD. 11 COM3 Driver COM2 Driver COM1 Driver
Figure 22-3 shows the proper way to connect the
resistor ladder to the Bias pins. 22.5 Segment Enables
22.4 LCD Multiplex Types The LCDSEx registers are used to select the pin
function for each segment pin. The selection allows
The LCD driver module can be configured into four each pin to operate as either an LCD segment driver or
multiplex types: a digital only pin. To configure the pin as a segment pin,
• Static (only COM0 used) the corresponding bits in the LCDSEx registers must
be set to ‘1’.
• 1/2 multiplex (COM0 and COM1 are used)
• 1/3 multiplex (COM0, COM1 and COM2 are used) If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEx
• 1/4 multiplex (all COM0, COM1, COM2 and COM3
registers overrides any bit settings in the corresponding
are used)
TRIS register.
The LMUX1:LMUX0 setting decides the function of the
PORTE<6:4> bits (see Table 22-3 for details). Note: On a Power-on Reset, these pins are
configured as digital I/O.
FIGURE 22-3: LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM
Static
1/2 Bias 1/3 Bias
Bias
VLCD 0 AVSS AVSS AVSS
VLCD 3 To VLCD 1 — 1/2 AVDD 1/3 AVDD
VLCD 2 LCD
VLCD 2 — 1/2 AVDD 2/3 AVDD
VLCD 1 Driver
VLCD 0 VLCD 3 AVDD AVDD AVDD
LCD Bias 3 LCD Bias 2 LCD Bias 1 Connections for External R-ladder
AVDD* Static Bias
1/2 Bias
AVDD* 10 kΩ* 10 kΩ*
AVSS
AVDD* 10 kΩ* 10 kΩ* 10 kΩ* 1/3 Bias

AVSS
* These values are provided for design guidance only and should be optimized for the application by the designer.

PIC18F6390/6490/8390/8490
22.6 Pixel Control 22.8 LCD Waveform Generation
The LCDDATAx registers contain bits which define the LCD waveform generation is based on the philosophy
state of each pixel. Each bit defines one unique pixel. that the net AC voltage across the dark pixel should be
Table 22-2 shows the correlation of each bit in the maximized and the net AC voltage across the clear
LCDDATAx registers to the respective common and pixel should be minimized. The net DC voltage across
segment signals. any pixel should be zero.
Any LCD pixel location not being used for display can The COM signal represents the time slice for each
be used as general purpose RAM. common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC com-
22.7 LCD Frame Frequency ponent and it can take only one of the two rms values.
The higher rms value will create a dark pixel and a
The rate at which the COM and SEG outputs changes lower rms value will create a clear pixel.
is called the LCD frame frequency
As the number of commons increases, the delta
between the two rms values decreases. The delta
TABLE 22-4: FRAME FREQUENCY represents the maximum contrast that the display can
FORMULAS have.
Multiplex Frame Frequency = The LCDs can be driven by two types of waveform:
Static Clock Source/(4 x 1 x (LP3:LP0 + 1)) Type-A and Type-B. In Type-A waveform, the phase
changes within each common type, whereas in Type-B
1/2 Clock Source/(2 x 2 x (LP3:LP0 + 1)) waveform, the phase changes on each frame
1/3 Clock Source/(1 x 3 x (LP3:LP0 + 1)) boundary. Thus, Type-A waveform maintains 0 VDC
1/4 Clock Source/(1 x 4 x (LP3:LP0 + 1)) over a single frame, whereas Type-B waveform takes
two frames.
Note: Clock source is (FOSC/4)/8192,
Timer1 Osc/32 or INTRC/32. Note 1: If Sleep has to be executed with LCD
Sleep enabled (LCDCON<SLPEN> is
TABLE 22-5: APPROXIMATE FRAME ‘1’), then care must be taken to execute
FREQUENCY (IN Hz) USING Sleep only when VDC on all the pixels is
FOSC @ 32 MHz, ‘0’.
TIMER1 @ 32.768 kHz OR 2: When the LCD clock source is
INTRC OSCILLATOR (FOSC/4)/8192, if Sleep is executed
irrespective of the LCDCON<SLPEN>
LP3:LP0 Static 1/2 1/3 1/4 setting, the LCD goes into Sleep. Thus,
1 125 125 167 125 take care to see that VDC on all pixels is ‘0’
when Sleep is executed.
2 83 83 111 83
3 62 62 83 62 Figure 22-4 through Figure 22-14 provide waveforms
for static, half-multiplex, one-third-multiplex and
4 50 50 67 50 quarter-multiplex drives for Type-A and Type-B
5 42 42 56 42 waveforms.
6 36 36 48 36
7 31 31 42 31

PIC18F6390/6490/8390/8490
FIGURE 22-4: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V1
COM0
COM0 V0
V1
SEG0
V0
V1
SEG1
V0
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
V1
COM0-SEG0 V0
-V1
COM0-SEG1 V0
1 Frame

PIC18F6390/6490/8390/8490
FIGURE 22-5: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
COM0 V1
V0
COM1
V2
COM0
COM1 V1
V0
V2
SEG0 V1
V0
V2
SEG3
SEG2
SEG1
SEG0
SEG1 V1
V0
V2
V1
COM0-SEG0 V0
-V1
-V2
V2
V1
COM0-SEG1 V0
-V1
-V2
1 Frame

PIC18F6390/6490/8390/8490
FIGURE 22-6: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
COM0 V1
COM1
V0
COM0
V2
COM1 V1
V0
V2
SEG0
V1
V0
V2
SEG1
SEG3
SEG2
SEG1
SEG0
V1
V0
V2
V1
COM0-SEG0 V0
-V1
-V2
V2
V1
COM0-SEG1 V0
-V1
-V2
2 Frames

PIC18F6390/6490/8390/8490
V3
V2
COM0
V1
COM1
V0
V3
COM0
V2
COM1
V1
V0
V3
V2
SEG0
V1
V0
V3
V2
SEG1
SEG3
SEG2
SEG1
SEG0
V1
V0
V3
V2
V1
COM0-SEG0 V0
-V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
-V1
-V2
1 Frame
-V3

PIC18F6390/6490/8390/8490
V3
V2
COM0
V1
COM1
V0
V3
COM0
V2
COM1
V1
V0
V3
V2
SEG0
V1
V0
V3
V2
SEG1
SEG3
SEG2
SEG1
SEG0
V1
V0
V3
V2
V1
COM0-SEG0 V0
-V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
-V1
-V2
2 Frames
-V3

PIC18F6390/6490/8390/8490
V2
COM0
V1
V0
COM2 V2
COM1 V1
COM1 V0
COM0
V2
COM2 V1
V0
V2
SEG0
V1
SEG2
V0
SEG2
SEG1
SEG0
V2
SEG1 V1
V0
V2
V1
COM0-SEG0 V0
-V1
-V2
V2
V1
COM0-SEG1 V0
-V1
-V2
1 Frame

PIC18F6390/6490/8390/8490
V2
COM0
V1
V0
COM2
V2
COM1
V1
COM1
V0
COM0
V2
COM2
V1
V0
V2
SEG0
V1
V0
SEG2
SEG1
SEG0
V2
SEG1
V1
V0
V2
V1
COM0-SEG0 V0
-V1
-V2
V2
V1
COM0-SEG1 V0
-V1
-V2
2 Frames

PIC18F6390/6490/8390/8490
V3
V2
COM0
V1
V0
COM2 V3
V2
COM1
V1
COM1
V0
COM0
V3
V2
COM2
V1
V0
V3
V2
SEG0
SEG2 V1
V0
SEG2
SEG1
SEG0
V3
V2
SEG1
V1
V0
V3
V2
V1
COM0-SEG0 V0
-V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
-V1
-V2
-V3
1 Frame

PIC18F6390/6490/8390/8490
V3
V2
COM0
V1
V0
COM2 V3
V2
COM1
V1
COM1
V0
COM0
V3
V2
COM2
V1
V0
V3
V2
SEG0
V1
V0
SEG2
SEG1
SEG0
V3
V2
SEG1
V1
V0
V3
V2
V1
COM0-SEG0 V0
-V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
-V1
-V2
-V3
2 Frames

PIC18F6390/6490/8390/8490
COM3
V3
COM2 V2
COM0 V1
V0
V3
COM1 V2
COM1 V1
COM0 V0
V3
V2
COM2 V1
V0
V3
V2
COM3 V1
V0
V3
V2
SEG0 V1
V0
SEG1
SEG0
V3
V2
SEG1 V1
V0
V3
V2
V1
COM0-SEG0 V0
-V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
-V1
-V2
-V3
1 Frame

PIC18F6390/6490/8390/8490
COM3
V3
COM2 V2
COM0 V1
V0
V3
COM1 V2
COM1 V1
COM0 V0
V3
V2
COM2 V1
V0
V3
V2
COM3 V1
V0
V3
V2
SEG0 V1
V0
SEG1
SEG0
V3
V2
SEG1 V1
V0
V3
V2
V1
COM0-SEG0 V0
-V1
-V2
-V3
V3
V2
V1
COM0-SEG1 V0
-V1
-V2
-V3
2 Frames

PIC18F6390/6490/8390/8490
22.9 LCD Interrupts When the LCD driver is running with Type-B waveforms
and the LMUX1:LMUX0 bits are not equal to ‘00’, there
The LCD timing generation provides an interrupt that are some additional issues that must be addressed.
defines the LCD frame timing. This interrupt can be Since the DC voltage on the pixel takes two frames to
used to coordinate the writing of the pixel data with the maintain zero volts, the pixel data must not change
start of a new frame. Writing pixel data at the frame between subsequent frames. If the pixel data were
boundary allows a visually crisp transition of the image. allowed to change, the waveform for the odd frames
This interrupt can also be used to synchronize external would not necessarily be the complement of the
events to the LCD. For example, the interface to an waveform generated in the even frames and a DC
external segment driver can be synchronized for component would be introduced into the panel. There-
segment data update to the LCD frame. fore, when using Type-B waveforms, the user must
A new frame is defined to begin at the leading edge of synchronize the LCD pixel updates to occur within a
the COM0 common signal. The interrupt will be set subframe after the frame interrupt.
immediately after the LCD controller completes To correctly sequence writing while in Type-B, the
accessing all pixel data required for a frame. This will interrupt will only occur on complete phase intervals. If
occur at a fixed interval before the frame boundary the user attempts to write when the write is disabled,
(TFINT), as shown in Figure 22-15. The LCD controller the WERR (LCDCON<5>) bit is set.
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins Note: The interrupt is not generated when the
to access data after the interrupt (TFWR). New data Type-A waveform is selected and when the
must be written within TFWR, as this is when the LCD Type-B with no multiplex (static) is
controller will begin to access the data for the next selected.
frame.
FIGURE 22-15: EXAMPLE WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY

CYCLE DRIVE
LCD Controller Accesses
Interrupt Next Frame Data
Occurs
V3
V2
COM0 V1
V0
V3
V2
COM1 V1
V0
V3
V2
COM2 V1
V0
COM3 V3
V2
V1
V0
2 Frames
TFINT
TFWR Frame
Frame Frame
Boundary Boundary Boundary
TFWR = TFRAME/2*(LMUX1:LMUX0 + 1) + TCY/2

TFINT = (TFWR/2 – (2 TCY + 40 ns)) → minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns)) → maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)

PIC18F6390/6490/8390/8490
22.10 Operation During Sleep If a SLEEP instruction is executed and SLPEN = 0, the
module will continue to display the current contents of
The LCD module can operate during Sleep. The selec- the LCDDATA registers. To allow the module to
tion is controlled by bit, SLPEN (LCDCON<6>). Setting continue operation while in Sleep, the clock source
the SLPEN bit allows the LCD module to go to Sleep. must be either the internal RC oscillator or Timer1
Clearing the SLPEN bit allows the module to continue external oscillator. While in Sleep, the LCD data cannot
to operate during Sleep. be changed. The LCD module current consumption will
If a SLEEP instruction is executed and SLPEN = 1, the not decrease in this mode, however, the overall
LCD module will cease all functions and go into a very consumption of the device will be lower due to shut
low-current consumption mode. The module will stop down of the core and other peripheral functions.
operation immediately and drive the minimum LCD If the system clock is selected and the module is
voltage on both segment and common lines. programmed to not Sleep, the module will ignore the
Figure 22-16 shows this operation. SLPEN bit and stop operation immediately. The
To ensure that no DC component is introduced on the minimum LCD voltage will then be driven onto the
panel, the SLEEP instruction should be executed segments and commons.
immediately after a LCD frame boundary. The LCD
Note: The internal RC oscillator or external
interrupt can be used to determine the frame boundary.
Timer1 oscillator must be used to operate
See Section 22.9 “LCD Interrupts” for the formulas to
the LCD module during Sleep.
calculate the delay.
FIGURE 22-16: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS1:CS0 = 00

V3
V2
V1
COM0 V0
V3
V2
V1
COM1 V0
V3
V2
V1
COM2 V0
V3
V2
V1
SEG0 V0
2 Frames
SLEEP Instruction Execution Wake-up

PIC18F6390/6490/8390/8490
22.11 Configuring the LCD Module 4. Write initial values to Pixel Data registers,
LCDDATA0 through LCDDATA23.
The following is the sequence of steps to configure the
5. Clear LCD Interrupt Flag, LCDIF (PIR3<6>),
LCD module.
and if desired, enable the interrupt by setting bit,
1. Select the frame clock prescale using bits, LCDIE (PIE3<6>).
LP3:LP0 (LCDPS<3:0>). 6. Enable the LCD module by setting bit, LCDEN
2. Configure the appropriate pins to function as (LCDCON<7>).
segment drivers using the LCDSEx registers.
3. Configure the LCD module for the following
using the LCDCON register:
- Multiplex and Bias mode, LMUX1:LMUX0
bits
- Timing source, CS1:CS0 bits
- Sleep mode, SLPEN bit

PIC18F6390/6490/8390/8490
TABLE 22-6: REGISTERS ASSOCIATED WITH LCD OPERATION
Reset
on Page
LCDDATA23(1) S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 63
LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 63
(1)
(1)
(1)
(2)
LCDSE4(2) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 64
LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 64
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers are implemented but unused on 64-pin devices and may be used as general purpose data
RAM.
2: These registers are unimplemented on 64-pin devices.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
23.0 SPECIAL FEATURES A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
OF THE CPU
In addition to their Power-up and Oscillator Start-up
PIC18F6390/6490/8390/8490 devices include several Timers provided for Resets, PIC18F6390/6490/8390/
features intended to maximize reliability and minimize 8490 devices have a Watchdog Timer, which is either
cost through elimination of external components. permanently enabled via the Configuration bits, or
These are: software controlled (if configured as disabled).
• Oscillator Selection The inclusion of an internal RC oscillator also provides
• Resets: the additional benefits of a Fail-Safe Clock Monitor
- Power-on Reset (POR) (FSCM) and Two-Speed Start-up. FSCM provides for
- Power-up Timer (PWRT) background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
- Oscillator Start-up Timer (OST)
Speed Start-up enables code to be executed almost
- Brown-out Reset (BOR) immediately on start-up, while the primary clock source
• Interrupts completes its start-up delays.
• Watchdog Timer (WDT) All of these features are enabled and configured by
• Fail-Safe Clock Monitor setting the appropriate Configuration register bits.
• Two-Speed Start-up
• Code Protection 23.1 Configuration Bits
• ID Locations The Configuration bits can be programmed (read as
• In-Circuit Serial Programming™ (ICSP™) ‘0’), or left unprogrammed (read as ‘1’), to select vari-
The oscillator can be configured for the application ous device configurations. These bits are mapped
depending on frequency, power, accuracy and cost. All starting at program memory location 300000h.
of the options are discussed in detail in Section 2.0 The user will note that address 300000h is beyond the
“Oscillator Configurations”. user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads.
TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs

Default/
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed
Value
300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — — — LPT1OSC — CCP2MX 1--- -0-1
300006h CONFIG4L DEBUG XINST — — — — — STVREN 10-- ---1
300008h CONFIG5L — — — — — — — CP ---- ---1
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 xxxx(1)
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Note 1: See Register 23-7 for DEVID values. DEVID registers are read-only and cannot be programmed by the user.

PIC18F6390/6490/8390/8490
REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1
IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7 IESO: Internal/External Oscillator Switchover bit

1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
bit 3-0 FOSC3:FOSC0: Oscillator Selection bits
11xx = External RC oscillator, CLKO function on RA6
101x = External RC oscillator, CLKO function on RA6
1001 = Internal oscillator block, CLKO function on RA6, port function on RA7
1000 = Internal oscillator block, port function on RA6 and RA7
0111 = External RC oscillator, port function on RA6
0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1)
0101 = EC oscillator, port function on RA6
0100 = EC oscillator, CLKO function on RA6
0011 = External RC oscillator, CLKO function on RA6
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator

PIC18F6390/6490/8390/8490
REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — BORV1 BORV0 BOREN1(1) BOREN0(1) PWRTEN(1)
bit 7 bit 0
Legend:

bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.1V
bit 2-1 BOREN1:BOREN0 Brown-out Reset Enable bits(1)
11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
10 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)
10 = Brown-out Reset disabled in hardware and software
bit 0 PWRTEN: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.

PIC18F6390/6490/8390/8490
U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
Legend:

bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)

R/P-1 U-0 U-0 U-0 U-0 R/P-0 U-0 R/P-1
MCLRE — — — — LPT1OSC — CCP2MX
bit 7 bit 0
Legend:
bit 7 MCLRE: MCLR Pin Enable bit

1 = MCLR pin enabled; RG5 input pin disabled
0 = RG5 input pin enabled; MCLR disabled
bit 2 LPT1OSC: Low-Power Timer 1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
bit 0 CCP2MX: CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RE7

PIC18F6390/6490/8390/8490
R/P-1 R/P-0 U-0 U-0 U-0 U-0 U-0 R/P-1
DEBUG XINST — — — — — STVREN
bit 7 bit 0
Legend:
bit 7 DEBUG: Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/C-1
— — — — — — — CP
bit 7 bit 0
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’

bit 0 CP: Code Protection bit
1 = Program memory block (000000-003FFFh) not code-protected
0 = Program memory block (000000-003FFFh) code-protected

PIC18F6390/6490/8390/8490
REGISTER 23-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6390/6490/8390/8490 DEVICES
R R R R R R R R
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
bit 7-5 DEV2:DEV0: Device ID bits

100 = PIC18F8390/8490
101 = PIC18F6390/6490
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 23-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F6390/6490/8390/8490 DEVICES

R R R R R R R R
DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1)
bit 7 bit 0
Legend:
bit 7-0 DEV10:DEV3: Device ID bits(1)

These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number.
0000 0110 = PIC18F6490/8490 devices
0000 1011 = PIC18F6390/8390 devices
Note 1: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified
by using the entire DEV10:DEV0 bit sequence.

PIC18F6390/6490/8390/8490
23.2 Watchdog Timer (WDT) Note 1: The CLRWDT and SLEEP instructions
For PIC18F6390/6490/8390/8490 devices, the WDT is clear the WDT and postscaler counts
driven by the INTRC source. When the WDT is when executed.
enabled, the clock source is also enabled. The nominal 2: Changing the setting of the IRCF bits
WDT period is 4 ms and has the same stability as the (OSCCON<6:4>) clears the WDT and
INTRC oscillator. postscaler counts.
The 4 ms period of the WDT is multiplied by a 16-bit 3: When a CLRWDT instruction is executed,
postscaler. Any output of the WDT postscaler is the postscaler count will be cleared.
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms 23.2.1 CONTROL REGISTER
to 134.2 seconds (2.24 minutes). The WDT and
Register 23-9 shows the WDTCON register. This is a
postscaler are cleared when any of the following events
readable and writable register, which contains a control
occur: a SLEEP or CLRWDT instruction is executed, the
bit that allows software to override the WDT enable
IRCF bits (OSCCON<6:4>) are changed, or a clock
Configuration bit, but only if the Configuration bit has
failure has occurred.
disabled the WDT.
FIGURE 23-1: WDT BLOCK DIAGRAM
SWDTEN Enable WDT

INTRC Control
WDTEN
WDT Counter
÷128 Wake-up from
INTRC Source
Power-Managed
Modes
Change on IRCF bits
Programmable Postscaler Reset WDT
CLRWDT Reset
1:1 to 1:32,768
All Device Resets WDT
WDTPS<3:0> 4
Sleep

PIC18F6390/6490/8390/8490
REGISTER 23-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — SWDTEN(1)
bit 7 bit 0
Legend:

bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Reset
on Page

WDTCON — — — — — — — SWDTEN 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

PIC18F6390/6490/8390/8490
23.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting the
The Two-Speed Start-up feature helps to minimize the IRCF2:IRCF0 bits prior to entering Sleep mode.
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC In all other power-managed modes, Two-Speed Start-up
oscillator as a clock source until the primary clock is not used. The device will be clocked by the currently
source is available. It is enabled by setting the IESO selected clock source until the primary clock source
Configuration bit. becomes available. The setting of the IESO bit is
ignored.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is LP, XT, HS or HSPLL 23.3.1 SPECIAL CONSIDERATIONS FOR
(Crystal-Based modes). Other sources do not require a USING TWO-SPEED START-UP
OST start-up delay; for these, Two-Speed Start-up
should be disabled. While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
When enabled, Resets and wake-ups from Sleep mode sequences for entering power-managed modes,
cause the device to configure itself to run from the including serial SLEEP instructions (refer to
internal oscillator block as the clock source, following Section 3.1.2 “Entering Power-Managed Modes”).
the time-out of the Power-up Timer after a Power-on In practice, this means that user code can change
Reset is enabled. This allows almost immediate code the SCS1:SCS0 bit settings or issue SLEEP
execution while the primary oscillator starts and the instructions before the OST times out. This would
OST is running. Once the OST times out, the device allow an application to briefly wake-up, perform
automatically switches to PRI_RUN mode. routine “housekeeping” tasks and return to Sleep
Because the OSCCON register is cleared on Reset before the device starts to operate from the primary
events, the INTOSC (or postscaler) clock source is not oscillator.
initially available after a Reset event; the INTRC clock User code can also check if the primary clock source is
is used directly at its base frequency. To use a higher currently providing the device clocking by checking the
clock speed on wake-up, the INTOSC or postscaler status of the OSTS bit (OSCCON<3>). If the bit is set,
clock sources can be selected to provide a higher clock the primary oscillator is providing the clock. Otherwise,
speed by setting bits, IRCF2:IRCF0, immediately after the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 23-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST(1) TPLL(1)
1 2 n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program PC PC + 2 PC + 4 PC + 6
Counter
Wake from Interrupt Event OSTS bit Set

PIC18F6390/6490/8390/8490
23.4 Fail-Safe Clock Monitor To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
The Fail-Safe Clock Monitor (FSCM) allows the a higher clock speed by setting bits, IRCF2:IRCF0,
microcontroller to continue operation in the event of an immediately after Reset. For wake-ups from Sleep, the
external oscillator failure by automatically switching the INTOSC or postscaler clock sources can be selected
device clock to the internal oscillator block. The FSCM by setting the IRCF2:IRCF0 bits prior to entering Sleep
function is enabled by setting the FCMEN Configuration mode.
bit.
The FSCM will detect failures of the primary or second-
When FSCM is enabled, the INTRC oscillator runs at ary clock sources only. If the internal oscillator block
all times to monitor clocks to peripherals and provide a fails, no failure would be detected, nor would any action
backup clock in the event of a clock failure. Clock be possible.
monitoring (shown in Figure 23-3) is accomplished by
creating a sample clock signal, which is the INTRC out- 23.4.1 FSCM AND THE WATCHDOG TIMER
put divided by 64. This allows ample time between
Both the FSCM and the WDT are clocked by the
FSCM sample clocks for a peripheral clock edge to
INTRC oscillator. Since the WDT operates with a
occur. The peripheral device clock and the sample
separate divider and counter, disabling the WDT has
clock are presented as inputs to the Clock Monitor latch
no effect on the operation of the INTRC oscillator when
(CM). The CM is set on the falling edge of the device
the FSCM is enabled.
clock source, but cleared on the rising edge of the
sample clock. As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
FIGURE 23-3: FSCM BLOCK DIAGRAM Depending on the frequency selected by the
Clock Monitor
IRCF2:IRCF0 bits, this may mean a substantial change
Latch (CM) in the speed of code execution. If the WDT is enabled
(edge-triggered) with a small prescale value, a decrease in clock speed
Peripheral allows a WDT time-out to occur and a subsequent
S Q
Clock device Reset. For this reason, Fail-Safe Clock Monitor
events also reset the WDT and postscaler, allowing
them to start timing from when execution speed was
INTRC changed and decreasing the likelihood of an erroneous
÷ 64 C Q
Source time-out.
(32 μs) 488 Hz
(2.048 ms) 23.4.2 EXITING FAIL-SAFE OPERATION
The Fail-Safe condition is terminated by either a device
Clock Reset or by entering a power-managed mode. On
Failure
Detected
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
Clock failure is tested for on the falling edge of the required start-up delays that are required for the oscil-
sample clock. If a sample clock falling edge occurs lator mode, such as the OST or PLL timer). The
while CM is still set, a clock failure has been detected INTOSC multiplexer provides the device clock until the
(Figure 23-4). This causes the following: primary clock source becomes ready (similar to a Two-
Speed Start-up). The clock source is then switched to
• the FSCM generates an oscillator fail interrupt by the primary clock (indicated by the OSTS bit in the
setting bit OSCFIF (PIR2<7>); OSCCON register becoming set). The Fail-Safe Clock
• the device clock source is switched to the internal Monitor then resumes monitoring the peripheral clock.
oscillator block (OSCCON is not updated to show
The primary clock source may never become ready
the current clock source – this is the Fail-Safe
during start-up. In this case, operation is clocked by the
condition); and
INTOSC multiplexer. The OSCCON register will remain
• the WDT is reset. in its Reset state until a power-managed mode is
During switchover, the postscaler frequency from the entered.
internal oscillator block may not be sufficiently stable for
timing sensitive applications. In these cases, it may be
desirable to select another clock configuration and enter
an alternate power-managed mode. This can be done to
attempt a partial recovery or execute a controlled shut-
down. See Section 3.1.2 “Entering Power-Managed
Modes” and Section 23.3.1 “Special Considerations
for Using Two-Speed Start-up” for more details.

PIC18F6390/6490/8390/8490
FIGURE 23-4: FSCM TIMING DIAGRAM
Sample Clock
Device Oscillator
Clock Failure
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test CM Test CM Test

Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this
example have been chosen for clarity.
23.4.3 FSCM INTERRUPTS IN 23.4.4 POR OR WAKE FROM SLEEP

POWER-MANAGED MODES The FSCM is designed to detect oscillator failure at any
By entering a power-managed mode, the clock point after the device has exited Power-on Reset
multiplexer selects the clock source selected by the (POR) or low-power Sleep mode. When the primary
OSCCON register. Fail-Safe Clock Monitoring of device clock is EC, RC or INTRC modes, monitoring
the power-managed clock source resumes in the can begin immediately following these events.
power-managed mode. For oscillator modes involving a crystal or resonator
If an oscillator failure occurs during power-managed (HS, HSPLL, LP or XT), the situation is somewhat
operation, the subsequent events depend on whether different. Since the oscillator may require a start-up
or not the Oscillator Failure Interrupt Flag is enabled. If time considerably longer than the FCSM sample clock
enabled (OSCFIF = 1), code execution will be clocked time, a false clock failure may be detected. To prevent
by the INTOSC multiplexer. An automatic transition this, the internal oscillator block is automatically con-
back to the failed clock source will not occur. figured as the device clock and functions until the
primary clock is stable (the OST and PLL timers have
If the interrupt is disabled, the device will not exit the
timed out). This is identical to Two-Speed Start-up
power-managed mode on oscillator failure. Instead, the
mode. Once the primary clock is stable, the INTRC
device will continue to operate as before, but clocked
returns to its role as the FSCM source.
by the INTOSC multiplexer. While in Idle mode, sub-
sequent interrupts will cause the CPU to begin Note: The same logic that prevents false
executing instructions while being clocked by the oscillator failure interrupts on POR, or
INTOSC multiplexer. wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
As noted in Section 23.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an
alternate power-managed mode while waiting for the
primary clock to become stable. When the new power-
managed mode is selected, the primary clock is
disabled.

PIC18F6390/6490/8390/8490
23.5 Program Verification and 23.5.1 READING PROGRAM MEMORY
Code Protection AND OTHER LOCATIONS
The overall structure of the code protection on the The program memory may be read to any location
PIC18F6390/6490/8390/8490 Flash devices differs using the table read instructions. The Device ID and the
from previous PIC18 devices. Configuration registers may be read with the table read
instructions.
For all devices in the PIC18F6X90/8X90 family, the
user program memory is made of a single block. 23.5.2 CONFIGURATION REGISTER
Figure 23-5 shows the program memory organization PROTECTION
for individual devices. Code protection for this block is
controlled by a single bit, CP (CONFIG5L<0>). The CP The Configuration registers can only be written via
bit inhibits external reads from and writes to the entire ICSP using an external programmer. No separate
program memory space. It has no direct effect in protection bit is associated with them.
normal execution mode.
FIGURE 23-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6390/6490/8390/8490

MEMORY SIZE/DEVICE
Block Code Protection
8 Kbytes Address 16 Kbytes Address Controlled By:
(PIC18F6390/8390) Range (PIC18F6490/8490) Range
Program Memory 000000h Program Memory 000000h

CP, EBTR
Block 001FFFh Block 003FFFh
002000h 004000h
Unimplemented Unimplemented
Read ‘0’s Read ‘0’s (Unimplemented Memory Space)
1FFFFFh 1FFFFFh
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS

300008h CONFIG5L — — — — — — — CP
Legend: Shaded cells are unimplemented.

PIC18F6390/6490/8390/8490
23.6 ID Locations 23.8 In-Circuit Debugger
Eight memory locations (200000h-200007h) are When the DEBUG Configuration bit is programmed to
designated as ID locations, where the user can store a ‘0’, the In-Circuit Debugger functionality is enabled.
checksum or other code identification numbers. These This function allows simple debugging functions when
locations are readable during normal execution through used with MPLAB® IDE. When the microcontroller has
the TBLRD instruction. During program/verify, these this feature enabled, some resources are not available
locations are readable and writable. The ID locations for general use. Table 23-4 shows which resources are
can be read when the device is code-protected. required by the background debugger.
23.7 In-Circuit Serial Programming TABLE 23-4: DEBUGGER RESOURCES

PIC18F6390/6490/8390/8490 microcontrollers can be I/O pins: RB6, RB7
serially programmed while in the end application circuit. Stack: 2 levels
This is simply done with two lines for clock and data Program Memory: 512 bytes
and three other lines for power, ground and the
Data Memory: 10 bytes
programming voltage. This allows customers to
manufacture boards with unprogrammed devices and To use the In-Circuit Debugger function of the micro-
then program the microcontroller just before shipping controller, the design must implement In-Circuit Serial
the product. This also allows the most recent firmware Programming connections to MCLR/VPP, VDD, VSS,
or a custom firmware to be programmed. RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
24.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following
operands:
PIC18FXX90 devices incorporate the standard set of
• A literal value to be loaded into a file register
seventy-five PIC18 core instructions, as well as an
(specified by ‘k’)
extended set of 8 new instructions for the optimization
of code that is recursive or that utilizes a software • The desired FSR register to load the literal value
stack. The extended set is discussed later in this into (specified by ‘f’)
section. • No operand required
(specified by ‘—’)
24.1 Standard Instruction Set The control instructions may use some of the following
operands:
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction • A program memory address (specified by ‘n’)
sets, while maintaining an easy migration from these • The mode of the CALL or RETURN instructions
PIC MCU instruction sets. Most instructions are a (specified by ‘s’)
single program memory word (16 bits), but there are • The mode of the table read and table write
four instructions that require two program memory instructions (specified by ‘m’)
locations. • No operand required
Each single-word instruction is a 16-bit word divided (specified by ‘—’)
into an opcode, which specifies the instruction type and All instructions are a single word, except for four
one or more operands, which further specify the double-word instructions. These instructions were
operation of the instruction. made double-word to contain the required information
The instruction set is highly orthogonal and is grouped in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
into four basic categories: this second word is executed as an instruction (by
• Byte-oriented operations itself), it will execute as a NOP.
• Bit-oriented operations All single-word instructions are executed in a single
• Literal operations instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
• Control operations
tion. In these cases, the execution takes two instruction
The PIC18 instruction set summary in Table 24-2 lists cycles with the additional instruction cycle(s) executed
byte-oriented, bit-oriented, literal and control as a NOP.
operations. Table 24-1 shows the opcode field
The double-word instructions execute in two instruction
descriptions.
cycles.
Most byte-oriented instructions have three operands:
One instruction cycle consists of four oscillator periods.
1. The file register (specified by ‘f’) Thus, for an oscillator frequency of 4 MHz, the normal
2. The destination of the result (specified by ‘d’) instruction execution time is 1 μs. If a conditional test is
3. The accessed memory (specified by ‘a’) true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
The file register designator, ‘f’, specifies which file Two-word branch instructions (if true) would take 3 μs.
register is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the opera- Figure 24-1 shows the general formats that the instruc-
tion is to be placed. If ‘d’ is zero, the result is placed in tions can have. All examples use the convention ‘nnh’
the WREG register. If ‘d’ is one, the result is placed in to represent a hexadecimal number.
the file register specified in the instruction. The Instruction Set Summary, shown in Table 24-2,
All bit-oriented instructions have three operands: lists the standard instructions recognized by the
Microchip MPASMTM Assembler.
1. The file register (specified by ‘f’)
Section 24.1.1 “Standard Instruction Set” provides
2. The bit in the file register (specified by ‘b’)
a description of each instruction.
3. The accessed memory (specified by ‘a’)
The bit field designator, ‘b’, selects the number of the bit
affected by the operation, while the file register desig-
nator, ‘f’, represents the number of the file in which the
bit is located.

PIC18F6390/6490/8390/8490
TABLE 24-1: OPCODE FIELD DESCRIPTIONS
Field Description
a RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f 8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
fs 12-bit register file address (000h to FFFh). This is the source address.
fd 12-bit register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
* No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
n The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-Down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
s Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a Program Memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
u Unused or unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
x Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs 7-bit offset value for Indirect Addressing of register files (source).
zd 7-bit offset value for Indirect Addressing of register files (destination).
{ } Optional argument.
[text] Indicates an indexed address.
(text) The contents of text.
[expr]<n> Specifies bit n of the register indicated by the pointer expr.
→ Assigned to.
< > Register bit field.
∈ In the set of.
italics User-defined term (font is Courier New).

PIC18F6390/6490/8390/8490
FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations Example Instruction
15 10 9 8 7 0
OPCODE d a f (FILE #) ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)

15 12 11 0
OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2
15 12 11 0
1111 f (Destination FILE #)
Bit-oriented file register operations

15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B
b = 3-bit position of bit in file register (f)

a = 0 to force Access Bank
a = 1 for BSR to select bank
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
n = 20-bit immediate value
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC

PIC18F6390/6490/8390/8490
TABLE 24-2: PIC18FXXXX INSTRUCTION SET
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, Skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, Skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, Skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
Borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
Borrow
SWAPF f, d, a Swap Nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, Skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared
if assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.

PIC18F6390/6490/8390/8490
TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, d, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call Subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to Address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop Top of Return Stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push Top of Return Stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software Device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from Interrupt Enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
if assigned.

PIC18F6390/6490/8390/8490
TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)
LITERAL OPERATIONS
ADDLW k Add Literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND Literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR Literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move Literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move Literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move Literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply Literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with Literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from Literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR Literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with Post-Increment 0000 0000 0000 1001 None
TBLRD*- Table Read with Post-Decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with Pre-Increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None 5
TBLWT*+ Table Write with Post-Increment 0000 0000 0000 1101 None 5
TBLWT*- Table Write with Post-Decrement 0000 0000 0000 1110 None 5
TBLWT+* Table Write with Pre-Increment 0000 0000 0000 1111 None 5
if assigned.

PIC18F6390/6490/8390/8490
24.1.1 STANDARD INSTRUCTION SET
ADDLW ADD Literal to W ADDWF ADD W to f
Syntax: ADDLW k Syntax: ADDWF f {,d {,a}}
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
Operation: (W) + k → W
a ∈ [0,1]
Status Affected: N, OV, C, DC, Z
Operation: (W) + (f) → dest
Encoding: 0000 1111 kkkk kkkk
Description: The contents of W are added to the
Encoding: 0010 01da ffff ffff
8-bit literal ‘k’ and the result is placed
in W. Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
Words: 1 result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
Cycles: 1 (default).
Q Cycle Activity: If ‘a’ is ‘0’, the Access Bank is selected.
Q1 Q2 Q3 Q4 If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Decode Read Process Write to W
literal ‘k’ Data If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
Example: ADDLW 15h mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Before Instruction Bit-Oriented Instructions in Indexed
W = 10h Literal Offset Mode” for details.
After Instruction
W = 25h Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register ‘f’ Data destination
Example: ADDWF REG, 0, 0

Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

PIC18F6390/6490/8390/8490
ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W
Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255
d ∈ [0,1]
Operation: (W) .AND. k → W
a ∈ [0,1]
Status Affected: N, Z
Operation: (W) + (f) + (C) → dest
Status Affected: N,OV, C, DC, Z
Description: The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
Description: Add W, the Carry flag and data memory Words: 1
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is Cycles: 1
placed in data memory Q Cycle Activity:
location ‘f’.
Q1 Q2 Q3 Q4
If ‘a’ is ‘0’, the Access Bank is selected.
Decode Read literal Process Write to W
If ‘a’ is ‘1’, the BSR is used to select the
‘k’ Data
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates Example: ANDLW 05Fh
in Indexed Literal Offset Addressing Before Instruction
mode whenever f ≤ 95 (5Fh). See W = A3h
Section 24.2.3 “Byte-Oriented and After Instruction
Bit-Oriented Instructions in Indexed W = 03h
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: ADDWFC REG, 0, 1

Before Instruction
Carry bit = 1
REG = 02h
W = 4Dh
After Instruction
Carry bit = 0
REG = 02h
W = 50h

PIC18F6390/6490/8390/8490
ANDWF AND W with f BC Branch if Carry
Syntax: ANDWF f {,d {,a}} Syntax: BC n
Operands: 0 ≤ f ≤ 255 Operands: -128 ≤ n ≤ 127
d ∈ [0,1]
Operation: if Carry bit is ‘1’,
a ∈ [0,1]
(PC) + 2 + 2n → PC
Operation: (W) .AND. (f) → dest
Status Affected: None
Status Affected: N, Z Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is ‘1’, then the program
Description: The contents of W are ANDed with will branch.
register ‘f’. If ‘d’ is ‘0’, the result is stored The 2’s complement number ‘2n’ is
in W. If ‘d’ is ‘1’, the result is stored back added to the PC. Since the PC will have
in register ‘f’ (default). incremented to fetch the next
If ‘a’ is ‘0’, the Access Bank is selected. instruction, the new address will be
If ‘a’ is ‘1’, the BSR is used to select the PC + 2 + 2n. This instruction is then a
GPR bank. two-cycle instruction.
If ‘a’ is ‘0’ and the extended instruction Words: 1
Cycles: 1(2)
mode whenever f ≤ 95 (5Fh). See Q Cycle Activity:
Section 24.2.3 “Byte-Oriented and If Jump:
Bit-Oriented Instructions in Indexed Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC
Words: 1 ‘n’ Data
Cycles: 1 No No No No
operation operation operation operation
Q Cycle Activity:
If No Jump:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
register ‘f’ Data destination Decode Read literal Process No
‘n’ Data operation
Example: ANDWF REG, 0, 0

Example: HERE BC 5
Before Instruction
Before Instruction
W = 17h
REG = C2h PC = address (HERE)
After Instruction After Instruction
W = 02h If Carry = 1;
REG = C2h PC = address (HERE + 12)
If Carry = 0;
PC = address (HERE + 2)

PIC18F6390/6490/8390/8490
BCF Bit Clear f BN Branch if Negative
Syntax: BCF f, b {,a} Syntax: BN n
0≤b≤7
Operation: if Negative bit is ‘1’,
a ∈ [0,1]
(PC) + 2 + 2n → PC
Operation: 0 → f
Status Affected: None Encoding: 1110 0110 nnnn nnnn
Encoding: 1001 bbba ffff ffff
Description: If the Negative bit is ‘1’, then the
Description: Bit ‘b’ in register ‘f’ is cleared. program will branch.
If ‘a’ is ‘0’, the Access Bank is selected. The 2’s complement number ‘2n’ is
If ‘a’ is ‘1’, the BSR is used to select the added to the PC. Since the PC will have
GPR bank. incremented to fetch the next
If ‘a’ is ‘0’ and the extended instruction instruction, the new address will be
set is enabled, this instruction operates PC + 2 + 2n. This instruction is then a
in Indexed Literal Offset Addressing two-cycle instruction.
mode whenever f ≤ 95 (5Fh). See Words: 1
Cycles: 1(2)
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Q Cycle Activity:
Words: 1 If Jump:
Cycles: 1 Q1 Q2 Q3 Q4
Q Cycle Activity:
‘n’ Data
Q1 Q2 Q3 Q4 No No No No
Decode Read Process Write operation operation operation operation
register ‘f’ Data register ‘f’ If No Jump:
Q1 Q2 Q3 Q4
Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No
Before Instruction ‘n’ Data operation
FLAG_REG = C7h
After Instruction Example: HERE BN Jump
FLAG_REG = 47h
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;

PIC18F6390/6490/8390/8490
BNC Branch if Not Carry BNN Branch if Not Negative
Syntax: BNC n Syntax: BNN n
Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127
Operation: if Carry bit is ‘0’, Operation: if Negative bit is ‘0’,
(PC) + 2 + 2n → PC (PC) + 2 + 2n → PC
Status Affected: None Status Affected: None
Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn
Description: If the Carry bit is ‘0’, then the program Description: If the Negative bit is ‘0’, then the
will branch. program will branch.
The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is
added to the PC. Since the PC will added to the PC. Since the PC will have
have incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
two-cycle instruction. two-cycle instruction.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Q Cycle Activity: Q Cycle Activity:
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC Decode Read literal Process Write to PC
‘n’ Data ‘n’ Data
No No No No No No No No
operation operation operation operation operation operation operation operation
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
‘n’ Data operation ‘n’ Data operation
Example: HERE BNC Jump Example: HERE BNN Jump

Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
If Carry = 0; If Negative = 0;
PC = address (Jump) PC = address (Jump)
If Carry = 1; If Negative = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

PIC18F6390/6490/8390/8490
BNOV Branch if Not Overflow BNZ Branch if Not Zero
Syntax: BNOV n Syntax: BNZ n
Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127
Operation: if Overflow bit is ‘0’, Operation: if Zero bit is ‘0’,
(PC) + 2 + 2n → PC (PC) + 2 + 2n → PC
Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn
Description: If the Overflow bit is ‘0’, then the Description: If the Zero bit is ‘0’, then the program
program will branch. will branch.
The 2’s complement number ‘2n’ is The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have added to the PC. Since the PC will have
incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
two-cycle instruction. two-cycle instruction.
Words: 1 Words: 1
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC Decode Read literal Process Write to PC
‘n’ Data ‘n’ Data
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
‘n’ Data operation ‘n’ Data operation
Example: HERE BNOV Jump Example: HERE BNZ Jump

If Overflow = 0; If Zero = 0;
PC = address (Jump) PC = address (Jump)
If Overflow = 1; If Zero = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

PIC18F6390/6490/8390/8490
BRA Unconditional Branch BSF Bit Set f
Syntax: BRA n Syntax: BSF f, b {,a}
Operands: -1024 ≤ n ≤ 1023 Operands: 0 ≤ f ≤ 255
0≤b≤7
Operation: (PC) + 2 + 2n → PC
a ∈ [0,1]
Operation: 1 → f
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number ‘2n’ to
Encoding: 1000 bbba ffff ffff
the PC. Since the PC will have
incremented to fetch the next Description: Bit ‘b’ in register ‘f’ is set.
instruction, the new address will be If ‘a’ is ‘0’, the Access Bank is selected.
PC + 2 + 2n. This instruction is a If ‘a’ is ‘1’, the BSR is used to select the
two-cycle instruction. GPR bank.
Words: 1 If ‘a’ is ‘0’ and the extended instruction
Cycles: 2
Q Cycle Activity: mode whenever f ≤ 95 (5Fh). See
Q1 Q2 Q3 Q4 Section 24.2.3 “Byte-Oriented and
Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed
‘n’ Data Literal Offset Mode” for details.
No No No No Words: 1
operation operation operation operation Cycles: 1
Q Cycle Activity:
Example: HERE BRA Jump Q1 Q2 Q3 Q4
Before Instruction Decode Read Process Write
PC = address (HERE) register ‘f’ Data register ‘f’
After Instruction
PC = address (Jump) Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah

PIC18F6390/6490/8390/8490
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a}
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
0≤b≤7 0≤b<7
a ∈ [0,1] a ∈ [0,1]
Operation: skip if (f) = 0 Operation: skip if (f) = 1
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the the next instruction fetched during the
current instruction execution is discarded current instruction execution is discarded
and a NOP is executed instead, making and a NOP is executed instead, making
this a two-cycle instruction. this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the ‘a’ is ‘1’, the BSR is used to select the
GPR bank. GPR bank.
If ‘a’ is ‘0’ and the extended instruction set If ‘a’ is ‘0’ and the extended instruction
is enabled, this instruction operates in set is enabled, this instruction operates
Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). mode whenever f ≤ 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Literal Offset Mode” for details.
Words: 1 Words: 1
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process No Decode Read Process No
register ‘f’ Data operation register ‘f’ Data operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0

FALSE : FALSE :
TRUE : TRUE :
If FLAG<1> = 0; If FLAG<1> = 0;
PC = address (TRUE) PC = address (FALSE)
If FLAG<1> = 1; If FLAG<1> = 1;
PC = address (FALSE) PC = address (TRUE)

PIC18F6390/6490/8390/8490
BTG Bit Toggle f BOV Branch if Overflow
Syntax: BTG f, b {,a} Syntax: BOV n
0≤b<7
Operation: if Overflow bit is ‘1’,
a ∈ [0,1]
(PC) + 2 + 2n → PC
Operation: (f) → f
Status Affected: None Encoding: 1110 0100 nnnn nnnn
Encoding: 0111 bbba ffff ffff Description: If the Overflow bit is ‘1’, then the
Description: Bit ‘b’ in data memory location ‘f’ is program will branch.
inverted. The 2’s complement number ‘2n’ is
If ‘a’ is ‘0’, the Access Bank is selected. added to the PC. Since the PC will
If ‘a’ is ‘1’, the BSR is used to select the have incremented to fetch the next
GPR bank. instruction, the new address will be
If ‘a’ is ‘0’ and the extended instruction PC + 2 + 2n. This instruction is then a
set is enabled, this instruction operates two-cycle instruction.
in Indexed Literal Offset Addressing Words: 1
mode whenever f ≤ 95 (5Fh). See
Cycles: 1(2)
Bit-Oriented Instructions in Indexed Q Cycle Activity:
Literal Offset Mode” for details. If Jump:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1 Decode Read literal Process Write to PC
‘n’ Data
Q Cycle Activity:
No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
Decode Read Process Write
If No Jump:
register ‘f’ Data register ‘f’
Q1 Q2 Q3 Q4
Decode Read literal Process No
Example: BTG PORTC, 4, 0 ‘n’ Data operation
Before Instruction:
PORTC = 0111 0101 [75h]
Example: HERE BOV Jump
After Instruction:
PORTC = 0110 0101 [65h] Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;

PIC18F6390/6490/8390/8490
BZ Branch if Zero CALL Subroutine Call
Syntax: BZ n Syntax: CALL k {,s}
Operands: -128 ≤ n ≤ 127 Operands: 0 ≤ k ≤ 1048575
s ∈ [0,1]
Operation: if Zero bit is ‘1’,
(PC) + 2 + 2n → PC Operation: (PC) + 4 → TOS,
k → PC<20:1>;
if s = 1,
Encoding: 1110 0000 nnnn nnnn (W) → WS,
Description: If the Zero bit is ‘1’, then the program (STATUS) → STATUSS,
will branch. (BSR) → BSRS
The 2’s complement number ‘2n’ is Status Affected: None
added to the PC. Since the PC will have
Encoding:
incremented to fetch the next
1st word (k<7:0>) 1110 110s k7kkk kkkk0
instruction, the new address will be
2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8
PC + 2 + 2n. This instruction is then a
two-cycle instruction. Description: Subroutine call of entire 2-Mbyte
Words: 1 memory range. First, return address
(PC + 4) is pushed onto the return
Cycles: 1(2)
stack. If ‘s’ = 1, the W, STATUS and
Q Cycle Activity: BSR registers are also pushed into their
If Jump: respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
Q1 Q2 Q3 Q4
update occurs (default). Then, the
20-bit value ‘k’ is loaded into PC<20:1>.
‘n’ Data CALL is a two-cycle instruction.
No No No No
Words: 2
If No Jump: Cycles: 2
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read literal Process No Q1 Q2 Q3 Q4
‘n’ Data operation Decode Read literal Push PC to Read literal
‘k’<7:0>, stack ‘k’<19:8>,
Example: HERE BZ Jump Write to PC
No No No No
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1; Example: HERE CALL THERE,1
PC = address (Jump)
If Zero = 0; Before Instruction
PC = address (HERE + 2) PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS= STATUS

PIC18F6390/6490/8390/8490
CLRF Clear f CLRWDT Clear Watchdog Timer
Syntax: CLRF f {,a} Syntax: CLRWDT
Operands: 0 ≤ f ≤ 255 Operands: None
a ∈ [0,1]
Operation: 000h → WDT,
Operation: 000h → f, 000h → WDT postscaler,
1→Z 1 → TO,
Status Affected: Z 1 → PD
Status Affected: TO, PD
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified Encoding: 0000 0000 0000 0100
register. Description: CLRWDT instruction resets the
If ‘a’ is ‘0’, the Access Bank is selected. Watchdog Timer. It also resets the
If ‘a’ is ‘1’, the BSR is used to select the postscaler of the WDT. Status bits, TO
GPR bank. and PD, are set.
If ‘a’ is ‘0’ and the extended instruction Words: 1
set is enabled, this instruction operates Cycles: 1
mode whenever f ≤ 95 (5Fh). See Q Cycle Activity:
Section 24.2.3 “Byte-Oriented and Q1 Q2 Q3 Q4
Bit-Oriented Instructions in Indexed Decode No Process No
Literal Offset Mode” for details. operation Data operation
Words: 1
Cycles: 1 Example: CLRWDT
Q Cycle Activity: Before Instruction
Q1 Q2 Q3 Q4 WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO = 1
Example: CLRF FLAG_REG,1 PD = 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h

PIC18F6390/6490/8390/8490
COMF Complement f CPFSEQ Compare f with W, Skip if f = W
Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a}

d ∈ [0,1] a ∈ [0,1]
a ∈ [0,1] Operation: (f) – (W),
skip if (f) = (W)
Operation: (f) → dest
(unsigned comparison)
Description: The contents of register ‘f’ are Description: Compares the contents of data memory
complemented. If ‘d’ is ‘1’, the result is location ‘f’ to the contents of W by
stored in W. If ‘d’ is ‘0’, the result is performing an unsigned subtraction.
stored back in register ‘f’ (default).
If ‘f’ = W, then the fetched instruction is
If ‘a’ is ‘0’, the Access Bank is selected. discarded and a NOP is executed
If ‘a’ is ‘1’, the BSR is used to select the instead, making this a two-cycle
GPR bank. instruction.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’, the Access Bank is selected.
set is enabled, this instruction operates If ‘a’ is ‘0’, the BSR is used to select the
in Indexed Literal Offset Addressing GPR bank.
Words: 1 Section 24.2.3 “Byte-Oriented and
Cycles: 1 Bit-Oriented Instructions in Indexed
Q Cycle Activity:
Words: 1
Q1 Q2 Q3 Q4
Cycles: 1(2)
register ‘f’ Data destination Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Example: COMF REG, 0, 0
Q1 Q2 Q3 Q4
Before Instruction Decode Read Process No
REG = 13h register ‘f’ Data operation
After Instruction
If skip:
REG = 13h
W = ECh Q1 Q2 Q3 Q4
No No No No
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
No No No No
Example: HERE CPFSEQ REG, 0

NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W = ?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG ≠ W;
PC = Address (NEQUAL)

PIC18F6390/6490/8390/8490
CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
a ∈ [0,1] a ∈ [0,1]
Operation: (f) − (W), Operation: (f) – (W),
skip if (f) > (W)
skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by Description: Compares the contents of data memory
performing an unsigned subtraction. location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched If the contents of ‘f’ are less than the
instruction is discarded and a NOP is contents of W, then the fetched
executed instead, making this a instruction is discarded and a NOP is
two-cycle instruction. executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘0’, the Access Bank is selected.
GPR bank. If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
set is enabled, this instruction operates Words: 1
in Indexed Literal Offset Addressing Cycles: 1(2)
Note: 3 cycles if skip and followed
Literal Offset Mode” for details. Q Cycle Activity:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1(2) Decode Read Process No
register ‘f’ Data operation
by a 2-word instruction. If skip:
Q1 Q2 Q3 Q4
Q Cycle Activity:
Decode Read Process No operation operation operation operation
register ‘f’ Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No Example: HERE CPFSLT REG, 1
operation operation operation operation NLESS :
No No No No LESS :
Before Instruction
PC = Address (HERE)
Example: HERE CPFSGT REG, 0 W = ?
NGREATER : After Instruction
GREATER : If REG < W;
Before Instruction PC = Address (LESS)
PC = Address (HERE) If REG ≥ W;
W = ? PC = Address (NLESS)
After Instruction
If REG > W;
PC = Address (GREATER)
If REG ≤ W;
PC = Address (NGREATER)

PIC18F6390/6490/8390/8490
DAW Decimal Adjust W Register DECF Decrement f
Syntax: DAW Syntax: DECF f {,d {,a}}
Operands: None Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
Operation: If [W<3:0> >9] or [DC = 1] then,
a ∈ [0,1]
(W<3:0>) + 6 → W<3:0>;
else, Operation: (f) – 1 → dest
(W<3:0>) → W<3:0>;
Status Affected: C, DC, N, OV, Z
If [W<7:4> >9] or [C = 1] then, Encoding: 0000 01da ffff ffff

(W<7:4>) + 6 → W<7:4>, Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
C = 1; result is stored in W. If ‘d’ is ‘1’, the
else, result is stored back in register ‘f’
(W<7:4>) → W<7:4> (default).
Status Affected: C If ‘a’ is ‘0’, the Access Bank is selected.
Encoding: 0000 0000 0000 0111 If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Description: DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words: 1 Bit-Oriented Instructions in Indexed
Cycles: 1
Q Cycle Activity: Words: 1
Q1 Q2 Q3 Q4 Cycles: 1
Decode Read Process Write Q Cycle Activity:
register W Data W Q1 Q2 Q3 Q4
Example 1: Decode Read Process Write to
DAW register ‘f’ Data destination
Before Instruction
W = A5h Example: DECF CNT, 1, 0
C = 0
DC = 0 Before Instruction
After Instruction CNT = 01h
W = 05h Z = 0
C = 1 After Instruction
DC = 0 CNT = 00h
Example 2: Z = 1
Before Instruction
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0

PIC18F6390/6490/8390/8490
DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0
Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}}
d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f) – 1 → dest, Operation: (f) – 1 → dest,
skip if result = 0 skip if result ≠ 0
Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default). placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction If the result is not ‘0’, the next
which is already fetched is discarded instruction which is already fetched is
and a NOP is executed instead, making discarded and a NOP is executed
it a two-cycle instruction. instead, making it a two-cycle
If ‘a’ is ‘0’, the Access Bank is selected. instruction.
If ‘a’ is ‘0’ and the extended instruction GPR bank.
set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing
Section 24.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See
Bit-Oriented Instructions in Indexed Section 24.2.3 “Byte-Oriented and
Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed
Words: 1 Literal Offset Mode” for details.
Cycles: 1(2) Words: 1
Note: 3 cycles if skip and followed Cycles: 1(2)

by a 2-word instruction. Note: 3 cycles if skip and followed
Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register ‘f’ Data destination Decode Read Process Write to
If skip: register ‘f’ Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
No No No No operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT – 1 After Instruction
If CNT = 0; TEMP = TEMP – 1,
PC = Address (CONTINUE) If TEMP = 0;
If CNT ≠ 0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP ≠ 0;
PC = Address (NZERO)

PIC18F6390/6490/8390/8490
GOTO Unconditional Branch INCF Increment f
Syntax: GOTO k Syntax: INCF f {,d {,a}}
d ∈ [0,1]
Operation: k → PC<20:1>
a ∈ [0,1]
Operation: (f) + 1 → dest
Encoding:
Status Affected: C, DC, N, OV, Z
1st word (k<7:0>) 1110 1111 k7kkk kkkk0
1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff
2nd word(k<19:8>)
Description: The contents of register ‘f’ are
Description: GOTO allows an unconditional branch
incremented. If ‘d’ is ‘0’, the result is
anywhere within entire
placed in W. If ‘d’ is ‘1’, the result is
2-Mbyte memory range. The 20-bit
placed back in register ‘f’ (default).
value ‘k’ is loaded into PC<20:1>.
GOTO is always a two-cycle If ‘a’ is ‘0’, the Access Bank is selected.
instruction. If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words: 2
Cycles: 2 set is enabled, this instruction operates
Q Cycle Activity: in Indexed Literal Offset Addressing
Q1 Q2 Q3 Q4
Decode Read literal No Read literal Bit-Oriented Instructions in Indexed
‘k’<7:0>, operation ‘k’<19:8>, Literal Offset Mode” for details.
Write to PC
Words: 1
No No No No
operation operation operation operation Cycles: 1
Q Cycle Activity:
Example: GOTO THERE Q1 Q2 Q3 Q4
After Instruction Decode Read Process Write to
PC = Address (THERE) register ‘f’ Data destination
Example: INCF CNT, 1, 0

Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?
After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1

PIC18F6390/6490/8390/8490
INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if not 0
Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}}

d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f) + 1 → dest, Operation: (f) + 1 → dest,

skip if result ≠ 0
skip if result = 0
Description: The contents of register ‘f’ are
Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is
incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is
placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).
If the result is not ‘0’, the next
If the result is ‘0’, the next instruction instruction which is already fetched is
which is already fetched is discarded discarded and a NOP is executed
and a NOP is executed instead, making instead, making it a two-cycle
it a two-cycle instruction. instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the If ‘a’ is ‘1’, the BSR is used to select the
GPR bank. GPR bank.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates set is enabled, this instruction operates
in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details. Literal Offset Mode” for details.
Words: 1 Words: 1
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
register ‘f’ Data destination register ‘f’ Data destination
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0

NZERO : ZERO
ZERO : NZERO
PC = Address (HERE) PC = Address (HERE)
CNT = CNT + 1 REG = REG + 1
If CNT = 0; If REG ≠ 0;
PC = Address (ZERO) PC = Address (NZERO)
If CNT ≠ 0; If REG = 0;
PC = Address (NZERO) PC = Address (ZERO)

PIC18F6390/6490/8390/8490
IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f
Syntax: IORLW k Syntax: IORWF f {,d {,a}}
d ∈ [0,1]
Operation: (W) .OR. k → W
a ∈ [0,1]
Operation: (W) .OR. (f) → dest
Description: The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W. Description: Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
Words: 1
the result is placed back in register ‘f’
Cycles: 1 (default).
GPR bank.
Example: IORLW 35h mode whenever f ≤ 95 (5Fh). See
Before Instruction Section 24.2.3 “Byte-Oriented and
W = 9Ah Bit-Oriented Instructions in Indexed
After Instruction Literal Offset Mode” for details.
W = BFh Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: IORWF RESULT, 0, 1

Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h

PIC18F6390/6490/8390/8490
LFSR Load FSR MOVF Move f
Syntax: LFSR f, k Syntax: MOVF f {,d {,a}}
Operands: 0≤f≤2 Operands: 0 ≤ f ≤ 255
0 ≤ k ≤ 4095 d ∈ [0,1]
a ∈ [0,1]
Operation: k → FSRf
Operation: f → dest
Encoding: 1110 1110 00ff Status Affected: N, Z
k11kkk
1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff
Description: The 12-bit literal ‘k’ is loaded into the Description: The contents of register ‘f’ are moved to
file select register pointed to by ‘f’. a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
Words: 2
placed in W. If ‘d’ is ‘1’, the result is
Cycles: 2 placed back in register ‘f’ (default).
Q Cycle Activity: Location ‘f’ can be anywhere in the
256-byte bank.
Q1 Q2 Q3 Q4
Decode Read literal Process Write
‘k’ MSB Data literal ‘k’
GPR bank.
MSB to
FSRfH If ‘a’ is ‘0’ and the extended instruction
Decode Read literal Process Write literal
‘k’ LSB Data ‘k’ to FSRfL
Example: LFSR 2, 3ABh Bit-Oriented Instructions in Indexed
After Instruction
FSR2H = 03h Words: 1
FSR2L = ABh
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write W
register ‘f’ Data
Example: MOVF REG, 0, 0

Before Instruction
REG = 22h
W = FFh
After Instruction
REG = 22h
W = 22h

PIC18F6390/6490/8390/8490
MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR
Syntax: MOVFF fs,fd Syntax: MOVLW k
Operands: 0 ≤ fs ≤ 4095 Operands: 0 ≤ k ≤ 255
0 ≤ fd ≤ 4095
Operation: k → BSR
Operation: (fs) → fd Status Affected: None
Status Affected: None Encoding: 0000 0001 kkkk kkkk
Encoding:
Description: The eight-bit literal ‘k’ is loaded into the
1st word (source) 1100 ffff ffff ffffs Bank Select Register (BSR). The value
2nd word (destin.) 1111 ffff ffff ffffd of BSR<7:4> always remains ‘0’,
regardless of the value of k7:k4.
Description: The contents of source register ‘fs’ are
moved to destination register ‘fd’. Words: 1
Location of source ‘fs’ can be anywhere
Cycles: 1
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’ Q Cycle Activity:
can also be anywhere from 000h to Q1 Q2 Q3 Q4
FFFh. Decode Read Process Write literal
Either source or destination can be W literal ‘k’ Data ‘k’ to BSR
(a useful special situation).
MOVFF is particularly useful for Example: MOVLB 5
transferring a data memory location to a
peripheral register (such as the transmit Before Instruction
buffer or an I/O port). BSR Register = 02h
After Instruction
The MOVFF instruction cannot use the
BSR Register = 05h
PCL, TOSU, TOSH or TOSL as the
destination register
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
(src)
Decode No No Write
operation operation register ‘f’
No dummy (dest)
read
Example: MOVFF REG1, REG2

Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h

PIC18F6390/6490/8390/8490
MOVLW Move Literal to W MOVWF Move W to f
Syntax: MOVLW k Syntax: MOVWF f {,a}
a ∈ [0,1]
Operation: k→W
Operation: (W) → f
Encoding: 0000 1110 kkkk kkkk Status Affected: None
Description: The eight-bit literal ‘k’ is loaded into W.
Words: 1 Description: Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
Cycles: 1 256-byte bank.
GPR bank.
Example: MOVLW 5Ah mode whenever f ≤ 95 (5Fh). See
After Instruction Section 24.2.3 “Byte-Oriented and
W = 5Ah Bit-Oriented Instructions in Indexed
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: MOVWF REG, 0

Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh

PIC18F6390/6490/8390/8490
MULLW Multiply Literal with W MULWF Multiply W with f
Syntax: MULLW k Syntax: MULWF f {,a}
a ∈ [0,1]
Operation: (W) x k → PRODH:PRODL
Operation: (W) x (f) → PRODH:PRODL
Description: An unsigned multiplication is carried
out between the contents of W and the Description: An unsigned multiplication is carried
8-bit literal ‘k’. The 16-bit result is out between the contents of W and the
placed in the PRODH:PRODL register register file location ‘f’. The 16-bit
pair. PRODH contains the high byte. result is stored in the PRODH:PRODL
W is unchanged. register pair. PRODH contains the
high byte. Both W and ‘f’ are
None of the Status flags are affected.
unchanged.
Note that neither Overflow nor Carry is
None of the Status flags are affected.
possible in this operation. A Zero result
is possible but not detected. Note that neither Overflow nor Carry is
possible in this operation. A Zero
Words: 1
result is possible but not detected.
Cycles: 1 If ‘a’ is ‘0’, the Access Bank is
Q Cycle Activity: selected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank.
Q1 Q2 Q3 Q4
If ‘a’ is ‘0’ and the extended
instruction set is enabled, this
literal ‘k’ Data registers
instruction operates in Indexed Literal
PRODH:
Offset Addressing mode whenever
PRODL
f ≤ 95 (5Fh). See Section 24.2.3
“Byte-Oriented and Bit-Oriented
Example: MULLW 0C4h Instructions in Indexed Literal Offset
Mode” for details.
Before Instruction
W = E2h Words: 1
PRODH = ?
PRODL = ? Cycles: 1
After Instruction Q Cycle Activity:
W = E2h
PRODH = ADh Q1 Q2 Q3 Q4
PRODL = 08h Decode Read Process Write
register ‘f’ Data registers
PRODH:
PRODL
Example: MULWF REG, 1

Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h

PIC18F6390/6490/8390/8490
NEGF Negate f NOP No Operation
Syntax: NEGF f {,a} Syntax: NOP
Operands: 0 ≤ f ≤ 255 Operands: None
a ∈ [0,1]
Operation: No operation
Operation: (f) + 1 → f
Status Affected: N, OV, C, DC, Z Encoding: 0000 0000 0000 0000
Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx
Description: Location ‘f’ is negated using two’s Description: No operation.
complement. The result is placed in the
Words: 1
data memory location ‘f’.
Cycles: 1
If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity:
GPR bank. Q1 Q2 Q3 Q4
If ‘a’ is ‘0’ and the extended instruction Decode No No No
set is enabled, this instruction operates operation operation operation
Section 24.2.3 “Byte-Oriented and Example:
Bit-Oriented Instructions in Indexed None.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: NEGF REG, 1

Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]

PIC18F6390/6490/8390/8490
POP Pop Top of Return Stack PUSH Push Top of Return Stack
Syntax: POP Syntax: PUSH
Operands: None Operands: None
Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of
stack and is discarded. The TOS value the return stack. The previous TOS
then becomes the previous value that value is pushed down on the stack.
was pushed onto the return stack. This instruction allows implementing a
This instruction is provided to enable software stack by modifying TOS and
the user to properly manage the return then pushing it onto the return stack.
stack to incorporate a software stack.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode PUSH No No
Decode No POP TOS No PC + 2 onto operation operation
operation value operation return stack
Example: POP Example: PUSH

GOTO NEW
Before Instruction
Before Instruction TOS = 345Ah
TOS = 0031A2h PC = 0124h
Stack (1 level down) = 014332h
After Instruction
After Instruction PC = 0126h
TOS = 014332h TOS = 0126h
PC = NEW Stack (1 level down) = 345Ah

PIC18F6390/6490/8390/8490
RCALL Relative Call RESET Reset
Syntax: RCALL n Syntax: RESET
Operands: -1024 ≤ n ≤ 1023 Operands: None
Operation: (PC) + 2 → TOS, Operation: Reset all registers and flags that are
(PC) + 2 + 2n → PC affected by a MCLR Reset.
Status Affected: None Status Affected: All
Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111
Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to
from the current location. First, return execute a MCLR Reset in software.
address (PC + 2) is pushed onto the
Words: 1
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will Cycles: 1
have incremented to fetch the next Q Cycle Activity:
instruction, the new address will be
Q1 Q2 Q3 Q4
PC + 2 + 2n. This instruction is a
two-cycle instruction. Decode Start No No
Reset operation operation
Words: 1
Cycles: 2
Example: RESET
Q Cycle Activity:
After Instruction
Q1 Q2 Q3 Q4 Registers = Reset Value
Decode Read literal Process Write to PC Flags* = Reset Value
‘n’ Data
PUSH PC to
stack
No No No No
Example: HERE RCALL Jump

Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)

PIC18F6390/6490/8390/8490
RETFIE Return from Interrupt RETLW Return Literal to W
Syntax: RETFIE {s} Syntax: RETLW k
Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255
Operation: (TOS) → PC, Operation: k → W,
1 → GIE/GIEH or PEIE/GIEL; (TOS) → PC,
if s = 1, PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR, Encoding: 0000 1100 kkkk kkkk
PCLATU, PCLATH are unchanged Description: W is loaded with the eight-bit literal ‘k’.
Status Affected: GIE/GIEH, PEIE/GIEL. The program counter is loaded from the
top of the stack (the return address).
Encoding: 0000 0000 0001 000s The high address latch (PCLATH)
Description: Return from Interrupt. Stack is popped remains unchanged.
and Top-of-Stack (TOS) is loaded into
Words: 1
the PC. Interrupts are enabled by
setting either the high or low-priority Cycles: 2
global interrupt enable bit. If ‘s’ = 1, the Q Cycle Activity:
contents of the shadow registers, WS,
Q1 Q2 Q3 Q4
STATUSS and BSRS, are loaded into
their corresponding registers, W, Decode Read Process POP PC
STATUS and BSR. If ‘s’ = 0, no update literal ‘k’ Data from stack,
of these registers occurs (default). Write to W
No No No No
Words: 1
Cycles: 2
Q Cycle Activity: Example:
Q1 Q2 Q3 Q4 CALL TABLE ; W contains table
Decode No No POP PC ; offset value
operation operation from stack ; W now has
Set GIEH or ; table value
GIEL :
TABLE
No No No No
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
Example: RETFIE 1 :
After Interrupt :
RETLW kn ; End of table
PC = TOS
W = WS Before Instruction
BSR = BSRS
W = 07h
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL = 1 After Instruction
W = value of kn

PIC18F6390/6490/8390/8490
RETURN Return from Subroutine RLCF Rotate Left f through Carry
Syntax: RETURN {s} Syntax: RLCF f {,d {,a}}
Operands: s ∈ [0,1] Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
Operation: (TOS) → PC;
a ∈ [0,1]
if s = 1,
(WS) → W, Operation: (f<n>) → dest<n + 1>,
(STATUSS) → STATUS, (f<7>) → C,
(BSRS) → BSR, (C) → dest<0>
PCLATU, PCLATH are unchanged
Status Affected: C, N, Z
Encoding: 0000 0000 0001 001s Description: The contents of register ‘f’ are rotated
Description: Return from subroutine. The stack is one bit to the left through the Carry
popped and the top of the stack (TOS) flag. If ‘d’ is ‘0’, the result is placed in
is loaded into the program counter. If W. If ‘d’ is ‘1’, the result is stored back
‘s’= 1, the contents of the shadow in register ‘f’ (default).
registers, WS, STATUSS and BSRS, If ‘a’ is ‘0’, the Access Bank is
are loaded into their corresponding selected. If ‘a’ is ‘1’, the BSR is used to
registers, W, STATUS and BSR. If select the GPR bank.
‘s’ = 0, no update of these registers
occurs (default).
set is enabled, this instruction
Words: 1 operates in Indexed Literal Offset
Addressing mode whenever
Cycles: 2
f ≤ 95 (5Fh). See Section 24.2.3
Q Cycle Activity: “Byte-Oriented and Bit-Oriented
Q1 Q2 Q3 Q4 Instructions in Indexed Literal Offset
Decode No Process POP PC Mode” for details.
operation Data from stack C register f
No No No No
operation operation operation operation Words: 1
Cycles: 1
Q Cycle Activity:
Example: RETURN
Q1 Q2 Q3 Q4
After Interrupt
PC = TOS
Example: RLCF REG, 0, 0

Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1

PIC18F6390/6490/8390/8490
RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry
Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}}
d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f<n>) → dest<n + 1>, Operation: (f<n>) → dest<n – 1>,
(f<7>) → dest<0> (f<0>) → C,
Status Affected: N, Z (C) → dest<7>
Status Affected: C, N, Z
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result Description: The contents of register ‘f’ are rotated
is placed in W. If ‘d’ is ‘1’, the result is one bit to the right through the Carry
stored back in register ‘f’ (default). flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘d’ is ‘1’, the result is placed back in
If ‘a’ is ‘1’, the BSR is used to select the register ‘f’ (default).
GPR bank. If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘0’ and the extended instruction If ‘a’ is ‘1’, the BSR is used to select the
set is enabled, this instruction operates GPR bank.
in Indexed Literal Offset Addressing If ‘a’ is ‘0’ and the extended instruction
mode whenever f ≤ 95 (5Fh). See set is enabled, this instruction operates
Section 24.2.3 “Byte-Oriented and in Indexed Literal Offset Addressing
Bit-Oriented Instructions in Indexed mode whenever f ≤ 95 (5Fh). See
Literal Offset Mode” for details. Section 24.2.3 “Byte-Oriented and
register f
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Example: RLNCF REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0

PIC18F6390/6490/8390/8490
RRNCF Rotate Right f (No Carry) SETF Set f
Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a}
d ∈ [0,1] a ∈ [0,1]
a ∈ [0,1]
Operation: FFh → f
Operation: (f<n>) → dest<n – 1>,
(f<0>) → dest<7>
Description: The contents of the specified register
are set to FFh.
Description: The contents of register ‘f’ are rotated If ‘a’ is ‘0’, the Access Bank is selected.
one bit to the right. If ‘d’ is ‘0’, the result If ‘a’ is ‘1’, the BSR is used to select the
is placed in W. If ‘d’ is ‘1’, the result is GPR bank.
If ‘a’ is ‘0’, the Access Bank will be set is enabled, this instruction operates
selected, overriding the BSR value. If ‘a’ in Indexed Literal Offset Addressing
is ‘1’, then the bank will be selected as mode whenever f ≤ 95 (5Fh). See
per the BSR value. Section 24.2.3 “Byte-Oriented and
If ‘a’ is ‘0’ and the extended instruction Bit-Oriented Instructions in Indexed
set is enabled, this instruction operates Literal Offset Mode” for details.
in Indexed Literal Offset Addressing Words: 1
Section 24.2.3 “Byte-Oriented and Cycles: 1
Bit-Oriented Instructions in Indexed Q Cycle Activity:
Q1 Q2 Q3 Q4
register f Decode Read Process Write
Words: 1
Cycles: 1 Example: SETF REG,1
Q Cycle Activity: Before Instruction
Q1 Q2 Q3 Q4 REG = 5Ah
After Instruction
REG = FFh
Example 1: RRNCF REG, 1, 0

Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0

Before Instruction
W = ?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111

PIC18F6390/6490/8390/8490
SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow
Syntax: SLEEP Syntax: SUBFWB f {,d {,a}}
Operands: None Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
Operation: 00h → WDT,
a ∈ [0,1]
0 → WDT postscaler,
1 → TO, Operation: (W) – (f) – (C) → dest
0 → PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011 Description: Subtract register ‘f’ and Carry flag
Description: The Power-Down status bit (PD) is (borrow) from W (2’s complement
cleared. The Time-out status bit (TO) method). If ‘d’ is ‘0’, the result is stored
is set. Watchdog Timer and its in W. If ‘d’ is ‘1’, the result is stored in
postscaler are cleared. register ‘f’ (default).
The processor is put into Sleep mode If ‘a’ is ‘0’, the Access Bank is selected.
with the oscillator stopped. If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words: 1
Cycles: 1
Q Cycle Activity: in Indexed Literal Offset Addressing
Q1 Q2 Q3 Q4 mode whenever f ≤ 95 (5Fh). See
Decode No Process Go to
operation Data Sleep
Words: 1
Example: SLEEP
Cycles: 1
Before Instruction
TO = ? Q Cycle Activity:
PD = ? Q1 Q2 Q3 Q4
After Instruction Decode Read Process Write to
TO = 1† register ‘f’ Data destination
PD = 0
Example 1: SUBFWB REG, 1, 0
Before Instruction
† If WDT causes wake-up, this bit is cleared.
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0

PIC18F6390/6490/8390/8490
SUBLW Subtract W from Literal SUBWF Subtract W from f
Syntax: SUBLW k Syntax: SUBWF f {,d {,a}}
d ∈ [0,1]
Operation: k – (W) → W
a ∈ [0,1]
Operation: (f) – (W) → dest
Description: W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Words: 1 Description: Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
Cycles: 1 result is stored in W. If ‘d’ is ‘1’, the
Q Cycle Activity: result is stored back in register ‘f’
(default).
Q1 Q2 Q3 Q4
literal ‘k’ Data
GPR bank.
Example 1: SUBLW 02h If ‘a’ is ‘0’ and the extended instruction
Before Instruction
W = 01h in Indexed Literal Offset Addressing
C = ? mode whenever f ≤ 95 (5Fh). See
After Instruction Section 24.2.3 “Byte-Oriented and
W = 01h Bit-Oriented Instructions in Indexed
C = 1 ; result is positive Literal Offset Mode” for details.
Z = 0
N = 0 Words: 1
Example 2: SUBLW 02h Cycles: 1
Before Instruction Q Cycle Activity:

W = 02h Q1 Q2 Q3 Q4
C = ?
After Instruction
W = 00h
C = 1 ; result is zero Example 1: SUBWF REG, 1, 0
Z = 1
N = 0 Before Instruction
REG = 3
Example 3: SUBLW 02h W = 2
Before Instruction C = ?
W = 03h After Instruction
C = ? REG = 1
After Instruction W = 2
C = 1 ; result is positive
W = FFh; (2’s complement) Z = 0
C = 0 ; result is negative N = 0
Z = 0
N = 1 Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W = 2
C = ?
After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W = 2
C = ?
After Instruction
REG = FFh ;(2’s complement)
W = 2
C = 0 ; result is negative
Z = 0
N = 1

PIC18F6390/6490/8390/8490
SUBWFB Subtract W from f with Borrow SWAPF Swap f
Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}}
d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>,
Status Affected: N, OV, C, DC, Z (f<7:4>) → dest<3:0>
Encoding: 0101 10da ffff ffff Status Affected: None
Description: Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored Description: The upper and lower nibbles of register
in W. If ‘d’ is ‘1’, the result is stored back ‘f’ are exchanged. If ‘d’ is ‘0’, the result
in register ‘f’ (default). is placed in W. If ‘d’ is ‘1’, the result is
If ‘a’ is ‘0’, the Access Bank is selected. placed in register ‘f’ (default).
If ‘a’ is ‘0’ and the extended instruction GPR bank.
set is enabled, this instruction operates If ‘a’ is ‘0’ and the extended instruction
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f ≤ 95 (5Fh). See in Indexed Literal Offset Addressing
Section 24.2.3 “Byte-Oriented and mode whenever f ≤ 95 (5Fh). See
Bit-Oriented Instructions in Indexed Section 24.2.3 “Byte-Oriented and
Literal Offset Mode” for details. Bit-Oriented Instructions in Indexed
Words: 1
Cycles: 1 Words: 1
Q Cycle Activity: Cycles: 1

Decode Read Process Write to Q1 Q2 Q3 Q4
Example 1: SUBWFB REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 19h (0001 1001) Example: SWAPF REG, 1, 0
W = 0Dh (0000 1101)
C = 1 Before Instruction
After Instruction REG = 53h
REG = 0Ch (0000 1011) After Instruction
W = 0Dh (0000 1101) REG = 35h
C = 1
Z = 0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1101)
C = 1
After Instruction
REG = F5h (1111 0100)
; [2’s comp]
W = 0Eh (0000 1101)
C = 0
Z = 0
N = 1 ; result is negative

PIC18F6390/6490/8390/8490
TBLRD Table Read TBLRD Table Read (Continued)
Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD *+ ;
Operands: None Before Instruction
TABLAT = 55h
Operation: if TBLRD *,
TBLPTR = 00A356h
(Prog Mem (TBLPTR)) → TABLAT, MEMORY(00A356h) = 34h
TBLPTR – No Change; After Instruction
if TBLRD *+, TABLAT = 34h
(Prog Mem (TBLPTR)) → TABLAT, TBLPTR = 00A357h
(TBLPTR) + 1 → TBLPTR;
Example 2: TBLRD +* ;
if TBLRD *-,
(Prog Mem (TBLPTR)) → TABLAT, Before Instruction
(TBLPTR) – 1 → TBLPTR; TABLAT = 0AAh
TBLPTR = 01A357h
if TBLRD +*,
MEMORY(01A357h) = 12h
(TBLPTR) + 1 → TBLPTR, MEMORY(01A358h) = 34h
(Prog Mem (TBLPTR)) → TABLAT After Instruction
Status Affected: None TABLAT = 34h
TBLPTR = 01A358h
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer, called Table
Pointer (TBLPTR), is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR<0> = 0: Least Significant Byte of
Program Memory Word
TBLPTR<0> = 1: Most Significant Byte of
Program Memory Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No operation No No operation
operation (Read Program operation (Write
Memory) TABLAT)

PIC18F6390/6490/8390/8490
TBLWT Table Write TBLWT Table Write (Continued)
Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+;
Operands: None
Before Instruction
Operation: if TBLWT*, TABLAT = 55h
(TABLAT) → Holding Register, TBLPTR = 00A356h
TBLPTR – No Change; HOLDING REGISTER
(00A356h) = FFh
if TBLWT*+,
After Instructions (table write completion)
(TABLAT) → Holding Register,
TABLAT = 55h
(TBLPTR) + 1 → TBLPTR; TBLPTR = 00A357h
if TBLWT*-, HOLDING REGISTER
(TABLAT) → Holding Register, (00A356h) = 55h
(TBLPTR) – 1 → TBLPTR; Example 2: TBLWT +*;
if TBLWT+*,
(TBLPTR) + 1 → TBLPTR, Before Instruction
TABLAT = 34h
(TABLAT) → Holding Register TBLPTR = 01389Ah
Status Affected: None HOLDING REGISTER
(01389Ah) = FFh
Encoding: 0000 0000 0000 11nn HOLDING REGISTER
nn=0 * (01389Bh) = FFh
=1 *+ After Instruction (table write completion)
=2 *- TABLAT = 34h
=3 +* TBLPTR = 01389Bh
HOLDING REGISTER
Description: This instruction uses the 3 LSBs of the (01389Ah) = FFh
TBLPTR to determine which of the HOLDING REGISTER
8 holding registers the TABLAT is written to. (01389Bh) = 34h
The holding registers are used to program
the contents of Program Memory (P.M.).
(Refer to Section 6.0 “Flash Program
Note: The table write (TBLWT) instructions are
Memory” for additional details on not available in user mode in
programming Flash memory.) PIC18F6X90/8X90 devices, as these
The TBLPTR (a 21-bit pointer) points to devices are standard Flash parts without
each byte in the program memory. TBLPTR an external bus interface.
has a 2-MBtye address range. The LSb of
the TBLPTR selects which byte of the
program memory location to access.
TBLPTR<0> = 0: Least Significant Byte
of Program Memory
Word
TBLPTR<0> = 1: Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No No No
(Read (Write to
TABLAT) Holding
Register )

PIC18F6390/6490/8390/8490
TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W
Syntax: TSTFSZ f {,a} Syntax: XORLW k
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ k ≤ 255
a ∈ [0,1]
Operation: (W) .XOR. k → W
Operation: skip if f = 0
Status Affected: None Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XORed with
Description: If ‘f’ = 0, the next instruction fetched the 8-bit literal ‘k’. The result is placed
during the current instruction execution in W.
is discarded and a NOP is executed, Words: 1
making this a two-cycle instruction.
Cycles: 1
If ‘a’ is ‘1’, the BSR is used to select the Q Cycle Activity:
GPR bank. Q1 Q2 Q3 Q4
If ‘a’ is ‘0’ and the extended instruction Decode Read Process Write to W
set is enabled, this instruction operates literal ‘k’ Data
Section 24.2.3 “Byte-Oriented and Example: XORLW 0AFh
Bit-Oriented Instructions in Indexed Before Instruction
Literal Offset Mode” for details. W = B5h
Words: 1 After Instruction
W = 1Ah
Cycles: 1(2)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
If skip:
Q1 Q2 Q3 Q4
No No No No
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
No No No No
Example: HERE TSTFSZ CNT, 1

NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT ≠ 00h,
PC = Address (NZERO)

PIC18F6390/6490/8390/8490
XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}
Operands: 0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) .XOR. (f) → dest
Description: Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
GPR bank.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: XORWF REG, 1, 0

Before Instruction
REG = AFh
W = B5h
After Instruction
REG = 1Ah
W = B5h

PIC18F6390/6490/8390/8490
24.2 Extended Instruction Set A summary of the instructions in the extended instruc-
tion set is provided in Table 24-3. Detailed descriptions
In addition to the standard 75 instructions of the PIC18 are provided in Section 24.2.2 “Extended Instruction
instruction set, PIC18FXX90 devices also provide an Set”. The opcode field descriptions in Table 24-1 apply
optional extension to the core CPU functionality. The to both the standard and extended PIC18 instruction
added features include eight additional instructions that sets.
augment Indirect and Indexed Addressing operations
and the implementation of Indexed Literal Offset Note: The instruction set extension and the
Addressing mode for many of the standard PIC18 Indexed Literal Offset Addressing mode
instructions. were designed for optimizing applications
written in C; the user may likely never use
The additional features are disabled by default. To
these instructions directly in assembler.
enable them, users must set the XINST Configuration
The syntax for these commands is pro-
bit.
vided as a reference for users who may be
The instructions in the extended set can all be reviewing code that has been generated
classified as literal operations, which either manipulate by a compiler.
the File Select Registers or use them for Indexed
Addressing. Two of the instructions, ADDFSR and 24.2.1 EXTENDED INSTRUCTION SYNTAX
SUBFSR, each have an additional special instantiation
Most of the extended instructions use indexed argu-
for using FSR2. These versions (ADDULNK and
ments, using one of the File Select Registers and some
SUBULNK) allow for automatic return after execution.
offset to specify a source or destination register. When
The extended instructions are specifically implemented an argument for an instruction serves as part of
to optimize re-entrant program code (that is, code that Indexed Addressing, it is enclosed in square brackets
is recursive or that uses a software stack) written in (“[ ]”). This is done to indicate that the argument is used
high-level languages, particularly C. Among other as an index or offset. MPASM™ Assembler will flag an
things, they allow users working in high-level error if it determines that an index or offset value is not
languages to perform certain operations on data bracketed.
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
• dynamic allocation and deallocation of software are also used to indicate index arguments in byte-
stack space when entering and leaving oriented and bit-oriented instructions. This is in addition
subroutines to other changes in their syntax. For more details, see
• Function Pointer invocation Section 24.2.3.1 “Extended Instruction Syntax with
• Software Stack Pointer manipulation Standard PIC18 Commands”.
• manipulation of variables located in a software Note: In the past, square brackets have been
stack used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional arguments
are denoted by braces (“{ }”).
TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Description Cycles
ADDFSR f, k Add Literal to FSR 1 1110 1000 ffkk kkkk None

ADDULNK k Add Literal to FSR2 and Return 2 1110 1000 11kk kkkk None
CALLW Call Subroutine using WREG 2 0000 0000 0001 0100 None
MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None
zd (destination) 2nd word 1111 xxxx xzzz zzzz
PUSHL k Store Literal at FSR2, 1 1110 1010 kkkk kkkk None
Decrement FSR2
SUBFSR f, k Subtract Literal from FSR 1 1110 1001 ffkk kkkk None
SUBULNK k Subtract Literal from FSR2 and 2 1110 1001 11kk kkkk None
Return

PIC18F6390/6490/8390/8490
24.2.2 EXTENDED INSTRUCTION SET
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 + k → FSR2,
Operation: FSR(f) + k → FSR(f) PC = (TOS)
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
Cycles: 1 TOS.
Q Cycle Activity: The instruction takes two cycles to
execute; a NOP is performed during the
Q1 Q2 Q3 Q4
second cycle.
This may be thought of as a special case
literal ‘k’ Data FSR
of the ADDFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Words: 1
Example: ADDFSR 2, 23h
Cycles: 2
Before Instruction
FSR2 = 03FFh
Q Cycle Activity:
After Instruction
FSR2 = 0422h Q1 Q2 Q3 Q4
literal ‘k’ Data FSR
No No No No
Operation Operation Operation Operation
Example: ADDULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

PIC18F6390/6490/8390/8490
CALLW Subroutine Call Using WREG MOVSF Move Indexed to f

Syntax: CALLW Syntax: MOVSF [zs], fd
Operands: None Operands: 0 ≤ zs ≤ 127
0 ≤ fd ≤ 4095
Operation: (PC + 2) → TOS,
(W) → PCL, Operation: ((FSR2) + zs) → fd
(PCLATH) → PCH,
(PCLATU) → PCU
Encoding:
1st word (source) 1110 1011 0zzz zzzzs
Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd
Description First, the return address (PC + 2) is
Description: The contents of the source register are
pushed onto the return stack. Next, the
moved to destination register ‘fd’. The
contents of W are written to PCL; the
actual address of the source register is
existing value is discarded. Then, the
determined by adding the 7-bit literal
contents of PCLATH and PCLATU are
offset ‘zs’ in the first word to the value of
latched into PCH and PCU,
FSR2. The address of the destination
respectively. The second cycle is
register is specified by the 12-bit literal
executed as a NOP instruction while the
‘fd’ in the second word. Both addresses
new next instruction is fetched.
can be anywhere in the 4096-byte data
Unlike CALL, there is no option to space (000h to FFFh).
update W, STATUS or BSR.
The MOVSF instruction cannot use the
Words: 1 PCL, TOSU, TOSH or TOSL as the
Cycles: 2 destination register.
If the resultant source address points to
Q Cycle Activity:
an Indirect Addressing register, the
Q1 Q2 Q3 Q4 value returned will be 00h.
Decode Read Push PC to No Words: 2
WREG stack operation
Cycles: 2
No No No No
operation operation operation operation Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
Example: HERE CALLW
source addr source addr source reg
Before Instruction Decode No No Write
PC = address (HERE) operation operation register ‘f’
PCLATH = 10h
PCLATU = 00h No dummy (dest)
W = 06h read
After Instruction
PC = 001006h
TOS = address (HERE + 2) Example: MOVSF [05h], REG2
PCLATH = 10h
PCLATU = 00h Before Instruction
W = 06h FSR2 = 80h
Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h

PIC18F6390/6490/8390/8490
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 ≤ zs ≤ 127 Operands: 0 ≤ k ≤ 255
0 ≤ zd ≤ 127
Operation: k → (FSR2),
Operation: ((FSR2) + zs) → ((FSR2) + zd) FSR2 – 1→ FSR2
Encoding:
1st word (source) 1110 1011 1zzz zzzzs
1111 xxxx xzzz zzzzd Description: The 8-bit literal ‘k’ is written to the data
2nd word (dest.)
memory address specified by FSR2. FSR2 is
Description The contents of the source register are decremented by 1 after the operation.
moved to the destination register. The
This instruction allows users to push values
addresses of the source and destination
onto a software stack.
registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’, Words: 1
respectively, to the value of FSR2. Both Cycles: 1
registers can be located anywhere in
Q Cycle Activity:
the 4096-byte data memory space
(000h to FFFh). Q1 Q2 Q3 Q4
The MOVSS instruction cannot use the Decode Read ‘k’ Process Write to
PCL, TOSU, TOSH or TOSL as the data destination
destination register.
If the resultant source address points to
an Indirect Addressing register, the Example: PUSHL 08h
value returned will be 00h. If the Before Instruction
resultant destination address points to FSR2H:FSR2L = 01ECh
an Indirect Addressing register, the Memory (01ECh) = 00h
instruction will execute as a NOP.
After Instruction
Words: 2
FSR2H:FSR2L = 01EBh
Cycles: 2 Memory (01ECh) = 08h
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
Example: MOVSS [05h], [06h]

Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h

PIC18F6390/6490/8390/8490
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63
f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2,
Operation: FSRf – k → FSRf (TOS) → PC
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from Description: The 6-bit literal ‘k’ is subtracted from the
the contents of the FSR specified contents of the FSR2. A RETURN is then
by ‘f’. executed by loading the PC with the TOS.
Words: 1 The instruction takes two cycles to execute;
Cycles: 1 a NOP is performed during the second cycle.
Q Cycle Activity: This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
Q1 Q2 Q3 Q4
‘11’); it operates only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity:
Example: SUBFSR 2, 23h Q1 Q2 Q3 Q4
Before Instruction Decode Read Process Write to
FSR2 = 03FFh register ‘f’ Data destination
After Instruction No No No No
FSR2 = 03DCh Operation Operation Operation Operation
Example: SUBULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)

PIC18F6390/6490/8390/8490
24.2.3 BYTE-ORIENTED AND 24.2.3.1 Extended Instruction Syntax with
BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands
INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file
Note: Enabling the PIC18 instruction set register argument, ‘f’, in the standard byte-oriented and
extension may cause legacy applications bit-oriented commands is replaced with the literal offset
to behave erratically or fail entirely. value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
In addition to eight new commands in the extended set, it must be indicated by square brackets (“[ ]”). As with
enabling the extended instruction set also enables the extended instructions, the use of brackets indicates
Indexed Literal Offset Addressing mode (Section 5.6.1 to the compiler that the value is to be interpreted as an
“Indexed Addressing With Literal Offset”). This has index or an offset. Omitting the brackets, or using a
a significant impact on the way that many commands of value greater than 5Fh within brackets, will generate an
the standard PIC18 instruction set are interpreted. error in the MPASM™ Assembler.
When the extended set is disabled, addresses embed- If the index argument is properly bracketed for Indexed
ded in opcodes are treated as literal memory locations: Literal Offset Addressing, the Access RAM argument is
either as a location in the Access Bank (a = 0), or in a never specified; it will automatically be assumed to be
GPR bank designated by the BSR (a = 1). When the ‘0’. This is in contrast to standard operation (extended
extended instruction set is enabled and a = 0, however, instruction set disabled) when ‘a’ is set on the basis of
a file register argument of 5Fh or less is interpreted as the target address. Declaring the Access RAM bit in
an offset from the pointer value in FSR2 and not as a this mode will also generate an error in the MPASM
literal address. For practical purposes, this means that Assembler.
all instructions that use the Access RAM bit as an The destination argument, ‘d’, functions as before.
argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instructions In the latest versions of the MPASM Assembler,
– may behave differently when the extended instruction language support for the extended instruction set must
set is enabled. be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
When the content of FSR2 is 00h, the boundaries of the source listing.
Access RAM are essentially remapped to their original
values. This may be useful in creating backward 24.2.4 CONSIDERATIONS WHEN
compatible code. If this technique is used, it may be ENABLING THE EXTENDED
necessary to save the value of FSR2 and restore it
INSTRUCTION SET
when moving back and forth between ‘C’ and assembly
routines in order to preserve the Stack Pointer. Users It is important to note that the extensions to the instruc-
must also keep in mind the syntax requirements of the tion set may not be beneficial to all users. In particular,
extended instruction set (see Section 24.2.3.1 users who are not writing code that uses a software
“Extended Instruction Syntax with Standard PIC18 stack may not benefit from using the extensions to the
Commands”). instruction set.
Although the Indexed Literal Offset Addressing mode Additionally, the Indexed Literal Offset Addressing
can be very useful for dynamic stack and pointer mode may create issues with legacy applications
manipulation, it can also be very annoying if a simple written to the PIC18 assembler. This is because
arithmetic operation is carried out on the wrong instructions in the legacy code may attempt to address
register. Users who are accustomed to the PIC18 registers in the Access Bank below 5Fh. Since these
programming must keep in mind that, when the addresses are interpreted as literal offsets to FSR2
extended instruction set is enabled, register addresses when the instruction set extension is enabled, the
of 5Fh or less are used for Indexed Literal Offset application may read or write to the wrong data
Addressing. addresses.
Representative examples of typical byte-oriented and When porting an application to the PIC18FXX90, it is
bit-oriented instructions in the Indexed Literal Offset very important to consider the type of code. A large, re-
Addressing mode are provided on the following page to entrant application that is written in ‘C’ and would benefit
show how execution is affected. The operand from efficient compilation will do well when using the
conditions shown in the examples are applicable to all instruction set extensions. Legacy applications that
instructions of these types. heavily use the Access Bank will most likely not benefit
from using the extended instruction set.

PIC18F6390/6490/8390/8490
ADD W to Indexed Bit Set Indexed

ADDWF BSF
(Indexed Literal Offset mode) (Indexed Literal Offset mode)
Syntax: ADDWF [k] {,d} Syntax: BSF [k], b
d ∈ [0,1] 0≤b≤7
a=0 a=0
Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2 + k))
Status Affected: N, OV, C, DC, Z Status Affected: None
Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk
Description: The contents of W are added to the contents Description: Bit ‘b’ of the register indicated by FSR2,
of the register indicated by FSR2, offset by the offset by the value ‘k’, is set.
value ‘k’. Words: 1
If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’,
Cycles: 1
the result is stored back in register ‘f’ (default).
Q Cycle Activity:
Words: 1
Q1 Q2 Q3 Q4
Cycles: 1
Q Cycle Activity: register ‘f’ Data destination
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process Write to Example: BSF [FLAG_OFST], 7
Data destination Before Instruction
FLAG_OFST = 0Ah
Example: ADDWF [OFST] ,0 FSR2 = 0A00h
Contents
Before Instruction of 0A0Ah = 55h
W = 17h After Instruction
OFST = 2Ch Contents
FSR2 = 0A00h of 0A0Ah = D5h
Contents
of 0A2Ch = 20h
After Instruction
W = 37h
Contents
of 0A2Ch = 20h
Set Indexed
SETF
(Indexed Literal Offset mode)
Syntax: SETF [k]
Operands: 0 ≤ k ≤ 95
Operation: FFh → ((FSR2) + k)
Description: The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process Write
Data register
Example: SETF [OFST]

Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh

PIC18F6390/6490/8390/8490
24.2.5 SPECIAL CONSIDERATIONS WITH To develop software for the extended instruction set,
MICROCHIP MPLAB® IDE TOOLS the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
The latest versions of Microchip’s software tools have Depending on the environment being used, this may be
been designed to fully support the extended instruction done in several ways:
set of the PIC18FXX90 family of devices. This includes
the MPLAB C18 C compiler, MPASM assembly • A menu option, or dialog box within the
language and MPLAB Integrated Development environment, that allows the user to configure the
Environment (IDE). language tool and its settings for the project
• A command line option
When selecting a target device for software develop-
ment, MPLAB IDE will automatically set default Config- • A directive in the source code
uration bits for that device. The default setting for the These options vary between different compilers,
XINST Configuration bit is ‘0’, disabling the extended assemblers and development environments. Users are
instruction set and Indexed Literal Offset Addressing encouraged to review the documentation accompany-
mode. For proper execution of applications developed ing their development systems for the appropriate
to take advantage of the extended instruction set, information.
XINST must be set during programming.

PIC18FXX90
25.0 DEVELOPMENT SUPPORT 25.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers are supported with a full
range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
operating system-based application that contains:
• Assemblers/Compilers/Linkers
• A single graphical interface to all debugging tools
- MPASMTM Assembler
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- Programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - Emulator (sold separately)
- MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately)
• Simulators • A full-featured editor with color-coded context
- MPLAB SIM Software Simulator • A multiple project manager
• Emulators • Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
• High-level source code debugging
- MPLAB REAL ICE™ In-Circuit Emulator
• Visual device initializer for easy register
• In-Circuit Debugger
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
- PICSTART® Plus Development Programmer windows
- MPLAB PM3 Device Programmer • Extensive on-line help
- PICkit™ 2 Development Programmer • Integration of select third party tools, such as
• Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR
Boards and Evaluation Kits C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

PIC18FXX90
25.2 MPASM Assembler 25.5 MPLAB ASM30 Assembler, Linker
The MPASM Assembler is a full-featured, universal
and Librarian
macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable
The MPASM Assembler generates relocatable object machine code from symbolic assembly language for
files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the
files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler
reference, absolute LST files that contain source lines generates relocatable object files that can then be
and generated machine code and COFF files for archived or linked with other relocatable object files and
debugging. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler features include:
• Support for the entire dsPIC30F instruction set
• Integration into MPLAB IDE projects
• Support for fixed-point and floating-point data
• User-defined macros to streamline
assembly code • Command line interface
• Conditional assembly for multi-purpose • Rich directive set
source files • Flexible macro language
• Directives that allow complete control over the • MPLAB IDE compatibility
assembly process
25.6 MPLAB SIM Software Simulator
25.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code
C Compilers development in a PC-hosted environment by simulat-
The MPLAB C18 and MPLAB C30 Code Development ing the PIC MCUs and dsPIC® DSCs on an instruction
Systems are complete ANSI C compilers for level. On any given instruction, the data areas can be
Microchip’s PIC18 and PIC24 families of microcontrol- examined or modified and stimuli can be applied from
lers and the dsPIC30 and dsPIC33 family of digital sig- a comprehensive stimulus controller. Registers can be
nal controllers. These compilers provide powerful logged to files for further run-time analysis. The trace
integration capabilities, superior code optimization and buffer and logic analyzer display extend the power of
ease of use not found with other compilers. the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE The MPLAB SIM Software Simulator fully supports
debugger. symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
25.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside
MPLIB Object Librarian of the hardware laboratory environment, making it an
The MPLINK Object Linker combines relocatable excellent, economical software development tool.
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction

PIC18FXX90
25.7 MPLAB ICE 2000 25.9 MPLAB ICD 2 In-Circuit Debugger
High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low-cost, run-time development tool,
The MPLAB ICE 2000 In-Circuit Emulator is intended connecting to the host PC via an RS-232 or high-speed
to provide the product development engineer with a USB interface. This tool is based on the Flash PIC
complete microcontroller design tool set for PIC MCUs and can be used to develop for these and other
microcontrollers. Software control of the MPLAB ICE PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
2000 In-Circuit Emulator is advanced by the MPLAB the in-circuit debugging capability built into the Flash
Integrated Development Environment, which allows devices. This feature, along with Microchip’s In-Circuit
editing, building, downloading and source debugging Serial ProgrammingTM (ICSPTM) protocol, offers cost-
from a single environment. effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and
system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step-
ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and
the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables
different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB
ICE 2000 In-Circuit Emulator allows expansion to ICD 2 also serves as a development programmer for
support new PIC microcontrollers. selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with 25.10 MPLAB PM3 Device Programmer
advanced features that are typically found on more
expensive development tools. The PC platform and The MPLAB PM3 Device Programmer is a universal,
Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable
chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for
simple, unified application. maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
25.8 MPLAB REAL ICE In-Circuit
package types. The ICSP™ cable assembly is included
Emulator System as a standard item. In Stand-Alone mode, the MPLAB
MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program
Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set
Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3
programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable.
with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and
the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large
included with each kit. memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.

PIC18FXX90
25.11 PICSTART Plus Development 25.13 Demonstration, Development and
Programmer Evaluation Boards
The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and
easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC
connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func-
Integrated Development Environment software makes tional systems. Most boards include prototyping areas for
using the programmer simple and efficient. The adding custom circuitry and provide application firmware
PICSTART Plus Development Programmer supports and source code for examination and modification.
most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs,
Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232
PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional
The PICSTART Plus Development Programmer is CE EEPROM memory.
compliant.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
25.12 PICkit 2 Development Programmer
circuits and for learning about various microcontroller
The PICkit™ 2 Development Programmer is a low-cost applications.
programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon-
an easy-to-use interface for programming many of stration/development board series of circuits, Microchip
Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software
Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN,
includes a prototyping development board, twelve IrDA®, PowerSmart battery management, SEEVAL®
sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate
Lite C compiler, and is designed to help get up to speed sensing, plus many more.
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop Check the Microchip web page (www.microchip.com)
applications using Microchip’s powerful, mid-range for the complete list of demonstration, development
Flash memory family of microcontrollers. and evaluation kits.

PIC18F6390/6490/8390/8490
26.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RG5 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RG5 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC18F6390/6490/8390/8490
FIGURE 26-1: PIC18F6390/6490/8390/8490 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V PIC18FX390/X490
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
Frequency
FIGURE 26-2: PIC18LF6390/6490/8390/8490 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V PIC18LFX390/X490
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz 40 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.

PIC18F6390/6490/8390/8490
26.1 DC Characteristics: Supply Voltage
PIC18F6390/6490/8390/8490 (Industrial)
PIC18LF6390/6490/8390/8490 (Industrial)
PIC18LF6390/6490/8390/8490 Standard Operating Conditions (unless otherwise stated)
(Industrial) Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC18F6390/6490/8390/8490 Standard Operating Conditions (unless otherwise stated)
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
D001 VDD Supply Voltage
PIC18LF6390/6490/8390/8490 2.0 — 5.5 V HS, XT, RC and LP Oscillator modes
PIC18F6390/6490/8390/8490 4.2 — 5.5 V
D002 VDR RAM Data Retention 1.5 — — V
Voltage(1)
D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for
to Ensure Internal Power-on details
Reset Signal
D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for
to Ensure Internal Power-on details
Reset Signal
VBOR Brown-out Reset Voltage
D005 PIC18LF6390/6490/8390/8490
BORV1:BORV0 = 11 2.00 2.05 2.16 V
BORV1:BORV0 = 10 2.65 2.79 2.93 V
D005 All devices
BORV1:BORV0 = 01 4.11 4.33 4.55 V
BORV1:BORV0 = 00 4.36 4.59 4.82 V
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.

PIC18F6390/6490/8390/8490
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F6390/6490/8390/8490 (Industrial)
Param
Device Typ Max Units Conditions
No.
Power-Down Current (IPD)(1)

PIC18LF6390/6490/8390/8490 0.1 1 μA -40°C
VDD = 2.0V
0.1 1 μA +25°C
(Sleep mode)
0.2 5 μA +85°C
PIC18LF6390/6490/8390/8490 0.1 2 μA -40°C
VDD = 3.0V
0.1 2 μA +25°C
(Sleep mode)
0.3 8 μA +85°C
All devices 0.1 2.0 μA -40°C
VDD = 5.0V
0.1 2.0 μA +25°C
(Sleep mode)
0.4 15 μA +85°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that
add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;
MCLR = VDD; WDT enabled/disabled as specified.
3: Low-power Timer1 oscillator selected.
4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be
less than the sum of both specifications.

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
PIC18LF6390/6490/8390/8490 (Industrial) (Continued)
Param
No.
Supply Current (IDD)(2)

PIC18LF6390/6490/8390/8490 12 26 μA -40°C
12 24 μA +25°C VDD = 2.0V
12 23 μA +85°C
PIC18LF6390/6490/8390/8490 32 50 μA -40°C FOSC = 31 kHz
27 48 μA +25°C VDD = 3.0V (RC_RUN mode,
22 46 μA +85°C INTRC source)
All devices 84 134 μA -40°C
82 128 μA +25°C VDD = 5.0V
72 128 μA +85°C
PIC18LF6390/6490/8390/8490 .26 .8 mA -40°C
.26 .8 mA +25°C VDD = 2.0V
.26 .8 mA +85°C
PIC18LF6390/6490/8390/8490 .48 1.04 mA -40°C FOSC = 1 MHz
.44 .96 mA +25°C VDD = 3.0V (RC_RUN mode,
.48 .88 mA +85°C INTOSC source)
All devices .88 1.84 mA -40°C
.88 1.76 mA +25°C VDD = 5.0V
.8 1.68 mA +85°C

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.

PIC18LF6390/6490/8390/8490 0.6 1.7 mA -40°C
0.6 1.6 mA +25°C VDD = 2.0V
0.6 1.5 mA +85°C
PIC18LF6390/6490/8390/8490 1.0 2.4 mA -40°C FOSC = 4 MHz
1.0 2.4 mA +25°C VDD = 3.0V (RC_RUN mode,
1.0 2.4 mA +85°C INTOSC source)
All devices 2.0 4.2 mA -40°C
2.0 4 mA +25°C VDD = 5.0V
2.0 3.8 mA +85°C
PIC18LF6390/6490/8390/8490 2.3 6.4 μA -40°C
2.5 6.4 μA +25°C VDD = 2.0V
2.9 8.8 μA +85°C
PIC18LF6390/6490/8390/8490 3.6 8.8 μA -40°C FOSC = 31 kHz
3.8 8.8 μA +25°C VDD = 3.0V (RC_IDLE mode,
4.6 12 μA +85°C INTRC source)
All devices 7.4 16 μA -40°C
7.8 16 μA +25°C VDD = 5.0V
9.1 29 μA +85°C

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.

PIC18LF6390/6490/8390/8490 132 400 μA -40°C
140 400 μA +25°C VDD = 2.0V
152 400 μA +85°C
PIC18LF6390/6490/8390/8490 200 600 μA -40°C FOSC = 1 MHz
216 600 μA +25°C VDD = 3.0V (RC_IDLE mode,
252 600 μA +85°C INTOSC source)
All devices 0.40 1 mA -40°C
0.42 1 mA +25°C VDD = 5.0V
0.44 1 mA +85°C
PIC18LF6390/6490/8390/8490 272 700 μA -40°C
280 700 μA +25°C VDD = 2.0V
288 700 μA +85°C
PIC18LF6390/6490/8390/8490 0.416 1 mA -40°C FOSC = 4 MHz
0.432 1 mA +25°C VDD = 3.0V (RC_IDLE mode,
0.464 1 mA +85°C INTOSC source)
.9 1.6 mA +25°C VDD = 5.0V
.9 1.6 mA +85°C

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.

PIC18LF6390/6490/8390/8490 250 500 μA -40°C
260 500 μA +25°C VDD = 2.0V
250 500 μA +85°C
PIC18LF6390/6490/8390/8490 550 650 μA -40°C FOSC = 1 MHZ
480 650 μA +25°C VDD = 3.0V (PRI_RUN,
460 650 μA +85°C EC oscillator)
1.1 1.5 mA +25°C VDD = 5.0V
1.0 1.4 mA +85°C
PIC18LF6390/6490/8390/8490 0.72 2.0 mA -40°C
0.74 2.0 mA +25°C VDD = 2.0V
0.74 2.0 mA +85°C
PIC18LF6390/6490/8390/8490 1.3 3.0 mA -40°C FOSC = 4 MHz
1.3 3.0 mA +25°C VDD = 3.0V (PRI_RUN,
1.3 3.0 mA +85°C EC oscillator)
2.6 6.0 mA +25°C VDD = 5.0V
2.5 6.0 mA +85°C
All devices 15 35 mA -40°C
16 35 mA +25°C VDD = 4.2V
16 35 mA +85°C FOSC = 40 MHZ
(PRI_RUN,
All devices 21 40 mA -40°C EC oscillator)
21 40 mA +25°C VDD = 5.0V
21 40 mA +85°C

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.

All devices 7.5 16 mA -40°C FOSC = 4 MHZ.
7.4 15 mA +25°C VDD = 4.2V 16 MHz internal
7.3 14 mA +85°C (PRI_RUN HS+PLL)
All devices 10 21 mA -40°C FOSC = 4 MHZ,
10 20 mA +25°C VDD = 5.0V 16 MHz internal
9.7 19 mA +85°C (PRI_RUN HS+PLL)
17 35 mA +85°C (PRI_RUN HS+PLL)
23 40 mA +85°C (PRI_RUN HS+PLL)

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.

PIC18LF6390/6490/8390/8490 59 117 μA -40°C
59 108 μA +25°C VDD = 2.0V
63 104 μA +85°C
108 225 μA +25°C VDD = 3.0V (PRI_IDLE mode,
216 405 μA +25°C VDD = 5.0V
270 387 μA +85°C
PIC18LF6390/6490/8390/8490 234 428 μA -40°C
230 405 μA +25°C VDD = 2.0V
243 387 μA +85°C
387 765 μA +25°C VDD = 3.0V (PRI_IDLE mode,
.8 1.26 mA +25°C VDD = 5.0V
.8 1.17 mA +85°C
5.6 14.4 mA +25°C VDD = 4.2V
5.9 14.4 mA +85°C FOSC = 40 MHz
(PRI_IDLE mode,
All devices 7.3 16.2 mA -40°C EC oscillator)
8.2 16.2 mA +25°C VDD = 5.0V
7.5 16.2 mA +85°C

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.

PIC18LF6390/6490/8390/8490 13 40 μA -40°C
14 40 μA +25°C VDD = 2.0V
16 40 μA +80°C
PIC18LF6390/6490/8390/8490 34 70 μA -40°C FOSC = 32 kHz
31 70 μA +25°C VDD = 3.0V (SEC_RUN mode,
28 70 μA +80°C Timer1 as clock)(4)
65 150 μA +25°C VDD = 5.0V
59 150 μA +80°C
PIC18LF6390/6490/8390/8490 5.5 15 μA -40°C
5.8 15 μA +25°C VDD = 2.0V
6.1 18 μA +80°C
PIC18LF6390/6490/8390/8490 8.2 30 μA -40°C FOSC = 32 kHz
8.6 30 μA +25°C VDD = 3.0V (SEC_IDLE mode,
8.8 35 μA +80°C Timer1 as clock)(4)
13 80 μA +25°C VDD = 5.0V
13 85 μA +80°C

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.
Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔILCD, ΔIOSCB, ΔIAD)

D022 Watchdog Timer 1.7 4 μA -40°C
(ΔIWDT) 2.1 4 μA +25°C VDD = 2.0V
2.6 5 μA +85°C
2.2 6 μA -40°C
2.4 6 μA +25°C VDD = 3.0V
2.8 7 μA +85°C
2.9 10 μA -40°C
3.1 10 μA +25°C VDD = 5.0V
3.3 13 μA +85°C
D022A Brown-out Reset 17 50 μA -40°C to VDD = 3.0V
(ΔIBOR) +85°C
42 60 μA -40°C to VDD = 5.0V
+85°C
D022B High/Low-Voltage Detect 14 38 μA -40°C to VDD = 2.0V
(ΔILVD) +85°C
18 40 μA -40°C to VDD = 3.0V
+85°C
21 45 μA -40°C to VDD = 5.0V
+85°C
D024 LCD Module 1.5 3 μA -40°C
(ΔILCD) LCD on INTRC clock,
1.5 3 μA +25°C VDD = 2.0V
LCD segments enabled.
1.7 4 μA +85°C
2.2 5 μA -40°C
LCD on INTRC clock,
2.5 5 μA +25°C VDD = 3.0V
2.7 6 μA +85°C
6.1 10 μA -40°C
LCD on INTRC clock,
6.5 10 μA +25°C VDD = 5.0V
7.2 10 μA +85°C

PIC18F6390/6490/8390/8490
PIC18F6390/6490/8390/8490 (Industrial)
Param
No.
Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔILCD, ΔIOSCB, ΔIAD)

D025 Timer1 Oscillator 1.0 3.5 μA -10°C
(ΔIOSCB) 1.1 3.5 μA +25°C VDD = 2.0V 32 kHz on Timer1(4)
1.1 4.5 μA +70°C
1.2 4.5 μA -10°C
1.3 4.5 μA +25°C VDD = 3.0V 32 kHz on Timer1(4)
1.2 5.5 μA +70°C
1.8 6.0 μA -10°C
1.9 6.0 μA +25°C VDD = 5.0V 32 kHz on Timer1(4)
1.9 7.0 μA +70°C
D026 A/D Converter 1.0 3.0 μA — VDD = 2.0V A/D on, not converting
(ΔIAD) 1.0 4.0 μA — VDD = 3.0V
1.0 8.0 μA — VDD = 5.0V

PIC18F6390/6490/8390/8490
26.3 DC Characteristics: PIC18F6390/6490/8390/8490 (Industrial)
Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
Symbol Characteristic Min Max Units Conditions
No.
VIL Input Low Voltage
I/O Ports:
D030 with TTL Buffer VSS 0.15 VDD V VDD < 4.5V
D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger Buffer VSS 0.2 VDD V
RC3 and RC4 VSS 0.3 VDD V
D032 MCLR VSS 0.2 VDD V
D032A OSC1 and T1OSI VSS 0.3 VDD V LP, XT, HS, HSPLL
modes(1)
D033 OSC1 VSS 0.2 VDD V EC mode(1)
VIH Input High Voltage
I/O Ports:
D040 with TTL Buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V
D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V
D041 with Schmitt Trigger Buffer 0.8 VDD VDD V
RC3 and RC4 0.7 VDD VDD V
D042 MCLR 0.8 VDD VDD V
D042A OSC1 and T1OSI 0.7 VDD VDD V LP, XT, HS, HSPLL
modes(1)
D043 OSC1 0.8 VDD VDD V EC mode(1)
IIL Input Leakage Current(2,3)
D060 I/O Ports — ±1 μA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061 MCLR — ±5 μA VSS ≤ VPIN ≤ VDD
D063 OSC1 — ±5 μA VSS ≤ VPIN ≤ VDD
IPU Weak Pull-up Current
D070 IPURB PORTB Weak Pull-up Current 50 400 μA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.

PIC18F6390/6490/8390/8490
26.3 DC Characteristics: PIC18F6390/6490/8390/8490 (Industrial)

DC CHARACTERISTICS
Param
No.
VOL Output Low Voltage
D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V,
(RC, RCIO, EC, ECIO modes) -40°C to +85°C
VOH Output High Voltage(3)
D090 I/O Ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V,
(RC, RCIO, EC, ECIO modes) -40°C to +85°C
D150 VOD Open-Drain High Voltage — 8.5 V RA4 pin
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes
when external clock is
used to drive OSC1
D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing
(in RC mode) Specifications
D102 CB SCL, SDA — 400 pF I2C™ Specification
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.

PIC18F6390/6490/8390/8490
TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS
DC Characteristics
Param
Sym Characteristic Min Typ† Max Units Conditions
No.
Program Flash Memory
D110 VPP Voltage on MCLR/VPP pin 10.0 — 12.0 V
D113 IDDP Supply Current during — — 1 mA
Programming
D130 EP Cell Endurance — 1K — E/W -40°C to +85°C
D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VIE VDD for Block Erase 2.75 — 5.5 V Using ICSP™ port
D132A VIW VDD for Externally Timed Erase 2.75 — 5.5 V Using ICSP port
or Write
D132B VPEW VDD for Self-Timed Write VMIN — 5.5 V VMIN = Minimum operating
voltage
D133 TIE ICSP Block Erase Cycle Time — 4 — ms VDD > 4.5V
D133A TIW ICSP Erase or Write Cycle Time 2 — — ms VDD > 4.5V
(externally timed)
D133A TIW Self-Timed Write Cycle Time — 2 — ms
D134 TRETD Characteristic Retention 40 100 — Year Provided no other
specifications are violated
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

PIC18F6390/6490/8390/8490
TABLE 26-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV
D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio* 55 — — dB
300 TRESP Response Time*(1) — 150 400 ns PIC18FXXXX
300A — 150 600 ns PIC18LFXXXX,
VDD = 2.0V
301 TMC2OV Comparator Mode Change to — — 10 μs
Output Valid*
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — — 1/2 LSb
D312 VRUR Unit Resistor Value (R) — 2k — Ω
310 TSET Settling Time(1) — — 10 μs
Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.

PIC18F6390/6490/8390/8490
FIGURE 26-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
For VDIRMAG = 1: VDD
VHLVD
(HLVDIF set by hardware) (HLVDIF can be

cleared in software)
VHLVD
For VDIRMAG = 0: VDD
HLVDIF
TABLE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

Param
No.
D420 HLVD Voltage on VDD HLVDL<3:0> = 0000 2.06 2.17 2.28 V
Transition High-to-Low HLVDL<3:0> = 0001 2.12 2.23 2.34 V
HLVDL<3:0> = 0010 2.24 2.36 2.48 V
HLVDL<3:0> = 0011 2.32 2.44 2.56 V
HLVDL<3:0> = 0100 2.47 2.60 2.73 V
HLVDL<3:0> = 0101 2.65 2.79 2.93 V
HLVDL<3:0> = 0110 2.74 2.89 3.04 V
HLVDL<3:0> = 0111 2.96 3.12 3.28 V
HLVDL<3:0> = 1000 3.22 3.39 3.56 V
HLVDL<3:0> = 1001 3.37 3.55 3.73 V
HLVDL<3:0> = 1010 3.52 3.71 3.90 V
HLVDL<3:0> = 1011 3.70 3.90 4.10 V
HLVDL<3:0> = 1100 3.90 4.11 4.32 V
HLVDL<3:0> = 1101 4.11 4.33 4.55 V
HLVDL<3:0> = 1110 4.36 4.59 4.82 V
D423 VBG Band Gap Reference HLVDL<3:0> = 1111 — 1.2 — V HLVD input external.
Voltage Value
† Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.

PIC18F6390/6490/8390/8490
26.4 AC (Timing) Characteristics
26.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T13CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO Stop condition
STA Start condition

PIC18F6390/6490/8390/8490
26.4.2 TIMING CONDITIONS Note: Because of space limitations, the generic
The temperature and voltages specified in Table 26-5 terms “PIC18FXXXX” and “PIC18LFXXXX”
apply to all timing specifications unless otherwise are used throughout this section to refer to
noted. Figure 26-4 specifies the load conditions for the the PIC18F6390/6490/8390/8490 and
timing specifications. PIC18LF6390/6490/8390/8490 families of
devices specifically and only those devices.
TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section 26.1 and
Section 26.3.
LF parts operate for industrial temperatures only.
FIGURE 26-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 Load Condition 2
VDD/2
RL Pin CL
VSS
CL
Pin
RL = 464Ω
VSS CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports

PIC18F6390/6490/8390/8490
26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3 4 4
2
CLKO
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.
No.
1A FOSC External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode
DC 20 MHz HS Oscillator mode
DC 31.25 kHz LP Oscillator mode
(1)
Oscillator Frequency DC 4 MHz RC Oscillator mode
0.1 4 MHz XT Oscillator mode
4 20 MHz HS Oscillator mode
5 200 kHz LP Oscillator mode
1 TOSC External CLKI Period(1) 1000 — ns XT, RC Oscillator mode
50 — ns HS Oscillator mode
32 — μs LP Oscillator mode
(1)
Oscillator Period 250 — ns RC Oscillator mode
250 1 μs XT Oscillator mode
100 250 ns HS Oscillator mode
50 250 ns HS Oscillator mode
5 — μs LP Oscillator mode
2 TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC
3 TOSL, External Clock in (OSC1) 30 — ns XT Oscillator mode
TOSH High or Low Time 2.5 — μs LP Oscillator mode
10 — ns HS Oscillator mode
4 TOSR, External Clock in (OSC1) — 20 ns XT Oscillator mode
TOSF Rise or Fall Time — 50 ns LP Oscillator mode
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

PIC18F6390/6490/8390/8490
TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Param
No.
F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only
F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only
F12 trc PLL Start-up Time (Lock Time) — — 2 ms
F13 ΔCLK CLKO Stability (Jitter) -2 — +2 %
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 26-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY

PIC18LF6390/6490/8390/8490 (INDUSTRIAL)
PIC18F6390/6490/8390/8490 (INDUSTRIAL)

Param
Device Min Typ Max Units Conditions
No.
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
PIC18LF6390/6490/8390/8490 -2 +/-1 2 % +25°C VDD = 2.7-3.3V
-5 — 5 % -10°C to +85°C VDD = 2.7-3.3V
-10 +/-1 10 % -40°C to +85°C VDD = 2.7-3.3V
PIC18F6390/6490/8390/8490 -2 +/-1 2 % +25°C VDD = 4.5-5.5V
-5 — 5 % -10°C to +85°C VDD = 4.5-5.5V
-10 +/-1 10 % -40°C to +85°C VDD = 4.5-5.5V
INTRC Accuracy @ Freq = 31 kHz(2)
PIC18LF6390/6490/8390/8490 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7-3.3V
PIC18F6390/6490/8390/8490 26.562 — 35.938 kHz -40°C to +85°C VDD = 4.5-5.5V
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC frequency after calibration.

PIC18F6390/6490/8390/8490
FIGURE 26-6: CLKO AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1
10 11
CLKO
13 12
14 19 18
16
I/O pin
(Input)
17 15
I/O pin Old Value New Value

(Output)
20, 21
Note: Refer to Figure 26-4 for load conditions.
TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS

Param
No.
10 TOSH2CKL OSC1 ↑ to CLKO ↓ — 75 200 ns (Note 1)
11 TOSH2CKH OSC1 ↑ to CLKO ↑ — 75 200 ns (Note 1)
12 TCKR CLKO Rise Time — 35 100 ns (Note 1)
13 TCKF CLKO Fall Time — 35 100 ns (Note 1)
14 TCKL2IOV CLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns (Note 1)
16 TCKH2IOI Port In Hold after CLKO ↑ 0 — — ns (Note 1)
17 TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid — 50 150 ns
18 TOSH2IOI OSC1↑ (Q2 cycle) to PIC18FXXXX 100 — — ns
18A Port Input Invalid PIC18LFXXXX 200 — — ns VDD = 2.0V
(I/O in hold time)
19 TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time) 0 — — ns
20 TIOR Port Output Rise Time PIC18FXXXX — 10 25 ns
20A PIC18LFXXXX — — 60 ns VDD = 2.0V
21 TIOF Port Output Fall Time PIC18FXXXX — 10 25 ns
21A PIC18LFXXXX — — 60 ns VDD = 2.0V
22† TINP INTx pin High or Low Time TCY — — ns
23† TRBP RB7:RB4 Change INTx High or Low Time TCY — — ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

PIC18F6390/6490/8390/8490
FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34 34
I/O pins
FIGURE 26-8: BROWN-OUT RESET TIMING
BVDD
VDD 35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference 36
Voltage Stable
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
30 TMCL MCLR Pulse Width (low) 2 — — μs

31 TWDT Watchdog Timer Time-out Period 3.4 4.0 4.6 ms
(No postscaler)
32 TOST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period
33 TPWRT Power-up Timer Period 55.5 65.5 75 ms
34 TIOZ I/O High-Impedance from MCLR — 2 — μs
Low or Watchdog Timer Reset
35 TBOR Brown-out Reset Pulse Width 200 — — μs VDD ≤ BVDD (see D005)
36 TIRVST Time for Internal Reference — 20 50 μs
Voltage to become Stable
37 TLVD Low-Voltage Detect Pulse Width 200 — — μs VDD ≤ VLVD
38 TCSD CPU Start-up Time — 10 — μs
39 TIOBST Time for INTRC Block to Stabilize — 1 — ms

PIC18F6390/6490/8390/8490
FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1OSO/T13CKI
45 46
47 48
TMR0 or
TMR1
TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
No.
40 TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
41 TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
42 TT0P T0CKI Period No Prescaler TCY + 10 — ns
With Prescaler Greater of: — ns N = prescale
20 ns or value
(TCY + 40)/N (1, 2, 4,..., 256)
45 TT1H T13CKI Synchronous, No Prescaler 0.5 TCY + 20 — ns
High Time Synchronous, PIC18FXXXX 10 — ns
with Prescaler PIC18LFXXXX 25 — ns VDD = 2.0V
Asynchronous PIC18FXXXX 30 — ns
PIC18LFXXXX 50 — ns VDD = 2.0V
46 TT1L T13CKI Synchronous, No Prescaler 0.5 TCY + 5 — ns
Low Time Synchronous, PIC18FXXXX 10 — ns
with Prescaler PIC18LFXXXX 25 — ns VDD = 2.0V
Asynchronous PIC18FXXXX 30 — ns
PIC18LFXXXX 50 — ns VDD = 2.0V
47 TT1P T13CKI Synchronous Greater of: — ns N = prescale
Input 20 ns or value
Period (TCY + 40)/N (1, 2, 4, 8)
Asynchronous 60 — ns
FT 1 T13CKI Oscillator Input Frequency Range DC 50 kHz
48 TCKE2TMRI Delay from External T13CKI Clock Edge to 2 TOSC 7 TOSC —
Timer Increment

PIC18F6390/6490/8390/8490
FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50 51
52
CCPx
(Compare or PWM Mode)
53 54
TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)

Param
No.
50 TCCL CCPx Input Low No Prescaler 0.5 TCY + 20 — ns
Time With PIC18FXXXX 10 — ns
Prescaler PIC18LFXXXX 20 — ns VDD = 2.0V
51 TCCH CCPx Input No Prescaler 0.5 TCY + 20 — ns
High Time With PIC18FXXXX 10 — ns
Prescaler PIC18LFXXXX 20 — ns VDD = 2.0V
52 TCCP CCPx Input Period 3 TCY + 40 — ns N = prescale
N value (1, 4 or 16)
53 TCCR CCPx Output Fall Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
54 TCCF CCPx Output Fall Time PIC18FXXXX — 25 ns

PIC18F6390/6490/8390/8490
FIGURE 26-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
SDO MSb bit 6 - - - - - - 1 LSb
75, 76
SDI MSb In bit 6 - - - - 1 LSb In

74
73
TABLE 26-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param
No.
70 TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input TCY — ns

TSSL2SCL
71 TSCH SCK Input High Time Continuous 1.25 TCY + 30 — ns
71A (Slave mode) Single Byte 40 — ns (Note 1)
72 TSCL SCK Input Low Time Continuous 1.25 TCY + 30 — ns
73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge 100 — ns
TDIV2SCL
73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2)
of Byte 2
74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge 100 — ns
TSCL2DIL
75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
78 TSCR SCK Output Rise Time PIC18FXXXX — 25 ns
(Master mode) PIC18LFXXXX — 45 ns VDD = 2.0V
79 TSCF SCK Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV, SDO Data Output Valid after PIC18FXXXX — 50 ns
TSCL2DOV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.

PIC18F6390/6490/8390/8490
FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
SDO MSb bit 6 - - - - - - 1 LSb
75, 76
74
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.
No.
TDIV2SCL
73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 — ns (Note 2)
of Byte 2
TSCL2DIL
80 TSCH2DOV, SDO Data Output Valid after PIC18FXXXX — 50 ns
TSCL2DOV SCK Edge PIC18LFXXXX — 100 ns VDD = 2.0V
81 TDOV2SCH, SDO Data Output Setup to SCK Edge TCY — ns
TDOV2SCL

PIC18F6390/6490/8390/8490
FIGURE 26-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
SDO MSb bit 6 - - - - - - 1 LSb
75, 76 77

74
73
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.

TSSL2SCL
TDIV2SCL
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
TSCL2DIL
77 TSSH2DOZ SS ↑ to SDO Output High-Impedance 10 50 ns
78 TSCR SCK Output Rise Time (Master mode) PIC18FXXXX — 25 ns
80 TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns
TSCL2DOV PIC18LFXXXX — 100 ns VDD = 2.0V
83 TSCH2SSH, SS ↑ after SCK Edge 1.5 TCY + 40 — ns
TSCL2SSH

PIC18F6390/6490/8390/8490
FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
SDO MSb bit 6 - - - - - - 1 LSb
75, 76 77
SDI
MSb In bit 6 - - - - 1 LSb In
74
TABLE 26-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param
No.

TSSL2SCL
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
TSCL2DIL
77 TSSH2DOZ SS ↑ to SDO Output High-Impedance 10 50 ns
80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXXXX — 50 ns
TSCL2DOV Edge PIC18LFXXXX — 100 ns VDD = 2.0V
82 TSSL2DOV SDO Data Output Valid after SS ↓ PIC18FXXXX — 50 ns
Edge PIC18LFXXXX — 100 ns VDD = 2.0V
83 TSCH2SSH, SS ↑ after SCK Edge 1.5 TCY + 40 — ns
TSCL2SSH

PIC18F6390/6490/8390/8490
FIGURE 26-15: I2C™ BUS START/STOP BITS TIMING
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
TABLE 26-17: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.
No.
90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated
Setup Time 400 kHz mode 600 — Start condition
91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first
Hold Time 400 kHz mode 600 — clock pulse is generated
92 TSU:STO Stop Condition 100 kHz mode 4700 — ns
Setup Time 400 kHz mode 600 —
93 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 —
FIGURE 26-16: I2C™ BUS DATA TIMING
103 100 102

101
SCL
90
106 107
91 92
SDA
In
110
109 109
SDA
Out

PIC18F6390/6490/8390/8490
TABLE 26-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
100 THIGH Clock High Time 100 kHz mode 4.0 — μs PIC18FXXXX must operate at
a minimum of 1.5 MHz
400 kHz mode 0.6 — μs PIC18FXXXX must operate at
a minimum of 10 MHz
MSSP module 1.5 TCY —
101 TLOW Clock Low Time 100 kHz mode 4.7 — μs PIC18FXXXX must operate at
a minimum of 1.5 MHz
400 kHz mode 1.3 — μs PIC18FXXXX must operate at
a minimum of 10 MHz
MSSP module 1.5 TCY —
102 TR SDA and SCL Rise Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 to 400 pF
103 TF SDA and SCL Fall Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated
400 kHz mode 0.6 — μs Start condition
91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first clock
400 kHz mode 0.6 — μs pulse is generated
106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 μs
107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — μs
400 kHz mode 0.6 — μs
109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free
400 kHz mode 1.3 — μs before a new transmission can
start
D102 CB Bus Capacitive Loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode I2C bus device can be used in a Standard mode I2C™ bus system, but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line
is released.

PIC18F6390/6490/8390/8490
FIGURE 26-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
TABLE 26-19: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS

Param.
No.
90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — Repeated Start
condition
1 MHz mode(1) 2(TOSC)(BRG + 1) —
91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — first clock pulse is
generated
92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 26-18: MASTER SSP I2C™ BUS DATA TIMING

103 100 102
101
SCL
90 106
91 107 92
SDA
In
109 109 110
SDA
Out

PIC18F6390/6490/8390/8490
TABLE 26-20: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
No.
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
102 TR SDA and SCL 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 300 ns
103 TF SDA and SCL 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 100 ns
90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms Repeated Start
condition
91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — ms clock pulse is generated
106 THD:DAT Data Input 100 kHz mode 0 — ns
Hold Time 400 kHz mode 0 0.9 ms
1 MHz mode(1) — — ns
107 TSU:DAT Data Input 100 kHz mode 250 — ns (Note 2)
Setup Time 400 kHz mode 100 — ns
1 MHz mode(1) — — ns
92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — ms
109 TAA Output Valid 100 kHz mode — 3500 ns
from Clock 400 kHz mode — 1000 ns
(1)
1 MHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free
400 kHz mode 1.3 — ms before a new transmission
can start
1 MHz mode(1) — — ms
D102 CB Bus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode,) before the
SCL line is released.

PIC18F6390/6490/8390/8490
FIGURE 26-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX1/CK1
pin
121 121
RC7/RX1/DT1
pin
120
122
TABLE 26-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param
No.
120 TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
121 TCKRF Clock Out Rise Time and Fall Time PIC18FXXXX — 20 ns
122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
FIGURE 26-20: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX1/CK1
pin 125
RC7/RX1/DT1
pin
126
TABLE 26-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.
No.
125 TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time) 10 — ns
126 TCKL2DTL Data Hold after CKx ↓ (DTx hold time) 15 — ns

PIC18F6390/6490/8390/8490
TABLE 26-23: A/D CONVERTER CHARACTERISTICS: PIC18F6390/6490/8390/8490 (INDUSTRIAL)
PIC18LF6390/6490/8390/8490 (INDUSTRIAL)
Param
No.
A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V
A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A06 EOFF Offset Error — — <±1 LSb ΔVREF ≥ 3.0V
A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V
A10 — Monotonicity Guaranteed(1) —
A20 ΔVREF Reference Voltage Range 3 — AVDD – AVSS V For 10-bit resolution
(VREFH – VREFL)
A21 VREFH Reference Voltage High AVSS + 3.0V — AVDD + 0.3V V For 10-bit resolution
A22 VREFL Reference Voltage Low AVSS – 0.3V — AVDD – 3.0V V For 10-bit resolution
A25 VAIN Analog Input Voltage VREFL — VREFH V
A30 ZAIN Recommended Impedance of — — 2.5 kΩ
Analog Voltage Source
A50 IREF VREF Input Current (Note 2) — — ±5 μA During VAIN acquisition.
— — ±150 μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+/SEG17 pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/SEG16 pin or AVSS, whichever is selected as the VREFL source.

PIC18F6390/6490/8390/8490
FIGURE 26-21: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
A/D DATA 9 8 7 ... ... 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF TCY
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 26-24: A/D CONVERSION REQUIREMENTS

Param
No.
130 TAD A/D Clock Period PIC18FXXXX 0.7 25.0(1) μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX 1.4 25.0(1) μs VDD = 2.0V;
TOSC based, VREF full range
PIC18FXXXX TBD 1 μs A/D RC mode
PIC18LFXXXX TBD 3 μs VDD = 2.0V; A/D RC mode
131 TCNV Conversion Time 11 12 TAD
(not including acquisition time) (Note 2)
132 TACQ Acquisition Time (Note 3) 1.4 — μs -40°C to +85°C
TBD — μs 0°C ≤ to ≤ +85°C
135 TSWC Switching Time from Convert → Sample — (Note 4)
TBD TDIS Discharge Time 0.2 — μs
Legend: TBD = To Be Determined
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
27.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
64-Lead TQFP Example
XXXXXXXXXX PIC18F6490
XXXXXXXXXX -I/PT e3
XXXXXXXXXX 0710017
YYWWNNN
80-Lead TQFP Example
XXXXXXXXXXXX PIC18F8490-E
XXXXXXXXXXXX /PT e3
YYWWNNN 0710017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC18F6390/6490/8390/8490
28.2 Package Details
The following sections give the technical details of the
packages.
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PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
APPENDIX A: REVISION HISTORY APPENDIX B: DEVICE
DIFFERENCES
Revision A (July 2004)
The differences between the devices listed in this data
Original data sheet for PIC18F6390/6490/8390/8490 sheet are shown in Table B-1.
devices.
Revision B (August 2004)

Updated preliminary “electrical characteristics” data.
Revision C (November 2007)

Revised I2C™ Slave Mode Timing figure. Updated DC
Power-Down and Supply Current table and package
drawings.
TABLE B-1: DEVICE DIFFERENCES

Features PIC18F6390 PIC18F6490 PIC18F8390 PIC18F8490
Number of Pixels the LCD Driver 128 (4 x 32) 128 (4 x 32) 192 (4 x 48) 192 (4 x 48)
can Drive
I/O Ports Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G F, G F, G, H, J F, G, H, J
Flash Program Memory 8 Kbytes 16 Kbytes 8 Kbytes 16 Kbytes
Packages 64-Pin TQFP 64-Pin TQFP 80-Pin TQFP 80-Pin TQFP

PIC18F6390/6490/8390/8490
APPENDIX C: CONVERSION APPENDIX D: MIGRATION FROM
CONSIDERATIONS BASELINE TO
This appendix discusses the considerations for ENHANCED DEVICES
converting from previous versions of a device to the This section discusses how to migrate from a Baseline
ones listed in this data sheet. Typically, these changes device (i.e., PIC16C5X) to an Enhanced MCU device
are due to the differences in the process technology (i.e., PIC18FXXX).
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B. The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available

PIC18F6390/6490/8390/8490
APPENDIX E: MIGRATION FROM APPENDIX F: MIGRATION FROM
MID-RANGE TO HIGH-END TO
ENHANCED DEVICES ENHANCED DEVICES
A detailed discussion of the differences between the A detailed discussion of the migration pathway and
mid-range MCU devices (i.e., PIC16CXXX) and the differences between the high-end MCU devices (i.e.,
enhanced devices (i.e., PIC18FXXX) is provided in PIC17CXXX) and the enhanced devices (i.e.,
AN716, “Migrating Designs from PIC16C74A/74B to PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18C442.” The changes discussed, while device PIC18CXXX Migration.” This Application Note is
specific, are generally applicable to all mid-range to available as Literature Number DS00726.
enhanced device migrations.
This Application Note is available as Literature Number
DS00716.

PIC18F6390/6490/8390/8490
NOTES:

PIC18F6390/6490/8390/8490
INDEX Baud Rate Generator (BRG) ................................... 220
Associated Registers ....................................... 220
A Baud Rate Error, Calculating ........................... 220
Baud Rates, Asynchronous Modes ................. 221
A/D ................................................................................... 231
A/D Converter Interrupt, Configuring ....................... 235 High Baud Rate Select (BRGH Bit) ................. 220
Acquisition Requirements ........................................ 236 Operation in Power-Managed Modes .............. 220
Sampling ......................................................... 220
ADCON0 Register .................................................... 231
ADCON1 Register .................................................... 231 Synchronous Master Mode ...................................... 226
ADCON2 Register .................................................... 231 Associated Registers, Receive ........................ 228
Associated Registers, Transmit ....................... 227
ADRESH Register ............................................ 231, 234
ADRESL Register .................................................... 231 Reception ........................................................ 228
Analog Port Pins, Configuring .................................. 238 Transmission ................................................... 226
Synchronous Slave Mode ........................................ 229
Associated Registers ............................................... 240
Automatic Acquisition Time ...................................... 237 Associated Registers, Receive ........................ 230
Configuring the Module ............................................ 235 Associated Registers, Transmit ....................... 229
Reception ........................................................ 230
Conversion Clock (TAD) ........................................... 237
Conversion Status (GO/DONE Bit) .......................... 234 Transmission ................................................... 229
Conversions ............................................................. 239 Auto-Wake-up on Sync Break Character ......................... 210
Converter Characteristics ........................................ 384 B
Discharge ................................................................. 239
Bank Select Register (BSR) .............................................. 71
Operation in Power-Managed Modes ...................... 238
Baud Rate Generator ...................................................... 183
Special Event Trigger (CCP) .................................... 240
BC .................................................................................... 303
Use of the CCP2 Trigger .......................................... 240
BCF ................................................................................. 304
Absolute Maximum Ratings ............................................. 349
BF .................................................................................... 187
AC (Timing) Characteristics ............................................. 367
BF Status Flag ................................................................. 187
Load Conditions for Device Timing
Block Diagrams
Specifications ................................................... 368
A/D ........................................................................... 234
Parameter Symbology ............................................. 367
Analog Input Model .................................................. 235
Temperature and Voltage Specifications ................. 368
AUSART Receive .................................................... 224
Timing Conditions .................................................... 368
AUSART Transmit ................................................... 222
Access Bank ...................................................................... 73
Baud Rate Generator .............................................. 183
Mapping with Indexed Literal Offset Mode ................. 86
Capture Mode Operation ......................................... 150
ACKSTAT ........................................................................ 187
Comparator Analog Input Model .............................. 245
ACKSTAT Status Flag ..................................................... 187
Comparator I/O Operating Modes ........................... 242
ADCON0 Register ............................................................ 231
Comparator Output .................................................. 244
GO/DONE Bit ........................................................... 234
Comparator Voltage Reference ............................... 248
ADCON1 Register ............................................................ 231
Compare Mode Operation ....................................... 151
ADCON2 Register ............................................................ 231
Device Clock .............................................................. 36
ADDFSR .......................................................................... 338
EUSART Receive .................................................... 208
ADDLW ............................................................................ 301
EUSART Transmit ................................................... 206
Addressable Universal Synchronous Asynchronous
External Power-on Reset Circuit
Receiver Transmitter (AUSART). See AUSART.
(Slow VDD Power-up) ........................................ 53
ADDULNK ........................................................................ 338
Fail-Safe Clock Monitor ........................................... 290
ADDWF ............................................................................ 301
Generic I/O Port Operation ...................................... 109
ADDWFC ......................................................................... 302
HLVD Module (with External Input) ......................... 252
ADRESH Register ............................................................ 231
Interrupt Logic ............................................................ 94
ADRESL Register .................................................... 231, 234
LCD Clock Generation ............................................. 262
Analog-to-Digital Converter. See A/D.
LCD Driver Module .................................................. 257
ANDLW ............................................................................ 302
LCD Resistor Ladder Connection ............................ 263
ANDWF ............................................................................ 303
MSSP (I2C Master Mode) ........................................ 181
Assembler
MSSP (I2C Mode) .................................................... 166
MPASM Assembler .................................................. 346
MSSP (SPI Mode) ................................................... 157
AUSART
On-Chip Reset Circuit ................................................ 51
Asynchronous Mode ................................................ 222
PLL (HS Mode) .......................................................... 33
Associated Registers, Receive ........................ 225
PWM Operation (Simplified) .................................... 153
Associated Registers, Transmit ....................... 223
Reads from Flash Program Memory ......................... 88
Receiver ........................................................... 224
Single Comparator ................................................... 243
Setting up 9-Bit Mode with
Table Read Operation ............................................... 87
Address Detect ........................................ 224
Timer0 in 16-Bit Mode ............................................. 132
Transmitter ....................................................... 222

PIC18F6390/6490/8390/8490
Timer0 in 8-Bit Mode ................................................ 132 Initializing PORTA .................................................... 109
Timer1 ...................................................................... 136 Initializing PORTB .................................................... 112
Timer1 (16-Bit Read/Write Mode) ............................ 136 Initializing PORTC ................................................... 115
Timer2 ...................................................................... 142 Initializing PORTD ................................................... 118
Timer3 ...................................................................... 144 Initializing PORTE .................................................... 120
Timer3 (16-Bit Read/Write Mode) ............................ 144 Initializing PORTF .................................................... 122
Voltage Reference Output Buffer Example .............. 249 Initializing PORTG ................................................... 125
Watchdog Timer ....................................................... 287 Initializing PORTH ................................................... 127
BN .................................................................................... 304 Initializing PORTJ .................................................... 129
BNC .................................................................................. 305 Loading the SSPBUF (SSPSR) Register ................. 160
BNN .................................................................................. 305 Reading a Flash Program Memory Word .................. 89
BNOV ............................................................................... 306 Saving STATUS, WREG and BSR
BNZ .................................................................................. 306 Registers in RAM ............................................. 108
BOR. See Brown-out Reset. Code Protection ............................................................... 281
BOV .................................................................................. 309 COMF .............................................................................. 312
BRA .................................................................................. 307 Comparator ...................................................................... 241
Break Character (12-Bit) Transmit and Receive .............. 211 Analog Input Connection Considerations ................ 245
BRG. See Baud Rate Generator. Associated Registers ............................................... 245
Brown-out Reset (BOR) ............................................. 54, 281 Configuration ........................................................... 242
Disabling in Sleep Mode ............................................ 54 Effects of a Reset .................................................... 244
BSF .................................................................................. 307 Interrupts ................................................................. 244
BSR .................................................................................... 86 Operation ................................................................. 243
BTFSC ............................................................................. 308 Operation During Sleep ........................................... 244
BTFSS .............................................................................. 308 Outputs .................................................................... 243
BTG .................................................................................. 309 Reference ................................................................ 243
BZ ..................................................................................... 310 External Signal ................................................ 243
Internal Signal .................................................. 243
C Response Time ........................................................ 243
C Compilers Comparator Specifications ............................................... 365
MPLAB C18 ............................................................. 346 Comparator Voltage Reference ....................................... 247
MPLAB C30 ............................................................. 346 Accuracy and Error .................................................. 248
CALL ................................................................................ 310 Associated Registers ............................................... 249
CALLW ............................................................................. 339 Configuring .............................................................. 247
Capture (CCP Module) ..................................................... 150 Connection Considerations ...................................... 248
Associated Registers ............................................... 152 Effects of a Reset .................................................... 248
CCP Pin Configuration ............................................. 150 Operation During Sleep ........................................... 248
CCPR2H:CCPR2L Registers ................................... 150 Compare (CCP Module) .................................................. 151
Software Interrupt .................................................... 150 Associated Registers ............................................... 152
Timer1/Timer3 Mode Selection ................................ 150 CCP Pin Configuration ............................................. 151
Capture/Compare/PWM (CCP) ........................................ 147 CCPR2 Register ...................................................... 151
Capture Mode. See Capture. Software Interrupt .................................................... 151
CCP Mode and Timer Resources ............................ 148 Special Event Trigger .............................. 145, 151, 240
CCPRxH Register .................................................... 148 Timer1/Timer3 Mode Selection ................................ 151
CCPRxL Register ..................................................... 148 Computed GOTO ............................................................... 68
Compare Mode. See Compare. Configuration Bits ............................................................ 281
Interaction of CCP1 and CCP2 for Configuration Register Protection .................................... 292
Timer Resources .............................................. 149 Context Saving During Interrupts ..................................... 108
Interconnect Configurations ..................................... 148 Conversion Considerations .............................................. 396
Module Configuration ............................................... 148 CPFSEQ .......................................................................... 312
Clock Sources .................................................................... 36 CPFSGT .......................................................................... 313
Selecting the 31 kHz Source ...................................... 37 CPFSLT ........................................................................... 313
Selection Using OSCCON Register ........................... 37 Crystal Oscillator/Ceramic Resonator ................................ 31
CLRF ................................................................................ 311 Customer Change Notification Service ............................ 409
CLRWDT .......................................................................... 311 Customer Notification Service ......................................... 409
Code Examples Customer Support ............................................................ 409
16 x 16 Signed Multiply Routine ................................ 92
16 x 16 Unsigned Multiply Routine ............................ 92 D
8 x 8 Signed Multiply Routine .................................... 91 Data Addressing Modes .................................................... 81
8 x 8 Unsigned Multiply Routine ................................ 91 Comparing Addressing Modes with the
Changing Between Capture Prescalers ................... 150 Extended Instruction Set Enabled ..................... 85
Computed GOTO Using an Offset Value ................... 68 Direct ......................................................................... 81
Fast Register Stack .................................................... 68 Indexed Literal Offset ................................................ 84
How to Clear RAM (Bank 1) Using Indirect ....................................................................... 81
Indirect Addressing ............................................ 81 Inherent and Literal .................................................... 81
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ............................... 139

PIC18F6390/6490/8390/8490
Data Memory ..................................................................... 71 Extended Instruction Set
Access Bank .............................................................. 73 ADDFSR .................................................................. 338
and the Extended Instruction Set ............................... 84 ADDULNK ............................................................... 338
Bank Select Register (BSR) ....................................... 71 CALLW .................................................................... 339
General Purpose Registers ........................................ 73 MOVSF .................................................................... 339
Map for PIC18F6X90/8X90 Devices .......................... 72 MOVSS .................................................................... 340
Special Function Registers ........................................ 74 PUSHL ..................................................................... 340
DAW ................................................................................. 314 SUBFSR .................................................................. 341
DC and AC Characteristics SUBULNK ................................................................ 341
Graphs and Tables .................................................. 387 External Clock Input ........................................................... 32
DC Characteristics ........................................................... 362
Power-Down and Supply Current ............................ 352 F
Supply Voltage ......................................................... 351 Fail-Safe Clock Monitor ........................................... 281, 290
DCFSNZ .......................................................................... 315 Interrupts in Power-Managed Modes ...................... 291
DECF ............................................................................... 314 POR or Wake from Sleep ........................................ 291
DECFSZ ........................................................................... 315 WDT During Oscillator Failure ................................. 290
Development Support ...................................................... 345 Fast Register Stack ........................................................... 68
Device Differences ........................................................... 395 Firmware Instructions ...................................................... 295
Device Overview .................................................................. 7 Flash Program Memory ..................................................... 87
Features (table) ............................................................ 9 Associated Registers ................................................. 89
New Core Features ...................................................... 7 Control Registers ....................................................... 88
Special Features .......................................................... 8 TABLAT (Table Latch) Register ........................ 88
Direct Addressing ............................................................... 82 TBLPTR (Table Pointer) Register ...................... 88
Reading ..................................................................... 88
E Table Reads .............................................................. 87
Effect on Standard Instructions .......................................... 84 FSCM. See Fail-Safe Clock Monitor.
Effect on Standard PIC MCU Instructions ........................ 342
Electrical Characteristics .................................................. 349 G
Enhanced Universal Synchronous Asynchronous GOTO .............................................................................. 316
Receiver Transmitter (EUSART). See EUSART.
Equations
H
A/D Acquisition Time ................................................ 236 Hardware Multiplier ............................................................ 91
A/D Minimum Charging Time ................................... 236 Introduction ................................................................ 91
Calculating the Minimum Required Operation ................................................................... 91
Acquisition Time .............................................. 236 Performance Comparison .......................................... 91
Errata ................................................................................... 5 High/Low-Voltage Detect ................................................. 251
EUSART Applications ............................................................. 254
Asynchronous Mode ................................................ 206 Typical Low-Voltage Detect (diagram) ............ 254
12-Bit Break Transmit and Receive ................. 211 Associated Registers ............................................... 255
Associated Registers, Receive ........................ 209 Characteristics ......................................................... 366
Associated Registers, Transmit ....................... 207 Current Consumption .............................................. 253
Auto-Wake-up on Sync Break ......................... 210 Effects of a Reset .................................................... 255
Receiver ........................................................... 208 Operation ................................................................. 252
Setting up 9-Bit Mode with During Sleep .................................................... 255
Address Detect ........................................ 208 Setup ....................................................................... 253
Transmitter ....................................................... 206 Start-up Time ........................................................... 253
Baud Rate Generator (BRG) .................................... 201 HLVD. See High/Low-Voltage Detect. ............................. 251
Associated Registers ....................................... 201
I
Auto-Baud Rate Detect .................................... 204
Baud Rate Error, Calculating ........................... 201 I/O Ports .......................................................................... 109
Baud Rates, Asynchronous Modes ................. 202 I2C Mode (MSSP)
High Baud Rate Select (BRGH Bit) ................. 201 Acknowledge Sequence Timing .............................. 190
Operation in Power-Managed Modes .............. 201 Associated Registers ............................................... 196
Sampling .......................................................... 201 Baud Rate Generator .............................................. 183
Synchronous Master Mode ...................................... 212 Bus Collision
Associated Registers, Receive ........................ 214 During a Repeated Start Condition .................. 194
Associated Registers, Transmit ....................... 213 During a Start Condition .................................. 192
Reception ......................................................... 214 During a Stop Condition .................................. 195
Transmission ................................................... 212 Clock Arbitration ...................................................... 184
Synchronous Slave Mode ........................................ 215 Clock Stretching ...................................................... 176
Associated Registers, Receive ........................ 216 10-Bit Slave Receive Mode (SEN = 1) ............ 176
Associated Registers, Transmit ....................... 215 10-Bit Slave Transmit Mode ............................ 176
Reception ......................................................... 216 7-Bit Slave Receive Mode (SEN = 1) .............. 176
Transmission ................................................... 215 7-Bit Slave Transmit Mode .............................. 176

PIC18F6390/6490/8390/8490
Effect of a Reset ...................................................... 191 DAW ........................................................................ 314
General Call Address Support ................................. 180 DCFSNZ .................................................................. 315
I2C Clock Rate w/BRG ............................................. 183 DECF ....................................................................... 314
Master Mode ............................................................ 181 DECFSZ .................................................................. 315
Operation ......................................................... 182 Extended Instructions .............................................. 337
Reception ......................................................... 187 and Using MPLAB IDE Tools .......................... 344
Repeated Start Condition Timing ..................... 186 Considerations when Enabling ........................ 342
Start Condition ................................................. 185 Syntax .............................................................. 337
Transmission .................................................... 187 General Format ........................................................ 297
Transmit Sequence .......................................... 182 GOTO ...................................................................... 316
Multi-Master Communication, Bus Collision INCF ........................................................................ 316
and Arbitration .................................................. 191 INCFSZ .................................................................... 317
Multi-Master Mode ................................................... 191 INFSNZ .................................................................... 317
Operation ................................................................. 170 IORLW ..................................................................... 318
Read/Write Bit Information (R/W Bit) ............... 170, 171 IORWF ..................................................................... 318
Registers .................................................................. 166 LFSR ....................................................................... 319
Serial Clock (RC3/SCK/SCL) ................................... 171 MOVF ...................................................................... 319
Slave Mode .............................................................. 170 MOVFF .................................................................... 320
Addressing ....................................................... 170 MOVLB .................................................................... 320
Reception ......................................................... 171 MOVLW ................................................................... 321
Sleep Operation ....................................................... 191 MOVWF ................................................................... 321
Stop Condition Timing .............................................. 190 MULLW .................................................................... 322
Transmission ............................................................ 171 MULWF .................................................................... 322
ID Locations ............................................................. 281, 293 NEGF ....................................................................... 323
INCF ................................................................................. 316 NOP ......................................................................... 323
INCFSZ ............................................................................ 317 POP ......................................................................... 324
In-Circuit Debugger .......................................................... 293 PUSH ....................................................................... 324
In-Circuit Serial Programming (ICSP) ...................... 281, 293 RCALL ..................................................................... 325
Indexed Literal Offset Addressing Mode .......................... 342 RESET ..................................................................... 325
and Standard PIC18 Instructions ............................. 342 RETFIE .................................................................... 326
Indexed Literal Offset Mode ......................................... 84, 86 RETLW .................................................................... 326
Indirect Addressing ............................................................ 82 RETURN .................................................................. 327
INFSNZ ............................................................................ 317 RLCF ....................................................................... 327
Initialization Conditions for all Registers ...................... 59–64 RLNCF ..................................................................... 328
Instruction Cycle ................................................................. 69 RRCF ....................................................................... 328
Clocking Scheme ....................................................... 69 RRNCF .................................................................... 329
Instruction Flow/Pipelining ................................................. 69 SETF ....................................................................... 329
Instruction Set .................................................................. 295 SETF (Indexed Literal Offset mode) ........................ 343
ADDLW .................................................................... 301 SLEEP ..................................................................... 330
ADDWF .................................................................... 301 Standard Instructions ............................................... 295
ADDWF (Indexed Literal Offset mode) .................... 343 SUBFWB ................................................................. 330
ADDWFC ................................................................. 302 SUBLW .................................................................... 331
ANDLW .................................................................... 302 SUBWF .................................................................... 331
ANDWF .................................................................... 303 SUBWFB ................................................................. 332
BC ............................................................................ 303 SWAPF .................................................................... 332
BCF .......................................................................... 304 TBLRD ..................................................................... 333
BN ............................................................................ 304 TBLWT .................................................................... 334
BNC ......................................................................... 305 TSTFSZ ................................................................... 335
BNN ......................................................................... 305 XORLW ................................................................... 335
BNOV ....................................................................... 306 XORWF ................................................................... 336
BNZ .......................................................................... 306 Summary Table ....................................................... 298
BOV ......................................................................... 309 INTCON Register
BRA .......................................................................... 307 RBIF Bit ................................................................... 112
BSF .......................................................................... 307 INTCON Registers ............................................................. 95
BSF (Indexed Literal Offset mode) .......................... 343 Inter-Integrated Circuit. See I2C.
BTFSC ..................................................................... 308 Internal Oscillator Block ..................................................... 34
BTFSS ..................................................................... 308 Adjustment ................................................................. 34
BTG .......................................................................... 309 INTIO Modes ............................................................. 34
BZ ............................................................................ 310 INTOSC Output Frequency ....................................... 34
CALL ........................................................................ 310 OSCTUNE Register ................................................... 34
CLRF ........................................................................ 311 Internal RC Oscillator
CLRWDT .................................................................. 311 Use with WDT .......................................................... 287
COMF ...................................................................... 312 Internet Address .............................................................. 409
CPFSEQ .................................................................. 312
CPFSGT .................................................................. 313
CPFSLT ................................................................... 313

PIC18F6390/6490/8390/8490
Interrupt Sources ............................................................. 281 MOVWF ........................................................................... 321
A/D Conversion Complete ....................................... 235 MPLAB ASM30 Assembler, Linker, Librarian .................. 346
Capture Complete (CCP) ......................................... 150 MPLAB ICD 2 In-Circuit Debugger .................................. 347
Compare Complete (CCP) ....................................... 151 MPLAB ICE 2000 High-Performance
Interrupt-on-Change (RB7:RB4) .............................. 112 Universal In-Circuit Emulator ................................... 347
INTx Pin ................................................................... 108 MPLAB Integrated Development
PORTB, Interrupt-on-Change .................................. 108 Environment Software ............................................. 345
TMR0 ....................................................................... 108 MPLAB PM3 Device Programmer ................................... 347
TMR0 Overflow ........................................................ 133 MPLAB REAL ICE In-Circuit Emulator System ............... 347
TMR1 Overflow ........................................................ 135 MPLINK Object Linker/MPLIB Object Librarian ............... 346
TMR2 to PR2 Match (PWM) .................................... 153 MSSP
TMR3 Overflow ................................................ 143, 145 ACK Pulse ....................................................... 170, 171
Interrupts ............................................................................ 93 Control Registers (general) ..................................... 157
Interrupts, Flag Bits I2C Mode. See I2C Mode.
Interrupt-on-Change (RB7:RB4) Flag Module Overview ..................................................... 157
(RBIF Bit) ......................................................... 112 SPI Master/Slave Connection .................................. 161
INTOSC Frequency Drift .................................................... 34 SPI Mode. See SPI Mode.
INTOSC, INTRC. See Internal Oscillator Block. SSPBUF .................................................................. 162
IORLW ............................................................................. 318 SSPSR .................................................................... 162
IORWF ............................................................................. 318 MULLW ............................................................................ 322
IPR Registers ................................................................... 104 MULWF ............................................................................ 322
L N
LCD NEGF ............................................................................... 323
Associated Registers ............................................... 279 NOP ................................................................................. 323
Bias Types ............................................................... 263
Clock Source Selection ............................................ 262 O
Configuring the Module ............................................ 278 Opcode Field Descriptions ............................................... 296
Frame Frequency ..................................................... 264 Oscillator Configuration ..................................................... 31
Interrupts .................................................................. 276 EC .............................................................................. 31
LCDCON Register ................................................... 258 ECIO .......................................................................... 31
LCDDATA Register .................................................. 258 HS .............................................................................. 31
LCDPS Register ....................................................... 258 HSPLL ....................................................................... 31
LCDSE Register ....................................................... 258 Internal Oscillator Block ............................................. 34
Multiplex Types ........................................................ 263 INTIO1 ....................................................................... 31
Operation During Sleep ........................................... 277 INTIO2 ....................................................................... 31
Pixel Control ............................................................. 264 LP .............................................................................. 31
Prescaler .................................................................. 262 RC ............................................................................. 31
Segment Enables ..................................................... 263 RCIO .......................................................................... 31
Waveform Generation .............................................. 264 XT .............................................................................. 31
LCDCON Register ........................................................... 258 Oscillator Selection .......................................................... 281
LCDDATA Register .......................................................... 258 Oscillator Start-up Timer (OST) ........................... 39, 55, 281
LCDPS Register ............................................................... 258 Oscillator Switching ........................................................... 36
LP3:LP0 Bits ............................................................ 262 Oscillator Transitions ......................................................... 37
LCDSE Register ............................................................... 258 Oscillator, Timer1 ..................................................... 135, 145
LFSR ................................................................................ 319 Oscillator, Timer3 ............................................................. 143
Liquid Crystal Display (LCD) Driver ................................. 257
Look-up Tables .................................................................. 68
P
Packaging ........................................................................ 389
M Details ...................................................................... 390
Master Clear (MCLR) ......................................................... 53 Marking .................................................................... 389
Master Synchronous Serial Port (MSSP). See MSSP. PICSTART Plus Development Programmer .................... 348
Memory Organization ......................................................... 65 PIE Registers ................................................................... 101
Data Memory ............................................................. 71 Pin Functions
Program Memory ....................................................... 65 AVDD .......................................................................... 29
Memory Programming Requirements .............................. 364 AVDD .......................................................................... 19
Microchip Internet Web Site ............................................. 409 AVSS .......................................................................... 29
Migration from Baseline to Enhanced Devices ................ 396 AVSS .......................................................................... 19
Migration from High-End to Enhanced Devices ............... 397 COM0 .................................................................. 17, 25
Migration from Mid-Range to Enhanced Devices ............ 397 LCDBIAS1 ........................................................... 17, 25
MOVF ............................................................................... 319 LCDBIAS2 ........................................................... 17, 25
MOVFF ............................................................................ 320 LCDBIAS3 ........................................................... 17, 25
MOVLB ............................................................................ 320 MCLR/VPP/RG5 ................................................... 12, 20
MOVLW ........................................................................... 321 OSC1/CLKI/RA7 .................................................. 12, 20
MOVSF ............................................................................ 339 OSC2/CLKO/RA6 ................................................ 12, 20
MOVSS ............................................................................ 340 RA0/AN0 .............................................................. 13, 21

PIC18F6390/6490/8390/8490
RA1/AN1 .............................................................. 13, 21 VSS ............................................................................ 29
RA2/AN2/VREF-/SEG16 ....................................... 13, 21 VSS ............................................................................ 19
RA3/AN3/VREF+/SEG17 ...................................... 13, 21 Pinout I/O Descriptions
RA4/T0CKI/SEG14 .............................................. 13, 21 PIC18F6X90 .............................................................. 12
RA5/AN4/HLVDIN/SEG15 ................................... 13, 21 PIC18F8X90 .............................................................. 20
RB0/INT0 ............................................................. 14, 22 PIR Registers ..................................................................... 98
RB1/INT1/SEG8 ................................................... 14, 22 PLL .................................................................................... 33
RB2/INT2/SEG9 ................................................... 14, 22 HSPLL Oscillator Mode ............................................. 33
RB3/INT3/SEG10 ................................................. 14, 22 Use with INTOSC ................................................ 33, 34
RB4/KBI0/SEG11 ................................................. 14, 22 PLL Lock Time-out ............................................................. 55
RB5/KBI1 ............................................................. 14, 22 POP ................................................................................. 324
RB6/KBI2/PGC .................................................... 14, 22 POR. See Power-on Reset.
RB7/KBI3/PGD .................................................... 14, 22 PORTA
RC0/T1OSO/T13CKI ........................................... 15, 23 Associated Registers ............................................... 111
RC1/T1OSI/CCP2 ................................................ 15, 23 LATA Register ......................................................... 109
RC2/CCP1/SEG13 ............................................... 15, 23 PORTA Register ...................................................... 109
RC3/SCK/SCL ..................................................... 15, 23 TRISA Register ........................................................ 109
RC4/SDI/SDA ...................................................... 15, 23 PORTB
RC5/SDO/SEG12 ................................................ 15, 23 Associated Registers ............................................... 114
RC6/TX1/CK1 ...................................................... 15, 23 LATB Register ......................................................... 112
RC7/RX1/DT1 ...................................................... 15, 23 PORTB Register ...................................................... 112
RD0/SEG0 ........................................................... 16, 24 RB7:RB4 Interrupt-on-Change Flag
RD1/SEG1 ........................................................... 16, 24 (RBIF Bit) ......................................................... 112
RD2/SEG2 ........................................................... 16, 24 TRISB Register ........................................................ 112
RD3/SEG3 ........................................................... 16, 24 PORTC
RD4/SEG4 ........................................................... 16, 24 Associated Registers ............................................... 117
RD5/SEG5 ........................................................... 16, 24 LATC Register ......................................................... 115
RD6/SEG6 ........................................................... 16, 24 PORTC Register ...................................................... 115
RD7/SEG7 ........................................................... 16, 24 RC3/SCK/SCL Pin ................................................... 171
RE4/COM1 ........................................................... 17, 25 TRISC Register ........................................................ 115
RE5/COM2 ........................................................... 17, 25 PORTD
RE6/COM3 ........................................................... 17, 25 Associated Registers ............................................... 119
RE7/CCP2/SEG31 ............................................... 17, 25 LATD Register ......................................................... 118
RF0/AN5/SEG18 .................................................. 18, 26 PORTD Register ...................................................... 118
RF1/AN6/C2OUT/SEG19 .................................... 18, 26 TRISD Register ........................................................ 118
RF2/AN7/C1OUT/SEG20 .................................... 18, 26 PORTE
RF3/AN8/SEG21 .................................................. 18, 26 Associated Registers ............................................... 121
RF4/AN9/SEG22 .................................................. 18, 26 LATE Register ......................................................... 120
RF5/AN10/CVREF/SEG23 .................................... 18, 26 PORTE Register ...................................................... 120
RF6/AN11/SEG24 ................................................ 18, 26 TRISE Register ........................................................ 120
RF7/SS/SEG25 .................................................... 18, 26 PORTF
RG0/SEG30 ......................................................... 19, 27 Associated Registers ............................................... 124
RG1/TX2/CK2/SEG29 ......................................... 19, 27 LATF Register .......................................................... 122
RG2/RX2/DT2/SEG28 ......................................... 19, 27 PORTF Register ...................................................... 122
RG3/SEG27 ......................................................... 19, 27 TRISF Register ........................................................ 122
RG4/SEG26 ......................................................... 19, 27 PORTG
RG5 ...................................................................... 19, 27 Associated Registers ............................................... 126
RH0/SEG47 ............................................................... 28 LATG Register ......................................................... 125
RH1/SEG46 ............................................................... 28 PORTG Register ...................................................... 125
RH2/SEG45 ............................................................... 28 TRISG Register ....................................................... 125
RH3/SEG44 ............................................................... 28 PORTH
RH4/SEG40 ............................................................... 28 Associated Registers ............................................... 128
RH5/SEG41 ............................................................... 28 LATH Register ......................................................... 127
RH6/SEG42 ............................................................... 28 PORTH Register ...................................................... 127
RH7/SEG43 ............................................................... 28 TRISH Register ........................................................ 127
RJ0/SEG32 ................................................................ 29 PORTJ
RJ1/SEG33 ................................................................ 29 Associated Registers ............................................... 130
RJ2/SEG34 ................................................................ 29 LATJ Register .......................................................... 129
RJ3/SEG35 ................................................................ 29 PORTJ Register ....................................................... 129
RJ4/SEG39 ................................................................ 29 TRISJ Register ........................................................ 129
RJ5/SEG38 ................................................................ 29 Postscaler, WDT
RJ6/SEG37 ................................................................ 29 Assignment (PSA Bit) .............................................. 133
RJ7/SEG36 ................................................................ 29 Rate Select (T0PS2:T0PS0 Bits) ............................. 133
VDD ............................................................................. 29 Switching Between Timer0 and WDT ...................... 133
VDD ............................................................................. 19

PIC18F6390/6490/8390/8490
Power-Managed Modes ..................................................... 41 Reader Response ............................................................ 410
and Multiple Sleep Commands .................................. 42 Reading Program Memory and Other Locations ............. 292
Effects on Clock Sources ........................................... 39 Register File ....................................................................... 73
Entering ...................................................................... 41 Register File Summary ................................................ 76–79
Exiting Idle and Sleep Modes Registers
by Reset ............................................................. 48 ADCON0 (A/D Control 0) ......................................... 231
by WDT Time-out ............................................... 48 ADCON1 (A/D Control 1) ......................................... 232
Without a Start-up Delay .................................... 48 ADCON2 (A/D Control 2) ......................................... 233
Exiting Idle or Sleep Modes ....................................... 48 BAUDCON1 (Baud Rate Control 1) ......................... 200
by Interrupt ......................................................... 48 CCPxCON (CCPx Control) ...................................... 147
Idle Modes ................................................................. 45 CMCON (Comparator Control) ................................ 241
PRI_IDLE ........................................................... 46 CONFIG1H (Configuration 1 High) .......................... 282
Run Modes ................................................................. 42 CONFIG2H (Configuration 2 High) .......................... 284
PRI_RUN ........................................................... 42 CONFIG2L (Configuration 2 Low) ........................... 283
RC_RUN ............................................................ 44 CONFIG3H (Configuration 3 High) .......................... 284
SEC_RUN .......................................................... 42 CONFIG4L (Configuration 4 Low) ........................... 285
Selecting .................................................................... 41 CONFIG5L (Configuration 5 Low) ........................... 285
Sleep Mode ................................................................ 45 CVRCON (Comparator Voltage
Summary (table) ........................................................ 41 Reference Control) .......................................... 247
Power-on Reset (POR) .............................................. 53, 281 DEVID1 (Device ID 1) .............................................. 286
Oscillator Start-up Timer (OST) ................................. 55 DEVID2 (Device ID 2) .............................................. 286
Power-up Timer (PWRT) ................................... 55, 281 HLVDCON (High/Low-Voltage
Time-out Sequence .................................................... 55 Detect Control) ................................................ 251
Power-up Delays ................................................................ 39 INTCON (Interrupt Control) ....................................... 95
Power-up Timer (PWRT) ............................................. 39, 55 INTCON2 (Interrupt Control 2) .................................. 96
Prescaler, Capture ........................................................... 150 INTCON3 (Interrupt Control 3) .................................. 97
Prescaler, Timer0 ............................................................. 133 IPR1 (Peripheral Interrupt Priority 1) ....................... 104
Assignment (PSA Bit) .............................................. 133 IPR2 (Peripheral Interrupt Priority 2) ....................... 105
Rate Select (T0PS2:T0PS0 Bits) ............................. 133 IPR3 (Peripheral Interrupt Priority 3) ....................... 106
Switching Between Timer0 and WDT ...................... 133 LCDCON (LCD Control) .......................................... 258
Prescaler, Timer2 ............................................................. 154 LCDDATAx (LCD Datax) ......................................... 261
Program Counter ............................................................... 66 LCDPS (LCD Phase) ............................................... 259
PCL, PCH and PCU Registers ................................... 66 LCDSEx (LCD Segmentx Enable) ........................... 260
PCLATH and PCLATU Registers .............................. 66 OSCCON (Oscillator Control) .................................... 38
Program Memory OSCTUNE (Oscillator Tuning) ................................... 35
and Extended Instruction Set ..................................... 84 PIE1 (Peripheral Interrupt Enable 1) ....................... 101
Instructions ................................................................. 70 PIE2 (Peripheral Interrupt Enable 2) ....................... 102
Two-Word .......................................................... 70 PIE3 (Peripheral Interrupt Enable 3) ....................... 103
Interrupt Vector .......................................................... 65 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 98
Map and Stack (diagram) ........................................... 65 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 99
Reset Vector .............................................................. 65 PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 100
Program Verification and Code Protection ....................... 292 RCON (Reset Control) ....................................... 52, 107
Associated Registers ............................................... 292 RCSTA1 (EUSART Receive
Programming, Device Instructions ................................... 295 Status and Control) .......................................... 199
Pulse-Width Modulation. See PWM (CCP Module). RCSTA2 (AUSART Receive
PUSH ............................................................................... 324 Status and Control) .......................................... 219
PUSH and POP Instructions .............................................. 67 SSPCON1 (MSSP Control 1, I2C Mode) ................. 168
PUSHL ............................................................................. 340 SSPCON1 (MSSP Control 1, SPI Mode) ................ 159
PWM (CCP Module) SSPCON2 (MSSP Control 2,
Associated Registers ............................................... 155 I2C Master Mode) ............................................ 169
Duty Cycle ................................................................ 154 SSPSTAT (MSSP Status, I2C Mode) ...................... 167
Example Frequencies/Resolutions .......................... 154 SSPSTAT (MSSP Status, SPI Mode) ...................... 158
Period ....................................................................... 153 STATUS .................................................................... 80
Setup for PWM Operation ........................................ 155 STKPTR (Stack Pointer) ............................................ 67
TMR2 to PR2 Match ................................................ 153 T0CON (Timer0 Control) ......................................... 131
T1CON (Timer1 Control) ......................................... 135
Q T2CON (Timer2 Control) ......................................... 141
Q Clock ............................................................................ 154 T3CON (Timer3 Control) ......................................... 143
TXSTA1 (EUSART Transmit
R Status and Control) .......................................... 198
RAM. See Data Memory. TXSTA2 (AUSART Transmit
RC Oscillator ...................................................................... 33 Status and Control) .......................................... 218
RCIO Oscillator Mode ................................................ 33 WDTCON (Watchdog Timer Control) ...................... 288
RCALL ............................................................................. 325 RESET ............................................................................. 325
RCON Register
Bit Status During Initialization .................................... 58

PIC18F6390/6490/8390/8490
Reset .................................................................................. 51 SUBULNK ........................................................................ 341
MCLR Reset, during Power-Managed Modes ........... 51 SUBWF ............................................................................ 331
MCLR Reset, Normal Operation ................................ 51 SUBWFB ......................................................................... 332
Power-on Reset (POR) .............................................. 51 SWAPF ............................................................................ 332
Programmable Brown-out Reset (BOR) .................... 51
Stack Full Reset ......................................................... 51 T
Stack Underflow Reset .............................................. 51 T0CON Register
Watchdog Timer (WDT) Reset ................................... 51 PSA Bit .................................................................... 133
Resets .............................................................................. 281 T0CS Bit .................................................................. 132
RETFIE ............................................................................ 326 T0PS2:T0PS0 Bits ................................................... 133
RETLW ............................................................................. 326 T0SE Bit .................................................................. 132
RETURN .......................................................................... 327 Table Pointer Operations (table) ........................................ 88
Return Address Stack ........................................................ 66 Table Reads ...................................................................... 68
Return Stack Pointer (STKPTR) ........................................ 67 TBLRD ............................................................................. 333
Revision History ............................................................... 395 TBLWT ............................................................................. 334
RLCF ................................................................................ 327 Time-out in Various Situations (table) ................................ 55
RLNCF ............................................................................. 328 Timer0 .............................................................................. 131
RRCF ............................................................................... 328 16-Bit Mode Timer Reads and Writes ...................... 132
RRNCF ............................................................................. 329 Associated Registers ............................................... 133
Clock Source Edge Select (T0SE Bit) ..................... 132
S Clock Source Select (T0CS Bit) ............................... 132
SCK .................................................................................. 157 Operation ................................................................. 132
SDI ................................................................................... 157 Overflow Interrupt .................................................... 133
SDO ................................................................................. 157 Prescaler. See Prescaler, Timer0.
Serial Clock, SCK ............................................................. 157 Timer1 .............................................................................. 135
Serial Data In (SDI) .......................................................... 157 16-Bit Read/Write Mode .......................................... 137
Serial Data Out (SDO) ..................................................... 157 Associated Registers ............................................... 139
Serial Peripheral Interface. See SPI Mode. Interrupt ................................................................... 138
SETF ................................................................................ 329 Operation ................................................................. 136
Slave Select (SS) ............................................................. 157 Oscillator .......................................................... 135, 137
SLEEP .............................................................................. 330 Layout Considerations ..................................... 138
Sleep Overflow Interrupt .................................................... 135
OSC1 and OSC2 Pin States ...................................... 39 Resetting, Using a Special Event Trigger
Software Enabled BOR ...................................................... 54 Output (CCP) ................................................... 138
Software Simulator (MPLAB SIM) .................................... 346 TMR1H Register ...................................................... 135
Special Event Trigger. See Compare (CCP Module). TMR1L Register ....................................................... 135
Special Features of the CPU ............................................ 281 Use as a Real-Time Clock ....................................... 138
Special Function Registers ................................................ 74 Timer2 .............................................................................. 141
Map ...................................................................... 74–75 Associated Registers ............................................... 142
SPI Mode (MSSP) Interrupt ................................................................... 142
Associated Registers ............................................... 165 Operation ................................................................. 141
Bus Mode Compatibility ........................................... 165 Output ...................................................................... 142
Effects of a Reset ..................................................... 165 PR2 Register ........................................................... 153
Enabling SPI I/O ...................................................... 161 TMR2 to PR2 Match Interrupt .................................. 153
Master Mode ............................................................ 162 Timer3 .............................................................................. 143
Master/Slave Connection ......................................... 161 16-Bit Read/Write Mode .......................................... 145
Operation ................................................................. 160 Associated Registers ............................................... 145
Serial Clock .............................................................. 157 Operation ................................................................. 144
Serial Data In ........................................................... 157 Oscillator .......................................................... 143, 145
Serial Data Out ........................................................ 157 Overflow Interrupt ............................................ 143, 145
Slave Mode .............................................................. 163 Special Event Trigger (CCP) ................................... 145
Slave Select ............................................................. 157 TMR3H Register ...................................................... 143
Slave Select Synchronization .................................. 163 TMR3L Register ....................................................... 143
Sleep Operation ....................................................... 165 Timing Diagrams
SPI Clock ................................................................. 162 A/D Conversion ........................................................ 385
Typical Connection .................................................. 161 Acknowledge Sequence .......................................... 190
SS .................................................................................... 157 Asynchronous Reception ................................. 209, 225
SSPOV ............................................................................. 187 Asynchronous Transmission ............................ 207, 223
SSPOV Status Flag .......................................................... 187 Asynchronous Transmission
SSPSTAT Register (Back-to-Back) ......................................... 207, 223
R/W Bit ............................................................. 170, 171 Automatic Baud Rate Calculation ............................ 205
Stack Full/Underflow Resets .............................................. 68 Auto-Wake-up Bit (WUE) During
STATUS Register ............................................................... 80 Normal Operation ............................................ 210
SUBFSR ........................................................................... 341 Auto-Wake-up Bit (WUE) During Sleep ................... 210
SUBFWB .......................................................................... 330 Baud Rate Generator with Clock Arbitration ............ 184
SUBLW ............................................................................ 331 BRG Overflow Sequence ......................................... 205

PIC18F6390/6490/8390/8490
BRG Reset Due to SDA Arbitration Time-out Sequence on POR w/PLL Enabled
During Start Condition ..................................... 193 (MCLR Tied to VDD) .......................................... 57
Brown-out Reset (BOR) ........................................... 372 Time-out Sequence on Power-up
Bus Collision During a Repeated MCLR Not Tied to VDD, Case 1 ......................... 56
Start Condition (Case 1) .................................. 194 MCLR Not Tied to VDD, Case 2 ......................... 56
Bus Collision During a Repeated MCLR Tied to VDD, VDD Rise < TPWRT ............. 56
Start Condition (Case 2) .................................. 194 Timer0 and Timer1 External Clock .......................... 373
Bus Collision During a Start Transition for Entry to PRI_IDLE Mode ..................... 46
Condition (SCL = 0) ......................................... 193 Transition for Entry to SEC_RUN Mode .................... 43
Bus Collision During a Start Transition for Entry to Sleep Mode ............................ 45
Condition (SDA Only) ...................................... 192 Transition for Two-Speed Start-up
Bus Collision During a Stop (INTOSC to HSPLL) ........................................ 289
Condition (Case 1) ........................................... 195 Transition for Wake from Idle to Run Mode ............... 46
Bus Collision During a Stop Transition for Wake from Sleep (HSPLL) .................. 45
Condition (Case 2) ........................................... 195 Transition from RC_RUN Mode to
Bus Collision for Transmit and Acknowledge ........... 191 PRI_RUN Mode ................................................. 44
Capture/Compare/PWM (All CCP Modules) ............ 374 Transition from SEC_RUN Mode to
CLKO and I/O .......................................................... 371 PRI_RUN Mode (HSPLL) .................................. 43
Clock Synchronization ............................................. 177 Transition to RC_RUN Mode ..................................... 44
Clock/Instruction Cycle .............................................. 69 Type-A in 1/2 MUX, 1/2 Bias Drive .......................... 266
Example SPI Master Mode (CKE = 0) ..................... 375 Type-A in 1/2 MUX, 1/3 Bias Drive .......................... 268
Example SPI Master Mode (CKE = 1) ..................... 376 Type-A in 1/3 MUX, 1/2 Bias Drive .......................... 270
Example SPI Slave Mode (CKE = 0) ....................... 377 Type-A in 1/3 MUX, 1/3 Bias Drive .......................... 272
Example SPI Slave Mode (CKE = 1) ....................... 378 Type-A in 1/4 MUX, 1/3 Bias Drive .......................... 274
External Clock (All Modes Except PLL) ................... 369 Type-A/Type-B in Static Drive ................................. 265
Fail-Safe Clock Monitor ............................................ 291 Type-B in 1/2 MUX, 1/2 Bias Drive .......................... 267
High/Low-Voltage Detect Characteristics ................ 366 Type-B in 1/2 MUX, 1/3 Bias Drive .......................... 269
High-Voltage Detect Operation (VDIRMAG = 1) ...... 254 Type-B in 1/3 MUX, 1/2 Bias Drive .......................... 271
I2C Bus Data ............................................................ 379 Type-B in 1/3 MUX, 1/3 Bias Drive .......................... 273
I2C Bus Start/Stop Bits ............................................. 379 Type-B in 1/4 MUX, 1/3 Bias Drive .......................... 275
I2C Master Mode (7 or 10-Bit Transmission) ........... 188 USART Synchronous Receive (Master/Slave) ........ 383
I2C Master Mode (7-Bit Reception) .......................... 189 USART Synchronous Transmission
I2C Master Mode First Start Bit ................................ 185 (Master/Slave) ................................................. 383
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 174 Timing Diagrams and Specifications
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 179 A/D Conversion Requirements ................................ 385
I2C Slave Mode (10-Bit Transmission) ..................... 175 AC Characteristics - Internal RC Accuracy .............. 370
I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 172 Capture/Compare/PWM Requirements
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 178 (All CCP Modules) ........................................... 374
I2C Slave Mode (7-Bit Transmission) ....................... 173 CLKO and I/O Requirements ................................... 371
I2C Slave Mode General Call Address Example SPI Mode Requirements
Sequence (7 or 10-Bit Addressing Mode) ........ 180 (Master Mode, CKE = 0) .................................. 375
I2C Stop Condition Receive or Transmit Mode ........ 190 Example SPI Mode Requirements
LCD Interrupt Timing in Quarter-Duty Cycle Drive ... 276 (Master Mode, CKE = 1) .................................. 376
LCD Sleep Entry/Exit When SLPEN = 1 or Example SPI Mode Requirements
CS1:CS0 = 00 .................................................. 277 (Slave Mode, CKE = 0) .................................... 377
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 253 Example SPI Slave Mode Requirements
Master SSP I2C Bus Data ........................................ 381 (CKE = 1) ......................................................... 378
Master SSP I2C Bus Start/Stop Bits ........................ 381 External Clock Requirements .................................. 369
PWM Output ............................................................ 153 I2C Bus Data Requirements (Slave Mode) .............. 380
Repeat Start Condition ............................................. 186 I2C Bus Start/Stop Bits Requirements
Reset, Watchdog Timer (WDT), Oscillator Start-up (Slave Mode) ................................................... 379
Timer (OST) and Power-up Timer (PWRT) ..... 372 Master SSP I2C Bus Data Requirements ................ 382
Send Break Character Sequence ............................ 211 Master SSP I2C Bus Start/Stop Bits
Slave Synchronization ............................................. 163 Requirements .................................................. 381
Slow Rise Time (MCLR Tied to VDD, PLL Clock ................................................................ 370
VDD Rise > TPWRT) ............................................ 57 Reset, Watchdog Timer, Oscillator Start-up
SPI Mode (Master Mode) ......................................... 162 Timer, Power-up Timer and Brown-out
SPI Mode (Slave Mode, CKE = 0) ........................... 164 Reset Requirements ........................................ 372
SPI Mode (Slave Mode, CKE = 1) ........................... 164 Timer0 and Timer1 External
Synchronous Reception Clock Requirements ........................................ 373
(Master Mode, SREN) ............................. 214, 228 USART Synchronous Receive
Synchronous Transmission .............................. 212, 226 Requirements .................................................. 383
Synchronous Transmission USART Synchronous Transmission
(Through TXEN) ...................................... 213, 227 Requirements .................................................. 383

PIC18F6390/6490/8390/8490
Top-of-Stack Access .......................................................... 66 W
TSTFSZ ............................................................................ 335
Watchdog Timer (WDT) ........................................... 281, 287
Two-Speed Start-up ................................................. 281, 289
Associated Registers ............................................... 288
Two-Word Instructions
Control Register ....................................................... 287
Example Cases .......................................................... 70
During Oscillator Failure .......................................... 290
TXSTA1 Register
Programming Considerations .................................. 287
BRGH Bit ................................................................. 201
WCOL ...................................................... 185, 186, 187, 190
TXSTA2 Register
WCOL Status Flag ................................... 185, 186, 187, 190
BRGH Bit ................................................................. 220
WWW Address ................................................................ 409
V WWW, On-Line Support ...................................................... 5
Voltage Reference Specifications .................................... 365 X
XORLW ............................................................................ 335
XORWF ........................................................................... 336

PIC18FXX90
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PIC18F6390/6490/8390/8490
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QTP pattern #301.
b) PIC18F8490-I/PT = Industrial temp., TQFP
package, normal VDD limits.
Device(1), (2) PIC18F6390/6490/8390/8490, c) PIC18F8490-E/PT = Extended temp., TQFP
PIC18F6390/6490/8390/8490T; package, normal VDD limits.
VDD range 4.2V to 5.5V
PIC18LF6390/6490/8390/8490,
PIC18LF6390/6490/8390/8490T;
VDD range 2.0V to 5.5V
Temperature Range I = -40°C to +85°C (Industrial)

E = -40°C to +125°C (Extended)
Package PT = TQFP (Thin Quad Flatpack)

Note 1: F = Standard Voltage Range
LF = Wide Voltage Range
Pattern QTP, SQTP, Code or Special Requirements 2: T = In tape and reel
(blank otherwise)

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10/05/07

Pic18F6390/6490/8390/8490 Data Sheet: 64/80-Pin Flash Microcontrollers With LCD Driver and Nanowatt Technology

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PIC18F6390/6490/8390/8490

© 2007 Microchip Technology Inc. DS39629C

Information contained in this publication regarding device Trademarks

Microchip received ISO/TS-16949:2002 certification for its worldwide

DS39629C-page ii © 2007 Microchip Technology Inc.

Program Memory MSSP

Memory LCD 10-Bit CCP Timers

© 2007 Microchip Technology Inc. DS39629C-page 1

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

DS39629C-page 2 © 2007 Microchip Technology Inc.

Note 1: RE7 is the alternate pin for CCP2 multiplexing.

© 2007 Microchip Technology Inc. DS39629C-page 3

DS39629C-page 4 © 2007 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

© 2007 Microchip Technology Inc. DS39629C-page 5

DS39629C-page 6 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS39629C-page 7

DS39629C-page 8 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS39629C-page 9

Comparators CCP1 CCP2 MSSP EUSART1 AUSART2 LCD

DS39629C-page 10 © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. DS39629C-page 11

MCLR/VPP/RG5 7 Master Clear (input) or programming voltage (input).

DS39629C-page 12 © 2007 Microchip Technology Inc.

PORTA is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 13

PORTB is a bidirectional I/O port. PORTB can be software

DS39629C-page 14 © 2007 Microchip Technology Inc.

PORTC is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 15

PORTD is a bidirectional I/O port.

DS39629C-page 16 © 2007 Microchip Technology Inc.

PORTE is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 17

PORTF is a bidirectional I/O port.

DS39629C-page 18 © 2007 Microchip Technology Inc.

PORTG is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 19

MCLR/VPP/RG5 9 Master Clear (input) or programming voltage (input).

DS39629C-page 20 © 2007 Microchip Technology Inc.

PORTA is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 21

PORTB is a bidirectional I/O port. PORTB can be software

DS39629C-page 22 © 2007 Microchip Technology Inc.

PORTC is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 23

PORTD is a bidirectional I/O port.

DS39629C-page 24 © 2007 Microchip Technology Inc.

PORTE is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 25

PORTF is a bidirectional I/O port.

DS39629C-page 26 © 2007 Microchip Technology Inc.

PORTG is a bidirectional I/O port.

© 2007 Microchip Technology Inc. DS39629C-page 27

PORTH is a bidirectional I/O port.

DS39629C-page 28 © 2007 Microchip Technology Inc.

PORTJ is a bidirectional I/O port.