Pic 32 MX

PIC32MX3XX/4XX Family
Data Sheet
64/100-Pin General Purpose and USB
32-Bit Flash Microcontrollers
© 2008 Microchip Technology Inc. Preliminary DS61143E

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, rfPIC and SmartShunt are registered trademarks
MICROCHIP MAKES NO REPRESENTATIONS OR
of Microchip Technology Incorporated in the U.S.A. and other
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS61143E-page ii Preliminary © 2008 Microchip Technology Inc.

PIC32MX3XX/4XX
High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller
64/100-Pin General Purpose and USB
High-Performance 32-bit RISC CPU: • Separate PLLs for CPU and USB Clocks
• Two I2C™ Modules
• MIPS32® M4K™ 32-bit Core with 5-Stage Pipeline
• Two UART Modules with:
• 80 MHz Maximum Frequency
- RS-232, RS-485 and LIN 1.2 support
• 1.56 DMIPS/MHz (Dhrystone 2.1) Performance
at 0 Wait State Flash Access - IrDA® with On-Chip Hardware Encoder and
Decoder
• Single-Cycle Multiply and High-Performance
Divide Unit • Parallel Master and Slave Port (PMP/PSP) with
8-bit and 16-bit Data and Up to 16 Address Lines
• MIPS16e™ Mode for Up to 40% Smaller Code
Size • Hardware Real-Time Clock/Calendar (RTCC)
• User and Kernel Modes to Enable Robust • Five 16-bit Timers/Counters (two 16-bit pairs com-
Embedded System bine to create two 32-bit timers)
• Two Sets of 32 Core Register Files (32-bit) to • Five Capture Inputs
Reduce Interrupt Latency • Five Compare/PWM Outputs
• Prefetch Cache Module to Speed Execution from • Five External Interrupt Pins
Flash • High-Speed I/O Pins Capable of Toggling at Up to
80 MHz
Microcontroller Features: • High-Current Sink/Source (18 mA/18 mA) on
All I/O Pins
• Operating Voltage Range of 2.3V to 3.6V
• Configurable Open-Drain Output on Digital I/O
• 32K to 512K Flash Memory (plus an additional Pins
12KB of Boot Flash)
• 8K to 32K SRAM Memory Debug Features:
• Pin-Compatible with Most PIC24/dsPIC® Devices
• Multiple Power Management Modes • Two Programming and Debugging Interfaces:
• Multiple Interrupt Vectors with Individually - 2-Wire Interface with Unintrusive Access and
Programmable Priority Real-time Data Exchange with Application
• Fail-Safe Clock Monitor Mode - 4-wire MIPS Standard Enhanced JTAG
interface
• Configurable Watchdog Timer with On-Chip
Low-Power RC Oscillator for Reliable Operation • Unintrusive Hardware-Based Instruction Trace
• IEEE Std 1149.2 Compatible (JTAG) Boundary
Peripheral Features: Scan
• Atomic SET, CLEAR and INVERT Operation on Analog Features:

Select Peripheral Registers
• Up to 4-Channel Hardware DMA Controller with • Up to 16-Channel 10-bit Analog-to-Digital
Automatic Data Size Detection Converter:
• USB 2.0 Compliant Full Speed Device and - 500 ksps Conversion Rate
On-The-Go (OTG) Controller - Conversion Available During Sleep, Idle
• USB has a Dedicated DMA Channel • Two Analog Comparators
• 10 MHz to 40 MHz Crystal Oscillator • 5.5V Tolerant Input Pins (digital pins only)
• Internal 8 MHz and 32 kHz Oscillators
© 2008 Microchip Technology Inc. Preliminary DS61143E-page 1

PIC32MX3XX/4XX
FIGURE 1: PIC32MX PACKAGE OUTLINE DRAWING
TQFP 64-Pin
10 x 10 mm
TQFP 100-Pin
12 x 12 mm
TABLE 2: PIC32MX GENERAL PURPOSE – FEATURES

General Purpose
DMA Channels
Programmable
Comparators
PMP/PSP
Program/ Data Timers/ EUART/
VREG
Trace
JTAG
10-bit
Device Pins MHz Memory Capture/ SPI/
A/D (ch)
(KB) Compare I2C™
PIC32MX320F032H 64 40 32/8 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes

PIC32MX320F128L 100 80 128/16 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes
PIC32MX340F128L 100 80 128/32 5/5/5 4 Yes No 2/2/2 16 2 Yes Yes
PIC32MX360F256L 100 80 256/32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes
PIC32MX360F512L 100 80 512/32 5/5/5 4 Yes Yes 2/2/2 16 2 Yes Yes
TABLE 3: PIC32MX USB – FEATURES

USB
Dedicated USB
DMA Channels
DMA Channels
Programmable
Comparators
PMP/PSP
Program/Data Timers/ EUART/

VREG
Trace
JTAG
10-bit
Device Pins MHz Memory Capture/ SPI/
2 A/D (ch)
(KB) Compare I C™
PIC32MX420F032H 64 80 32/8 5/5/5 0 2 Yes No 2/1/2 16 2 Yes Yes

PIC32MX440F128L 100 80 128/32 5/5/5 4 2 Yes No 2/2/2 16 2 Yes Yes
PIC32MX460F256L 100 80 256/32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes
PIC32MX460F512L 100 80 512/32 5/5/5 4 2 Yes Yes 2/2/2 16 2 Yes Yes
DS61143E-page 2 Preliminary © 2008 Microchip Technology Inc.

PIC32MX3XX/4XX
Pin Diagram (64-Pin General Purpose)
64-Pin TQFP (General Purpose)
PMWR/OC5/IC5/CN13/RD4
PMRD/CN14/RD5
VCAP/VDDCORE
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
CN16/RD7
CN15/RD6
OC4/RD3
OC3/RD2
OC2/RD1
ENVREG
RF1
RF0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1 48 SOSCO/T1CK/CN0/RC14
PMD5/RE5
47 SOSCI/CN1/RC13
PMD6/RE6 2
PMD7/RE7 46 OC1/RD0
3
PMA5/SCK2/CN8/RG6 4 45 IC4/PMCS1/PMA14/INT4/RD11
PMA4/SDI2/CN9/RG7 5 44 IC3/PMCS2/PMA15/INT3/RD10
PMA3/SDO2/CN10/RG8 6 43 IC2/U1CTS/INT2/RD9
MCLR 7 42 IC1/RTCC/INT1/RD8
PMA2/SS2/CN11/RG9 8 PIC32MX3XXH 41 Vss
VSS 9 40 OSC2/CLKO/RC15
VDD 10 39 OSC1/CLKI/RC12
C1IN+/AN5/CN7/RB5 11 38 VDD
C1IN-/AN4/CN6/RB4 12 37 SCL1/RG2
C2IN+/AN3/CN5/RB3 13 36 SDA1/RG3
C2IN-/AN2/SS1/CN4/RB2 14 35 U1RTS/BCLK1/SCK1/INT0/RF6
PGC1/EMUC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 U1RX/SDI1/RF2
PGD1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0 16 33 U1TX/SDO1/RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
PMALL/PMA0/AN15/OCFB/CN12/RB15
PGD2/EMUD2/AN7/RB7
PGC2/EMUC2/AN6/OCFA/RB6
AVDD
U2CTS/C1OUT/AN8/RB8
PMA7/C2OUT/AN9/RB9
TDO/PMA12/AN11/RB11
TCK/PMA11/AN12/RB12
PMALH/PMA1/U2RTS/BCLK2/AN14/RB14
PMA9/U2RX/SDA2/CN17/RF4
PMA8/U2TX/SCL2/CN18/RF5
TMS/CVREFOUT/PMA13/AN10/RB10
VDD
TDI/PMA10/AN13/RB13
AVSS

PIC32MX3XX/4XX
Pin Diagram (100-Pin General Purpose)
100-Pin TQFP (General Purpose)
PMWR/OC5/CN13/RD4
PMD13/CN19/RD13
PMD15/CN16/RD7
PMD14/CN15/RD6
PMRD/CN14/RD5
PMD12/IC5/RD12
VCAP/VDDCORE
TRD0/RG13
TRD1/RG12
TRD2/RG14
TRCLK/RA6
PMD10/RF1
PMD11/RF0
PMD8/RG0
PMD9/RG1
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
TRD3/RA7
OC4/RD3
OC3/RD2
OC2/RD1
ENVREG
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RG15 1 75 VSS
VDD 2 74 SOSCO/T1CK/CN0/RC14
PMD5/RE5 3 73 SOSCI/CN1/RC13
PMD6/RE6 4 72 OC1/RD0
PMD7/RE7 5 71 IC4/PMCS1/PMA14/RD11
T2CK/RC1 6 70 IC3/PMCS2/PMA15/RD10
T3CK/RC2 7 69 IC2/RD9
T4CK/RC3 8 68 IC1/RTCC/RD8
T5CK/RC4 9 67 INT4/RA15
PMA5/SCK2/CN8/RG6 10 66 INT3/RA14
PMA4/SDI2/CN9/RG7 11 65 VSS
PMA3/SDO2/CN10/RG8 12 64 OSC2/CLKO/RC15
MCLR 13 PIC32MX3XXL 63 OSC1/CLKI/RC12
PMA2/SS2/CN11/RG9 14 62 VDD
VSS 15 61 TDO/RA5
VDD 16 60 TDI/RA4
TMS/RA0 17 59 SDA2/RA3
INT1/RE8 18 58 SCL2/RA2
INT2/RE9 19 57 SCL1/RG2
C1IN+/AN5/CN7/RB5 20 56 SDA1/RG3
C1IN-/AN4/CN6/RB4 21 55 SCK1/INT0/RF6
C2IN+/AN3/CN5/RB3 22 54 SDI1/RF7
C2IN-/AN2/SS1/CN4/RB2 23 53 SDO1/RF8
PGC1/EMUC1/AN1/CN3/RB1 24 52 U1RX/RF2
PGD1/EMUD1/AN0/CN2/RB0 25 51 U1TX/RF3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
CVREFOUT/PMA13/AN10/RB10
PMA9/U2RX/CN17/RF4
PMA7/VREF-/CVREF-/RA9
PMA6/VREF+/CVREF+/RA10
C1OUT/AN8/RB8
C2OUT/AN9/RB9
PMA12/AN11/RB11
TCK/RA1
U2RTS/BCLK2/RF13
U2CTS/RF12
PMA11/AN12/RB12
PMA10/AN13/RB13
PMALH/PMA1/AN14/RB14
CN20/U1CTS/RD14
U1RTS/BCLK1/CN21/RD15
PMA8/U2TX/CN18/RF5
PGD2/EMUD2/AN7/RB7
AVSS
VSS
AVDD
VDD

PIC32MX3XX/4XX
Pin Diagram (64-Pin USB)
64-Pin TQFP (USB)
PMWR/OC5/IC5/CN13/RD4
OC2/U1RTS/BCLK1/RD1
PMRD/CN14/RD5
OC3/U1RX/RD2
OC4/U1TX/RD3
VCAP/VDDCORE
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
CN16/RD7
CN15/RD6
ENVREG
RF1
RF0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1 48 SOSCO/T1CK/CN0/RC14
PMD5/RE5
47 SOSCI/CN1/RC13
PMD6/RE6 2
PMD7/RE7 46 OC1/INT0/RD0
3
PMA5/SCK2/CN8/RG6 45 IC4/PMCS1/PMA14/INT4/RD11
4
PMA4/SDI2/CN9/RG7 5 44 IC3/PMCS2/PMA15/INT3/SCL1/RD10
PMA3/SDO2/CN10/RG8 6 43 IC2/U1CTS//INT2/SDA1/RD9
MCLR 7 42 IC1/RTCC/INT1/RD8
PMA2/SS2/CN11/RG9 8 PIC32MX4XXH 41 Vss
VSS 9 40 OSC2/CLKO/RC15
VDD 10 39 OSC1/CLKI/RC12
VBUSON/C1IN+/AN5/CN7/RB5 11 38 VDD
C1IN-/AN4/CN6/RB4 12 37 D+/RG2
C2IN+/AN3/CN5/RB3 13 36 D-/RG3
C2IN-/AN2/CN4/RB2 14 35 VUSB
PGC1/EMUC1/AN1/VREF-/CVREF-/CN3/RB1 15 34 VBUS
PGD1/EMUD1/PMA6/AN0/VREF+/CVREF+/CN2/RB0 16 33 USBID/RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGD2/EMUD2/AN7/RB7
U2CTS/C1OUT/AN8/RB8
PMA7/C2OUT/AN9/RB9
TMS/CVREFOUT/PMA13/AN10/RB10
TDO/PMA12/AN11/RB11
TCK/PMA11/AN12/RB12
TDI/PMA10/AN13/RB13
PMALH/PMA1/U2RTS/BCLK2/AN14/RB14
PMA9/U2RX/SDA2/CN17/RF4
PMA8/U2TX/SCL2/CN18/RF5
VSS
AVDD
VDD
AVSS

PIC32MX3XX/4XX
Pin Diagram (100-Pin USB)
100-Pin TQFP (USB)
PMWR/OC5/CN13/RD4
PMD13/CN19/RD13
PMD15/CN16/RD7
PMD14/CN15/RD6
PMRD/CN14/RD5
PMD12/IC5/RD12
VCAP/VDDCORE
TRD0/RG13
TRD1/RG12
TRD2/RG14
TRCLK/RA6
PMD10/RF1
PMD11/RF0
PMD8/RG0
PMD9/RG1
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
TRD3/RA7
OC4/RD3
OC3/RD2
OC2/RD1
ENVREG
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RG15 1 75 VSS
VDD 2 74 SOSCO/T1CK/CN0/RC14
PMD5/RE5 3 73 SOSCI/CN1/RC13
PMD6/RE6 4 72 SDO1/OC1/INT0/RD0
PMD7/RE7 5 71 IC4/PMCS1/PMA14/RD11
T2CK/RC1 6 70 IC3/SCKI/PMCS2/PMA15/RD10
T3CK/RC2 7 69 IC2/SS1/RD9
T4CK/RC3 8 68 IC1/RTCC/RD8
SDI1/T5CK/RC4 9 67 SDA1/INT4/RA15
PMA5/SCK2/CN8/RG6 10 66 SCL1/INT3/RA14
PMA4/SDI2/CN9/RG7 11 65 VSS
PMA3/SDO2/CN10/RG8 12 64 OSC2/CLKO/RC15
MCLR 13 PIC32MX4XXL 63 OSC1/CLKI/RC12
PMA2/SS2/CN11/RG9 14 62 VDD
VSS 15 61 TDO/RA5
VDD 16 60 TDI/RA4
TMS/RA0 17 59 SDA2/RA3
INT1/RE8 18 58 SCL2/RA2
INT2/RE9 19 57 D+/RG2
VBUSON/C1IN+/AN5/CN7/RB5 20 56 D-/RG3
C1IN-/AN4/CN6/RB4 21 55 VUSB
C2IN+/AN3/CN5/RB3 22 54 VBUS
C2IN-/AN2/CN4/RB2 23 53 U1TX/RF8
PGC1/EMUC1/AN1/CN3/RB1 24 52 U1RX/RF2
PGD1/EMUD1/AN0/CN2/RB0 25 51 USBID/RF3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PGD2/EMUD2/AN7/RB7
PMA7/VREF-/CVREF-/RA9
PMA10/AN13/RB13
U2RTS/BCLK2/RF13
U2CTS/RF12
PMA11/AN12/RB12
PMALH/PMA1/AN14/RB14
PMA6/VREF+/CVREF+/RA10
AVDD
C1OUT/AN8/RB8
C2OUT/AN9/RB9
CVREFOUT/PMA13/AN10/RB10
PMA12/AN11/RB11
VDD
TCK/RA1
CN20/U1CTS/RD14
U1RTS/BCLK1/CN21/RD15
PMA9/U2RX/CN17/RF4
PMA8/U2TX/CN18/RF5
AVSS
VSS

PIC32MX3XX/4XX
Table of Contents
High-Performance 80 MHz MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose and USB ..................................... 1
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 PIC32MX MCU........................................................................................................................................................................... 33
3.0 Instruction Set ............................................................................................................................................................................ 47
4.0 Oscillators................................................................................................................................................................................... 53
5.0 Resets ........................................................................................................................................................................................ 83
6.0 Memory Organization ................................................................................................................................................................. 93
7.0 Flash Program Memory............................................................................................................................................................ 115
8.0 Interrupts .................................................................................................................................................................................. 125
9.0 Prefetch Cache......................................................................................................................................................................... 177
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 197
11.0 USB On-The-Go....................................................................................................................................................................... 241
12.0 I/O Ports ................................................................................................................................................................................... 305
13.0 Timer1 ...................................................................................................................................................................................... 327
14.0 Timers 2, 3, 4, 5 ....................................................................................................................................................................... 339
15.0 Input Capture............................................................................................................................................................................ 355
16.0 Output Compare....................................................................................................................................................................... 365
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 383
18.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 409
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 425
20.0 Parallel Master Port.................................................................................................................................................................. 439
21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 467
22.0 Analog-Digital Converter .......................................................................................................................................................... 489
23.0 Power Saving ........................................................................................................................................................................... 521
24.0 Comparator .............................................................................................................................................................................. 537
25.0 Comparator Reference............................................................................................................................................................. 549
26.0 Watchdog Timer ....................................................................................................................................................................... 555
27.0 Special Features ...................................................................................................................................................................... 565
28.0 Programming and Diagnostics ................................................................................................................................................. 577
29.0 Development Support............................................................................................................................................................... 589
30.0 Electrical Characteristics .......................................................................................................................................................... 593
31.0 Packaging Information.............................................................................................................................................................. 631
Index .................................................................................................................................................................................................. 641
Worldwide Sales and Service ............................................................................................................................................................ 644

PIC32MX3XX/4XX
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PIC32MX3XX/4XX
64/100-Pin General Purpose and USB,
32-bit Flash Microcontrollers
1.0 DEVICE OVERVIEW 1.2 Core Features

This document contains device specific information for 1.2.1 32-BIT RISC ARCHITECTURE
the following devices:
Central to all PIC32MX3XX/4XX devices is the 32-bit
• PIC32MX320F032H MIPS32 M4K CPU core, offering a wide range of
• PIC32MX320F064H features, including the following:
• PIC32MX320F128H • Up to 1.56 DMIPS/MHz
• PIC32MX320F128L • 32-bit Address and Data paths
• PIC32MX340F128H • 32-bit Linear (program space) addressing
• PIC32MX340F128L • (2) thirty-two element 32-bit core register files
• PIC32MX340F256H • Single-cycle multiply and high-performance divide
• PIC32MX340F512H unit for 32-bit integer math
• PIC32MX360F256L • 16 and 32-bit instructions, optimized for
• PIC32MX360F512L high-level languages, such as ‘C’.
• PIC32MX420F032H
• PIC32MX440F256H 1.3 Power-Saving Technology
• PIC32MX440F128H All of the devices in the PIC32MX family incorporate a
• PIC32MX440F128L range of features that can significantly reduce power
• PIC32MX440F512H consumption during operation. Key features include:
• PIC32MX460F256L • On-the-Fly Clock Switching: The device clock
• PIC32MX460F512L can be changed under software control to any of
the four clock sources during operation.
This family introduces a new line of Microchip devices:
a 32-bit RISC microcontroller family with a broad • Instruction-Based Power-Saving Modes: The
peripheral feature set and enhanced computational microcontroller can suspend all operations, or
performance. The PIC32MX3XX/4XX family offers a selectively shut down its core while leaving its
new migration option for those high-performance appli- peripherals active, with a single instruction in
cations which may be outgrowing their 16-bit platforms. software.
1.1 Easy Migration 1.4 Communications

The PIC32MX incorporates a range of serial communi-
The PIC32MX family of microcontrollers was designed cation peripherals to handle a range of application
to provide an easy migration path as the application requirements. All devices are equipped with two inde-
needs change. pendent UARTs with built-in IrDA encoder/decoders.
The consistent pinout scheme used throughout the There are also two independent SPI modules, and two
entire family aids in migrating to the next larger device. independent I2C modules that support both Master and
This is true when moving between devices with the Slave modes of operation.
same pin count, or even jumping from 64-pin to 100-pin
devices. 1.5 10-bit A/D Converter
The PIC32MX family is pin and peripheral compatible
The A/D Converter features 500 ksps maximum sample
with Microchip PIC24FJ128GA010 devices.
rate. This configurable module incorporates a user-
selectable scan list and auto-convert functions to allow
acquisitions without processor intervention. Multiple A/D
trigger sources are user-selectable: timer event, external
pin, manual and auto-convert.

PIC32MX3XX/4XX
1.6 External Interface
A Parallel Master Port Parallel Slave Port enables 8/16-
bit parallel data communications in Master mode with
up to 16 address lines; 8-bit Slave modes are also
supported.
1.7 Real-Time Clock/Calendar

This module implements a full-featured clock and
calendar with alarm functions in hardware, freeing up
timer resources and program memory space for use of
the core application.
1.8 Oscillator Options and Features

All of the devices in the PIC32MX family offer four
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• A Primary Oscillator (POSC) with two External
Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes with selectable
peripheral bus clock output.
• A Fast Internal Oscillator (FRC) with a nominal
8 MHz output.
• On-board postscalers and/or PLL to provide clock
speeds ranging from 31 kHz to maximum
specified frequency.
• A Secondary Oscillator (SOSC) designed to
operate with an external 32.768 kHz crystal. This
oscillator can also be used with Timer1 and the
integrated RTCC.
• An Internal Low-Power RC oscillator (LPRC)
having a fixed 31 kHz output, which provides a
low-power option for timing-insensitive
applications.
The oscillator block also provides a stable reference
source for the user-controlled Fail-Safe Clock Monitor.
This option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.

PIC32MX3XX/4XX
1.9 Device Features, Block Diagrams
and Pinout Tables
TABLE 1-1: DEVICE FEATURES, BLOCK DIAGRAMS AND PINOUT TABLES
PIC32MX320F032H
PIC32MX320F064H
PIC32MX320F128H
PIC32MX340F256H
PIC32MX320F128L
PIC32MX360F256L
PIC32MX360F512L
Features
Operating Frequency DC – 40 MHz DC – 80 MHz

Program Memory (Bytes) 32K 64K 128K 256K 128K 256K 512K
Data Memory (Bytes) 8K 16K 16K 32K 16K 32K 32K
Interrupt Sources/Vectors 95 / 63
I/O Ports Ports B, C, D, E, F, G Ports A, B, C, D, E, F, G
Total I/O Pins 53 85
DMA Channels 0 4 0 4
Timers:
Total number (16-bit) 5
32-bit (paired 16-bit) 2
32-bit core timer 1
Input Capture Channels 5
Output Compare/PWM 5
Channels
Input Change Interrupt 19 22
Notification
Serial Communications:
Enhanced UART 2
SPI (3-wire/4-wire) 2
2C™
I 2
Parallel Communications Yes, 8-bit only Yes, 8-bit/16-bit
(PMP/PSP)
JTAG Boundary Scan Yes
JTAG Debug and Program Yes
ICSP™ 2-Wire Debug and Yes
Program
Instruction Trace No Yes
Hardware Break Points 6 Instruction, 2 Data
10-bit Analog-to-Digital 16
Module (input channels)
Analog Comparators 2
Internal LDO Yes
Resets (and delays) POR, BOR, MCLR, WDT, SWR (Software Reset), CM (Configuration Bit Mismatch)
(PWRT, OST, PLL Lock)
Instruction Support MIPS32® Enhanced Architecture (Release 2)
MIPS16e™ Code Compression
Packages 64-pin TQFP 100-pin TQFP

PIC32MX3XX/4XX
TABLE 1-2: DEVICE FEATURES FOR THE PIC32MX3XXFXXX GENERAL PURPOSE FAMILY
PIC32MX340F128H
PIC32MX340F512H
PIC32MX340F128L
Features
Operating Frequency DC – 80 MHz

Program Memory (Bytes) 128K 512K 128K
Data Memory (Bytes) 32K 32K 32K
Interrupt Sources/Vectors 95 / 63
DMA Channels 4
Timers:
32-bit (paired 16-bit) 2
32-bit core timer 1
Output Compare/PWM Channels 5
Input Change Interrupt Notification 19 22
Enhanced UART 2
SPI (3-wire/4-wire) 2
2C™
I 2
Parallel Communications (PMP/PSP) Yes, 8-bit only Yes, 8-bit/16-bit
ICSP™ 2-Wire Debug and Program Yes
Instruction Trace No
Hardware Break Points 6 Instruction, 2 Data
10-bit Analog-to-Digital Module (input 16
channels)
Internal LDO Yes
Resets (and delays) POR, BOR, MCLR, WDT, SWR (Software Reset), CM (Configuration Bit
Mismatch)
Instruction Support MIPS32® Enhanced Architecture (Release 2)

PIC32MX3XX/4XX
TABLE 1-3: DEVICE FEATURES FOR THE PIC32MX4XXFXXX USB FAMILY
PIC32MX420F032H
PIC32MX440F128H
PIC32MX440F256H
PIC32MX440F512H
PIC32MX440F128L
PIC32MX460F256L
PIC32MX460F512L
Features
Operating Frequency DC – 40 DC – 80 MHz

MHz
Program Memory (Bytes) 32K 128K 256K 512K 128K 256K 512K
Data Memory (Bytes) 8K 32K 32K 32K 32K 32K 32K
Interrupt Sources / Vectors 95 / 63
DMA Channels 0 + 2 USB 4 + 2 USB
Timers:
32-bit (from paired 16-bit 2
timers)
32-bit Core Timer 1
Output Compare/PWM 5
Channels
Input Change Interrupt 19 22
Notification
Enhanced UART 2
SPI (3-wire/4-wire) 1 2
I2C™ 2
Parallel Communications Yes, 8-bit only Yes, 8-bit/16-bit
(PMP/PSP)
ICSP 2-wire Debug and Yes
Program
Instruction Trace No Yes
Hardware Break Points: 6 Instruction, 2 Data
10-bit Analog-to-Digital 16
Module (input channels)
Internal LDO Yes
Resets (and Delays) POR, BOR, MCLR, WDT, SWR (Software Reset), CM (Configuration Bit Mismatch)
Instruction Support MIPS32 Enhanced Architecture (Release 2)

PIC32MX3XX/4XX
FIGURE 1-1: PIC32MX3XX BLOCK DIAGRAM (GENERAL PURPOSE)
VDDCORE/VCAP
OSC2/CLKO OSC/SOSC
OSC1/CLKI Oscillators Power-up VDD, VSS
Timer
FRC/LPRC ENVREG MCLR
Oscillators Voltage Oscillator
Regulator Start-up Timer
PLL
Power-on
Precision Reset
DIVIDERS Band Gap
Reference
Watchdog
Timer
SYSCLK
Timing Brown-out
Generation PBCLK Reset(3)
Peripheral Bus Clocked by SYSCLK
CN1-22(1)
PORTA(1,4)
JTAG Interrupt
BSCAN Controller
PWM
OC1-5
PORTB
Peripheral Bus Clocked by PBCLK

EJTAG INT
DMAC(2) ICD
32
IC1-5
MIPS32® M4K™ CPU Core
PORTC(1)
IS DS
32 32 SPI1,2(1)
32
32 32
(1)
PORTD
Bus Matrix
I2C1,2
32 32 32
32
PORTE(1)
Prefetch
Peripheral Bridge PMP(1)
Module(2) Data RAM
PORTF(1)
128 UART1,2
Controller
Flash
128-bit Wide
PORTG(1) Program Flash Memory
Comparators
Timer1 Timer2 Timer3 Timer4 Timer5 RTCC 10-bit ADC
Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-4 for I/O port pin descriptions.
2: Some features are not available on certain devices.
3: BOR functionality is provided when the on-board voltage regulator is enabled.
4: PORTA is not present on 64-pin devices

PIC32MX3XX/4XX
FIGURE 1-2: PIC32MX4XX BLOCK DIAGRAM (USB)
VDDCORE/VCAP
OSC2/CLKO OSC/SOSC
OSC1/CLKI Oscillators Power-up VDD, VSS
Timer
FRC/LPRC ENVREG MCLR
Oscillators Voltage(1) Oscillator
Regulator Start-up Timer
PLL
Power-on
Precision Reset
DIVIDERS Band Gap
Reference
PLL-USB Watchdog
USBCLK Timer
SYSCLK Brown-out
Timing
Generation PBCLK Reset(2)
Peripheral Bus Clocked by SYSCLK
CN1-22(1)
PORTA(1,4)
Priority
JTAG Interrupt
BSCAN Controller
PWM
OC 1,5
PORTB

EJTAG INT
USB DMAC(1) ICD
32
IC 1,5
MIPS M4K CPU Core
PORTC(1)
IS DS
32 32 32 SPI 1,2(1)
32
32 32
PORTD(1)
Bus Matrix
I2C 1,2
32 32 32
32
PORTE(1)
Pre-Fetch
Peripheral Bridge PMP(1)
Module(1) Data RAM
PORTF(1)
128 UART 1,2
Controller
Flash
128-bit wide
PORTG(1) Program Flash Memory
Comparators
Timer1 Timer2 Timer3 Timer4 Timer5 RTCC 10-bit ADC
Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-5 for I/O port pin descriptions.
2: Some features are not available on certain device variants.
3: BOR functionality is provided when the on-board voltage regulator is enabled.
4: PORTA is not present on 64 pin devices

PIC32MX3XX/4XX
TABLE 1-4: PIC32MX3XX/4XX PINOUT DESCRIPTIONS – GENERAL PURPOSE
Pin Number Input
Function I/O Description
64-pin 100-pin Buffer
AN0 16 25 I ANA A/D Analog Inputs

AN1 15 24 I ANA
AN2 14 23 I ANA
AN3 13 22 I ANA
AN4 12 21 I ANA
AN5 11 20 I ANA
AN6 17 26 I ANA
AN7 18 27 I ANA
AN8 21 32 I ANA
AN9 22 33 I ANA
AN10 23 34 I ANA
AN11 24 35 I ANA
AN12 27 41 I ANA
AN13 28 42 I ANA
AN14 29 43 I ANA
AN15 30 44 I ANA
AVDD 19 30 P — Positive Supply for Analog Modules
AVSS 20 31 P — Ground Reference for Analog Modules
BCLK1 35 48 O — UART1 IrDA® Baud Clock
BCLK2 29 39 O — UART2 IrDA Baud Clock
C1IN- 12 21 I ANA Comparator 1 Negative Input
C1IN+ 11 20 I ANA Comparator 1 Positive Input
C1OUT 21 32 O — Comparator 1 Output
CLKI 39 63 I ANA Main Clock Input Connection
CLKO 40 64 O — System Clock Output
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I2C™ = I2C/SMBus input buffer
Note: In some cases, I/O pins are multiplexed with more than one peripheral. In general, the dominant output control of a
multiplexed I/O pin can be determined by the order of the peripheral output names assigned to a pin (read from left to
right). Multiplexed peripheral inputs have no priority.

PIC32MX3XX/4XX
TABLE 1-4: PIC32MX3XX/4XX PINOUT DESCRIPTIONS – GENERAL PURPOSE (CONTINUED)
Pin Number Input
CN0 48 74 I ST Interrupt-on-Change Inputs

CN1 47 73 I ST
CN2 16 25 I ST
CN3 15 24 I ST
CN4 14 23 I ST
CN5 13 22 I ST
CN6 12 21 I ST
CN7 11 20 I ST
CN8 4 10 I ST
CN9 5 11 I ST
CN10 6 12 I ST
CN11 8 14 I ST
CN12 30 44 I ST
CN13 52 81 I ST
CN14 53 82 I ST
CN15 54 83 I ST
CN16 55 84 I ST
CN17 31 49 I ST
CN19 — 80 I ST
CN20 — 47 I ST
CN21 — 48 I ST
CVREF- 15 28 I ANA Comparator Reference Voltage (Low) Input
CVREF+ 16 29 I ANA Comparator Reference Voltage (High) Input
CVREFOUT 23 34 O ANA Comparator Voltage Reference Output
EMUC1 15 24 I/O ST In-Circuit Emulator Clock Input/Output
EMUD1 16 25 I/O ST In-Circuit Emulator Data Input/Output
ENVREG 57 86 I ST Enable for On-Chip Voltage Regulator
IC1 42 68 I ST Input Capture Inputs
IC2 43 69 I ST
IC3 44 70 I ST
IC4 45 71 I ST
IC5 52 79 I ST
INT0 35 55 I ST External Interrupt Inputs
INT1 42 18 I ST
INT2 43 19 I ST
INT3 44 66 I ST
INT4 45 67 I ST
MCLR 7 13 I ST Master Clear (Device Reset) Input. Bring this line low to cause a
Reset.

PIC32MX3XX/4XX
Pin Number Input
OC1 46 72 O — Output Compare/PWM Outputs

OC2 49 76 O —
OC3 50 77 O —
OC4 51 78 O —
OC5 52 81 O —
OCFA 17 26 I ST Output Compare Fault A Input
OCFB 30 44 I ST Output Compare Fault B Input
OSC1 39 63 I ANA Main Oscillator Input Connection
OSC2 40 64 O ANA Main Oscillator Output Connection.
PGC1 15 24 I/O ST In-Circuit Debugger and ICSP™ Programming Clock
PGD1 16 25 I/O ST In-Circuit Debugger and ICSP Programming Data
PMALL 30 44 O — Parallel Master Port Address Latch Enable low-byte
(Multiplexed Master modes)
PMALH 29 43 O — Parallel Master Port Address Latch Enable high-byte
(Multiplexed Master modes)
PMA0 30 44 O — Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes)
PMA2 8 14 O — Parallel Master Port Address (Demultiplexed Master modes)
PMA3 6 12 O —
PMA4 5 11 O —
PMA5 4 10 O —
PMA6 16 29 O —
PMA7 22 28 O —
PMA8 32 50 O —
PMA9 31 49 O —
PMA10 28 42 O —
PMA11 27 41 O —
PMA12 24 35 O —
PMA13 23 34 O —
PMA14 45 71 O —
PMA15 44 70 O —
PMCS1 45 71 O — Parallel Master Port Chip Select 1 Strobe

PIC32MX3XX/4XX
Pin Number Input
PMD0 60 93 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
PMD1 61 94 I/O ST/TTL Address/Data (Multiplexed Master modes)
PMD2 62 98 I/O ST/TTL

PMD5 1 3 I/O ST/TTL
PMD6 2 4 I/O ST/TTL
PMD7 3 5 I/O ST/TTL
PMD8 — 90 I/O ST/TTL
PMENB 52 81 O — Parallel Master Port Enable Strobe (Master Mode 1)
PMRD 53 82 O — Parallel Master Port Read Strobe (Master Mode 2)
PMRD/PMWR 53 82 O — Parallel Master Port Read/Write Strobe (Master Mode 1)
PMWR 52 81 O — Parallel Master Port Write Strobe (Master Mode 2)

PIC32MX3XX/4XX
Pin Number Input
RA0 — 17 I/O ST PORTA Digital I/O

RA1 — 38 I/O ST Notes: On 100-pin devices, JTAG program/debug port is multi-
RA2 — 58 I/O ST plexed with port pins RA0, RA1, RA4 and RA5. At Reset,
these pins are controlled by the JTAG port. To use these
RA3 — 59 I/O ST pins for general purpose I/O, the user’s application code
RA4 — 60 I/O ST must clear JTAGEN (DDPCON<3>) bit = 0. To use these
RA5 — 61 I/O ST pins for JTAG program/debug, the user’s application
code must maintain JTAGEN bit = 1.
RA6 — 91 I/O ST
On specific 100-pin devices, the instruction TRACE port
RA7 — 92 I/O ST
is multiplexed with PORTA pins RA6, RA7; PORTG pins
RA9 — 28 I/O ST RG12, RG13 and RG14. At Power-on Reset, these pins
RA10 — 29 I/O ST are general purpose I/O pins. To maintain these pins as
general purpose I/O pins, the user’s application code
RA14 — 66 I/O ST
must maintain TROEN (DDPCON<2>) bit = 0. To use
RA15 — 67 I/O ST these pins as instruction TRACE pins, TROEN must be
set = 1.
RB0 16 25 I/O ST PORTB Digital I/O
RB1 15 24 I/O ST Note: On 64-pin devices, JTAG program/debug port is multi-
RB2 14 23 I/O ST plexed with port pins RB10, RB11, RB12 and RB13. At
Reset, these pins are controlled by the JTAG port. To use
RB3 13 22 I/O ST
these pins for general purpose I/O, the user’s application
RB4 12 21 I/O ST code must clear JTAGEN (DDPCON<3>) bit = 0. To use
RB5 11 20 I/O ST these pins for JTAG program/debug, the user’s
application code must maintain JTAGEN bit = 1.
RB6 17 26 I/O ST
RB7 18 27 I/O ST
RB8 21 32 I/O ST
RB9 22 33 I/O ST
RB10 23 34 I/O ST
RB11 24 35 I/O ST
RB12 27 41 I/O ST
RB13 28 42 I/O ST
RB14 29 43 I/O ST
RB15 30 44 I/O ST
RC1 — 6 I/O ST PORTC Digital I/O
RC2 — 7 I/O ST
RC3 — 8 I/O ST
RC4 — 9 I/O ST
RC12 39 63 I/O ST
RC13 47 73 I/O ST
RC14 48 74 I/O ST
RC15 40 64 I/O ST

PIC32MX3XX/4XX
Pin Number Input
RD0 46 72 I/O ST PORTD Digital I/O

RD1 49 76 I/O ST
RD2 50 77 I/O ST
RD3 51 78 I/O ST
RD4 52 81 I/O ST
RD5 53 82 I/O ST
RD6 54 83 I/O ST
RD7 55 84 I/O ST
RD8 42 68 I/O ST
RD9 43 69 I/O ST
RD10 44 70 I/O ST
RD11 45 71 I/O ST
RD12 — 79 I/O ST
RD13 — 80 I/O ST
RD14 — 47 I/O ST
RD15 — 48 I/O ST
RE0 60 93 I/O ST PORTE Digital I/O
RE1 61 94 I/O ST
RE2 62 98 I/O ST
RE3 63 99 I/O ST
RE4 64 100 I/O ST
RE5 1 3 I/O ST
RE6 2 4 I/O ST
RE7 3 5 I/O ST
RE8 — 18 I/O ST
RE9 — 19 I/O ST
RF0 58 87 I/O ST PORTF Digital I/O
RF1 59 88 I/O ST
RF2 34 52 I/O ST
RF3 33 51 I/O ST
RF4 31 49 I/O ST
RF5 32 50 I/O ST
RF6 35 55 I/O ST
RF7 — 54 I/O ST
RF8 — 53 I/O ST
RF12 — 40 I/O ST
RF13 — 39 I/O ST

PIC32MX3XX/4XX
Pin Number Input
RG0 — 90 I/O ST PORTG Digital I/O

RG1 — 89 I/O ST
RG2 37 57 I/O ST Note: On specific 100-pin devices, the Instruction TRACE port
RG3 36 56 I/O ST
RG12, RG13, and RG14. At power-on-reset, these pins
RG6 4 10 I/O ST are general purpose I/O pins. To maintain these pins as
RG7 5 11 I/O ST general purpose I/O pins, the user’s application code
RG8 6 12 I/O ST
these pins as Instruction TRACE pins, TROEN must be
RG9 8 14 I/O ST set = 1.
RG12 — 96 I/O ST
RG13 — 97 I/O ST
RG14 — 95 I/O ST
RG15 — 1 I/O ST
RTCC 42 68 O — Real-Time Clock Alarm Output
SCK1 35 55 O — SPI1 Serial Clock Output
SCK2 4 10 I/O ST SPI2 Serial Clock Output
SCL1 37 57 I/O I2C I2C1 Synchronous Serial Clock Input/Output
SCL2 32 58 I/O I2C I2C2 Synchronous Serial Clock Input/Output.
SDA1 36 56 I/O I2C I2C1 Data Input/Output
2
SDA2 31 59 I/O I C I2C2 Data Input/Output
SDI1 34 54 I ST SPI1 Serial Data Input
SDO1 33 53 O — SPI1 Serial Data Output
SOSCI 47 73 I ANA Secondary Oscillator/Timer1 External Clock Input
SOSCO 48 74 O ANA Secondary Oscillator/Timer1 External Clock Output
SS1 14 23 I/O ST Slave Select Input/Frame Select Output (SPI1)
T1CK 48 74 I ST Timer1 External Clock Input
T2CK — 6 I ST Timer2 External Clock Input
TCK 27 38 I ST JTAG Test Clock/Programming Clock Input
TDI 28 60 I ST JTAG Test Data/Programming Data Input
TDO 24 61 O — JTAG Test Data Output
TMS 23 17 I ST JTAG Test Mode Select Input
TRCLK — 91 O — Trace Clock
TRD0 — 97 O — Trace Data Bit 0

PIC32MX3XX/4XX
Pin Number Input
U1CTS 43 47 I ST UART1 Clear to Send Input

U1RTS 35 48 O — UART1 Request to Send Output
U1RX 34 52 I ST UART1 Receive
U1TX 33 51 O — UART1 Transmit Output
U2RX 31 49 I ST UART 2 Receive Input
VDD 10, 26, 38 2, 16, 37, P — Positive Supply for Peripheral Digital Logic and I/O pins
46, 62
VDDCAP 56 85 P — External Filter Capacitor Connection (regulator enabled)
VDDCORE 56 85 P — Positive Supply for Microcontroller Core Logic (regulator disabled)
VREF- 15 28 I ANA A/D Reference Voltage (Low) Input
VREF+ 16 29 I ANA A/D Reference Voltage (High) Input
VSS 9, 25, 41 15, 36, P — Ground Reference for Logic and I/O pins
45, 65, 75

PIC32MX3XX/4XX
TABLE 1-5: PIC32MX3XX/4XX PINOUT DESCRIPTIONS – USB
Pin Number Input
AN0 16 25 I ANA A/D Analog Inputs

AN1 15 24 I ANA
AN2 14 23 I ANA
AN3 13 22 I ANA
AN4 12 21 I ANA
AN5 11 20 I ANA
AN6 17 26 I ANA
AN7 18 27 I ANA
AN8 21 32 I ANA
AN9 22 33 I ANA
AN10 23 34 I ANA
AN11 24 35 I ANA
AN12 27 41 I ANA
AN13 28 42 I ANA
AN14 29 43 I ANA
AN15 30 44 I ANA
AVDD 19 30 P — Positive Supply for Analog Modules
AVSS 20 31 P — Ground Reference for Analog Modules
CLKI 39 63 I ANA Main Clock Input Connection
CLKO 40 64 O — System Clock Output

PIC32MX3XX/4XX
TABLE 1-5: PIC32MX3XX/4XX PINOUT DESCRIPTIONS – USB (CONTINUED)
Pin Number Input

CN1 47 73 I ST
CN2 16 25 I ST
CN3 15 24 I ST
CN4 14 23 I ST
CN5 13 22 I ST
CN6 12 21 I ST
CN7 11 20 I ST
CN8 4 10 I ST
CN9 5 11 I ST
CN10 6 12 I ST
CN11 8 14 I ST
CN12 30 44 I ST
CN13 52 81 I ST
CN14 53 82 I ST
CN15 54 83 I ST
CN16 55 84 I ST
CN17 31 49 I ST
CN19 — 80 I ST
CN20 — 47 I ST
CN21 — 48 I ST
CVREF- 15 28 I ANA Comparator Reference Voltage (Low) Input
CVREF+ 16 29 I ANA Comparator Reference Voltage (High) Input
CVREFOUT 23 34 O ANA Comparator Voltage Reference Output
D+ 37 57 I/O ANA USB D+
D- 36 56 I/O ANA USB D-
ENVREG 57 86 I ST Enable for On-Chip Voltage Regulator
IC1 42 68 I ST Input Capture Inputs
IC2 43 69 I ST
IC3 44 70 I ST
IC4 45 71 I ST
IC5 52 79 I ST

PIC32MX3XX/4XX
Pin Number Input
INT0 46 72 I ST External Interrupt Inputs

INT1 42 18 I ST
INT2 43 19 I ST
INT3 44 66 I ST
INT4 45 67 I ST
MCLR 7 13 I ST Master Clear (Device Reset) Input
Bring this line low to cause a Reset.
OC1 46 72 O — Output Compare/PWM Outputs
OC2 49 76 O —
OC3 50 77 O —
OC4 51 78 O —
OC5 52 81 O —
OCFA 17 26 I ST Output Compare Fault A Input
OCFB 30 44 I ST Output Compare Fault B Input
OSC1 39 63 I ANA Main Oscillator Input Connection
OSC2 40 64 O ANA Main Oscillator Output Connection
PMALL 30 44 O — Parallel Master Port Address Latch Enable low-byte (Multiplexed Mas-
ter modes)
PMALH 29 43 O — Parallel Master Port Address Latch Enable high-byte (Multiplexed
Master modes)

PIC32MX3XX/4XX
Pin Number Input
PMA2 8 14 O — Parallel Master Port Address (Demultiplexed Master modes)
PMA3 6 12 O —
PMA4 5 11 O —
PMA5 4 10 O —
PMA6 16 29 O —
PMA7 22 28 O —
PMA8 32 50 O —
PMA9 31 49 O —
PMA10 28 42 O —
PMA11 27 41 O —
PMA12 24 35 O —
PMA13 23 34 O —
PMA14 45 71 O — Address bit 14
PMA15 44 70 O — Address bit 15
PMD0 60 93 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
PMD1 61 94 I/O ST/TTL Address/Data (Multiplexed Master modes)

PMD5 1 3 I/O ST/TTL
PMD6 2 4 I/O ST/TTL
PMD7 3 5 I/O ST/TTL
PMENB 52 81 O — Parallel Master Port Enable Strobe (Master mode 1)
PMRD 53 82 O — Parallel Master Port Read Strobe (Master mode 2)
PMRD/PMWR 53 82 O — Parallel Master Port Read/Write Strobe (Master mode 1)
PMWR 52 81 O — Parallel Master Port Write Strobe (Master mode 2)

PIC32MX3XX/4XX
Pin Number Input
RA0 — 17 I/O ST PORTA Digital I/O

RA1 — 38 I/O ST Notes: On 100-pin devices, JTAG program/debug port is multi-
RA2 — 58 I/O ST plexed with port pins RA0, RA1, RA4 and RA5. At Reset,
these pins are controlled by the JTAG port. To use these
RA3 — 59 I/O ST pins for general purpose I/O, the user’s application code
RA4 — 60 I/O ST must clear JTAGEN (DDPCON<3>) bit = 0. To use these
RA5 — 61 I/O ST pins for JTAG program/debug, the user’s application
code must maintain JTAGEN bit = 1.
RA6 — 91 I/O ST
On specific 100-pin devices, the instruction TRACE port
RA7 — 92 I/O ST
RA9 — 28 I/O ST RG12, RG13 and RG14. At Power-on Reset, these pins
RA10 — 29 I/O ST are general purpose I/O pins. To maintain these pins as
general purpose I/O pins, the user’s application code
RA14 — 66 I/O ST
RA15 — 67 I/O ST these pins as instruction TRACE pins, TROEN must be
set = 1.
RB0 16 25 I/O ST PORTB Digital I/O
RB1 15 24 I/O ST Note: On 64-pin devices, JTAG program/debug port is multi-
RB2 14 23 I/O ST plexed with port pins RB10, RB11, RB12 and RB13. At
Reset, these pins are controlled by the JTAG port. To use
RB3 13 22 I/O ST
these pins for general purpose I/O, the user’s application
RB4 12 21 I/O ST code must clear JTAGEN (DDPCON<3>) bit = 0. To use
RB5 11 20 I/O ST these pins for JTAG program/debug, the user’s
application code must maintain JTAGEN bit = 1.
RB6 17 26 I/O ST
RB7 18 27 I/O ST
RB8 21 32 I/O ST
RB9 22 33 I/O ST
RB10 23 34 I/O ST
RB11 24 35 I/O ST
RB12 27 41 I/O ST
RB13 28 42 I/O ST
RB14 29 43 I/O ST
RB15 30 44 I/O ST
RC1 — 6 I/O ST PORTC Digital I/O
RC2 — 7 I/O ST
RC3 — 8 I/O ST
RC4 — 9 I/O ST
RC12 39 63 I/O ST
RC13 47 73 I/O ST
RC14 48 74 I/O ST
RC15 40 64 I/O ST

PIC32MX3XX/4XX
Pin Number Input
RD0 46 72 I/O ST PORTD Digital I/O

RD1 49 76 I/O ST
RD2 50 77 I/O ST
RD3 51 78 I/O ST
RD4 52 81 I/O ST
RD5 53 82 I/O ST
RD6 54 83 I/O ST
RD7 55 84 I/O ST
RD8 42 68 I/O ST
RD9 43 69 I/O ST
RD10 44 70 I/O ST
RD11 45 71 I/O ST
RD12 — 79 I/O ST
RD13 — 80 I/O ST
RD14 — 47 I/O ST
RD15 — 48 I/O ST
RE0 60 93 I/O ST PORTE Digital I/O
RE1 61 94 I/O ST
RE2 62 98 I/O ST
RE3 63 99 I/O ST
RE4 64 100 I/O ST
RE5 1 3 I/O ST
RE6 2 4 I/O ST
RE7 3 5 I/O ST
RE8 — 18 I/O ST
RE9 — 19 I/O ST
RF0 58 87 I/O ST PORTF Digital I/O
RF1 59 88 I/O ST
RF2 — 52 I/O ST
RF3 33 51 I/O ST
RF4 31 49 I/O ST
RF5 32 50 I/O ST
RF8 — 53 I/O ST
RF12 — 40 I/O ST
RF13 — 39 I/O ST

PIC32MX3XX/4XX
Pin Number Input
RG0 — 90 I/O ST PORTG Digital I/O

RG1 — 89 I/O ST
RG2 37 57 I/O ST Note: On specific 100-pin devices, the instruction TRACE port
RG3 36 56 I/O ST
RG12, RG13 and RG14. At Power-on Reset, these pins
RG6 4 10 I/O ST are general purpose I/O pins. To maintain these pins as
RG7 5 11 I/O ST general purpose I/O pins, the user’s application code
RG8 6 12 I/O ST
these pins as instruction TRACE pins, TROEN must be
RG9 8 14 I/O ST set = 1.
RG12 — 96 I/O ST
RG13 — 97 I/O ST
RG14 — 95 I/O ST
RG15 — 1 I/O ST
RTCC 42 68 O — Real-Time Clock Alarm Output
SCK1 — 70 O —
SCK2 4 10 I/O ST SPI2 Serial Clock Output
SDA1 43 67 I/O I2C I2C1 Data Input/Output
2
SDA2 31 59 I/O I C I2C2 Data Input/Output
SDI1 — 9 I ST
SDO1 — 72 O —
SOSCI 47 73 I ANA Secondary Oscillator/Timer1 External Clock Input
SOSCO 48 74 O ANA Secondary Oscillator/Timer1 External Clock Output
SS1 — 69 I/O ST Slave Select Input/Frame Select Output (SPI1)
T1CK 48 74 I ST Timer1 External Clock Input
TCK 27 38 I ST JTAG Test Clock/Programming Clock Input
TDI 28 60 I ST JTAG Test Data/Programming Data Input
TDO 24 61 O — JTAG Test Data Output
TMS 23 17 I ST JTAG Test Mode Select Input
TRCLK — 91 O — Trace Clock

PIC32MX3XX/4XX
Pin Number Input

U1RX 50 52 I ST UART1 Receive
U2RX 31 49 I ST UART 2 Receive Input
VDD 10, 26, 38 2, 16, 37, P — Positive Supply for Peripheral Digital Logic and I/O pins
46, 62
VDDCAP 56 85 P — External Filter Capacitor Connection (regulator enabled)
VDDCORE 56 85 P — Positive Supply for Microcontroller Core Logic (regulator disabled)
VREF- 15 28 I ANA A/D and Comparator Reference Voltage (Low) Input
VREF+ 16 29 I ANA A/D and Comparator Reference Voltage (High) Input
VSS 9, 25, 41 15, 36, P — Ground Reference for Logic and I/O pins
45, 65, 75
VBUS 34 54 I ANA USB Bus Power Monitor
VUSB 35 55 P — USB Internal Transceiver Supply
VBUSON 11 20 O — USB Host and OTG Bus Power Control Output
USBID 33 51 I ST USB OTG ID Detect

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
2.0 PIC32MX MCU • Autonomous Multiply/Divide Unit
- Maximum issue rate of one 32x16 multiply
Note: This data sheet summarizes the features of per clock
the PIC32MX3XX/4XX Family of devices. It - Maximum issue rate of one 32x32 multiply
is not intended to be a comprehensive refer- every other clock
ence source. Refer to the “PIC32MX Family
- Early-in iterative divide. Minimum 11 and
Reference Manual” (DS61132) for a detailed
maximum 34 clock latency (dividend (rs) sign
description of the PIC32MX mcu.
extension-dependent)
Resources for the MIPS32® M4K®
Processor Core are available at • Power Control
www.mips.com/products/cores/32-bit-cores/ - Minimum frequency: 0 MHz
mips32-m4k/#. - Low-Power mode (triggered by WAIT
instruction)
The MCU module is the heart of the PIC32MX3XX/4XX
Family processor. The MCU fetches instructions, - Extensive use of local gated clocks
decodes each instruction, fetches source operands, • EJTAG Debug and Instruction Trace
executes each instruction and writes the results of - Support for single stepping
instruction execution to the proper destinations. - Virtual instruction and data address/value
breakpoints
2.1 Features - PC tracing with trace compression
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-Accumulate and Multiply-Subtract
Instructions
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- WAIT Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
• MIPS16e™ Code Compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE & RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple Dual Bus Interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency

PIC32MX3XX/4XX
2.2 Architecture Overview
The PIC32MX3XX/4XX Family core contains several

logic blocks working together in parallel, providing an
efficient high performance computing engine. The
following blocks are included with the core:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Fixed Mapping Translation (FMT)
• Dual Internal Bus interfaces
• Power Management
• MIPS16e Support
• Enhanced JTAG (EJTAG) Controller
FIGURE 2-1: MCU BLOCK DIAGRAM
EJTAG Trace I/F
Trace
MDU Off-Chip
TAP
Debug I/F
Execution
Bus Matrix
Core FMT Bus Interface Dual Bus I/F
(RF/ALU/Shift)
System Power
Coprocessor
Mgmt

PIC32MX3XX/4XX
2.2.1 EXECUTION UNIT 2.2.2 MULTIPLY/DIVIDE UNIT (MDU)
The PIC32MX3XX/4XX Family core execution unit The PIC32MX3XX/4XX Family core includes a
implements a load/store architecture with single-cycle multiply/divide unit (MDU) that contains a separate
ALU operations (logical, shift, add, subtract) and an pipeline for multiply and divide operations. This pipeline
autonomous multiply/divide unit. The core contains operates in parallel with the integer unit (IU) pipeline
thirty-two 32-bit general purpose registers used for and does not stall when the IU pipeline stalls. This
integer operations and address calculation. One allows MDU operations to be partially masked by
additional register file shadow set (containing thirty-two system stalls and/or other integer unit instructions.
registers) is added to minimize context switching
overhead during interrupt/exception processing. The The high-performance MDU consists of a 32x16 booth
register file consists of two read ports and one write recoded multiplier, result/accumulation registers (HI
port and is fully bypassed to minimize operation latency and LO), a divide state machine, and the necessary
in the pipeline. multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
The execution unit includes: number (‘16’ of 32x16) represents the rt operand. The
• 32-bit adder used for calculating the data address PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
• Address unit for calculating the next instruction
must pass through the multiplier. The 16x16 and 32x16
address
operations pass through the multiplier once. A 32x32
• Logic for branch determination and branch target operation passes through the multiplier twice.
address calculation
• Load aligner The MDU supports execution of one 16x16 or 32x16
• Bypass multiplexers used to avoid stalls when multiply operation every clock cycle; 32x32 multiply
executing instructions streams where data operations can be issued every other clock cycle.
producing instructions are followed closely by Appropriate interlocks are implemented to stall the
consumers of their results issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
• Leading Zero/One detect unit for implementing the by logic built into the MDU.
CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bitwise Divide operations are implemented with a simple 1 bit
logical operations per clock iterative algorithm. An early-in detection
• Shifter and Store Aligner checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-
bit-wide rs, 15 iterations are skipped, and for a 24-bit-
wide rs, 7 iterations are skipped. Any attempt to issue
a subsequent MDU instruction while a divide is still
active causes an IU pipeline stall until the divide
operation is completed.
Table 2-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency
(number of cycles until a result is available) for the
PIC32MX core multiply and divide instructions. The
approximate latency and repeat rates are listed in
terms of pipeline clocks.

PIC32MX3XX/4XX
TABLE 2-1: PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate
MULT/MULTU, MADD/MADDU, 16 bits 1 1
MSUB/MSUBU 32 bits 2 2
MUL 16 bits 2 1
32 bits 3 2
DIV/DIVU 8 bits 12 11
16 bits 19 18
24 bits 26 25
32 bits 33 32
The MIPS architecture defines that the result of a

multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the general purpose register file.
In addition to the HI/LO targeted operations, the

MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination registers, the throughput of
multiply-intensive operations is increased.
Two other instructions, multiply-add (MADD) and

multiply-subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.

PIC32MX3XX/4XX
2.2.3 SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the

virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (kernel, user, and debug), and
whether interrupts are enabled or disabled.
Configuration information, such as presence of options
like MIPS16e, is also available by accessing the CP0
registers, listed in Table 2-2.
TABLE 2-2: COPROCESSOR 0 REGISTERS

Register Register
Function
Number Name
0-6 Reserved Reserved in the PIC32MX3XX/4XX Family core
7 HWREna Enables access via the RDHWR instruction to selected hardware registers
8 BadVAddr(1) Reports the address for the most recent address-related exception
9 Count(1) Processor cycle count
10 Reserved Reserved in the PIC32MX3XX/4XX Family core
11 Compare(1) Timer interrupt control
12 Status(1) Processor status and control
12 IntCtl(1) Interrupt system status and control
12 SRSCtl(1) Shadow register set status and control
12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set
13 Cause(1) Cause of last general exception
(1)
14 EPC Program counter at last exception
15 PRId Processor identification and revision
15 EBASE Exception vector base register
16 Config Configuration register
16 Config1 Configuration register 1
(2)
23 Debug Debug control and exception status
24 DEPC(2) Program counter at last debug exception
30 ErrorEPC(1) Program counter at last error
31 DESAVE(2) Debug handler scratchpad register
Note 1: Registers used in exception processing.
2: Registers used during debug.

PIC32MX3XX/4XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events, or program errors. Table 2-3
shows the exception types in order of priority.
TABLE 2-3: PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES

Exception Description
Reset Assertion MCLR or a Power-On Reset (POR)
DSS EJTAG Debug Single Step
DINT EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the
EjtagBrk bit in the ECR register
NMI Assertion of NMI signal
Interrupt Assertion of unmasked hardware or software interrupt signal
DIB EJTAG debug hardware instruction break matched
AdEL Fetch address alignment error
Fetch reference to protected address
IBE Instruction fetch bus error
DBp EJTAG Breakpoint (execution of SDBBP instruction)
Sys Execution of SYSCALL instruction
Bp Execution of BREAK instruction
RI Execution of a Reserved Instruction
CpU Execution of a coprocessor instruction for a coprocessor that is not enabled
CEU Execution of a CorExtend instruction when CorExtend is not enabled
Ov Execution of an arithmetic instruction that overflowed
Tr Execution of a trap (when trap condition is true)
DDBL / DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)
AdEL Load address alignment error
Load reference to protected address
AdES Store address alignment error
Store to protected address
DBE Load or store bus error
DDBL EJTAG data hardware breakpoint matched in load data compare

PIC32MX3XX/4XX
2.2.4 INTERRUPT HANDLING 2.2.5 GPR SHADOW REGISTERS
The PIC32MX3XX/4XX Family core includes support Release 2 of the MIPS32 Architecture optionally
for peripheral interrupts, two software interrupts, and a removes the need to save and restore GPRs on entry
timer interrupt. to high priority interrupts or exceptions, and to provide
The PIC32MX MCU uses the MIPS External Interrupt specified processor modes with the same capability.
Controller (EIC) mode, which redefines the way in This is done by introducing multiple copies of the
which interrupts are handled to provide full support for GPRs, called “shadow sets”, and allowing privileged
an external interrupt controller handling prioritization software to associate a shadow set with entry to kernel
and vectoring of interrupts. This presence of this mode mode via an interrupt vector or exception. The normal
denoted by the VEIC bit in the Config3 register. On the GPRs are logically considered shadow set zero.
PIC32MX core, the VEIC bit is always set to ‘1’ to
indicate the presence of an external interrupt controller. The PIC32MX3XX/4XX Family core implements two
sets of registers, the normal GPRs, and one shadow
Note: Although EIC mode is designated as set. This is indicated by the SRSCtlHSS field.
“External”, the interrupt controller is
on-chip.
The interrupt controller specifies which shadow set

should be used upon entry to a particular vector. The
shadow registers further improve interrupt latency by
avoiding the need to save context when invoking an
interrupt handler.

PIC32MX3XX/4XX
2.3 Modes of Operation
The PIC32MX3XX/4XX Family core supports three

modes of operation: user mode, kernel mode and
debug mode. User mode is most often used for
applications programs. Kernel mode is typically used
for handling exceptions and operating system kernel
functions, including CP0 management and I/O device
accesses. An additional Debug mode is used during
system bring-up and software development. Refer to
the EJTAG specification for more information on Debug
mode.
FIGURE 2-2: PIC32MX3XX/4XX FAMILY CORE VIRTUAL ADDRESS MAP
0xFFFFFFFF
Fixed Mapped
0xFF400000
0xFF3FFFFF
0xFF200000 Memory/EJTAG(1) kseg3
0xF1FFFFFF
Fixed Mapped
0xE0000000
0xDFFFFFFF
Kernel Virtual Address Space
kseg2
Fixed Mapped, 512 MB
0xC0000000
0xBFFFFFFF Kernel Virtual Address Space
Unmapped, 512 MB kseg1
0xA0000000 Uncached
0x9FFFFFFF
Kernel Virtual Address Space
Unmapped, 512 MB kseg0
0x80000000
0x7FFFFFFF
User Virtual Address Space kuseg

Fixed Mapped, 2048 MB
0x00000000
Note 1: This space is mapped to memory in user or kernel mode, and by the EJTAG module in Debug mode.

PIC32MX3XX/4XX
2.3.1 FIXED MAPPING TRANSLATION
The PIC32MX3XX/4XX Family core provides a simple

Fixed Mapping Translation (FMT) mechanism that is
smaller and simpler than a full Translation Lookaside
Buffer (TLB) found in other MIPS cores. Like a TLB, the
FMT performs virtual-to-physical address translation
and provides attributes for the different segments.
Those segments that are unmapped in a TLB
implementation (kseg0 and kseg1) are translated
identically by the FMT. Figure 2-3 shows how the FMT
is implemented in the PIC32MX core.
FIGURE 2-3: ADDRESS TRANSLATION DURING MEMORY ACCESS
Virtual
Address Physical
Address
Instruction
Address
Instn
Calculator
SRAM
SRAM
FMT Interface
Data
Data SRAM
Address
Calculator
Physical
Virtual Address
Address
In general, the FMT also determines the cacheability of

each segment. These attributes are controlled via bits
in the Config register. Table 2-4 shows the encoding for
the K23 (bits 30:28), KU (bits 27:25), and K0 (bits 2:0)
fields of the Config register. The PIC32MX core passes
these Config fields to the Prefetch Cache module to
determine cacheability of Program Memory Flash
accesses. Table 2-5 shows how the cacheability of the
virtual address segments is controlled by these fields.
TABLE 2-4: CACHE COHERENCY

ATTRIBUTES
Config Register
Fields Cache Coherency Attribute
K23, KU, and K0
2 Uncached
3 Cacheable

PIC32MX3XX/4XX
In the PIC32MX3XX/4XX Family core, no translation
exceptions are taken, although address errors are still
possible.
TABLE 2-5: CACHEABILITY OF SEGMENTS WITH FIXED MAPPING TRANSLATION

Segment Virtual Address Range Cacheability
useg/kuseg 0x0000_0000-0x7FFF_FFFF Controlled by the KU field (bits 27:25) of the Config register.
See Figure 2-4 for mapping.
This segment is always uncached when ERL = 1.
kseg0 0x8000_0000- 0x9FFF_FFFF Controlled by the K0 field (bits 2:0) of the Config register.
kseg1 0xA000_0000-0xBFFF_FFFF Always uncacheable.
kseg2 0xC000_0000-0xDFFF_FFFF Controlled by the K23 field (bits 30:28) of the Config register.
kseg3 0xE000_0000-0xFFFF_FFFF Controlled by the K23 field (bits 30:28) of the Config register.
The FMT performs a simple translation to map from

virtual addresses to physical addresses. This mapping
is shown in Figure 2-4.
FIGURE 2-4: FMT MEMORY MAP (ERL = 0) IN THE PIC32MX3XX/4XX FAMILY CORE
Virtual Address Physical Address

kseg3 kseg3
0xE000_0000 0xE000_0000
kseg2 kseg2
0xC000_0000 0xC000_0000
kseg1
0xA000_0000
kseg0
0x8000_0000
useg/kuseg
useg/kuseg 0x4000_0000
reserved
0x2000_0000
kseg0/kseg1
0x0000_0000 0x0000_0000

PIC32MX3XX/4XX
When ERL = 1, useg and kuseg become unmapped
(virtual address is identical to the physical address) and
uncached. This behavior is the same as if there was a
TLB. This mapping is shown in Figure 2-5.
FIGURE 2-5: PIC32MX3XX/4XX FAMILY CORE FMT MEMORY MAP (ERL = 1)

kseg3 kseg3
0xE000_0000 0xE000_0000
kseg2 kseg2
0xC000_0000 0xC000_0000
kseg1
0xA000_0000
reserved
kseg0
0x8000_0000 0x8000_0000
useg/kuseg useg/kuseg
kseg0/kseg1
0x0000_0000 0x0000_0000
2.3.2 DUAL INTERNAL BUS INTERFACES 2.3.3 MIPS16E EXECUTION
The SRAM interface includes dual instruction and data When the core is operating in MIPS16e mode,
interfaces. instruction fetches only require 16 bits of data to be
The dual interface enables independent connection to returned. For improved efficiency, however, the core
instruction and data devices. It yields the highest per- will fetch 32 bits of instruction data whenever the
formance, since the pipeline can generate simultane- address is word-aligned. Thus for sequential MIPS16e
ous I and D requests which are then serviced in code, fetches only occur for every other instruction,
parallel. resulting in better performance and reduced system
power.
The internal buses are connected to the Bus Matrix
unit, which is a switch fabric that provides this parallel
operation.

PIC32MX3XX/4XX
2.4 Power Management 2.5.1 DEBUG REGISTERS
The PIC32MX3XX/4XX Family core offers a number of Three debug registers (DEBUG, DEPC, and DESAVE)
power management features, including low-power have been added to the MIPS Coprocessor 0 (CP0)
design, active power management, and power-down register set. The DEBUG register shows the cause of
modes of operation. The core is a static design that the debug exception and is used for setting up single-
supports slowing or halting the clocks, which reduces step operations. The DEPC, or Debug Exception
system power consumption during idle periods. Program Counter, register holds the address on which
the debug exception was taken. This is used to resume
2.4.1 INSTRUCTION-CONTROLLED program execution after the debug operation finishes.
POWER MANAGEMENT Finally, the DESAVE, or Debug Exception Save,
register enables the saving of general purpose
The mechanism for invoking power-down mode is registers used during execution of the debug exception
through execution of the WAIT instruction. For more handler.
information on power management, see Section 23.0
“Power Saving”. To exit debug mode, a Debug Exception Return
(DERET) instruction is executed. When this instruction
2.4.2 LOCAL CLOCK GATING is executed, the system exits debug mode, allowing
normal execution of application and system code to
The majority of the power consumed by the resume.
PIC32MX3XX/4XX Family core is in the clock tree and
clocking registers. The PIC32MX family uses extensive 2.5.2 EJTAG HARDWARE BREAKPOINTS
use of local gated-clocks to reduce this dynamic power
consumption. There are several types of simple hardware
breakpoints defined in the EJTAG specification. These
2.5 EJTAG Debug Support stop the normal operation of the MCU and force the
system into debug mode. There are two types of simple
The PIC32MX3XX/4XX Family core provides for an hardware breakpoints implemented in the
Enhanced JTAG (EJTAG) interface for use in the PIC32MX3XX/4XX Family core: Instruction
software debug of application and kernel code. In breakpoints and Data breakpoints.
addition to standard user mode and kernel modes of
operation, the PIC32MX3XX/4XX Family core provides The PIC32MX3XX/4XX Family core has two data and
a Debug mode that is entered after a debug exception six instruction breakpoints
(derived from a hardware breakpoint, single-step
exception, etc.) is taken and continues until a debug Instruction breaks occur on instruction fetch
exception return (DERET) instruction is executed. operations, and the break is set on the virtual address.
During this time, the processor executes the debug A mask can be applied to the virtual address to set
exception handler routine. breakpoints on a range of instructions.
The EJTAG interface operates through the Test Access Data breakpoints occur on load/store transactions.
Port (TAP), a serial communication port used for Breakpoints are set on virtual address values, similar to
transferring test data in and out of the the Instruction breakpoint. Data breakpoints can be set
PIC32MX3XX/4XX Family core. In addition to the on a load, a store, or both. Data breakpoints can also
standard JTAG instructions, special instructions be set based on the value of the load/store operation.
defined in the EJTAG specification define what Finally, masks can be applied to both the virtual
registers are selected and how they are used. address and the load/store value.
2.5.3 INSTRUCTION TRACING
The PIC32MX3XX/4XX Family core includes Trace

support for real-time tracing of instruction addresses.
The trace information is collected in an off-chip
memory, for post-capture processing by trace
regeneration software.
Off-chip trace memory is accessed through a special

trace probe that consists of 4 data pins plus a clock.

PIC32MX3XX/4XX
2.6 MCU Initialization 2.6.2 COPROCESSOR 0 STATE
Software is required to initialize the following parts of Miscellaneous CP0 states need to be initialized prior to
the device after a Reset event: leaving the boot code. There are various exceptions
which are blocked by ERL = 1 or EXL = 1 and which are
• General Purpose Registers not cleared by Reset. These can be cleared to avoid
• Coprocessor 0 State taking spurious exceptions when leaving the boot code.
2.6.1 GENERAL PURPOSE REGISTERS

The MCU register file powers up in an unknown state
with the exception of r0 which is always 0. Initializing
the rest of the register file is not required for proper
operation of hardware. Depending on the software
environment however, several registers may need to
be initialized. Some of these are:
• SP – Stack Pointer
• GP – Global Pointer
• FP – Frame Pointer
TABLE 2-6: CP0 INITIALIZATION

CP0 Register Action
Cause WP (Watch Pending), SW0/1 (Software Interrupts) should be cleared.
Config Typically, the K0, KU and K23 fields should be set to the desired Cache Coherency Algorithm
(CCA) value prior to accessing the corresponding memory regions. But in the M4K core, all
CCA values are treated identically, so the hardware reset value of these fields need not be
modified.
Count(1) Should be set to a known value if Timer Interrupts are used.
Compare(1) Should be set to a known value if Timer Interrupts are used. The write to compare will also
clear any pending Timer Interrupts (thus, Count should be set before Compare to avoid any
unexpected interrupts).
Status Desired state of the device should be set.
Other CP0 state Other registers should be written before they are read. Some registers are not explicitly
writable, and are only updated as a by-product of instruction execution or a taken exception.
Uninitialized bits should be masked off after reading these registers.
Note 1: When the Count register is equal to the Compare register, a timer interrupt is signaled. There is a mask bit in
the interrupt controller to disable passing this interrupt to the MCU if desired.
2.7 I/O Pin Configuration

The MCU module has EJTAG pins that may be config-
ured as user-available I/O pins. If EJTAG is used for
debug, it is important to make sure that software does
not clear DDPCON<JTAGEN>.

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
3.0 INSTRUCTION SET Note: Refer to “MIPS32® Architecture for Pro-
grammers Volume II: The MIPS32®
The PIC32MX3XX/4XX family instruction set complies
Instruction Set” at www.mips.com for more
with the MIPS32 Release 2 instruction set architecture.
information.
PIC32MX does not support the following features:
• CoreExtend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Table 3-1 provides a summary of the instructions that
are implemented by the PIC32MX3XX/4XX family
core.
TABLE 3-1: PIC32MX3XX/4XX INSTRUCTION SET

Instruction Description Function
ADD Integer Add Rd = Rs + Rt
ADDI Integer Add Immediate Rt = Rs + Immed
ADDIU Unsigned Integer Add Immediate Rt = Rs +U Immed
ADDIUPC Unsigned Integer Add Immediate to PC Rt = PC +u Immed
(MIPS16e™ only)
ADDU Unsigned Integer Add Rd = Rs +U Rt
AND Logical AND Rd = Rs & Rt
ANDI Logical AND Immediate Rt = Rs & (016 || Immed)
B Unconditional Branch PC += (int)offset
(Assembler idiom for: BEQ r0, r0, offset)
BAL Branch and Link GPR[31> = PC + 8
(Assembler idiom for: BGEZAL r0, offset) PC += (int)offset
BEQ Branch On Equal if Rs == Rt
PC += (int)offset
BEQL Branch On Equal Likely if Rs == Rt
PC += (int)offset
else
Ignore Next Instruction
BGEZ Branch on Greater Than or Equal To Zero if !Rs[31>
PC += (int)offset
BGEZAL Branch on Greater Than or Equal To Zero And Link GPR[31> = PC + 8
if !Rs[31>
PC += (int)offset
BGEZALL Branch on Greater Than or Equal To Zero And Link GPR[31> = PC + 8
Likely if !Rs[31>
PC += (int)offset
else
BGEZL Branch on Greater Than or Equal To Zero Likely if !Rs[31>
PC += (int)offset
else
BGTZ Branch on Greater Than Zero if !Rs[31> && Rs != 0
PC += (int)offset
BGTZL Branch on Greater Than Zero Likely if !Rs[31> && Rs != 0
PC += (int)offset
else

PIC32MX3XX/4XX
TABLE 3-1: PIC32MX3XX/4XX INSTRUCTION SET (CONTINUED)
BLEZ Branch on Less Than or Equal to Zero if Rs[31> || Rs == 0
PC += (int)offset
BLEZL Branch on Less Than or Equal to Zero Likely if Rs[31> || Rs == 0
PC += (int)offset
else
BLTZ Branch on Less Than Zero if Rs[31>
PC += (int)offset
BLTZAL Branch on Less Than Zero And Link GPR[31> = PC + 8
if Rs[31>
PC += (int)offset
BLTZALL Branch on Less Than Zero And Link Likely GPR[31> = PC + 8
if Rs[31>
PC += (int)offset
else
BLTZL Branch on Less Than Zero Likely if Rs[31>
PC += (int)offset
else
BNE Branch on Not Equal if Rs != Rt
PC += (int)offset
BNEL Branch on Not Equal Likely if Rs != Rt
PC += (int)offset
else
BREAK Breakpoint Break Exception
CLO Count Leading Ones Rd = NumLeadingOnes(Rs)
CLZ Count Leading Zeroes Rd = NumLeadingZeroes(Rs)
COP0 Coprocessor 0 Operation See Software User’s Manual
DERET Return from Debug Exception PC = DEPC
Exit Debug Mode
DI Atomically Disable Interrupts Rt = Status; StatusIE = 0
DIV Divide LO = (int)Rs / (int)Rt
HI = (int)Rs % (int)Rt
DIVU Unsigned Divide LO = (uns)Rs / (uns)Rt
HI = (uns)Rs % (uns)Rt
EHB Execution Hazard Barrier Stop instruction execution
until execution hazards are
cleared
EI Atomically Enable Interrupts Rt = Status; StatusIE = 1
ERET Return from Exception if SR[2>
PC = ErrorEPC
else
PC = EPC
SR[1> = 0
SR[2> = 0
LL = 0
EXT Extract Bit Field Rt = ExtractField(Rs, pos,
size)

PIC32MX3XX/4XX
INS Insert Bit Field Rt = InsertField(Rs, Rt, pos,
size)
J Unconditional Jump PC = PC[31:28> || offset<<2
JAL Jump and Link GPR[31> = PC + 8
PC = PC[31:28> || offset<<2
JALR Jump and Link Register Rd = PC + 8
PC = Rs
JALR.HB Jump and Link Register with Hazard Barrier Like JALR, but also clears execution and
instruction hazards
JALRC Jump and Link Register Compact – do not execute Rd = PC + 2
instruction in jump delay slot (MIPS16e™ only) PC = Rs
JR Jump Register PC = Rs
JR.HB Jump Register with Hazard Barrier Like JR, but also clears execution and
instruction hazards
JRC Jump Register Compact – do not execute instruction in PC = Rs
jump delay slot (MIPS16e only)
LB Load Byte Rt = (byte)Mem[Rs+offset>
LBU Unsigned Load Byte Rt = (ubyte))Mem[Rs+offset>
LH Load Halfword Rt = (half)Mem[Rs+offset>
LHU Unsigned Load Halfword Rt = (uhalf)Mem[Rs+offset>
LL Load Linked Word Rt = Mem[Rs+offset>
LL = 1
LLAdr = Rs + offset
LUI Load Upper Immediate Rt = immediate << 16
LW Load Word Rt = Mem[Rs+offset>
LWPC Load Word, PC relative Rt = Mem[PC+offset>
LWL Load Word Left See Architecture Reference Manual
LWR Load Word Right See Architecture Reference Manual
MADD Multiply-Add HI | LO += (int)Rs * (int)Rt
MADDU Multiply-Add Unsigned HI | LO += (uns)Rs * (uns)Rt
MFC0 Move From Coprocessor 0 Rt = CPR[0, Rd, sel>
MFHI Move From HI Rd = HI
MFLO Move From LO Rd = LO
MOVN Move Conditional on Not Zero if Rt ¼ 0 then
Rd = Rs
MOVZ Move Conditional on Zero if Rt = 0 then
Rd = Rs
MSUB Multiply-Subtract HI | LO -= (int)Rs * (int)Rt
MSUBU Multiply-Subtract Unsigned HI | LO -= (uns)Rs * (uns)Rt
MTC0 Move To Coprocessor 0 CPR[0, n, Sel> = Rt
MTHI Move To HI HI = Rs
MTLO Move To LO LO = Rs
MUL Multiply with register write HI | LO =Unpredictable
Rd = ((int)Rs * (int)Rt)31..0
MULT Integer Multiply HI | LO = (int)Rs * (int)Rd
MULTU Unsigned Multiply HI | LO = (uns)Rs * (uns)Rd

PIC32MX3XX/4XX
NOP No Operation
(Assembler idiom for: SLL r0, r0, r0)
NOR Logical NOR Rd = ~(Rs | Rt)
OR Logical OR Rd = Rs | Rt
ORI Logical OR Immediate Rt = Rs | Immed
RDHWR Read Hardware Register Allows unprivileged access to registers
enabled by HWREna register
RDPGPR Read GPR from Previous Shadow Set Rt = SGPR[SRSCtlPSS, Rd>
RESTORE Restore registers and deallocate stack frame See Architecture Reference Manual
(MIPS16e™ only)
ROTR Rotate Word Right Rd = Rtsa-1..0 || Rt31..sa
ROTRV Rotate Word Right Variable Rd = RtRs-1..0 || Rt31..Rs
SAVE Save registers and allocate stack frame (MIPS16e only) See Architecture Reference Manual
SB Store Byte (byte)Mem[Rs+offset> = Rt
SC Store Conditional Word if LL = 1
mem[Rs+offset> = Rt
Rt = LL
SDBBP Software Debug Break Point Trap to SW Debug Handler
SEB Sign-Extend Byte Rd = (byte)Rs
SEH Sign-Extend Half Rd = (half)Rs
SH Store Half (half)Mem[Rs+offset> = Rt
SLL Shift Left Logical Rd = Rt << sa
SLLV Shift Left Logical Variable Rd = Rt << Rs[4:0>
SLT Set on Less Than if (int)Rs < (int)Rt
Rd = 1
else
Rd = 0
SLTI Set on Less Than Immediate if (int)Rs < (int)Immed
Rt = 1
else
Rt = 0
SLTIU Set on Less Than Immediate Unsigned if (uns)Rs < (uns)Immed
Rt = 1
else
Rt = 0
SLTU Set on Less Than Unsigned if (uns)Rs < (uns)Immed
Rd = 1
else
Rd = 0
SRA Shift Right Arithmetic Rd = (int)Rt >> sa
SRAV Shift Right Arithmetic Variable Rd = (int)Rt >> Rs[4:0>
SRL Shift Right Logical Rd = (uns)Rt >> sa
SRLV Shift Right Logical Variable Rd = (uns)Rt >> Rs[4:0>
SSNOP Superscalar Inhibit No Operation NOP
SUB Integer Subtract Rt = (int)Rs - (int)Rd
SUBU Unsigned Subtract Rt = (uns)Rs - (uns)Rd
SW Store Word Mem[Rs+offset> = Rt
SWL Store Word Left See Architecture Reference Manual

PIC32MX3XX/4XX
SWR Store Word Right See Architecture Reference Manual
SYNC Synchronize See Software User’s Manual
SYSCALL System Call SystemCallException
TEQ Trap if Equal if Rs == Rt
TrapException
TEQI Trap if Equal Immediate if Rs == (int)Immed
TrapException
TGE Trap if Greater Than or Equal if (int)Rs >= (int)Rt
TrapException
TGEI Trap if Greater Than or Equal Immediate if (int)Rs >= (int)Immed
TrapException
TGEIU Trap if Greater Than or Equal Immediate Unsigned if (uns)Rs >= (uns)Immed
TrapException
TGEU Trap if Greater Than or Equal Unsigned if (uns)Rs >= (uns)Rt
TrapException
TLT Trap if Less Than if (int)Rs < (int)Rt
TrapException
TLTI Trap if Less Than Immediate if (int)Rs < (int)Immed
TrapException
TLTIU Trap if Less Than Immediate Unsigned if (uns)Rs < (uns)Immed
TrapException
TLTU Trap if Less Than Unsigned if (uns)Rs < (uns)Rt
TrapException
TNE Trap if Not Equal if Rs != Rt
TrapException
TNEI Trap if Not Equal Immediate if Rs != (int)Immed
TrapException
WAIT Wait for Interrupts Stall until interrupt occurs
WRPGPR Write to GPR in Previous Shadow Set SGPR[SRSCtlPSS, Rd> = Rt
WSBH Word Swap Bytes Within Halfwords Rd = Rt23..16 || Rt31..24 || Rt7..0
|| Rt15..8
XOR Exclusive OR Rd = Rs ^ Rt
XORI Exclusive OR Immediate Rt = Rs ^ (uns)Immed
ZEB Zero-extend byte (MIPS16e™ only) Rt = (ubyte) Rs
ZEH Zero-extend half (MIPS16e only) Rt = (uhalf) Rs

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
4.0 OSCILLATORS
Note: This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
Reference Manual” (DS61132) for a
detailed description of this peripheral.
This section describes the PIC32MX3XX/4XX oscilla-
tor system and its operation. The PIC32MX oscillator
system has the following modules and features:
• A total of four external and internal oscillator
options as clock sources
• On-chip PLL with user-selectable input divider,
multiplier, and output divider to boost operating
frequency on select internal and external
oscillator sources
• On-chip user-selectable divisor postscaler on
select oscillator sources
• Software-controllable switching between various
clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
A simplified diagram of the oscillator system is shown
in Figure 4-1.

PIC32MX3XX/4XX
Figure 4-1: PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM
Primary Oscillator
(POSC)
UFIN USB Clock (48 MHz)
div x PLL x24 div 2
OSCI 4 MHz ≤ UFIN ≤ 5 MHz UFRCEN
PLLDIV<2:0> UPLLEN
XT, HS, EC
OSCO
Peripherals
PBCLK out 4 MHz ≤ FIN ≤ 5 MHz Postscaler
available on XTPLL, HSPLL, div x
FIN ECPLL, FRCPLL PBCLK
OSCO pin div x PLL div y
in certain
clock modes
PLL Input Divider PLL Output Divider PBDIV<2:0>
FPLLIDIV<2:0> PLLODIV<2:0>
FRC
Oscillator PLL Multiplier
8 MHz typical COSC<2:0> PLLMULT<2:0>
FRC CPU & Select Peripherals
TUN<5:0>
FRC /16
div 16
FRCDIV
Postscaler
FRCDIV<2:0>
LPRC LPRC
Oscillator 32 kHz typical
Secondary Oscillator (SOSC)

32.768 kHz SOSC
SOSCO
SOSCEN and FSOSCEN
SOSCI
Clock Control Logic
Fail-Safe FSCM INT
Clock
Monitor FSCM Event
NOSC<2:0>
COSC<2:0>
FSCMEN<1:0> OSWEN
WDT, PWRT
Timer1, RTCC

PIC32MX3XX/4XX
4.1 Control Registers The Oscillator module also has the following
associated bits for interrupt control:
The Oscillator module consists of the following Special
Function Registers (SFRs): • Interrupt Flag Status bits (IFS1<14>) for Clock
Fail FSCMIF in IFS1 Interrupt register
• OSCCON: Control Register for the Oscillator
module • Interrupt Enable Control bits (IEC1<14>) for Clock
Fail FSCMIE in IEC1 Interrupt register
OSCCONCLR, OSCCONSET, OSCCONINV:
• Interrupt Priority Control bits (FSCMIP<12:10>)
Atomic Bit Manipulation Write-only Registers for
for Clock Fail in IPC8 Interrupt register
OSCCON register
• Interrupt Subpriority Control bits (FSCMIP<9:8>)
• OSCTUN: FRC Tuning Register for the Oscillator for Clock Fail in IPC8 Interrupt register
module
The following tables provide brief summaries of
OSCTUNCLR, OSCTUNSET, OSCTUNINV: Atomic Oscillator-module-related registers. Corresponding
Bit Manipulation Write-only Registers for OSCTUN registers appear after the summaries, followed by a
register detailed description of each register.
TABLE 4-1: OSCILLATOR SFR SUMMARY
Bit Bit
Virtual Bit Bit Bit Bit Bit Bit
Name 28/20/12/ 27/19/11/
Address 31/23/15/7 30/22/14/6 29/21/13/5 26/18/10/2 25/17/9/1 24/16/8/0
4 3
BF80_F000 OSCCON 31:24 — — PLLODIV<2:0> FRCDIV<2:0>

23:16 — SOSCRDY — PBDIV<1:0> PLLMULT<2:0>
15:8 — COSC<2:0> — NOSC<2:0>
7:0 CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN
BF80_F004 OSCCONCLR 31:0 Write clears selected bits in OSCCON, read yields undefined value
BF80_F008 OSCCONSET 31:0 Write sets selected bits in OSCCON, read yields undefined value
BF80_F00C OSCCONINV 31:0 Write inverts selected bits in OSCCON, read yields undefined value
BF80_F010 OSCTUN 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 — — TUN<5:0>
BF80_F014 OSCTUNCLR 31:0 Write clears selected bits in OSCTUN, read yields undefined value
BF80_F018 OSCTUNSET 31:0 Write sets selected bits in OSCTUN, read yields undefined value
BF80_F01C OSCTUNINV 31:0 Write inverts selected bits in OSCTUN, read yields undefined value
TABLE 4-2: WATCHDOG TIMER SFR SUMMARY(1)

Bit Bit
Virtual Bit Bit Bit Bit Bit Bit
Name 28/20/12/ 27/19/11/
Address 31/23/15/7 30/22/14/6 29/21/13/5 26/18/10/2 25/17/9/1 24/16/8/0
4 3
BF80_0000 WDTCON 15:8 ON — — — — — — —
Note 1: This summary table contains partial register definitions that only pertain to the Oscillator peripheral. Refer to the
“PIC32MX Family Reference Manual” (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
TABLE 4-3: OSCILLATOR INTERRUPT REGISTER SUMMARY(1)
Virtual Bit Bit Bit Bit Bit Bit Bit Bit
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1070 IEC1 15:8 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE
BF88_1040 IFS1 15:8 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF
BF88_1110 IPC8 23:16 — — — FSCMIP<2:0> FSCMIS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Oscillator peripheral. Refer to the
TABLE 4-4: DEVCFG: DEVICE CONFIGURATION REGISTER SUMMARY(1, 2)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BFC0_2FF8 DEVCFG1 23:16 FWDTEN — — FWDTPS<4:0>
15:8 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMD<1:0>
7:0 IESO — FSOSCEN — — FNOSC<2:0>
BFC0_2FF4 DEVCFG2 23:16 — — — — — FPLLODIV<2:0>
15:8 FUPLLEN — — — — FUPLLIDIV<2:0>
7:0 — FPLLMULT<2:0> — FPLLIDIV<2:0>
Note 1: FUPLLEN and FPLLODIV<2:0> are only available on PIC32MX4XX family variants.
2: This summary table contains partial register definitions that only pertain to the Oscillator peripheral. Refer to the

PIC32MX3XX/4XX
REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER
r-x r-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1
— — PLLODIV<2:0> FRCDIV<2:0>
bit 31 bit 24
r-x R-0 r-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SOSCRDY — PBDIV<1:0> PLLMULT<2:0>
bit 23 bit 16
r-x R-0 R-0 R-0 r-x R/W-x R/W-x R/W-x

— COSC<2:0> — NOSC<2:0>
bit 15 bit 8
R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-x R/W-x

CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-30 Reserved: Write ‘0’; ignore read

bit 29-27 PLLODIV<2:0>: Output Divider for PLL
111 = PLL output divided by 256
Note: On Reset these bits are set to the value of the FPLLODIV configuration bits
(DEVCFG2<18:16>)
bit 26-24 FRCDIV<2:0>: Fast Internal RC Clock Divider bits
111 = FRC divided by 256
001 = FRC divided by 2 (default setting)
bit 23 Reserved: Write ‘0’; ignore read
bit 22 SOSCRDY: Secondary Oscillator Ready Indicator bit
1 = Indicates that the Secondary Oscillator is running and is stable
0 = Secondary oscillator is either turned off or is still warming up

PIC32MX3XX/4XX
bit 20-19 PBDIV<1:0>: Peripheral Bus Clock Divisor
11 = PBCLK is SYSCLK divided by 8 (default)
10 = PBCLK is SYSCLK divided by 4
Note: On Reset these bits are set to the value of the FPBDIV Configuration bits
(DEVCFG1<13:12>).
bit 18-16 PLLMULT<2:0>: PLL Multiplier bits
111 = Clock is multiplied by 24
Note: On Reset these bits are set to the value of the FPLLMULT Configuration bits
(DEVCFG2<6:4>).
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = Fast Internal RC Oscillator divided by OSCCON<FRCDIV> bits
110 = Fast Internal RC Oscillator divided by 16
101 = Low-Power Internal RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Fast RC Oscillator with PLL module divided by 2 (FRCPLL)
000 = Fast RC Oscillator (FRC)
Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
001 = Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Fast Internal RC Oscillator (FRC)
bit 7 CLKLOCK: Clock Selection Lock Enable bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked.
0 = Clock and PLL selections are not locked and may be modified
If FSCM is disabled (FCKSM1 = 0):
Note: Clock and PLL selections are never locked and may be modified.
bit 6 ULOCK: USB PLL Lock Status bit
1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress
or USB PLL is disabled
bit 5 LOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled

PIC32MX3XX/4XX
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM (Fail Safe Clock Monitor) has detected a clock failure
0 = No clock failure has been detected
bit 2 UFRCEN: USB FRC Clock Enable bit
1 = Enable FRC as the clock source for the USB clock source
0 = Use the primary oscillator or USB PLL as the USB clock source
bit 1 SOSCEN: 32.768 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
Note: On Reset these bits are set to the value of the FSOSCEN Configuration bit (DEVCFG1<5>).
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to selection specified by NOSC2:NOSC0 bits
0 = Oscillator switch is complete

PIC32MX3XX/4XX
REGISTER 4-2: OSCTUN: FRC TUNING REGISTER
r-x r-x r-x r-x r-x r-x r-x r-x
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN<5:0>
bit 7 bit 0
Legend:
bit 31:6 Reserved: Write ‘0’; ignore read

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
011111 = Maximum frequency.
011110 =
•
000001 =
000000 = Center frequency. Oscillator runs at calibrated frequency.
111111 =
•
100001 =
100000 = Minimum frequency.

PIC32MX3XX/4XX
REGISTER 4-3: WDTCON: WATCHDOG TIMER CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 r-x r-x r-x r-x R-1 R-1 R-0

ON — — — — — — —
bit 15 bit 8
r-x R-x R-x R-x R-x R-x r-0 R/W-0

— WDTPS<4:0> — WDTCLR
bit 7 bit 0
Legend:
bit 15 ON: Watchdog Timer Enable bit

1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if it was enabled in software
Notes: A read of this bit will result in a ‘1’ if the WDT is enabled by the device configuration or
by software.
The LPRC oscillator will automatically be enabled when this bit is set.
Note: Shaded bit names in this register control other PIC32MX3XX/4XX peripherals and are not related to the
oscillator.

PIC32MX3XX/4XX
REGISTER 4-4: IEC1: INTERRUPT ENABLE CONTROL REGISTER
r-x r-x r-x r-x r-x r-x R/W-0 R/W-0
— — — — — — USBIE FCEIE
bit 31 bit 24
r-0 r-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — DMA3IE DMA2IE DMA1IE DMA0IE
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE
bit 15 bit 8

SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE
bit 7 bit 0
Legend:
bit 14 FSCMIE: Fail-Safe Clock Monitor Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled
Note: Shaded bit names in this Interrupt register control other PIC32MX3XX/4XX peripherals and are not related to
the oscillator.

PIC32MX3XX/4XX
REGISTER 4-5: IFS1: INTERRUPT FLAG STATUS REGISTER
— — — — — — USBIF FCEIF
bit 31 bit 24
r-0 r-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — DMA3IF DMA2IF DMA1IF DMA0IF
bit 23 bit 16

RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF
bit 15 bit 8

SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF
bit 7 bit 0
Legend:
bit 14 FSCMIF: Fail-Safe Clock Monitor Interrupt Flag bit

1 = Interrupt request has occured
0 = No interrupt request has occurred
the oscillator.

PIC32MX3XX/4XX
REGISTER 4-6: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DMA0IP<2:0> DMA0IS<1:0>
bit 31 bit 24

— — — RTCCIP<2:0> RTCCIS<1:0>
bit 23 bit 16

— — — FSCMIP<2:0> FSCMIS<1:0>
bit 15 bit 8

— — — I2C2IP<2:0> I2C2IS<1:0>
bit 7 bit 0
Legend:
bit 12-10 FSCMIP<2:0>: Fail-Safe Clock Monitor Interrupt Priority bits

111 = Interrupt priority is 7
bit 9-8 FSCMIS<1:0>: Fail-Safe Clock Monitor Interrupt Subpriority bits
11 = Interrupt subpriority is 3
the oscillator.

PIC32MX3XX/4XX
REGISTER 4-7: DEVCFG1 BOOT CONFIGURATION REGISTER
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
R/P-1 R/P-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FWDTEN — — FWDTPS4 FWDTPS3 FWDTPS2 FWDTPS1 FWDTPS0
bit 23 bit 16
R/P-1 R/P-1 R/P-1 R/P-1 r-1 R/P-1 R/P-1 R/P-1

FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMD<1:0>
bit 15 bit 8
R/P-1 r-1 R/P-1 r-1 r-1 R/P-1 R/P-1 R/P-1

IESO — FSOSCEN — — FNOSC2 FNOSC1 FNOSC0
bit 7 bit 0
Legend:
bit 15-14 FCKSM<1:0>: Fail-safe Clock Monitor (FSCM) and Clock Switch Configuration bits
1x = FSCM and Clock Switching are disabled
01 = Clock Switching is enabled, FSCM is disabled
00 = Clock Switching and FSCM are enabled
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock divisor default value
bit 10 OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for
the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or = 00)
0 = CLKO output disabled
bit 9-8 POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary Oscillator Disabled
10 = HS mode
01 = XT Mode
00 = EC Mode
bit 7 IESO: Internal External Clock Switchover Select bit
1 = Internal External Clock Switchover mode enabled; Two-Speed Start-up mode
0 = Internal External Clock Switchover mode disabled; Single-Speed Start-up mode
bit 5 FSOSCEN: Secondary Oscillator Enable bit
1 = Enable secondary oscillator
0 = Disable secondary oscillator

PIC32MX3XX/4XX
bit 2-0 FNOSC<2:0>: CPU Clock Oscillator Select bits
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
110 = FRC Divided by 16 (FRCDIV16)
101 = Low-Power RC Oscillator (LPRC)
011 = Primary Oscillator with PLL (XTPLL, HSPLL, or ECPLL)
010 = Primary Oscillator without PLL (XT, HS, or EC)
001 = Fast RC Oscillator with PLL

PIC32MX3XX/4XX
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
r-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1

— — — — — FPLLODIV<2:0>
bit 23 bit 16
R/P-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1

FUPLLEN — — — — FUPLLIDIV<2:0>
bit 15 bit 8
r-x R/P-1 R/P-1 R/P-1 r-x R/P-1 R/P-1 R/P-1

— FPLLMULT<2:0> — FPLLIDIV<2:0>
bit 7 bit 0
Legend:
bit 18-16 FPLLODIV<2:0>: Default postscaler for PLL.

000 = PLL output divided by 1 (default setting)
bit 15 FUPLLEN: USB PLL Enable bit
00 = Enable USB PLL
00 = Disable and bypass USB PLL
bit 10-8 FUPLLIDIV<2:0>: PLL Input Divider bits
000 = 1x divider
001 = 2x divider
010 = 3x divider
011 = 4x divider
100 = 5x divider
101 = 6x divider
110 = 10x divider
111 = 12x divider
bit 6-4 FPLLMULT<2:0>: Default PLL Multiplier Value bits
111 = 24x multiplier

PIC32MX3XX/4XX
bit 2-0 FPLLIDIV<2:0>: Default PLL Input Divider Value bits
111 = Divide by 12
110 = Divide by 10
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1

PIC32MX3XX/4XX
4.2 Operation: Clock Generation and
Clock Sources
The PIC32MX3XX/4XX device has two internal clocks:
CPU clock and PB clock. They are derived from the
currently selected clock source. The clock source can
be chosen from the 4 available internal or external
clock sources. Some of these clock sources have
Phase Locked Loops (PLLs), programmable output
dividers, or input dividers to scale the input frequency
to suit the application. The clock source can be
changed on-the-fly by software. The oscillator control
register is locked by hardware, it must be unlocked by
a series of writes before software can perform a clock
switch.
There are three main clocks in the PIC32MX3XX/4XX
device:
• The System Clock (SYSCLK) used by CPU and
some peripherals
• The Peripheral Bus Clock (PBCLK) used by most
peripherals
• The USB Clock (USBCLK) used by USB
peripheral
The PIC32MX3XX/4XX clocks are derived from one of
the following sources:
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Internal Fast RC Oscillator (FRC)
• Internal Low-Power RC Oscillator (LPRC)
Each of the clock sources has unique configurable
options, such as a PLL, input divider and/or output
divider, that are detailed in their respective sections.
There are up to four internal clocks, depending on the
specific device. The clocks are derived from the
currently selected oscillator source.
Note: Clock sources for peripherals that use

external clocks, such as the RTCC and
Timer 1, are covered in their respective
sections.

PIC32MX3XX/4XX
4.2.1 SYSTEM CLOCK (SYSCLK)
GENERATION
The SYSCLK is the primary clock used by the CPU and
select peripherals such as DMA, Interrupt Controller,
and Prefetch Cache. The SYSCLK is derived from one
of the four clock sources: POSC, SOSC, FRC, or
LPRC. Some of the clock sources have specific clock
multipliers and/or divider options. No clock scaling is
applied other than the user specified values. The
SYSCLK source is selected by the device configuration
and can be changed by software during operation. The
ability to switch clock sources during operation allows
the application to reduce power consumption by reduc-
ing the clock speed. Refer to Table 4-5 for a list of SYS-
CLK sources.
TABLE 4-5: CLOCK SELECTION CONFIGURATION BIT VALUES

Oscillator FNOSC2:
Oscillator Mode POSCMD<1:0> Notes
Source FNOSC0
Fast RC Oscillator with Postscaler (FRCDIV) Internal xx 111 1, 2
Fast RC Oscillator divided by 16 (FRCDIV16) Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal xx 101 1
Secondary (Timer1/RTCC) Oscillator (SOSC) Secondary xx 100 1
Primary Oscillator (HS) with PLL Module Primary 10 011 3
(HSPLL)
Primary Oscillator (XT) with PLL Module Primary 01 011 3
(XTPLL)
Primary Oscillator (EC) with PLL Module Primary 00 011 3
(ECPLL)
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010
Fast RC Oscillator with PLL Module Internal 10 001 1,4
(FRCPLL)
Fast RC Oscillator (FRC) Internal xx 000 1
Note 1: OSCO pin function as PBCLK out or Digital I/O is determined by the OSCIOFNC Configuration bit. When
the pin is not required by the Oscillator mode it may be configured for one of these noted options.
2: Default Oscillator mode for an unprogrammed (erased) device.
3: When using the PLL modes the input divider must be chosen such that resulting frequency applied to the
PLL is in the range of 4 MHz to 5 MHz.
4: In this mode, the PLL input divider is forced to ‘2’ to provide a 4 MHz input to the PLL. This parameter
cannot be modified and satisfies the requirements described in Note 3.

PIC32MX3XX/4XX
4.2.1.1 Primary Oscillator (POSC) divider, multiplier, and output divider to provide a wide
range of output frequencies. The oscillator circuit will
The POSC has six operating modes, as summarized in
consume more current when the PLL is enabled.
Table 4-6. The first three modes can each be combined
with a PLL module to form the last three modes. The External Clock modes, EC and ECPLL, allow the
Figure 4-2, Figure 4-3, and Figure 4-4 show various system clock to be derived from an external clock
POSC configurations. The primary oscillator is con- source. These modes configure the OSCI pin as a
nected to the OSCI and OSCO pins of the device fam- high-impedance input that can be driven by a CMOS
ily. The primary oscillator can be configured for an driver. The external clock can be used to drive the sys-
external clock input, or an external crystal or resonator. tem clock directly (EC) or the ECPLL module with pres-
cale and postscaler can be used to change the input
The XT, XTPLL, HS, and HSPLL modes are External
clock frequency (ECPLL). The External Clock modes
Crystal or Resonator Controller Oscillator modes. The
also disable the internal feedback buffer, allowing the
XT and HS modes are functionally very similar. The pri-
OSCO pin to be used for other functions. In External
mary difference is the gain of the internal inverter of the
Clock mode, the OSCO pin can be used as an addi-
oscillator circuit (see Figure 4-2). The XT mode is a
tional device I/O pin (see Figure 4-4) or as a PBCLK
medium-power, medium-frequency mode and has
output pin (see Figure 4-3).
medium inverter gain. HS mode is higher power and
provides the highest oscillator frequencies and has the
highest inverter gain. OSCO provides crystal/resonator Note: When using PLL modes, the input divider
feedback in both XT and HS Oscillator modes and must be chosen such that the resulting
hence is not available for use as a input or output in frequency applied to the PLL is in the
these modes. The XTPLL and HSPLL modes have a range of 4 MHz to 5 MHz.
Phase Locked Loop (PLL) with user selectable input
TABLE 4-6: PRIMARY OSCILLATOR OPERATING MODES

Oscillator Mode Description
HS 10 MHz-40 MHz crystal
XT 3.5 MHz-10 MHz resonator
EC External clock input (0-80 MHz)
HSPLL 10 MHz-40 MHz crystal, PLL enabled
XTPLL 4 MHz-10 MHz resonator, PLL enabled
ECPLL External clock input (5-80 MHz), PLL enabled
Note: The clock applied to the CPU after applicable prescalers, postscalers, and PLL multipliers must not exceed
the maximum allowable processor frequency.
FIGURE 4-2: CRYSTAL OR CERAMIC RESONATOR OPERATION (XT, XTPLL, HS, OR HSPLL
OSCILLATOR MODE)
To Internal Logic
OSCI
C1(3)
XTAL Enable
RF(2)
OSCO
RS(1)
C2(3)
PIC32MX3XX/4XX
Note 1: A series resistor, Rs, may be required for AT strip cut crystals.
2: The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
3: Refer to the “PIC32MX Family Reference Manual” (DS61132) for help determining the best oscillator components.

PIC32MX3XX/4XX
FIGURE 4-3: EXTERNAL CLOCK INPUT 4.2.1.3 Oscillator Start-up Timer
OPERATION WITH In order to ensure that a crystal oscillator (or ceramic
CLOCK-OUT (EC, ECPLL resonator) has started and stabilized, an Oscillator
MODE) Start-up Timer (OST) is provided. The OST is a simple
10-bit counter that counts 1024 TOSC cycles before
releasing the oscillator clock to the rest of the system.
Clock from OSCI
This time-out period is designated as TOST. The ampli-
Ext. System tude of the oscillator signal must reach the VIL and VIH
PIC32MX3XX/4XX
thresholds for the oscillator pins before the OST can
PBCLK OSCO (Clock Out) begin to count cycles.
The TOST interval is required every time the oscillator
has to restart (i.e., on POR, BOR and wake-up from
Sleep mode). The Oscillator Start-up Timer is applied to
FIGURE 4-4: EXTERNAL CLOCK INPUT the XT and HS modes for the primary oscillator, as well
OPERATION WITH NO as the secondary oscillator, see Section 4.2.1.5 “Sec-
CLOCK-OUT (EC OR ondary Oscillator (SOSC)”.
ECPLL MODE)
Clock from OSCI

Ext. System
PIC32MX3XX/4XX
I/O I/O (OSCO)
4.2.1.2 Primary Oscillator (POSC)

Configuration
To configure the POSC, the following steps should be
performed:
1. Select POSC as the default oscillator in the
device Configuration register, DEVCFG1, by
setting FNOSC<2:0> = 010, without PLL; or
FNOSC<2:0> = 011, with PLL.
2. Select the desired mode (HS, XT, or EC), using
POSCMD<1:0> in the DEVCFG1 register.
3. If the PLL is to be used:
a) Select the appropriate Configuration bits for
the PLL input divider to scale the input
frequency to be between 4 MHz and 5 MHz
using FPLLIDIV<2:0> in the DEVCFG2
register.
b) Select the desired PLL multiplier ratio using
FPLLMULT<2:0> in the DEVCFG2 register.
c) At runtime, select the desired PLL output
divider using OSCCON<29:27> in the
PLLODIV register to provide the desired
clock frequency. The default value is set by
the DEVCFG1 register.

PIC32MX3XX/4XX
4.2.1.4 System Clock Phase Locked Loop
(PLL)
The system clock PLL provides a user configurable
input divider, multiplier, and output divider which can be
used with the XT, HS and EC Primary Oscillator modes
and with the Internal Fast RC Oscillator (FRC) mode to
create a variety of clock frequencies from a single clock
source.
The Input divider, multiplier, and output divider control
initial value bits are contained in the in the DEVCFG2
device Configuration register. The multiplier and output
divider bits are also contained in the OSCCON register.
As part of a device Reset, values from the device con-
figuration register, DEVCFG2, are copied to the
OSCCON register. This allows the user to preset the
input divider to provide the appropriate input frequency
to the PLL and set an initial PLL multiplier when pro-
gramming the device. At runtime the multiplier, divider
and output divider can be changed by software to scale
the clock frequency to suit the application. The PLL
input divider cannot be changed at run time. This is to
prevent applying an input frequency outside the speci-
fied limits to the PLL.
To configure the PLL the following steps are required:
1. Calculate the PLL input divider, PLL multiplier,
and PLL output divider values.
2. Set the PLL input divider and the initial PLL mul-
tiplier value in the DEVCFG2 register when pro-
gramming the part.
3. At runtime the PLL multiplier and PLL output
divider can be changed to suit the application.
Combinations of PLL input divider, multiplier and output
divider provide a combined multiplier of approximately
0.006 to 24 times the input frequency. For reliable oper-
ation the output of the PLL module must not exceed the
maximum clock frequency of the device. The PLL input
divider value should be chosen to limit the input fre-
quency to the PLL to the range of 4 MHz to 5 MHz.
Due to the time required for the PLL to provide a stable
output, a Status bit LOCK (OSCCON<5>) is provided.
When the clock input to the PLL is changed, this bit is
driven low (‘0’). After the PLL has achieved a lock or the
PLL start-up timer has expired, the bit is set. The bit will
be set upon the expiration of the timer even if the PLL
has not achieved a lock.

PIC32MX3XX/4XX
TABLE 4-7: NET MULTIPLIER OUTPUT FOR SELECTED PLL AND OUTPUT DIVIDER VALUES
Net Net
PLLODIV PLLMULT PLLODIV PLLMULT
Multiplier Postscaler Multiplication Multiplier Postscaler Multiplication
<2:0> <2:0> <2:0> <2:0>
factor factor
15 1 15 ‘000’ ‘000’ 15 16 .938 ‘100’ ‘000’

16 1 16 ‘000’ ‘001’ 16 16 1 ‘100’ ‘001’
17 1 17 ‘000’ ‘010’ 17 16 1.063 ‘100’ ‘010’
18 1 18 ‘000’ ‘011’ 18 16 1.125 ‘100’ ‘011’
19 1 19 ‘000’ ‘100’ 19 16 1.188 ‘100’ ‘100’
20 1 20 ‘000’ ‘101’ 20 16 1.250 ‘100’ ‘101’
21 1 21 ‘000’ ‘110’ 21 16 1.313 ‘100’ ‘110’
24 1 24 ‘000’ ‘111’ 24 16 1.5 ‘100’ ‘111’
15 2 7.5 ‘001’ ‘000’ 15 32 .4688 ‘101’ ‘000’

16 2 8 ‘001’ ‘001’ 16 32 .5 ‘101’ ‘001’
17 2 8.5 ‘001’ ‘010’ 17 32 .5313 ‘101’ ‘010’
18 2 9 ‘001’ ‘011’ 18 32 .5625 ‘101’ ‘011’
19 2 9.5 ‘001’ ‘100’ 19 32 .5938 ‘101’ ‘100’
20 2 10 ‘001’ ‘101’ 20 32 .6250 ‘101’ ‘101’
21 2 10.5 ‘001’ ‘110’ 21 32 .6563 ‘101’ ‘110’
24 2 12 ‘001’ ‘111’ 24 32 .7500 ‘101’ ‘111’
15 4 3.75 ‘010’ ‘000’ 15 64 .234 ‘110’ ‘000’

16 4 4 ‘010’ ‘001’ 16 64 .250 ‘110’ ‘001’
17 4 4.25 ‘010’ ‘010’ 17 64 .266 ‘110’ ‘010’
18 4 4.5 ‘010’ ‘011’ 18 64 .281 ‘110’ ‘011’
19 4 4.75 ‘010’ ‘100’ 19 64 .297 ‘110’ ‘100’
20 4 5 ‘010’ ‘101’ 20 64 .313 ‘110’ ‘101’
21 4 5.25 ‘010’ ‘110’ 21 64 .328 ‘110’ ‘110’
24 4 6 ‘010’ ‘111’ 24 64 .375 ‘110’ ‘111’
15 8 1.875 ‘011’ ‘000’ 15 256 .05859 ‘111’ ‘000’

16 8 2 ‘011’ ‘001’ 16 256 .06250 ‘111’ ‘001’
17 8 2.125 ‘011’ ‘010’ 17 256 .06641 ‘111’ ‘010’
18 8 2.250 ‘011’ ‘011’ 18 256 .07031 ‘111’ ‘011’
19 8 2.375 ‘011’ ‘100’ 19 256 .07422 ‘111’ ‘100’
20 8 2.5 ‘011’ ‘101’ 20 256 .07813 ‘111’ ‘101’
21 8 2.625 ‘011’ ‘110’ 21 256 .08203 ‘111’ ‘110’
24 8 3 ‘011’ ‘111’ 24 256 .09375 ‘111’ ‘111’

PIC32MX3XX/4XX
4.2.1.4.1 PLL Lock Status 4.2.1.5 Secondary Oscillator (SOSC)
The LOCK bit (OSCCON<5>) is a read-only Status bit The Secondary Oscillator (SOSC) is designed specifi-
that indicates the lock status of the PLL. It is automatically for low-power operation with a external
cally set after the typical time delay for the PLL to 32.768 kHz crystal. The oscillator is located on the
achieve lock, also designated as TLOCK. If the PLL SOSCO and SOSCI device pins and serves as a sec-
does not stabilize properly during start-up, LOCK may ondary crystal clock source for low-power operation. It
not reflect the actual status of PLL lock, nor does it can also drive Timer1 and/or the Real-Time Clock/Cal-
detect when the PLL loses lock during normal opera- endar module for Real-Time Clock applications.
tion.
4.2.1.5.1 Enabling the SOSC Oscillator
The LOCK bit is cleared at a Power-on Reset and on
clock switches when the PLL is selected as a destina- The SOSC is hardware enabled by the FSOSCEN
tion clock source. It remains clear when any clock Configuration bit (DEVCFG1<5>). Once SOSC is
source not using the PLL is selected. enabled, software can control it by modifying SOSCEN
bit (OSCCON<1>). Setting SOSCEN enables the oscil-
Refer to the Electrical Characteristics section in the
lator; the SOSCO and SOSCI pins are controlled by the
specific device data sheet for further information on the
oscillator and cannot be used for port I/O or other func-
PLL lock interval.
tions.
4.2.1.4.2 USB PLL Lock Status Note: An unlock sequence is required before a
write to OSCCON can occur. Refer to
The ULOCK bit (OSCCON<6>) is a read-only status bit
Section 4.2.6.2 “Oscillator Switching
that indicates the lock status of the USB PLL. It is auto-
Sequence” for more information.
matically set after the typical time delay for the PLL to
achieve lock, also designated as TLOCK. If the PLL The Secondary Oscillator requires a warm-up period
does not stabilize properly during start-up, LOCK may before it can be used as a clock source. When the oscil-
not reflect the actual status of PLL lock, nor does it lator is enabled, a warm-up counter increments to
detect when the PLL loses lock during normal opera- 1024. When the counter expires the SOSCRDY
tion. (OSCCON<22>) is set to ‘1’.
The ULOCK bit is cleared at a Power-on Reset. It
4.2.1.5.2 SOSC Continuous Operation
remains clear when any clock source not using the PLL
is selected. The SOSC is always enabled when SOSCEN
Refer to the Electrical Characteristics section in the (OSCCON<1>) is set. Leaving the oscillator running at
specific device data sheet for further information on the all times allows a fast switch to the 32 kHz system clock
PLL lock interval. for lower power operation. Returning to the faster main
oscillator will still require an oscillator start-up time if it
4.2.1.4.3 Primary Oscillator Start-up from Sleep is a crystal type source and/or uses the PLL.
Mode
In addition, the oscillator will need to remain running at
To ensure reliable wake-up from Sleep, care must be all times for Real-Time Clock applications and may be
taken to properly design the primary oscillator circuit. required for Timer1.
This is because the load capacitors have both partially
charged to some quiescent value and phase differential
at wake-up is minimal. Thus, more time is required to
achieve stable oscillation. Remember also that low-
voltage, high temperatures and the lower frequency
clock modes also impose limitations on loop gain,
which in turn, affects start-up.
Each of the following factors increases the start-up
time:
• Low-frequency design (with a Low Gain Clock
mode)
• Quiet environment (such as a battery operated
device)
• Operating in a shielded box (away from the noisy
RF area)
• Low voltage
• High temperature
• Wake-up from Sleep mode

PIC32MX3XX/4XX
EXAMPLE 4-1: ENABLING THE SOSC
SYSKEY = 0x12345678; // ensure OSCCON is locked
SYSKEY = 0xAA996655; // Write Key1 to SYSKEY
SYSKEY = 0x556699AA; // Write Key2 to SYSKEY
// OSCCON is now unlocked
// make the desired change

OSCCONSET = 2; // request clock switch
// Relock the SYSKEY

SYSKEY = 0x12345678; // Write any value other than Key1 or Key2
// OSCCON is relocked
4.2.1.6 Internal Fast RC Oscillator (FRC) 4.2.1.6.3 Oscillator Tune Register (OSCTUN)
The FRC oscillator is a fast (8 MHz nominal), user trim- The FRC Oscillator Tuning register OSCTUN allows
mable, internal RC oscillator with user selectable input the user to fine tune the FRC oscillator over a range of
divider, PLL multiplier, and output divider. approximately ±12% (typical). Each bit increment or
decrement changes the factory calibrated frequency of
4.2.1.6.1 FRC Postscaler Mode (FRCDIV)
the FRC oscillator by a fixed amount.
Users are not limited to the nominal 8 MHz FRC output
if they wish to use the fast internal oscillator as a clock 4.2.1.7 Internal Low-Power RC Oscillator
source. An additional FRC mode, FRCDIV, implements (LPRC)
a selectable output divider that allows the choice of a The LPRC oscillator is separate from the FRC. It oscil-
lower clock frequency from 7 different options, plus the lates at a nominal frequency of 31.25 kHz. The LPRC
direct 8 MHz output. The output divider is configured oscillator is the clock source for the Power-up Timer
using the FRCDIV<2:0> bits (OSCCON<26:24>). (PWRT), Watchdog Timer (WDT), Fail Safe Clock Mon-
Assuming a nominal 8 MHz output, available lower fre- itor (FSCM) and PLL reference circuits. It may also be
quency options range from 4 MHz (divide-by-2) to used to provide a low-frequency clock source option for
31 kHz (divide-by-256). The range of frequencies the device in those applications where power
allows users the ability to save power at any time in an consumption is critical, and timing accuracy is not
application by simply changing the FRCDIV bits. The required.
FRCDIV mode is selected whenever the COSC bits
(OSCCON<14:12>) are ‘111’.
4.2.1.6.2 FRC Oscillator with PLL Mode (FRCPLL)
The output of the FRC may also be combined with a

user selectable PLL multiplier and output divider to pro-
duce a SYSCLK across a wide range of frequencies.
The FRC PLL mode is selected whenever the COSC
bits (OSCCON<14:12>) are ‘001’.
Note: In this mode, the PLL input divider is

forced to ‘2’ to provide a 4 MHz input to the
PLL. This parameter cannot be modified.
The desired PLL multiplier and output divider values

can be chosen to provide the desired device frequency

PIC32MX3XX/4XX
4.2.1.7.1 Enabling the LPRC Oscillator 4.2.3 USB Clock (USBCLK)
Since it serves the PWRT clock source, the LPRC
Generation
oscillator is disabled at Power-on Reset whenever the The USBCLK can be derived from 8 MHz internal FRC
on-board voltage regulator is enabled. After the PWRT oscillator, 48 MHz POSC, or 96 MHz PLL from POSC.
expires, the LPRC oscillator will remain on if any one of For normal operation, the USB module requires exact
the following is true: 48 MHz clock. When using 96 MHz PLL, the output is
• The Fail-Safe Clock Monitor is enabled. internally divided to obtain 48 MHz clock. The FRC
• The WDT is enabled. clock source is used to detect USB activity and bring
USB module out of SUSPEND mode. Once USB mod-
• The LPRC oscillator is selected as the system
ule is out of SUSPEND mode, it starts using any of two
clock (COSC2:COSC0 = 100).
48 MHz clock sources. The internal FRC oscillator is
If none of the above is true, the LPRC will shut off after not used for normal USB module operation.
the PWRT expires.
4.2.3.0.1 USB Clock Phase Locked Loop (UPLL)
4.2.2 PERIPHERAL BUS CLOCK (PBCLK)
The USB clock PLL provides a user configurable input
GENERATION
divider which can be used with the XT, HS and EC pri-
The PBCLK is derived from the System Clock (SYS- mary oscillator modes and with the Internal Fast RC
CLK) divided by PBDIV<1:0> (OSCCON<20:19>). The Oscillator (FRC) mode to create a variety of clock fre-
PBCLK Divisor bits PBDIV<1:0> allow postscalers of quencies from a clock source. The actual source must
1:1, 1:2, 1:4, and 1:8. Refer to the individual peripheral be able to provide stable clock as required by the USB
module section(s) for information regarding which bus specifications.
a specific peripheral uses.
The UPLL enable and Input divider bits are contained
in the in the DEVCFG2 device configuration register.
Notes: When the PBDIV divisor is set to a ratio of The input to the UPLL must be limited to 4 MHz only.
‘1:1’ the SYSCLK and PBCLK are equiva- Appropriate input divider must be selected to ensure
lent in frequency. The PBCLK frequency is that the UPLL input is 4 MHz.
never greater than the processor clock fre-
quency. To configure the UPLL the following steps are required:
The effect of changing the PBCLK fre- 1. Enable USB PLL by setting FUPLLEN bit in
quency on individual peripherals should be DEVCFG2 register.
taken into account when selecting or 2. Based on the source clock, calculate the UPLL
changing the PBDIV value. input divider value such that the PLL input is 4
MHz
Performing back-to-back operations on
PBCLK peripheral registers when the PB 3. Set the UPLL input divider FUPLLIDIV bits in the
divisor is not set at 1:1 will cause the CPU DEVCFG2 register when programming the part.
to stall for a number of cycles. This stall 4.2.3.0.2 USB PLL Lock Status
occurs to prevent an operation from occur-
ring before the pervious one has com- The ULOCK bit (OSCCON<6>) is a read-only status bit
pleted. The length of the stall is that indicates the lock status of the USB PLL. It is auto-
determined by the ratio of the CPU and matically set after the typical time delay for the PLL to
PBCLK and synchronizing time between achieve lock, also designated as TULOCK. If the PLL
the two busses. does not stabilize properly during start-up, ULOCK may
Changing the PBCLK frequency has no not reflect the actual status of PLL lock, nor does it
effect on the SYSCLK peripherals detect when the PLL loses lock during normal opera-
operation. tion.
The ULOCK bit is cleared at a Power-on Reset. It
remains clear when any clock source not using the PLL
is selected.
Refer to the Electrical Characteristics section in the
specific device data sheet for further information on the
USB PLL lock interval.

PIC32MX3XX/4XX
4.2.3.0.3 Using Internal FRC Oscillator with USB The FSCM module takes the following actions when
switching to the FRC oscillator:
The internal 8 MHz FRC oscillator is available as a
clock source to detect any USB activity during USB 1. The COSC bits (OSCCON<14:12>) are loaded
SUSPEND mode and bring the module out of the SUS- with ‘000’.
PEND mode. To enable FRC for USB usage, the 2. The CF OSCCON<3> bit is set to indicate the
UFRCEN bit (OSCCON<2>) must be set ‘1’ before put- clock failure
ting USB module to SUSPEND mode. 3. The OSWEN control bit (OSCCON<0>) is
cleared to cancel any pending clock switches.
4.2.4 TWO-SPEED START-UP
To enable FSCM the following steps should be
Two-Speed Start-up mode can be used to reduce the performed:
device start-up latency when using all External Crystal
POSC modes, including PLL. Two-Speed Start-up uses 1. Enable the FSCM in the device Configuration
the FRC clock as the SYSCLK source until the Primary register, DEVCFG1, by configuring the
Oscillator (POSC) has stabilized. After the user FCKSM<1:0> bits to ‘00’.
selected oscillator has stabilized, the clock source will 01 = Clock Switching is enabled, FSCM is
switch to POSC. This allows the CPU to begin running disabled
code, at a lower speed, while the oscillator is stabiliz- 00 = Clock Switching and FSCM are enabled
ing. When the POSC has met the start-up criteria an 2. Select the desired mode HS, XT, or EC using
automatic clock switch occurs to switch to POSC. This FNOSC<2:0> in DEVCFG1.
mode is enabled by the device Configuration bits 3. Select POSC as the default oscillator in the
FCKSM<1:0> (DEVCFG1<15:14>). Two-Speed Start- device Configuration register, DEVCFG1 by
up operates after a Power-on Reset (POR) or exit from configuring FNOSC<2:0> = 010 without PLL or
SLEEP. Software can determine the oscillator source 011 with PLL.
currently in use by reading the COSC<2:0> bits in the
If the PLL is to be used:
OSCCON register.
1. Select the appropriate Configuration bits for
Note: The Watchdog Timer (WDT), if enabled, the PLL input divider to scale the input fre-
will continue to count at the same rate quency to be between 4 MHz and 5 MHz
regardless of the SYSCLK frequency. using FPLLIDIV<2:0> (DEVCFG2<2:0>).
Care must be taken to service the WDT
Note: When using FRCPLL mode, the PLL input
during Two-Speed Start-up, taking into
divider is forced to ‘2’ to provide a 4 MHz
account the change in SYSCLK.
input to the PLL. This parameter cannot be
modified.
4.2.5 FAIL-SAFE CLOCK MONITOR 2. Select the desired PLL multiplier using FPLL-
OPERATION MULT<2:0> (DEVCFG2<6:4>).
The Fail-Safe Clock Monitor (FSCM) is designed to 3. Select the desired PLL output divider using
allow continued device operation if the current oscilla- FPLLODIV<2:0> (DEVCFG2<18:16>).
tor fails. It is intended for use with the Primary Oscillator
(POSC) and automatically switches to the FRC oscilla- If a FSCM interrupt is desired when a FSCM event
tor if a POSC failure is detected. The switch to the Fast occurs, the following steps should be performed during
Internal RC Oscillator (FRC) oscillator allows continued start-up code:
device operation and the ability to retry the POSC or to 1. Clear the FSCM interrupt bit FSCMIF
execute code appropriate for a clock failure. (IFS1<14>).
The FSCM mode is controlled by the FCKSM<1:0> bits 2. Set the Interrupt priority FSCMIP<2:0>
in the device Configuration register, DEVCFG1. Any of (IPC8<12:10>) and subpriority FSCMIS<1:0>
the POSC modes can be used with FSCM. (IPC8<9:8>).
When a clock failure is detected with FSCM enabled 3. Set the FSCM Interrupt Enable bit FSCMIE
and the FSCM Interrupt Enable bit FSCMIE (IEC1<14>)
(IEC1<14>) set, the clock source will be switched from
POSC to FRC. An Oscillator Fail interrupt will be gen- Note: The Watchdog Timer, if enabled, will con-
erated, with the CF bit (OSCCON<3>) set. This inter- tinue to count at the same rate regardless
rupt has a user-settable priority FSCMIP<2:0> of the SYSCLK frequency. Care must be
(IPC8<12:10>) and subpriority FSCMIS<1:0> taken to service the WDT after a Fail-Safe
(IPC8<9:8>). The clock source will remain FRC until a Clock Monitor event, taking into account
device Reset or a clock switch is performed. Failure to the change in SYSCLK.
enable the FSCM interrupt will not inhibit the actual
clock switch.

PIC32MX3XX/4XX
4.2.5.1 FSCM Delay Note: The device does not prevent changing the
On a POR, BOR or wake from Sleep mode event, a PLL postscaler or multiplier values on the
nominal delay (TFSCM) may be inserted before the clock source that is in use. The device will
FSCM begins to monitor the system clock source. not permit direct switching between PLL
Refer to Section 5.0 “Resets” for FSCM delay timing clock sources. The user should not
information. change the PLL multiplier values or post-
scaler values when running from the
The TFSCM interval is applied whenever the FSCM is
affected PLL source. To perform either of
enabled and the HS, HSPLL, XT, XTPLL, or SOSC
the above clock switching functions, the
Oscillator modes are selected as the system clock.
clock switch should be performed in two
Note: Please refer to the Electrical steps. The clock source should first be
Characteristics section for TFSCM switched to a non-PLL source, such as
specification values. FRC, and then switched to the desired
source. This requirement only applies to
4.2.5.2 FSCM and Slow Oscillator Start-up PLL-based clock sources.
A slow oscillator start-up will not generate a FSCM
event. The FSCM does not begin monitoring until the 4.2.6.1 Enabling Clock Switching
source to be monitored is running. If the oscillator does
not start-up the device will not run due to the lack of a To enable clock switching, the FCKSM1 Configuration
clock source. To detect the failure and prevent this the bit (DEVCFG1<15>) must be programmed to ‘0’. If the
user should use Two-Speed Start-Up to allow the FCKSM1 Configuration bit is unprogrammed (= 1), the
device to run using the FRC oscillator while the POSC clock switching function and Fail-Safe Clock Monitor
oscillator starts up. The COSC<2:0> bits can then be function are disabled. This is the default setting.
polled to test for the clock switch to POSC. Refer to The NOSC control bits (OSCCON<10:8>) do not con-
Section 4.2.4 “Two-Speed Start-up” for further infor- trol the clock selection when clock switching is dis-
mation. abled. However, the COSC bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSC
4.2.5.3 FSCM and Slow Clock Sources Configuration bits.
Use of the FSCM with slow clock sources (below 100 The OSWEN control bit (OSCCON<0>) has no effect
kHz) is not recommended. Slow clock sources may when clock switching is disabled. It is held at ‘0’ at all
cause the FSCM to incorrectly detect a clock failure times.
event.
4.2.6.2 Oscillator Switching Sequence
4.2.5.4 FSCM and WDT
At a minimum, performing a clock switch requires the
The FSCM and the WDT both use the LPRC oscillator following sequence:
as their time base. In the event of a clock failure, the
1. If desired, read the COSC<2:0> bits
WDT is unaffected and continues to run.
(OSCCON<14:12>) to determine the current
oscillator source.
4.2.6 CLOCK SWITCHING OPERATION
2. Perform the unlock sequence to allow a write to
With few limitations, applications are free to switch the OSCCON register. The unlock sequence
between any of the four clock sources (POSC, SOSC, has critical timing requirements and should be
FRC and LPRC) under software control and at any performed with interrupts and DMA disabled.
time. To limit the possible side effects that could result
3. Write the appropriate value to the NOSC<2:0>
from this flexibility, PIC32MX3XX/4XX devices have a
control bits (OSCCON<10:8>) for the new
safeguard lock built into the switch process.
oscillator source.
Note: Primary Oscillator mode has three differ- 4. Set the OSWEN bit (OSCCON<0>) to initiate
ent submodes (XT, HS and EC) which are the oscillator switch.
determined by the POSCMD Configura- 5. Optionally perform the lock sequence to lock the
tion bits in DEVCFG1. While an applica- OSCCON. The lock sequence must be per-
tion can switch to and from Primary formed separately from any other operation.
Oscillator mode in software, it cannot
switch between the different primary sub- Once the basic sequence is completed, the system
modes without reprogramming the device. clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC<2:0> Status bits with the new value of
the NOSC control bits. If they are the same, then
the clock switch is a redundant operation. In this

PIC32MX3XX/4XX
case, the OSWEN bit is cleared automatically 4.2.6.3 Clock Switching Considerations
and the clock switch is aborted.
When incorporating clock switching into an application,
2. The new oscillator is turned on by the hardware users should keep certain things in mind when
if it is not currently running. If a crystal oscillator designing their code.
must be turned on, the hardware will wait until
the Oscillator Start-up timer (OST) expires. If the • The SYSLOCK unlock sequence is timing critical.
new source is using the PLL, then the hardware The two Key values must be written back-to-back
waits until a PLL lock is detected (LOCK = 1). with no in-between peripheral register access. To
prevent unintended peripheral register accesses,
3. The hardware clears the OSWEN bit to indicate
it is recommended that all interrupts and DMA
a successful clock transition. In addition, the
transfers are disabled.
NOSC bit values are transferred to the COSC
Status bits. • The system will not relock automatically. The user
should perform the relock sequence as soon after
4. The old clock source is turned off at this time if
the clock switch as is possible.
the clock is not being used by any modules.
• The unlock sequence unlocks other registers
such as the those related to Real-Time Clock
Note: The processor will continue to execute
control.
code throughout the clock switching
sequence. Timing-sensitive code should • If the destination clock source is a crystal oscilla-
not be executed during this time. tor, the clock switch time will be dictated by the
oscillator start-up time.
The following is a recommended code sequence for a • If the new clock source does not start, or is not
clock switch: present, the OSWEN bit will remain set.
• A clock switch to a different frequency will affect
1. Disable interrupts and DMA prior to the system
the clocks to peripherals. Peripherals may require
unlock sequence.
reconfiguration to continue operation at the same
2. Execute the system unlock sequence by writing rate as they did before the clock switch occurred.
the Key values of 0xAA996655 and
• If the new clock source uses the PLL, a clock
0x556699AA to the SYSKEY register in two
switch will not occur until lock has been achieved.
back-to-back assembly or ‘C’ instructions.
• If the WDT is used, care must be taken to ensure
3. Write the new oscillator source value to the
it can be serviced in a timely manner at the new
NOSC control bits.
clock rate.
4. Set the OSWEN bit in the OSCCON register to
initiate the clock switch. Note: The application should not attempt to
5. Write a non-key value (such as 0x12345678) to switch to a clock with a frequency lower
the SYSKEY register to perform a lock. Con- than 100 kHz when the Fail-Safe Clock
tinue to execute code that is not clock-sensitive Monitor is enabled. Clock switching in
(optional). these instances may generate a false
6. Check to see if OSWEN is ‘0’. If it is, the switch oscillator fail event and result in a switch to
was successful. Loop until the bit is ‘0’. the Internal Fast RC oscillator.
7. Re-enable interrupts and DMA.
Note: The device does not prevent changing the
Notes: There are no timing requirements for the PLL postscaler or multiplier values on the
steps other than the initial back-to-back clock source that is in use. The device will
writing of the Key values to perform the not permit direct switching between PLL
unlock sequence. clock sources. The user should not
change the PLL multiplier values or post-
The unlock sequence unlocks all registers scaler values when running from the
that are secured by the lock function. It is affected PLL source. To perform either of
recommended that amount to time is the the above clock switching functions, the
system is unlock is kept to a minimum. The clock switch should be performed in two
core sequence for unlocking the OSCCON steps. The clock source should first be
register and initiating a clock switch is switched to a non-PLL source, such as
shown in Example 4-2. FRC, and then switched to the desired
source. This requirement only applies to
PLL-based clock sources.

PIC32MX3XX/4XX
EXAMPLE 4-2: PERFORMING A CLOCK SWITCH
// note: clock switching must be enabled in the device configuration

SYSKEY = 0x0; // write invalid key to force lock
// make the desired change
OSCCONCLR = 7 << 8; // clear the clock select bits
OSCCONSET = 7 << 8; // set the new clock source to FRC
OSCCONSET = 1; // request clock switch
// Relock the SYSKEY
SYSKEY = 0x0; // Write any value other than Key1 or Key2
4.2.6.4 Entering Sleep Mode During a Clock used as SYSCLK, such as after a clock switch, it can-
Switch not be disabled by writing to the SOSCEN bit. If the
SOSC is enabled by the SOSCEN bit, it will continue to
If the device enters Sleep mode during a clock switch
operate when the device is in SLEEP. To prevent inad-
operation, the clock switch operation is aborted. The
vertent clock changes the OSCCON register is locked.
processor keeps the old clock selection and the
It must be unlocked prior to software enabling or
OSWEN bit (OSCCON<0>) is cleared. The WAIT
disabling the SOSC.
instruction is then executed normally.
4.2.6.5 SOSC Control 4.3 Input/Output Pins

The SOSC can be used by modules, as well as the The pins used by the POSC and SOSC are shared by
CPU. Therefore, the SOSC is controlled by a combina- other peripherals modules. Table shows the function of
tion of software and hardware. Setting the SOSCEN bit these shared pins in the available oscillator modes.
(OSCCON<1>) to a ‘1’ enables the SOSC. The SOSC When the pins are not used by a oscillator they are
is disabled when it is not being used by the CPU mod- available for use as general I/O pins or by use by a
ule and the SOSCEN bit is ‘0’. If the SOSC is being peripheral sharing the pin.
TABLE 4-8: CONFIGURATION OF PINS ASSOCIATED WITH THE OSCILLATOR MODULE

Pin Name Clock Mode Configuration Bit FIeld(1) TRIS Pin Type
OSCI HS, HSPLL, XT, XTPLL COSC<2:0>, POSCMD<1:0> X OSC

OSCO HS, HSPLL, XT, XTPLL COSC<2:0>, POSCMD X OSC
OSCI EC, ECPLL COSC<2:0>, POSCMD X CLOCK IN
OSCO EC, ECPLL COSC<2:0>, POSCMD, X PBCLK OUT
OSCOFNC
OSCO EC, ECPLL COSC<2:0>, POSCMD, INPUT INPUT
OSCOFNC
OSCO EC, ECPLL COSC<2:0>, POSCMD, OUTPUT OUTPUT
OSCOFNC
N/A FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC COSC<2:0> X GPIO
SOSCI SOSC COSC<2:0> X OSC
SOSCO SOSC COSC<2:0> X OSC
Note 1: During device start-up, the device oscillator configuration data is copied from device configuration to
COSC.

PIC32MX3XX/4XX
4.3.1 OSCI AND OSCO PIN FUNCTIONS
IN NON-EXTERNAL OSCILLATOR
MODES
When the primary oscillator (POSC) on OSCI and
OSCO is not configured as a clock source the OSCI pin
is automatically reconfigured as a digital I/O. In this
configuration, as well as when the primary oscillator is
configured for EC mode (POSCMD1:POSCMD0 = 00),
the OSCO pin can also be configured as a digital I/O by
programming the OSCIOFCN Configuration bit.
When OSCIOFCN is unprogrammed (‘1’), a PBCLK is
available on OSCO for testing or synchronization pur-
poses. With OSCIOFCN programmed (‘0’), the OSCO
pin becomes a general purpose I/O pin. In both of these
configurations, the feedback device between OSCI and
OSCO is turned off to save current.
4.3.2 SOSCI AND SOCI PIN FUNCTIONS

IN NON-EXTERNAL OSCILLATOR
MODES
When the secondary oscillator (SOSC) on SOSCI and
SOSCO pin is not configured as a clock source the pins
are automatically reconfigured as a digital I/O.

PIC32MX3XX/4XX
5.0 RESETS
The Reset module combines all Reset sources and

controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Master Clear Reset Pin
• SWR: Software Reset
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• CMR: Configuration Mismatch Reset
A simplified block diagram of the Reset module is
shown in Figure 5-1.
FIGURE 5-1: SYSTEM RESET BLOCK DIAGRAM
MCLR
MCLR
Glitch Filter
SLEEP or IDLE WDTR

Voltage WDT
Time-out
Regulator
Enabled
Power-up POR
Timer SYSRST
VDD
VDD Rise
Detect
Brown-out BOR
Reset
Configuration
Mismatch
Reset CMR
SWR
Software Reset

PIC32MX3XX/4XX
5.1 Reset Registers
TABLE 5-1: RESET SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_F600 RCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — CMR VREGS
7:0 EXTR SWR — WDTO SLEEP IDLE BOR POR
BF80_F604 RCONCLR 31:0 Write clears selected bits in RCON, read yields undefined value
BF80_F608 RCONSET 31:0 Write sets selected bits in RCON, read yields undefined value
BF80_F60C RCONINV 31:0 Write inverts selected bits in RCON, read yields undefined value
BF80_F610 RSWRST 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 — — — — — — — SWRST
BF80_F614 RSWRSTCLR 31:0 Write clears selected bits in RSWRST, read yields undefined value
BF80_F618 RSWRSTSET 31:0 Write sets selected bits in RSWRST, read yields undefined value
BF80_F61C RSWRSTINV 31:0 Write inverts selected bits in RSWRST, read yields undefined value

PIC32MX3XX/4XX
REGISTER 5-1: RCON: RESET CONTROL REGISTER(3)
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
r-x r-x r-x r-x r-x r-0 R/W-0 R/W-0

— — — — — — CMR VREGS
bit 15 bit 8
R/W-0 R/W-0 r-x R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR — WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:

bit 9 CMR: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
Note: This bit is set in hardware, it can only be cleared (= 0) in software.
bit 8 VREGS: Voltage Regulator Standby Enable bit
1 = Regulator will be active during Sleep
0 = Regulator will go to Standby mode during Sleep
bit 7 EXTR: External Reset (MCLR) Pin Flag bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag bit
1 = A Software Reset was executed
0 = A Software Reset was not executed
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
Note 1: User must clear this bit to view next detection.
2: BOR is also set after a Power-on Reset.
3: The RCON flag bits only serve as status bits. Setting a particular Reset status bit in software will not cause
a device Reset to occur.

PIC32MX3XX/4XX
REGISTER 5-1: RCON: RESET CONTROL REGISTER(3) (CONTINUED)
bit 2 IDLE: Wake-up From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit(1,2)
1 = A Brown-out Reset has occurred.
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit(1)
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1: User must clear this bit to view next detection.
2: BOR is also set after a Power-on Reset.
3: The RCON flag bits only serve as status bits. Setting a particular Reset status bit in software will not cause
a device Reset to occur.

PIC32MX3XX/4XX
REGISTER 5-2: RSWRST: SOFTWARE RESET REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
r-x r-x r-x r-x r-x r-x r-x W-0

— — — — — — — SWRST
bit 7 bit 0
Legend:

bit 0 SWRST: Software Reset Trigger bit
1 = Enable software Reset event
0 = Has no effect
Note: The system unlock sequence must be performed before the SWRST bit can be written. A
read must follow the write of this bit to generate a Reset.

PIC32MX3XX/4XX
5.2 Reset Modes 5.2.3 SOFTWARE RESET (SWR)
The PIC32MX3XX/4XX internal device Reset signal is The PIC32MX3XX/4XX CPU core doesn’t provide a
SYSRST and can be generated from multiple Reset specific RESET “instruction”; however, a hardware
sources, such as POR (Power-on Reset), BOR Reset can be performed in software (Software Reset)
(Brown-out Reset), MCLR (Master Clear Reset), by executing a Software Reset command sequence:
WDTO (Watchdog Time-out Reset), SWR (Software • Write the system unlock sequence
Reset) and CMR (Configuration Mismatch Reset). A • Set bit, SWRST (RSWRST<0>) = 1
Reset source sets a corresponding status bit in the
• Read RSWRST register – Reset occurs
RCON register to indicate the type of Reset (see
Register 5-1). A system Reset is active at first the POR • Follow with “while(1);” or 4 “NOP” instructions
and asserted until device configuration settings are Writing a ‘1’ to the RSWRST register sets bit SWRST,
loaded and the clock oscillator sources become stable. arming the Software Reset. The subsequent read of
The system Reset is then deasserted allowing the CPU the RSWRST register triggers the Software Reset,
to start fetching code after 8 system clock cycles (SYS- which should occur on the next clock cycle following
CLK). the read operation. To ensure no other user code is
executed before the Reset event occurs, it is recom-
5.2.1 POWER-ON RESET (POR) mended that 4 ‘NOP’ instructions or a “while(1);” state-
A power-on event generates an internal Power-On ment be placed after the READ instruction.
Reset pulse when a VDD rise is detected above VPOR. The SWR Status bit (RCON<6>) is set to indicate the
The device supply voltage characteristics must meet Software Reset.
the specified starting voltage and rise rate require-
ments to generate the POR pulse. In particular, VDD
must fall below VPOR before a new POR is initiated. For
more information on the VPOR and VDD rise rate speci-
fications, refer to Section 30.0 “Electrical Character-
istics” of this device family data sheet.
5.2.2 MCLR RESET (EXTR)

Whenever the MCLR pin is driven low, the device asyn-
chronously asserts SYSRST provided the input pulse on
MCLR is longer than a certain minimum width, as spec-
ified in Section 30.0 “Electrical Characteristics” of
this device family data sheet.
MCLR provides a filter to minimize the effects of noise
and to avoid unwanted Reset conditions. The EXTR bit
(RCON<7>) is set to indicate the MCLR Reset.
EXAMPLE 5-1: SOFTWARE RESET COMMAND SEQUENCE

/* The following code illustrates a software Reset */
// assume interrupts are disabled
// assume the DMA controller is suspended
// assume the device is locked
/* perform a system unlock sequence */
// starting critical sequence
SYSKEY = 0x12345678; //write invalid key to force lock
SYSKEY = 0xAA996655 //write key1 to SYSKEY
SYSKEY = 0x556699AA //write key2 to SYSKEY
/* set SWRST bit to arm reset */
RSWRSTSET = 1;
/* read RSWRST register to trigger reset */

unsigned int dummy;
dummy = RSWRST;
/* prevent any unwanted code execution until reset occurs*/

PIC32MX3XX/4XX
5.2.4 WATCHDOG TIMER TIME-OUT 5.3 Reset States
RESET (WDTR)
5.3.1 SPECIAL FUNCTION REGISTER
A Watchdog Timer time-out causes the device Reset,
SYSRST, to be asserted asynchronously. Note that a RESET STATES
WDT time-out during SLEEP or IDLE mode will wake-up Most of the Special Function Registers (SFRs) associ-
the processor and branch to the PIC32MX3XX/4XX ated with the PIC32MX3XX/4XX CPU and peripherals
Reset vector, but not reset the processor. The only bits are reset to a particular value at a device Reset. Refer
affected are WDTO and the SLEEP or IDLE bits in the to the corresponding data sheet section for a periph-
RCON register. For more information, refer to Section eral’s SFR details. The Reset value for each SFR will
26.0 “Watchdog Timer”. depend on the type of Reset.
Note: In this document, a distinction is made 5.3.2 CONFIGURATION WORD
between a power mode as it is used in a
REGISTER RESET STATES
specific module, and a power mode as it is
used by the device, e.g., Sleep mode of the All Reset conditions force the Flash Configuration
comparator and SLEEP mode of the CPU. Word registers to be re-loaded. However, a POR forces
To indicate which type of power mode is Flash Configuration Word registers to be reset prior to
intended, uppercase and lowercase letters being reloaded. For all other Reset conditions, the
(Sleep, Idle, Debug) signify a module Flash Configuration Word registers are not reset prior
power mode, and all uppercase letters to being re-loaded. This difference accommodates
(SLEEP, IDLE, DEBUG) signify a device MCLR assertions during Debug mode without affecting
power mode. the state of the debug operations.
5.2.5 BROWN-OUT RESET (BOR)

PIC32MX3XX/4XX devices have a simple brown-out
capability. If the voltage supplied to the regulator is inad-
equate to maintain a regulated level, the regulator Reset
circuitry will generate a Brown-out Reset. This event is
captured by the BOR flag bit (RCON<1>). Refer to
Section 30.2 “AC Characteristics and Timing Param-
eters” for further details.
5.2.6 CONFIGURATION MISMATCH

RESET
To maintain the integrity of the stored configuration val-
ues, all device Configuration bits are implemented as a
complementary set of register bits. For each bit, as the
actual value of the register is written as ‘1’, a comple-
mentary value, ‘0’, is stored into its corresponding
background register and vice versa. The bit pairs are
compared every time, including Sleep mode. During
this comparison, if the Configuration bit values are not
found opposite to each other, a Configuration Mismatch
event is generated which causes a device Reset.
If a device Reset occurs as a result of a Configuration
Mismatch, the CM bit (RCON<9>) is set.

PIC32MX3XX/4XX
5.3.3 RCON REGISTER STATES
Status bits from the RCON register are set or cleared
differently in different Reset situations, as indicated in
Table 5-2. The RCON bits only serve as status bits. The
user may set or clear any of the bits at any time during
code execution. Setting a particular Reset bit in
software will not cause a device Reset to occur. The
RCON register also has other bits associated with the
Watchdog Timer and device power-saving states.
TABLE 5-2: STATUS BITS, INITIALIZATION CONDITION FOR RCON REGISTER
SLEEP
WDTO
EXTR
SWR
IDLE
BOR
POR
CM
Condition Program Counter
Power-on Reset 0xBFC0_0000 0 0 0 0 0 0 1 1

Brown-out Reset 0 0 0 0 0 0 1 0
MCLR During Run Mode 1 u u u u u u u
MCLR During Idle Mode 1 u u u 1(2) u u u
u (2) u u u u
MCLR During Sleep Mode 1 u 1
Software Reset Command u 1 u u u u u u
Configuration Word u u u u u 1 u u
Mismatch Reset
WDT Time-out Reset u u 1 u u u u u
During Run Mode
WDT Time-out Reset u u 1 u 1(2) u u u
During Idle Mode
WDT Time-out Reset u u 1 1(2) u u u u
During Sleep Mode
Interrupt Exit from Idle Mode Vector(1) u u 0 u 1(2) u u u
Interrupt Exit from Sleep Mode u u 0 1(2) u u u u
Legend: u = unchanged
Note 1: Depends on Interrupt source.
2: SLEEP and IDLE bits states defined by previously executed WAIT instruction.
5.4 Using the RCON Status Bits

The user can read the RCON register after any device
Reset to determine the cause of the Reset. The status
bits in the RCON register should be cleared after they
are read so that the next RCON register value after a
device Reset will be meaningful.

PIC32MX3XX/4XX
TABLE 5-3: RESET FLAG BIT OPERATION
Flag Bit Set by: Cleared by:
POR (RCON<0>) POR User Software
BOR (RCON<1>) POR, BOR User Software
EXTR (RCON<7>) MCLR Reset User Software, POR, BOR
SWR (RCON<6>) Software Reset Command User Software, POR, BOR
CMR (RCON<9> Configuration Mismatch User Software, POR, BOR
WDTO (RCON<4>) WDT Time-Out User Software, POR, BOR
SLEEP (RCON<3>) WAIT Instruction User Software, POR, BOR
IDLE (RCON<2>) WAIT Instruction User Software, POR, BOR
Note: All Reset flag bits may be set or cleared by the user software.
5.4.1 DEVICE RESET TO CODE

EXECUTION START TIME
The delay between the end of a Reset event and when
the device actually begins to execute code is determined
by two main factors: the type of Reset and the system
clock source coming out of the Reset. The code execu-
tion start time for various types of device Resets are
characterized in Section 30.2 “AC Characteristics and
Timing Parameters”.
TABLE 5-4: CODE EXECUTION START TIME FOR VARIOUS DEVICE RESETS
System Clock
Reset Type Clock Source Power-Up Delay(1)(2)(3) FSCM Delay(6)
Delay(4)(5)
POR EC, FRC, FRCDIV, LPRC (TPU OR TPWRT) + TSYSDLY — —
ECPLL, FRCPLL (TPU OR TPWRT) + TSYSDLY TLOCK TFSCM
XT, HS, SOSC (TPU OR TPWRT) + TSYSDLY TOST TFSCM
XTPLL, HSPLL (TPU OR TPWRT) + TSYSDLY TOST + TLOCK TFSCM
BOR EC, FRC, FRCDIV, LPRC TSYSDLY — —
ECPLL, FRCPLL TSYSDLY TLOCK TFSCM
XT, HS, SOSC TSYSDLY TOST TFSCM
XTPLL TSYSDLY TOST + TLOCK TFSCM
MCLR, CMR, Any Clock TSYSDLY — —
SWR, WDTO
Note 1: TPU = Power-up Period with on-chip regulator enabled.
2: TPWRT = Power-up Period (POWER-UP TIMER) with on-chip regulator disabled.
3: TSYSDLY = Time required to reload Device Configuration Fuses plus 8 SYSCLK cycles.
4: TOST = Oscillator Start-up Timer.
5: TLOCK = PLL lock time.
6: TFSCM = Fail-Safe Clock Monitor delay.
Note: For parameter specifications, see Section 30.2 “AC Characteristics and Timing Parameters.”

PIC32MX3XX/4XX
5.5 Interrupts
There are no interrupts for this module.
5.6 I/O Pin Control

There are not I/O pin controls associated with this
module.

PIC32MX3XX/4XX
6.0 MEMORY ORGANIZATION 6.1 PIC32MX3XX/4XX Memory Layout
Note: This data sheet summarizes the features of PIC32MX3XX/4XX microcontrollers implement two
the PIC32MX3XX/4XX family of devices. It address spaces: Virtual and Physical. All hardware
is not intended to be a comprehensive refer- resources such as program memory, data memory and
ence source. Refer to the “PIC32MX Family peripherals are located at their respective physical
Reference Manual” (DS61132) for a addresses. Virtual addresses are exclusively used by
detailed description of this peripheral. the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
PIC32MX3XX/4XX microcontrollers provides 4 GB of peripherals such as DMA and Flash controller that
unified virtual memory address space. All memory access memory independently of CPU.
regions including program, data memory, SFRs, and The entire 4 GB virtual address space is divided into
Configuration registers reside in this address space at two primary regions – user and kernel space. The lower
their respective unique addresses. The program and 2 GB of space forms the User mode segment, called
data memories can be optionally partitioned into user useg/kuseg. The upper 2 GB of virtual address space
and kernel memories. In addition, the data memory can forms the kernel-only space. The kernel space is
be made executable, allowing PIC32MX3XX/4XX to divided into four segments of 512 MB each: kseg 0,
execute from data memory. kseg 1, kseg 2 and kseg 3. Only Kernel mode applica-
Key Features: tions can access kernel space memory. The peripheral
• 32-bit native data width registers are only visible through kernel space.
• Separate User and Kernel mode address space The Fixed Mapping Translation (FMT) unit translates
• Flexible program Flash memory partitioning the memory segments into corresponding physical
address regions. A virtual memory segment may also
• Flexible data RAM partitioning for data and
be cached, provided the cache module is available on
program space
the device. Please note that the kseg 1 memory seg-
• Separate boot Flash memory for protected code ment is not cacheable, while kseg 0 and useg/kuseg
• Robust bus exception handling to intercept are cacheable.
runaway code.
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable and non-cacheable address regions

PIC32MX3XX/4XX
FIGURE 6-1: VIRTUAL TO PHYSICAL FIXED MEMORY MAPPING
Virtual Memory Map Physical Memory Map

0xFFFFFFFF 0xFFFFFFFF
KSEG2/KSEG3
0xC0000000 Internal RAM

(User Partition) 0xBF000000
+ BMXDUDBA
Internal Boot Flash
0xBFC00000
Internal Flash
Internal Peripherals (User Partition) 0xBD000000
0xBF800000 + BMXPUPBA
KSEG1
Internal Program Flash

0xBD000000 0x4FFFFFFF
0xAFFFFFFF Reserved Reserved
0x40000000
Internal RAM
0xA0000000
0x9FC00000 Internal Boot Flash

KSEG0

0x9D000000
0x8FFFFFFF
Reserved
Internal RAM Internal Boot Flash

0x80000000
0x1FC00000
Internal RAM (User Internal Peripherals

0x7F000000 Partition) 0x1F800000
USEG/KUSEG

Program Flash (User 0x1D000000
0x7D000000+ Partition)
BMXPUPBA 0x0FFFFFFF
Reserved
BMXDUDBA
0x0FFFFFFF
Reserved Internal RAM
0x00000000 0x00000000

PIC32MX3XX/4XX
6.2 Bus Matrix Registers
TABLE 6-1: BUS MATRIX REGISTER SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_2000 BMXCON 31:24 — — — — — BMX- — —
CHEDMA
23:16 — — — BMXERRIXI BMXERRICD BMX- BMXERRDS BMXERRIS
ERRDMA
15:8 — — — — — — — —
7:0 — BMXWSDRM — — — BMXARB<2:0>
BF88_2004 BMXCON- 31:0 Write clears selected bits in BMXCON, read yields undefined value
CLR
BF88_2008 BMXCON- 31:0 Write sets selected bits in BMXCON, read yields undefined value
SET
BF88_200C BMXCON- 31:0 Write inverts selected bits in BMXCON, read yields undefined value
INV
BF88_2010 BMXDKPBA 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 BMXDKPBA<15:8>
7:0 BMXDKPBA<7:0>
BF88_2014 BMX- 31:0 Write clears selected bits in BMXDKPBA, read yields undefined value
DKPBACLR
BF88_2018 BMX- 31:0 Write sets selected bits in BMXDKPBA, read yields undefined value
DKPBASET
BF88_201C BMX 31:0 Write inverts selected bits in BMXDKPBA, read yields undefined value
DKPBAINV
BF88_2020 BMXDUDBA 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 BMXDUDBA<15:8>
7:0 BMXDUDBA<7:0>
BF88_2024 BMX- 31:0 Write clears selected bits in BMXDUDBA, read yields undefined value
DUDBACLR
BF88_2028 BMX- 31:0 Write sets selected bits in BMXDUDBA, read yields undefined value
DUDBASET
BF88_202C BMX- 31:0 Write inverts selected bits in BMXDUDBA, read yields undefined value
DUDBAINV
BF88_2030 BMX 31:24 — — — — — — — —
DUPBA 23:16 — — — — — — — —
15:8 BMXDUPBA<15:8>
7:0 BMXDUPBA<7:0>
BF88_2034 BMX 31:0 Write clears selected bits in BMXDUPBA, read yields undefined value
DUPBACLR
BF88_2038 BMX 31:0 Write sets selected bits in BMXDUPBA, read yields undefined value
DUPBASET
BF88_203C BMX 31:0 Write inverts selected bits in BMXDUPBA, read yields undefined value
DUPBAINV
BF88_2040 BMXDRMSZ 31:24 BMXDRMSZ<31:24>
23:16 BMXDRMSZ<23:16>
15:8 BMXDRMSZ<15:8>
7:0 BMXDRMSZ<7:0>
BF88_2050 BMXPUPBA 31:24 — — — — — — — —
23:16 — — — — BMXPUPBA<19:16>
15:8 BMXPUPBA<15:8>
7:0 BMXPUPBA<7:0>
BF88_2060 BMXPFMSZ 31:24 BMXPFMSZ<31:24>
23:16 BMXPFMSZ<23:16>
15:8 BMXPFMSZ<15:8>
7:0 BMXPFMSZ<7:0>
BF88_2070 BMX- 31:24 BMXBOOTSZ<31:24>
BOOTSZ 23:16 BMXBOOTSZ<23:16>
15:8 BMXBOOTSZ<15:8>
7:0 BMXBOOTSZ<7:0>

PIC32MX3XX/4XX
REGISTER 6-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER
r-x r-x r-x r-x r-x R/W-0 r-x r-x
— — — — — BMX- — —
CHEDMA
bit 31 bit 24

— — — BMXERRIXI BMXER- BMX- BMX- BMXERRIS
RICD ERRDMA ERRDS
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
r-x R/W-1 r-x r-x r-x R/W-0 R/W-0 R/W-0

— BMXWS- — — — BMXARB<2:0>
DRM
bit 7 bit 0
Legend:

bit 26 BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit
1 = Enable program Flash memory (data) cacheability for DMA accesses
(requires cache to have data caching enabled)
0 = Disable program Flash memory (data) cacheability for DMA accesses
(hits are still read from the cache, but misses do not update the cache)
bit 20 BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
bit 18 BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
bit 16 BMXERRIS: Bus error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction
access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction
access

PIC32MX3XX/4XX
REGISTER 6-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER (CONTINUED)
bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1 = Data RAM accesses from CPU have one Wait state for address setup
0 = Data RAM accesses from CPU have zero Wait states for address setup
bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits
111...011 = Reserved (using these Configuration modes will produce undefined behavior)
010 = Arbitration Mode 2
Note: For detailed descriptions of the arbitration modes, refer to the ‘PIC32MX Family Reference Manual,
Chapter 3. Memory Organization, Section 3.5 Bus Matrix’ (DS61132).

PIC32MX3XX/4XX
REGISTER 6-2: BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXDKPBA<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDKPBA<7:0>
bit 7 bit 0
Legend:

bit 15-11 BMXDKPBA<15:11>: DRM Kernel Program Base Address bits
When non-zero, this value selects the relative base address for kernel program space in RAM
bit 10-0 BMXDKPBA<10:0>: Read-Only bits
Value is always ‘0’, which forces 2 KB increments

PIC32MX3XX/4XX
REGISTER 6-3: BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXDUDBA<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUDBA<7:0>
bit 7 bit 0
Legend:

bit 15-11 BMXDUDBA<15:11>: DRM User Data Base Address bits
When non-zero, the value selects the relative base address for User mode data space in RAM
Note: If non-zero, the value must be greater than BMXDKPBA.
bit 10-0 BMXDUDBA<10:0>: Read-Only bits

PIC32MX3XX/4XX
REGISTER 6-4: BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXDUPBA<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXDUPBA<7:0>
bit 7 bit 0
Legend:

bit 15-11 BMXDUPBA<15:11>: DRM User Program Base Address bits
When non-zero, the value selects the relative base address for User mode program space in RAM
Note: If non-zero, BMXDUPBA must be greater than BMXDUDBA.
bit 10-0 BMXDUPBA<10:0>: Read-Only bits

PIC32MX3XX/4XX
REGISTER 6-5: BMXDRMSZ: DATA RAM SIZE REGISTER
R R R R R R R R
BMXDRMSZ<31:24>
bit 31 bit 24
R R R R R R R R
BMXDRMSZ<23:16>
bit 23 bit 16
R R R R R R R R
BMXDRMSZ<15:8>
bit 15 bit 8
R R R R R R R R
BMXDRMSZ<7:0>
bit 7 bit 0
Legend:
bit 31-0 BMXDRMSZ: Data RAM Memory (DRM) Size bits

Static value that indicates the size of the Data RAM in bytes:
0x00002000 = device has 8 KB RAM

PIC32MX3XX/4XX
REGISTER 6-6: BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS
REGISTER
— — — — — — — —
bit 31 bit 24
r-x r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0

— — — — BMXPUPBA<19:16>
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

BMXPUPBA<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

BMXPUPBA<7:0>
bit 7 bit 0
Legend:

bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits
When non-zero, this value selects the PFM relative base address for User mode program space.
bit 10-0 BMXPUPBA<10:0>: Read-Only bits

PIC32MX3XX/4XX
REGISTER 6-7: BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER
R R R R R R R R
BMXPFMSZ<31:24>
bit 31 bit 24
R R R R R R R R
BMXPFMSZ<23:16>
bit 23 bit 16
R R R R R R R R
BMXPFMSZ<15:8>
bit 15 bit 8
R R R R R R R R
BMXPFMSZ<7:0>
bit 7 bit 0
Legend:
bit 31-0 BMXPFMSZ: Program Flash Memory (PFM) Size bits

Static value that indicates the size of the PFM in bytes:
0x00008000 = device has 32 KB Flash

PIC32MX3XX/4XX
REGISTER 6-8: BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER
R R R R R R R R
BMXBOOTSZ<31:24>
bit 31 bit 24
R R R R R R R R
BMXBOOTSZ<23:16>
bit 23 bit 16
R R R R R R R R
BMXBOOTSZ<15:8>
bit 15 bit 8
R R R R R R R R
BMXBOOTSZ<7:0>
bit 7 bit 0
Legend:
bit 31-0 BMXBOOTSZ: Boot Flash Memory (BFM) Size bits

Static value that indicates the size of the Boot PFM in bytes:
0x00003000 = device has 12 KB boot Flash

PIC32MX3XX/4XX
6.3 User and Kernel Memory Areas
The two modes of operation of the PIC32MX3XX/4XX
core are User mode and Kernel mode. To support
these modes, the virtual address space is also divided
into two segments, kernel segments and user seg-
ments. The lower 2 gigabytes of virtual addresses form
the User mode partition, and the upper 2 gigabytes
forms the Kernel mode partition.
Most application will run only in Kernel mode. For these
applications, the entire program can reside in the ker-
nel address space providing full access to all
resources.
FIGURE 6-2: USER/KERNEL ADDRESS

SEGMENTS
0xFFFFFFFF
KERNEL
SEGMENTS
(KSEG 0,1,2,3)
0x80000000
0x7FFFFFFF
USER / KERNEL
SEGMENT
(USEG / KUSEG)
0x00000000

PIC32MX3XX/4XX
6.4 PIC32MX3XX/4XX Address Map 6.4.1 PHYSICAL MEMORY ADDRESS
Table 6-2 shows the address map of the The Kernel Program Flash address space starts at
PIC32MX3XX/4XX microcontroller. physical address 0x1D000000, whereas the user pro-
gram flash space starts at physical address
On reset, the PIC32MX3XX/4XX starts executing code 0xBD000000 + BMXPUPBA register value.
from 0xBFC0_0000 virtual address which reside in the
kseg1 segment (non cacheable segment). Similarly, the internal RAM is also divided into Kernel
and User partitions. The kernel RAM space starts at
physical address 0x00000000, whereas the User RAM
space starts at physical address 0xBF000000 +
BMXDUDBA register value.
By default the entire Flash memory and RAM are
mapped to the Kernel mode application only.
TABLE 6-2: PIC32MX3XX/4XX ADDRESS MAP

Virtual Addresses Physical Addresses Size in Bytes
Memory Type Begin Address End Address Begin Address End Address Calculation
Boot Flash 0xBFC00000 0xBFC02FFF 0x1FC00000 0x1FC02FFF 12 KB
Program 0xBD000000 0xBD000000 + 0x1D000000 0x1D00000 + BMXPUPBA
Kernel Address Space
Flash(1) BMXPUPBA - 1 BMXPUPBA - 1

Program 0x9D000000 0x9D000000 + 0x1D000000 0x1D000000 + BMXPUPBA
Flash(2) BMXPUPBA - 1 BMXPUPBA - 1
RAM (Data) 0x80000000 0x80000000 + 0x00000000 BMXDKPBA - 1 BMXDKPBA
BMXDKPBA - 1
RAM (Prog) 0x80000000 + 0x80000000 + BMXDKPBA BMXDUDBA -1 BMXDUDBA -
BMXDKPBA BMXDUDBA -1 BMXDKPBA
Peripheral 0xBF800000 0xBF8FFFFF 0x1F800000 0x1F8FFFFF 1 MB
User Address Space
Program 0x7D000000 + 0x7D000000 + 0xBD000000 + 0xBD000000 + PFM Size -

Flash BMXPUPBA PFM Size - 1 BMXPUPBA PFM Size - 1 BMXPUPBA
RAM (Data) 0x7F000000 + 0x7F000000 + 0xBF000000 + 0xBF000000 + BMXDUPBA -
BMXDUDBA BMXDUPBA - 1 BMXDUDBA BMXDUPBA - 1 BMXDUDBA
RAM (Prog) 0x7F000000 + 0x7F000000 + 0xBF000000 + 0xBF000000 + DRM Size -
BMXDUPBA RAM Size(3) - 1 BMXDUPBA RAM Size(3) - 1 BMXDUPBA
Note 1: Program Flash virtual addresses in the non-cacheable range (KSEG1).

2: Program Flash virtual addresses in the cacheable and prefetchable range (KSEG0).
3: The RAM size varies between PIC32MX3XX/4XX device family members.

PIC32MX3XX/4XX
6.5 Program Flash Memory Wait 6.6 Program Flash Memory
States Partitioning
For optimal performance, PFMWS(CHECON<2:0>) The Program Flash Memory can be partitioned for User
must be programmed to the minimum value possible. and Kernel mode programs as shown in Figure 6-3.
There are two parameters that determine this value: At Reset, the User mode partition does not exist
Flash Access Time – The Flash access time is (BMX-PUPBA is initialized to ‘0’). The entire Program
33 nSec for the PIC32MX3XX/4XX processor family. Flash Memory is mapped to Kernel mode program
CPU Core frequency – The Core frequency is space starting at virtual address KSEG1: 0xBD000000
programmable. Care must be taken when changing fre- (or KSEG0: 0x9D000000). To set up a partition for the
quencies to make sure that there are enough Wait User mode program, initialize BMXPUPBA as follows:
states to prevent any Flash memory access timing BMXPUPBA = BMXPFMSZ – USER_FLASH_PGM_SZ
violations. The USER_FLASH_PGM_SZ is the partition size of
To determine the required number of Wait states for a the User mode program. BMXPFMSZ is the bus matrix
particular core clock frequency, refer to Table 30-11 in register that holds the total size of Program Flash
Section 30.0 “Electrical Characteristics” of this data Memory.
sheet. Example:
Assuming the PIC32MX3XX/4XX device has
512 Kbytes of Flash memory, the BMXPFMSZ will
contain 0x00080000.
To create a user Flash program partition of
20 Kbytes (0x5000):
BMXPUPBA = 0x80000 – 0x5000 = 0x7B000
The size of the user Flash will be 20K and the size left
for the kernel Flash will be 512k – 20k = 492K.
The user Flash partition will extend from 0x7D07B000
to 0x7D07FFFF (virtual addresses).
The Kernel mode partition always starts from KSEG1:
0xBD000000 or KSEG0: 0x9D000000. In the above
example, the kernel partition will extend from
0xBD000000 to 0xBD07AFFF (492 Kbytes in size).

PIC32MX3XX/4XX
FIGURE 6-3: FLASH PARTITIONING
KSEG0: 0x9D000000
+BMXPUPBA
Kernel Flash Size(1)

KSEG1: 0xBD000000
+BMXPUPBA Flash Partition for
Kernel Program
(KSEG 0/1)
KSEG0: 0x9D000000 0x1D000000
KSEG1: 0xBD000000
User Flash Size(2)

Optional
Flash Partition for
User Program
(USEG/KUSEG)
0x7D000000+ 0xBD000000+
BMXPUPBA BMXPUPBA
0x00000000
Note 1: Kernel Flash Size = BMXPUPBA

2: User Flash Size = BMXPFMSZ-BMXPUPBA
3: If BMXPUPBA is ‘0’, then:
K Flash Size = BMXPFMSZ (i.e., all the Flash)
Usr Flash Size = 0
6.6.1 RAM PARTITIONING

The RAM memory can be divided into 4 partitions.
These are:
1. Kernel Data
2. Kernel Program
3. User Data
4. User Program
In order to execute from data RAM, a kernel or user
program partition must be defined. At Power-on Reset,
the entire data RAM is assigned to the kernel data par-
tition. This partition always starts from the base of the
data RAM. See Figure 6-4 for details.
The registers controlling the RAM partitions are BMXD-
KPBA, BMXDUDBA, and BMXDUPBA. For a detailed
discussion on how to use these registers for partition-
ing the RAM, please refer to the Memory Organization
section of the PIC32MX3XX/4XX Family Reference
Manual (DS61132).

PIC32MX3XX/4XX
FIGURE 6-4: RAM PARTITIONING
KSEG0: 0x80000000
+BMXDUDBA 0x00000000
Kernel Program Kernel Data

KSEG1: 0xA0000000 +BMXDUDBA
RAM Size(2)
+BMXDUDBA Optional
Kernel Program Partition
KSEG 0/1
KSEG0: 0x80000000
+BMXDKPBA 0x00000000
KSEG1: 0xA0000000 +BMXDKPBA
RAM Size(1)
+BMXDKPBA
Kernel Data Partition
KSEG 0/1
KSEG0: 0x80000000 0x00000000

KSEG1: 0xA0000000
User Program User Data

RAM Size(4) RAM Size(3)
Optional
User Program RAM Partition
(USEG/KUSEG)
0x7F000000 0xBF000000
+BMXDUPBA +BMXDUPBA
Optional
User RAM Partition
(USEG/KUSEG)
0x7F000000 0xBF000000
+BMXDUDBA +BMXDUDBA
0x00000000
Note 1: Kernel Data RAM Size = BMXDKPBA

2: Kernel Program RAM Size = BMXDUDBA – BMXDKPBA
3: User Data RAM Size = BMXDUPBA – BMXDUDBA
4: User Program RAM Size = DRM Size – BMXDUPBA
5: If BMXDKPBA, BMXDUDBA or BMXDUPBA is ‘0’, then:
Kernel Data RAM Size = BMXDRMSZ (i.e., all RAM)
Kernel Program RAM Size = 0
User Data RAM Size = 0
User Program RAM Size = 0
6.6.2 ADDRESS DECODE

Table 6-3 shows the address map for system
resources available to the CPU when it is operating in
either User mode or Kernel mode.
resources mapped in KSEG0 that are available to the
CPU when it is operating in Kernel mode.
resources mapped in KSEG1 that are available to the
CPU when it is operating in Kernel mode.

PIC32MX3XX/4XX
TABLE 6-3: USEG/KUSEG ADDRESS MAP
Virtual Physical
PIC32MX3XXF032x PIC32MX3XXF064x PIC32MX3XXF128x PIC32MX3XXF256x PIC32MX3XXF512x
Address Address
0x0000_0000 0x4000_0000 RSVD RSVD RSVD RSVD RSVD
0x7D00_0000 + 0xBD00_0000 +
BMXPUPBA - 1 BMXPUPBA - 1
0x7D00_0000 + 0xBD00_0000 + PFM PFM PFM PFM PFM
BMXPUPBA BMXPUPBA User Program User Program User Program User Program User Program
0x7D00_7FFF 0xBD00_7FFF
RSVD
0x7D00_FFFF 0xBD00_FFFF
RSVD
RSVD
RSVD
0x7D08_0000 0xBD08_0000 RSVD
0x7D08_0000 + 0xBD08_0000 +
BMXDUPBA - 1 BMXDUPBA - 1
0x7F00_0000 + 0xBF00_0000 + DRM DRM DRM DRM DRM
BMXDUDBA BMXDUDBA User Data User Data User Data User Data User Data
0x7F00_0000 + 0xBF00_0000 +
BMXDUPBA - 1 BMXDUPBA - 1
0x7F00_0000 + 0xBF00_0000 + DRM DRM DRM DRM DRM
BMXDUPBA BMXDUPBA User Program User Program User Program User Program User Program
0x7F00_1FFF 0xBF00_1FFF DRM=8KB DRM=8KB

RSVD
0x7F00_3FFF 0xBF00_3FFF DRM=16KB DRM=16KB DRM=16KB
RSVD
0x7F00_7FFF 0xBF00_7FFF DRM=32KB DRM=32KB DRM=32KB
0x7F0_8000 0xBF0_8000 RSVD RSVD RSVD
0x7FFF_FFFF 0xBFFF_FFFF

PIC32MX3XX/4XX
TABLE 6-4: KSEG0 ADDRESS MAP
Virtual Physical
Address Address
0x8000_0000 0x0000_0000 DRM DRM DRM DRM DRM
Kernel Data Kernel Data Kernel Data Kernel Data Kernel Data
0x8000_0000 + 0x0000_0000 +
BMXDKPBA - 1 BMXDKPBA - 1
0x8000_0000 + 0x0000_0000 + DRM DRM DRM DRM DRM
BMXDKBPA BMXDKBPA Kernel Kernel Kernel Kernel Kernel
Program Program Program Program Program
0x8000_0000 + 0x0000_0000 +
BMXDUDBA - 1 BMXDUDBA - 1
Note 1 Note 1 Note 1 Note 1 Note 1
0x8000_1FFF 0x0000_1FFF DRM=8KB DRM=8KB

RSVD
0x8000_3FFF 0x0000_3FFF DRM=16KB DRM=16KB DRM=16KB
RSVD
0x8000_7FFF 0x0000_7FFF DRM=32KB DRM=32KB DRM=32KB
RSVD RSVD RSVD
0x9CFF_FFFF 0x1CFF_FFFF
0x9D00_0000 0x1D00_0000 PFM PFM PFM PFM PFM
Kernel Program Kernel Program Kernel Program Kernel Program Kernel Program
0x9D00_0000 + 0x1D00_0000 +
0x9D00_7FFF 0x1D00_7FFF
RSVD
0x9D00_FFFF 0x1D00_FFFF
RSVD
RSVD
RSVD
0x9D08_0000 0x1D08_0000 RSVD
0x9FBF_FFFF 0x1FBF_FFFF
0x9FC0_0000 0x1FC0_0000 Boot Flash Boot Flash Boot Flash Boot Flash Boot Flash
0x9FC0_2FFF 0x1FC0_2FFF
0x9FC0_3000 0x1FC0_3000 RSVD RSVD RSVD RSVD RSVD
0x9FFF_EFFF 0x1FFF_EFFF
0x9FFF_F000 0x1FFF_F000 Test Flash Test Flash Test Flash Test Flash Test Flash
0x9FFF_FFFF 0x1FFF_FFFF
Note 1: Not available in KSEG0 if mapped to USEG/KUSEG (i.e. BMXDUDBA or BMXDUPBA non-zero).
2: Not available in KSEG0 if mapped in USEG/KUSEG (i.e. BMXPUPBA non-zero).

PIC32MX3XX/4XX
TABLE 6-5: KSEG1 ADDRESS MAP
Virtual Physical
Address Address
0xA000_0000 0x0000_0000 DRM DRM DRM DRM DRM
Kernel Data Kernel Data Kernel Data Kernel Data Kernel Data
0xA000_0000 + 0x0000_0000 +
BMXDKPBA - 1 BMXDKPBA - 1
0xA000_0000 + 0x0000_0000 + DRM DRM DRM DRM DRM
BMXDKBPA BMXDKBPA Kernel Program Kernel Program Kernel Program Kernel Program Kernel Program
0xA000_0000 + 0x0000_0000 +
BMXDUDBA - 1 BMXDUDBA - 1
0xA000_1FFF 0x0000_1FFF DRM=8KB DRM=8KB

RSVD
0xA000_3FFF 0x0000_3FFF DRM=16KB DRM=16KB DRM=16KB
RSVD
0xA000_7FFF 0x0000_7FFF DRM=32KB DRM=32KB DRM=32KB
0xA000_8000 0x0000_8000 RSVD RSVD RSVD
0xBCFF_FFFF 0x1CFF_FFFF
0xBD00_0000 0x1D00_0000 PFM PFM PFM PFM PFM
Kernel Program Kernel Program Kernel Program Kernel Program Kernel Program
0xBD00_0000 + 0x1D00_0000 +
0xBD00_0000 + 0x1D00_0000 + Note 2 Note 2 Note 2 Note 2 Note 2
BMXPUPBA BMXPUPBA
0xBD00_7FFF 0x1D00_7FFF
RSVD
0xBD00_FFFF 0x1D00_FFFF
RSVD
RSVD
RSVD
0xBD08_0000 0x1D08_0000 RSVD
0xBF7F_FFFF 0x1F7F_FFFF
0xBF80_0000 0x1F80_0000 Peripherals Peripherals Peripherals Peripherals Peripherals
0xBF8F_FFFF 0x1F8F_FFFF
0xBF90_0000 0x1F90_0000 RSVD RSVD RSVD RSVD RSVD
0xBFB_FFFF 0x1FB_FFFF
0xBFC0_0000 0x1FC0_0000 Boot Flash Boot Flash Boot Flash Boot Flash Boot Flash
0xBFC0_2FFF 0x1FC0_2FFF
0xBFC0_3000 0x1FC0_3000 RSVD RSVD RSVD RSVD RSVD
0xBFFF_EFFF 0x1FFF_EFFF
0xBFFF_F000 0x1FFF_F000 Test Flash Test Flash Test Flash Test Flash Test Flash
0xBFFF_FFFF 0x1FFF_FFFF
Note 1: Not available in KSEG1 if mapped to USEG/KUSEG (i.e. BMXDUDBA or BMXDUPBA non-zero).
2: Not available in KSEG1 if mapped in USEG/KUSEG (i.e. BMXPUPBA non-zero).

PIC32MX3XX/4XX
6.6.3 PERIPHERAL REGISTERS
LOCATIONS
Table 6-6 contains the peripheral address map for the
PIC32MX3XX/4XX device. Peripherals located on the
PB Bus are mapped to 512 byte boundaries. Peripher-
als on the FPB Bus are mapped to 4 Kbyte boundaries.
TABLE 6-6: PERIPHERAL ADDRESS TABLE

Peripheral
Start End Start End
WDT BF80_0000 BF80_01FF 1F80_0000 1F80_01FF
RTCC BF80_0200 BF80_03FF 1F80_0200 1F80_03FF
TMR1 BF80_0600 BF80_07FF 1F80_0600 1F80_07FF
TMR2 BF80_0800 BF80_09FF 1F80_0800 1F80_09FF
TMR3 BF80_0A00 BF80_0BFF 1F80_0A00 1F80_0BFF
TMR4 BF80_0C00 BF80_0DFF 1F80_0C00 1F80_0DFF
TMR5 BF80_0E00 BF80_0FFF 1F80_0E00 1F80_0FFF
Input Capture1 BF80_2000 BF80_21FF 1F80_2000 1F80_21FF
Output Compare1 BF80_3000 BF80_31FF 1F80_3000 1F80_31FF
I2C1 BF80_5000 BF80_51FF 1F80_5000 1F80_51FF
I2C2 BF80_5200 BF80_53FF 1F80_5200 1F80_53FF
SPI1 BF80_5800 BF80_59FF 1F80_5800 1F80_59FF
SPI2 BF80_5A00 BF80_5BFF 1F80_5A00 1F80_5BFF
UART1 BF80_6000 BF80_61FF 1F80_6000 1F80_61FF
UART2 BF80_6200 BF80_63FF 1F80_6200 1F80_63FF
Parallel Master Port BF80_7000 BF80_71FF 1F80_7000 1F80_71FF
ADC BF80_9000 BF80_91FF 1F80_9000 1F80_91FF
Comparator Voltage REF BF80_9800 BF80_99FF 1F80_9800 1F80_99FF
Comparator BF80_A000 BF80_A1FF 1F80_A000 1F80_A1FF
Oscillator BF80_F000 BF80_F1FF 1F80_F000 1F80_F1FF
Configuration BF80_F200 BF80_F3FF 1F80_F200 1F80_F3FF
Flash (NVM) BF80_F400 BF80_F5FF 1F80_F400 1F80_F5FF
Reset BF80_F600 BF80_F7FF 1F80_F600 1F80_F7FF
Interrupts BF88_1000 BF88_1FFF 1F88_1000 1F88_1FFF
Bus Matrix BF88_2000 BF88_2FFF 1F88_2000 1F88_2FFF
DMA BF88_3000 BF88_3FFF 1F88_3000 1F88_3FFF
Prefetch Cache BF88_4000 BF88_4FFF 1F88_4000 1F88_4FFF
USB BF88_5000 BF88_53FF 1F88_5000 1F88_53FF
GPIO BF88_6000 BF88_61FF 1F88_6000 1F88_61FF

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
7.0 FLASH PROGRAM MEMORY
The PIC32MX3XX/4XX of devices contain internal pro-

gram Flash memory for executing user code. There are
three methods by which the user can program this
memory:
1. Run-Time Self Programming (RTSP)
2. In-Circuit Serial Programming™ (ICSP™)
3. EJTAG Programming
RTSP is performed by software executing from either
Flash or RAM memory. EJTAG is performed using the
EJTAG port of the device and a EJTAG capable pro-
grammer. ICSP is performed using a serial data con-
nection to the device and allows much faster
programming times than RTSP. RTSP techniques are
described in this chapter. The ICSP and EJTAG meth-
ods are described in the “PIC32MX3XX/4XX Program-
ming Specification” (DS61145) document, which may
be downloaded from the Microchip web site.

PIC32MX3XX/4XX
7.1 FLASH Controller Registers
TABLE 7-1: FLASH CONTROLLER SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_F400 NVMCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 NVMWR NVMWREN NVMERR LVDERR LVDSTAT — — —
7:0 — — — — NVMOP<3:0>
BF80_F404 NVMCONCLR 31:0 Write clears selected bits in NVMCON, read yields undefined value
BF80_F408 NVMCONSET 31:0 Write sets selected bits in NVMCON, read yields undefined value
BF80_F40C NVMCON-INV 31:0 Write inverts selected bits in NVMCON, read yields undefined value
BF80_F410 NVMKEY 31:24 NVMKEY<31:24>
23:16 NVMKEY<23:16>
15:8 NVMKEY<15:8>
7:0 NVMKEY<7:0>
BF80_F420 NVMADDR 31:24 NVMADDR<31:24>
23:16 NVMADDR<23:16>
15:8 NVMADDR<15:8>
7:0 NVMADDR<7:0>
BF80_F424 NVMADDR- 31:0 Write clears selected bits in NVMADDR, read yields undefined value
CLR
BF80_F428 NVMADDR- 31:0 Write sets selected bits in NVMADDR, read yields undefined value
SET
BF80_F42C NVMADDR 31:0 Write inverts selected bits in NVMADDR, read yields undefined value
INV
BF80_F430 NVMDATA 31:24 NVMDATA<31:24>
23:16 NVMDATA<23:16>
15:8 NVMDATA<15:8>
7:0 NVMDATA<7:0>
BF80_F440 NVMSR- 31:24 NVMSRCADDR<31:24>
CADDR
23:16 NVMSRCADDR<23:16>
15:8 NVMSRCADDR<15:8>
7:0 NVMSRCADDR<7:0>
TABLE 7-2: FLASH CONTROLLER INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1070 IEC1 31:24 — — — — — — USBIE FCEIE
BF88_1040 IFS1 31:24 — — — — — — USBIF FCEIF
BF88_1140 IPC11 7:0 — — — FCEIP<2:0> FCEIS<1:0>
Note: This summary table contains partial register definitions that only pertain to the FLASH memory controller peripheral. Refer to
the “PIC32MX Family Reference Manual” (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
REGISTER 7-1: NVMCON: PROGRAMMING CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R-0 R-0 R-0 r-x r-x r-x

NVMWR NVMWREN NVMERR LVDERR LVDSTAT — — —
bit 15 bit 8

— — — — NVMOP3 NVMOP2 NVMOP1 NVMOP0
bit 7 bit 0
Legend:

bit 15 NVMWR: Write Control bit
This bit is writable when NVMWREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation (Hardware clears this bit when the operation completes.)
0 = Flash operation complete or inactive
Note: Wait at least 500 nsec after detecting a ‘0’ in NVMWR bit before writing to any NVM registers.
bit 14 NVMWREN: Write Enable bit
1 = Enables writes to NVMWR bit and enables LVD circuit
0 = Disables writes to NVMWR bit and disables LVD circuit
Note: This is the only bit in this register that is reset by a device Reset.
bit 13 NVMERR: Write Error bit
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR).
bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)
This error is only captured for programming/erase operations
1 = Low-voltage detected
0 = Voltage level ok for programming
bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)
This bit is read-only and is automatically set by hardware
1 = Low-voltage event active
0 = Low-voltage event NOT active

PIC32MX3XX/4XX
REGISTER 7-1: NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)
bit 3-0 NVMOP<3:0>: NVM Operation bits
0111 = Reserved
0110 = No operation
0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = No operation
0001 = Word program operation: programs word selected by NVMADD,R if it is not write-protected
0000 = No operation

PIC32MX3XX/4XX
7.2 RTSP Operation 7.3 Control Registers
RTSP allows the user code to modify Flash program There are two SFRs used to erase and write the PFM:
memory contents. The device Flash memory is divided NVMCON and NVMKEY.
into two logical Flash partitions: the Program Flash The NVMCON register (Register 7-1) controls which
Memory (PFM), and the Boot Flash Memory (BFM). blocks are to be erased, which memory block is to be
The last page in Boot Flash Memory contains the programmed and the start of the programming cycle.
DEBUG Page, which is reserved for use by the
debugger tool while debugging. NVMKEY is a write-only register that is used for write-
protection. To start a programming or erase sequence,
The program Flash array for the PIC32MX3XX/4XX the user must consecutively write 0xAA996655 and
device is built up of a series of rows. A row contains 128 0x556699AA to the NVMKEY register. Interrupts should
32-bit instruction words or 512 bytes. A group of 8 rows be disabled. Refer to Section 7.4 “Programming
compose a page; which, therefore, contains 8 × 512 = Operations” for further details.
4096 bytes or 1024 instruction words. A page of Flash
is the smallest unit of memory that can be erased at a
single time. The program Flash array can be pro-
7.4 Programming Operations
grammed in one of two ways: A complete programming sequence is necessary for
• Row programming, with 128 instruction words at a programming or erasing the internal Flash in RTSP
time. mode. A programming operation is nominally 5 ms in
• Word programming, with 1 instruction word at a duration and the processor stalls (WAITS) until the
time. operation is finished. Setting the NVMWR bit (NVM-
CON<15>) starts the operation, and the NVMWR bit is
The CPU stalls (waits) until the programming opera- automatically cleared when the operation is finished.
tion is finished. The CPU will not execute any instruc-
tion, or respond to interrupts, during this time. If any
interrupts occur during the programming cycle, they
remain pending until the cycle completes.
Note: A minimum VDD requirement for Flash
erase and write operations is required.
Refer to Section 30.1 “DC Characteris-
tics” for details.

PIC32MX3XX/4XX
7.4.1 PROGRAMMING ALGORITHM 5. Repeat steps 4 and 5, using the next available
128 words from the block in data RAM by incre-
The user can program one row of program Flash memory
menting the value in NVMADDR and
at a time. To do this, it is necessary to erase the 8-row
NVMASRCADDR, until all 1024 instructions are
erase block containing the desired row. The general
written back to Flash memory.
process is:
For protection against accidental operations, the write
1. Read eight rows of program memory
initiate sequence for NVMKEY must be used to allow
(1024 instructions) and store in data RAM.
any erase or program operation to proceed. After the
2. Update the program data in RAM with the programming command has been executed, the user
desired new data. must wait for the programming time until programming
3. Erase the page (see Example 7-1): is complete.
4. Write the first 128 words from data RAM into the
program memory buffers (see Example 7-1).
EXAMPLE 7-1: ERASING FLASH PAGE

unsigned int NVMUnlock (unsigned int nvmop)
{
unsigned int status;
// Suspend or Disable all Interrupts

asm volatile (“di %0” : “=r” (status));
// Enable Flash Write/Erase Operations and Select

// Flash operation to perform
NVMCON = nvmop;
// Write Keys
NVMKEY = 0xAA996655;
NVMKEY = 0x556699AA;
// Start the operation using the Set Register

NVMCONSET = 0x8000;
// Wait for operation to complete

while (NVMCON & 0x8000);
// Restore Interrupts
if (status & 0x00000001
asm volatile (“ei”);
else
asm volatile (“di”);
// Return NVMERR and LVDERR Error Status Bits

return (NVMCON & 0x3000)
}
unsigned int NVMErasePage(void* address)

{
unsigned int res;
// Set NVMADDR to the Start Address of page to erase

NVMADDR = (unsigned int) address;
// Unlock and Erase Page

res = NVMUnlock(0x4004);
// Return Result
return res;
}

PIC32MX3XX/4XX
EXAMPLE 7-2: ROW PROGRAMMING SEQUENCE
{


NVMCON = nvmop;
// Write Keys

NVMCONSET = 0x8000;

if (status & 0x00000001
else

}
unsigned int NVMWriteRow (void* address, void* data)

{
unsigned int res;
// Set NVMADDR to Start Address of row to program

// Set NVMSRCADDR to the SRAM data buffer Address

NVMSRCADDR = (unsigned int) data;
// Unlock and Write Row

// Return Result
return res;
}

PIC32MX3XX/4XX
EXAMPLE 7-3: WORD PROGRAMMING SEQUENCE
{


NVMCON = nvmop;
// Write Keys

NVMCONSET = 0x8000;

if (status & 0x00000001
else

}
unsigned int NVMWriteWord (void* address, unsigned int data)

{
unsigned int res;
// Load data into NVMDATA register

NVMDATA = data;
// Load address to program into NVMADDR register

// Unlock and Write Word

res = NVMUnlock (0x4001);
// Return Result
return res;
}

PIC32MX3XX/4XX
EXAMPLE 7-4: PROGRAM FLASH ERASE SEQUENCE
{


NVMCON = nvmop;
// Write Keys

NVMCONSET = 0x8000;

if (status & 0x00000001
else

}
unsigned int NVMErasePFM(void)

{
unsigned int res;
// Unlock and Erase Program Flash

// Return Result
return res;
}

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
8.0 INTERRUPTS The PIC32MX3XX/4XX interrupts module includes the
following features:
Note: This data sheet summarizes the features of • Up to 96 interrupt sources
• Up to 64 interrupt vectors
ence source. Refer to the “PIC32MX Family • Single and Multi-Vector mode operations
Reference Manual” (DS61132) for a • 5 external interrupts with edge polarity control
detailed description of this peripheral. • Interrupt proximity timer
• Module Freeze in Debug mode
PIC32MX3XX/4XX generates interrupt requests in
response to interrupt events from peripheral modules. • 7 user-selectable priority levels for each vector
The Interrupt Control Module exists external to the • 4 user-selectable subpriority levels within each
CPU logic and prioritizes the interrupt events before priority
presenting them to the CPU. • Dedicated shadow set for highest priority level
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
FIGURE 8-1: INTERRUPT CONTROLLER MODULE

Interrupt Requests
Vector Number
Interrupt Controller CPU Core

Priority Level
Shadow Set Number
Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and
bits) are associated with the CPU. Details about them are available in Section 2.0 "PIC32MX MCU".
To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this
section, and all other sections of this manual, are signified by uppercase letters only.CPU register names
are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas,
IntCtl is a CPU register.

PIC32MX3XX/4XX
8.1 Control Registers • IPTMR: Interrupt Proximity Timer Register
IPTMRCLR, IPTMRSET, IPTMRNINV: Atomic Bit
Manipulation, Write-Only Registers for IPTMR
Note: Each PIC32MX device variant may have
one or more Interrupt channels. An ‘x’ • IFS0, IFS1: Interrupt Flag Status Registers
used in the names of control/Status bits IFSxCLR, IFSxSET, IFSxINV: Atomic Bit
and registers denotes the particular chan- Manipulation, Write-Only Registers for IFSx
nel. Refer to the specific device data • IEC0, IEC1: Interrupt Enable Control Registers
sheets for more details. IECxCLR, IECxSET, IECxINV: Atomic Bit
Manipulation, Write-Only Registers for IECx
The interrupts module consists of the following Special
• IPC0 - IPC11: Interrupt Priority Control Registers
Function Registers (SFRs):
IPCxCLR, IPCxSET, IPCxINV: Atomic Bit
• INTCON: Interrupt Control Register Manipulation, Write-Only Registers for IPCx
INTCONCLR, INTCONSET, INTCONINV: Atomic Bit
The following table provides a brief summary of inter-
Manipulation, Write-Only Registers for INTCON
rupts module related registers. Corresponding regis-
• INTSTAT: Interrupt Status Register ters appear after the summary, followed by a detailed
INTSTATCLR, INTSTATSET, INTSTATINV: Atomic description of each register.
Bit Manipulation, Write-Only Registers for INTSTAT
TABLE 8-1: INTERRUPT SFR SUMMARY

Address
Name
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1000 INTCON 31:24 — — — — — — — —
23:16 — — — — — — — SS0
15:8 — FRZ — MVEC — TPC<2:0>
7:0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP
BF88_1004 INTCONCLR 31:0 Write clears the selected bits in INTCON, read yields undefined value
BF88_1008 INTCONSET 31:0 Write sets the selected bits in INTCON, read yields undefined value
BF88_100C INTCONINV 31:0 Write inverts the selected bits in INTCON, read yields undefined value
BF88_1010 INTSTAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — RIPL<2:0>
7:0 — — VEC<5:0>
BF88_1014 INTSTATCLR 31:0 Write clears the selected bits in INTSTAT, read yields undefined value
BF88_1018 INTSTATSET 31:0 Write sets the selected bits in INTSTAT, read yields undefined value
BF88_101C INTSTATINV 31:0 Write inverts the selected bits in INTSTAT, read yields undefined value
BF88_1020 IPTMR 31:24
23:16 IPTMR<31:0>
15:8
7:0
BF88_1024 IPTMRCLR 31:0 Write clears the selected bits in IPTMR, read yields undefined value
BF88_1028 IPTMRSET 31:0 Write clears the selected bits in IPTMR, read yields undefined value
BF88_102C IPTMRINV 31:0 Write clears the selected bits in IPTMR, read yields undefined value
BF88_1030 IFS0 31:24 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF
23:16 SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF
15:8 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF
7:0 INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF
BF88_1034 IFS0CLR 31:0 Write clears the selected bits in IFS0, read yields undefined value
BF88_1038 IFS0SET 31:0 Write sets the selected bits in IFS0, read yields undefined value
BF88_103C IFS0INV 31:0 Write inverts the selected bits in IFS0, read yields undefined value

PIC32MX3XX/4XX
TABLE 8-1: INTERRUPT SFR SUMMARY (CONTINUED)
Address
Name
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
23:16 — — — — DMA3IF DMA2IF DMA1IF DMA0IF
15:8 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF
7:0 SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF
BF88_1044 IFS1CLR 31:0 Write clears the selected bits in IFS1, read yields undefined value
BF88_1048 IFS1SET 31:0 Write sets the selected bits in IFS1, read yields undefined value
BF88_104C IFS1INV 31:0 Write inverts the selected bits in IFS1, read yields undefined value
BF88_1060 IEC0 31:24 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE
23:16 SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE
15:8 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE
7:0 INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE
BF88_1064 IEC0CLR 31:0 Write clears the selected bits in IEC0, read yields undefined value
BF88_1068 IEC0SET 31:0 Write sets the selected bits in IEC0, read yields undefined value
BF88_106C IEC0INV 31:0 Write inverts the selected bits in IEC0, read yields undefined value
23:16 — — — — DMA3IE DMA2IE DMA1IE DMA0IE
15:8 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE
7:0 SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE
BF88_1074 IEC1CLR 31:0 Write clears the selected bits in IEC1, read yields undefined value
BF88_1078 IEC1SET 31:0 Write sets the selected bits in IEC1, read yields undefined value
BF88_107C IEC1INV 31:0 Write inverts the selected bits in IEC1, read yields undefined value
BF88_1090 IPC0 31:24 — — — INT0IP<2:0> INT0IS<1:0>
23:16 — — — CS1IP<2:0> CS1IS<1:0>
15:8 — — — CS0IP<2:0> CS0IS<1:0>
7:0 — — — CTIP<2:0> CTIS<1:0>
BF88_1094 IPC0CLR 31:0 Write clears the selected bits in IPC0, read yields undefined value
BF88_1098 IPC0SET 31:0 Write sets the selected bits in IPC0, read yields undefined value
BF88_109C IPC0INV 31:0 Write inverts the selected bits in IPC0, read yields undefined value
BF88_10A0 IPC1 31:24 — — — INT1IP<2:0> INT1IS<1:0>
23:16 — — — OC1IP<2:0> OC1IS<1:0>
15:8 — — — IC1IP<2:0> IC1IS<1:0>
7:0 — — — T1IP<2:0> T1IS<1:0>
BF88_10A4 IPC1CLR 31:0 Write clears the selected bits in IPC1, read yields undefined value
BF88_10A8 IPC1SET 31:0 Write sets the selected bits in IPC1, read yields undefined value
BF88_10AC IPC1INV 31:0 Write inverts the selected bits in IPC1, read yields undefined value
BF88_10B0 IPC2 31:24 — — — INT2IP<2:0> INT2IS<1:0>
23:16 — — — OC2IP<2:0> OC2IS<1:0>
15:8 — — — IC2IP<2:0> IC2IS<1:0>
7:0 — — — T2IP<2:0> T2IS<1:0>
BF88_10B4 IPC2CLR 31:0 Write clears the selected bits in IPC2, read yields undefined value
BF88_10B8 IPC2SET 31:0 Write sets the selected bits in IPC2, read yields undefined value
BF88_10BC IPC2INV 31:0 Write inverts the selected bits in IPC2, read yields undefined value

PIC32MX3XX/4XX
Address
Name
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10C0 IPC3 31:24 — — — INT3IP<2:0> INT3IS<1:0>
23:16 — — — OC3IP<2:0> OC3IS<1:0>
15:8 — — — IC3IP<2:0> IC3IS<1:0>
7:0 — — — T3IP<2:0> T3IS<1:0>
BF88_10C4 IPC3CLR 31:0 Write clears the selected bits in IPC3, read yields undefined value
BF88_10C8 IPC3SET 31:0 Write sets the selected bits in IPC3, read yields undefined value
BF88_10CC IPC3INV 31:0 Write inverts the selected bits in IPC3, read yields undefined value
BF88_10D0 IPC4 31:24 — — — INT4IP<2:0> INT4IS<1:0>
23:16 — — — OC4IP<2:0> OC4IS<1:0>
15:8 — — — IC4IP<2:0> IC4IS<1:0>
7:0 — — — T4IP<2:0> T4IS<1:0>
BF88_10D4 IPC4CLR 31:0 Write clears the selected bits in IPC4, read yields undefined value
BF88_10D8 IPC4SET 31:0 Write sets the selected bits in IPC4, read yields undefined value
BF88_10DC IPC4INV 31:0 Write inverts the selected bits in IPC4, read yields undefined value
BF88_10E0 IPC5 31:24 — — — SPI1IP<2:0> SPI1IS<1:0>
23:16 — — — OC5IP<2:0> OC5IS<1:0>
15:8 — — — IC5IP<2:0> IC5IS<1:0>
7:0 — — — T5IP<2:0> T5IS<1:0>
BF88_10E4 IPC5CLR 31:0 Write clears the selected bits in IPC5, read yields undefined value
BF88_10E8 IPC5SET 31:0 Write sets the selected bits in IPC5, read yields undefined value
BF88_10EC IPC5INV 31:0 Write inverts the selected bits in IPC5, read yields undefined value
BF88_10F0 IPC6 31:24 — — — AD1IP<2:0> AD1IS<1:0>
23:16 — — — CNIP<2:0> CNIS<1:0>
15:8 — — — I2C1IP<2:0> I2C1IS<1:0>
7:0 — — — U1IP<2:0> U1IS<1:0>
BF88_10F4 IPC6CLR 31:0 Write clears the selected bits in IPC6, read yields undefined value
BF88_10F8 IPC6SET 31:0 Write sets the selected bits in IPC6, read yields undefined value
BF88_10FC IPC6INV 31:0 Write inverts the selected bits in IPC6, read yields undefined value
BF88_1100 IPC7 31:24 — — — SPI2IP<2:0> SPI2IS<1:0>
23:16 — — — CMP2IP<2:0> CMP2IS<1:0>
15:8 — — — CMP1IP<2:0> CMP1IS<1:0>
7:0 — — — PMPIP<2:0> PMPIS<1:0>
BF88_1110 IPC8 31:24 — — — RTCCIP<2:0> RTCCIS<1:0>
23:16 — — — FSCMIP<2:0> FSCMIS<1:0>
15:8 — — — I2C2IP<2:0> I2C2IS<1:0>
7:0 — — — U2IP<2:0> U2IS<1:0>

PIC32MX3XX/4XX
Address
Name
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1120 IPC9 31:24 — — — DMA3IP<2:0> DMA3IS<1:0>
23:16 — — — DMA2IP<2:0> DMA2IS<1:0>
15:8 — — — DMA1IP<2:0> DMA1IS<1:0>
7:0 — — — DMA0IP<2:0> DMA0IS<1:0>
BF88_1130 IPC10 31:24 — — — — _
23:16 — — — — —
15:8 — — — — _
7:0 — — — — —
BF88_1140 IPC11 31:24 — — — — _
23:16 — — — — —
15:8 — — — USBIP<2:0> USBIS<1:0>
7:0 — — — FCEIP<2:0> FCEIS<1:0>

PIC32MX3XX/4XX
REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER
— — — — — — — —
bit 31 bit 24
r-x r-x r-x r-x r-x r-x r-x R/W-0

— — — — — — — SS0
bit 23 bit 16
r-x R/W-0 r-x R/W-0 r-x R/W-0 R/W-0 R/W-0

— FRZ — MVEC — TPC<2:0>
bit 15 bit 8

— — — INT4EP INT3EP INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
U = Unimplemented bit -n = Bit value at POR (‘0’, ‘1’, x = Unknown)

bit 16 SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
bit 14 FRZ: Freeze in Debug Exception Mode bit
1 = Freeze operation when CPU is in Debug Exception mode
0 = Continue operation even when CPU is in Debug Exception mode
Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode.
bit 12 MVEC: Multi-Vector Configuration bit
1 = Interrupt controller configured for Multi-Vectored mode
0 = Interrupt controller configured for Single Vectored mode
bit 10-8 TPC<2:0>: Temporal Proximity Control bits
111 = Interrupt of group priority 7 or lower starts the IP timer
001 = Interrupt of group priority 1 starts the IP timer
000 = Disables proximity timer
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge

PIC32MX3XX/4XX
REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER (CONTINUED)
1 = Rising edge
0 = Falling edge
1 = Rising edge
0 = Falling edge
1 = Rising edge
0 = Falling edge
1 = Rising edge
0 = Falling edge

PIC32MX3XX/4XX
REGISTER 8-2: INTSTAT: INTERRUPT STATUS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
r-x r-x r-x r-x r-x R-0 R-0 R-0

— — — — — RIPL<2:0>
bit 15 bit 8
r-x r-x R-0 R-0 R-0 R-0 R-0 R-0

— — VEC<5:0>
bit 7 bit 0
Legend:

bit 10-8 RIPL<2:0>: Requested Priority Level bits
000 — 111 = The priority level of the latest interrupt presented to the CPU
Note: This value should only be used when the interrupt controller is configured for Single
Vector mode.
bit 5-0 VEC: Interrupt Vector bits
00000 — 11111 = The interrupt vector that is presented to the CPU
Note: This value should only be used when the interrupt controller is configured for Single
Vector mode.

PIC32MX3XX/4XX
REGISTER 8-3: IPTMR: INTERRUPT PROXIMITY TIMER REGISTER
IPTMR<31:24>
bit 31 bit 24

IPTMR<23:16>
bit 23 bit 16

IPTMR<15:8>
bit 15 bit 8

IPTMR<7:0>
bit 7 bit 0
Legend:
bit 31-0 IPTMR: Interrupt Proximity Timer Reload bits

Used by the interrupt proximity timer as a reload value when the interrupt proximity timer is triggered
by an interrupt event.

PIC32MX3XX/4XX
REGISTER 8-4: IFS0: INTERRUPT FLAG STATUS REGISTER 0
I2C1MIF I2CSIF I2CBIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF
bit 31 bit 24

SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF
bit 23 bit 16

INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF
bit 15 bit 8

INT1IF OC1IF IC2IF T1IF INT0IF CS1IF CS0IF CTIF
bit 7 bit 0
Legend:
bit 31 I2C1MIF: I2C1 Master Interrupt Request Flag bit

1 = Interrupt request has occurred
0 = No interrupt request has a occurred
bit 30 I2CSIF: I2C1 Slave Interrupt Request Flag bit
bit 29 I2CBIF: I2C1 Bus Collision Interrupt Request Flag bit
bit 28 U1TXIF: UART1 Transmitter Interrupt Request Flag bit
bit 27 U1RXIF: UART1 Receiver Interrupt Request Flag bit
bit 26 U1EIF: UART1 Error Interrupt Request Flag bit
bit 25 SPI1RXIF: SPI1 Receive Interrupt Request Flag bit
bit 24 SPI1TXIF: SPI1 Transmitter Interrupt Request Flag bit
bit 23 SPI1EIF: SPI1 Error Interrupt Request Flag bit

PIC32MX3XX/4XX
REGISTER 8-4: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 22 OC5IF: Output Compare 5 Interrupt Request Flag bit
bit 21 IC5IF: Input Compare 5 Interrupt Request Flag bit
bit 20 T5IF: Timer5 Interrupt Request Flag bit
bit 19 INT4IF: External Interrupt 4 Request Flag bit

PIC32MX3XX/4XX
bit 2 CS1IF: Core Software Interrupt 1 Request Flag bit
bit 1 CS0IF: Core Software Interrupt 0 Request Flag bit
bit 0 CTIF: Core Timer Interrupt Request Flag bit

PIC32MX3XX/4XX
REGISTER 8-5: IFS1: INTERRUPT FLAG STATUS REGISTER 1
— — — — — — USBIF FCEIF
bit 31 bit 24

— — — — DMA3IF DMA2IF DMA1IF DMA0IF
bit 23 bit 16

RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF
bit 15 bit 8

SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF
bit 7 bit 0
Legend:

bit 25 USBIF: USB Interrupt Request Flag bit
bit 24 FCEIF: Flash Control Event Interrupt Flag bit
bit 19 DMA3IF: DMA3 Interrupt Request Flag bit
bit 15 RTCCIF: Real Time Clock Interrupt Flag bit
bit 14 FSCMIF: Fail-Safe Clock Monitor Interrupt Flag bit

PIC32MX3XX/4XX
bit 13 I2C2MIF: I2C2 Master Interrupt Request bit
bit 12 I2C2SIF: I2C2 Slave Interrupt Request bit
bit 11 I2C2BIF: I2C2 Bus Collision Interrupt Request bit
bit 10 U2TXIF: UART2 Transmitter Interrupt Request bit
bit 9 U2RXIF: UART2 Receiver Interrupt Request Flag bit
bit 8 U2EIF: UART2 Error Interrupt Request Flag bit
bit 7 SPI2RXIF: SPI2 Receiver Interrupt Request Flag bit
bit 6 SPI2TXIF: SPI2 Transmitter Interrupt Request Flag bit
bit 5 SPI2EIF: SPI2 Error Interrupt Request Flag bit
bit 4 CMP2IF: Comparator 2 Interrupt Request Flag bit
bit 3 CMP1IF: Comparator 1 Interrupt Request Flag bit
bit 2 PMPIF: Parallel Master Port Interrupt Request Flag bit
bit 1 AD1IF: Analog-to-Digital 1 Interrupt Request Flag bit
bit 0 CNIF: Input Change Interrupt Request Flag bit

PIC32MX3XX/4XX
REGISTER 8-6: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE
bit 31 bit 24

SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE
bit 23 bit 16

INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE
bit 15 bit 8

INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE
bit 7 bit 0
Legend:
bit 31 I2C2MIE: I2C2 Master Interrupt Enable bit

bit 30 I2C1SIE: I2C1 Slave Interrupt Enable bit
bit 29 I2C1BIE: I2C1 Bus Collision Interrupt Enable bit
bit 28 U1TXIE: UART1 Transmitter Interrupt Enable bit
bit 27 U1RXIE: UART1 Receiver Interrupt Enable bit
bit 26 U1EIE: UART1 Error Interrupt Enable bit
bit 25 SPI1RXIE: SPI1 Receive Interrupt Enable bit
bit 24 SPI1TXIE: SPI1 Transmitter Interrupt Enable bit
bit 23 SPI1EIE: SPI1 Error Interrupt Enable bit

PIC32MX3XX/4XX
REGISTER 8-6: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 22 OC5IE: Output Compare 5 Interrupt Enable bit
bit 21 IC5IE: Input Compare 5 Interrupt Enable bit
bit 20 T5IE: Timer5 Interrupt Enable bit
bit 19 INT4IE: External Interrupt 4 Enable bit

PIC32MX3XX/4XX
bit 2 CS1IE: Core Software Interrupt 1 Enable bit
bit 1 CS0IE: Core Software Interrupt 0 Enable bit
bit 0 CTIE: Core Timer Interrupt Enable bit

PIC32MX3XX/4XX
REGISTER 8-7: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
bit 31 bit 24

bit 23 bit 16

bit 15 bit 8

bit 7 bit 0
Legend:

bit 25 USBIE: USB Interrupt Enable bit
bit 24 FCEIE: Flash Control Event Interrupt Enable bit
bit 19 DMA3IE: DMA3 Interrupt Enable bit
bit 15 RTCCIE: Real-Time Clock Interrupt Enable bit
bit 14 FSCMIE: Fail-Safe Clock Monitor Interrupt Enable bit

PIC32MX3XX/4XX
bit 13 I2C2MIE: I2C2 Master Interrupt Request bit
bit 12 I2C2SIE: I2C2 Slave Interrupt Request bit
bit 11 I2C2BIE: I2C2 Bus Collision Interrupt Request bit
bit 10 U2TXIE: UART2 Transmitter Interrupt Request bit
bit 9 U2RXIE: UART2 Receiver Interrupt Enable bit
bit 8 U2EIE: UART2 Error Interrupt Enable bit
bit 7 SPI2RXIE: SPI2 Receiver Interrupt Enable bit
bit 6 SPI2TXIE: SPI2 Transmitter Interrupt Enable bit
bit 5 SPI2EIE: SPI2 Error Interrupt Enable bit
bit 4 CMP2IE: Comparator 2 Interrupt Enable bit
bit 3 CMP1IE: Comparator 1 Interrupt Enable bit
bit 2 PMPIE: Parallel Master Port Interrupt Enable bit
bit 1 AD1IE: Analog-to-Digital 1 Interrupt Enable bit
bit 0 CNIE: Input Change Interrupt Enable bit

PIC32MX3XX/4XX
— — — INT0IP<2:0> INT0IS<1:0>
bit 31 bit 24

— — — CS1IP<2:0> CS1IS<1:0>
bit 23 bit 16

— — — CS0IP<2:0> CS0IS<1:0>
bit 15 bit 8

— — — CTIP<2:0> CTIS<1:0>
bit 7 bit 0
Legend:

bit 28-26 INT0IP<2:0>: External Interrupt 0 Priority bits
bit 25-24 INT0IS<1:0>: External Interrupt 0 Subpriority bits
bit 20-18 CS1IP<2:0>: Core Software 1 Interrupt Priority bits
bit 17-16 CS1IS<1:0>: Core Software 1 Interrupt subpriority bits

PIC32MX3XX/4XX
REGISTER 8-8: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 (CONTINUED)
bit 12-10 CS0IP<2:0>: Core Software 0 Interrupt Priority bits
bit 9-8 CS0IS<1:0>: Core Software 0 Interrupt Subpriority bits
bit 4-2 CTIP<2:0>: Core Timer Interrupt Priority bits
bit 1-0 CTIS<1:0>: Core Timer Interrupt Subpriority bits

PIC32MX3XX/4XX
— — — INT1IP<2:0> INT1IS<1:0>
bit 31 bit 24

— — — OC1IP<2:0> OC1IS<1:0>
bit 23 bit 16

— — — IC1IP<2:0> IC1IS<1:0>
bit 15 bit 8

— — — T1IP<2:0> T1IS<1:0>
bit 7 bit 0
Legend:

bit 20-18 OC1IP<2:0>: Output Compare 1 Interrupt Priority bits
bit 17-16 OC1IS<1:0>: Output Compare 1 Interrupt Subpriority bits

PIC32MX3XX/4XX
bit 12-10 IC1IP<2:0>: Input Compare 1 Interrupt Priority bits
bit 9-8 IC1IS<1:0>: Input Compare 1 Interrupt Subpriority bits
bit 4-2 T1IP<2:0>: Timer1 Interrupt Priority bits
bit 1-0 T1IS<1:0>: Timer1 Interrupt Subpriority bits

PIC32MX3XX/4XX
— — — INT2IP<2:0> INT2IS<1:0>
bit 31 bit 24

— — — OC2IP<2:0> OC2IS<1:0>
bit 23 bit 16

— — — IC2IP<2:0> IC2IS<1:0>
bit 15 bit 8

— — — T2IP<2:0> T2IS<1:0>
bit 7 bit 0
Legend:


PIC32MX3XX/4XX

PIC32MX3XX/4XX
— — — INT3IP<2:0> INT3IS<1:0>
bit 31 bit 24

— — — OC3IP<2:0> OC3IS<1:0>
bit 23 bit 16

— — — IC3IP<2:0> IC3IS<1:0>
bit 15 bit 8

— — — T3IP<2:0> T3IS<1:0>
bit 7 bit 0
Legend:

111 = Interrupt Priority is 7

PIC32MX3XX/4XX

PIC32MX3XX/4XX
— — — INT4IP<2:0> INT4IS<1:0>
bit 31 bit 24

— — — OC4IP<2:0> OC4IS<1:0>
bit 23 bit 16

— — — IC4IP<2:0> IC4IS<1:0>
bit 15 bit 8

— — — T4IP<2:0> T4IS<1:0>
Legend:


PIC32MX3XX/4XX

PIC32MX3XX/4XX
— — — SPI1IP<2:0> SPI1IS<1:0>
bit 31 bit 24

— — — OC5IP<2:0> OC5IS<1:0>
bit 23 bit 16

— — — IC5IP<2:0> IC5IS<1:0>
bit 15 bit 8

— — — T5IP<2:0> T5IS<1:0>
bit 7 bit 0
Legend:

bit 28-26 SPI1IP<2:0>: SPI1 Interrupt Priority bits
bit 25-24 SPI1IS<1:0>: SPI1 Interrupt Subpriority bits

PIC32MX3XX/4XX

PIC32MX3XX/4XX
— — — AD1IP<2:0> AD1IS<1:0>
bit 31 bit 24

— — — CNIP<2:0> CNIS<1:0>
bit 23 bit 16

— — — I2C1IP<2:0> I2C1IS<1:0>
bit 15 bit 8

— — — U1IP<2:0> U1IS<1:0>
bit 7 bit 0
Legend:

bit 28-26 AD1IP<2:0>: Analog-to-Digital 1 Interrupt Priority bits
bit 25-24 AD1IS<1:0>: Analog-to-Digital 1 Subpriority bits
bit 20-18 CNIP<2:0>: Input Change Interrupt Priority bits
bit 17-16 CNIS<1:0>: Input Change Subpriority bits

PIC32MX3XX/4XX
bit 12-10 I2C1IP<2:0>: I2C1 Interrupt Priority bits
bit 9-8 I2C1IS<1:0>: I2C1 Interrupt Subpriority bits
bit 4-2 U1IP<2:0>: UART1 Interrupt Priority bits
bit 1-0 U1IS<1:0>: UART1 Interrupt Subpriority bits

PIC32MX3XX/4XX
— — — SPI2IP<2:0> SPI2IS<1:0>
bit 31 bit 24

— — — CMP2IP<2:0> CMP2IS<1:0>
bit 23 bit 16

— — — CMP1IP<2:0> CMP1IS<1:0>
bit 15 bit 8

— — — PMPIP<2:0> PMPIS<1:0>
bit 7 bit 0
Legend:

bit 28-26 SPI2IP<2:0>: SPI2 Interrupt Priority bits
bit 25-24 SPI2IS<1:0>: SPI2 Interrupt Subpriority bits
bit 20-18 CMP2IP<2:0>: Compare 2 Interrupt Priority bits
bit 17-16 CMP2IS<1:0>: Compare 2 Interrupt Subpriority bits

PIC32MX3XX/4XX
bit 12-10 CMP1IP<2:0>: Compare 1 Interrupt Priority bits
bit 9-8 CMP1IS<1:0>: Compare 1 Interrupt Subpriority bits
bit 4-2 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits
bit 1-0 PMPIS<1:0>: Parallel Master Port Interrupt Subpriority bits

PIC32MX3XX/4XX
— — — RTCCIP<2:0> RTCCIS<1:0>
bit 31 bit 24

— — — FSCMIP<2:0> FSCMIS<1:0>
bit 23 bit 16

— — — I2C2IP<2:0> I2C2IS<1:0>
bit 15 bit 8

— — — U2IP<2:0> U2IS<1:0>
bit 7 bit 0
Legend:

bit 28-26 RTCCIP<2:0>: Real-Time Clock Interrupt Priority bits
bit 25-24 RTCCIS<1:0>: Real-Time Clock Interrupt subpriority bits
bit 12-10 FSCMIP<2:0>: Fail-Safe Clock Monitor Interrupt Priority bits
bit 9-8 FSCMIS<1:0>: Fail-Safe Clock Monitor Interrupt subpriority bits

PIC32MX3XX/4XX
bit 12-10 I2C2IP<2:0>: I2C2 Interrupt Priority bits
bit 9-8 I2C2IS<1:0>: I2C2 Interrupt subpriority bits
bit 4-2 U2IP<2:0>: UART2 Interrupt Priority bits
bit 1-0 U2IS<1:0>: UART2 subpriority bits

PIC32MX3XX/4XX
— — — DMA3IP<2:0> DMA3IS<1:0>
bit 31 bit 24

— — — DMA2IP<2:0> DMA2IS<1:0>
bit 23 bit 16

— — — DMA1IP<2:0> DMA1IS<1:0>
bit 15 bit 8

— — — DMA0IP<2:0> DMA0IS<1:0>
bit 7 bit 0
Legend:

bit 28-26 DMA3IP<2:0>: DMA3 Interrupt Priority bits
bit 25-24 DMA3IS<1:0>: DMA3 Interrupt Subpriority bits

PIC32MX3XX/4XX
bit 1-0 DMA0IS<1:0>: DMA0 Subpriority bits

PIC32MX3XX/4XX
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — USBIP<2:0> USBIS<1:0>
bit 15 bit 8

— — — FCEIP<2:0> FCEIS<1:0>
bit 7 bit 0
Legend:

bit 12-10 USBIP<2:0>: USB Interrupt Priority bits
bit 9-8 USBIS<1:0>: USB Sub-Priority bits
11 = Interrupt Sub-Priority is 3
bit 4-2 FCEIP<2:0>: Flash Control Event Interrupt Priority bits
bit 1-0 FCEIS<1:0>: Flash Control Event Interrupt Subpriority bits

PIC32MX3XX/4XX
TABLE 8-2: INTERRUPT IRQ AND VECTOR LOCATION
Interrupt Source IRQ(1) Vector Number
Highest Natural Order Priority
CT – Core Timer Interrupt 0 0
CS0 – Core Software Interrupt 0 1 1
CS1 – Core Software Interrupt 1 2 2
INT0 – External Interrupt 0 3 3
T1 – Timer1 4 4
IC1 – Input Capture 1 5 5
OC1 – Output Compare 1 6 6
T2 – Timer2 8 8
T3 – Timer3 12 12
T4 – Timer4 16 16
T5 – Timer5 20 20
SPI1E – SPI1 Fault 23 23
SPI1TX – SPI1 Transfer Done 24 23
SPI1RX – SPI1 Receive Done 25 23
U1E – UART1 Error 26 24
U1RX – UART1 Receiver 27 24
U1TX – UART1 Transmitter 28 24
I2C1B – I2C1 Bus Collision Event 29 25
I2C1S – I2C1 Slave Event 30 25
I2C1M – I2C1 Master Event 31 25
CN – Input Change Interrupt 32 26
AD1 – ADC1 convert done 33 27
PMP – Parallel Master Port 34 28
CMP1 – Comparator Interrupt 35 29
CMP2 – Comparator Interrupt 36 30
SPI2E – SPI2 Fault 37 31
SPI2TX – SPI2 Transfer Done 38 31
Note 1: The “IRQ Number” in Table 8-2 is also the “Interrupt Number” listed in the IFSx, IECx and IPSx register
definitions.

PIC32MX3XX/4XX
TABLE 8-2: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)
Interrupt Source IRQ(1) Vector Number
SPI2RX – SPI2 Receive Done 39 31
U2E – UART2 Error 40 32
U2RX – UART2 Receiver 41 32
U2TX – UART2 Transmitter 42 32
I2C2B – I2C2 Bus Collision Event 43 33
I2C2S – I2C2 Slave Event 44 33
I2C2M – I2C2 Master Event 45 33
FSCM – Fail-Safe Clock Monitor 46 34
RTCC – Real-Time Clock 47 35
DMA0 – DMA Channel 0 48 36
FCE – Flash Control Event 56 44
USB 57 45
(Reserved)
Lowest Natural Order Priority
Note 1: The “IRQ Number” in Table 8-2 is also the “Interrupt Number” listed in the IFSx, IECx and IPSx register
definitions.

PIC32MX3XX/4XX
8.2 Operation The INTSTAT register contains the Interrupt Vector
Number bits, VEC (INTSTAT<5:0>), and Requested
The interrupt controller is responsible for pre- Interrupt Priority bits, RIPLx (INTSTAT<10:8>), of the
processing Interrupt Requests (IRQ) from a number of current pending interrupt. This may not be the same as
on-chip peripherals and presenting them in the the interrupt which caused the core to diverge from
appropriate order to the processor. normal execution.
Figure 8-2 depicts the process within the interrupt con- The processor returns to the previous state when the
troller module. The interrupt controller is designed to ERET (Exception Return) instruction is executed. ERET
receive up to 96 IRQs from the processor core and clears the EXL bit, restores the program counter and
from on-chip peripherals capable of generating inter- reverts the current shadow set to the previous one.
rupts. All IRQs are sampled on the rising edge of the
SYSCLK and latched in associated IFSx registers. A The PIC32MX3XX/4XX interrupt controller can be con-
pending IRQ is indicated by the flag bit being equal to figured to operate in one of two modes:
‘1’ in an IFSx register. The pending IRQ will not cause • Single Vector mode – all interrupt requests will be
further processing if the corresponding bit in the Inter- serviced at one vector address (mode out of
rupt Enable (IECx) register is clear. The IECx bits act to Reset).
gate the interrupt flag. If the interrupt is enabled, all • Multi-Vector mode – interrupt requests will be
IRQs are encoded into a 5-bit wide vector number. The serviced at the calculated vector address.
5-bit vector results in 0 to 63 unique interrupt vector
numbers. Since there are more IRQs than available
vector numbers, some IRQs share common vector Notes: While the user can, during run time,
numbers. Each vector number is assigned an interrupt reconfigure the interrupt controller from
priority level and shadow set number. The priority level Single Vector to Multi-Vector mode (or
is determined by the IPCx register setting of the asso- vice versa), such action is strongly dis-
ciated vector. In Multi-Vector mode, all priority level 7 couraged. Changing interrupt controller
interrupts use a dedicated register set, while in Single modes after initialization may result in
Vector mode, all interrupts may receive a dedicated undefined behavior.
shadow set. The interrupt controller selects the highest The M4K core supports several different
priority IRQ among all pending IRQs and presents the interrupt processing modes. The interrupt
associated vector number, priority level and shadow controller is designed to work in External
set number to the processor core. Interrupt Controller mode.
The processor core samples the presented vector
information between the ‘E’ and ‘M’ stage of the pipe-
line. If the vector’s priority level presented to the core is
greater than the current priority indicated by the CPU
Interrupt Priority bits IPLx (Status<15:10>), the inter-
rupt is serviced; otherwise, it will remain pending until
the current priority is less than the interrupt’s priority.
When servicing an interrupt, the processor core pushes
the program counter into the Exception Program Coun-
ter (EPC) register in the CPU and sets Exception Level
bit EXL (Status<1>) in the CPU. The EXL bit disables
further interrupts until the application explicitly re-
enables them by clearing the EXL bit. Next, it branches
to the vector address calculated from the presented
vector number.

PIC32MX3XX/4XX
FIGURE 8-2: INTERRUPT PROCESS
ENCODE LATCH COMPARE GENERATE
StatusIPL
RIPL Any Request
Interrupt Request
>
IPL
•
StatusIE
Interrupt Exception
Load IntCtlVS
Fields
Vector Number
Interrupt Sources
Interrupt Module
Generator
Offset
CauseRIPL
Requested IPL Exception Vector Offset
Shadow Set Number

SRSCtlEICSS
Shadow Set Number
Note: SRSCtl, Cause, Status, and IntCtl registers are CPU registers and are described in Section 2. “CPU”.

PIC32MX3XX/4XX
8.3 Single Vector Mode To configure the CPU in Single Vector mode, the follow-
ing CPU registers (IntCtl, Cause, and Status) and INT-
On any form of Reset, the interrupt controller initializes CON register must be configured as follows:
to Single Vector mode. When the MVEC (INT-
CON<12>) bit is ‘0’, the interrupt controller operates in • EBase ≠ 00000
Single Vector mode. In this mode, the CPU always vec- • VS (IntCtl<9:5>) ≠ 00000
tors to the same address. • IV (Cause<23>) = 1
Note: Users familiar with MIPS32 Architecture • EXL (Status<1>) = 0
must note that the M4K core in • BEV (Status<22>) = 0
PIC32MX3XX/4XX is still operating in • MVEC (INTCON<12>) = 0
External Interrupt Controller (EIC) mode. • IE (Status<0>) = 1
The PIC32MX3XX/4XX achieves Single
Vector mode by forcing all IRQs to use a
vector number of 0x00. Because the M4K
core in PIC32MX3XX/4XX always oper-
ates in EIC mode, the single vector behav-
ior through “Interrupt Compatibility Mode,”
as defined by MIPS32 Architecture, is not
recommended.
EXAMPLE 8-1: SINGLE VECTOR MODE INITIALIZATION

/*
Set the CP0 registers for multi-vector interrupt
Place EBASE at 0xBD000000
This code example uses MPLAB C32 intrinsic functions to access CP0 registers.
Check your compiler documentation to find equivalent functions or use inline assembly
*/
unsigned int temp;
asm volatile(“di”); // Disable all interrupts
temp = _CP0_GET_STATUS(); // Get Status

temp |= 0x00400000; // Set BEV bit
_CP0_SET_STATUS(temp); // Update Status
_CP0_SET_EBASE(0xBD000000); // Set an EBase value of 0xBD000000

_CP0_SET_INTCTL(0x00000020); // Set the Vector Spacing to non-zero value
temp = _CP0_GET_CAUSE(); // Get Cause

temp |= 0x00800000; // Set IV
_CP0_SET_CAUSE(temp); // Update Cause
temp = _CP0_GET_STATUS(); // Get Status

temp &= 0xFFBFFFFD; // Clear BEV and EXL
_CP0_SET_STATUS(temp); // Update Status
INTCONCLR = 0x1000; // Clear MVEC bit
asm volatile(“ei”); // Enable all interrupts

PIC32MX3XX/4XX
8.4 Multi-Vector Mode To configure the CPU in Multi-Vector mode, the follow-
ing CPU registers (IntCtl, Cause, and Status) and the
When the MVEC (INTCON<12>) bit is ‘1’, the interrupt INTCON register must be configured as follows:
controller operates in Multi-Vector mode. In this mode,
the CPU vectors to the unique address for each vector • EBase ≠ 00000
number. Each vector is located at a specific offset, with • VS (IntCtl<9:5>) ≠ 00000
respect to a base address specified by the EBase reg- • IV (Cause<23>) = 1
ister in the CPU. The individual vector address offset is • EXL (Status<1>) = 0
determined by the vector space that is specified by the • BEV (Status<22>) = 0
VS bits in the IntCtl register. (The IntCtl register is
• MVEC (INTCON<12>) = 1
located in the CPU; refer to Section 2.0 "PIC32MX
MCU" of this manual for more information.) • IE (Status<0>) = 1
EXAMPLE 8-2: MULTI-VECTOR MODE INITIALIZATION
/*
Set the CP0 registers for multi-vector interrupt
Place EBASE at 0xBD000000 and Vector Spacing to 32 bytes
This code example uses MPLAB C32 intrinsic functions to access CP0 registers.
Check your compiler documentation to find equivalent functions or use inline assembly
*/
unsigned int temp;
asm volatile(“di”); // Disable all interrupts
temp = _CP0_GET_STATUS(); // Get the CPO Status register

temp |= _CPO_STATUS_BEV_MASK; // Set the BEV bit
_CP0_SET_STATUS(temp); // Update the Status register
_CP0_SET_EBASE(0xBD000000); // Set an EBASE Value (Kseg0 or Kseg1)

_CP0_SET_INTCTL(0x20); // Set the Vector Spacing
temp = _CP0_GET_CAUSE(); // Get the CPO Cause register

temp |= _CPO_CAUSE_IV_MASK; // Set the IV bit
_CP0_SET_CAUSE(temp); // Update the Cause register
temp = _CP0_GET_STATUS(); // Get the CPO Status register

temp &= ~(_CPO_STATUS_EXL_MASK| // Clear EXL and BEV bits
_CPO_STATUS_BEV_MASK;
_CP0_SET_STATUS(temp); // Update the Status register
INTCONSET = _INTCON_MVEC_MASK; // Set the interrupt controller to multi-vectored mode
asm volatile(“ei”); // Enable all interrupts
asm volatile(“ie”); // Enable all interrupts

PIC32MX3XX/4XX
8.5 Interrupt Priorities Cause register, RIPLx (Cause<15:10>), into the Status
register’s Interrupt Priority bits, IPLx (Status<15:10>),
8.5.1 INTERRUPT GROUP PRIORITY before re-enabling interrupts. (The Cause and Status
registers are located in the CPU; refer to Section 2.0
The user is able to assign a group priority to each of the
"PIC32MX MCU" of this manual for more information.)
interrupt vectors. The groups’ priority level bits are
This action will disable all lower priority interrupts until
located in the IPCx register. Each IPCx register con-
the completion of the Interrupt Service Routine.
tains group priority bits for four interrupt vectors. The
user-selectable priority levels range from 1 (the lowest
priority) to 7 (the highest). If an interrupt priority is set to Note: The Interrupt Service Routine (ISR) must
zero, the interrupt vector is disabled for both interrupt clear the associated interrupt flag in the
and wake-up purposes. Interrupt vectors with a higher IFSx register before lowering the interrupt
priority level preempt lower priority interrupts. The user priority level to avoid recursive interrupts.
must move the Requested Interrupt Priority bit of the
EXAMPLE 8-3: SETTING GROUP PRIORITY LEVEL

/*
The following code example will set the priority to level 2. Multi-Vector initialization
must be performed (See Example 8-2)
*/
IPC0CLR = 0x0000001C; // clear the priority level
IPC0SET = 0x00000008; // set priority level to 2
8.5.2 INTERRUPT SUBPRIORITY IPCx register contains subpriority bits for four of the
interrupt vectors. These bits define the subpriority
The user can assign a subpriority level within each
within the priority level of the vector. The user-
group priority. The subpriority will not cause preemption
selectable subpriority levels range from 0 (the lowest
of an interrupt in the same priority; rather, if two inter-
subpriority) to 3 (the highest).
rupts with the same priority are pending, the interrupt
with the highest subpriority will be handled first. The
subpriority bits are located in the IPCx register. Each
EXAMPLE 8-4: SETTING SUBPRIORITY LEVEL

/*
The following code example will set the subpriority to level 2. Multi-Vector initialization
must be performed (See Example 8-2)
*/
IPC0CLR = 0x00000003; // clear the subpriority level

IPC0SET = 0x00000002; // set the subpriority to 2

PIC32MX3XX/4XX
8.6 Interrupt Processing EXAMPLE 8-5: SINGLE VECTOR
INTERRUPT HANDLER
When the priority of a requested interrupt is greater
PROLOGUE IN ASSEMBLY
than the current CPU priority, the interrupt request is
taken and the CPU branches to the vector address CODE
associated with the requested interrupt. Depending on rdpgpr sp, sp
the priority of the interrupt, the prologue and epilogue mfc0 k0, Cause
mfc0 k1, EPC
of the interrupt handler must perform certain tasks
srl k0, k0, 0xa
before executing any useful code. The following
addiu sp, sp, -76
examples provide recommended prologues and sw k1, 0(sp)
epilogues. mfc0 k1, Status
sw k1, 4(sp)
8.6.1 INTERRUPT PROCESSING IN ins k1, k0, 10, 6
SINGLE VECTOR MODE ins k1,zero, 1, 4
mtc0 k1, Status
When the interrupt controller is configured in Single
sw s8, 8(sp)
Vector mode, all of the interrupt requests are serviced sw a0, 12(sp)
at the same vector address. The interrupt handler sw a1, 16(sp)
routine must generate a prologue and an epilogue to sw a2, 20(sp)
properly configure, save and restore all of the core reg- sw a3, 24(sp)
isters, along with General Purpose Registers. At a sw v0, 28(sp)
worst case, all of the modifiable General Purpose Reg- sw v1, 32(sp)
isters must be saved and restored by the prologue and sw t0, 36(sp)
epilogue. sw t1, 40(sp)
sw t2, 44(sp)
8.6.1.1 Single Vector Mode Prologue sw t3, 48(sp)
sw t4, 52(sp)
When entering the interrupt handler routine, the inter- sw t5, 56(sp)
rupt controller must first save the current priority and sw t6, 60(sp)
exception PC counter from Interrupt Priority bits, IPLx sw t7, 64(sp)
(Status<15:10>), and the ErrorEPC register, respec- sw t8, 68(sp)
tively, on the stack. (Status and ErrorEPC are CPU reg- sw t9, 72(sp)
addu s8, sp, zero
isters.) If the routine is presented a new register set, the
previous register set’s stack register must be copied to
// start interrupt handler code here
the current set’s stack register. Then, the requested pri-
ority may be stored in the IPLx from the Requested
Interrupt Priority bits, RIPLx (Cause<15:10>), Excep-
tion Level bit, EXL, and Error Level bit, ERL, in the Sta-
tus register (Status<1> and Status<2>) are cleared and
the Master Interrupt Enable bit (Status<0>) is set.
Finally, the General Purpose Registers will be saved on
the stack. (The Cause and Status registers are located
in the CPU.)

PIC32MX3XX/4XX
8.6.1.2 Single Vector Mode Epilogue 8.6.2.1 Multi-Vector Mode Prologue
After completing all useful code of the interrupt handler When entering the interrupt handler routine, the Inter-
routine, the original state of the Status and EPC regis- rupt Service Routine (ISR) must first save the current
ters, along with the General Purpose Registers saved priority and exception PC counter from Interrupt Priority
on the stack, must be restored. bits, IPL (Status<15:10>), and the ErrorEPC register,
respectively, on the stack. If the routine is presented a
EXAMPLE 8-6: SINGLE VECTOR new register set, the previous register set’s stack regis-
INTERRUPT HANDLER ter must be copied to the current set’s stack register.
EPILOGUE IN ASSEMBLY Then, the requested priority may be stored in the IPLx
from Requested Interrupt Priority bits, RIPLx
CODE
(Cause<15:10>), Exception Level bit, EXL, and Error
// end of interrupt handler code Level bit, ERL, in the Status register (Status<1> and
Status<2>) are cleared, and the Master Interrupt
addu sp, s8, zero
Enable bit (Status<0>) is set. If the interrupt handler is
lw t9, 72(sp)
not presented a new General Purpose Register set,
lw t8, 68(sp)
lw t7, 64(sp) these resisters will be saved on the stack. (Cause and
lw t6, 60(sp) Status are CPU registers; refer to Section 2.0
lw t5, 56(sp) "PIC32MX MCU" of this manual for more information.)
lw t4, 52(sp)
lw t3, 48(sp) EXAMPLE 8-7: PROLOGUE WITHOUT A
lw t2, 44(sp) DEDICATED GENERAL
lw t1, 40(sp)
lw t0, 36(sp)
PURPOSE REGISTER SET
lw v1, 32(sp) IN ASSEMBLY CODE
lw v0, 28(sp)
rdpgpr sp, sp
lw a3, 24(sp)
mfc0 k0, Cause
lw a2, 20(sp)
mfc0 k1, EPC
lw a1, 16(sp)
srl k0, k0, 0xa
lw a0, 12(sp)
addiu sp, sp, -76
lw s8, 8(sp)
sw k1, 0(sp)
di
mfc0 k1, Status
lw k0, 0(sp)
sw k1, 4(sp)
mtc0 k0, EPC
ins k1, k0, 10, 6
lw k0, 4(sp)
ins k1,zero, 1, 4
mtc0 k0, Status
mtc0 k1, Status
eret
sw s8, 8(sp)
sw a0, 12(sp)
8.6.2 INTERRUPT PROCESSING IN sw a1, 16(sp)
sw a2, 20(sp)
MULTI-VECTOR MODE
sw a3, 24(sp)
When the interrupt controller is configured in Multi- sw v0, 28(sp)
Vector mode, the interrupt requests are serviced at the sw v1, 32(sp)
calculated vector addresses. The interrupt handler sw t0, 36(sp)
routine must generate a prologue and an epilogue to sw t1, 40(sp)
sw t2, 44(sp)
properly configure, save and restore all of the core reg-
sw t3, 48(sp)
isters, along with General Purpose Registers. At a
sw t4, 52(sp)
worst case, all of the modifiable General Purpose Reg- sw t5, 56(sp)
isters must be saved and restored by the prologue and sw t6, 60(sp)
epilogue. If the interrupt priority is set to receive its own sw t7, 64(sp)
General Purpose Register set, the prologue and epi- sw t8, 68(sp)
logue will not need to save or restore any of the modi- sw t9, 72(sp)
fiable General Purpose Registers, thus providing the addu s8, sp, zero
lowest latency.

PIC32MX3XX/4XX
EXAMPLE 8-8: PROLOGUE WITH A EXAMPLE 8-10: EPILOGUE WITH A
DEDICATED GENERAL DEDICATED GENERAL
PURPOSE REGISTER SET PURPOSE REGISTER SET
IN ASSEMBLY CODE IN ASSEMBLY CODE
rdpgpr sp, sp // end of interrupt handler code
mfc0 k0, Cause
mfc0 k1, EPC addu sp, s8, zero
srl k0, k0, 0xa di
addiu sp, sp, -76 lw k0, 0(sp)
sw k1, 0(sp) mtc0 k0, EPC
mfc0 k1, Status lw k0, 4(sp)
sw k1, 4(sp) mtc0 k0, Status
ins k1, k0, 10, 6 eret
ins k1,zero, 1, 4
mtc0 k1, Status
addu s8, sp, zero
8.6.2.2 Multi-Vector Mode Epilogue

After completing all useful code of the interrupt handler
routine, the original state of the Status and ErrorEPC
registers, along with the General Purpose Registers
saved on the stack, must be restored. (The Status and
ErrorEPC registers are located in the CPU; refer to
Section 2.0 "PIC32MX MCU" of this manual for more
information.)
EXAMPLE 8-9: EPILOGUE WITHOUT A

DEDICATED GENERAL
PURPOSE REGISTER SET
IN ASSEMBLY CODE
// end of interrupt handler code
addu sp, s8, zero

lw t9, 72(sp)
lw t8, 68(sp)
lw t7, 64(sp)
lw t6, 60(sp)
lw t5, 56(sp)
lw t4, 52(sp)
lw t3, 48(sp)
lw t2, 44(sp)
lw t1, 40(sp)
lw t0, 36(sp)
lw v1, 32(sp)
lw v0, 28(sp)
lw a3, 24(sp)
lw a2, 20(sp)
lw a1, 16(sp)
lw a0, 12(sp)
lw s8, 8(sp)
di
lw k0, 0(sp)
mtc0 k0, EPC
lw k0, 4(sp)
mtc0 k0, Status
eret

PIC32MX3XX/4XX
8.7 External Interrupts
The interrupt controller supports five external interrupt-
request signals (INT4-INT0). These inputs are edge
sensitive; they require a low-to-high or a high-to-low
transition to create an interrupt request. The INTCON
register has five bits that select the polarity of the edge
detection circuitry: INT4EP (INTCON<4>), INT3EP
(INTCON<3>), INT2EP (INTCON<2>), INT1EP (INT-
CON<1>) and INT0EP (INTCON<0>).
Note: Changing the external interrupt polarity

may trigger an interrupt request. It is rec-
ommended that before changing the
polarity, the user disables that interrupt,
changes the polarity, clears the interrupt
flag and re-enables the interrupt.
EXAMPLE 8-11: SETTING EXTERNAL INTERRUPT POLARITY

/*
The following code example will set INT3 to trigger on a high to low transition edge. The CPU
must be set up for either multi or single vector interrupts to handle external interrupts
*/
IEC0CLR = 0x00008000; // disable INT3
INTCONCLR = 0x00000008; // clear the bit for falling edge trigger
IFS0CLR = 0x00008000; // clear the interrupt flag
IEC0SET = 0x00008000; // enable INT3
8.8 Temporal Proximity Interrupt Interrupt proximity interrupt uses the interrupt proximity
Coalescing timer, IPTMR, to create a temporal window in which a
group of interrupts of the same, or lower, priority will be
The PIC32MX3XX/4XX CPU responds to interrupt held off. The user can activate temporal proximity inter-
events as if they are all immediately critical because rupt coalescing by performing the following steps:
the interrupt controller asserts the interrupt request to
• Set the TPC<2:0> INTCON<10:8> bit to the pre-
the CPU when the interrupt request occurs. The CPU
ferred priority level. (Setting TPC to zero will dis-
immediately recognizes the interrupt if the current CPU
able the proximity timer.)
priority is lower than the pending priority. Entering and
exiting an ISR consumes clock cycles for saving and • Load the preferred 32-bit value to IPTMR.
restoring context. Events are asynchronous with The interrupt proximity timer will trigger when an inter-
respect to the main program and have a limited rupt request of a priority equal, or lower, matches the
possibility of occurring simultaneously or close together TPC value.
in time. This prevents the ability of a shared ISR to
process multiple interrupts at one time.
EXAMPLE 8-12: INTERRUPT PROXIMITY INTERRUPT COALESCING EXAMPLE

/*
The following code example will set the Interrupt Proximity Coalescing to trigger on interrupt
priority level of 3 or below and the interrupt timer to be set to 0x12345678.
*/
INTCONCLR = 0x00000700; // clear TPC

IPTMPCLR = 0xFFFFFFFF; // clear the timer
INTCONSET = 0x00000300; // set TPC->3
IPTMR = 0x12345678; // set the timer to 0x12345678

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
9.0 PREFETCH CACHE 9.1 Features
Note: This data sheet summarizes the features of • 16 Fully Associative Lockable Cache Lines
the PIC32MX3XX/4XX family of devices. It • 16-byte Cache Lines
is not intended to be a comprehensive refer- • Up to 4 Cache Lines allocated to Data
ence source. Refer to the “PIC32MX Family • 2 Cache Lines with Address Mask to hold
Reference Manual” (DS61132) for a repeated instructions
• Pseudo LRU replacement policy
The Prefetch cache increases performance for appli- • All Cache Lines are software writable
cations executing out of the cacheable program flash • 16-byte parallel memory fetch
memory region by implementing instruction caching, • Predictive Instruction Prefetch
data caching and instruction prefetching.
FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM
FSM CTRL
Tag Logic Cache Line

BMX/CPU
CTRL
Bus Ctrl
BMX/CPU
Cache Ctrl
Prefetch Ctrl
Cache
Line RDATA
Hit LRU
Address
Encode
Miss LRU
Hit Logic
PreFetch PreFetch
Pre-Fetch Pre-Fetch
Tag
RDATA
CTRL
PFM

PIC32MX3XX/4XX
TABLE 9-1: PREFETCH SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_4000 CHECON 31:24 — — — — — — — —
23:16 — — — — — — — CHECOH
15:8 — — — — — — DCSZ<1:0>
7:0 — — PREFEN<1:0> — PFMWS<2:0>
BF88_4004 CHECONCLR 31:0 Clears selected bits in CHECON, read yields undefined value
BF88_4008 CHECONSET 31:0 Sets selected bits in CHECON, read yields undefined value
BF88_400C CHECONINV 31:0 Inverts selected bits in CHECON, read yields undefined value
BF88_4010 CHEACC 31:24 CHEWEN — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 — — — — CHEIDX<3:0>
BF88_4014 CHEACCCLR 31:0 Clears selected bits in CHEACC, read yields undefined value
BF88_4018 CHEACCSET 31:0 Sets selected bits in CHEACC, read yields undefined value
BF88_401C CHEACCINV 31:0 Inverts selected bits CHEACC, read yields undefined value
BF88_4020 CHETAG 31:24 LTAGBOOT — — — — — — —
23:16 LTAG<23:16>
15:8 LTAG<15:8>
7:0 LTAG<7:4> LVALID LLOCK LTYPE —
BF88_4024 CHETAGCLR 31:0 Clears selected bits in CHETAG, read yields undefined value
BF88_4028 CHETAGSET 31:0 Sets selected bits in CHETAG, read yields undefined value
BF88_402C CHETAGINV 31:0 Inverts selected bits CHETAG, read yields undefined value
BF88_4030 CHEMSK 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 LMASK<15:8>
7:0 LMASK<7:5> — — — — —
BF88_4034 CHEMSKCLR 31:0 Clears selected bits in CHEMSK, read yields undefined value
BF88_4038 CHEMSKSET 31:0 Sets selected bits in CHEMSK, read yields undefined value
BF88_403C CHEMSKINV 31:0 Inverts selected bits CHEMSK, read yields undefined value
BF88_4040 CHEW0 31:24 CHEW0<31:24>
23:16 CHEW0<23:16>
15:8 CHEW0<15:8>
7:0 CHEW0<7:0>
BF88_4050 CHEW1 31:24 CHEW1<31:24>
23:16 CHEW1<23:16>
15:8 CHEW1<15:8>
7:0 CHEW1<7:0>
BF88_4060 CHEW2 31:24 CHEW2<31:24>
23:16 CHEW2<23:16>
15:8 CHEW2<15:8>
7:0 CHEW2<7:0>
BF88_4070 CHEW3 31:24 CHEW3<31:24>
23:16 CHEW3<23:16>
15:8 CHEW3<15:8>
7:0 CHEW3<7:0>
BF88_4080 CHELRU 31:24 — — — — — — — CHELRU<24>
23:16 CHELRU<23:16>
15:8 CHELRU<15:8>
7:0 CHELRU<7:0>>
BF88_4090 CHEHIT 31:24 CHEHIT<31:24>
23:16 CHEHIT<23:16>
15:8 CHEHIT<15:8>
7:0 CHENIT<7:0>
BF88_40A0 CHEMIS 31:24 CHEMIS<31:24>
23:16 CHEMIS<23:16>
15:8 CHEMIS<15:8>
7:0 CHEMIS<7:0>

PIC32MX3XX/4XX
TABLE 9-1: PREFETCH SFR SUMMARY (CONTINUED)
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_40C0 CHEPFABT 31:24 CHEPFABT<31:24>
23:16 CHEPFABT<23:16>
15:8 CHEPFABT<15:8>
7:0 CHEPFABT<7:0>

PIC32MX3XX/4XX
9.2 Prefetch Registers
REGISTER 9-1: CHECON: CACHE CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — CHECOH
bit 23 bit 16
r-x r-x r-0 r-0 r-x r-x R/W-0 R/W-0

— — — — — — DCSZ<1:0>
bit 15 bit 8
r-x r-x R/W-0 R/W-0 r-x R/W-1 R/W-1 R/W-1

— — PREFEN<1:0> — PFMWS<2:0>
bit 7 bit 0
Legend:

bit 16 CHECOH: Cache Coherency setting on a PFM Program Cycle bit
1 = Invalidate all data and instruction lines
0 = Invalidate all data lines and instruction lines that are not locked
bit 13-12 Reserved: Must be written with zeros
bit 9-8 DCSZ<1:0>: Data Cache Size in Lines bits
11 = Enable data caching with a size of 4 Lines
10 = Enable data caching with a size of 2 Lines
01 = Enable data caching with a size of 1 Line
00 = Disable data caching
Changing this field causes all lines to be re-initialized to the “invalid” state.
bit 5-4 PREFEN<1:0>: Predictive Prefetch Cache Enable bits
11 = Enable predictive prefetch cache for both cacheable and non-cacheable regions
10 = Enable predictive prefetch cache for non-cacheable regions only
01 = Enable predictive prefetch cache for cacheable regions only
00 = Disable predictive prefetch cache

PIC32MX3XX/4XX
REGISTER 9-1: CHECON: CACHE CONTROL REGISTER (CONTINUED)
bit 2-0 PFMWS<2:0>: PFM Access Time Defined in terms of SYSLK Wait states bits
111 = Seven Wait states
110 = Six Wait states
101 = Five Wait state
100 = Four Wait states
011 = Three Wait states
010 = Two Wait states
001 = One Wait state
000 = Zero Wait states

PIC32MX3XX/4XX
REGISTER 9-2: CHEACC: CACHE ACCESS
R/W-0 r-x r-x r-x r-x r-x r-x r-x
CHEWEN — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

— — — — CHEIDX<3:0>
bit 7 bit 0
Legend:
bit 31 CHEWEN: Cache Access Enable bits for registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2,
and CHEW3
1 = The cache line selected by CHEIDX is writable
0 = The cache line selected by CHEIDX is not writable
bit 3-0 CHEIDX<3:0>: Cache Line Index bits
The value selects the cache line for reading or writing.

PIC32MX3XX/4XX
REGISTER 9-3: CHETAG(1): CACHE TAG REGISTER
LTAGBOOT — — — — — — —
bit 31 bit 24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

LTAG<23:16>
bit 23 bit 16

LTAG<15:8>
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1 r-0

LTAG<7:4> LVALID LLOCK LTYPE —
bit 7 bit 0
Legend:
bit 31 LTAGBOOT: Line TAG Address Boot

1 = The line is in the 0x1D000000 (physical) area of memory
0 = The line is in the 0x1FC00000 (physical) area of memory
bit 23-4 LTAG<23:4>: Line TAG Address bits
LTAG bits are compared against physical address <23:4> to determine a hit. Because its address
range and position of Flash in kernel space and user space, the LTAG Flash address is identical for
virtual addresses, (system) physical addresses, and Flash physical addresses.
bit 3 LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection
0 = The line is not valid and is not compared to the physical address for hit detection
bit 2 LLOCK: Line Lock bit
1 = The line is locked and will not be replaced
0 = The line is not locked and can be replaced
bit 1 LTYPE: Line Type bit
1 = The line caches instruction words
0 = The line caches data words
bit 0 Reserved:
Note 1: The TAG and Status of the Line pointed to by CHEIDX (CHEACC<3:0>).

PIC32MX3XX/4XX
REGISTER 9-4: CHEMSK(1): CACHE TAG MASK REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

LMASK<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x

LMASK<7:5> — — — — —
bit 7 bit 0
Legend:

bit 15-5 LMASK<15:5>: Line Mask bits
1 = Enables mask logic to force a match on the corresponding bit position in LTAG (CHETAG<23:4>)
and the physical address.
0 = Only writable for values of CHEIDX (CHEACC<3:0>) equal to OxOA and OxOB.
Disables mask logic.
Note 1: The TAG Mask of the Line pointed to by CHEIDX (CHEACC<3:07>).

PIC32MX3XX/4XX
REGISTER 9-5: CHEW0: CACHE WORD 0
CHEW0<31:24>
bit 31 bit 24

CHEW0<23:16>
bit 23 bit 16

CHEW0<15:8>
bit 15 bit 8

CHEW0<7:0>
bit 7 bit 0
Legend:
bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by CHEACC.CHEIDX

Readable only if the device is not code-protected.

PIC32MX3XX/4XX
REGISTER 9-6: CHEW1: CACHE WORD 1
CHEW1<31:24>
bit 31 bit 24

CHEW1<23:16>
bit 23 bit 16

CHEW1<15:8>
bit 15 bit 8

CHEW1<7:0>
bit 7 bit 0
Legend:


PIC32MX3XX/4XX
REGISTER 9-7: CHEW2 CACHE WORD 2
CHEW2<31:24>
bit 31 bit 24

CHEW2<23:16>
bit 23 bit 16

CHEW2<15:8>
bit 15 bit 8

CHEW2<7:0>
bit 7 bit 0
Legend:


PIC32MX3XX/4XX
REGISTER 9-8: CHEW3(1): CACHE WORD 3
CHEW3<31:24>
bit 31 bit 24

CHEW3<23:16>
bit 23 bit 16

CHEW3<15:8>
bit 15 bit 8

CHEW3<7:0>
bit 7 bit 0
Legend:

Note 1: This register is a window into the cache data array and is readable only if the device is not code-protected.

PIC32MX3XX/4XX
REGISTER 9-9: CHELRU: CACHE LRU REGISTER
r-x r-x r-x r-x r-x r-x r-x R-0
— — — — — — — CHELRU<24>
bit 31 bit 24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHELRU<23-16>
bit 23 bit 16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHELRU<15-8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHELRU<7-0>
bit 7 bit 0
Legend:

bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits
CHELRU indicates the Pseudo-LRU state of the cache.

PIC32MX3XX/4XX
REGISTER 9-10: CHEHIT: CACHE HIT STATISTICS REGISTER
CHEHIT<31:24>
bit 31 bit 24

CHEHIT<23:16>
bit 23 bit 16

CHEHIT<15:8>
bit 15 bit 8

CHEHIT<7:0>
bit 7 bit 0
Legend:
bit 31-0 CHEHIT<31:0>: Cache Hit Count bits

Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache
from a cacheable region. Non-cacheable accesses do not modify this value.

PIC32MX3XX/4XX
REGISTER 9-11: CHEMIS: CACHE MISS STATISTICS REGISTER
CHEMIS<31:24>
bit 31 bit 24

CHEMIS<23:16>
bit 23 bit 16

CHEMIS<15:8>
bit 15 bit 8

CHEMIS<7:0>
bit 7 bit 0
Legend:
bit 31-0 CHEMIS<31:0>: Cache Miss Count bits

Incremented each time the processor issues an instruction fetch from a cacheable region that misses
the prefetch cache. Non-cacheable accesses do not modify this value.

PIC32MX3XX/4XX
REGISTER 9-12: CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER
CHEPFABT<31:24>
bit 31 bit 24

CHEPFABT<23:16>
bit 23 bit 16

CHEPFABT<15:8>
bit 15 bit 8

CHEPFABT<7:0>
bit 7 bit 0
Legend:
bit 31-0 CHEPFABT<31:0>: Prefab Abort Count bits

Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction
fetch, load or store.

PIC32MX3XX/4XX
9.3 Prefetch Configuration
The CHECON register controls the configurations TABLE 9-2: PROGRAM DATA CACHE
available for instruction and data caching of Program
DCSZ<1:0> Lines Allocated to Program Data
Flash Memory.
In addition to normal instruction caching, the prefetch 00 None
cache has the ability to cache lines specifically for 01 Cache Line Number 15
Flash Memory data.
10 Cache Line Number 14 and 15
The CHECON.DCSZ field controls the number of lines
11 Cache Line Number 12 through 15
allocated to program data caching. Table 9-2 shows
the cache line relationship for values of DCSZ. The
data caching capability is for read only data such as The CHECON.PREFEN field controls predictive
constants, parameters, table data, etc., that are not prefetching, which allows the prefetch module to spec-
modified. ulatively fetch the next 16-byte aligned set of instruc-
tions.
The prefetch module loads data into the data array only
on accesses to cacheable regions (CCA bits = 3).
EXAMPLE 9-1: EXAMPLE CODE: INITIALIZATION CODE FOR PREFETCH MODULE

/* Prefetch Cache Initialization */
tmp = _CP0_GET_CONFIG(); // read CONFIG register

tmp |= 1; // kseg0 cacheable
_CP0_SET_CONFIG(tmp); // write CONFIG register
CHECON = (1<<4) | 3; // 3 wait-states,

// Prefetching enabled for cached memory
9.3.1 LINE LOCKING If cache lines are manually filled, it is recommended

that the following sequence be used:
Each line in the cache can be locked to hold its con-
tents. A line is locked if both LVALID = 1 and 1. Choose a cache line to fill.
LLOCK = 1. If LVALID = 0 and LLOCK = 1, the 2. Set the Lock and Valid bits of the cache line by
prefetch module issues a preload request (see below). writing to CHETAG.
Locking cache lines may reduce the performance of 3. Write to each word of the cache line by writing to
general program flow. However, if one or two functions CHEW0, CHEW1, CHEW2, and CHEW3.
calls consume a significant percent of overall process-
ing, locking their address can provide improved perfor-
mance.
Though any number of lines can be locked, the cache
works most efficiently when locking either 1 or 4 lines.
If locking 4 lines, choose lines whose line number
divide by 4 have the same quotient. This locks an
entire LRU group which benefits the LRU algorithm.
For example, lines 8, 9, A, and B each have a quotient
of 2 when divided by 4.
EXAMPLE 9-2: EXAMPLE CODE: LOCKING A LINE IN PREFETCH MODULE

#define LOCKED_LINE_NUM 3
/* lock first line of func1() in cache */
CHEACC = (1<<31) | LOCKED_LINE_NUM;

tmp = (unsigned long)func1;
ltagboot = (tmp & 0x00c00000) ? 0 : 1;
CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid

PIC32MX3XX/4XX
9.3.2 PRELOAD BEHAVIOR 9.3.3 ADDRESS MASK
Application code can direct the prefetch module to pre- Cache lines 10 and 11 allow masking of the CPU
form a preload of a cache line and lock it with instruc- address and tag address to force a match on corre-
tions or data from the flash. The Preload function uses sponding bits. The CHEMSK.LMASK field is set up to
the CHEACC.CHEIDX register field to select the compliment the interrupt vector spacing field in the
cache line into which the load is directed. Setting CPU. This feature allows boot code to lock the first
CHEACC.CHEWEN to a ‘1’ enables writes to the four instruction of a vector in the cache. If all vectors
CHETAG register. contain identical instructions in their first four locations,
Writing CHETAG.LVALID = 0 and then setting the CHEMSK.LMASK to match the vector
CHETAG.LLOCK = 1 causes a preload request to the spacing and the LTAG to match the vector base
prefetch module. The controller acknowledges the address causes all the vector addresses to hit the
request in the cycle after the write and if possible stops cache. The prefetch module responds with zero Wait
any outstanding flash access and stalls any CPU load states and immediately initiates a fetch of the next set
from the cache or Flash. of four instruction for the requesting vector if prefetch
is enabled.
When it has finished or stalled the previous transac-
tion, it initiates a flash read to fetch the instructions or Using CHEMSK.LMASK is restricted to aligned
data requested using the address in CHETAG.LTAG. address ranges. Its size allows for a max range of
After the programmed number of Wait states as 32KB and a minimum spacing of 32B. Using the two
defined by CHECON.PFMWS, the controller updates lines, in conjunction provides the ability to have differ-
the data array with the values read from flash. On the ent ranges and different spacing.
update it sets CHETAG.LVALID = 1. The LRU state of Setting up the address mask such that more than one
the line is not affected. line will match an address causes undefined results.
Once the controller finishes updating the cache, it Therefore, it is highly recommended to set up masking
allows CPU requests to complete. If this request before entering cacheable code.
misses the cache, the controller initiates a flash read
which incurs the full flash access time.
EXAMPLE 9-3: EXAMPLE CODE: DUPLICATION OF CODE USING MASK REGISTERS

#define INT_LINE_NUM 10
CHEACC = (1<<31) | INT_LINE_NUM;

tmp = (unsigned long)intbase;
ltagboot = (tmp & 0x00c00000) ? 0 : 1;
CHETAG = (ltagboot<<31) | (tmp & 0x0007fff0) | 6; // locked and invalid
CHEMSK = 0xe0; // first 4 instructions of intbase() replicated 8 times on 32-byte boundaries

PIC32MX3XX/4XX
9.3.4 PREDICTIVE PREFETCH 9.3.5 COHERENCY SUPPORT
BEHAVIOR It is not possible to execute out of cache while pro-
When configured for predictive prefetch on cacheable gramming the flash memory. The flash controller stalls
addresses, the module predicts the next line address the cache during the programming sequence. There-
and returns it into the pseudo LRU line of the cache. If fore, user code that initiates a programming sequence
enabled, the prefetch function starts predicting based must not be located in a cacheable address region.
on the first CPU instruction fetch. When the first line is If CHECON.CHECOH = 1, then coherency is strictly
placed in the cache, the module simply increments the supported by invalidating, unlocking, and clearing
address to the next 16-byte aligned address and starts masks for all lines whenever the Flash Program
a flash access. When running linear code (i.e. no Memory is written or programmed.
jumps), the flash returns the next set of instructions
into the prefetch buffer on or before all instructions can If CHECON.CHECOH = 0, then only lines that are not
be executed from the previous line. locked are forced invalid. Lines that are locked are
retained.
If at any time during a predicted flash access, a new
CPU address does not match the predicted one, the
9.4 Prefetch Module Interrupts and
flash access will be changed to the correct address.
This behavior does not cause the CPU access to take Exceptions
any longer than without prediction. The prefetch module does not generate any interrupts.
If an access that misses the cache hits the prefetch Exceptions can occur if cache lines are marked as valid
buffer, the instructions are placed in the pseudo LRU manually by writing to individual CHETAG registers
line along with its address tag. The pseudo LRU value then executing code that hits one of these lines contain-
is marked as the most recently used line and other ing invalid instructions. Also manually placing data into
lines are updated accordingly. If an access misses an un-locked cache line may cause a coherency prob-
both the cache and the prefetch buffer, the access lem from an eviction due to a cache miss in the middle
passes to the flash and those returning instructions of the loading algorithm.
are placed in the pseudo LRU line.
When configured for predictive prefetch on non- 9.5 I/O Pin Configuration
cacheable addresses, the controller only uses the
prefetch buffer. The LRU cache line is not updated for The prefetch module does not use any external pins.
hits or fills so the cache remains intact. For linear
code, enabling predictive prefetch for non-cacheable
addresses allows the CPU to fetch instructions in zero
Wait states.
It is not useful to use non-cacheable predictive
prefetching when accesses to the flash are set for zero
Wait states. The controller holds prefetched instruc-
tions on the output of the flash for up to 3 clock cycles
(while the CPU is fetching from the buffer). This con-
sumes more power without any benefit for zero Wait
state flash accesses.
Predictive data prefetching is not supported. However,
a data access in the middle of a predictive instruction
fetch causes the prefetch controller to stop the flash
access for the instruction fetch and to start the data
load from flash. The predictive prefetch does not
resume, but instead waits for another instruction fetch.
At which time, it either fills the buffer because of a
miss, or starts a prefetch because of a hit.

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
10.0 DIRECT MEMORY ACCESS • Flexible DMA Requests:
(DMA) CONTROLLER - A DMA request can be selected from any of
the peripheral interrupt sources
Note: This data sheet summarizes the features of - Each channel can select any (appropriate)
the PIC32MX3XX/4XX family of devices. It observable interrupt as its DMA request
is not intended to be a comprehensive refer- source
ence source. Refer to the “PIC32MX Family - A DMA transfer abort can be selected from
Reference Manual” (DS61132) for a any of the peripheral interrupt sources
- Pattern (data) match transfer termination
The PIC32MX Direct Memory Access (DMA) controller • Multiple DMA Channel Status Interrupts:
is a bus master module useful for data transfers - DMA channel block transfer complete
between different devices without the CPU interven- - Source empty or half empty
tion. The source and destination of a DMA transfer can
- Destination full or half-full
be any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices: - DMA transfer aborted due to an external
SPI, UART, I2C™, etc.) or memory itself. event
- Invalid DMA address generated
Following are some of the key features of the DMA
controller module: • DMA Debug Support Features:
- Most recent address accessed by a DMA
• Four Identical Channels, each featuring:
channel
- Auto-Increment Source and Destination
- Most recent DMA channel to transfer data
Address Registers
• CRC Generation Module:
- Source and Destination Pointers
- CRC module can be assigned to any of the
• Automatic Word-Size Detection:
available channels
- Transfer Granularity, down to byte level
- CRC module is highly configurable
- Bytes need not be word-aligned at source
and destination
• Fixed Priority Channel Arbitration
• Flexible DMA Channel Operating Modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
TABLE 10-1: DMA CONTROLLER FEATURES

and Destination Sizes
Memory to Peripheral
Channel Auto-Enable
Unaligned Transfers
Memory to Memory
Channel Chaining
Events Start/Stop
CRC Calculation
Different Source
Transfer Length
Pattern Match
Detection
Transfers
Transfers
<= 256B Yes Yes Yes Yes Yes Yes Yes Yes Yes

PIC32MX3XX/4XX
FIGURE 10-1: DMA CONTROLLER BLOCK DIAGRAM
INT Controller System IRQ
SE
L
Peripheral Bus Address Decoder Channel 0 Control I0
Channel 1 Control I1 Y Bus Interface Device Bus + Bus Arbitration
I2
Global Control Channel n Control In

(DMACON) L
SE
Channel Priority
Arbitration
10.1 DMA Controller Registers
TABLE 10-2: DMA GLOBAL SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3000 DMACON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL SUSPEND — — — —
7:0 — — — — — — —
BF88_3004 DMACONCLR 31:0 Write clears selected bits in DMACON, read yields undefined value
BF88_3008 DMACONSET 31:0 Write sets selected bits in DMACON, read yields undefined value
BF88_300C DMACONINV 31:0 Write inverts selected bits in DMACON, read yields undefined value
BF88_3010 DMASTAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 — — — — RDWR — DMACH<1:0>
BF88_3020 DMAADDR 31:24 DMAADDR<31:24>
23:16 DMAADDR<23:16>
15:8 DMAADDR<15:8>
7:0 DMAADDR<7:0>

PIC32MX3XX/4XX
TABLE 10-3: DMA CRC SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3030 DCRCCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — PLEN<3:0>
7:0 CRCEN CRCAPP — — — — CRCCH<1:0>
BF88_3034 DCRCCONCLR 31:0 Write clears selected bits in DCRCCON, read yields undefined value
BF88_3038 DCRCCONSET 31:0 Write sets selected bits in DCRCCON, read yields undefined value
BF88_303C DCRCCONINV 31:0 Write inverts selected bits in DCRCCON, read yields undefined value
BF88_3040 DCRCDATA 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 DCRCDATA<15:8>
7:0 DCRCDATA<7:0>
BF88_3044 DCRCDATACLR 31:0 Write clears selected bits in DCRCDATA, read yields undefined value
BF88_3048 DCRCDATASET 31:0 Write sets selected bits in DCRCDATA, read yields undefined value
BF88_304C DCRCDATAINV 31:0 Write inverts selected bits in DCRCDATA, read yields undefined value
BF88_3050 DCRCXOR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 DCRCXOR<15:8>
7:0 DCRCXOR<7:0>
BF88_3054 DCRCXORCLR 31:0 Write clears selected bits in DCRCXOR, read yields undefined value
BF88_3058 DCRCXORSET 31:0 Write sets selected bits in DCRCXOR, read yields undefined value
BF88_305C DCRCXORINV 31:0 Write inverts selected bits in DCRCXOR, read yields undefined value
TABLE 10-4: DMA CHANNEL 0 SFR SUMMARY

Name
Address (1) 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3060 DCH0CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — CHCHNS
7:0 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>
BF88_3064 DCH0CONCLR 31:0 Write clears selected bits in DCH0CON, read yields undefined value
BF88_3068 DCH0CONSET 31:0 Write sets selected bits in DCH0CON, read yields undefined value
BF88_306C DCH0CONINV 31:0 Write inverts selected bits in DCH0CON, read yields undefined value
BF88_3070 DCH0ECON 31:24 — — — — — — — —
23:16 CHAIRQ<7:0>
15:8 CHSIRQ<7:0>
7:0 CFORCE CABORT PATEN SIRQEN AIRQEN — — —
BF88_3074 DCH0ECONCLR 31:0 Write clears selected bits in DCH0ECON, read yields undefined value
BF88_3078 DCH0ECONSET 31:0 Write sets selected bits in DCH0ECON, read yields undefined value
BF88_307C DCH0ECONINV 31:0 Write inverts selected bits in DCH0ECON, read yields undefined value
BF88_3080 DCH0INT 31:24 — — — — — — — —
23:16 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE
15:8 — — — — — — — —
7:0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF
BF88_3084 DCH0INTCLR 31:0 Write clears selected bits in DCH0INT, read yields undefined value
BF88_3088 DCH0INTSET 31:0 Write sets selected bits in DCH0INT, read yields undefined value
BF88_308C DCH0INTINV 31:0 Write inverts selected bits in DCH0INT, read yields undefined value
BF88_3090 DCH0SSA 31:24 CHSSA<31:24>
23:16 CHSSA<23:16>
15:8 CHSSA<15:8>
7:0 CHSSA<7:0>
BF88_3094 DCH0SSACLR 31:0 Write clears selected bits in DCH0SSA, read yields undefined value
BF88_3098 DCH0SSASET 31:0 Write sets selected bits in DCH0SSA, read yields undefined value
BF88_309C DCH0SSAINV 31:0 Write inverts selected bits in DCH0SSA, read yields undefined value
Note 1: The starting address of the registers for DMA channel n is 0xbf883060 + 0xc0*n.

PIC32MX3XX/4XX
TABLE 10-4: DMA CHANNEL 0 SFR SUMMARY (CONTINUED)
Name
Address (1) 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_30A0 DCH0DSA 31:24 CHDSA<31:24>
23:16 CHDSA<23:16>
15:8 CHDSA<15:8>
7:0 CHDSA<7:0>
BF88_30A4 DCH0DSACLR 31:0 Write clears selected bits in DCH0DSA, read yields undefined value
BF88_30A8 DCH0DSASET 31:0 Write sets selected bits in DCH0DSA, read yields undefined value
BF88_30AC DCH0DSAINV 31:0 Write inverts selected bits in DCH0DSA, read yields undefined value
BF88_30B0 DCH0SSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSSIZ<7:0>
BF88_30B4 DCH0SSIZCLR 31:0 Write clears selected bits in DCH0SSIZ, read yields undefined value
BF88_30B8 DCH0SSIZSET 31:0 Write sets selected bits in DCH0SSIZ, read yields undefined value
BF88_30BC DCH0SSIZINV 31:0 Write inverts selected bits in DCH0SSIZ, read yields undefined value
BF88_30C0 DCH0DSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDSIZ<7:0>
BF88_30C4 DCH0DSIZCLR 31:0 Write clears selected bits in DCH0DSIZ, read yields undefined value
BF88_30C8 DCH0DSIZSET 31:0 Write sets selected bits in DCH0DSIZ, read yields undefined value
BF88_30CC DCH0DSIZINV 31:0 Write inverts selected bits in DCH0DSIZ, read yields undefined value
BF88_30D0 DCH0SPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSTR<7:0>
BF88_30E0 DCH0DPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDPTR<7:0>
BF88_30F0 DCH0CSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCSIZ<7:0>
BF88_30F4 DCH0CSIZCLR 31:0 Write clears selected bits in DCH0CSIZ, read yields undefined value
BF88_30F8 DCH0CSIZSET 31:0 Write sets selected bits in DCH0CSIZ, read yields undefined value
BF88_30FC DCH0CSIZINV 31:0 Write inverts selected bits in DCH0CSIZ, read yields undefined value
BF88_3100 DCH0CPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCPTR<7:0>
BF88_3110 DCH0DAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHPDAT<7:0>
BF88_3114 DCH0DATCLR 31:0 Write clears selected bits in DCH0DAT, read yields undefined value
BF88_3118 DCH0DATSET 31:0 Write sets selected bits in DCH0DAT, read yields undefined value
BF88_311C DCH0DATINV 31:0 Write inverts selected bits in DCH0DAT, read yields undefined value

PIC32MX3XX/4XX
TABLE 10-5: DMA CHANNEL 0 INTERRUPT REGISTER SUMMARY(1)
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1070 IEC1 23:16 — — — — DMA3IE DMA2IE DMA1IE DMA0IE
BF88_1040 IFS1 23:16 — — — — DMA3IF DMA2IF DMA1IF DMA0IF
Note 1: This summary table contains partial register definitions that only pertain to the DMA peripheral. Refer to the PIC32MX Family Reference
Manual (DS61132) for a detailed description of these registers.

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3120 DCH1CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — CHCHNS
BF88_3124 DCH1CONCLR 31:0 Write clears selected bits in DCH1CON, read yields undefined value
BF88_3128 DCH1CONSET 31:0 Write sets selected bits in DCH1CON, read yields undefined value
BF88_312C DCH1CONINV 31:0 Write inverts selected bits in DCH1CON, read yields undefined value
BF88_3130 DCH1ECON 31:24 — — — — — — — —
23:16 CHAIRQ<7:0>
15:8 CHSIRQ<7:0>
7:0 CFORCE CABORT PATEN SIRQEN AIRQEN - — —
BF88_3134 DCH1ECONCLR 31:0 Write clears selected bits in DCH1ECON, read yields undefined value
BF88_3138 DCH1ECONSET 31:0 Write sets selected bits in DCH1ECON, read yields undefined value
BF88_313C DCH1ECONINV 31:0 Write inverts selected bits in DCH1ECON, read yields undefined value
BF88_3140 DCH1INT 31:24 — — — — — — — —
15:8 — — — — — — — —
BF88_3150 DCH1SSA 31:24 CHSSA<31:24>
23:16 CHSSA<23:16>
15:8 CHSSA<15:8>
7:0 CHSSA<7:0>
BF88_3160 DCH1DSA 31:24 CHDSA<31:24>
23:16 CHDSA<23:16>
15:8 CHDSA<15:8>
7:0 CHDSA<7:0>
BF88_3164 DCH1DSACLR 31:0 Write clears selected bits in DCH1DSA, read yields undefined value
BF88_3168 DCH1DSASET 31:0 Write sets selected bits in DCH1DSA, read yields undefined value
BF88_316C DCH1DSAINV 31:0 Write inverts selected bits in DCH1DSA, read yields undefined value
BF88_3170 DCH1SSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSSIZ<7:0>
BF88_3174 DCH1SSIZCLR 31:0 Write clears selected bits in DCH1SSIZ, read yields undefined value
BF88_3178 DCH1SSIZSET 31:0 Write sets selected bits in DCH1SSIZ, read yields undefined value
BF88_317C DCH1SSIZINV 31:0 Write inverts selected bits in DCH1SSIZ, read yields undefined value

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3180 DCH1DSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDSIZ<7:0>
BF88_3184 DCH1DSIZCLR 31:0 Write clears selected bits in DCH1DSIZ, read yields undefined value
BF88_3188 DCH1DSIZSET 31:0 Write sets selected bits in DCH1DSIZ, read yields undefined value
BF88_318C DCH1DSIZINV 31:0 Write inverts selected bits in DCH1DSIZ, read yields undefined value
BF88_3190 DCH1SPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSPTR<7:0>
BF88_31A0 DCH1DPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDPTR<7:0>
BF88_31B0 DCH1CSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCSIZ<7:0>
BF88_31B4 DCH1CSIZCLR 31:0 Write clears selected bits in DCH1CSIZ, read yields undefined value
BF88_31B8 DCH1CSIZSET 31:0 Write sets selected bits in DCH1CSIZ, read yields undefined value
BF88_31BC DCH1CSIZINV 31:0 Write inverts selected bits in DCH1CSIZ, read yields undefined value
BF88_31C0 DCH1CPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCPTR<7:0>
BF88_31D0 DCH1DAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHPDAT<7:0>
BF88_31D4 DCH1DATCLR 31:0 Write clears selected bits in DCH1DAT, read yields undefined value
BF88_31D8 DCH1DATSET 31:0 Write sets selected bits in DCH1DAT, read yields undefined value
BF88_31DC DCH1DATINV 31:0 Write inverts selected bits in DCH1DAT, read yields undefined value

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
Note 1: This summary table contains partial register definitions that only pertain to the DMA peripheral. Refer to the “PIC32MX Family Reference
Manual” (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
Name
Address(1) 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_31E0 DCH2CON 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — — CHCHNS
BF88_31E4 DCH2CONCLR 31:0 Write clears selected bits in DCH2CON, read yields undefined value
BF88_31E8 DCH2CONSET 31:0 Write sets selected bits in DCH2CON, read yields undefined value
BF88_31EC DCH2CONINV 31:0 Write inverts selected bits in DCH2CON, read yields undefined value
BF88_31F0 DCH2ECON 31:24 — — — — — — — —
23:16 CHAIRQ<7:0>
15:8 CHSIRQ<7:0>
BF88_31F4 DCH2ECONCLR 31:0 Write clears selected bits in DCH2ECON, read yields undefined value
BF88_31F8 DCH2ECONSET 31:0 Write sets selected bits in DCH2ECON, read yields undefined value
BF88_31FC DCH2ECONINV 31:0 Write inverts selected bits in DCH2ECON, read yields undefined value
BF88_3200 DCH2INT 31:24 — — — — — — — —
15:8 — — — — — — — —
BF88_3210 DCH2SSA 31:24 CHSSA<31:24>
23:16 CHSSA<23:16>
15:8 CHSSA<15:8>
7:0 CHSSA<7:0>
BF88_3220 DCH2DSA 31:24 CHDSA<31:24>
23:16 CHDSA<23:16>
15:8 CHDSA<15:8>
7:0 CHDSA<7:0>
BF88_3224 DCH2DSACLR 31:0 Write clears selected bits in DCH2DSA, read yields undefined value
BF88_3228 DCH2DSASET 31:0 Write sets selected bits in DCH2DSA, read yields undefined value
BF88_322C DCH2DSAINV 31:0 Write inverts selected bits in DCH2DSA, read yields undefined value
BF88_3230 DCH2SSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSSIZ<7:0>
BF88_3234 DCH2SSIZCLR 31:0 Write clears selected bits in DCH2SSIZ, read yields undefined value
BF88_3238 DCH2SSIZSET 31:0 Write sets selected bits in DCH2SSIZ, read yields undefined value
BF88_323C DCH2SSIZINV 31:0 Write inverts selected bits in DCH2SSIZ, read yields undefined value
BF88_3240 DCH2DSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDSIZ<7:0>

PIC32MX3XX/4XX
Name
Address(1) 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3250 DCH2SPTR 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSPTR<7:0>
BF88_3260 DCH2DPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDPTR<7:0>
BF88_3270 DCH2CSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCSIZ<7:0>
BF88_3274 DCH2CSIZCLR 31:0 Write clears selected bits in DCH2CSIZ, read yields undefined value
BF88_3278 DCH2CSIZSET 31:0 Write sets selected bits in DCH2CSIZ, read yields undefined value
BF88_327C DCH2CSIZINV 31:0 Write inverts selected bits in DCH2CSIZ, read yields undefined value
BF88_3280 DCH2CPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCPTR<7:0>
BF88_3290 DCH2DAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHPDAT<7:0>

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

PIC32MX3XX/4XX
Name
Address(1) 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_32A0 DCH3CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — CHCHNS
BF88_32A4 DCH3CONCLR 31:0 Write clears selected bits in DCH3CON, read yields undefined value
BF88_32A8 DCH3CONSET 31:0 Write sets selected bits in DCH3CON, read yields undefined value
BF88_32AC DCH3CONINV 31:0 Write inverts selected bits in DCH3CON, read yields undefined value
BF88_32B0 DCH3ECON 31:24 — — — — — — — —
23:16 CHAIRQ<7:0>
15:8 CHSIRQ<7:0>
BF88_32B4 DCH3ECONCLR 31:0 Write clears selected bits in DCH3ECON, read yields undefined value
BF88_32B8 DCH3ECONSET 31:0 Write sets selected bits in DCH3ECON, read yields undefined value
BF88_32BC DCH3ECONINV 31:0 Write inverts selected bits in DCH3ECON, read yields undefined value
BF88_32C0 DCH3INT 31:24 — — — — — — — —
15:8 — — — — — — — —
BF88_32C4 DCH3INTCLR 31:0 Write clears selected bits in DCH3INT, read yields undefined value
BF88_32C8 DCH3INTSET 31:0 Write sets selected bits in DCH3INT, read yields undefined value
BF88_32CC DCH3INTINV 31:0 Write inverts selected bits in DCH3INT, read yields undefined value
BF88_32D0 DCH3SSA 31:24 CHSSA<31:24>
23:16 CHSSA<23:16>
15:8 CHSSA<15:8>
7:0 CHSSA<7:0>
BF88_32D4 DCH3SSACLR 31:0 Write clears selected bits in DCH3SSA, read yields undefined value
BF88_32D8 DCH3SSASET 31:0 Write sets selected bits in DCH3SSA, read yields undefined value
BF88_32DC DCH3SSAINV 31:0 Write inverts selected bits in DCH3SSA, read yields undefined value
BF88_32E0 DCH3DSA 31:24 CHDSA<31:24>
23:16 CHDSA<23:16>
15:8 CHDSA<15:8>
7:0 CHDSA<7:0>
BF88_32E4 DCH3DSACLR 31:0 Write clears selected bits in DCH3DSA, read yields undefined value
BF88_32E8 DCH3DSASET 31:0 Write sets selected bits in DCH3DSA, read yields undefined value
BF88_32EC DCH3DSAINV 31:0 Write inverts selected bits in DCH3DSA, read yields undefined value
BF88_32F0 DCH3SSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSSIZ<7:0>
BF88_32F4 DCH3SSIZCLR 31:0 Write clears selected bits in DCH3SSIZ, read yields undefined value
BF88_32F8 DCH3SSIZSET 31:0 Write sets selected bits in DCH3SSIZ, read yields undefined value
BF88_32FC DCH3SSIZINV 31:0 Write inverts selected bits in DCH3SSIZ, read yields undefined value
BF88_3300 DCH3DSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDSIZ<7:0>
BF88_3310 DCH3SPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHSPTR<7:0>

PIC32MX3XX/4XX
Name
Address(1) 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_3320 DCH3DPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHDPTR<7:0>
BF88_3330 DCH3CSIZ 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCSIZ<7:0>
BF88_3334 DCH3CSIZCLR 31:0 Write clears selected bits in DCH3CSIZ, read yields undefined value
BF88_3338 DCH3CSIZSET 31:0 Write sets selected bits in DCH3CSIZ, read yields undefined value
BF88_333C DCH3CSIZINV 31:0 Write inverts selected bits in DCH3CSIZ, read yields undefined value
BF88_3340 DCH3CPTR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHCPTR<7:0>
BF88_3350 DCH3DAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CHPDAT<7:0>
TABLE 10-11: DMA CHANNEL 3 INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

PIC32MX3XX/4XX
REGISTER 10-1: DMACON: DMA CONTROLLER CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x

ON FRZ SIDL SUSPEND — — — —
bit 15 bit 8

— — — — — — — —
bit 7 bit 0
Legend:

bit 15 ON: DMA On bit
1 = DMA module is enabled
0 = DMA module is disabled
bit 14 FRZ: DMA Freeze bit(1)
1 = DMA is frozen during Debug mode
0 = DMA continues to run during Debug mode
Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in Normal mode.
bit 13 SIDL: Stop in Idle Mode bit
1 = DMA transfers are frozen during Sleep
0 = DMA transfers continue during Sleep
bit 12 SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally

PIC32MX3XX/4XX
REGISTER 10-2: DMASTAT: DMA STATUS REGISTER(1)
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
r-x r-x r-x r-x R-0 r-x R-0 R-0

— — — — RDWR — DMACH<1:0>
bit 7 bit 0
Legend:

bit 3 RDWR: Read/Write Status bit
1 = Last DMA bus access was a read
0 = Last DMA bus access was a write
bit 1-0 DMACH<1:0>: DMA Channel bits
Note 1: This register contains the value of the most recent active DMA channel.

PIC32MX3XX/4XX
REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER(1)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<31:24>
bit 31 bit 24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<23:16>
bit 23 bit 16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DMAADDR<7:0>
bit 7 bit 0
Legend:
bit 31-0 DMAADDR<31:0>: DMA Module Address bits

Note 1: This register contains the address of the most recent DMA access.

PIC32MX3XX/4XX
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — PLEN<3:0>
bit 15 bit 8
R/W-0 R/W-0 r-x r-x r-x r-x R/W-0 R/W-0

CRCEN CRCAPP — — — — CRCCH<1:0>
bit 7 bit 0
Legend:

bit 11-8 PLEN<3:0>: Polynomial Length bits
Denotes the length of the polynomial –1.
bit 7 CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
bit 6 CRCAPP: CRC Append Mode bit
1 = Data read will be passed to the CRC, to be included in the CRC calculation, but is not written to
the destination register. When a block transfer completes, the calculated CRC will be written to
the location given by DCHxDSA
0 = Channel behaves normally, with the CRC being calculated as data is transferred from the source
to the destination
bit 1-0 CRCCH<1:0>: CRC Channel Select bits
11 = CRC is assigned to Channel 3

PIC32MX3XX/4XX
REGISTER 10-5: DCRCDATA: DMA CRC DATA REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

DCRCDATA<15:8>
bit 15 bit 8

DCRCDATA<7:0>
bit 7 bit 0
Legend:

bit 15-0 DCRCDATA<15:0>: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current
value of the CRC. Bits > PLEN will return ‘0’ on any read.

PIC32MX3XX/4XX
REGISTER 10-6: DCRCXOR: DMA CRC XOR ENABLE REGISTER(1)
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

DCRCXOR<15:8>
bit 15 bit 8

DCRCXOR<7:0>
bit 7 bit 0
Legend:

bit 15-0 DCRCXOR<15:0>: CRC XOR Register bits
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted directly in from the previous stage in
the register
Note 1: The LSb of the DCRCXOR register will be always set.

PIC32MX3XX/4XX
REGISTER 10-7: DCHXCON: DMA CHANNEL X CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — CHCHNS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 r-x R-0 R/W-0 R/W-0

CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>
bit 7 bit 0
Legend:

bit 8 CHCHNS: Chain Channel Selection bit
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
Note: The chain selection bit takes effect when chaining is enabled, i.e., CHCHN = 1.
bit 7 CHEN: Channel Enable bit
1 = Channel is enabled
0 = Channel is disabled
bit 6 CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit 5 CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained to channel higher in natural priority
0 = Do not chain to channel higher in natural priority
bit 4 CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 2 CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0 CHPRI<1:0>: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2

PIC32MX3XX/4XX
REGISTER 10-8: DCHXECON: DMA CHANNEL X EVENT CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

CHAIRQ<7:0>
bit 23 bit 16

CHSIRQ<7:0>
bit 15 bit 8
S-0 S-0 R/W-0 R/W-0 R/W-0 r-x r-x r-x

CFORCE CABORT PATEN SIRQEN AIRQEN — — —
bit 7 bit 0
Legend:

bit 23-16 CHAIRQ<7:0>: IRQ that will abort Channel Transfer bits
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•••
bit 15-8 CHSIRQ<7:0>: IRQ that will Start Channel Transfer bits
11111111 = Interrupt 255 will initiate a DMA transfer
•••

bit 7 CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 6 CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 5 PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
bit 4 SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer

PIC32MX3XX/4XX
REGISTER 10-8: DCHXECON: DMA CHANNEL X EVENT CONTROL REGISTER (CONTINUED)
bit 3 AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer

PIC32MX3XX/4XX
REGISTER 10-9: DCHXINT: DMA CHANNEL X INTERRUPT CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF
bit 7 bit 0
Legend:

bit 23 CHSDIE: Channel Source Done Interrupt Enable bit
bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit
bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit
bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit
bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit
bit 16 CHERIE: Channel Address Error Interrupt Enable bit

PIC32MX3XX/4XX
REGISTER 10-9: DCHXINT: DMA CHANNEL X INTERRUPT CONTROL REGISTER (CONTINUED)
bit 7 CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR == CHSSIZ)
0 = No interrupt is pending
bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR == CHSSIZ/2)
bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR == CHDSIZ)
bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR == CHDSIZ/2)
bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred)
or a pattern match event occurs
bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
bit 0 CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected
Either the source or the destination address is invalid.

PIC32MX3XX/4XX
REGISTER 10-10: DCHXSSA: DMA CHANNEL X SOURCE START ADDRESS REGISTER
CHSSA<31:24>
bit 31 bit 24

CHSSA<23:16>
bit 23 bit 16

CHSSA<15:8>
bit 15 bit 8

CHSSA<7:0>
bit 7 bit 0
Legend:
bit 31-0 CHSSA<31:0> Channel Source Start Address bits

Channel source start address.
Note: This must be the physical address of the source.

PIC32MX3XX/4XX
REGISTER 10-11: DCHXDSA: DMA CHANNEL X DESTINATION START ADDRESS REGISTER
CHDSA<31:24>
bit 31 bit 24

CHDSA<23:16>
bit 23 bit 16

CHDSA<15:8>
bit 15 bit 8

CHDSA<7:0>
bit 7 bit 0
Legend:
bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits

Channel destination start address.
Note: This must be the physical address of the destination.

PIC32MX3XX/4XX
REGISTER 10-12: DCHXSSIZ: DMA CHANNEL X SOURCE SIZE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

CHSSIZ<7:0>
bit 7 bit 0
Legend:

bit 7-0 CHSSIZ<7:0>: Channel Source Size bits
255 = 255-byte source size
•••


PIC32MX3XX/4XX
REGISTER 10-13: DCHXDSIZ: DMA CHANNEL X DESTINATION SIZE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

CHDSIZ<7:0>
bit 7 bit 0
Legend:

bit 7-0 CHDSIZ<7:0>: Channel Destination Size bits
255 = 255-byte destination size
•••


PIC32MX3XX/4XX
REGISTER 10-14: DCHXSPTR: DMA CHANNEL X SOURCE POINTER REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHSPTR<7:0>
bit 7 bit 0
Legend:

bit 7-0 CHSPTR<7:0>: Channel Source Pointer bits
255 = Points to 255th byte of the source
•••
1 = Points to 1st byte of the source

0 = Points to 0th byte of the source
Note: This is reset on pattern detect, when in Pattern Detect mode.

PIC32MX3XX/4XX
REGISTER 10-15: DCHXDPTR: CHANNEL X DESTINATION POINTER REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHDPTR<7:0>
bit 7 bit 0
Legend:

bit 7-0 CHDPTR<7:0>: Channel Destination Pointer bits
255 = Points to 255th byte of the destination
•••
1 = Points to 1st byte of the destination

0 = Points to 0th byte of the destination

PIC32MX3XX/4XX
REGISTER 10-16: DCHXCSIZ: DMA CHANNEL X CELL-SIZE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

CHCSIZ<7:0>
bit 7 bit 0
Legend:

bit 7-0 CHCSIZ<7:0>: Channel Cell Size bits
255 = 255 bytes transferred on an event
•••

1 = 1 byte transferred on an event

PIC32MX3XX/4XX
REGISTER 10-17: DCHXCPTR: DMA CHANNEL X CELL POINTER REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHCPTR<7:0>
bit 7 bit 0
Legend:

bit 7-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits
255 = 255 Bytes have been transferred since the last event
•••

Note: This is reset on pattern detect, when in Pattern Detect mode.

PIC32MX3XX/4XX
REGISTER 10-18: DCHXDAT: DMA CHANNEL X PATTERN DATA REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

CHPDAT<7:0>
bit 7 bit 0
Legend:

bit 7-0 CHPDAT<7:0>: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:

Unused.

PIC32MX3XX/4XX
10.2 DMA Controller Operation • The Source and Destination Pointers are reset:
A DMA channel will transfer data from a source to a - On any device Reset.
destination without CPU intervention. - When the DMA is turned off (ON bit
(DMACON<15>) is ‘0’).
DMA controller configuration resources:
Note: Always wait for the channels to complete
• The DMA Controller and the corresponding DMA
the current transactions (or abort first and
channel have to be enabled using the ON
make sure the transfers were successfully
(DMACON<15>) and the CHEN (DCHxCON<7>)
aborted) before switching the DMA
bits.
controller OFF.
• The source and destination of the transfer are
programmable using the DCHxSSA and - A block transfer completes (regardless of the
DCHxDSA registers respectively. state of CHAEN (DCHxCON<4>)).
• The source and destination are further indepen- - A pattern match terminates a transfer
dently configurable using the DCHxSSIZ and (regardless of the state of auto-enable
DCHxDSIZ registers. CHAEN (DCHxCON<4>)).
• A DMA transfer can be initiated in one of two - CABORT (DCHxECON<6>) flag is written.
ways: Note: If the DMA channel is suspended in the mid-
- Software can initiate a transfer by setting the dle of a transfer (If CHEN (DCHxCON)<7>
channel CFORCE (DCHxECON<7>) bit. = 0) or if the DMA controller is suspended in
- An interrupt event occurs that matches the the middle of a transfer (If SUSPEND
CHSIRQ (DCHxECON<15:8>) interrupt and (DMACON)<12> = 1) and a CABORT is
SIRQEN = 1 (DCHxECON<4>). The user can issued, the Source, Destination and Cell
select any interrupt on the device to start a pointers are not Reset.
DMA transfer. - If the channel source address (DCHxSSA) is
Note: BMX arbitration mode 2 (rotating priority) is updated, the Source Pointer (DCHxSPTR)
recommended when a system may will be reset.
experience heavy bus load. - Similarly, updates to the Destination Address
(DCHxDSA) will cause the Destination
• At each event requiring a DMA transfer, a num-
Pointer (DCHxDPTR) to be reset.
ber of bytes specified by the cell size (DCHxCSIZ)
will be transferred (one or more transactions will • Normally, the DMA channel remains enabled until
occur). the DMA channel has completed a block transfer
unless the auto-enable feature is turned on
• The channel keeps track of the number of bytes
(i.e., CHAEN = 1).
transferred from the source to destination, using
Source and Destination Pointers (DCHxSPTR • When the channel is disabled, further transfers
and DCHxDPTR). will be prohibited until the channel is re-enabled
(CHEN is set to ‘1’).
• The Source and Destination Pointers are read-
only and are updated after every transaction. • A DMA transfer request will be stopped/aborted
by:
• Interrupts are generated when the Source or
Destination pointer is half of the source or desti- - Writing the CABORT bit (DCHxECON<6>).
nation size (DCHxSSIZ/2 or DCHxDSIZ/2), or - Pattern match occurs if pattern match is
when the source or destination counter equals the enabled PATEN = 1 (DCHxECON<5>), pro-
size of the source or destination. These interrupts vided that channel CHAEN is not set.
are CHSHIF, CHDHIF and CHSDIF, CHDDIF, - Interrupt event occurs on the device that
respectively. matches the CHAIRQ (DCHxECON<23:16>)
interrupt if enabled by AIRQEN
(DCHxECON<3>).
- An address error is detected.
- A block transfer completes provided that
Channel Auto-Enable mode (CHAEN) is not
set.
• When a channel abort interrupt occurs, the
Channel Abort Interrupt Flag, CHTAIF,
(DCHxINT<1>) is set. This allows the user to
detect and recover from an aborted DMA transfer.
When a transfer is aborted, any transaction
currently underway will be completed.

PIC32MX3XX/4XX
10.2.1 DMA CONTROLLER TERMINOLOGY 10.3.1 BASIC TRANSFER MODE
Event: Any system event that can initiate or abort a CONFIGURATION
DMA transfer. Microchip recommends taking the following steps to
Transaction: A single-word transfer (up to 4 bytes), configure a DMA transfer:
comprised of read and write operations. • Disable the DMA channel interrupts in the INT
Cell Transfer: The number of bytes transferred when controller.
a DMA channel has a transfer initiated before waiting • Clear any existing channel interrupt flags in the
for another event (given by the DCHCSIZ register). A INT controller.
cell transfer comprises one or more transactions. • Enable the DMA controller (if not already
Block Transfer: Defined as the number of bytes trans- enabled) in DMACON register.
ferred when a channel is enabled. The number of bytes • Set Channel Control register: Priority,
is the larger of either DCHxSSIZ or DCHxDSIZ. A block Auto-Enable mode, etc., in DCHxCON. (Don’t
transfer comprises one or more cell transfers. enable the channel yet!)
• Set the channel event control: clear/set the events
10.3 Basic Transfer Mode starting and aborting the transfer. If needed, also
Basic Transfer mode transfer features: set the pattern match enable in DCHxECON.
• If using a pattern match, set the pattern in the
• The transfer size is limited to a maximum of 256
DCHxDAT register.
bytes transferred per channel.
• Set the transfer source and destination physical
• The Source and Destination Pointers wrap around
addresses (DCHxSSA and DCHxDSA registers).
based on the selected source and destination
size. • Set the source and destination sizes (DCHxSSIZ,
DCHxDSIZ registers).
• A block transfer is complete when the block size
bytes have been transferred. The block size is the • Set the cell transfer size (DCHxCSIZ).
larger of source and destination sizes: • Clear any existing event flag in the DCHxINT
- blockSize = max (DCHxSSIZ, DCHxDSIZ). register.
• A DMA event will transfer cell size (DCHxCSIZ) • If using interrupts:
bytes from source to destination. However, if - Set the conditions that will generate an inter-
DCHxCSIZ is greater than the block size, then rupt in the DCHxINT register (at least error
just block size bytes will be transferred. interrupt enable and abort interrupt enable,
usually block complete interrupt).
- Set the DMA channel interrupt priority and
subpriority in the INT controller.
- Enable the DMA channel interrupt in the INT
controller.
• Enable the selected DMA channel with CHEN
(DCHxCON<7>).
• If not using system events to start the DMA
transfer use CFORCE (DCHxECON<7>) to start
transfer.
• Until the DMA transfer is complete you can do
some other processing.
• If transfer complete interrupts (cell complete,
block complete, etc.) are enabled, a notification
will be presented in the ISR that the DMA transfer
completed.
• Otherwise, the DMA channel can be polled to see
if the transfer is completed using, for example,
CHBCIF (DCHxINT<3>).
Refer to Example 10-1.

PIC32MX3XX/4XX
EXAMPLE 10-1: CONFIGURING THE DMA FOR BASIC TRANSFER MODE OPERATION
/*
The following code example illustrates the DMA channel 0 configuration for a basic transfer.
*/
IEC1CLR=0x00010000; // disable DMA channel 0 interrupts
IFS1CLR=0x00010000; // clear existing DMA channel 0 interrupt flag
DMACONSET=0x00008000; // enable the DMA controller

DCH0CON=0x3; // channel off, pri 3, no chaining
CH0ECON=0; // no start or stop irq’s, no pattern match
// program the transfer

DCH0SSA=0x1d010000; // transfer source physical address
DCH0DSA=0x1d020000; // transfer destination physical address
DCH0SSIZ=0; // source size 256 bytes
DCH0DSIZ=0; // destination size 256 bytes
DCH0CSIZ=0; // 256 bytes transferred per event
DCH0INTCLR=0x00ff00ff; // clear existing events, disable all interrupts

DCH0CONSET=0x80; // turn channel on
// initiate a transfer
DCH0ECONSET=0x00000080; // set CFORCE to 1
// do something else
// poll to see that the transfer was done
while(TRUE)
{
register int pollCnt; // use a poll counter.
// polling continuously the DMA controller in a tight
// loop would affect the performance of the DMA transfer
int dmaFlags=DCH0INT;
if( (dmaFlags&0xb)
{ // one of CHERIF (DCHxINT<0>), CHTAIF (DCHxINT<1>)
// or CHBCIF (DCHxINT<3>) flags set
break; // transfer completed
}
pollCnt=100; // use an adjusted value here
while(pollCnt--); // wait before reading again the DMA controller
}
// check the transfer completion result

PIC32MX3XX/4XX
10.4 Pattern Match Termination • If using interrupts:
- Set the conditions that will generate an inter-
The Pattern Match mode is enabled by setting the
rupt in the DCHxINT register (at least error
PATEN bit (DCHxECON<5>).
interrupt enable and abort interrupt enable,
This feature is useful in applications where a variable usually block complete interrupt).
data size is required and eases the setup of the DMA - Set the DMA channel interrupt priority and
channel. A good usage is for transferring ASCII com- subpriority in the INT controller.
mand strings from an UART, <CR> ended. This is also
- Enable the DMA channel interrupt in the INT
useful for implementing string copy routines with DMA
controller.
support.
• Enable the selected DMA channel with CHEN
Pattern Match mode features: (DCHxCON<7>).
• Allows the user to end a transfer if a byte of data • If not using system events to start the DMA
written during a transaction matches a specific transfer use CFORCE (DCHxECON<7>) to start
pattern. transfer.
• A pattern match is treated the same way as a • Until the DMA transfer is complete, you can do
block transfer complete, where the CHBCIF some other processing.
(DCHxINT<3>) bit is set and the CHEN • If you enabled transfer complete interrupts (cell
(DCHxCON<7>) bit is cleared provided complete, block complete, etc) you’ll be notified in
auto-enable CHAEN = 0 (DCHxCON<4>). the ISR that the DMA transfer completed.
• The pattern is stored in the DCHxDAT register. • Otherwise, you can poll the DMA channel to see if
• If any byte in the source matches DCHxDAT, a the transfer is completed using, for example,
pattern match is detected. CHBCIF (DCHxINT<3>).
10.4.1 PATTERN MATCH MODE
CONFIGURATION
The Pattern Match mode is an option for use when
performing DMA transfers in basic DMA configuration.
Therefore, the steps needed in Pattern Match mode
are identical to those used in basic DMA configuration.
An extra step is needed to store the desired pattern in
DCHxDAT register.
The following steps are recommended to be taken to
configure a DMA transfer in Pattern Match mode:
• Disable the DMA channel interrupts in the INT
controller.
• Clear any existing channel interrupt flags in the
INT controller.
• Enable the DMA controller (if not already
enabled) in DMACON register.
• Set Channel Control register: Priority,
Auto-Enable mode, etc., in DCHxCON. Don’t
enable the channel yet.
• Set the channel event control: clear/set the events
starting and aborting the transfer. Set the pattern
match enable PATEN in DCHxECON.
• Set the pattern in the DCHxDAT register.
• Set the transfer source and destination physical
addresses (DCHxSSA and DCHxDSA registers).
• Set the source and destination sizes (DCHxSSIZ,
DCHxDSIZ registers).
• Set the cell transfer size (DCHxCSIZ).
• Clear any existing event flag in DCHxINT register.

PIC32MX3XX/4XX
EXAMPLE 10-2: CONFIGURING THE DMA FOR PATTERN MATCH OPERATION
/*
The following code example illustrates the DMA channel 0 configuration for data transfer with
pattern match enabled. Transfer from the UART1 a <CR> ended string, at most 256 characters long
*/

IFS1CLR=0x00010000; // clear any existing DMA channel 0 interrupt flag

DCH0CON=0x03; // channel off, priority 3, no chaining
DCH0ECON=(27 <<8)| 0x30; // start irq is UART1 RX, pattern match enabled
DCH0DAT=’\r’; // pattern value, carriage return

DCH0SSA=VirtToPhys(&U1RXREG); // transfer source physical address
DCH0SSIZ=1; // source size is 1 byte
DCH0DSIZ=0; // dst size at most 256 bytes
DCH0CSIZ=1; // one byte per UART transfer request

DCH0INTSET=0x00090000; // enable Block Complete and error interrupts
IPC9CLR=0x0000001f; // clear the DMA channel 0 priority and subpriority

IPC9SET=0x00000016; // set IPL 5, subpriority 2
IEC1SET=0x00010000; // enable DMA channel 0 interrupt
// wait for an UART RX interrupt to initiate a transfer
// will get an interrupt when the transfer is done

// or when an address error occurred

PIC32MX3XX/4XX
10.5 Channel Chaining Mode 10.6 Channel Auto-Enable Mode
The Chaining mode is enabled by setting the Chaining The Auto-Enable mode is enabled by setting the
Enable it CHCEN bit (DCHxCON<5>) and Chaining CHAEN bit (DCHxCON<4>).
Direction bit CHCHNS (DCHxCON<8>). Channel auto-enable function is an enhancement to
Channel chaining is an enhancement to the DMA the DMA channel operation.
channel operation. The channel auto-enable can be used to keep a chan-
A good usage is for transferring data packets from one nel active, even if a block transfer completes or a pat-
peripheral to memory and then from memory to tern match occurs. This prevents the user from having
another peripheral. This module is also useful for to re-enable the channel each time a block transfer
implementing data acquisition in multiple buffers. completes. This mode is useful for applications that do
Chaining mode features: repeated pattern matching.
• A channel (slave channel) can be chained to an 10.6.1 AUTO-ENABLE MODE

adjacent channel (master channel). When the CONFIGURATION
master channel completes a block transfer the
slave channel will be enabled. The Auto-Enable mode is an extra option for use when
performing DMA transfers. Therefore, the steps
• At this point, any event on the slave channel will
needed in Auto-Enable mode are identical to those
initiate a cell transfer. If the channel has an event
used in basic DMA configuration, with the following dif-
pending, a cell transfer will begin immediately.
ferences (refer to Section 10.3.1 “Basic Transfer
• Channels are chained in natural priority order Mode Configuration”):
where channel 0 has the highest priority and
channel 3 the lowest. A specific channel can be • The CHAEN bit has to be set before enabling the
enabled by an adjacent channel, either higher, or channel (setting the CHEN bit (DCHxCON<7>)).
lower, in natural order, by configuring the • The channel will behave as normal except that
CHCHNS (DCHxCON<8>) bit. Chaining must be normal termination of a transfer will not result in
enabled, CHCHN (DCHxCON<5>) = 1. the channel being disabled.
• An important feature of the DMA controller is the • Normal block transfer completion is defined as:
ability to allow events while the channel is dis- - block transfer complete
abled using the CHAED (DCHxCON<6>) bit. This - pattern match detect
bit is particularly useful in Chained mode where • As before, the Channel Pointers will be reset.
the slave channel needs to be ready to start a
transfer as soon as the channel is enabled by the
master channel.
10.5.1 CHAINING MODE CONFIGURATION

The Chaining mode is an option for use when perform-
ing DMA transfers. Therefore, the steps needed in
Chaining mode are identical to those used in basic
DMA configuration, with the following differences
(refer to Section 10.3.1 “Basic Transfer Mode Con-
figuration”):
• Two different channels have to be configured and
the slave channel has to have chaining enable
(CHCHN) and chaining direction (CHCHNS) set.

PIC32MX3XX/4XX
EXAMPLE 10-3: CONFIGURING THE DMA FOR CHAINING MODE OPERATION
/*
The following code example illustrates the DMA channel 0 configuration for data transfer
with pattern match enabled. DMA channel 0 transfer from the UART1 to a RAM buffer while DMA
channel 1 transfers data from the RAM buffer to UART2. Transferred strings are at most 256
characters long. Transfer on UART2 will start as soon as the UART1 transfer is completed.
*/
unsigned char myBuff<256>; // transfer buffer

DCH0CON=0x3; // channel 0 off, priority 3, no chaining

DCH1CON=0x62; // channel 1 off, priority 2
// chain to higher priority
// (ch 0), enable events detection while disabled
DCH0ECON=(27 <<8)| 0x30; // start irq is UART1 RX, pattern enabled

DCH1ECON=(42 <<8)| 0x30; // start irq is UART1 TX, pattern enabled
DCH0DAT=DCH1DAT=’\r’; // pattern value, carriage return
// program channel 0 transfer

DCH0SSA=VirtToPhys(&U1RXREG); // transfer source physical address
DCH0DSA=VirtToPhys(myBuff); // transfer destination physical address
DCH0SSIZ=1; // source size is 1 byte
DCH0DSIZ=0; // dst size at most 256 bytes
// program channel 1 transfer

DCH1SSA=VirtToPhys(myBuff); // transfer source physical address
DCH1DSA=VirtToPhys(&U2TXREG); // transfer destination physical address
DCH1SSIZ=0; // source size at most 256 bytes
DCH1DSIZ=1; // dst size is 1 byte
DCH0INTCLR=0x00ff00ff; // DMA0: clear events, disable interrupts

DCH1INTSET=0x00090000; // DMA1: enable Block Complete and error interrupts
IPC9CLR=0x00001f1f; // clear the DMA channels 0 and 1 priority and

// subpriority
IPC9SET=0x00000b16; // set IPL 5, subpriority 2 for DMA channel 0
// set IPL 2, subpriority 3 for DMA channel 1
// the UART1 RX interrupts will initiate the DMA channel 0 transfer

// once this transfer is complete, the DMA channel 1 will start
// upon DMA channel 1 transfer completion will get an interrupt
while(!intCh1occurred); // poll DMA channel 1 interrupt

PIC32MX3XX/4XX
10.7 CRC Module Operation 10.8 CRC Background Mode
The DMA module has one integrated CRC generation The CRC Background mode is enabled by clearing
module shared by all channels. The CRC module is a CRCAPP (DCRCCON<6>).
highly configurable, 16-bit CRC generator. The CRC In this mode, the behavior of the DMA channel is
module can be assigned to any available DMA chan- maintained with data read from the channel source
nel by setting the CRCCH bits (DCRCCON<1:0>) being passed to the CRC module and then written
appropriately. The CRC is enabled by setting the back to the destination.
CRCEN bit (DCRCCON<7>).
In the Background mode, the calculated CRC is left in
The CRC generator will take 1 system clock to process the DCRCDATA register at the end of the block
each byte of data read from the source. This implies transfer.
that if 32 bits of data are read from the source, the
CRC generation will take 4 system clocks to process This mode can be used to calculate a CRC as data is
the data. moved from source to destination. A good example of
where this can be used is to calculate a CRC as data
The CRC module modifies the behavior of the DMA is transmitted to or received from the UART module.
channel associated with the CRC module. The two When the data transfer is complete the user can read
operating modes for a DMA channel associated with the calculated CRC and either append it to the
the CRC module are: transmitted data or verify the received CRC data.
• Background Mode: CRC is calculated in the
background, with normal DMA behavior 10.8.1 CRC BACKGROUND MODE
maintained. CONFIGURATION
• Append Mode: Data read from the source is not Microchip recommends taking the following steps to
written to the destination, but the CRC data is configure a CRC calculation in Background mode:
accumulated in the CRC data register. The accu-
• Seed the CRC generator by writing the initial seed
mulated CRC is written to the destination address
to the DCRCDATA register.
when a block transfer completes.
• Set the polynomial generator by writing to the
CRC Configurable resources: DCRCXOR register.
• The terms of the polynomial can be programmed • Set the polynomial generator length by writing the
using the DCRCXOR<15:0> bits. Considering the PLEN (DCRCCON<11:8>).
CRC polynomial: x16 + x12 + x5 + 1, 17 bits are • Attach the CRC calculation to the desired DMA
needed to define this polynomial. However, the channel performing the transfer by writing the
value to be written to the DCRCXOR register will CRCCH (DCRCCON<2:0>).
be 0b0001 0000 0010 0000, i.e., 0x1020.
• Use the Background mode by clearing the
Note: The LSb and MSb do not have to be CRCAPP (DCRCCON<6>) bit.
specified, they are always set. The actual • Enable the CRC calculation by setting the
value used for the polynomial generator CRCEN (DCRCCON<7>).
will be 0x11021.
• Once the DMA transfer begins, the CRC
• The length of the polynomial generator can be calculation will begin as well.
programmed using the PLEN (DCRCCON<11:8>)
• Once the DMA transfer ends, the CRC result will
bits. For the above polynomial, the size will be 16.
be available by reading the DCRCDATA register.
The PLEN will be programmed with length -1, i.e.,
0x0F. Refer to Example 10-4.
• The CRC module can be assigned to any avail- Note: The configuration steps specific for the
able DMA channel by setting the CRCCH bits CRC configuration are shown. The DMA
(DCRCCON<2:0>) appropriately. transfer configuration is the same as
• The CRC is enabled by setting the CRCEN bit previously explained (see Section 10.2
(DCRCCON<7>). “DMA Controller Operation”).
• The CRC generator can be seeded by writing to
the DCRCDATA register before enabling the
channel that will use the CRC module.
• The CRC can be read as it progresses by reading
the DCRCDATA register at any time during the
CRC generation.
• Data Order: As data is read from the source regis-
ter, the data is fed into the CRC generator MSB
first.

PIC32MX3XX/4XX
EXAMPLE 10-4: CRC BACKGROUND MODE OPERATION
/*
The following code example illustrates a DMA calculation using the CRC background mode. Data is
transferred from a 256 bytes Flash buffer to a RAM buffer and the CRC is calculated while the
transfer takes place. */
unsigned int blockCrc; // CRC of the flash block

DCRCDATA=0xffff; // seed the CRC generator

DCRCXOR=0x1021; // Use the standard CCITT CRC 16 polynomial: X^16+X^12+X^5+1
DCRCCON=0x0f80; // CRC enabled, polynomial length 16, background mode
// CRC attached to the DMA channel 0.

DCH0ECON=0; // no start irqs, no match enabled
// program channel transfer

DCH0SSA=VirtToPhys(flashBuff); // transfer source physical address
DCH0DSA=VirtToPhys(ramBuff); // transfer destination physical address
DCH0SSIZ=0; // source size
DCH0DSIZ=0; // dst size
DCH0CSIZ=0; // 256 bytes per transfer
DCH0CONSET=0x80; // channel 0 on
// do something else while the transfer takes place
BOOL error=FALSE;
while(TRUE)
{
register int pollCnt; // don’t poll in a tight loop
if( (dmaFlags& 0x3)
{ // CHERIF (DCHxINT<0>) or CHTAIF (DCHxINT<1> set
error=TRUE; // error or aborted...
break;
}
else if (dmaFlags&0x8)
{ // CHBCIF (DCHxINT<3>) set
break; // transfer completed normally
}
while(pollCnt--); // wait before polling again
}
if(!error)
{
blockCrc=DCRDATA; // read the CRC of the transferred flash block
}
else
{
// process error
}

PIC32MX3XX/4XX
10.9 CRC Append Mode 10.9.1 CRC APPEND MODE
CONFIGURATION
The CRC Append mode is enabled by setting
CRCAPP (DCRCCON<6>). Microchip recommends taking the following steps to
configure a CRC calculation in Background mode:
In this mode, the behavior of the DMA channel is
changed. • Seed the CRC generator by writing the initial seed
to the DCRCDATA register.
Data read from the source will be fed into the CRC
generation module. No data is written to the destina- • Set the polynomial generator by writing to the
tion address in CRC Append mode until a block trans- DCRCXOR register.
fer completes or a pattern match occurs. On • Set the polynomial generator length by writing the
completion, the CRC value will be written to the PLEN (DCRCCON<11:8>).
address given by the Destination register (DCHxDSA). • Attach the CRC calculation to the desired DMA
This mode can be used for the CRC calculation of a channel performing the transfer by writing the
memory buffer, without actually performing a DMA CRCCH (DCRCCON<2:0>).
transfer to a destination. • Use the Append mode by setting the CRCAPP
(DCRCCON<6>) bit.
CRC Append mode Features:
• Enable the CRC calculation by setting the
• Only the source is considered when deciding if a CRCEN (DCRCCON<7>).
block transfer is complete.
• Program the DMA transfer destination with the
• The destination address (DCHxDSA) is only used
physical address of a variable where the CRC is
as the location to write the generated CRC to.
to be stored.
• The destination size (DCHxDSIZ) can have a
maximum size of 4. • Once the DMA transfer begins, the CRC
- If DCHxDSIZ is greater than 4, only 4 bytes are calculation will begin as well.
written at the end of the transfer. • Once the DMA transfer ends, the CRC result will
- If DCHxDSIZ is less than 4, only DCHxDSIZ bytes be deposited at the programmed DMA destination
of the CRC are written to the destination address. address.
- The high bytes (bits 31:16) are written as 0’s if Refer to Example 10-5.
more than 16 bits of the CRC are written.
- PLEN (CRCCON<11:8>) has no effect on the Note: The configuration steps specific for the
number of CRC bits that will be written to the CRC configuration are shown. The DMA
Destination register. transfer configuration is the same as
previously explained (see Section 10.2
• No CRC written back on an abort IRQ, user abort,
“DMA Controller Operation”).
bus error, etc.

PIC32MX3XX/4XX
EXAMPLE 10-5: CRC APPEND MODE OPERATION
/*
The following code example illustrates a DMA calculation using the CRC append mode. The CRC of a
200 bytes flash buffer is calculated without performing any data transfer. As soon as the CRC
calculation is completed the CRC value of the flash buffer is available in a local variable for
further use. */
unsigned int blockCrc; // CRC of the flash block

DCRCDATA=0xffff; // seed the CRC generator

DCRCXOR=0x1021; // Use the standard CCITT CRC 16 polynomial: X^16+X^12+X^5+1
DCRCCON=0x0fc0; // CRC enabled, polynomial length 16, append mode
// CRC attached to the DMA channel 0.

DCH0ECON=0; // no start irqs, no match enabled
// program channel transfer

DCH0SSA=VirtToPhys(flashBuff); // transfer source physical address
DCH0DSA=VirtToPhys(&blockCrc); // transfer destination physical address
DCH0SSIZ=200; // source size
DCH0DSIZ=200; // dst size
DCH0CSIZ=200; // 200 bytes per transfer

DCH0CONSET=0x80; // channel 0 on
// do something else while the CRC calculation takes place

BOOL error=FALSE;
while(TRUE)
{
register int pollCnt; // don’t poll in a tight loop
if( (dmaFlags& 0x3)
{ // CHERIF (DCHxINT<0>) or CHTAIF (DCHxINT<1> set
error=TRUE; // error or aborted...
break;
}
else if (dmaFlags&0x8)
{ // CHBCIF (DCHxINT<3>) set
break; // transfer completed normally
}
while(pollCnt--); // wait before polling again
}
if(error)
{
// process error
}
// the block CRC is available in the blockCrc variable

PIC32MX3XX/4XX
10.10 DMA Interrupts All the interrupts belonging to a DMA channel map to
the corresponding channel interrupt vector.
The DMA device has the ability to generate interrupts
reflecting the events that occur during the channel’s The corresponding interrupt flags are:
data transfer. The different kinds of DMA interrupt flags • DMA0IF (IFS1<16>)
are: • DMA1IF (IFS1<17>)
• CHERIF (DCHxINT<0>): Channel Error • DMA2IF (IFS1<18>)
interrupts, enabled using CHERIE • DMA3IF (IFS1<19>)
(DCHxINT<16>).
All these interrupt flags must be cleared in software.
• CHTAIF (DCHxINT<1>): Channel Abort interrupts,
enabled using CHTAIE (DCHxINT<17>). A DMA channel is enabled as a source of interrupts via
the respective DMA interrupt enable bits:
• CHBCIF (DCHxINT<3>): Channel Block complete
interrupts, enabled using CHBCIE • DMA0IE (IEC1<16>)
(DCHxINT<19>). • DMA1IE (IEC1<17>)
• CHCCIF (DCHxINT<2>): Channel Cell complete • DMA2IE (IEC1<18>)
interrupts, enabled using CHCCIE • DMA3IE (IEC1<19>)
(DCHxINT<18>).
The interrupt priority level bits and interrupt subpriority
• CHSDIF (DCHxINT<7>): Channel Source pointer
level bits must be also be configured:
reached the end of the source, enabled by
CHSDIE (DCHxINT<23>). • DMA0IP<2:0> (IPC9<4:2>), DMA0IS<1:0>
• CHSHIF (DCHxINT<6>): Channel Source pointer (IPC9<1:0>).
reached midpoint of the source, enabled by • DMA1IP<2:0> (IPC9<12:10>), DMA1IS<1:0>
CHSHIE (DCHxINT<22>). (IPC9<9:8>).
• CHDDIF (DCHxINT<5>): Channel Destination • DMA2IP<2:0> (IPC9<20:18>), DMA2IS<1:0>
Pointer reached the end of the destination, (IPC9<17:16>).
enabled by CHDDIE (DCHxINT<21>) • DMA3IP<2:0> (IPC9<28:26>), DMA3IS<1:0>
• CHDHIF (DCHxINT<4>): Channel Destination (IPC9<25:24>).
Pointer reached midpoint of the destination, In addition to enabling the DMA interrupts, Interrupt
enabled by CHDHIE (DCHxINT<20>). Service Routines (ISRs) are required for each different
interrupt vector used. See Example 10-6 and
Example 10-7.
Note: It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.

PIC32MX3XX/4XX
EXAMPLE 10-6: DMA INITIALIZATION WITH INTERRUPTS
/*
The following code example illustrates a DMA channel 0 interrupt configuration.
When the DMA channel 0 interrupt is generated, the CPU will jump to the vector assigned to DMA0
interrupt.
*/


DCH0ECON=0; // no start or stop irq’s, no pattern match

DCH0SSA=0x1d010000; // transfer source physical address
DCH0SSIZ=0; // source size 256 bytes
DCH0DSIZ=0; // destination size 256 bytes
DCH0CSIZ=0; // 256 bytes transferred pe event

DCH0INTSET=0x00090000; // enable Block Complete and error interrupts
IPC9CLR=0x0000001f; // clear the DMA channel 0 priority and subpriority

IPC9SET=0x00000016; // set IPL 5, subpriority 2

// will get an interrupt when the block transfer is done

// or when error occurred
EXAMPLE 10-7: DMA CHANNEL 0 ISR

/*
The following code example demonstrates a simple Interrupt Service Routine for DMA channel 0
interrupts. The user’s code at this vector should perform any application specific operations
and must clear the DMA0 interrupt flags before exiting.
*/
void __ISR(_DMA_0_VECTOR, ipl5) __DMA0Interrupt(void)

{
int dmaFlags=DCH0INT&0xff; // read the interrupt flags
// perform application specific operations in response to any interrupt flag set
DCH0INTCLR=0x000000ff; // clear the DMA channel interrupt flags

IFS1CLR = 0x00010000; // Be sure to clear the DMA0 interrupt flags
// before exiting the service routine.
}
Note: The DMA ISR code example shows

MPLAB® C32 C compiler specific syntax.
Refer to your compiler manual regarding
support for ISRs.

PIC32MX3XX/4XX
10.11 I/O Pin Control
The DMA controller module does not use any I/O pins.

PIC32MX3XX/4XX
11.0 USB ON-THE-GO The PIC32MX USB module includes the following
features:
Note: This data sheet summarizes the features of • USB Full-Speed Support for Host and Device
• Low-Speed Host Support
ence source. Refer to the “PIC32MX Family • USB On-The-Go (OTG) Support
Reference Manual” (DS61132) for a • Integrated Signaling Resistors
detailed description of this peripheral. • Integrated Analog Comparators for VBUS
Monitoring
The Universal Serial Bus (USB) module contains ana-
• Integrated USB Transceiver
log and digital components to provide a USB 2.0 full-
speed and low-speed embedded host, full-speed • Transaction Handshaking Performed by
device, or OTG implementation with a minimum of Hardware
external components. This module in Host mode is • Endpoint Buffering Anywhere in System RAM
intended for use as an embedded host and therefore • Integrated DMA Controller to Access System
does not implement a UHCI or OHCI controller. RAM and Flash
The USB module consists of the clock generator, the Note: IMPORTANT: The implementation and
USB voltage comparators, the transceiver, the Serial use of the USB specifications, as well as
Interface Engine (SIE), a dedicated USB DMA control- other third-party specifications or technol-
ler, pull-up and pull-down resistors, and the register ogies, may require licensing; including,
interface. A block diagram of the PIC32MX USB OTG but not limited to, USB Implementers
module is presented in Figure 11-1. Forum, Inc. (also referred to as USB-IF).
The clock generator provides the 48 MHz clock The user is fully responsible for investigat-
required for USB full-speed and low-speed communi- ing and satisfying any applicable licensing
cation. The voltage comparators monitor the voltage on obligations.
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers, and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The inte-
grated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.

PIC32MX3XX/4XX
FIGURE 11-1: PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM
USBEN
FRC
USB Suspend Oscillator
8 MHz Typical
CPU Clock Not POSC
Sleep TUN<5:0>(4)
Primary Oscillator
(POSC)
UFIN(5)
Div x PLL Div 2
OSC1 UFRCEN(3)
FUPLLIDIV(6) FUPLLEN(6)
USB Suspend To Clock Generator for Core and Peripherals
OSC2 Sleep or Idle
(PB out)(1)
USB Module
USB
SRP Charge Voltage
VBUS Comparators
SRP Discharge
48 MHz USB Clock(7)
Full Speed Pull-up
D+(2)
Registers
and
Control
Host Pull-down Interface
SIE
Transceiver
Low Speed Pull-up
D-(2)
DMA System
controller RAM
Host Pull-down
ID Pull-up
ID(8)
VBUSON(8)
VUSB Transceiver Power 3.3V
Note 1: PB clock is only available on this pin for select EC modes.

2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL UFIN requirements: 4 MHz <= FIN <= 5 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB module is disabled.

PIC32MX3XX/4XX
11.1 Control Registers 11.1.7 U1IE REGISTER
The USB module includes the following Special Func- U1IE (Register 11-7) values provide gating of the vari-
tion Registers (SFRs): ous interrupt signals onto the USB interrupt signal.
These values do not interact with the USB module.
• U1OTGIR: USB OTG Interrupt Flag Register Setting any of these bits enables the corresponding
• U1OTGIE: USB OTG Interrupt Enable Register interrupt source in the U1IR register.
• U1OTGSTAT: USB Comparator and Pin Status
Register 11.1.8 U1EIR REGISTER
• U1OTGCON: USB Resistor and Pin Control U1EIR (Register 11-8) contains information on pending
Register error interrupt values. Once an interrupt bit is set, it can
• U1PWRC: USB Power Control Register be cleared by writing a ‘1’ to the corresponding bit.
• U1IR: USB Pending Interrupt Register
11.1.9 U1EIE REGISTER
• U1IE: USB Interrupt Enable Register
• U1EIR: USB Pending Error Interrupt Register U1EIE (Register 11-9) values provide gating of the var-
ious interrupt signals onto the USB interrupt signal.
• U1EIE: USB Interrupt Enable Register
These values do not interact with the USB module. Set-
• U1STAT: USB Status FIFO Register ting any of these bits enables the respective interrupt
• U1CON: USB Module Control Register source in the U1EIR register if UERR is also set in the
• U1ADDR: USB Address Register U1IE register.
• U1FRMH and U1FRML: USB Frame Count
Registers 11.1.10 U1STAT REGISTER
• U1TOK: USB Host Control Register U1STAT (Register 11-10) is a 16-deep First In, First
• U1SOF: USB SOF Counter Register Out (FIFO) register. It is read-only by the CPU and
read/write by the USB module. U1STAT is only valid
• U1BDTP1, U1BDTP2, and U1BDTP3: USB Buffer
when the U1IR<TRNIF> bit is set.
Descriptor Table Pointer Register
• U1CNFG1: USB Debug and Idle Register 11.1.11 U1CON REGISTER
• U1EP0-U1EP15: USB Endpoint Control Registers U1CON (Register 11-11) provides miscellaneous
control and information about the module.
11.1.1 U1OTGIR REGISTER
U1OTGIR (Register 11-1) records changes on the ID, 11.1.12 U1ADDR REGISTER
data and VBUS pins, enabling software to determine U1ADDR (Register 11-12) is a read/write register from
which event caused an interrupt. The interrupt bits are the CPU side and read-only from the USB module side.
cleared by writing a ‘1’ to the corresponding interrupt. Although the register values affect the settings of the
USB module, the content of the registers does not
11.1.2 U1OTGIE REGISTER
change during access.
U1OTGIE (Register 11-2) enables the corresponding
In Device mode, this address defines the USB device
interrupt Status bits defined in the U1OTGIR register to
address as assigned by the host during the SETUP
generate an interrupt.
phase. The firmware writes the address in response to
the SETUP request. The address is automatically reset
11.1.3 U1OTGSTAT REGISTER
when a USB bus Reset is detected. In Host mode, the
U1OTGSTAT (Register 11-3) provides access to the module transmits the address provided in this register
status of the VBUS voltage comparators and the with the corresponding token packet. This allows the
debounced status of the ID pin. USB module to uniquely address the connected
device.
11.1.4 U1OTGCON REGISTER
U1OTGCON (Register 11-4) controls the operation of 11.1.13 U1FRMH AND U1FRML REGISTERS
the VBUS pin, and the pull-up and pull-down resistors. U1FRMH and U1FRML (Register 11-13 and
Register 11-14) are read-only registers. The frame
11.1.5 U1PWRC REGISTER number is formed by concatenating the two 8-bit regis-
U1PWRC (Register 11-5) controls the power-saving ters. The high-order byte is in the U1FRMH register,
modes, as well as the module enable/disable control. and the low-order byte is in U1FRML.
11.1.6 U1IR REGISTER

U1IR (Register 11-6) contains information on pending
interrupts. Once an interrupt bit is set, it can be cleared
by writing a ‘1’ to the corresponding bit.

PIC32MX3XX/4XX
11.1.14 U1TOK REGISTER 11.1.19 ASSOCIATED REGISTERS
U1TOK (Register 11-15) is a read/write register The following registers are not part of the USB module
required when the module operates as a host. It is used but are associated with module operation.
to specify the token type, PID<3:0> (Packet ID), and • IEC1: Interrupt Enable Control Register
the endpoint, EP<3:0>, being addressed by the host (Register 11-22)
processor. Writing to this register triggers a host
• IFS1: Interrupt Flag Status Register
transaction.
(Register 8-5)
11.1.15 U1SOF REGISTER • DEVCFG2: Device Configuration Word 2
(Register 27-3)
U1SOF (Register 11-16) threshold is a read/write reg-
ister that contains the count bits of the Start-of-Frame • OSCCON: Oscillator Control Register
(SOF) threshold value, and are used in Host mode only. (Register 4-1)
To prevent colliding a packet data with the SOF token 11.1.20 CLEARING USB OTG INTERRUPTS
that is sent every 1 ms, the USB module will not send
Unlike other device-level interrupts, the USB OTG
any new transactions within the last U1SOF byte times.
interrupt status flags are not freely writable in software.
The USB module will complete any transactions that
All USB OTG flag bits are implemented as hardware-
are in progress. In Host mode, the SOF interrupt occurs
set bits. These bits can only be cleared in software by
when this threshold is reached, not when the SOF
writing a ‘1’ to their locations. Writing a ‘0’ to a flag bit
occurs. In Device mode, the interrupt occurs when a
has no effect.
SOF is received. Transactions started within the SOF
threshold are held by the USB module until after the Note: Throughout this section, a bit that can only
SOF token is sent. be cleared by writing a ‘1’ to its location is
referred to as “Write ‘1’ to clear bit”. In reg-
11.1.16 U1BDTP1, U1BDTP2 AND U1BDTP3 ister descriptions, this function is indicated
REGISTERS by the descriptor ‘K’.
These registers (Register 11-17, Register 11-18 and
Register 11-19) are read/write registers that define the
upper 23 bits of the 32-bit base address of the Buffer
Descriptor Table (BDT) in the system memory. The
BDT is forced to be 512 byte-aligned. This register
allows relocation of the BDT in real time.
11.1.17 U1CNFG1 REGISTER

U1CNFG1 (Register 11-20) is a read/write register that
controls the Debug and Idle behavior of the module.
The register must be preprogrammed prior to enabling
the module.
11.1.18 U1EP0-U1EP15 REGISTERS

These registers control the behavior of the correspond-
ing endpoint.

PIC32MX3XX/4XX
TABLE 11-1: USB REGISTER SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_5040 U1OTGIR 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF
BF88_5050 U1OTGIE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE
BF88_5060 U1OTGSTAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 ID — LSTATE — SESVD SESEND — VBUSVD
BF88_5070 U1OTGCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS
BF88_5080 U1PWRC 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 UACTPND — — USLPGRD — — USUSPEND USBPWR
BF88_5200 U1IR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 URSTIF
STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF
DETACHIF
BF88_5210 U1IE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 URSTIE
STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE
DETACHIE
BF88_5220 U1EIR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CRC5EF
BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF PIDEF
EOFEF
BF88_5230 U1EIE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CRC5EE
BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE
EOFEE
BF88_5240 U1STAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 ENDPT<3:0> DIR PPBI — —

PIC32MX3XX/4XX
TABLE 11-1: USB REGISTER SUMMARY (CONTINUED)
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_5250 U1CON 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 PKTDIS USBEN
JSTATE SE0 USBRST HOSTEN RESUME PPBRST
TOKBUSY SOFEN
BF88_5260 U1ADDR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 LSPDEN DEVADDR<6:0>
BF88_5270 U1BDTP1 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 BDTPTRL<15:9> —
BF88_5280 U1FRML 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 FRML<7:0>
BF88_5290 U1FRMH 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 — — — — — FRMH<10:8>
BF88_52A0 U1TOK 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 PID<3:0> EP<3:0>
BF88_52B0 U1SOF 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 CNT<7:0>
BF88_52C0 U1BDTP2 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 BDTPTRH<23:16>
BF88_52D0 U1BDTP3 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 BDTPTRU<31:24>
BF88_52E0 U1CNFG1 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 UTEYE UOEMON USBFRZ USBSIDL — — — —
BF88_5300 U1EP0 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_5310 U1EP1 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
BF88_5320 U1EP2 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_5330 U1EP3 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_5340 U1EP4 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_5350 U1EP5 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_5360 U1EP6 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_5370 U1EP7 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_5380 U1EP8 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_5390 U1EP9 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_53A0 U1EP10 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_53B0 U1EP11 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_53C0 U1EP12 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_53D0 U1EP13 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_53E0 U1EP14 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
BF88_53F0 U1EP15 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
TABLE 11-2: USB INTERRUPT REGISTER SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1140 IPC11 15:8 — — — USBIP<2:0> USBIS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the USB peripheral. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a detailed description of these registers.
TABLE 11-3: OSCILLATOR CONFIGURATION(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_F000 OSCCON 7:0 CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN
BFC0_2FF4 DEVCFG2 15:8 FUPLLEN(2) — — — — FUPLLIDIV<2:0>(2)
Note 1: This summary table contains partial register definitions that only pertain to the USB peripheral. Refer to the “PIC32MX Family
Note 2: FUPLLEN and FPLLODIV<2:0> are only available on PIC32MX4XX family variants.

PIC32MX3XX/4XX
REGISTER 11-1: U1OTGIR: USB OTG INTERRUPT FLAG REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 r-x R/W/K-0

IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF
bit 7 bit 0
Legend:
U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (‘0’, ‘1’, x = unknown)

bit 7 IDIF: ID State Change Indicator bit
Write a ‘1’ to this bit to clear the interrupt.
1 = Change in ID state detected
0 = No change in ID state detected
bit 6 T1MSECIF: 1 Millisecond Timer bit
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5 LSTATEIF: Line State Stable Indicator bit
1 = USB line state has been stable for 1 ms, but different from last time
0 = USB line state has not been stable for 1 ms
bit 4 ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+, D-, ID, or VBUS pins has caused the device to wake-up
0 = Activity has not been detected
bit 3 SESVDIF: Session Valid Change Indicator bit
1 = VBUS voltage has dropped below the session end level
0 = VBUS voltage has not dropped below the session end level
bit 2 SESENDIF: B-Device VBUS Change Indicator bit
1 = A change on the session end input was detected
0 = No change on the session end input was detected

PIC32MX3XX/4XX
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 r-x R/W/K-0

IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF
bit 7 bit 0
Legend:

bit 7 IDIF: ID State Change Indicator bit
1 = Change in ID state detected
0 = No change in ID state detected
bit 6 T1MSECIF: 1 Millisecond Timer bit
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5 LSTATEIF: Line State Stable Indicator bit
1 = USB line state has been stable for 1 ms, but different from last time
0 = USB line state has not been stable for 1 ms
bit 4 ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+, D-, ID, or VBUS pins has caused the device to wake-up
0 = Activity has not been detected
bit 3 SESVDIF: Session Valid Change Indicator bit
1 = VBUS voltage has dropped below the session end level
0 = VBUS voltage has not dropped below the session end level
bit 2 SESENDIF: B-Device VBUS Change Indicator bit
1 = A change on the session end input was detected
0 = No change on the session end input was detected

PIC32MX3XX/4XX
bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit
1 = Change on the session valid input detected
0 = No change on the session valid input detected

PIC32MX3XX/4XX
REGISTER 11-2: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE
bit 7 bit 0
Legend:

bit 7 IDIE: ID Interrupt Enable bit
1 = ID interrupt enabled
0 = ID interrupt disabled
bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt enabled
0 = 1 millisecond timer interrupt disabled
bit 5 LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt enabled
0 = Line state interrupt disabled
bit 4 ACTVIE: Bus Activity Interrupt Enable bit
1 = ACTIVITY interrupt enabled
0 = ACTIVITY interrupt disabled
bit 3 SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt enabled
0 = Session valid interrupt disabled
bit 2 SESENDIE: B-Session End Interrupt Enable bit
1 = B-session end interrupt enabled
0 = B-session end interrupt disabled
bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit
1 = A-VBUS valid interrupt enabled
0 = A-VBUS valid interrupt disabled

PIC32MX3XX/4XX
REGISTER 11-3: U1OTGSTAT: USB OTG STATUS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-0 r-x R-0 r-x R-0 R-0 r-x R-0

ID — LSTATE — SESVD SESEND — VBUSVD
bit 7 bit 0
Legend:

bit 7 ID: ID Pin State Indicator bit
1 = No cable is attached or a type B cable has been plugged into the USB receptacle
0 = A type A OTG cable has been plugged into the USB receptacle
bit 5 LSTATE: Line State Stable Indicator bit
1 = USB line state (U1CON[SE0] and U1CON[JSTATE]) has been stable for the previous 1 ms
0 = USB line state (U1CON[SE0] and U1CON[JSTATE]) has not been stable for the previous 1 ms
bit 3 SESVD: Session Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A or B device
0 = VBUS voltage is below Session Valid on the A or B device
bit 2 SESEND: B-Session End Indicator bit
1 = VBUS voltage is below Session Valid on the B device
0 = VBUS voltage is above Session Valid on the B device
bit 0 VBUSVD: A-VBUS Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A device
0 = VBUS voltage is below Session Valid on the A device

PIC32MX3XX/4XX
REGISTER 11-4: U1OTGCON: USB OTG CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS
bit 7 bit 0
Legend:

bit 7 DPPULUP: D+ Pull-Up Enable bit
1 = D+ data line pull-up resistor is enabled
0 = D+ data line pull-up resistor is disabled
bit 6 DMPULUP: D- Pull-Up Enable bit
1 = D- data line pull-up resistor is enabled
0 = D- data line pull-up resistor is disabled
bit 5 DPPULDWN: D+ Pull-Down Enable bit
1 = D+ data line pull-down resistor is enabled
0 = D+ data line pull-down resistor is disabled
bit 4 DMPULDWN: D- Pull-Down Enable bit
1 = D- data line pull-down resistor is enabled
0 = D- data line pull-down resistor is disabled
bit 3 VBUSON: VBUS Power-on bit
1 = VBUS line is powered
0 = VBUS line is not powered
bit 2 OTGEN: OTG Functionality Enable bit
1 = DPPULUP, DMPULUP, DPPULDWN, and DMPULDWN bits are under software control
0 = DPPULUP, DMPULUP, DPPULDWN, and DMPULDWN bits are under USB hardware control
bit 1 VBUSCHG: VBUS Charge Enable bit
1 = VBUS line is charged through a pull-up resistor
0 = VBUS line is not charged through a resistor
bit 0 VBUSDIS: VBUS Discharge Enable bit
1 = VBUS line is discharged through a pull-down resistor
0 = VBUS line is not discharged through a resistor

PIC32MX3XX/4XX
REGISTER 11-5: U1PWRC: USB POWER CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-0 r-x r-x R/W-0 r-x r-x R/W-0 R/W-0

UACTPND — — USLPGRD — — USUSPEND USBPWR
bit 7 bit 0
Legend:

bit 7 UACTPND: USB Suspend Mode bit
1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet
0 = An interrupt is not pending
bit 4 USLPGRD: USB Sleep Entry Guard bit
1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending
0 = USB module does not block Sleep entry
bit 1 USUSPEND: USB Suspend Mode bit
1 = USB module is placed in suspend mode
(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
0 = USB module operates normally.
bit 0 USBPWR: USB Operation Enable bit
1 = USB module is turned on
0 = USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut-down to reduce
power consumption.)

PIC32MX3XX/4XX
REGISTER 11-6: U1IR: USB INTERRUPT REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/K-0 R/W/K-0

URSTIF(5)
STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF
DETACHIF(6)
bit 7 bit 0
Legend:
U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (0, 1, x = unknown)

bit 7 STALLIF: STALL Handshake Interrupt bit
1 = In host mode a STALL handshake was received during the handshake phase of the transaction
In device mode a STALL handshake was transmitted during the handshake phase of the
transaction
0 = STALL handshake has not been sent
bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1)
1 = Peripheral attachment was detected by the USB module
0 = Peripheral attachment was not detected
bit 5 RESUMEIF: Resume Interrupt bit(2)
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
bit 4 IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Token Processing Complete Interrupt bit(3)
1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint
information
0 = Processing of current token not complete

PIC32MX3XX/4XX
REGISTER 11-6: U1IR: USB INTERRUPT REGISTER (CONTINUED)
bit 2 SOFIF: SOF Token Interrupt bit
1 = SOF token received by the peripheral or the SOF threshold reached by the host
0 = SOF token was not received nor threshold reached
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = Unmasked error condition has occurred
0 = Unmasked error condition has not occurred
bit 0 URSTIF: USB Reset Interrupt bit (Device mode)
1 = Valid USB Reset has occurred
0 = No USB Reset has occurred
DETACHIF: USB Detach Interrupt bit (Host mode)
1 = Peripheral detachment was detected by the USB module
0 = Peripheral detachment was not detected
Note 1: This bit is valid only if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
2: When not in Suspend mode, this interrupt should be disabled.
3: Clearing this bit will cause the STAT FIFO to advance.
4: Only error conditions enabled through the U1EIE register will set this bit.
5: Device mode.
6: Host mode.

PIC32MX3XX/4XX
REGISTER 11-7: U1IE: USB INTERRUPT ENABLE REGISTER(1)
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

URSTIE(2)
STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE
DETACHIE(3)
bit 7 bit 0
Legend:

bit 7 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 6 ATTACHIE: ATTACH Interrupt Enable bit
1 = ATTACH interrupt enabled
0 = ATTACH interrupt disabled
bit 5 RESUMEIE: RESUME Interrupt Enable bit
1 = RESUME interrupt enabled
0 = RESUME interrupt disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = IDLE interrupt enabled
0 = IDLE interrupt disabled
bit 3 TRNIE: Token Processing Complete Interrupt Enable bit
1 = TRNIF interrupt enabled
0 = TRNIF interrupt disabled
bit 2 SOFIE: SOF Token Interrupt Enable bit
1 = SOFIF interrupt enabled
0 = SOFIF interrupt disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB Error interrupt enabled
0 = USB Error interrupt disabled

PIC32MX3XX/4XX
REGISTER 11-7: U1IE: USB INTERRUPT ENABLE REGISTER(1) (CONTINUED)
bit 0 URSTIE: USB Reset Interrupt Enable bit (Device mode)
1 = URSTIF interrupt enabled
0 = URSTIF interrupt disabled
DETACHIE: USB Detach Interrupt Enable bit (Host Mode)
1 = DATTCHIF interrupt enabled
0 = DATTCHIF interrupt disabled
Note 1: For an interrupt to propagate to the U1IR bit USBIF(IFS1<25>), the UERRIE bit (U1IE<1>) must be set.
2: Device mode.
3: Host mode.

PIC32MX3XX/4XX
REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W/K-0 R/W-0 R/W-0

CRC5EF(4)
BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF PIDEF
EOFEF(5)
bit 7 bit 0
Legend:

bit 7 BTSEF: Bit Stuff Error Flag bit
1 = Packet rejected due to bit stuff error
0 = Packet accepted
bit 6 BMXEF: Bus Matrix Error Flag bit
1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry,
is invalid.
0 = No address error
bit 5 DMAEF: DMA Error Flag bit(1)
1 = USB DMA error condition detected
0 = No DMA error
bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2)
1 = Bus turnaround time-out has occurred
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = Data field received is not an integral number of bytes
0 = Data field received is an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = Data packet rejected due to CRC16 error
0 = Data packet accepted

PIC32MX3XX/4XX
REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER
bit 1 CRC5EF: CRC5 Host Error Flag bit(3) (Device Mode)
1 = Token packet rejected due to CRC5 error
0 = Token packet accepted
EOFEF: EOF Error Flag bit (Host Mode)
1 = EOF error condition detected
0 = No EOF error condition
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed
Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16 bit-times of Idle from the previous (End-of-Packet) EOP
has elapsed.
3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
4: Device mode.
5: Host mode.

PIC32MX3XX/4XX
REGISTER 11-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER(1)
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

CRC5EE(2)
BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE
EOFEE(3)
bit 7 bit 0
Legend:

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit
1 = BTSEF interrupt enabled
0 = BTSEF interrupt disabled
bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit
1 = BMXEF interrupt enabled
0 = BMXEF interrupt disabled
bit 5 DMAEE: DMA Error Interrupt Enable bit
1 = DMAEF interrupt enabled
0 = DMAEF interrupt disabled
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = BTOEF interrupt enabled
0 = BTOEF interrupt disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = DFN8EF interrupt enabled
0 = DFN8EF interrupt disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16EF interrupt enabled
0 = CRC16EF interrupt disabled
Note 1: For an error interrupt to propagate to USBIF(IFS1<25>), the UERRIE bit (U1IE<1> must be set).
2: Device mode.
3: Host mode.

PIC32MX3XX/4XX
REGISTER 11-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER(1) (CONTINUED)
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit (Device Mode)
1 = CRC5EF interrupt enabled
0 = CRC5EF interrupt disabled
EOFEE: EOF Error Interrupt Enable bit (Host Mode)
1 = EOF interrupt enabled
0 = EOF interrupt disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PIDEF interrupt enabled
0 = PIDEF interrupt disabled
Note 1: For an error interrupt to propagate to USBIF(IFS1<25>), the UERRIE bit (U1IE<1> must be set).
2: Device mode.
3: Host mode.

PIC32MX3XX/4XX
REGISTER 11-10: U1STAT: USB STATUS FIFO REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-x R-x R-x R-x R-x R-x r-x r-x

ENDPT<3:0> DIR PPBI — —
bit 7 bit 0
Legend:

bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits
(Represents the number of the BDT, updated by the last USB transfer.)
1111 = Endpoint 15
1110 = Endpoint 14
....
0001 = Endpoint 1
0000 = Endpoint 0
bit 3 DIR: Last BD Direction Indicator bit
1 = Last transaction was a transmit transfer (TX)
0 = Last transaction was a receive transfer (RX)
bit 2 PPBI: Ping-Pong BD Pointer Indicator bit
1 = The last transaction was to the ODD BD bank
0 = The last transaction was to the EVEN BD bank
Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only
valid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in register is
invalid when U1IR<TRNIF> = 0.

PIC32MX3XX/4XX
REGISTER 11-11: U1CON: USB MODULE CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(4)
PKTDIS USBEN(4)
JSTATE SE0 USBRST HOSTEN RESUME PPBRST
TOKBUSY(5) SOFEN(5)
bit 7 bit 0
Legend:

bit 7 JSTATE: Live Differential Receiver JSTATE flag bit
1 = JSTATE detected on the USB
0 = No JSTATE detected
bit 6 SE0: Live Single-Ended Zero flag bit
1 = Single-Ended Zero detected on the USB
0 = No Single-Ended Zero detected
bit 5 PKTDIS: Packet Transfer Disable bit (Device mode)
1 = Token and packet processing disabled (set upon SETUP token received)
0 = Token and packet processing enabled
TOKBUSY: Token Busy Indicator bit(1) (Host mode)
1 = Token being executed by the USB module
0 = No token being executed
bit 4 USBRST: Module Reset bit (Host mode only)
1 = USB reset generated
0 = USB reset terminated
bit 3 HOSTEN: Host Mode Enable bit(2)
1 = USB host capability enabled
0 = USB host capability disabled
bit 2 RESUME: RESUME Signaling Enable bit(3)
1 = RESUME signaling activated
0 = RESUME signaling disabled
bit 1 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Even/Odd buffer pointers to the EVEN BD banks
0 = Even/Odd buffer pointers not being Reset

PIC32MX3XX/4XX
REGISTER 11-11: U1CON: USB MODULE CONTROL REGISTER (CONTINUED)
bit 0 USBEN: USB Module Enable bit (Device mode)
1 = USB module and supporting circuitry enabled
0 = USB module and supporting circuitry disabled
SOFEN: SOF Enable bit (Host mode)
1 = SOF token sent every 1 ms
0 = SOF token disabled
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register, see
Register 11-15.
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then
clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the
RESUME signaling when this bit is cleared.
4: Device mode.
5: Host mode.

PIC32MX3XX/4XX
REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

LSPDEN DEVADDR<6:0>
bit 7 bit 0
Legend:

bit 7 LSPDEN: Low-Speed Enable Indicator bit
1 = Next token command to be executed at Low Speed
0 = Next token command to be executed at Full Speed
bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits

PIC32MX3XX/4XX
REGISTER 11-13: U1FRML: USB FRAME COUNT LOW REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FRML<7:0>
bit 7 bit 0
Legend:

bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.

PIC32MX3XX/4XX
REGISTER 11-14: U1FRMH: USB FRAME COUNT HIGH REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
r-x r-x r-x r-x r-x R-0 R-0 R-0

— — — — — FRMH<2:0>
bit 7 bit 0
Legend:

bit 2-0 FRMH<2:0>: The Upper 3 Bits of the Frame Numbers
The register bits are updated with the current frame number whenever a SOF TOKEN is received.

PIC32MX3XX/4XX
REGISTER 11-15: U1TOK: USB HOST CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

PID<3:0> EP<3:0>
bit 7 bit 0
Legend:

bit 7-4 PID<3:0>: Token Type Indicator bits(1)
0001 = OUT (TX) token type transaction
1001 = IN (RX) token type transaction
1101 = SETUP (TX) token type transaction
bit 3-0 EP<3:0>: Token Command Endpoint Address bits
The four-bit value must specify a valid endpoint.
Note 1: All other values are reserved and must not be used.

PIC32MX3XX/4XX
REGISTER 11-16: U1SOF: USB SOF COUNTER REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x

CNT<7:0>
bit 7 bit 0
Legend:

bit 7-0 CNT<7:0>: SOF Threshold Value bits
Typical values of the threshold are:
0100 1010 = 64-byte packet
0010 1010 = 32-byte packet
0001 1010 = 16-byte packet
0001 0010 = 8-byte packet

PIC32MX3XX/4XX
REGISTER 11-17: U1BDTP1: USB BDT REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x

BDTPTRL<6:0> —
bit 7 bit 0
Legend:

bit 7-1 BDTPTRL<6:0>: BDT Base Address bits
This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the BDT’s
starting location in the system memory.
The 32-bit BDT base address is 512-byte aligned.

PIC32MX3XX/4XX
REGISTER 11-18: U1BDTP2: USB BDT PAGE 2 REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

BDTPTRH<7:0>
bit 7 bit 0
Legend:

bit 7-0 BDTPTRH<7:30>: BDT Base Address bits

PIC32MX3XX/4XX
REGISTER 11-19: U1BDTP3: USB BDT PAGE 3 REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

BDTPTRU<7:0>
bit 7 bit 0
Legend:

bit 7-0 BDTPTRU<7:0>: BDT Base Address bits

PIC32MX3XX/4XX
REGISTER 11-20: U1CNFG1: USB DEBUG AND IDLE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x

UTEYE UOEMON USBFRZ USBSIDL — — — —
bit 7 bit 0
Legend:

bit 7 UTEYE: USB Eye-Pattern Test Enable bit
1 = Eye-Pattern Test enabled
0 = Eye-Pattern Test disabled
bit 6 UOEMON: USB OE Monitor Enable bit
1 = OE signal active; it indicates intervals during which the D+/D- lines are driving
0 = OE signal inactive
bit 5 USBFRZ: Freeze in DEBUG Mode bit
1 = When emulator is in DEBUG mode, module freezes operation
0 = When emulator is in DEBUG mode, module continues operation
Note: USBFRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode.
bit 4 USBSIDL: Stop in IDLE Mode bit
1 = Discontinue module operation when device enters IDLE mode
0 = Continue module operation in IDLE mode

PIC32MX3XX/4XX
REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
bit 7 bit 0
Legend:

bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1 = Direct connection to a low-speed device enabled
0 = Direct connection to a low-speed device disabled; hub required with PRE_PID
bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
1 = Retry NAK’d transactions disabled
0 = Retry NAK’d transactions enabled; retry done in hardware
bit 4 EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed
0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
Otherwise, this bit is ignored.
bit 3 EPRXEN: Endpoint Receive Enable bit
1 = Endpoint n receive enabled
0 = Endpoint n receive disabled
bit 2 EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint n transmit enabled
0 = Endpoint n transmit disabled
bit 1 EPSTALL: Endpoint Stall Status bit
1 = Endpoint n was stalled
0 = Endpoint n was not stalled
bit 0 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint Handshake enabled
0 = Endpoint Handshake disabled (typically used for isochronous endpoints)

PIC32MX3XX/4XX
REGISTER 11-22: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1(1)
bit 31 bit 24
r r r r R/W-0 R/W-0 R/W-0 R/W-0

bit 23 bit 16

bit 15 bit 8

bit 7 bit 0
Legend:

bit 25 USBIE: USB Interrupt Enable bit
Note 1: Register is cleared on all forms of Reset.
Shaded bit names in this Interrupt register control other PIC32MX3XX/4XX peripherals and are not related
to USB.

PIC32MX3XX/4XX
11.2 Operation 11.4.1.1 USB Standard Host
This section contains a brief overview of USB opera- In USB Standard Host mode, the following features and
tion, followed by PIC32MX USB module implementa- requirements are relevant:
tion specifics, and module initialization requirements. • Large variety of devices are supported
Note: A good understanding of USB can be • Supports all USB transfer types
gained from documents that are available • USB hubs are supported (allows connection of
on the USB implementers web site. In par- multiple devices simultaneously)
ticular, refer to the “Universal Serial Bus • Device drivers can be updated to support new
Specification, Revision 2.0” devices
(http://www.usb.org/developers/docs/). • Type ‘A’ receptacle is used for each port
• Each port must be able to deliver a minimum of
11.3 USB 2.0 Operation Overview 100 mA for a configured or unconfigured device,
and optionally, up to 500 mA for a configured
USB is an asynchronous serial interface with a tiered
device
star configuration. USB is implemented as a mas-
ter/slave configuration. On a given bus, there can be • Full-speed and low-speed protocols must be sup-
multiple (up to 127) slaves (devices), but there is only ported (high-speed can be supported).
one master (host). Note: This mode is not supported by the
There are three possible module modes of operation: PIC32MX family.
Host, Device, and OTG Dual Role.
11.4.1.2 Embedded Host
11.4 Modes of Operation In Embedded Host mode, the following features and
requirements are relevant:
The following USB implementation modes are
described in this overview: • Only supports a specific list of devices, referred to
as a Targeted Peripheral List (TPL)
• Host mode
• Only required to support those transfer types that
- USB Standard Host mode – the USB imple- are required by devices in the TPL
mentation that is typically used for a personal
• USB hub support is optional
computer
• Device drivers are not required to be updateable
- Embedded Host mode – the USB implemen-
tation that is typically used for a • Type ‘A’ receptacle is used for each port
microcontroller • Only those speeds required by devices in the TLP
• Device mode – the USB implementation that is must be supported
typically used for a peripheral such as a thumb- • Each port must be able to deliver a minimum of
drive, keyboard, or mouse 100 mA for a configured or unconfigured device,
• OTG Dual Role mode – the USB implementation and optionally, up to 500 mA for a configured
in which an application may dynamically switch its device
role as either host or device
11.4.2 DEVICE MODE
11.4.1 HOST MODE USB devices accept commands and data from the host
The host is the master in a USB system and is respon- and respond to requests for data. USB devices perform
sible for identifying all devices connected to it (enumer- peripheral functions, e.g., a mouse or other I/O, or data
ation), initiating all transfers, allocating bus bandwidth storage.
and supplying power to any bus-powered USB devices The following characteristics generally describe a USB
connected directly to it. device:
• Functionality may be class- or vendor-specific
• Draws 100 mA or less from the bus before config-
uration
• Can draw up to 500 mA from the bus after suc-
cessful negotiation with the host
• Can support low-speed, full-speed, or high-speed
protocol (high-speed support requires implemen-
tation of full-speed protocol to enumerate)
• Supports control and data transfers as required
for implementation

PIC32MX3XX/4XX
• Optionally supports Session Request Protocol requirements, but can draw up to 500 mA after
(SRP) successful negotiation with the host
• Can be bus-powered or self-powered • A single micro-AB receptacle is used
• Must support full-speed protocol (support of low-
11.4.3 OTG DUAL ROLE speed and/or high-speed protocol is optional
The OTG dual role device supports both USB host and • Supports control transfers, and supports data
device functionality. OTG dual role devices use a transfers as they are required for implementation
micro-AB receptacle. This allows a micro-A or a micro- • Supports both forms of SRP – VBUS pulsing and
B plug to be attached. Both the micro-A and micro-B data-line pulsing
plugs have an additional pin, the ID pin, to signify which
• Supports HNP
plug type was connected. The plug type connected to
the receptacle, micro-A or micro-B, determines the B-device does not supply VBUS power, even if the roles
default role of the OTG device, host or device. An OTG are swapped using HNP.
device will perform the role of a host when a micro-A Note: Dual role devices that do not support full
plug is detected. When a micro-B plug is detected, the OTG functionality are possible using mul-
role of a USB device is performed. tiple USB receptacles. However, there
When an OTG device is directly connected to another may be special requirements if those
OTG device using an OTG cable (micro-A to micro-B), devices are to be made USB compliant.
Host Negotiation Protocol (HNP) can be used to swap Refer to the USB implementer’s forum for
the roles of host and USB device between the two with- the most current details.
out disconnecting and reconnecting the cable. To differ-
•
entiate between the two OTG devices, the term “A-
device” refers to the device connected to the micro-A 11.4.4 PHYSICAL BUS INTERFACE
plug and “B-device” refers to the device connected to
the micro-B plug. 11.4.4.1 Bus Speed Selection
11.4.3.1 A-Device, the Default Host The USB specification defines full-speed operation as
12 Mb/s and low speed operation as 1.5 Mb/s. A data
In OTG dual role, operating as a host, the following fea- line pull-up resistor is used to identify a device as full
tures and requirements describe an A-device: speed or low speed. For full-speed operation, the D+
• Supports the devices on the TPL (class support is line is pulled up; for low-speed operation, the D- line is
not allowed) pulled up.
• Required to support those transaction types that
are required by devices in the TPL 11.4.4.2 VBUS Control
• USB hub support is optional VBUS is the 5V USB power supplied by the host or a
• Device drivers are not required to be updateable hub to operate bus-powered devices. The need for
VBUS control depends on the role of the application. If
• A single micro-AB receptacle is used
VBUS power must be enabled and disabled, the control
• Full-speed protocol must be supported (high- must be managed by firmware.
speed and/or low-speed protocol can be
supported) The following list details the VBUS requirements:
• USB port must be able to deliver a minimum of 8 • Standard host typically supplies power to the bus
mA for a configured or unconfigured device, and at all times.
optionally, up to 500 mA for a configured device • Host may switch off VBUS to conserve power
• Supports HNP; the host can switch roles to • USB device never powers the bus – VBUS pulsing
become a device may be supported as part of the SRP.
• Supports at least one form of SRP • OTG A-device supplies power to the bus, and
• A-device supplies VBUS power when the bus is typically turns off VBUS to conserve power.
powered, even if the roles are swapped using • OTG B-device can pulse VBUS for SRP.
HNP
Note: Refer to the specific device data sheet for
VBUS electrical parameters.
11.4.3.2 B-Device, the Default Device
In OTG dual role, operating as a USB device, the fol-
lowing features and requirements describe a B-Device:
• Class- or vendor-specific functionality
• Draws 8 mA or less before configuration
• Is typically self-powered, due to low-current

PIC32MX3XX/4XX
11.5 PIC32MX Implementation ing buffers maximizes data throughput by allowing
Specifics CPU data access in parallel with data transfer. This
technique is referred to as ping-pong buffering.
This section details how the USB specification require- Figure 11-2 illustrates how the endpoints are mapped
ments are implemented in the PIC32MX USB module. in the BDT.
11.5.1 BUS SPEED 11.5.2.1 Endpoint Control

The PIC32MX USB module supports the following Each endpoint is controlled by an Endpoint Control reg-
speeds: ister, U1EPn, that configures the transfer direction, the
• Full-speed operation as a host and a device handshake, and the stalling properties of the endpoint.
The Endpoint Control register also allows support of
• Low-speed operation as a host
control transfers.
11.5.2 ENDPOINTS AND DESCRIPTORS
11.5.2.2 Host Endpoints
All USB endpoints are implemented as buffers in RAM.
The CPU and USB module have access to the buffers. Note: In Host mode, Endpoint 0 has additional
To arbitrate access to these buffers between the USB bits for auto-retry and hub support.
module and CPU, a semaphore flag system is used. The host performs all transactions through a single
Each endpoint can be configured for TX and/or RX, and endpoint (Endpoint 0). All other endpoints should be
each has an ODD and an EVEN buffer. disabled and other endpoint buffers are not be used.
Use of the Buffer Descriptor Table (BDT) allows the buf-
fers to be located anywhere in RAM, and provides sta- 11.5.2.3 Device Endpoints
tus flags and control bits. The BDT contains the Endpoint 0 must be implemented for a USB device to
address of each endpoint data buffer, as well as infor- be enumerated and controlled. Devices typically imple-
mation about each buffer (see Figure 11-2, Figure 11-3 ment additional endpoints to transfer data.
and Figure 11-4). Each BDT entry is called a Buffer
Descriptor (BD) and is 8 bytes long. All endpoints, rang- 11.5.3 BUFFER MANAGEMENT
ing from endpoint 0 to the highest endpoint in use, must The buffers are shared between the PIC32MX and the
have four descriptor entries. Even if all of the buffers for USB module, and are implemented in system memory.
an endpoint are not used, four descriptors entries are So, a simple semaphore mechanism is used to distin-
required for each endpoint. guish current ownership of the BD, and associated buf-
The USB module calculates a buffer’s location in RAM fers, in memory. This semaphore mechanism is
using the BDT. The base of the BDT is held in registers implemented by the UOWN bit in each BD.
U1BDTP1 through U1BDTP3. The address of the The USB module clears the UOWN bit automatically
desired buffer is found by using the endpoint number, when the transaction for that buffer is complete. When
the type (RX/TX) and the ODD/EVEN bit to index into the UOWN bit is clear, the descriptor is owned by the
the BDT. The address held by this entry is the address PIC32MX – which may modify the descriptor and buffer
of the desired data buffer. Refer to Section 11.4.3.1 as necessary.
“A-Device, the Default Host”.
Software must configure the BDT entry for the next
Note: The contents of the U1BDTP1-U1BDTP3 transaction, then set the UOWN bit to return control to
registers provide the upper 23 bits of the the USB module.
32-bit address; therefore, the BTD must
A BD is only valid if the corresponding endpoint has
be aligned to a 512-byte boundary (see
been enabled in the U1EPn register. The BDT is imple-
Figure 11-2). This address must be the
mented in data memory, and the BDs are not modified
physical (not virtual) memory address.
when the USB module is reset. Initialize the BDs prior
Each of the 16 endpoints owns two descriptor pairs: to enabling them through the U1EPn. At a minimum,
two for packets to transmit, and two for packets the UOWN bits must be cleared prior to being enabled.
received. Each pair manages two buffers, an EVEN
In Host mode, BDT initialization is required before the
and an ODD, requiring a maximum of 64 descriptors
U1TOK register is written, triggering a transfer.
(16 * 2 * 2).
Having EVEN and ODD buffers for each direction
allows the CPU to access data in one buffer while the
USB module transfers data to or from the other buffer.
The USB module alternates between buffers, clearing
the UOWN bit in the buffer descriptor automatically
when the transaction for that buffer is complete (see
Section 11.4.3 “OTG Dual Role”). The use of alternat-

PIC32MX3XX/4XX
FIGURE 11-2: BDT ADDRESS GENERATION
BDTBA<22:0> ENDPOINT<3:0> DIR PPBI FSOTG
31:9 8:5 4 3 2:0
bit 31:9 BDTBA<22:0>: BDT Base Address bits

The 23-bit value is made up of the contents of the U1BDTP3, U1BDTP2, and U1BDTP1 registers.
bit 8:5 ENDPOINT<3:0>: Transfer Endpoint Number bits
0000 = Endpoint 0
0001 = Endpoint 1
....
1110 = Endpoint 14
1111 = Endpoint 15
bit 4 DIR: Transfer Direction bit
1 = Transmit: SETUP/OUT for host, IN for function
0 = Receive: IN for host, SETUP/OUT for function
bit 3 PPBI: Ping-Pong Pointer bit
1 = ODD buffer
0 = EVEN buffer
bit 2:0 Manipulated by the USB module

PIC32MX3XX/4XX
11.5.3.1 Buffer Descriptor Format Buffer descriptor control format, in which software
writes the descriptor and hands it to hardware, is
The buffer descriptor is used in the following formats:
• Control
Buffer descriptor status format, in which hardware
• Status. writes the descriptor and hands it back to software, is
FIGURE 11-3: USB BUFFER DESCRIPTOR FORMAT: SOFTWARE → HARDWARE
Address Offset +0
31 26 25 16 15 8 7 6 5 4 3 2 1 0
DATA0/1
— BYTE COUNT<9:0> —
BSTALL
—
UOWN
KEEP
NINC
DTS
Address Offset +4
31 0
BUFFER ADDRESS<31:0>
Address Offset +0
bit 25-16 BYTE_COUNT<9:0>: Byte Count bits

Byte count represents the number of bytes to be transmitted or the maximum number of bytes to be
received during a transfer.
bit 7 UOWN: USB Own bit
1 = USB module owns the BD and its corresponding buffer
CPU must not modify the BD or the buffer.
0 = CPU owns the BD and its corresponding buffer
USB module ignores all other fields in the BD.
USBFRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode.
Note: This bit can be programmed by either the CPU or the USB module, and it must be initialized by the
user to the desired value prior to enabling the USB module.
bit 6 DATA0/1: Data Toggle Packet bit
1 = Transmit a Data 1 packet or Check received PID = DATA1, if DTS = 1
0 = Transmit a Data 0 packet or Check received PID = DATA1, if DTS = 1
bit 5 KEEP: BD Keep Enable bit
1 = USB will keep the BD indefinitely once UOWN is set
U1STAT FIFO will not be updated and TRNIF bit will not be set at the end of each transaction.
0 = USB will hand back the BD once a token has been processed
bit 4 NINC: DMA Address Increment Disable bit
1 = DMA address increment disabled
0 = DMA address increment enabled
bit 3 DTS: Data Toggle Synchronization Enable bit
1 = Data Toggle Synchronization is enabled – data packets with incorrect sync value will be ignored
0 = No Data Toggle Synchronization is performed
Note: Expected value of DATA PID (DATA0/DATA1) specified in the DATA0/1 field.

PIC32MX3XX/4XX
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buffer STALL enabled
STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit
remains set, BD value is unchanged).
Corresponding EPSTALL bit will get set on any STALL handshake.
0 = Buffer STALL disabled
Address Offset +4
bit 31-0 BUFFER_ADDRESS: Buffer Address bits(3)

Starting point address of the endpoint packet data buffer.
Note: The individual buffer addresses in the BDT must be physical memory addresses.

PIC32MX3XX/4XX
FIGURE 11-4: USB BUFFER DESCRIPTOR FORMAT: HARDWARE → SOFTWARE
Address Offset +0
31 26 25 16 15 8 7 6 5 4 3 2 1 0
DATA0/1
— BYTE COUNT<9:0> — PID<3:0> —
UOWN
Address Offset +4
31 0
BUFFER ADDRESS<31:0>
Address Offset +0
bit 25-16 BYTE_COUNT<9:0>: Byte Count bits

Byte count reflects the actual number of bytes received or transmitted.
bit 7 UOWN: USB Own bit
1 = USB module owns the BD and its corresponding buffer
CPU must not modify the BD or the buffer.
0 = CPU owns the BD and its corresponding buffer
Note: This bit can be programmed by either the CPU or the USB module, and it must be initialized by the
user to the desired value prior to enabling the USB module.
bit 6 DATA0/1: Data Toggle Packet bit
1 = Data 1 packet received
0 = Data 0 packet received
Note: This bit is unchanged on an outgoing packet.
bit 5-2 PID<3:0>: Packet Identifier bits
The current token PID when a transfer completes.
The values written back are the token PID values from the USB specification: 0x1 for an OUT token, 0x9 for
an IN token or 0xd for a SETUP token.
In Host mode, this field is used to report the last returned PID or a transfer status indication.
The possible values returned are: 0x3 DATA0, 0xb DATA1, 0x2 ACK, 0xe STALL, 0xa NAK,
0x0 Bus Time-out, 0xf Data Error.
Address Offset +4
bit 31-0 BUFFER_ADDRESS: Buffer Address bits

Starting point address of the endpoint packet data buffer.

PIC32MX3XX/4XX
FIGURE 11-5: BUFFER MANAGEMENT OVERVIEW
U1BDTP1:3 BDT Transfer Buffers

located in RAM* Located in RAM
Pointer
EP0 RX EVEN Descriptor EP0 RX EVEN Buffer
EP0 RX ODD Descriptor
EP0 TX EVEN Descriptor EP0 RX ODD Buffer
EP0 TX ODD Descriptor
EP1 RX EVEN Descriptor EP0 TX EVEN Buffer
EP1 TX EVEN Descriptor EP0 TX ODD Buffer
EP2 RX EVEN Descriptor EP1 RX EVEN Buffer
EP2 TX EVEN Descriptor EP1 RX ODD Buffer
... EP1 TX EVEN Buffer
*512 byte aligned EP1 TX ODD Buffer
EP2 RX EVEN Buffer
EP2 RX ODD Buffer
EP2 TX EVEN Buffer
EP2 TX ODD Buffer

...
EP15 TX ODD Buffer

PIC32MX3XX/4XX
11.5.4 BUFFER DESCRIPTOR 11.6 Hardware Interface
CONFIGURATION
11.6.1 POWER SUPPLY REQUIREMENTS
The UOWN, DTSEN and BSTALL bits in each BDT
entry control the data transfer for the associated buffer Power supply requirements for USB implementation
and endpoint. vary with the type of application, and are outlined
below.
Setting the DTSEN bit enables the USB module to per-
form data toggle synchronization. When DTS is • Device:
enabled: if a packet arrives with an incorrect DTS, it will Operation as a device requires a power supply
be ignored, the buffer remains unchanged, and the for the PIC32MX and the USB transceiver, see
packet will be NAK’d (Negatively Acknowledged). Figure 11-6 for an overview of USB implementa-
Setting the BSTALL bit causes the USB to issue a tion as a device.
STALL handshake if a token is received by the SIE that • Embedded Host:
would use the BD in this location – the corresponding
EPSTALL bit is set and a STALLIF interrupt is gener- Operation as a host requires a power supply for
ated. When the BSTALL bit is set, the BD is not con- the PIC32MX, the USB transceiver, and a 5V
sumed by the USB module (the UOWN bit remains set nominal supply for the USB VBUS. The power
and the rest of the BD values are unchanged). If a supply must be able to deliver 100 mA, or up to
SETUP token is sent to the stalled endpoint, the mod- 500 mA, depending on the requirements of the
ule automatically clears the corresponding BSTALL bit. devices in the TPL. The application dictates
whether the VBUS power supply can be disabled
The byte count represents the total number of bytes or disconnected from the bus by the PIC32MX
that are transmitted or received. Valid byte counts application. Figure 11-7 presents an overview of
range from 0 to 1023. For all endpoint transfers, the USB implementation as a host.
byte count is updated by the USB module, with the
actual number of bytes transmitted or received, after • OTG Dual Role:
the transfer is completed. If the number of bytes Operation as an OTG dual role requires a power
received exceeds the corresponding byte count value supply for the PIC32MX, the USB transceiver,
written by the firmware, the overflow bit is set and the and a switchable 5V nominal supply for the USB
data is truncated to fit the size of the buffer (as given in VBUS. An overview of USB implementation as
the BTD). OTG is presented in Figure 11-8.
When acting as an A-device, power must be
supplied to VBUS. The power supply must be
able to deliver 8 mA, 100 mA, or up to 500 mA,
depending on the requirements of the devices in
the TPL.
When acting as a B-device, power must not be
supplied to VBUS. VBUS pulsing can be per-
formed by the USB module or by a capable
power supply.
11.6.2 VBUS REGULATOR INTERFACE

The VBUSON output can be used to control an off-chip
5V VBUS regulator. The VBUSON pin is controlled by
the VBUSON bit (U1OTGCON<3>). VBUSON appears
in Figure 11-7 and Figure 11-8.

PIC32MX3XX/4XX
FIGURE 11-6: OVERVIEW OF USB IMPLEMENTATION AS A DEVICE
VUSB
3.3V
USB Type ‘B’

Connector
VBUS
1
D+
2
USB Module
D-
3

PIC32MX3XX/4XX
FIGURE 11-7: OVERVIEW OF USB IMPLEMENTATION AS A HOST
VUSB
External Power 3.3V
5V
VBUSON
USB Type ‘A’

Connector
VBUS
1
USB Module
D+
2
D-
3

PIC32MX3XX/4XX
FIGURE 11-8: OVERVIEW OF USB IMPLEMENTATION FOR OTG (DUAL ROLE)
VUSB
External Power 3.3V
5V
VBUSON
USB Type
Micro ‘AB’
Connector
VBUS SRP Source

1
SRP Discharge
D+
2 USB Module
D-
3
ID
4

PIC32MX3XX/4XX
11.7 Module Initialization 11.7.3 USB ENABLE/MODE BITS
This section describes the steps that must be taken to USB mode of operation is controlled by the following
properly initialize the OTG USB module. enable bits: OTGEN (U1OTGCON<2>), HOSTEN
(U1CON<3>), and USBEN/SOFEN (U1CON<0>).
11.7.1 ENABLING THE USB HARDWARE • OTGEN:
In order to use the USB peripheral, software must set OTGEN selects whether the PIC32MX is to act
the USBPWR bit (U1PWRC<0>) to ‘1’. This may be as an OTG part (OTGEN = 1) or not. OTG
done in start-up boot sequence. devices support SRP and HNP in hardware with
USBPWR is used to initiate the following actions: Firmware management and have direct control
over the data-line pull-up and pull-down resis-
• Start the USB clock
tors.
• Allow the USB interrupt to be activated
• HOSTEN:
• Select USB as the owner of the necessary IO pins
• Enable the USB transceiver HOSTEN controls whether the part is acting in
the role of USB Host (HOSTEN = 1) or USB
• Enable the USB comparators
Device (HOSTEN = 0). Note that this role may
The USB module and internal registers are reset when change dynamically in an OTG application.
USBPWR is cleared. Consequently, the appropriate ini-
• USBEN/SOFEN:
tialization process must be performed whenever the
USB module is enabled, as described in the following USBEN controls the connection to USB when
subsections. Otherwise, any configuration packet sent the USB module is not configured as a host.
to the USB module will be stalled, by hardware, until the If the USB module is configured as a host,
reset is complete. SOFEN controls whether the host is active on
the USB link and sends SOF tokens every 1 ms.
11.7.2 INITIALIZING THE BDT
Note: The other USB module control registers
All descriptors for a given endpoint and direction must
should be properly initialized before
be initialized prior to enabling the endpoint (for that
enabling USB via these bits.
direction). After a Reset, all endpoints are disabled and
start with the EVEN buffer for transmit and receive
directions. 11.8 Device Operation
Transmit descriptors must be written with the UOWN bit All communication on the USB is initiated by the host.
cleared to ‘0’ (owned by software). All other transmit Therefore, in Device mode, when USB is enabled
descriptor setup may be performed anytime prior to USBEN = 1 (U1CON<0>), Endpoint 0 must be ready to
setting the UOWN bit to ‘1’. receive control transfers. Initialization of the remaining
Receive descriptors must be fully initialized to receive endpoints, descriptors, and buffers can be delayed until
data. This means that memory must be reserved for the host selects a configuration for the device. Refer to
received packet data. The pointer to that memory Chapter 9 of the “Universal Serial Bus Specification,
(physical address), and the size reserved in bytes, Revision 2.0” for more information on this subject.
must be written to the descriptor. The receive descrip- The following steps are performed to respond to a USB
tor UOWN bit should be initialized to ‘1’ (owned by transaction:
hardware). The DTS and STALL bits should also be 1. Software pre-initializes the appropriate BDs,
configured appropriately. and sets the UOWN bits to ‘1’ to be ready for a
If a transaction is received and the descriptor’s UOWN transaction.
bit is ‘0’ (owned by software), the USB module returns 2. Hardware receives a TOKEN PID (IN, OUT,
a NAK handshake to the host. Usually, this causes the SETUP) from the USB host, and checks the
host to retry the transaction. appropriate BD.
3. If the transaction will be transmitted (IN), the
module reads packet data from data memory.
4. Hardware receives a DATA PID (DATA0/1), and
sends or receives the packet data.
5. If a transaction is received (SETUP, OUT), the
module writes packet data to data memory.

PIC32MX3XX/4XX
6. The module issues, or waits for, a handshake 11.8.2 RECEIVING AN OUT TOKEN IN
PID (ACK, NAK, STALL), unless the endpoint is DEVICE MODE
setup as an isochronous endpoint (EPHSHK bit
Perform the following steps to receive an OUT token in
UEPMx<0> is cleared).
Device mode:
7. The module updates the BD, and writes the
UOWN bit to ‘0’ (SW owned). 1. Attach to a USB host and enumerate as
described in Chapter 9 of the USB 2.0
8. The module updates the U1STAT register, and
specification.
sets the TRNIF interrupt.
2. Create a data buffer with the amount of data you
9. Software reads the U1STAT register, and deter-
are expecting from the host.
mines the endpoint and direction for the transac-
tion. 3. In the appropriate (EVEN or ODD) transmit buf-
fer descriptor for the desired endpoint:
10. Software reads the appropriate BD, completes
all necessary processing, and clears the TRNIF a) Set up the Status bit field (BDnSTAT) with
interrupt. the correct data toggle (DATA0/1) value and
the byte count of the data buffer.
Note: For transmitted (IN) transactions (host
b) Set up the address bit field (BDnADR) with
reading data from the device), the read
the starting address of the data buffer.
data must be ready when the Host begins
USB signaling. Otherwise, the USB mod- c) Set the UOWN bit of the Status bit field to
ule will send a NAK handshake if UOWN is ‘1’.
‘0’. 4. When the USB module receives an OUT token,
it will automatically receive the data the host
11.8.1 RECEIVING AN IN TOKEN IN sent into the buffer. Upon completion, the mod-
DEVICE MODE ule updates the Status bit field (BDnSTAT),
clears the UOWN bit and sets the transfer
Perform the following steps to receive an IN token in
complete interrupt (U1IR<TRNIF>).
Device mode:
1. Attach to a USB host and enumerate as 11.9 Host Mode Operation
described in Chapter 9 of the USB 2.0
specification. In Host mode, only Endpoint 0 is used (all other end-
2. Populate the data buffer with the data to send to points should be disabled). Since the host initiates all
the host. transfers, the BD does not require immediate initializa-
tion. However, the BDs must be configured before a
3. In the appropriate (EVEN or ODD) transmit buf-
transfer is initiated – which is done by writing to the
fer descriptor for the desired endpoint:
U1TOK register.
a) Set up the control bit field (BDnSTAT) with
the correct data toggle (DATA0/1) value and The following sections describe how to perform com-
the byte count of the data buffer. mon Host mode tasks. In Host mode, USB transfers
are invoked explicitly by the host software. The host
b) Set up the address bit field (BDnADR) with
software is responsible for initiating the setup, data,
the starting address of the data buffer.
and status stages of all control transfers. The acknowl-
c) Set the UOWN bit field to ‘1’. edge (ACK or NAK) is generated automatically by the
4. When the USB module receives an IN token, it hardware, based on the CRC. Host software is also
automatically transmits the data in the buffer. responsible for scheduling packets so that they do not
Upon completion, the module updates the Sta- violate USB protocol. All transfers are performed using
tus bit field (BDnSTAT), clears the UOWN bit the Endpoint 0 Control register (U1EP0) and BDs.
and sets the transfer complete interrupt
(U1IR<TRNIF>).

PIC32MX3XX/4XX
11.10 Configuring the SOF Threshold register is in terms of bytes), no new tokens are started
until after the SOF has been transmitted. Thus, the
The module counts down the number of bits that could USB module attempts to ensure that the USB link is idle
be transmitted within the current USB full-speed frame. when the SOF token needs to be transmitted.
Since 12,000 bits can be transmitted during the 1 ms
frame time, a counter, not visible to software, is loaded This implies that the value programmed into the
with the value ‘12,000’ at the start of each frame. The U1SOF register must reserve enough time to insure the
counter decrements once for each bit time in the frame. completion of the worst-case transaction. Typically, the
When the counter reaches zero the next frame’s SOF worst-case transaction is an IN token followed by a
packet is transmitted, see Figure 11-9. maximum-sized data packet from the target, followed
by the response from the host. If the host is targeting a
The SOF threshold register (U1SOF) is used to ensure low-speed device that is bridging through a full-speed
that no new tokens are started too close to the end of a hub, the transaction will also include the special PRE
frame. This prevents a conflict with the next frame’s token packets.
SOF packet. When the counter reaches the threshold
value of the U1SOF register (the value in the U1SOF
FIGURE 11-9: ALLOCATION OF BITS FOR A FULL-SPEED FRAME
1 Full-Speed Frame
SOF Threshold
U1SOF * 8
bit times
SOF SOF
0 ms 1 ms (12,000 bit times)

Note: Drawing is not to scale.
Table 11-4 and Table 11-5 show examples of calculat-

ing worst-case bit times.
Note 1: While the U1SOF register value is described in terms of bytes, these examples show the result in terms
of bits.
2: In the second table, the IN, DATA, and HANDSHAKE packets are transmitted at low speed (8 times slower
than full speed).
3: These calculations do not take the possibility that the packet data needs to be bit-stuffed for NRZI encoding
into account.
TABLE 11-4: EXAMPLE OF SOF THRESHOLD CALCULATION: FULL SPEED

Packet Fields Bits
IN SYNC, PID, ADDR, ENDP, CRC5, EOP 35
Turnaround(1) 8
DATA SYNC, PID, DATA(2), CRC16, EOP 547
Turnaround 2
HANDSHAKE SYNC, PID, EOP 19
Inter-packet 2
Total 613
Note 1: Inter-packet delay of 2. An additional 5.5 bit times of latency is added to represent a worst-case propaga-
tion delay through 5 hubs.
2: Using 64-bytes maximum packet size for this example calculation.

PIC32MX3XX/4XX
TABLE 11-5: EXAMPLE OF SOF THRESHOLD CALCULATION: LOW SPEED VIA HUB
Packet Fields Bits FS Bits
PRE SYNC, PID 16 16
Hub setup 4 4
IN SYNC, PID, ADDR, ENDP, CRC5, EOP 35 280
(1)
Turnaround 8 8
DATA SYNC, PID, DATA(2), CRC16, EOP 99 792
Turnaround 2 2
PRE SYNC, PID 16 16
HANDSHAKE SYNC, PID, EOP 19 152
Inter-packet 2 2
Total 1272
Note 1: Inter-packet delay of 2. An additional 5.5 bit times of latency is added to represent a worst-case propaga-
tion delay through 5 hubs.
2: Packets limited to 8-bytes maximum in Low-Speed mode.
Note: Refer to Section 5.11.3 “Calculating Bus

Transaction Times” in the USB 2.0 spec-
ification for details on calculating bus
transaction time.

PIC32MX3XX/4XX
11.11 Enabling Host Mode and 5. Hardware reads the BD to determine the appro-
Discovering a Connected Device priate action, and to obtain the pointer to data
memory.
To enable Host mode, perform the following steps: 6. Hardware issues the correct TOKEN PID (IN,
1. Enable Host mode (U1CON<HOSTEN> = 1). OUT, SETUP) on the USB link.
This enables the D+ and D- pull-down resistors, 7. If the transaction is a transmit transaction (OUT,
and disables the D+ and D- pull-up resistors. To SETUP), the USB module reads the packet data
reduce noise on the bus, disable the SOF out of data memory. Then the module follows
packet generation by writing the SOF Enable bit with the desired DATA PID (DATA0/DATA1) and
to ‘0’ (U1CON<SOFEN> = 0). packet data.
2. Enable the device attach interrupt 8. If the transaction is a receive transaction (IN),
(U1IE<ATTACHIE> = 1). the USB module waits to receive the DATA PID
3. Wait for the device attach interrupt and packet data. Hardware writes the packet
(U1IR<ATTACHIF>). data to memory.
This is signaled by the USB device changing the 9. Hardware issues or waits for a Handshake PID
state of D+ or D- from ‘0’ to ‘1’ (SE0 to JSTATE). (ACK, NAK, or STALL), unless the endpoint is
After it occurs, wait for the device power to staset up as an isochronous endpoint (EPHSHK bit
bilize (10 ms is minimum, 100 ms is recom- U1EPx<0> is cleared).
mended). 10. Hardware updates the BD, and writes the
4. Check the state of the JSTATE and SE0 bits in UOWN bit to ‘0’ (SW owned).
the control register U1CON. 11. Hardware updates the U1STAT register, and
If U1CON<JSTATE> is ‘0’, the connecting sets the TRNIF (U1IR<3>) interrupt.
device is low speed; otherwise, the device is full
12. Hardware reads the next BD (EVEN or ODD) to
speed.
see whether it is owned by the USB module. If it
5. If the connecting device is low speed, set the is, hardware begins the next transaction.
low-speed enable bit in the address register
13. Software should read the U1STAT register, and
(U1ADDR<LSPDEN>= 1), and the low-speed
then clear the TRNIF interrupt.
bit in the Endpoint 0 Control register
(U1EP0<LSPD> = 1). But, if the device is full If Software does not set the UOWN bit to ‘1’ in the
speed, clear these bits. appropriate BD prior to writing the U1TOK register, the
6. Reset the USB device by sending the Reset sig- module will read the descriptor and do nothing.
naling for at least 50 ms (U1CON<USBRST> =
1). After 50 ms, terminate the Reset
(U1CON<USBRST> = 0).
7. Enable SOF packet generation to keep the con-
nected device from going into suspend
(U1CON<SOFEN> = 1).
8. Wait 10 ms for the device to recover from Reset.
9. Perform enumeration as described in Chapter 9
of the USB 2.0 specification.
11.11.1 HOST TRANSACTIONS

When acting as a host, a transaction consists of the fol-
lowing:
1. Software configures the appropriate BD (End-
point n, DIR, PPBI), and sets the UOWN bit to ‘1’
(HW owned).
2. Software checks the state of TOKBUSY
(U1CON<5>) to verify that any previous
transaction has completed.
3. Software writes the address of the target device
in the U1ADDR register.
4. Software writes the endpoint number and the
desired TOKEN PID (IN, OUT, or SETUP) to the
U1TOK register.

PIC32MX3XX/4XX
11.12 Completing a Control Transaction 8. Write the Token register with the appropriate IN
to a Connected Device or OUT token to Endpoint 0, the target device’s
default control pipe) for example, an IN token for
Complete all of the following steps to discover a con- a GET DEVICE DESCRIPTOR command
nected device: (U1TOK = 0x90). This will initiate an IN token on
1. Set up the Endpoint Control register for bidirec- the bus followed by a data packet from the
tional control transfers, U1EP0<4:0> = 0x0D. device to the host. When the data packet com-
pletes, the BD0STAT is written and a transfer
2. Place an 8-byte of the device setup packet in the
done interrupt will be asserted (U1IR<TRNIF>).
appropriate memory buffer. See Chapter 9 of
For control transfers with a single packet data
the USB 2.0 specification for information on the
phase, this completes the data phase of the
device framework command set.
setup transaction. If more data needs to be
3. Initialize the current (EVEN or ODD) TX EP0 BD transferred, return to step 8.
to transfer the 8 byte device framework com-
9. To initiate the status stage of the setup transac-
mand (for example, a GET DEVICE DESCRIP-
tion, set up a buffer in memory to receive or send
TOR command).
the zero length status phase data packet.
a) Set the BD status (BD0STAT) to 0x8008 –
10. Initialize the current (EVEN or ODD) TX EP0 BD
UOWN bit set, byte count of 8.
to transfer the status data.
b) Set the BD data buffer address (BD0ADR)
a) Set the BD status (BD0STAT) to 0x8000 –
to the starting address of the 8-byte
UOWN bit to ‘1’, data toggle (DTS) to
memory buffer containing the command, if it
DATA0 and byte count to ‘0’.
is not already initialized.
b) Set the BDT buffer address field to the start
4. Set the USB address of the target device in the
address of the data buffer.
address register U1ADDR<6:0>. After a USB
bus Reset, the device USB address will be zero. 11. Write the Token register with the appropriate IN
After enumeration, it must be set to another or OUT token to Endpoint 0, the target device’s
value, between 1 and 127, by the host software. default control pipe) for example, an OUT token
for a GET DEVICE DESCRIPTOR command
5. Write the token register with a SETUP command
(U1TOK = 0x10). This will initiate a token on the
to Endpoint 0, the target device’s default control
bus, followed by a zero length data packet from
pipe (U1TOK = 0xD0). This will initiate a SETUP
the host to the device. When the data packet
token on the bus followed by a data packet. The
completes, the BD is updated with the hand-
device handshake will be returned in the PID
shake from the device, and a transfer done inter-
field of BD0STAT after the packets complete.
rupt will be asserted (U1IR<TRNIF>). This
When the module updates BD0STAT, a transfer
completes the status phase of the setup
done interrupt will be asserted (U1IR<TRNIF>).
transaction.
This completes the setup stage of the setup
transfer as described in Chapter 9 of the USB Note: Some devices can only effectively
specification. respond to one transaction per frame.
6. To initiate the data stage of the setup transaction
(for example, get the data for the GET DEVICE
DESCRIPTOR command), set up a buffer in
memory to store the received data.
7. Initialize the current (EVEN or ODD) RX or TX
(RX for IN, TX for OUT) EP0 BD to transfer the
data.
a) Set the BD status (BD0STAT) UOWN bit to
‘1’, data toggle (DTS) to DATA1 and byte
count to the length of the data buffer.
b) Set the BD data buffer address (BD0ADR)
to the starting address of the data buffer if it
is not already initialized.

PIC32MX3XX/4XX
11.13 Data Transfer with a Target Device 11.13.1.1 Reset
Complete all of the following steps to discover and con- As a host, software is required to drive Reset signaling.
figure a connected device. It may do this by setting USBRST (U1CON<4>). As per
the USB specification, the host must drive the Reset for
1. Write the EP0 Control register (U1EP0) to at least 50 ms. (This does not have to be continuous
enable transmit and receive transfers as appro- Reset signaling. Refer to the USB 2.0 specification for
priate with handshaking enabled (unless iso- more information.) Following Reset, the host must not
chronous transfers are to be used). If the target initiate any downstream traffic for another 10 ms.
device is a low-speed device, also set the Low-
Speed Enable bit (U1EP0<LSPD>). If you want As a device, the USB module will assert the URSTIF
the hardware to automatically retry indefinitely if (U1IR<0>) interrupt when it has detected Reset signal-
the target device asserts a NAK on the transfer, ing for 2.5 μs. Software must perform any Reset initial-
clear the Retry Disable bit (U1EP0<RETRY- ization processing at this time. This includes setting the
DIS>). address register to 0x00 and enabling Endpoint 0. The
URSTIF interrupt will not be set again until the Reset
Note: Use of automatic indefinite retries can lead signaling has gone away and then has been detected
to a deadlock condition if the device never again for 2.5 μs.
responds.
2. Set up the current buffer descriptor (EVEN or 11.13.1.2 Idle and Suspend
ODD) in the appropriate direction to transfer the The Idle state of the USB is a constant J state. When
desired number of bytes. the USB has been Idle for 3 ms, a device should go into
3. Set the address of the target device in the suspend state. During active operation, the USB host
address register (U1ADDR<6:0>). will send a SOF token every 1 ms, preventing a device
4. Write the Token register (U1TOK) with an IN or from going into suspend state.
OUT token as appropriate for the desired end- Once the USB link is in the suspend state, a USB host
point. This triggers the module’s transmit state or device must drive resume signaling prior to initiating
machines to begin transmitting the token and any bus activity. (The USB link may also be discon-
the data. nected.)
5. Wait for the transfer done interrupt
As a USB host, software should consider the link in
(U1IR<TRNIF>). This will indicate that the BD
suspend state as soon as software clears the SOFEN
has been released back to the microprocessor
(U1CON<0>).
and the transfer has completed. If the retry dis-
able bit is set, the handshake (ACK, NAK, As a USB device, hardware will set the IDLEIF
STALL or ERROR (0xf)) will be returned in the (U1IR<4>) interrupt when it detects a constant Idle on
BD PID field. If a stall interrupt occurs, then the the bus for 3 ms. Software should consider the link in
pending packet must be dequeued and the error suspend state when the IDLEIF interrupt is set.
condition in the target device cleared. If a detach Once a suspend condition has been detected, the soft-
interrupt occurs (SE0 for more than 2.5 μs), then ware may wish to place the USB hardware in a Sus-
the target has detached (U1IR<DETACHIF>). pend mode by setting USUSPEND (U1PWRC<1>).
6. Once the transfer done interrupt The hardware Suspend mode gates the USB module’s
(U1IR<TRNIF>) occurs, the BD can be 48 MHz clock and places the USB transceiver in a Low-
examined and the next data packet queued by Power mode.
returning to step 2.
Additionally, the user may put the PIC32MX into Sleep
mode while the link is suspended.
Note: USB speed, transceiver and pull-ups
should only be configured during the mod- 11.13.1.3 Driving Resume Signaling
ule set-up phase. It is not recommended to If software wants to wake the USB from suspend state,
change these settings while the module is it may do so by setting RESUME (U1CON<2>). This
enabled. will cause the hardware to generate the proper resume
signaling (including finishing with a low-speed EOP if a
11.13.1 USB LINK STATES host).
Three possible link states are described in the following A USB device should not drive resume signaling unless
subsections: the Idle state has persisted for at least 5 ms. The USB
• Reset host also must have enabled the function for remote
• Idle and Suspend wake-up.
• Resume Signalling

PIC32MX3XX/4XX
Software must set RESUME for 1-15 ms if a USB 1. VBUS supply is below the session end voltage.
device, or >20 ms if a USB host, then clear it to enable 2. Both D+ and D- have been low for at least 2 ms.
remote wake-up. For more information on RESUME
The B-device will be notified of condition 1 by the SES-
signaling, see Section 7.1.7.7, 11.9 and 11.4.4 in the
ENDIF (U1OTGIR<2>) interrupt.
USB 2.0 specification.
Software can use the LSTATEIF (U1OTGIR<5>) bit
Writing RESUME will automatically clear the special
and the 1 ms timer to identify condition 2.
hardware suspend (low-power) state.
The B-device may aid in achieving condition 1 by dis-
If the part is acting as a USB host, software should, at
charging the VBUS supply through a resistor. Software
minimum, set the SOFEN (U1CON<0>) after driving its
may do this by setting VBUSDIS (U1OTGCON<0>).
resume signaling. Otherwise, the USB link would return
right back to the suspend state. Also, software must not The B-device then proceeds by pulsing the D+ data
initiate any downstream traffic for 10 ms following the line. Software should do this by setting DPPULUP
end of resume signaling. (U1OTGCON<7>). The data line should be held high
for 5-10 ms.
11.13.1.4 Receiving Resume Signaling After these initial conditions are met, the B-device may
When the USB logic detects resume signaling on the begin requesting the new session. It begins by pulsing
USB bus for 2.5 μs, hardware will set the RESUMEIF the VBUS supply. Software should do this by setting
(U1IR<5>) interrupt. VBUSCHG (U1OTGCON<1>).
A device receiving resume signaling must prepare itself When an A-device detects SRP signaling (either via the
to receive normal USB activity. A host receiving resume ATTACHIF (U1IR<6>) interrupt or via the SESVDIF
signaling must immediately start driving resume signal- (U1OTGIR<3>) interrupt), the A-device must restore
ing of its own. The special hardware suspend (low- the VBUS supply by setting VBUSON
power) state is automatically cleared upon receiving (U1OTGCON<3>).
any activity on the USB link. The B-device should not monitor the state of the VBUS
Reception of any activity on the USB link (this may be supply while performing VBUS supply pulsing. After-
due to resume signaling or a link disconnect) while the wards, if the B-device does detect that the VBUS supply
PIC32MX is in Sleep mode will cause the ACTVIF has been restored (via the SESVDIF (U1OTGIR<3>)
(U1OTGIR<4>) interrupt to be set. This will cause interrupt), it must reconnect to the USB link by pulling
wake-up from Sleep. up D+. The A-device must complete the SRP by
enabling VBUS and driving reset signalling.
11.13.1.5 SRP Support
11.13.1.6 HNP
SRP support is not required by non-OTG applications.
SRP may only be initiated at full speed. Refer to the An OTG application with a micro-AB receptacle must
On-The-Go Supplement specification for more infor- support HNP. HNP allows an OTG B-device to tempo-
mation regarding SRP. rarily become the USB host. The A-device must first
enable HNP in the B-device. HNP may only be initiated
An OTG A-device or embedded host may decide to
at full-speed. Refer to the On-The-Go supplement for
power-down the VBUS supply when it is not using the
more information regarding HNP.
USB link. Software may do this by clearing VBUSON
(U1OTGCON<3>). When the VBUS supply is powered After being enabled for HNP by the A-device, the B-device
down, the A-device is said to have ended a USB ses- can request to become the host any time that the USB link is
sion. in suspend state by simply indicating a disconnect. Software
may accomplish this by clearing the DPPULUP bit
(U1OTGCON<7>).
Note: When the A-device powers down the VBUS When the A-device detects the disconnect condition
supply, the B-device must disconnect its (via the URSTIF (U1IR<0>) interrupt), the A-device
pull-up resistor unless signalling a desire may allow the B-device to take over as host. The A-
to become host during HNP negotiation. device does this by signaling connect as a full-speed
Refer to Section 11.13.1.6 “HNP”. device. Software may accomplish this by disabling host
An OTG A-device or embedded host may repower the operation, HOSTEN = 0 (U1CON<3>), and connecting
VBUS supply at any time to initiate a new session. An as a device (DPPULUP = 1). If the A-device instead
OTG B-device may also request that the OTG A-device responds with resume signaling, the A-device will
repower the VBUS supply to initiate a new session. This remain as host.
is the purpose of the SRP. When the B-device detects the connect condition (via
Prior to requesting a new session, the B-device must ATTACHIF (U1IR<6>), the B-device becomes host.
first check that the previous session has definitely The B-device drives Reset signaling prior to using the
ended. To do this, the B-device must check that: bus.

PIC32MX3XX/4XX
When the B-device has finished in its role as host, it 11.16 USB Module Interrupt Request
stops all bus activity and turns on its D+ pull-up resistor Generation
by disabling host operations (HOSTEN = 0) and recon-
necting as a device (DPPULUP = 1). The USB module can generate interrupt requests from
a variety of events. To interface these interrupts to the
Then the A-device detects a suspend condition (Idle for
CPU, the USB interrupts are combined such that any
3 ms), the A-device turns off its D+ pull-up. Alternatively
enabled USB interrupt will cause a generic USB inter-
the A-device may also power-down the VBUS supply to
rupt (if the USB interrupt is enabled) to the interrupt
end the session.
controller, see Figure 11-11. The USB ISR must then
When the A-device detects the connect condition (via determine which USB event(s) caused the CPU inter-
ATTACHIF), the A-device resumes host operation, and rupt and service them appropriately. There are two lay-
drives Reset signaling. ers of interrupt registers in the USB module. The top
level of bits consists of overall USB status interrupts in
11.13.2 CLOCK REQUIREMENTS the U1OTGIR and U1IR registers. The U1OTGIR and
For proper USB operation, the USB module must be U1IR bits are individually enabled through the corre-
clocked with a 48 MHz clock. This clock source is used sponding bits in the U1OTGIE and U1IE registers. In
to generate the timing for USB transfers; it is the clock addition, the USB Error Condition bit (UERRIF) passes
source for the SIE. The control registers are clocked at through any interrupt conditions in the U1EIR register
the same speed as the CPU (refer to Figure 11-1). enabled via the U1EIE register bits.
The USB module clock is derived from the Primary
Oscillator (POSC) for USB operation. A USB PLL and 11.17 Interrupt Timing
input prescalers are provided to allow 48 MHz clock Interrupts for transfers are generated at the end of the
generation from a wide variety of input frequencies. transfer. Figure 11-10 shows some typical event
The USB PLL allows the CPU and the USB module to sequences that can generate a USB interrupt and
operate at different frequencies while both use the when that interrupt is generated. There is no mecha-
POSC as a clock source. To prevent buffer overruns nism by which software can manually set an interrupt
and timing issues, the CPU core must be clocked at a bit.
minimum of 16 MHz.
The values in the Interrupt Enable registers (U1IE,
The USB module can also use the on-board Fast RC U1EIE, U1OTGIE) only affect the propagation of an
oscillator (FRC) as a clock source. When using this interrupt condition to the CPU’s interrupt controller.
clock source, the USB module will not meet the USB Even though an interrupt is not enabled, interrupt flag
timing requirements. The FRC clock source is intended bits can still be polled and serviced.
to allow the USB module to detect a USB wake-up and
report it to the interrupt controller when operating in
low-power modes. The USB module must be running
11.18 Interrupt Servicing
from the Primary oscillator before beginning USB Once an interrupt bit has been set by the USB module
transmissions. (in U1IR, U1EIR or U1OTGIR), it must be cleared by
software by writing a ‘1’ to the appropriate bit position
11.14 Interrupts to clear the interrupt. The USB Interrupt, USBIF
(IFS1<25>), must be cleared before the end of the ISR.
The USB module uses interrupts to signal USB events
such as a change in status, data received and buffer
empty events, to the CPU. Software must be able to
respond to these interrupts in a timely manner.
11.15 Interrupt Control

Each interrupt source in the USB module has an inter-
rupt flag bit and a corresponding enable bit. In addition,
the UERRIF bit (U1IR<1>) is a logical OR of all the
enabled error flags and is read-only. The UERRIF bit
can be used to poll the USB module for events while in
an Interrupt Service Routine (ISR).

PIC32MX3XX/4XX
FIGURE 11-10: TYPICAL EVENTS FOR USB INTERRUPTS
USB USBRST SOF
SOFIF
URSTIF Interrupt Generated
Interrupt Generated
Control
SETUP TOKEN DATA ACK
TRNIF
Interrupt Generated
IN TOKEN DATA ACK
TRNIF
Interrupt Generated
OUT TOKEN DATA ACK
TRNIF
Interrupt Generated
= Host = Function

PIC32MX3XX/4XX
FIGURE 11-11: USB INTERRUPT LOGIC
STALLIF
STALLIE
ATTACHIF
ATTACHIE
RESUMEIF
RESUMEIE
IDLEIF
IDLEIE
TRNIF
TRNIE
BTSEF SOFIF
SOFIE
BTSEE
DMAEF
DMAEE DETACHIF/URSTIF USB Interrupt
DETACHIE/URSTIE
BTOEF
BTOEE UERRIF
DFN8EF UERRIE
DFN8EE
CRC16EF IDIF
CRC16EE IDIE
CRC5EF/EOFEF T1MSECIF
CRC5EE/EOFEE T1MSECIE
PIDEF LSTATEIF
PIDEE LSTATEIE
BMXEF ACTVIF
BMXEE ACTVIE
SESVDIF
SESVDIE
SESENDIF
SESENDIE
VBUSVDIF
VBUSVDIE

PIC32MX3XX/4XX
11.19 I/O Pins
Table 11-6 summarizes the use of pins relating to the
USB module.
TABLE 11-6: PINS ASSOCIATED WITH THE USB MODULE

Required
Module Controlling Pin
Mode Pin Name TRIS Bit Description
Control Bit Field(1) Type
Setting
Embedded D+ USBEN — — U Data line +
Host
D- USBEN — — U Data line -
VBUS USBEN — — P Input for USB power, connects to
OTG comparators
VBUSON USBEN VBUSON — D, O Output to control supply for VBUS(2)
VUSB — — — P Power in for USB transceiver
ID USBEN — — R Reserved
Device D+ USBEN — — U Data line +
VBUS USBEN — — P Input for USB power, connects to
OTG comparators
VBUSON — — — R Reserved(2)
ID — — — R Reserved
OTG D+ USBEN — — U Data line +
VBUS USBEN VBUSCHG, — A, I/O, Analog input for USB power,
VBUSDIS P connects to OTG comparators
VBUSON USBEN VBUSCHG, — D, O Output to control supply for VBUS(2)
VBUSDIS
VBUSON
ID USBEN — — D, I OTG mode host/device select input
USB D+ USBEN — 1 D, I General purpose digital input
Disabled
D- USBEN — 1 D, I General purpose digital input
VBUS USBEN — — R Reserved
VBUSON USBEN — 0 D, O General purpose digital input
VBUSON USBEN — 1 D, I General purpose digital output
VUSB USBEN — — R Reserved
ID USBEN — 1 D, I General purpose digital input
Legend: I = Input O = Output A = Analog D = Digital
U = USB P = Power R = Reserved
Note 1: All pins are subject to the device pin priority control. See the specific device data sheet for further
information.
2: When USB is enabled, this pin is controlled by the USB module and therefore is not available as a
comparator input.

PIC32MX3XX/4XX
TABLE 11-6: PINS ASSOCIATED WITH THE USB MODULE (CONTINUED)
Required
Module Controlling Pin
Mode Pin Name TRIS Bit Description
Control Bit Field(1) Type
Setting
ID USBEN — 0 D, O General purpose digital output
Legend: I = Input O = Output A = Analog D = Digital
U = USB P = Power R = Reserved
Note 1: All pins are subject to the device pin priority control. See the specific device data sheet for further
information.
2: When USB is enabled, this pin is controlled by the USB module and therefore is not available as a
comparator input.

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX

PIC32MX3XX/4XX
12.0 I/O PORTS Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
is not intended to be a comprehensive refer- • Monitor selective inputs and generate interrupt
ence source. Refer to the “PIC32MX Family when change in pin state is detected
Reference Manual” (DS61132) for a • Operation during CPU Sleep and Idle modes
detailed description of this peripheral. • Fast bit manipulation using CLR, SET and INV
registers
The general purpose I/O pins can be considered the
simplest of peripherals. They allow the PIC® MCU to Figure 12-1 shows a block diagram of a typical I/O port,
monitor and control other devices. To add flexibility and whereas Figure 12-2 shows a block diagram of a
functionality, some pins are multiplexed with alternate typical multiplexed I/O port.
function(s). These functions depend on which periph-
eral features are on the device. In general, when a
peripheral is functioning, that pin may not be used as a
general purpose I/O pin.
FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL PORT STRUCTURE
Dedicated Port Module
RD ODC
Data Bus D Q
SYSCLK CK ODC
Q
EN
WR ODC
RD TRIS I/O Cell
0
1
D Q
CK TRIS
Q
EN
WR TRIS
D Q
CK LAT I/O pin
Q
EN
WR LAT
WR PORT
RD LAT
RD PORT 0
Q D Q D
Sleep Q CK Q CK
SYSCLK
Synchronization
© 2008 Microchip Technology Inc. Preliminary DS61143E - page 305

PIC32MX3XX/4XX
FIGURE 12-2: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable

Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus D Q
SYSCLK CK ODC
Q
EN
WR ODC
1 IO Cell
RD TRIS 0
0
1
D Q
TRIS 1
CK
Q 0
EN
WR TRIS
Output Multiplexers
D Q
CK LAT IO Pin
Q
EN
WR LAT
WR PORT
RD LAT
RD PORT 0
Q D Q D
Sleep Q CK Q CK
SYSCLK
Synchronization
Peripheral Input R
Peripheral Input Buffer
Notes: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes
only. The actual structure for any specific port/peripheral combination may be different than what is shown
here.
Legend: R = Peripheral input buffer types may vary. Refer to the specific PIC32MX3XX/4XX data sheet for peripheral
details.
DS61143E - page 306 Preliminary © 2008 Microchip Technology Inc.

PIC32MX3XX/4XX
12.1 Port Registers
TABLE 12-1: PORTA SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_6000 TRISA 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 TRISA15 TRISA14 — — — TRISA10 TRISA9 —
7:0 TRISA<7:0>
BF88_6004 TRISACLR 31:0 Write clears selected bits in TRISA, read yields undefined value
BF88_6008 TRISASET 31:0 Write sets selected bits in TRISA, read yields undefined value
BF88_600C TRISAINV 31:0 Write inverts selected bits in TRISA, read yields undefined value
BF88_6010 PORTA 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 RA15 RA14 — — — RA10 RA9 —
7:0 RA<7:0>
BF88_6014 PORTACLR 31:0 Write clears selected bits in PORTA, read yields undefined value
BF88_6018 PORTASET 31:0 Write sets selected bits in PORTA, read yields undefined value
BF88_601C PORTAINV 31:0 Write inverts selected bits in PORTA, read yields undefined value
BF88_6020 LATA 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 LATA15 LATA14 — — — LATA10 LATA9 —
7:0 LATA<7:0>
BF88_6024 LATACLR 31:0 Write clears selected bits in LATA, read yields undefined value
BF88_6028 LATASET 31:0 Write sets selected bits in LATA, read yields undefined value
BF88_602C LATAINV 31:0 Write inverts selected bits in LATA, read yields undefined value
BF88_6030 ODCA 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ODCA15 ODCA14 — — — ODCA10 ODCA9 —
7:0 ODCA<7:0>
BF88_6034 ODCACLR 31:0 Write clears selected bits in ODCA, read yields undefined value
BF88_6038 ODCFASET 31:0 Write sets selected bits in ODCA, read yields undefined value
BF88_603C ODCAINV 31:0 Write inverts selected bits in ODCA, read yields undefined value
Notes: TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset,
these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user’s application code must
clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must
maintain JTAGEN bit = 1.
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12,
RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain these pins as general pur-
pose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction
TRACE pins, TROEN must be set = 1.

PIC32MX3XX/4XX
TABLE 12-2: PORTB SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_6040 TRISB 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 TRISB<15:8>
7:0 TRISB<7:0>
BF88_6044 TRISBCLR 31:0 Write clears selected bits in TRISB, read yields undefined value
BF88_6048 TRISBSET 31:0 Write sets selected bits in TRISB, read yields undefined value
BF88_604C TRISBINV 31:0 Write inverts selected bits in TRISB, read yields undefined value
BF88_6050 PORTB 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 RB<15:8>
7:0 RB<7:0>
BF88_6054 PORTBCLR 31:0 Write clears selected bits in PORTB, read yields undefined value
BF88_6058 PORTBSET 31:0 Write sets selected bits in PORTB, read yields undefined value
BF88_605C PORTBINV 31:0 Write inverts selected bits in PORTB, read yields undefined value
BF88_6060 LATB 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 LATB<15:8>
7:0 LATB<7:0>
BF88_6064 LATBCLR 31:0 Write clears selected bits in LATB, read yields undefined value
BF88_6068 LATBSET 31:0 Write sets selected bits in LATB, read yields undefined value
BF88_606C LATBINV 31:0 Write inverts selected bits in LATB, read yields undefined value
BF88_6070 ODCB 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ODCB<15:8>
7:0 ODCB<7:0>
BF88_6074 ODCBCLR 31:0 Write clears selected bits in ODCB, read yields undefined value
BF88_6078 ODCBSET 31:0 Write sets selected bits in ODCB, read yields undefined value
BF88_607C ODCBINV 31:0 Write inverts selected bits in ODCB, read yields undefined value
Note: JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset,
these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the user’s application code must
clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must
maintain JTAGEN bit = 1.

PIC32MX3XX/4XX
TABLE 12-3: PORTC SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_6080 TRISC 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 TRISC15 TRISC14 TRISC13 TRISC12 — — — —
7:0 — — — TRISC4(1) TRISC3(1) TRISC2(1) TRISC1(1) —
BF88_6084 TRISCCLR 31:0 Write clears selected bits in TRISC, read yields undefined value
BF88_60088 TRISCSET 31:0 Write sets selected bits in TRISC, read yields undefined value
BF88_6088C TRISCINV 31:0 Write inverts selected bits in TRISC, read yields undefined value
BF88_6090 PORTC 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 RC15 RC14 RC13 RC12 — — — —
7:0 — — — RC4(1) RC3(1) RC2(1) RC1(1) —
BF88_6094 PORTCCLR 31:0 Write clears selected bits in PORTC, read yields undefined value
BF88_6098 PORTCSET 31:0 Write sets selected bits in PORTC, read yields undefined value
BF88_609C PORTCINV 31:0 Write inverts selected bits in PORTC, read yields undefined value
BF88_60A0 LATC 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 LATC15 LATC14 LATC13 LATC12 — — — —
(1) (1) (1) (1)
7:0 — — — LATC4 LATC3 LATC2 LATC1 —
BF88_60A4 LATCCLR 31:0 Write clears selected bits in LATC, read yields undefined value
BF88_60A8 LATCSET 31:0 Write sets selected bits in LATC, read yields undefined value
BF88_60AC LATCINV 31:0 Write inverts selected bits in LATC, read yields undefined value
BF88_60B0 ODCC 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ODCC15 ODCC14 ODCC13 ODCC12 — — — —
7:0 — — — ODCC4(1) ODCC3(1) ODCC2(1) ODCC1(1) —
BF88_60B4 ODCCCLR 31:0 Write clears selected bits in ODCC, read yields undefined value
BF88_60B8 ODCCSET 31:0 Write sets selected bits in ODCC, read yields undefined value
BF88_60BC ODCCINV 31:0 Write inverts selected bits in ODCC, read yields undefined value
Note 1: TRIS, PORT, LAT and ODC bit(s) are not implemented on 64-pin devices, and read as ‘0’.

PIC32MX3XX/4XX
TABLE 12-4: PORTD SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_60C0 TRISD 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 TRISD15(1) TRISD14(1) TRISD13(1) TRISD12(1) TRISD<11:8>
7:0 TRISD<7:0>
BF88_60C4 TRISDCLR 31:0 Write clears selected bits in TRISD, read yields undefined value
BF88_60C8 TRISDSET 31:0 Write sets selected bits in TRISD, read yields undefined value
BF88_60CC TRISDINV 31:0 Write inverts selected bits in TRISD, read yields undefined value
BF88_60D0 PORTD 31:24 — — — — — — — —
23:16 — — — — — — —
15:8 RD15(1) RD14(1) RD13(1) RD12(1) RD<11:8>
7:0 RD<7:0>
BF88_60D4 PORTDCLR 31:0 Write clears selected bits in PORTD, read yields undefined value
BF88_60D8 PORTDSET 31:0 Write sets selected bits in PORTD, read yields undefined value
BF88_60DC PORTDINV 31:0 Write inverts selected bits in PORTD, read yields undefined value
BF88_60E0 LATD 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 LAT15(1) LAT14(1) LAT13(1) LAT12(1) LATD<11:8>
7:0 LATD<7:0>
BF88_60E4 LATDCLR 31:0 Write clears selected bits in LATD, read yields undefined value
BF88_60E8 LATDSET 31:0 Write sets selected bits in LATD, read yields undefined value
BF88_60EC LATDINV 31:0 Write inverts selected bits in LATD, read yields undefined value
BF88_60F0 ODCD 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ODCD15(1) ODCD14(1) ODCD13(1) ODCD12(1) ODCD<11:8>
7:0 ODCD<7:0>
BF88_60F4 ODCDCLR 31:0 Write clears selected bits in ODCD, read yields undefined value
BF88_60F8 ODCDSET 31:0 Write sets selected bits in ODCD, read yields undefined value
BF88_60FC ODCDINV 31:0 Write inverts selected bits in ODCD, read yields undefined value

PIC32MX3XX/4XX
TABLE 12-5: PORTE SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_6100 TRISE 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — TRISE9(1) TRISE8(1)
7:0 TRISE<7:0>
BF88_6104 TRISECLR 31:0 Write clears selected bits in TRISE, read yields undefined value
BF88_6108 TRISESET 31:0 Write sets selected bits in TRISE, read yields undefined value
BF88_610C TRISEINV 31:0 Write inverts selected bits in TRISE, read yields undefined value
BF88_6110 PORTE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — RE9(1) RE8(1)
7:0 RE<7:0>
BF88_6114 PORTECLR 31:0 Write clears selected bits in PORTE, read yields undefined value
BF88_6118 PORTESET 31:0 Write sets selected bits in PORTE, read yields undefined value
BF88_611C PORTEINV 31:0 Write inverts selected bits in PORTE, read yields undefined value
BF88_6120 LATE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — LATE9(1) LATE8(1)
7:0 LATE<7:0>
BF88_6124 LATECLR 31:0 Write clears selected bits in LATE, read yields undefined value
BF88_6128 LATESET 31:0 Write sets selected bits in LATE, read yields undefined value
BF88_612C LATEINV 31:0 Write inverts selected bits in LATE, read yields undefined value
BF88_6130 ODCE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — ODCE9(1) ODCE8(1)
7:0 ODCE<7:0>
BF88_6134 ODCECLR 31:0 Write clears selected bits in ODCE, read yields undefined value
BF88_6138 ODCESET 31:0 Write sets selected bits in ODCE, read yields undefined value
BF88_613C ODCEINV 31:0 Write inverts selected bits in ODCE, read yields undefined value

PIC32MX3XX/4XX
TABLE 12-6: PORTF SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_6140 TRISF 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — TRISF13(1) TRISF12(1) — — — TRISF8(1)
7:0 TRISF7(1) TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
BF88_6144 TRISFCLR 31:0 Write clears selected bits in TRISF, read yields undefined value
BF88_6148 TRISFSET 31:0 Write sets selected bits in TRISF, read yields undefined value
BF88_614C TRISFINV 31:0 Write inverts selected bits in TRISF, read yields undefined value
BF88_6150 PORTF 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — RF13(1) RF12(1) — — — RF8(1)
(1) RF5 RF4 RF3 RF1 RF0
7:0 RF7 RF6 RF2
BF88_6154 PORTFCLR 31:0 Write clears selected bits in PORTF, read yields undefined value
BF88_6158 PORTFSET 31:0 Write sets selected bits in PORTF, read yields undefined value
BF88_615C PORTFINV 31:0 Write inverts selected bits in PORTF, read yields undefined value
BF88_6160 LATF 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — LATF13(1) LATF12(1) — — — LATF8(1)
7:0 LATF7(1) LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0
BF88_6164 LATFCLR 31:0 Write clears selected bits in LATF, read yields undefined value
BF88_6168 LATFSET 31:0 Write sets selected bits in LATF, read yields undefined value
BF88_616C LATFINV 31:0 Write inverts selected bits in LATF, read yields undefined value
BF88_6170 ODCF 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — ODCF13(1) ODCF12(1) — — — ODCF8(1)
7:0 ODCF7(1) ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0
BF88_6174 ODCFCLR 31:0 Write clears selected bits in ODCF, read yields undefined value
BF88_6178 ODCFSET 31:0 Write sets selected bits in ODCF, read yields undefined value
BF88_617C ODCFINV 31:0 Write inverts selected bits in ODCF, read yields undefined value

PIC32MX3XX/4XX
TABLE 12-7: PORTG SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_6180 TRISG 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 TRISG15(1) TRISG14(1) TRISG13(1) TRISG12(1) — — TRISG9 TRISG8
7:0 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1(1) TRISG0(1)
BF88_6184 TRISGCLR 31:0 Write clears selected bits in TRISG, read yields undefined value
BF88_6188 TRISGSET 31:0 Write sets selected bits in TRISG, read yields undefined value
BF88_618C TRISGINV 31:0 Write inverts selected bits in TRISG, read yields undefined value
BF88_6190 PORTG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 RG15(1) RG14(1) RG13(1) RG12(1) — — RG9 RG8
7:0 RG7 RG6 — — RG3 RG2 RG1(1) RG0(1)
BF88_6194 PORTGCLR 31:0 Write clears selected bits in PORTG, read yields undefined value
BF88_6198 PORTGSET 31:0 Write sets selected bits in PORTG, read yields undefined value
BF88_619C PORTGINV 31:0 Write inverts selected bits in PORTG, read yields undefined value
BF88_61A0 LATG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 LATG15(1) LATG14(1) LATG13(1) LATG12(1) — — LATG9 LATG8
7:0 LATG7 LATG6 — — LATG3 LATG2 LATG1(1) LATG0(1)
BF88_61A4 LATGCLR 31:0 Write clears selected bits in LATG, read yields undefined value
BF88_61A8 LATGSET 31:0 Write sets selected bits in LATG, read yields undefined value
BF88_61AC LATGINV 31:0 Write inverts selected bits in LATG, read yields undefined value
BF88_61B0 ODCG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ODCG15(1) ODCG14(1) ODCG13(1) ODCG12(1) — — ODCG9 ODCG8
7:0 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1(1) ODCG0(1)
BF88_61B4 ODCGCLR 31:0 Write clears selected bits in ODCG, read yields undefined value
BF88_61B8 ODCGSET 31:0 Write sets selected bits in ODCG, read yields undefined value
BF88_61BC ODCGINV 31:0 Write inverts selected bits in ODCG, read yields undefined value
2: On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12,
RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain these pins as general pur-
pose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction
TRACE pins, TROEN must be set = 1.

PIC32MX3XX/4XX
TABLE 12-8: CHANGE NOTICE AND PULL-UP SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_61C0 CNCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
7:0 — — — — — — — —
BF88_61C4 CNCONCLR 31:0 Write clears selected bits in CNCON, read yields undefined value
BF88_61C8 CNCONSET 31:0 Write sets selected bits in CNCON, read yields undefined value
BF88_61CC CNCONINV 31:0 Write inverts selected bits in CNCON, read yields undefined value
BF88_61D0 CNEN 31:24 — — — — — — — —
23:16 — — CNEN21(1) CNEN20(1) CNEN19(1) CNEN18 CNEN17 CNEN16
15:8 CNEN<15:8>
7:0 CNEN<7:0>
BF88_61D4 CNENCLR 31:0 Write clears selected bits in CNEN, read yields undefined value
BF88_61D8 CNENSET 31:0 Write sets selected bits in CNEN, read yields undefined value
BF88_61DC CNENINV 31:0 Write inverts selected bits in CNEN, read yields undefined value
BF88_61E0 CNPUE 31:24 — — — — — — — —
(1) (1) (1)
23:16 — — CNPUE21 CNPUE20 CNPUE9 CNPUE18 CNPUE17 CNPUE16
15:8 CNPUE<15:8>
7:0 CNPUE<7:0>
BF88_61E4 CNPUECLR 31:0 Write clears selected bits in CNPUE, read yields undefined value
BF88_61E8 CNPUESET 31:0 Write sets selected bits in CNPUE, read yields undefined value
BF88_61EC CNPUEINV 31:0 Write inverts selected bits in CNPUE, read yields undefined value
Note 1: CNEN and CNPUE bit(s) are not implemented on 64-pin devices, and read as ‘0’.
TABLE 12-9: CHANGE NOTICE INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1070 IEC1 7:0 SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE
BF88_1040 IFS1 7:0 SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF
BF88_10F0 IPC6 23:16 — — — CNIP<2:0> CNIS<1:0>
Note: This summary table contains partial register definitions that only pertain to the GPIO peripheral. Refer to the “PIC32MX Family

PIC32MX3XX/4XX
REGISTER 12-1: TRISx: TRIS REGISTERS
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

TRISx<15:8>
bit 15 bit 8

TRISx<7:0>
bit 7 bit 0
Legend:

bit 15-0 TRISx<15:0>: TRISx Register bits(1)
1 = Corresponding port pin ‘Input’
0 = Corresponding port pin ‘Output’
Note 1: Depending on the device, certain register bits or the entire register may not be implemented. Refer to
Table 12.1 for specific register and bit assignments.

PIC32MX3XX/4XX
REGISTER 12-2: PORTx: PORT REGISTERS
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

Rx<15:8>
bit 15 bit 8

Rx<7:0>
bit 7 bit 0
Legend:

bit 15-0 PORTx<15:0>: PORTx Register bits(1)
Read = Value on port pins
Write = Value written to the LATx register, port latch and I/O pins
Note 1: Depending on the device family variant, certain register bits or the entire register may not be implemented.
Refer to Table 12.1 for specific register and bit assignments.

PIC32MX3XX/4XX
REGISTER 12-3: LATx: LAT REGISTERS
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

LATx<15:8>
bit 15 bit 8

LATx<7:0>
bit 7 bit 0
Legend:

bit 15-0 LATx<15:0>: LATx Register bits(1)
Read = Value on port latch, not I/O pins
Write = Value written to port latch and I/O pins

PIC32MX3XX/4XX
REGISTER 12-4: ODCx: OPEN DRAIN CONFIGURATION REGISTERS
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

ODCx<15:8>
bit 15 bit 8

ODCx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable r = Reserved bit
U = Unimplemented bit, read as ‘0’ -n = Bit value at POR: (‘0’, ‘1’, x = unknown)

bit 15-0 ODCx<15:0>: ODCx Register bits(1)
If a port pin is configured as an output (corresponding TRISx bit = 0).
1 = Port pin open-drain output enabled
0 = Port pin open-drain output disabled
If a port pin is configured as an input, ODCx bits have no effect.

PIC32MX3XX/4XX
REGISTER 12-5: CNCON: CHANGE NOTICE CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

ON FRZ SIDL — — — — —
bit 15 bit 8

— — — — — — — —
bit 7 bit 0
Legend:

bit 15 ON: Change Notice Module On bit
1 = CN module is enabled
0 = CN module is disabled
0 = Continue operation when CPU is in Debug Exception mode
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode

PIC32MX3XX/4XX
REGISTER 12-6: CNEN: INPUT CHANGE NOTIFICATION INTERRUPT ENABLE REGISTER(1)
— — — — — — — —
bit 31 bit 24

— — CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16
bit 23 bit 16

CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8
bit 15 bit 8

CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0
bit 7 bit 0
Legend:

bit 21-0 CNEN<21:0>: CNEN Register bits
If a port pin is configured as an input (corresponding TRISx bit = 1)
1 = Port pin input change notice enabled
0 = Port pin input change notice disabled
If a port pin is configured as an output, CNENx bits have no effect

PIC32MX3XX/4XX
REGISTER 12-7: CNPUE: INPUT CHANGE NOTIFICATION PULL-UP ENABLE(1)
— — — — — — — —
bit 31 bit 24

— — CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16
bit 23 bit 16

CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8
bit 15 bit 8

CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0
bit 7 bit 0
Legend:

bit 21-0 CNPUE<21:0>: CNPUE Register bits
If a port pin is configured as an input (corresponding TRISx bit = 1).
1 = Port pin pull-up enabled
0 = Port pin pull-up disabled
If a port pin is configured as an output, it is recommended to disable the corresponding CNPUEx bit.

PIC32MX3XX/4XX
12.2 Parallel I/O (PIO) Ports 12.2.2 DIGITAL INPUTS
All port pins have three registers (TRIS, LAT, and Pins are configured as digital inputs by setting the cor-
PORT) that are directly associated with their operation. responding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
TRIS is a data direction or tri-state control register that Several digital pins share functionality with analog
determines whether a digital pin is an input or an out- inputs and default to the analog inputs at POR. Setting
put. Setting a TRISx register bit = 1 configures the cor- the corresponding bit in the ADP1CFG register = 1
responding I/O pin as an input; setting a TRISx register enables the pin as a digital pin.
bit = 0 configures the corresponding I/O pin as an out-
put. All port I/O pins are defined as inputs after a device Digital only pins are capable of input voltages up to
Reset. Certain I/O pins are shared with analog 5.5V. Any pin that shares digital and analog
peripherals and default to analog inputs after a device functionality is limited to voltages up to VDD + 0.3V.
Reset. .
TABLE 12-10: MAXIMUM INPUT PIN
PORT is a register used to read the current state of the
VOLTAGES
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx regis- Input Pin Mode(s) VIH (max)
ter, latching the data to the port’s I/O pins. Digital Only VIH = 5.5v
LAT is a register used to write data to the port I/O pins. Digital + Analog VIH = VDD + 0.03v
The LATx latch register holds the data written to either
Analog VIH = VDD + 0.03v
the LATx or PORTx registers. Reading the LATx latch
register reads the last value written to the Note: Refer to Section 30.0 “Electrical Characteris-
corresponding port or latch register. tics” regarding the VIH specification.
Not all port I/O pins are implemented on some devices,
Note: Analog levels on any pin that is defined as
therefore, the corresponding PORTx, LATx and TRISx
a digital input (including the ANx pins) may
register bits will read as zeros. See Section 12.1
cause the input buffer to consume current
“Port Registers”.
that exceeds the device specifications.
12.2.1 CLR, SET AND INV REGISTERS
12.2.3 ANALOG INPUTS
Every I/O module register has a corresponding CLR
Certain pins can be configured as analog inputs used
(clear), SET (set) and INV (invert) register designed to
by the ADC and Comparator modules. Setting the cor-
provide fast atomic bit manipulations. As the name of
responding bits in the ADP1CFG register = 0 enables
the register implies, a value written to a SET, CLR or
the pin as an analog input pin and must have the corre-
INV register effectively performs the implied operation,
sponding TRIS bit set = 1 (input). If the TRIS bit is
but only on the corresponding base register and only
cleared = 0 (output), the digital output level (VOH or
bits specified as ‘1’ are modified. Bits specified as ‘0’
VOL) will be converted. Any time a port I/O pin is config-
are not modified.
ured as analog, its digital input is disabled and the cor-
Reading SET, CLR and INV registers returns undefined responding PORTx register bit will read ‘0’.
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read. 12.2.4 DIGITAL OUTPUTS
To set PORTC bit 0, write to the LATSET register: Pins are configured as digital outputs by setting the cor-
LATCSET = 0x0001; responding TRIS register bits = 0. When configured as
digital outputs, these pins are CMOS drivers or can be
To clear PORTC bit 0, write to the LATCLR register: configured as open drain outputs by setting the corre-
LATCCLR = 0x0001; sponding bits in the ODCx Open-Drain Configuration
To toggle PORTC bit 0, write to the LATINV register: register.
LATCINV = 0x0001; Digital output pin voltage is limited to VDD.
12.2.5 ANALOG OUTPUTS

Note: Using a PORTxINV register to toggle a bit
Certain pins can be configured as analog outputs, such
is recommended because the operation is
as the CVREF output voltage used by the comparator
performed in hardware atomically, using
module. Configuring the Comparator Reference mod-
fewer instructions as compared to the tra-
ule to provide this output will present the analog output
ditional read-modify-write method shown
voltage on the pin, independent of the TRIS register
below:
setting for the corresponding pin.
PORTC ^= 0x0001;

PIC32MX3XX/4XX
12.2.6 OPEN-DRAIN CONFIGURATION Notes: JTAG program/debug port is multiplexed
In addition to the PORT, LAT and TRIS registers for with PORTA pins RA0, RA1, RA4 and RA5
data control, each port pin configured as a digital output on 100-pin devices; PORTB pins RB10,
can also select between an active drive output and RB11, RB12 and RB13 on 64-pin devices.
open-drain output. This is controlled by the Open-Drain At power-on-reset, these pins are con-
Control register, ODCx, associated with each port. trolled by the JTAG port. To use these pins
From POR, when an IO pin is configured as a digital as general purpose I/O pins, the user’s
output, its output is active drive by default. Setting a bit application code must clear JTAGEN
in the ODCx register = 1 configures the corresponding (DDPCON<3>) bit = 0. To maintain these
pin as an open-drain output. pins for JTAG program/debug, the user’s
application code must maintain JTAGEN
The open-drain feature allows the generation of
bit = 1.
outputs higher than VDD, e.g., 5V, on any desired
digital-only pins by using external pull-up resistors. The On specific 100-pin devices, the instruc-
maximum open-drain voltage allowed is the same as tion TRACE port is multiplexed with
the maximum VIH specification, typically 5.5v. PORTA pins RA6, RA7; PORTG pins
RG12, RG13 and RG14. At Power-on
12.2.7 PERIPHERAL MULTIPLEXING Reset, these pins are general purpose I/O
In many cases, I/O pins are multiplexed with more than pins. To maintain these pins as general
one peripheral. A parallel I/O port pin that is multiplexed purpose I/O pins, the user’s application
with a peripheral is, in general, subordinate to the code must maintain TROEN (DDP-
peripheral. CON<2>) bit = 0. To use these pins as
instruction TRACE pins, TROEN must be
When a peripheral is enabled and actively driving the set = 1.
multiplexed pin, the use of the pin as a general purpose
output pin is disabled. The I/O pin may be read, but the 12.2.8 SOFTWARE INPUT PIN CONTROL
output driver for the parallel port bit will be disabled. If,
Some peripheral inputs assigned to an I/O pin may not
however, a peripheral is enabled, but the peripheral is
take control of the I/O pin output driver. If the I/O pin
not actively driving a pin, that pin may be driven by a
associated with the peripheral is configured as an out-
port.
put, using the appropriate TRIS control bit, the user can
The peripheral’s output buffer data and control signals manually affect the state of the peripheral’s input pin
are provided to a pair of multiplexers. The multiplexers through its corresponding LAT register. This behavior
select whether the peripheral or the associated port can be useful in some situations, especially for testing
has ownership of the output data and control signals of purposes, when no external signal is connected to the
the I/O pin. The logic also prevents “loop through”, in input pin.
which a port’s digital output can drive the input of a
In general, the following peripherals allow their input
peripheral that shares the same pin. Figure 12-2 shows
pins to be controlled manually through the LAT
how ports are shared with other peripherals and the
registers:
associated I/O pin to which they are connected.
• External Interrupt pins
In general, the dominant output control of a multiplexed
I/O pin can be determined by the order of the peripheral • Timer Clock Input pins
output names assigned to a pin (read from left to right). • Input Capture pins
Multiplexed peripheral inputs have no priority. • PWM Fault pins
For example, a pin labeled “U1TX/RF3”, indicates the Most serial communication peripherals, when enabled,
UART1 Transmit output, if enabled, has a higher prece- take full control of the I/O pin so that the input pins
dence over PORTF and therefore overrides the output associated with the peripheral cannot be affected
control of this pin. through the corresponding PORT registers. These
peripherals include the following modules:
• SPI
• I2C™
• UART

PIC32MX3XX/4XX
12.2.9 INPUT CHANGE NOTIFICATION TABLE 12-11: CHANGE NOTICE PIN AND
Certain PIC32MX I/O port pins provide Input Change PULL-UP TABLE
notification that can generate interrupt requests to the 64-Pin 100-Pin
processor in response to a Change-Of-State (COS) on Change Weak Device Device
Port Pin
those selected input pins. The initial state of any Notice Pull-Up
enabled Change Notice (CN) pin must be established Pin#
by reading the corresponding PORT register. This fea- CN0 CNPUE0 RC14 48 74
ture is capable of detecting input COS even in Sleep
CN1 CNPUE1 RC13 47 73
mode, when the clocks are disabled. Depending on the
device pin count, there are up to 22 external signals CN2 CNPUE2 RB0 16 25
(CN0 through CN21) that may be selected (enabled) CN3 CNPUE3 RB1 15 24
for generating an interrupt request on a COS. CN4 CNPUE4 RB2 14 23
The following control registers are associated with the CN5 CNPUE5 RB3 13 22
change notice module:
CN6 CNPUE6 RB4 12 21
• CNCON
CN7 CNPUE7 RB5 11 20
• CNEN
CN8 CNPUE8 RG6 4 10
• CNPUE
CN9 CNPUE9 RG7 5 11
The CNCON control register ON bit enables or disables
CN10 CNPUE10 RG8 6 12
the CN module and its ability to generate interrupts or
respond to mismatch conditions. CN11 CNPUE11 RG9 8 14
The CNEN (change notice enable) register control bits CN12 CNPUE12 RB15 30 44
enable each CN input. Setting any of these bits enables CN13 CNPUE13 RD4 52 81
a CN for the corresponding pins. CN14 CNPUE14 RD5 53 82
The CNPUE (change notice pull-up enable) register CN15 CNPUE15 RD6 54 83
control bits enable a weak pull-up to a corresponding
CN16 CNPUE16 RD7 55 84
CN input pin. The pull-ups act as a current source that
is connected to the pin, and eliminate the need for CN17 CNPUE17 RF4 31 49
external resistors when push button or keypad devices CN18 CNPUE18 RF5 32 50
are connected. CN19 CNPUE19 RD13 — 80
CN20 CNPUE20 RD14 — 47
Note: Pull-up resistors on change notification
CN21 CNPUE21 RD15 — 48
pins should always be disabled whenever
the port pin is configured as a digital
output.
12.2.10 CHANGE NOTICE INTERRUPTS
The Change Notice module is enabled as a source of
interrupts via the respective CN interrupt enable bits:
• CNIE (IEC1<0>)
• CNIF (IFS1<0>)
level bits must also be configured:
• CNIP<2:0> (IPC6<20:18>)
• CNIS<1:0> (IPC6<17:16>)
To enable CN interrupts, the ON bit (CNCON<15>)
must = 1, one or more CN input pins must be enabled
and the Change Notice Interrupt Enable bit, CNIE,
must = 1.

PIC32MX3XX/4XX
To prevent possible spurious interrupts when configur- The port must be read first to clear the mismatch con-
ing change notice interrupts, the following steps are dition, then the CN interrupt flag, CNIF (IFS1<0>), can
recommended: be cleared in software. Failing to read the port before
1. Disable CPU interrupts. attempting to clear the CNIF bit may not allow the CNIF
bit to be cleared.
2. Set desired CN I/O pin as input by setting corre-
sponding TRISx register bits = 1. In addition to enabling the CN interrupt, an Interrupt
Note: If the I/O pin is shared with an analog Service Routine (ISR), is required. Example 12-1 and
peripheral, it may be necessary to set the corre- Example 12-2 show a partial code example of an ISR.
sponding AD1PCFG bit = 1 to ensure that the Note: It is the user’s responsibility to clear the
I/O pin is a digital input. corresponding interrupt flag bit before
3. Enable change notice module returning from an ISR.
ON (CNCON<15>) = 1.
4. Enable individual CN input pin(s); enable
optional pull-up(s).
5. Read corresponding PORT registers to clear
mismatch condition on CN input pins.
6. Configure the CN interrupt priority, CNIP<2:0>,
and subpriority CNIS<1:0>.
7. Clear CN interrupt flag, CNIF = 0.
8. Enable CN interrupt enable, CNIE = 1.
9. Enable CPU interrupts.
EXAMPLE 12-1: CHANGE NOTICE CONFIGURATION EXAMPLE

/*
The following code example illustrates a Change Notice
interrupt configuration for pins CN1(PORTC.RC13), CN4(PORTB.RB2) and CN18(PORTF.RF5).
*/
unsigned int value;
/* NOTE: disable vector interrupts prior to configuration */
CNCON = 0x8000; // Enable Change Notice module

CNEN= 0x00040012; // Enable CN1, CN4 and CN18 pins
CNPUE= 0x00040012; // Enable weak pull ups for CN1, CN4 and CN18 pins
/* read port(s) to clear mismatch on change notice pins */

value = PORTB;
value = PORTC;
value = PORTF;
IPS6SET = 0x00140000; // Set priority level=5

IPS6SET = 0x00030000; // Set subpriority level=3
// Could have also done this in single
// operation by assigning IPS6SET = 0x00170000
IFS1CLR = 0x0001; // Clear the interrupt flag status bit

IEC1SET = 0x0001; // Enable Change Notice interrupts
/* re-enable vector interrupts after configuration */

PIC32MX3XX/4XX
EXAMPLE 12-2: CHANGE NOTICE ISR EXAMPLE
/*
The following code example demonstrates a simple interrupt service
routine for CN interrupts. The user’s code at this vector can perform any
application-specific operations. The user’s code must read the CN
corresponding PORT registers to clear the mismatch conditions before
clearing the CN interrupt status flag.
Finally, the CN interrupt status flag must be cleared before exiting.
*/
void __ISR(_CHANGE_NOTICE_VECTOR, ipl5) CN_Interrupt_ISR(void)
{
unsigned int value;
value = PORTB // Read PORTB to clear CN4 mismatch condition

value = PORTC // Read PORTC to clear CN1,CN0 mismatch condition
... perform application specific operations in response to the interrupt
IFS1CLR = 0x0001; // Be sure to clear the CN interrupt status

// flag before exiting the service routine.
}
Note: The CN ISR code example shows MPLAB® C32 C compiler-specific syntax. Refer to your compiler manual
regarding support for ISRs.

PIC32MX3XX/4XX
13.0 TIMER1 13.1 Additional Supported Features
Note: This data sheet summarizes the features • Selectable clock prescaler
of the PIC32MX3XX/4XX family of • Timer operation during CPU Idle and Sleep mode
devices. It is not intended to be a compre- • Fast bit manipulation using CLR, SET and INV
hensive reference source. Refer to the registers
“PIC32MX Family Reference Manual” • Asynchronous mode can be used with the
(DS61132) for a detailed description of this Low-Power Secondary Oscillator to function as a
peripheral. Real-Time Clock (RTC).
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can oper-
ate as a free-running interval timer for various timing
applications and counting external events. This timer
can also be used with the Low-Power Secondary
Oscillator, SOSC, for real-time clock applications. The
following modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
TABLE 13-1: TIMER1 FEATURES

16-bit 32-bit Special
Low-Power Asynchronous
Timer Synchronous Synchronous Gated Timer Event
Oscillator External Clock
Timer/Counter Timer/Counter Trigger
Timer 1 Yes Yes Yes No Yes No

PIC32MX3XX/4XX
FIGURE 13-1: TIMER1 BLOCK DIAGRAM(1)
PR1
Equal
16-bit Comparator TSYNC (T1CON<2>)
1 Sync
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE (T1CON<7>)
Q
TCS (T1CON<1>)
TGATE (T1CON<7>)
ON (T1CON<15>)
SOSCO/T1CK x1
Gate Prescaler
SOSCEN
Sync 10 1, 8, 64, 256
SOSCI
PBCLK 00
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word DEVCFG1.

PIC32MX3XX/4XX
13.2 Timer Registers
TABLE 13-2: TIMER1 SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0600 T1CON 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 ON FRZ SIDL TWDIS TWIP — — —
7:0 TGATE — TCKPS<1:0> — TSYNC TCS —
BF80_0604 T1CONCLR 31:0 Write clears selected bits in T1CON, read yields undefined value
BF80_0608 T1CONSET 31:0 Write sets selected bits in T1CON, read yields undefined value
BF80_060C T1CONINV 31:0 Write inverts selected bits in T1CON, read yields undefined value
BF80_0610 TMR1 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 TMR1<15:8>
7:0 TMR1<7:0>
BF80_0614 TMR1CLR 31:0 Write clears selected bits in TMR1, read yields undefined value
BF80_0618 TMR1SET 31:0 Write sets selected bits in TMR1, read yields undefined value
BF80_061C TMR1INV 31:0 Write inverts selected bits in TMR1, read yields undefined value
BF80_0620 PR1 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 PR1<15:8>
7:0 PR1<7:0>
BF80_0624 PR1CLR 31:0 Write clears selected bits in PR1, read yields undefined value
BF80_0628 PR1SET 31:0 Write sets selected bits in PR1, read yields undefined value
BF80_062C PR1INV 31:0 Write inverts selected bits in PR1, read yields undefined value
TABLE 13-3: TIMER1 INTERRUPT REGISTER SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1060 IEC0 7:0 INT1IE OC1IE IC2IE T1IE INT0IE CS1IE CS0IE CTIE
BF88_1030 IFS0 7:0 INT1IF OC1IF IC2IF T1IF INT0IF CS1IF CS0IF CTIF
BF88_10A0 IPC1 7:0 — — — T1IP<2:0> T1IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer1 peripheral. Refer to the “PIC32MX
Family Reference Manual” (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R-0 r-x r-x r-x

ON FRZ SIDL TWDIS TWIP — — —
bit 15 bit 8
R/W-0 r-x R/W-0 R/W-0 r-x R/W-0 R/W-0 r-x

TGATE — TCKPS<1:0> — TSYNC TCS —
bit 7 bit 0
Legend:

bit 15 ON: Timer On bit
1 = Timer is enabled
0 = Timer is disabled
bit 12 TWDIS: Asynchronous Timer Write Disable bit
In Asynchronous Timer mode:
1 = Writes to asynchronous TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (legacy asynchronous timer functionality)
In Synchronous Timer mode:
This bit has no effect.
bit 11 TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.

PIC32MX3XX/4XX
REGISTER 13-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED)
bit 7 TGATE: Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored and read ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer Input Clock prescaler Select bits
11 = 1:256 prescale value
bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
bit 1 TCS: Timer Clock Source Select bit
1 = External clock from T1CKI pin
0 = Internal peripheral clock

PIC32MX3XX/4XX
13.3 Modes of Operation
The 16-bit Timer1 peripheral can operate as a 13.3.2 SYNCHRONOUS INTERNAL TIMER
synchronous timer using internal or external clock
In this mode, the timer clock source is the internal
sources, or as a gated timer using internal clock source
PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0.
and external clock pin, or as an asynchronous timer
Clock synchronization is not required, therefore the
using an external asynchronous clock source, such as
Timer1 Synchronization bit, TSYNC (T1CON<2>), is
the low-power secondary oscillator. Each mode is
ignored. The TMR1 Count register increments on every
easily configured and described in the following
PBCLK clock cycle when the timer clock prescale
sections.
<TCKPS> is 1:1.
13.3.1 CONSIDERATIONS FOR ALL Timer1 generates a timer match event after the TMR1
TIMER 1 MODES Count register matches the PR1 Period register value
(mid-clock cycle on the falling edge), then resets to
• Timer1 module is disabled and powered off when
0x0000 on the next PBCLK clock cycle. See
the ON bit (T1CON<15>) = 0, thus providing max-
Section 13.5 “Timer Interrupts” regarding timer
imum power savings. All other TxCON bits
events and interrupts.
remain unchanged.
• Updates to the T1CON register should only be For clock prescale = N (other than 1:1), the timer oper-
performed when the timer module is disabled, ON ates at a clock rate = PBCLK/N and the TMRx Count
bit (T1CON<15>) = 0. register increments on every Nth PBCLK clock. For
further details regarding the timer prescaler, refer to
• Timer1 continues operating when the CPU goes
Section 13.4.2 “Timer Clock Prescaler”.
into Idle mode if the “Stop In Idle mode” control bit
is disabled, SIDL (TxCON<13>) bit = 0. If The following steps should be performed to properly
enabled, SIDL = 1, the timer module stops configure the Timer1 peripheral for Timer mode
operation while the CPU is in Idle mode. operation.
• Setting or clearing the ON bit (T1CON<15>) and 1. Clear ON control bit (T1CON<15>) = 0 to
any other bits in T1CON in the same instruction disable timer.
may cause undefined behavior. The user is 2. Configure TCKPS control bits (T1CON<5:4) to
advised to program the T1CON register with the select desired timer clock prescale.
desired settings with one instruction, and then set 3. Set TCS control bit (T1CON<1>) = 0 to select
the ON bit in a subsequent instruction. the internal PBCLK clock source.
4. Clear TMR1 register.
5. Load PR1 register with desired 16-bit match
value.
6. If timer interrupts are to be used, refer to
Section 13.5 “Timer Interrupts” for interrupt
configuration steps.
7. Set ON control bit = 1 to enable Timer.
EXAMPLE 13-1: SYNCHRONOUS

INTERNAL TIMER
INITIALIZATION
T1CON = 0x0 // Stop and Init Timer
TMR1 = 0x0; // Clear timer register
PR1 = 0xFFFF; // Load period register
T1CONSET = 0x8000;// Start Timer

PIC32MX3XX/4XX
13.3.3 SYNCHRONOUS EXTERNAL TIMER EXAMPLE 13-2: SYNCHRONOUS
In this mode, the timer clock source is an external clock EXTERNAL TIMER
source or pulse applied to the T1CK pin, TCS INITIALIZATION
(T1CON<1>) = 1. To provide synchronization, Timer1 T1CON = 0x0; // Stop Timer and reset
synchronization bit TSYNC (T1CON<2>) must be set T1CON = 0x0036 // Set prescaler=1:256,
(= 1). The 16-bit TMR1 Count register increments on // external clock,
every synchronized rising edge of an external clock // synchronous mode
when the timer clock prescale <TCKPS> is 1:1.
Timer1 generates a timer match event after the TMR1 PR1 = 0x3FFF; // Load period register
Count register matches the PR1 Period register value
(mid-clock cycle on the falling edge), then resets to T1CONSET = 0x8000; // Start Timer
0x0000 on the next synchronized external clock cycle.
The timer continues to increment and repeat the period
match until the timer is disabled. For further details 13.3.4 ASYNCHRONOUS EXTERNAL
regarding timer events and interrupts, see TIMER
Section 13.5 “Timer Interrupts”. In this mode, the timer clock source is an external clock
For clock prescale = N (other than 1:1), the timer oper- source or pulse applied to the T1CK pin, TCS
ates at a clock rate = (external clock/N), therefore, the (T1CON<1>) = 1. Clock synchronization is not
TMRx Count register increments on every Nth external required, therefore, the Timer1 clock synchronization
synchronized clock cycle. For further details regarding bit should be cleared, TSYNC (T1CON<2>) = 0. The
timer prescaler, refer to Section 13.4.2 “Timer Clock 16-bit TMR1 Count register increments on every rising
Prescaler”. edge of an external clock when the timer clock prescale
<TCKPS> is 1:1.
13.3.3.1 Considerations Timer1 generates a timer match event after the TMR1
• When using an external clock source, regardless Count register matches the PR1 register value (mid-
of the Timer1 prescale value, 2-3 external clock clock cycle on the falling edge), then resets to 0x0000
cycles are required, after the ON bit = 1, before on the next external clock cycle. The timer continues to
the TMR1 register begins incrementing. increment and repeat the period match until the timer is
• Timer1 will not operate from a synchronized exter- disabled. For further details regarding timer events and
nal clock source while the CPU is in SLEEP interrupts, see Section 13.5 “Timer Interrupts”.
mode, since the synchronizing PB clock is For clock prescale = N (other than 1:1), the timer oper-
disabled during Sleep mode. ates at a clock rate = (external clock/N), therefore, the
The following steps should be performed to properly TMR1 Count register increments on every Nth exter-
configure the Timer1 peripheral for Synchronous Coun- nal clock cycle. For further details regarding the timer
ter mode operation. prescaler, refer to Section 13.4.2 “Timer Clock
Prescaler”.
1. Clear control bit, ON (T1CON<15>) = 0, to
disable Timer1. 13.3.4.1 Considerations
2. Select the desired timer prescaler using bits,
TCKPS<1:0> (T1CON<5:4). • Regardless of the Timer1 prescale setting, 2-3
3. Set control bit, TCS (T1CON<1>) = 1, to select external clocks are required after the ON bit = 1,
before the TMR1 register begins incrementing.
an external clock source.
4. Set control bit, TSYNC (T1CON<2>) = 1, to • Timer1 can operate while the CPU is in Sleep
enable synchronization. mode.
5. Clear Timer register TMR1. • The Timer1 interrupt can be used to wake the
6. Load Period register PR1 with desired CPU from Sleep mode.
16-bit match value. • Typical use is with the Secondary Low-Power
7. If timer interrupts are used, refer to Section 13.5 Oscillator, SOSC and RTCC Real-Time Clock
“Timer Interrupts” for interrupt configuration Calendar peripheral.
steps. Note: The SOSC oscillator may be used by the
8. Set control bit, ON (T1CON<15>) = 1, to enable CPU as a low-power clock source. Timer 1
Timer1. does not have exclusive usage to this
oscillator. Refer to the “PIC32MX Family
Reference Manual” (DS61132) regarding
the operation of the Secondary Low-
Power Oscillator.

PIC32MX3XX/4XX
13.4 Reading and Writing TMR1 EXAMPLE 13-3: ASYNCHRONOUS
Register EXTERNAL TIMER
INITIALIZATION
Due to the asynchronous nature of Timer1 operating in
Asynchronous Clock mode, reading and writing to the T1CON = 0x0; // Stop Time and reset
TMR1 Count register requires synchronization T1CON = 0x0012; // Set prescaler at 1:8,
// external clock source,
between the asynchronous clock source and the inter-
// asynchronous mode
nal PBCLK (Peripheral Bus Clock). Timer1 features a TMR1 = 0x0; // Clear timer register
Timer Write Disable (TWDIS) control bit (T1CON<12>) PR1 = 0x7FFF; // Load period register
and a TWIP (TImer Write in Progress) Status bit
(T1CON<11>). These bits provide the user with 2 T1CONSET = 0x8000; // Start Timer
options for safely writing to the TMR1 Count register
while Timer1 is enabled. These bits have no affect in
Synchronous Clock modes.
• Option 1 – Legacy Timer1 Write mode, TWDIS bit
= 0. To determine when it is safe to write to the
TMR1 Count register, it is recommended to poll
the TWIP bit. When TWIP = 0, it is safe to perform
the next write operation to the TMR1 Count regis-
ter. When TWIP = 1, the previous write operation
to the TMR1 Count register is still being synchro-
nized and any additional write operations should
wait until TWIP = 0.
• Option 2 – New synchronized Timer1 Write mode,
TWDIS bit = 1. A write to the TMR1 Count register
can be performed at any time. However, if the pre-
vious write operation to the TMR1 Count register
is still being synchronized, any additional write
operations are ignored.
Writing to the TMR1 Count register requires 2 to 3
asynchronous external clock cycles for the value to be
synchronized into the TMR1 Count register.
Reading from the TMR1 Count register requires 2
PBCLK cycle delays between the current unsynchro-
nized value in the TMR1 Count register and the
synchronized value returned by the read operation. In
other words, the value read is always 2 PBCLK cycles
behind the actual value in the TMR1 Count register.
The following steps should be performed to properly
configure the Timer1 peripheral for Asynchronous
Counter mode operation.
1. Clear control bit, ON (T1CON<15>) = 0, to
disable Timer1.
TCKPS<1:0> (T1CON<5:4).
3. Set control bit, TCS (T1CON<1>) = 1, to select
4. Set control bit, TSYNC (T1CON<2>) = 0, to
disable synchronization.
5. Clear Timer Register, TMR1.
6. Load Period Register, PR1, with desired 16-bit
match value.
7. If timer interrupts are used, refer to 13.5 “Timer
Interrupts” for interrupt configuration steps.
8. Set control bit, ON (T1CON<15>) = 1, to enable
Timer1.

PIC32MX3XX/4XX
13.4.1 Synchronous Internal Gated Timer EXAMPLE 13-4: SYNCHRONOUS
In this mode, the timer clock source can only be the INTERNAL GATED TIMER
internal PBCLK (Peripheral Bus Cock), TCS INITIALIZATION
(T1CON<1>) = 0. The T1CK pin provides the gating T1CON = 0x0; // Stop Timer and reset
mechanism to enable and disable the timer counting, T1CON = 0x0060; // Enable gated mode,
TGATE (T1CON<7>) = 1. Clock synchronization is not // prescaler at 1:64,
required, therefore Timer1 synchronization bit, TSYNC // internal clock source
(T1CON<2>), is ignored. The 16-bit TMR1 Count reg- TMR1 = 0x0; // Clear timer register
ister is enabled on the rising edge of the T1CK pin and PR1 = 0xFFFF; // Load period register
increments on every internal PBCLK cycle when the
timer clock prescale <TCKPS> is 1:1.
The timer increments until the TMR1 Count register
matches the PR1 register value. The TMR1 Count reg- 13.4.2 TIMER CLOCK PRESCALER
ister resets to 0x0000 on the next PBCLK clock cycle. Timer clock prescale bits, TCKPS<1:0>
A timer match event is not generated. The timer contin- (T1CON<5:4>), are used to divide the timer clock
ues to increment and repeat the period match until the source, permitting the TMR register to increment on
falling edge of the T1CK pin or the timer is disabled. On every 1, 8, 64, or 256 (PBCLK or external) clock cycles.
the falling edge of the gate signal, a timer gate event is For example, if the clock prescale is 1:8, then the timer
generated and the TMR1 Count register stops count- increments on every 8th timer clock cycle.
ing, but is not reset to 0x0000. The TMR1 Count regis-
Associated with the clock prescale selection bits is a
ter must be reset in software. For further details
prescale counter. This prescale counter is cleared
regarding timer events and interrupts, see
when any of the following conditions occur:
Section 13.5 “Timer Interrupts”.
• Any device Reset, except a Power-on Reset
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMR1 • The timer is disabled
Count register increments on every Nth PBCLK clock • A write to the TMR register
cycle. For further details regarding timer prescaler, Note: When the timer clock source is external
refer to Section 13.4.2 “Timer Clock Prescaler”. and the timer clock prescale = N (other
The following steps should be performed to properly than 1:1), 2 to 3 external clock cycles are
configure the Timer1 peripheral for Gated Timer mode required to reset and synchronize the
operation: prescaler.
1. Clear control bit, ON (T1CON<15>) = 0, to • When the timer clock source is external and the
disable Timer1. timer clock prescale = N (other than 1:1), 2 to 3
2. Select the desired timer prescaler using bits, external clock cycles are required, after the timer
TCKPS<1:0> (T1CON<5:4>). ON bit is set = 1, before the TMR1 Count register
increments.
3. Set control bit, TCS (T1CON<1>) = 0, to select
the internal clock source. • After a timer match event (TMR1 = PR1) and
depending on the timer clock prescale setting N
4. Set control bit TGATE (T1CON<6>) = 1.
(other than 1:1), the timer will require N/2 addi-
5. Clear Timer register, TMR1. tional (PBCLK or external) clock cycles before the
6. Load Period register, PR1, with desired TMR1 Counter register reset to 0x0000. Reading
16-bit match value. the TMR1 Count register just after the timer match
7. If timer interrupts are used, refer to Section 13.5 event, but before the TMR1 Count register is rest,
“Timer Interrupts” for interrupt configuration will return the timer match value.
steps.
8. Set control bit ON, (T1CON<15>) = 1, to enable
Timer1.

PIC32MX3XX/4XX
13.5 Timer Interrupts
Timer1 can generate an interrupt on a period match
event or a gate event, caused by the falling edge of the
external gate signal.
Timer1 sets the interrupt flag bit, T1IF (IFS0<4>),
whenever a Timer1 event is generated. Refer to a spe-
cific Timer mode for details regarding event conditions.
When a Timer1 event is generated, the interrupt flag bit
is set within 1 PBCLK + 2 SYSCLK cycles. If Timer1
Interrupt Enable bit is set, T1IE (IEC0<4>) = 1, an
interrupt is generated.
The Timer1 module is enabled as a source of interrupts
through its respective interrupt enable bit, T1IE
(IEC0<4>). The Timer1 Interrupt Flag, T1IF (IFS0<4>),
must be cleared in software.
• T1IP<2:0> (IPC1<4:2>)
• T1IS<1:0> (IPC1<1:0)
Setting Timer1 interrupt priority level = 0 effectively
disables the timer’s ability to generate an interrupt.
In addition to enabling the Timer1 interrupt, an Interrupt
Service Routine, ISR, is generally required. Below is a
partial code example of an ISR.
EXAMPLE 13-5: TIMER INTERRUPT AND PRIORITIES

T1CON = 0x0 // Stop the Timer and Reset Control register
// Set prescaler at 1:1, internal clock source

IPC1SET = 0x000C; // Set priority level=3

IPC1SET = 0x0001; // Set subpriority level=1
// operation by assigning IPC1SET = 0x000D
IFS0CLR = 0x0010; // Clear Timer interrupt status flag

IEC0SET = 0x0010; // Enable Timer interrupts
T1CONSET = 0x8000; // Start Timer
EXAMPLE 13-6: TIMER ISR

void __ISR(_TIMER_1_VECTOR, ipl3) T1_Interrupt_ISR(void)
{
IFS0CLR = 0x0010; // Be sure to clear the Timer 1 interrupt status

}
Note: The timer ISR code example shows MPLAB® C32 C Compiler specific syntax. Refer to your compiler
manual regarding support for ISRs.

PIC32MX3XX/4XX
Table 13-4 provides a summary of I/O pin resources
associated with Timer1. The table shows the settings
required to make each I/O pin work with a specific timer
module.
TABLE 13-4: I/O PIN CONFIGURATION FOR USE WITH THE TIMER MODULE
Required Settings for Module
Pin Control
I/O Pin Module Bit Pin Buffer

Required TRIS Description
Name Enable(2) Field(2) Type Type
T1CK Yes(1) ON TCS, Input I ST Timer1 External Clock/Gate Input

TGATE
Legend:
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
Note 1: This pin is only required for Gated Timer or External Synchronous Clock modes. Otherwise, this pin can be used for general
purpose I/O and requires the user to set the corresponding TRIS control register bits.
2: This bit is located in the T1CON register.

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
14.0 TIMERS 2, 3, 4, 5 14.1 Additional Supported Features
Note: This data sheet summarizes the features of • Selectable clock prescaler
the PIC32MX3XX/4XX family of devices. It • Timers operational during CPU IDLE
is not intended to be a comprehensive refer- • Time base for input capture and output compare
ence source. Refer to the “PIC32MX Family modules (Timer2 and Timer3 only)
Reference Manual” (DS61132) for a • ADC event trigger (Timer3 only)
• Fast bit manipulation using CLR, SET and INV
This family of PIC32MX devices features four registers
synchronous 16-bit timers (default) that can operate as Table 14-1 highlights the available features of these
a free-running interval timer for various timing applica- timers.
tions and counting external events. The following
modes are supported:
• Synchronous Internal 16-bit Timer
• Synchronous Internal 16-bit Gated Timer
• Synchronous External 16-bit Timer
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
• Synchronous Internal 32-bit Timer
• Synchronous Internal 32-bit Gated Timer
• Synchronous External 32-bit Timer
Note: Throughout this chapter, references to

registers TxCON, TMRx, and PRx use ‘x’
to represent Timer2 through 5 in 16-bit
modes. In 32-bit modes, ‘x’ represents
Timer2 or 4; ‘y’ represents Timer3 or 5.
TABLE 14-1: TIMER FEATURES

16-bit 32-bit Special
Low-Power Asynchronous Synchronous
Timers Synchronous Gated Timer Event
Oscillator External Clock
Timer Timer(1) Trigger
2, 4 No No Yes Yes Yes No
3, 5 No No Yes Yes Yes Yes(2)
Note 1: 32-bit mode requires combining timers 2 and 3 or timers 4 and 5.
2: ADC event trigger supported by Timer3 only.

PIC32MX3XX/4XX
FIGURE 14-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
TMRx Sync
(Note 1)
ADC Event
Trigger Comparator x 16
Equal
PRx
Reset
0
TxIF
Event Flag 1 Q D TGATE (TxCON<7>)
Q TCS (TxCON<1>)
TGATE (TxCON<7>)
ON (TxCON<15>)
(Note 2)
TxCK x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK 00
3
Note 1: ADC event trigger is available on Timer3 only. TCKPS (TxCON<6:4>)
2: TxCK pins not available on 64-pin devices.
FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)
Reset
TMRy TMRx Sync
(Note 3)
MSHalfWord LSHalfWord
ADC Event
Trigger 32-bit Comparator
Equal
PRy PRx
TyIF Event 0
Flag
1 Q D TGATE (TxCON<7>)
Q TCS (TxCON<1>)
TGATE (TxCON<7>)
ON (TxCON<15>)
(Note 2)
TxCK x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK 00
3
TCKPS (TxCON<6:4>)
Note 1: In this diagram, the use of “x’ in registers TxCON, TMRx, PRx, TxCK refers to either
Timer2 or Timer4; the use of ‘y’ in registers TyCON, TMRy, PRy, TyIF refers to either Timer3 or Timer5.
2: TxCK pins not available on 64-pin devices.
3: ADC event trigger is available only on Timer2/3 pair.

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0800 T2CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
7:0 TGATE TCKPS<2:0> T32 — TCS —
BF80_0804 T2CONCLR 31:0 Write clears selected bits in T2CON, read yields undefined value
BF80_0808 T2CONSET 31:0 Write sets selected bits in T2CON, read yields undefined value
BF80_080C T2CONINV 31:0 Write inverts selected bits in T2CON, read yields undefined value
BF80_0810 TMR2 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 TMR2<15:8>
7:0 TMR2<7:0>
BF80_0814 TMR2CLR 31:0 Write clears selected bits in TMR2, read yields undefined value
BF80_0818 TMR2SET 31:0 Write sets selected bits in TMR2, read yields undefined value
BF80_081C TMR2INV 31:0 Write inverts selected bits in TMR2, read yields undefined value
BF80_0820 PR2 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 PR2<15:8>
7:0 PR2<7:0>
BF80_0824 PR2CLR 31:0 Write clears selected bits in PR2, read yields undefined value
BF80_0828 PR2SET 31:0 Write sets selected bits in PR2, read yields undefined value
BF80_082C PR2INV 31:0 Write inverts selected bits in PR2, read yields undefined value

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1060 IEC0 15:8 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE
BF88_1030 IFS0 15:8 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF
BF88_10B0 IPC2 7:0 — — — T2IP<2:0> T2IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer2 peripheral. Refer to the “PIC32MX Fam-
ily Reference Manual” (DS61132) for a detailed description of these registers.

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0A00 T3CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
7:0 TGATE TCKPS<2:0> — — TCS —
BF80_0A04 T3CONCLR 31:0 Write clears selected bits in T3CON, read yields undefined value
BF80_0A08 T3CONSET 31:0 Write sets selected bits in T3CON, read yields undefined value
BF80_0A0C T3CONINV 31:0 Write inverts selected bits in T3CON, read yields undefined value
BF80_0A10 TMR3 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 TMR3<15:8>
7:0 TMR3<7:0>
BF80_0A14 TMR3CLR 31:0 Write clears selected bits in TMR3, read yields undefined value
BF80_0A18 TMR3SET 31:0 Write sets selected bits in TMR3, read yields undefined value
BF80_0A1C TMR3INV 31:0 Write inverts selected bits in TMR3, read yields undefined value

PIC32MX3XX/4XX
TABLE 14-3: TIMER3 SFR SUMMARY (CONTINUED)
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0A20 PR3 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 PR3<15:8>
7:0 PR3<7:0>
BF80_0A24 PR3CLR 31:0 Write clears selected bits in PR3, read yields undefined value
BF80_0A28 PR3SET 31:0 Write sets selected bits in PR3, read yields undefined value
BF80_0A2C PR3INV 31:0 Write inverts selected bits in PR3, read yields undefined value
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10C0 IPC3 7:0 — — — T3IP<2:0> T3IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer 3 peripheral. Refer to the PIC32MX Fam-
ily Reference Manual (DS61132) for a detailed description of these registers.
REGISTER 14-5: TIMER4 SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0C00 T4CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
BF80_0C04 T4CONCLR 31:0 Write clears selected bits in T4CON, read yields undefined value
BF80_0C08 T4CONSET 31:0 Write sets selected bits in T4CON, read yields undefined value
BF80_0C0C T4CONINV 31:0 Write inverts selected bits in T4CON, read yields undefined value
BF80_0C10 TMR4 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 TMR4<15:8>
7:0 TMR4<7:0>
BF80_0C14 TMR4CLR 31:0 Write clears selected bits in TMR4, read yields undefined value
BF80_0C18 TMR4SET 31:0 Write sets selected bits in TMR4, read yields undefined value
BF80_0C1C TMR4INV 31:0 Write inverts selected bits in TMR4, read yields undefined value
BF80_0C20 PR4 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 PR4<15:8>
7:0 PR4<7:0>
BF80_0C24 PR4CLR 31:0 Write clears selected bits in PR4, read yields undefined value
BF80_0C28 PR4SET 31:0 Write sets selected bits in PR4, read yields undefined value
BF80_0C2C PR4INV 31:0 Write inverts selected bits in PR4, read yields undefined value
REGISTER 14-6: TIMER4 INTERRUPT REGISTER SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1060 IEC0 23:16 SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE
BF88_1030 IFS0 23:16 SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF
BF88_10D0 IPC4 7:0 — — — T4IP<2:0> T4IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer4 peripheral. Refer to the “PIC32MX Fam-
ily Reference Manual” (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0E00 T5CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
BF80_0E04 T5CONCLR 31:0 Write clears selected bits in T5CON, read yields undefined value
BF80_0E08 T5CONSET 31:0 Write sets selected bits in T5CON, read yields undefined value
BF80_0E0C T5CONINV 31:0 Write inverts selected bits in T5CON, read yields undefined value
BF80_0E10 TMR5 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 TMR5<15:8>
7:0 TMR5<7:0>
BF80_0E14 TMR5CLR 31:0 Write clears selected bits in TMR5, read yields undefined value
BF80_0E18 TMR5SET 31:0 Write sets selected bits in TMR5, read yields undefined value
BF80_0E1C TMR5INV 31:0 Write inverts selected bits in TMR5, read yields undefined value
BF80_0E20 PR5 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 PR5<15:8>
7:0 PR5<7:0>
BF80_0E24 PR5CLR 31:0 Write clears selected bits in PR5, read yields undefined value
BF80_0E28 PR5SET 31:0 Write sets selected bits in PR5, read yields undefined value
BF80_0E2C PR5INV 31:0 Write inverts selected bits in PR5, read yields undefined value

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10E0 IPC5 7:0 — — — T5IP<2:0> T5IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer5 peripheral. Refer to the “PIC32MX

PIC32MX3XX/4XX
14.2 Control Registers
REGISTER 14-9: T2CON, T4CON: TIMER2 AND TIMER4 CONTROL REGISTER

— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 r-x

TGATE TCKPS<2:0> T32 — TCS —
bit 7 bit 0
Legend:

1 = Timer is enabled
0 = Timer is disabled
When TCS = 1:
When TCS = 0:
bit 6-4 TCKPS<2:0>: Timer Input Clock prescaler Select bits

PIC32MX3XX/4XX
bit 3 T32: 32-bit Timer Mode Select bits
1 = TMRx and TMRy form a 32-bit timer
0 = TMRx and TMRy form separate 16-bit timers
1 = External clock from TxCK pin

PIC32MX3XX/4XX
REGISTER 14-10: T3CON, T5CON: TIMER3 AND TIMER5 CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 r-x r-x R/W-0 r-x

TGATE TCKPS<2:0> — — TCS —
bit 7 bit 0
Legend:

1 = Module is enabled
0 = Module is disabled
When TCS = 1:
When TCS = 0:
bit 6-4 TCKPS<1:0>: Timer Input Clock Prescaler Select bits

PIC32MX3XX/4XX
1 = External clock from TxCK pin

PIC32MX3XX/4XX
14.3 Modes of Operation The following steps should be performed to properly
configure the 16-bit Timer peripherals for Timer mode
The 16-bit (default) and 32-bit mode timer peripherals operation:
can operate as synchronous timer/counters using inter-
nal or external clock sources, or as synchronous gated 1. Clear ON control bit, (TxCON<15>) = 0, to
timers using an internal clock source and external disable timer.
clock/gate pins. Each mode is easily configured and 2. Configure TCKPS control bits, (TxCON<6:4), to
described in the following sections. select desired timer clock prescale.
3. Set TCS control bit, (TxCON<1>) = 0, to select
14.3.1 CONSIDERATIONS FOR ALL TIMER the internal PBCLK clock source.
MODES 4. Clear TMRx register.
• A timer module is disabled and powered off when 5. Load PRx register with desired 16-bit match
the ON bit (TxCON<15>) = 0, thus providing value.
maximum power savings. All other TxCON bits 6. If timer interrupts are to be used, refer to
remain unchanged. Section 14.4 Timer Interrupts for interrupt
• Updates to the TxCON register should only be configuration steps.
performed when the timer module is disabled, ON 7. Set ON control bit = 1 to enable Timer.
bit (TxCON<15>) = 0.
• A timer continues operating when the CPU goes EXAMPLE 14-1: 16-BIT INTERNAL CLOCK
into Idle mode if the “Stop In Idle mode” control bit COUNTER/TIMER
is disabled, SIDL (TxCON<13>) bit = 0. If INITIALIZATION
enabled, SIDL = 1, the timer module stops
operation while the CPU is in Idle mode. T2CON = 0x0; //Stop and Init Timer
• Setting or clearing the ON bit (TxCON<15>) and
TMR2 = 0x0; //Clear timer register
any other bits in the TxCON register during a
single instruction may cause undefined behavior. PR2 = 0xFFFF; //Load period register
The user is advised to program the TxCON
register with the desired settings with one instruc- T2CONSET = 0x8000; // Start Timer
tion, and then set the ON bit in a subsequent
instruction.
14.3.2 16-BIT INTERNAL CLOCK

COUNTER/TIMER MODE
In this mode, the timer clock source is the internal
PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0.
The 16-bit TMRx Count register increments on every
internal PBCLK cycle when the timer clock prescale
<TCKPS> is 1:1.
The timer generates a timer match event after the
TMRx Count register matches the PRx Period register
value, then resets to 0x0000 on the next PBCLK clock
cycle. The timer continues to increment and repeat the
period match until the timer is disabled. For further
details regarding timer events and interrupts, see
Section 14.4 Timer Interrupts.
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMRx
Count register increments on every Nth PBCLK clock
cycle. For further details regarding timer prescaler,
refer to Section 14.3.9 Timer Clock Prescaler.

PIC32MX3XX/4XX
14.3.3 16-BIT SYNCHRONOUS EXTERNAL 14.3.4 16-BIT GATED CLOCK COUNTER/
CLOCK COUNTER/TIMER MODE TIMER MODE
In this mode, the timer clock source is an external clock In this mode, the timer clock source can only be the
source or pulse applied to the TxCK pin, TCS internal PBCLK (Peripheral Bus Clock), TCS
(TxCON<1>) = 1. The 16-bit TMRx Count register (TxCON<1>) = 0. The TxCK pin provides the gating
increments on every rising edge of an external clock mechanism to enable and disable the timer counting,
when the timer clock prescale <TCKPS> is 1:1. TGATE (TxCON<7>) = 1. The 16-bit TMRx Count reg-
ister is enabled on the rising edge of the TxCK pin and
Note: TxCK pins not available on 64-pin devices.
increments on every internal PBCLK cycle when the
The timer generates a timer match event after the timer clock prescale <TCKPS> is 1:1.
TMRx Count register matches the PRx register value,
then resets to 0x0000 on the next external clock cycle.
The timer continues to increment and repeat the period The timer increments until the TMRx Count register
match until the timer is disabled. For further details matches the PRx register value. The TMRx Count reg-
regarding timer events and interrupts, see ister resets to 0x0000 on the next PBCLK clock cycle.
Section 14.4 Timer Interrupts. A timer match event is not generated. The timer contin-
For clock prescale = N (other than 1:1), the timer ues to increment and repeat the period match until the
operates at a clock rate = (external clock/N); there- falling edge of the TxCK pin or the timer is disabled. On
fore, the TMRx Count register increments on every the falling edge of the gate signal, a timer gate event is
Nth external clock cycle. For further details regarding generated and the TMRx Count register stops count-
the timer prescaler, refer to Section 14.3.9 Timer ing, but is not reset to 0x0000. The TMRx Count regis-
Clock Prescaler. ter must be reset in software. For further details
regarding timer events and interrupts, see
The following steps should be performed to properly Section 14.4 Timer Interrupts.
configure the timer peripheral for Synchronous Counter
mode operation: For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMRx
1. Clear control bit, ON (TxCON<15>) = 0, to Count register increments on every Nth PBCLK clock
disable timer. cycle. For further details regarding timer prescaler,
2. Select the desired timer prescaler using bits, refer to Section 14.3.9 Timer Clock Prescaler.
TCKPS<2:0> (TxCON<6:4).
3. Set control bit, TCS (TxCON<1>) = 1, to select configure the timer peripheral for Gated Timer mode
an external clock source. operation:
4. Clear Timer register, TMRx.
1. Clear control bit, ON (TxCON<15>) = 0, to
5. Load Period register, PRx, with desired 16-bit disable Timer.
match value.
6. If timer interrupts are used, refer to Section 14.4 TCKPS<2:0> (TxCON<6:4>).
Timer Interrupts for interrupt configuration
3. Set control bit, TCS (TxCON<1>) = 0, to select
steps.
the internal clock source.
7. Set control bit, ON (TxCON<15>) = 1, to enable
4. Set control bit, TGATE (TxCON<7>) = 1.
timer.
EXAMPLE 14-2: 16-BIT SYNCHRONOUS 6. Load Period register, PRx, with desired 16-bit
match value.
EXTERNAL CLOCK
COUNTER/TIMER 7. If timer interrupts are to be used, refer to
Section 14.4 Timer Interrupts for interrupt
INITIALIZATION
configuration steps.
T3CON = 0x0; //Stop and Init Timer 8. Set control bit, ON (TxCON<15>) = 1, to enable
timer.
T3CONSET = 0x0072; //Prescaler=1:256,
//external clock
TMR3 = 0x0; //Clear timer register
PR3 = 0x3FFF; //Load period register
T3CONSET = 0x8000;//Start Timer

PIC32MX3XX/4XX
EXAMPLE 14-3: 16-BIT GATED CLOCK The following steps should be performed to properly
COUNTER/TIMER configure the 32-bit timer peripherals for Timer mode
INITIALIZATION operation.
T4CON = 0x0; //Stop and Init Timer
disable timer.
T4CON = 0x00E0; //Enable gated mode, 2. Set control bit, T32 (TxCON<3>).
//prescaler=1:64, 3. Select the desired timer prescaler using bits
//internal clock TCKPS<2:0> (TxCON<6:4>).
TMR4 = 0; //Clear timer register
PR4 = 0xFFFF; //Load period register the internal clock source.
5. Clear Timer register, TMRxy.
T4CONSET = 0x8000;//Start Timer 6. Load Period register, PRxy, with desired 32-bit
match value.
14.3.5 32-BIT INTERNAL CLOCK 7. If timer interrupts are used, refer to Section 14.4
COUNTER/TIMER MODE Timer Interrupts for interrupt configuration
steps.
In this mode, T32 (TxCON<3>) = 1 and the timer clock
source is the internal PBCLK (Peripheral Bus Clock),
timer.
TCS (TxCON<1>) = 0. The 32-bit TMRxy Count regis-
ter increments on every internal PBCLK cycle when the
timer clock prescale <TCKPS> is 1:1. EXAMPLE 14-4: 32-BIT INTERNAL CLOCK
COUNTER/TIMER
INITIALIZATION
TMRxy Count register matches the PRxy Period regis-
ter value, then resets to 0x00000000 on the next T4CON = 0x0; //Stop Timer4 and clear
PBCLK clock cycle. The timer continues to increment T5CON = 0x0; //Stop Timer5 and clear
and repeat the period match until the timer is disabled. T4CONSET = 0x0038; // Enable 32-bit mode,
For further details regarding timer events and // prescaler at 1:8,
// internal clock
interrupts, see Section 14.4 Timer Interrupts.
TMR4 = 0x0; // Clear TMR4 and TMR5
For clock prescale = N (other than 1:1), the timer oper- // Same as TMR4 = 0x0
ates at a clock rate = (PBCLK/N); therefore, the TMRxy PR4 = 0xFFFFFFFF; // Load PR4 and PR5
Count register increments on every Nth PBCLK clock // with 32-bit value
cycle. For further details regarding the timer prescaler, // Same as PR4=0xFFFFFFFF
refer to Section 14.3.9 Timer Clock Prescaler. T4CONSET = 0x8000; // Start Timer
14.3.6 CONSIDERATIONS
• 32-bit timer pairs can be created using Timer2
with Timer3, or Timer4 with Timer5.
• With Timer2 or Timer4 enabled, setting the T32 bit
(T2CON<3> or T4CON<3>) = 1 automatically
enables the corresponding Timer3 or Timer5
module. For this reason, it is not necessary to
manually enable Timer3 or Timer5.
• T2CON and T4CON control registers are used for
configuring the 32-bit timer operations; Writes to
T3CON and T5CON are ignored.
• T2CK and T4CK input pins are utilized for the 32-
bit gated timer or external synchronous counter
operations; T3CK and T5CK are ignored.
• 32-bit timer interrupts use Timer3 or Timer5 inter-
rupt enable bits and interrupt flag bits; Timer2 and
Timer4 interrupt enable and interrupt flag bits are
ignored.
• Load TMRxy pair by writing the 32-bit value to
TMRx.
• Load PRxy pair by writing the 32-bit value to PRx.

PIC32MX3XX/4XX
14.3.7 32-BIT SYNCHRONOUS EXTERNAL 14.3.8 32-BIT GATED CLOCK
CLOCK COUNTER/TIMER MODE COUNTER/TIMER MODE
In this mode, T32 (TxCON<3>) = 1 and the timer clock In this mode, the timer clock source is the internal
source is an external clock source or pulse applied to PBCLK (Peripheral Bus Clock), TCS (TxCON<1>) = 0.
the TxCK pin, TCS (TxCON<1>) = 1. The 32-bit TMRxy The TxCK pin provides the gating mechanism to
Count register increments on every synchronized rising enable and disable the timer counting, TGATE
edge of an external clock when the timer clock prescale (TxCON<7>) = 1. The 32-bit TMRxy Count register is
<TCKPS> is 1:1. enabled on the rising edge of the TxCK pin and incre-
ments on every internal PBCLK cycle when the timer
clock prescale <TCKPS> is 1:1.
TMRxy Count register matches the PRxy register
value, then resets to 0x00000000 on the next external The timer increments until the TMRxy Count register
clock cycle. The timer continues to increment and matches the PRxy register value. The TMRxy Count
repeat the period match until the timer is disabled. For register resets to 0x00000000 on the next PBCLK clock
further details regarding timer events and interrupts, cycle. A timer match event is not generated. The timer
see Section 14.4 Timer Interrupts. continues to increment and repeat the period match
For clock prescale = N (other than 1:1), the timer until the falling edge of the TxCK pin or the timer is dis-
operates at a clock rate = (external clock/N); there- abled. On the falling edge of the gate signal, a timer
fore, the TMRxy Count register increments on every gate event is generated and the TMRxy Count register
Nth external clock cycle. For further details regarding stops counting, but is not reset to 0x00000000. The
timer prescaler, refer to Section 14.3.9 Timer Clock TMRxy Count register must be reset in software. For
Prescaler. further details regarding timer events and interrupts,
see Section 14.4 Timer Interrupts.
configure the 32-bit timer peripheral for Synchronous For clock prescale = N (other than 1:1), the timer oper-
Counter mode operation: ates at a clock rate = (PBCLK/N); therefore, the TMRxy
Count register increments on every Nth timer clock
1. Clear control bit, ON (TxCON<15>) = 0, to cycle. For further details regarding timer prescaler,
disable Timer. refer to Section 14.3.9 Timer Clock Prescaler.
2. Set control bit, T32 (TxCON<3>).
3. Select the desired timer prescaler using bits configure the timer peripheral for Gated Timer mode
TCKPS<2:0> (TxCON<6:4>). operation:
disable timer.
2. Set control bit, T32 (TxCON<3>).
6. Load Period register, PRx, with desired 32-bit
3. Select the desired timer prescaler using bits
match value.
TCKPS<2:0> (TxCON<6:4>).
7. If timer interrupts are used, refer to Section 14.4
Timer Interrupts for interrupt configuration
the internal clock source.
steps.
5. Set control bit, TGATE (TxCON<7>) = 1.
timer. 6. Clear Timer register, TMRx.
7. Load Period register, PRx, with desired 32-bit
EXAMPLE 14-5: 32-BIT SYNCHRONOUS match value.
EXTERNAL CLOCK 8. Set control bit, ON (TxCON<15>) = 1, to enable
COUNTER/TIMER timer.
INITIALIZATION
T2CON = 0x0; //Stop Timer2 and clear
T2CONSET = 0x006A //32-bit mode,
//external clock,
//prescale=1:64
TMR2 = 0x0; // Clear TMR2 and TMR3
// Same as TMR2 = 0x0
PR2 = 0xFFFFFFFF; // Load PR2 and PR3
// Same as PR2=0xFFFFFFFF
T2CONSET = 0x8000; // Start timer

PIC32MX3XX/4XX
EXAMPLE 14-6: 32-BIT GATED CLOCK
COUNTER/TIMER
INITIALIZATION
T4CONSET = 0x00C8; //32-bit mode,
//gate enable,
//internal clock,
//1:16 prescale
TMR4 = 0x0; //Clear TMR4 and TMR5
//Same as TMR4 = 0x0
PR4 = 0xFFFFFFFF; //Load PR4 and PR5 regs
//Same as PR4 =0xFFFFFFFF
T4CONSET = 0x8000; //Start 32-bit timer
14.3.9 TIMER CLOCK PRESCALER

Timer clock prescale bits, TCKPS<1:0>
(TxCON<6:4>), are used to divide the timer clock
source permitting the TMR register to increment on
every 1, 2, 4, 8, 16, 32, 64, or 256 (PBCLK or external)
clock cycles. For example, if the clock prescale is 1:8,
then the timer increments on every 8th timer clock
cycle.
14.3.10 CONSIDERATIONS
Associated with the clock prescale selection bits is a
prescale counter. The timer prescale counter is cleared
when any of the following conditions occur:
1. Any device Reset, except a Power-on Reset.
2. The timer is disabled.
3. Any write to the TMR register.
Note: When the timer clock source is external and
the timer clock prescale = N (other than
1:1), 2 to 3 external clock cycles are
required to reset and synchronize the
prescaler.
• When the timer clock source is external and the
timer clock prescale = N (other than 1:1), 2 to 3
external clock cycles are required, after the timer
ON bit is set = 1, before the TMRx Count register
increments.
• After a timer match event (TMRx = PRx) and
depending on the timer clock prescale setting N
(other than 1:1), the timer will require N additional
(PBCLK or external) clock cycles before the
TMRx Counter register resets to 0x0000. Reading
the TMRx Count register just after the timer match
event, but before the TMRx Count register is
reset, will return the timer match value.

PIC32MX3XX/4XX
14.4 Timer Interrupts The interrupt priority level bits and interrupt subpriority
A timer can generate an interrupt on a period match
event or a gate event, caused by the falling edge of the • TxIP<2:0> (IPCx<4:2>)
external gate signal. • TxIS<1:0> (IPCx<1:0)
A timer sets its corresponding interrupt flag bit, TxIF, Setting the timer’s interrupt priority level = 0 effectively
whenever the timer event is generated. Refer to a disables the timer’s ability to generate an interrupt.
specific timer mode for details regarding these event In addition to enabling the timer interrupt, an Interrupt
conditions. When a timer event is generated, the inter- Service Routine, ISR, is required. Example 14-7
rupt flag bit is set within 1 PBCLK + 2 SYSCLK cycles. through Example 14-9 show a partial code example of
If the timer interrupt enable bit is set, TxIE = 1, an an ISR.
interrupt is generated.
The timer module is enabled as a source of interrupts
via the respective Timer Interrupt Enable bit, TxIE
(IECx<n>). The Timer Interrupt Flag, TxIF (IFSx<n>),
must be cleared in software.
EXAMPLE 14-7: 16-BIT TIMER INTERRUPT AND PRIORITIES

T2CON = 0x0; // Stop Timer and clear control register,
// prescaler at 1:1,internal clock source

IPC2SET = 0x0000000C; // Set priority level=3

// operation by assigning IPC2SET = 0x0000000D
IFS0CLR = 0x00000100; // Clear Timer interrupt status flag

IEC0SET = 0x00000100; // Enable Timer interrupts
EXAMPLE 14-8: 32-BIT TIMER INTERRUPT AND PRIORITIES

T4CON = 0x0; // Stop 16-bit Timer4 and clear control register
T5CON = 0x0; // Stop 16-bit Timer5 and clear control register
T4CONSET = 0x0038; // Enable 32-bit mode, prescaler at 1:8,
// internal clock source
TMR4= 0x0; // Clear contents of the TMR4 and TMR5

// registers in one 32-bit load operation
PR4 = 0xFFFFFFFF; // Load PR4 and PR5 registers with 32-bit value
// 0xFFFFFFFF in one 32-bit load operation
IPC5SET = 0x00000004; // Set priority level=1 and

// operation by assigning IPC5SET = 0x00000005
IFS0CLR = 0x10000000; // Clear the Timer5 interrupt status flag

IEC0SET = 0x10000000; // Enable Timer5 interrupts

PIC32MX3XX/4XX
EXAMPLE 14-9: TIMER ISR
void __ISR(_TIMER_2_VECTOR, ipl3) T2_Interrupt_ISR(void)
{
IFS0CLR = 0x00000100; // Be sure to clear the Timer2 interrupt status

}
void__ISR(TIMER_5_VECTOR. ipl1) T5_Interrupt_ISR(void)
{
...perform application specific operations in response to the interrupt
IFS0CLR = 0x10000000; // Be sure to clear the Timer5 interrupt status
}
Note: The timer ISR code example shows MPLAB® C32 Compiler specific syntax. Refer to your compiler manual
regarding support for ISRs.

The table below provides a summary of I/O pin
resources associated with the timer modules. The table
shows the settings required to make an I/O pin
available for a specific Timer module.
TABLE 14-2: I/O PIN CONFIGURATION FOR USE WITH TIMER MODULES
Pin Control
I/O Pin Module Pin Buffer

Required Bit Field(2) TRIS Description
Name Enable(2) Type Type

TGATE
T3CK Yes1) ON TCS, Input I ST Timer3 External Clock/Gate Input
TGATE
TGATE
TGATE
Legend:
CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
Note 1: These pins are only required for modes using gated timer or external clock inputs. Otherwise, these pins can be used for
general purpose I/O and require the user to set the corresponding TRIS register bits. TxCK pins not available on 64-pin
devices.
2: These bits are located in the TxCON register.

PIC32MX3XX/4XX
15.0 INPUT CAPTURE 3. Capture timer value on every edge (rising and
falling), specified edge first.
Note: This data sheet summarizes the features of 4. Prescaler Capture Event modes
the PIC32MX3XX/4XX family of devices. It - Capture timer value on every 4th rising edge
is not intended to be a comprehensive refer- of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
The input capture module is useful in applications two 16-bit timers (Timer2 or Timer3) for the time base,
requiring frequency (period) and pulse measurement. or two 16-bit timers (Timer2 and Timer3) together to
The PIC32MX3XX/4XX devices support up to five input form a 32-bit timer. The selected timer can use either
capture channels. an internal or external clock.
The input capture module captures the 16-bit or 32-bit Other operational features include:
value of the selected Time Base registers when an
• Device wake-up from capture pin during CPU
event occurs at the ICx pin. The events that cause a
Sleep and Idle modes
capture event are listed below in three categories:
• Interrupt on input capture event
1. Simple Capture Event modes
• 4-word FIFO buffer for capture values
- Capture timer value on every falling edge of
- Interrupt optionally generated after 1, 2, 3 or
input at ICx pin
4 buffer locations are filled
- Capture timer value on every rising edge of
• Input capture can also be used to provide
input at ICx pin
additional sources of external interrupts
2. Capture timer value on every edge (rising and
falling)
FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM
ICx Input Timer 3 Timer 2
ICTMR
0 1
ICC32
FIFO Control
ICxBUF<31:16> ICxBUF<15:0>
Prescaler
Edge Detect
1, 4, 16
ICM<2:0> ICBNE
ICFEDGE ICOV
ICM<2:0>
Interrupt
ICxCON Event
ICI<1:0> Generation
Data Space Interface
Interrupt Peripheral Data Bus

PIC32MX3XX/4XX
TABLE 15-1: INPUT CAPTURE1 REGISTER SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_2000 IC1CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — ICFEDGE ICC32
7:0 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
BF80_2004 IC1CONCLR 31:0 Write clears selected bits in IC1CON, read yields an undefined value
BF80_2008 IC1CONSET 31:0 Write sets selected bits in IC1CON, read yields an undefined value
BF80_200C IC1CONINV 31:0 Write inverts selected bits in IC1CON, read yields an undefined value
BF80_2010 IC1BUF 31:24 IC1BUF<31:24>
23:16 IC1BUF<23:16>
15:8 IC1BUF<15:8>
7:0 IC1BUF<7:0>
TABLE 15-2: INPUT CAPTURE1 INTERRUPT REGISTER SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10A0 IPC1 15:8 — — — IC1IP<2:0> 15:8 —
Note 1: This summary table contains partial register definitions that only pertain to the Input Capture1 peripheral. Refer to the “PIC32MX Family

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_2200 IC2CON 31:24 — — — — — — — —
23:16 — — — — — — — —
BF80_2210 IC2BUF 31:24 IC2BUF<31:24>
23:16 IC2BUF<23:16>
15:8 IC2BUF<15:8>
7:0 IC2BUF<7:0>

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10B0 IPC2 15:8 — — — IC2IP<2:0> IC2IS<1:0>

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_2400 IC3CON 31:24 — — — — — — — —
23:16 — — — — — — — —
BF80_2410 IC3BUF 31:24 IC3BUF<31:24>
23:16 IC3BUF<23:16>
15:8 IC3BUF<15:8>
7:0 IC3BUF<7:0>

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10C0 IPC3 15:8 — — — IC3IP<2:0> IC3IS<1:0>

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_2600 IC4CON 31:24 — — — — — — — —
23:16 — — — — — — — —
BF80_2610 IC4BUF 31:24 IC4BUF<31:24>
23:16 IC4BUF<23:16>
15:8 IC4BUF<15:8>
7:0 IC4BUF<7:0>

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10D0 IPC4 15:8 — — — IC4IP<2:0> IC4IS<1:0>

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_2800 IC5CON 31:24 — — — — — — — —
23:16 — — — — — — — —
BF80_2810 IC5BUF 31:24 IC5BUF<31:24>
23:16 IC5BUF<23:16>
15:8 IC5BUF<15:8>
7:0 IC5BUF<7:0>

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10E0 IPC5 15:8 — — — IC5IP<2:0> IC5IS<1:0>

PIC32MX3XX/4XX
REGISTER 15-1: ICXCON: INPUT CAPTURE X CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 r-x r-x r-x R/W-0 R/W-0

ON FRZ SIDL — — — ICFEDGE ICC32
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
bit 7 bit 0
Legend:

bit 15 ON: ON bit
1 = Module enabled
0 = Disable and Reset module, disable clocks, disable interrupt generation, and allow SFR
modifications
bit 14 FRZ: Freeze in Debug Mode Control bit
1 = Freeze module operation when in Debug mode
0 = Do not freeze module operation when in Debug mode
bit 13 SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
bit 9 ICFEDGE: First Capture Edge Select bit (only used in mode 6, ICxM = 110)
1 = Capture rising edge first
0 = Capture falling edge first
bit 8 ICC32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
bit 7 ICTMR: Timer Select bit (Does not affect timer selection when ICxC32 (ICxCON<8>) is ‘1’)
0 = Timer3 is the counter source for capture
1 = Timer2 is the counter source for capture
bit 6-5 ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event

PIC32MX3XX/4XX
REGISTER 15-1: ICXCON: INPUT CAPTURE X CONTROL REGISTER (CONTINUED)
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture Mode Select bits
111 = Interrupt Only mode
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every 16th rising edge
100 = Prescaled Capture Event mode – every 4th rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Capture Disable mode

PIC32MX3XX/4XX
REGISTER 15-2: ICXBUF: INPUT CAPTURE X BUFFER REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
ICxBUF<31:24>
bit 31 bit 24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ICxBUF<23:16>
bit 23 bit 16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ICxBUF<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ICxBUF<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
bit 31-0 ICxBUF<31:0>: Buffer Register bits

Value of the current captured input timer count

PIC32MX3XX/4XX
15.1 Timer Selection 15.2 Simple Capture Event Modes
The input capture module can select between one of These modes are specified by setting the ICM
two 16-bit timers for the time base, or two 16-bit timers (ICxCON<2:0>) bits to ‘010’, ‘011’, or ‘110’. Setting
together to form a 32-bit timer. Setting ICTMR ICM = ‘011’ configures the module to capture the timer
(ICxCON<7>) to ‘0’ selects the Timer3 for capture. value on any rising edge of the capture input. ICM =
Setting ICTMR (ICxCON<7>) to 1 selects the Timer2 ‘010’ configures the module to capture the timer on any
for capture. falling edge of the capture input. Setting ICM = ‘110’
An input capture channel configured to support 32-bit configures the channel to capture the timer on every
capture, may use a 32-bit timer resource for capture. transition of the capture input, beginning with the edge
By setting ICC32 (ICxCON<8>) to ‘1’, a 32-bit timer specified by ICFEDGE (ICxCON<9>). In Simple Cap-
resource is captured. The 32-bit timer resource is ture Event mode, the prescaler is not used. See
routed into the module using the existing 16-bit timer Figure 15-2 for simplified timing diagrams of a simple
inputs. capture event.
The timers clock can be setup using the internal periph- Note: Since the capture input must be synchro-
eral clock source, or using a synchronized external nized to the peripheral clock, the module
clock source applied at the TxCK pin. captures the timer count value, which is valid
2-3 peripheral clock cycles (TPB) after the
capture event.
An input capture interrupt event is generated after one,
two, three or four timer count captures, as configured
by ICI (ICxCON<6:5>).
FIGURE 15-2: SIMPLE CAPTURE EVENT TIMING DIAGRAM CAPTURE EVERY RISING EDGE
Peripheral Clock
Timer Count n n+1 n+2 m m+1 m+2 m+3 m+4 m+5
ICx Input
Synchronized Capture
Capture Data n+2 m+3
Capture Interrupt
15.3 Prescaled Capture Event Modes

In Prescaled Capture Event mode, the input capture Note: Since the capture input must be synchro-
module triggers a capture event on either every fourth nized to the peripheral clock, the timer count
or every sixteenth rising edge. These modes are value is captured, which is valid 2-3
selected by setting the ICM (ICxCON<2:0>) bits to peripheral clock periods after the capture
‘100’ or ‘101’, respectively. event.

PIC32MX3XX/4XX
Note: It is recommended that the user disable (i.e.,
clear ON bit, ICxCON<15>) the capture
module before switching to Prescaler Cap-
ture Event mode. Simply switching to Pres-
caler Capture Event mode from another
active mode does not reset the prescaler
and may cause an inadvertent capture
event.
Figure 15-3 depicts a capture event when the input
capture module is in Prescaler Capture Event mode.
FIGURE 15-3: PRESCALER CAPTURE EVENT TIMING DIAGRAM

TPB
Peripheral Clock
Timer Count n n+1 n+2 n+3 n+4
TICX_IN_L
TICX_IN_H
Capture Input
Prescaler Count 1 2 3 4
Prescaler Output
Synchronized Capture
Capture Data n+2
Capture Interrupt
15.4 Edge Detect (Hall Sensor) Mode 15.5 Interrupt Only Mode
In Edge Detect mode, the input capture module cap- When the Input Capture module is set for Interrupt
tures a timer count value on every edge of the capture Only mode (ICM = ‘111’) and the device is in Sleep or
input. Edge Detect mode is selected by setting the ICM Idle mode, the capture input functions as an interrupt
bit to ‘001’. In this mode, the capture prescaler is not pin. Any rising edge on the capture input triggers an
used and the capture overflow bit, ICOV (ICxCON<4>) interrupt. No timer values are captured and the FIFO
is not updated. In this mode, the Interrupt Control bits buffer is not updated. When the device leaves Sleep or
(ICI, ICxCON<6:5>) are ignored and an interrupt event Idle mode, the interrupt signal is deasserted.
is generated for every timer count capture In this mode, since no timer values are captured, the
Timer Select bit ICTMR (ICxCON<7>) is ignored and
there is no need to configure the timer source. A wake-
up interrupt is generated on the first rising edge, there-
fore the Interrupt Control bits ICI (ICxCON<6:5>) are
also ignored. The prescaler is not used in this mode.

PIC32MX3XX/4XX
EXAMPLE 15-1: INPUT CAPTURE EXAMPLE CODE
/*
The following code segment initialized the timer and setup the input capture
module.
*/
...
//Initialize timer 2
T2CON = 0x0 // Stop and Init Timer
PR2 = 0x7000; // Load period register
// Init IC1 module

IC1CON = 0x8081;//Enable Module, use timer 2,
//Capture mode 1 (capture every edge)
...
//Read the capture data if available
int cap_data;
while( IC1CONbits.ICBNE ) // while data available in capture FIFO
{
cap_data = IC1BUF;
... //process data
}
...

PIC32MX3XX/4XX
16.0 OUTPUT COMPARE The following are some of the key features:
• Multiple output compare modules in a device
• Programmable interrupt generation on compare
event
ence source. Refer to the “PIC32MX Family • Single and Dual Compare modes
Reference Manual” (DS61132) for a • Single and continuous output pulse generation
detailed description of this peripheral. • Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and auto-
The Output Compare module (OCMP) is used to gen-
matic output disable
erate a single pulse or a train of pulses in response to
selected time base events. For all modes of operation, • Programmable selection of 16-bit or 32-bit time
the OCMP module compares the values stored in the bases.
OCxR and/or the OCxRS registers to the value in the • Can operate from either of two available 16-bit
selected timer. When a match occurs, the OCMP mod- time bases or a single 32-bit time base.
ule generates an event based on the selected mode of
operation.
FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit

OCxIF(1)
OCxRS(1)
Output S Q
OCxR(1) OCx(1)
Logic R
3 Output Enable
OCM<2:0>
Mode Select OCFA or OCFB
Comparator (see Note 2)
0 1 OCTSEL 0 1
16 16
TMR register inputs Period match signals

from time bases from time bases
(see Note 3). (see Note 3).
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.

PIC32MX3XX/4XX
16.1 Output Compare Registers
TABLE 16-1: OUTPUT COMPARE SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_3000 OC1CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
7:0 — — OC32 OCFLT OCTSEL OCM<2:0>
BF80_3004 OC1CONCLR 31:0 Write clears selected bits in OC1CON, Read yields an undefined value.
BF80_3008 OC1CONSET 31:0 Write sets selected bits in OC1CON, Read yields an undefined value.
BF80_300C OC1CONINV 31:0 Write inverts selected bits in OC1CON, Read yields an undefined value.
BF80_3010 OC1R 31:24 OC1R<31:24>
23:16 OC1R<23:16>
15:8 OC1R<15:8>
7:0 OC1R<7:0>
BF80_3014 OC1RCLR 31:0 Write clears selected bits in OC1R, Read yields an undefined value.
BF80_3018 OC1RSET 31:0 Write sets selected bits in OC1R, Read yields an undefined value.
BF80_301C OC1RINV 31:0 Write inverts selected bits in OC1R, Read yields an undefined value.
BF80_3020 OC1RS 31:24 OC1RS<31:24>
23:16 OC1RS<23:16>
15:8 OC1RS<15:8>
7:0 OC1RS<7:0>
BF80_3024 OC1RSCLR 31:0 Write clears selected bits in OC1RS, Read yields an undefined value.
BF80_3028 OC1RSSET 31:0 Write sets selected bits in OC1RS, Read yields an undefined value.
BF80_302C OC1RSINV 31:0 Write inverts selected bits in OC1RS, Read yields an undefined value.
TABLE 16-2: OUTPUT COMPARE1 INTERRUPT REGISTER SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10A0 IPC1 23:16 — — — OC1IP<2:0> OC1IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Output Compare1 peripheral. Refer to the “PIC32MX Family

PIC32MX3XX/4XX
TABLE 16-3: OUTPUT COMPARE2 SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_3200 OC2CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
BF80_3210 OC2R 31:24 OC2R<31:24>
23:16 OC2R<23:16>
15:8 OC2R<15:8>
7:0 OC2R<7:0>
BF80_3220 OC2RS 31:24 OC2RS<31:24>
23:16 OC2RS<23:16>
15:8 OC2RS<15:8>
7:0 OC2RS<7:0>
BF80_3224 OC2RSCLR 31:0 Write clears selected bits in OC2RS, Read yields an undefined value.
BF80_3228 OC2RSSET 31:0 Write sets selected bits in OC2RS, Read yields an undefined value.
BF80_322C OC2RSINV 31:0 Write inverts selected bits in OC2RS, Read yields an undefined value.

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10B0 IPC2 23:16 — — — OC2IP<2:0> OC2IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Output Compare2 peripheral. Refer to the PIC32MX Family Ref-
erence Manual (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_3400 OC3CON 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
BF80_3410 OC3R 31:24 OC3R<31:24>
23:16 OC3R<23:16>
15:8 OC3R<15:8>
7:0 OC3R<7:0>
BF80_3420 OC3RS 31:24 OC3RS<31:24>
23:16 OC3RS<23:16>
15:8 OC3RS<15:8>
7:0 OC3RS<7:0>
BF80_3424 OC3RSCLR 31:0 Write clears selected bits in OC3RS, Read yields an undefined value
BF80_3428 OC3RSSET 31:0 Write sets selected bits in OC3RS, Read yields an undefined value
BF80_342C OC3RSINV 31:0 Write inverts selected bits in OC3RS, Read yields an undefined value

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10C0 IPC3 23:16 — — — OC3IP<2:0> OC3IS<1:0>

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_3600 OC4CON 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
BF80_3604 OC4CONCLR 31:0 Write clears selected bits in OC4CON, read yields an undefined value
BF80_3608 OC4CONSET 31:0 Write sets selected bits in OC4CON, read yields an undefined value
BF80_360C OC4CONINV 31:0 Write inverts selected bits in OC4CON, read yields an undefined value
BF80_3610 OC4R 31:24 OC4R<31:24>
23:16 OC4R<23:16>
15:8 OC4R<15:8>
7:0 OC4R<7:0>
BF80_3614 OC4RCLR 31:0 Write clears selected bits in OC4R, read yields an undefined value
BF80_3618 OC4RSET 31:0 Write sets selected bits in OC4R, read yields an undefined value
BF80_361C OC4RINV 31:0 Write inverts selected bits in OC4R, read yields an undefined value
BF80_3620 OC4RS 31:24 OC4RS<31:24>
23:16 OC4RS<23:16>
15:8 OC4RS<15:8>
7:0 OC4RS<7:0>
BF80_3624 OC4RSCLR 31:0 Write clears selected bits in OC4RS, read yields an undefined value
BF80_3628 OC4RSSET 31:0 Write sets selected bits in OC4RS, read yields an undefined value
BF80_362C OC4RSINV 31:0 Write inverts selected bits in OC4RS, read yields an undefined value

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10D0 IPC4 23:16 — — — OC4IP<2:0> OC4IS<1:0>

PIC32MX3XX/4XX
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_3800 OC5CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL — — — — —
BF80_3804 OC5CONCLR 31:0 Write clears selected bits in OC5CON, read yields an undefined value
BF80_3808 OC5CONSET 31:0 Write sets selected bits in OC5CON, read yields an undefined value
BF80_380C OC5CONINV 31:0 Write inverts selected bits in OC5CON, read yields an undefined value
BF80_3810 OC5R 31:24 OC5R<31:24>
23:16 OC5R<23:16>
15:8 OC5R<15:8>
7:0 OC5R<7:0>
BF80_3814 OC5RCLR 31:0 Write clears selected bits in OC5R, read yields an undefined value
BF80_3818 OC5RSET 31:0 Write sets selected bits in OC5R, read yields an undefined value
BF80_381C OC5RINV 31:0 Write inverts selected bits in OC5R, read yields an undefined value
BF80_3820 OC5RS 31:24 OC5RS<31:24>
23:16 OC5RS<23:16>
15:8 OC5RS<15:8>
7:0 OC5RS<7:0>
BF80_3824 OC5RSCLR 31:0 Write clears selected bits in OC5RS, read yields an undefined value
BF80_3828 OC5RSSET 31:0 Write sets selected bits in OC5RS, read yields an undefined value
BF80_382C OC5RSINV 31:0 Write inverts selected bits in OC5RS, read yields an undefined value

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10E0 IPC5 23:16 — — — OC5IP<2:0> OC5IS<1:0>

PIC32MX3XX/4XX
TABLE 16-11: TIMER REGISTER SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0800 T2CON 15:8 ON FRZ SIDL — — — — —
BF80_0810 TMR2 15:8 TMR2<15:8>
7:0 TMR2<7:0>
BF80_0820 PR2 15:8 PR2<15:8>
7:0 PR2<7:0>
BF80_0A00 T3CON 15:8 ON FRZ SIDL — — — — —
BF80_0A10 TMR3 15:8 TMR3<15:8>
7:0 TMR3<7:0>
BF80_0A20 PR3 15:8 PR3<15:8>
7:0 PR3<7:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer 2 and Timer 3 peripherals. Refer to the “PIC32MX Family

PIC32MX3XX/4XX
REGISTER 16-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

bit 15 bit 8
r-x r-x R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— — OC32 OCFLT OCTSEL OCM<2:0>
bit 7 bit 0
Legend:

bit 15 ON: Output Compare Peripheral On bit
1 = Output compare peripheral is enabled. The status of other bits in the register are not affected by
setting this bit
0 = Output compare peripheral is disabled and not drawing current. SFR modifications are allowed.
The status of other bits in this register are not affected by clearing this bit
1 = Freeze operation when CPU enters in Debug Exception mode
0 = Continue operation when CPU enters in Debug Exception mode
Note: FRZ is only writable in Debug Exception mode; it is forced to ‘0’ in normal mode.
1 = Discontinue operation when CPU enters in Idle mode
bit 5 OC32: 32-bit Compare Mode bit
1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source
0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
bit 4 OCFLT: PWM Fault Condition Status bit(1)
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
Note: This bit is only used when OCM<2:0> = 111.
bit 3 OCTSEL: Output Compare Timer Select bit
1 = Timer3 is the clock source for compare x
0 = Timer2 is the clock source for compare x
Note: OCTSEL must be set to ‘1’ when using 32-bit mode (OC32 = 1).
Note 1: Reads as ‘0’ in modes other than PWM mode.

PIC32MX3XX/4XX
REGISTER 16-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
bit 2-0 OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx, Fault pin enabled
110 = PWM mode on OCx, Fault pin disabled
101 = Initialize OCx pin low, generate continuous output pulses on OCx pin
100 = Initialize OCx pin low, generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high, compare event forces OCx pin low
001 = Initialize OCx pin low, compare event forces OCx pin high
000 = Output compare peripheral is disabled
Note 1: Reads as ‘0’ in modes other than PWM mode.

PIC32MX3XX/4XX
REGISTER 16-2: OCxR: OUTPUT COMPARE x COMPARE PRIMARY REGISTER
OCR<31:24>
bit 31 bit 24

OCR<23:16>
bit 23 bit 16

OCR<15>8>
bit 15 bit 8

OCR<7:0>
bit 7 bit 0
Legend:
bit 31-16 OCxR<31:16>: Upper 16 bits of 32-bit compare value when OC32 (OCxCON<5>) = 1
bit 15-0 OCxR<15:0>: Lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value

PIC32MX3XX/4XX
REGISTER 16-3: OCxRS: OUTPUT COMPARE x COMPARE SECONDARY REGISTER
OCRS<31:24>
bit 31 bit 24

OCRS<23:16>
bit 23 bit 16

OCRS<5>8>
bit 15 bit 8

OCRS<7:0>
bit 7 bit 0
Legend:
bit 31-16 OCxRS<31:16>: Upper 16 bits of 32-bit compare value, when OC32 (OCxCON<5>) = 1
bit 15-0 OCxRS<15:0>: Lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value

PIC32MX3XX/4XX
16.2 Setup for Single Output Change 11. When the incrementing timer, TMRx, matches the
Secondary Compare register, OCxRS, the
There are three modes of operation that change the second and trailing edge (high-to-low) of the pulse
state of the output pin; these modes can be referred to is driven onto the OCx pin. No additional pulses
as drive high, drive low and toggle. The configuration are driven onto the OCx pin and it remains at low.
for these modes is identical, the mode is selected by As a result of the second compare match event,
the OCM bits. For this example, Tx will represent the OCxIF interrupt flag bit is set, which will
Timer2. result in an interrupt if it is enabled, by setting
the OCxIE bit. For further information on
Drive High: When the OCM control bits
peripheral interrupts, refer to Section 8.0
(OCxCON<2:0>) are set to ‘001’, the selected output
“Interrupts”.
compare channel initializes the OCx pin to the low state
12. To initiate another single pulse output, change the
and drives the output pin high when a compare event
Timer and Compare register settings, if needed,
occurs.
and then issue a write to set the OCM bits to the
Drive Low: When the OCM control bits desired mode of operation. Disabling and re-
(OCxCON<2:0>) are set to ‘010’, the selected output enabling of the timer and clearing the Timer
compare channel initializes the OCx pin to the high register are not required, but may be
state and drives the output pin low when a compare advantageous for defining a pulse from a known
event occurs. event time boundary.
Toggle: When the OCM control bits (OCxCON<2:0>)
are set to ‘011’, the selected output compare channel 16.3 Setup for Single Output Pulse
OCx pin is not initialized. The OCx pin is driven to the Generation
opposite state when a compare event occurs.
When the OCM control bits (OCxCON<2:0>) are set to
To generate a output change signal, the following steps ‘100’, the selected output compare channel initializes
are required (these steps assume the timer source is the OCx pin to the low state and generates a single out-
initially turned off, but this is not a requirement for the put pulse.
module operation):
To generate a single output pulse, the following steps
1. Determine the timer clock cycle time. Take into are required (these steps assume the timer source is
account the frequency of the external clock to initially turned off, but this is not a requirement for the
the timer source (if one is used) and the timer module operation): For this example Tx will represent
prescaler settings. Timer2.
2. Calculate time to the rising edge of the output
1. Determine the timer clock cycle time. Take into
pulse relative to the timer start value (0000h).
account the frequency of the external clock to
3. Determine if the output compare module will be the timer source (if one is used) and the timer
used in 16 or 32-bit mode based on the previous prescaler settings.
calculations.
2. Calculate time to the rising edge of the output
4. Configure the timer to be used as the time base pulse relative to the timer start value (0000h).
for 16 or 32-bit mode by writing to the T32 bit
3. Calculate the time to the falling edge of the pulse
(TxCON<T32>). based on the desired pulse width and the time to
5. Configure the output compare channel for 16 or the rising edge of the pulse.
32-bit operation by writing to the OC32 bit 4. Determine if the output compare module will be
(OCxCON<5>). used in 16 or 32-bit mode based on the previous
6. Write the value computed in step 2 above into calculations.
the Compare register, OCxR. 5. Configure the timer to be used as the time base
7. Set Timer Period register, PRx, to the value equal for 16 or 32-bit mode by writing to the T32 bit
to or greater than the value in OCxRS, the (TxCON<T32>).
Secondary Compare register. 6. Configure the output compare channel for 16 or
8. Set the OCM bits to the desired mode of operation 32-bit operation by writing to the OC32 bit
and the OCTSEL (OCxCON<3>) bit to the desired (OCxCON<5>).
timer source. The OCx pin state will now be driven
7. Write the values computed in steps 2 and 3
low.
above into the Compare register, OCxR, and the
9. Set the ON (TxCON<15>) bit to ‘1’ which enables Secondary Compare register, OCxRS,
the compare time base to count. respectively.
10. Upon the first match between TMRx and OCxR, 8. Set Timer Period register, PRx, to the value equal
the OCx pin will be driven high. to or greater than the value in the OCxRS, the
Secondary Compare register.

PIC32MX3XX/4XX
9. Set the OCM bits to ‘100’ and the OCTSEL
(OCxCON<3>) bit to the desired timer source.
The OCx pin state will now be driven low.
10. Set the ON (TxCON<15>) bit to ‘1’ which enables
the compare time base to count.
11. Upon the first match between TMRx and OCxR,
the OCx pin will be driven high.
12. When the incrementing timer matches the Sec-
ondary Compare register, OCxRS, the second
and trailing edge (high-to-low) of the pulse is
driven onto the OCx pin. No additional pulses are
driven onto the OCx pin and it remains at low. As
a result of the second compare match event, the
OCxIF interrupt flag bit is set, which will result in
an interrupt if it is enabled, by setting the OCxIE
bit. For further information on peripheral
interrupts, refer to Section 8.0 “Interrupts”.
13. To initiate another single pulse output, change the
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling of the timer and clear-
ing the TMRx register are not required, but may
be advantageous for defining a pulse from a
known event time boundary.
EXAMPLE 16-1: EXAMPLE CODE

// The following code example will set the Output Compare 1 module for interrupts on the
// single pulse event and select Timer 2 as the clock source for the compare time base.
T2CON = 0x0010; // Configure Timer 2 for a prescaler of 2
OC1CON = 0x0000; // Turn off OC1 while doing setup.

OC1CON = 0x0004; // Configure for single pulse mode
OC1R = 0x3000; // Initialize primary Compare Register
OC1RS = 0x3003; // Initialize secondary Compare Register
PR2 = 0x3003; // Set period (PR2 is now 32-bits wide)
// configure int
IF0CLR = 0x00000080; // Clear the OC1 interrupt flag
IE0SET = 0x00000080; // Enable OC1 interrupt
IPC1SET = 0x0030000; // Set OC1 interrupt subpriority to 3,
// the highest level
IPC1SET = 0x00000003; // Set subpriority to 3, maximum
T2CONSET = 0x8000; // Enable timer2

OC1CONSET = 0x8000; // Enable the OC1 module
// Example code for Output Compare 1 ISR:
void__ISR (_OUTPUT_COMPARE__1_VECTOR, ipl4) OC1_IntHandler(void)

{
// insert user code here
IFS0CLR = 0x00000080; // Clear the OC1 interrupt flag
}

PIC32MX3XX/4XX
16.4 Setup for Continuous Output 14. When the compare time base and the value in its
Pulse Generation respective Period register match, the TMRx
register resets to 0x0000 and resumes counting.
When the OCM control bits (OCxCON<2:0>) are set to 15. Steps 8 through 11 are repeated and a continuous
‘101’, the selected output compare channel initializes stream of pulses is generated, indefinitely. The
the OCx pin to the low state and generates output OCxIF flag is set on each OCxRS-TMRx compare
pulses on each and every compare match event. match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following 16.5 Pulse-Width Modulation Mode
steps are required (these steps assume the timer
There are two modes of PWM operation for this device:
source is initially turned off, but this is not a requirement
PWM and PWM with Fault input. The configuration of
for the module operation). For this example, Tx will
both modes is identical with the exception of the value
represent Timer2.
written to the OCM bits to select the desired mode.
1. Determine the timer clock cycle time. Take into
The following steps should be taken when configuring
account the frequency of the external clock to
the timer source (if one is used) and the timer the output compare module for PWM operation:
prescaler settings. 1. Calculate the PWM period.
2. Calculate time to the rising edge of the output 2. Calculate the PWM duty cycle.
pulse relative to the TMRx start value (0000h). 3. Determine if the Output Compare module will be
3. Calculate the time to the falling edge of the pulse used in 16 or 32-bit mode based on the previous
based on the desired pulse width and the time to calculations.
the rising edge of the pulse. 4. Configure the timer to be used as the time base
4. Determine if the output compare module will be for 16 or 32-bit mode by writing to the T32 bit
used in 16 or 32-bit mode based on the previous (TxCON<T32>).
calculations. 5. Configure the output compare channel for 16 or
5. Configure the timer to be used as the time base 32-bit operation by writing to the OC32 bit
for 16 or 32-bit mode by writing to the T32 bit (OCxCON<5>).
(TxCON<T32>).
6. Set the PWM period by writing to the selected
6. Configure the output compare channel for 16 or Timer Period register (PR).
32-bit operation by writing to the OC32 bit
7. Set the PWM duty cycle by writing to the OCxRS
(OCxCON<5>).
register.
7. Write the values computed in step 2 and 3
8. Write the OCxR register with the initial duty
above into the Compare register, OCxR, and the
cycle.
Secondary Compare register, OCxRS,
respectively. 9. Enable interrupts, if required, for the timer and
output compare modules. The output compare
8. Set Timer Period register, PRx, to the value equal
interrupt is required for PWM Fault pin
to or greater than the value in OCxRS, the
utilization.
Secondary Compare register.
10. Configure the output compare module for one of
9. Set the OCM bits to ‘101’ and the OCTSEL bit to
the desired timer source. The OCx pin state will two PWM operation modes by writing to the Out-
now be driven low. put Compare mode bits OCM<2:0>
(OCxCON<2:0>).
10. Enable the compare time base by setting the ON
(TxCON<15>) bit to ‘1’. 11. Set the TMRx prescale value and enable the
time base by setting ON (TxCON<15>) = 1.
11. Upon the first match between TMRx and OCxR,
the OCx pin will be driven high. Note: The OCxR register should be initialized
12. When the compare time base, TMRy, matches before the output compare module is first
the Secondary Compare register, OCxRS, the enabled. The OCxR register becomes a
second and trailing edge (high-to-low) of the pulse read-only Duty Cycle register when the
is driven onto the OCx pin. module is operated in the PWM modes.
13. As a result of the second compare match event, The value held in OCxR will become the
the OCxIF interrupt flag bit set. PWM duty cycle for the first PWM period.
The contents of the Duty Cycle Buffer
register, OCxRS, will not be transferred
into OCxR until a time base period match
occurs.

PIC32MX3XX/4XX
16.5.1 PWM WITH FAULT PROTECTION 16.5.2 PWM PERIOD
INPUT PIN The PWM period is specified by writing to PR, the
When the Output Compare mode bits, OCM<2:0> Timer Period register. The PWM period can be
(OCxCON<2:0>), are set to ‘111’, the selected output calculated using Equation 16-1.
compare channel is configured for the PWM mode of
operation. All functions of the PWM are applicable with EQUATION 16-1: CALCULATING THE PWM
the addition of Fault Protection Input. PERIOD
Fault protection is provided via the OCFA and OCFB
PWM Period = [(PR+ 1) • TPB • (TMR Prescale Value)]
pins. The OCFA pin is associated with output compare
channels 1 through 4, while the OCFB pin is associated PWM Frequency = 1/[PWM Period]
with output compare channel 5.
If a logic ‘0’ is detected on the OCFA/OCFB pin, the
selected PWM output pin(s) is placed in a high-
impedance state. The user may elect to provide a pull- Note: A PRy value of N will produce a PWM
down or pull-up resistor on the PWM pin to provide a period of N + 1 time base count cycles. For
desired state if a Fault condition occurs. The shutdown example, a value of 7 written into the PRy
of the PWM output is immediate and is not tied to the register will yield a period consisting of
device clock source. This state will remain until the 8 time base cycles.
following changes occur:
• the external Fault condition has been removed
16.5.3 PWM DUTY CYCLE
• PWM mode is re-enabled by writing to the mode The PWM duty cycle is specified by writing to the
bits OCM<2:0>. OCxRS register. The OCxRS register can be written to
at any time, but the duty cycle value is not latched into
As a result of the Fault condition, the respective inter-
OCxR until a match between the PR and timer occurs
rupt flag OCxIF is asserted and an interrupt will be gen-
(i.e., the period is complete). This provides a double
erated, if it is enabled. Upon detection of the Fault
buffer for the PWM duty cycle and is essential for glitch-
condition, the OCFLT bit (OCxCON<4>) is asserted
less PWM operation. In the PWM mode, OCxR is a
high (logic ‘1’). This bit is a read-only bit and will only be
read-only register.
cleared once the external Fault condition has been
removed and the PWM mode is re-enabled, by writing Some important boundary parameters of the PWM duty
to the appropriate mode bits, OCM<2:0>. cycle include:
• If the Duty Cycle register, OCxR, is loaded with
0000h, the OCx pin will remain low (0% duty cycle).
• If OCxR is greater than PR (Timer Period register),
the pin will remain high (100% duty cycle).
• If OCxR is equal to PR, the OCx pin will be low for
one time base count value and high for all other
count values.
See Example 16-2 for PWM mode timing details.
Table shows example PWM frequencies and
resolutions for a device peripheral bus operating at
10 MHz.
EQUATION 16-2: CALCULATION FOR MAXIMUM PWM RESOLUTION
FPB
log10 (F PWM • ) bits
TMRy • Prescaler
Maximum PWM Resolution (bits) =
log10(2)

PIC32MX3XX/4XX
EXAMPLE 16-2: PWM PERIOD AND DUTY CYCLE CALCULATION
Desired PWM frequency is 52.08 kHz,
FPB = 10 MHz
Timer 2 prescale setting: 1:1
1/52.08 kHz = (PR2 + 1) • FBP • (Timer2 prescale value)

19.20 μs = (PR2 + 1) • 0.1 μs • (1)
PR2 = 191
Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz PWM frequency
and a 10 MHz peripheral bus clock rate.
1/52.08 kHz = 2PWM RESOLUTION • 1/10 MHz • 1

19.20 μs = 2PWM RESOLUTION • 100 nsec • 1
192 = 2PWM RESOLUTION
log10(192) = (PWM Resolution) • log10(2)
PWM Resolution= 7.6 bits
Note: If the PR value exceeds 16 bits the module must be used in 32-bit mode to maintain the calculated PWM
resolution. If reduced resolution is acceptable the timer prescaler may be increased and the calculation
repeated until the result is a 16-bit value. Increasing the timer prescaler to allow operation in 16-bit mode
may result in reduced PWM resolution.
EXAMPLE 16-3: PWM MODE PULSE SETUP AND INTERRUPT SERVICING (32-BIT MODE)
// The following code example will set the Output Compare 1 module
// for PWM mode with FAULT pin disabled, a 50% duty cycle and a
// PWM frequency of 52.08 kHz at FPB = 40 MHz. Timer2 is selected as
// the clock for the PWM time base and Output Compare 1 interrupts
// are enabled.
OC1CON = 0x0000; // Turn off OC1 while doing setup.

OC1R = 0x00600000; // Initialize primary Compare Register
OC1RS = 0x00600000; // Initialize secondary Compare Register
OC1CON = 0x0006; // Configure for PWM mode, Fault pin Disabled
PR2 = 0x00600000; // Set period
// configure int
IFS0 &= ~0x00000080; // Clear the OC1 interrupt flag
IEC0 |= 0x00000080; // Enable OC1 interrupt
IPC1 |= 0x001C0000; // Set OC1 interrupt priority to 7,
// the highest level
IPC1 |= 0x00000003; // Set subpriority to 3, maximum
T2CON |= 0x8000; // Enable timer2

OC1CON |= 0x8000; // turn on OC1 module
// Example code for Output Compare 1 ISR:

void__ISR (_OUTPUT_COMPARE_1_VECTOR, ipl4) OC1_IntHandler(void)
{
// insert user code here
IFS0CLR = 0x00000080; // Clear the interrupt flag
}

PIC32MX3XX/4XX
TABLE 16-12: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PERIPHERAL BUS
CLOCK OF 10 MHZ (16-BIT MODE)
PWM Frequency 19.5 Hz 153 Hz 305 Hz 2.44 kHz 9.77 kHz 78.1 kHz 313 kHz
Timer Prescaler Ratio 8 1 1 1 1 1 1
Period Register Value (hex) 0xFA65 0xFF4E 0x8011 0x1001 0x03FE 0x007F 0x001E
Resolution (bits) (decimal) 16 16 15 12 10 7 5
PWM Frequency 58 Hz 458 Hz 916 Hz 7.32 kHz 29.3 kHz 234 kHz 938 kHz
Period Register Value (hex) 0xFC8E 0xFFDD 0x7FEE 0x1001 0x03FE 0x007F 0x001E
Resolution (bits) (decimal) 16 16 15 12 10 7 5
PWM Frequency 58 Hz 458 Hz 916 Hz 7.32 kHz 29.3 kHz 234 kHz 938 kHz
Period Register Value (hex) 0x349C 0x354D 0xD538 0x1AAD 0x06A9 0x00D4 0x0034
Resolution (bits) (decimal) 13.7 13.7 15.7 12.7 10.7 7.7 5.7
PWM Frequency 100 Hz 200 Hz 500 Hz 1 kHz 2 kHz 5 kHz 10 kHz
Period Register Value (hex) 0xF423 0x7A11 0x30D3 0xC34F 0x0C34 0x270F 0x1387
PWM Frequency 100 Hz 200 Hz 500 Hz 1 kHz 2 kHz 5 kHz 10 kHz
Period Register Value (hex) 0xF423 0xF423 0xC34F 0x0C34F 0x61A7 0x270F 0x1387
PWM
100 Hz 200 Hz 500 Hz 1 kHz 2 kHz 5 kHz 10 kHz
Frequency
Period Register 1 1 1 1 1 8 1
Value (hex)
Resolution (bits) 0x0007A11F 0x0003D08F 0x0001869F 0x0000C34F 0x000061A7 0x000004E1 0x00001387
(decimal)
Resolution (bits) 18.9 17.9 16.6 15.6 14.6 10.3 12.3

PIC32MX3XX/4XX
16.6 Output Compare Register I/O Pin
Control
When the output compare module is enabled, the I/O
pin direction is controlled by the compare module. The
compare module returns the I/O pin control back to the
appropriate pin LAT and TRIS control bits when it is
disabled.
When the PWM with Fault Protection Input mode is
enabled, the OCFx Fault pin must be configured as an
input by setting the respective TRIS SFR bit. The OCFx
Fault input pin is not automatically configured as an
input when PWM with Fault Input mode is selected.
TABLE 16-18: PINS ASSOCIATED WITH OUTPUT COMPARE MODULES 1- 5

Required
Module Controlling Pin Buffer
Pin Name TRIS bit Description
Control Bit Field Type Type
Setting
OC1 ON(2) OCM<2:0>(1,3) — D, O — Output Compare/PWM Channel 1
OCFA ON(2) OCM<2:0>(1,3) Input D, I ST PWM Fault Protection A Input
(For Channels 1-4)(4)
OCFB ON(2) OCM<2:0>(1,3) Input D, I ST PWM Fault Protection B Input
(For Channel 5)(4)
Legend: ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output, A = Analog, D = Digital
Note 1: All pins are subject to device pin priority control.
2: ON (OCxCON<15>) = 1. When the module is turned off, pins controlled by the module are released.
3: Mode select bits OCM<2:0> (CMxCON<2:0>).
4: Use of PWM Fault input is optional and is controlled by the OCM bits.

PIC32MX3XX/4XX
17.0 SERIAL PERIPHERAL Following are some of the key features of this module:
INTERFACE (SPI) • Master and Slave Modes Support
• Four Different Clock Formats
• Framed SPI Protocol Support
is not intended to be a comprehensive refer- • User Configurable 8-bit, 16-bit and 32-bit Data
ence source. Refer to the “PIC32MX Family Width
Reference Manual” (DS61132) for a • Separate SPI Data Registers for Receive and
detailed description of this peripheral. Transmit
• Programmable Interrupt Event on every 8-bit,
The Serial Peripheral Interface (SPI) module is a syn- 16-bit and 32-bit Data Transfer
chronous serial interface useful for communicating with
• Operation during CPU Sleep and Idle Mode
external peripherals and other microcontroller devices.
These peripheral devices may be Serial EEPROMs, • Fast Bit Manipulation using CLR, SET and INV
shift registers, display drivers, A/D converters, etc. The Registers
PIC32MX SPI module is compatible with Motorola® SPI
and SIOP interfaces.
TABLE 17-1: SPI FEATURES

Selectable
8-bit, 16-bit Selectable Slave
Available SPI SPI Frame Frame Frame Sync
and 32-bit Clock Pulses Select
SPI Modes Master Slave Master Slave Pulses and
Modes and Edges Pulse
Edges
Normal Mode Yes Yes — — Yes Yes — Yes
Framed Mode Yes Yes Yes Yes Yes Yes Yes No

PIC32MX3XX/4XX
FIGURE 17-1: SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read Write
Registers share address SPIxBUF
SPIxRXB SPIxTXB
Transmit
Receive
SPIxSR
SDIx bit 0
SDOx Shift
Control
Slave Select Clock Edge
and Frame Control Select
SSx/FSYNC Sync Control
Baud Rate
PBCLK
Generator
SCKx
Enable Master Clock
Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register.

PIC32MX3XX/4XX
17.1 SPI Registers
TABLE 17-2: SPI1 SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_5800 SPI1CON 31:24 FRMEN FRMSYNC FRMPOL — — — — —
23:16 — — — — — — SPIFE —
15:8 ON FRZ SIDL DISSDO MODE32 MODE16 SMP CKE
7:0 SSEN CKP MSTEN — — — — —
BF80_5804 SPI1CONCLR 31:0 Write clears selected bits in SPI1CON, read yields an undefined value
BF80_5808 SPI1CONSET 31:0 Write sets selected bits in SPI1CON, read yields an undefined value
BF80_580C SPI1CONINV 31:0 Write inverts selected bits in SPI1CON, read yields an undefined value
BF80_5810 SPI1STAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — SPIBUSY — — —
7:0 — SPIROV — — SPITBE — — SPIRBF
BF80_5814 SPI1STATCLR 31:0 Write clears selected bits in SPI1STAT, read yields an undefined value
BF80_5820 SPI1BUF 31:24 DATA<31:24>
23:16 DATA<23:16>
15:8 DATA<15:8>
7:0 DATA<7:0>
BF80_5830 SPI1BRG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — BRG<8>
7:0 BRG<7:0>
BF80_5834 SPI1BRGCLR 31:0 Write clears selected bits in SPI1BRG, read yields an undefined value
BF80_5838 SPI1BRGSET 31:0 Write sets selected bits in SPI1BRG, read yields an undefined value
BF80_583C SPI1BRGINV 31:0 Write inverts selected bits in SPI1BRG, read yields an undefined value
TABLE 17-3: SPI1 INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
23:16 SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE
23:16 SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF
BF88_10E0 IPC5 31:24 — — — SPI1IP<2:0> SPI1IS<1:0>
Note: This summary table contains partial register definitions that only pertain to the SPI1 peripheral. Refer to the “PIC32MX Family Reference

PIC32MX3XX/4XX
TABLE 17-4: SPI2 SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_5A00 SPI2CON 31:24 FRMEN FRMSYNC FRMPOL — — — — —
23:16 — — — — — — SPIFE —
15:8 ON FRZ SIDL DISSDO MODE32 MODE16 SMP CKE
7:0 SSEN CKP MSTEN — — — — —
BF80_5A04 SPI2CONCLR 31:0 Write clears selected bits in SPI2CON, read yields an undefined value
BF80_5A08 SPI2CONSET 31:0 Write sets selected bits in SPI2CON, read yields an undefined value
BF80_5A0C SPI2CONINV 31:0 Write inverts selected bits in SPI2CON, read yields an undefined value
BF80_5A10 SPI2STAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — SPIBUSY — — —
7:0 — SPIROV — — SPITBE — — SPIRBF
BF80_5A14 SPI2STATCLR 31:0 Write clears selected bits in SPI2STAT, read yields an undefined value
BF80_5A20 SPI2BUF 31:24 DATA<31:24>
23:16 DATA<23:16>
15:8 DATA<15:8>
7:0 DATA<7:0>
BF80_5A30 SPI2BRG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — BRG<8>
7:0 BRG<7:0>
BF80_5A34 SPI2BRGCLR 31:0 Write clears selected bits in SPI2BRG, read yields an undefined value
BF80_5A38 SPI2BRGSET 31:0 Write sets selected bits in SPI2BRG, read yields an undefined value
BF80_5A3C SPI2BRGINV 31:0 Write inverts selected bits in SPI2BRG, read yields an undefined value
TABLE 17-5: SPI2 INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1100 IPC7 23:16 — — — SPI2IP<2:0> SP2IS<1:0>
Note: This summary table contains partial register definitions that only pertain to the SPI2 peripheral. Refer to the “PIC32MX

PIC32MX3XX/4XX
REGISTER 17-1: SPIXCON: SPI CONTROL REGISTER
FRMEN FRMSYNC FRMPOL — — — — —
bit 31 bit 24
r-x r-x r-x r-x r-x r-x R/W-0 r-x

— — — — — — SPIFE —
bit 23 bit 16

ON FRZ SIDL DISSDO MODE32 MODE16 SMP CKE
bit 15 bit 8

SSEN CKP MSTEN — — — — —
bit 7 bit 0
Legend:
bit 31 FRMEN: Framed SPI Support bit

1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
bit 17 SPIFE: Frame Sync Pulse Edge Select bit (framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 15 ON: SPI Peripheral On bit
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
bit 14 FRZ: Freeze in DEBUG Exception Mode bit
1 = Freeze operation when CPU enters Debug Exception mode
0 = Continue operation when CPU enters Debug Exception mode
Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in Normal mode.
bit 13 SIDL: Stop in IDLE Mode bit
1 = Discontinue operation when CPU enters in Idle mode
bit 12 DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module

PIC32MX3XX/4XX
bit 11-10 MODE<32,16>: 32/16-bit Communication Select bits
1x = 32-bit data width
01 = 16-bit data width
00 = 8-bit data width
bit 9 SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8 CKE: SPI Clock Edge Select bit
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
Note: The CKE bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the
Framed SPI mode (FRMEN = 1).
bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode, pin controlled by port function.
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode

PIC32MX3XX/4XX
REGISTER 17-2: SPIXSTAT: SPI STATUS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
r-x r-x r-x r-x R-0 r-x r-x r-x

— — — — SPIBUSY — — —
bit 15 bit 8
r-x R/W-0 r-x r-x R-0 r-x r-x R-0

— SPIROV — — SPITBE — — SPIRBF
bit 7 bit 0
Legend:

bit 11 SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous
data in the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 3 SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 0 SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIXRXB is not full
Automatically set in hardware when SPI transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.

PIC32MX3XX/4XX
17.2 Master and Slave Modes 17.2.1 8, 16, AND 32-BIT OPERATION
The PIC32MX3XX/4XX SPI module operates in normal The PIC32MX3XX/4XX SPI module allows three types
Master or Slave modes and offers the following addi- of data widths when transmitting and receiving data
tional modes: over an SPI bus. The selection of data width deter-
mines the minimum length of SPI data.
• Framed Master
Two control bits, MODE32 and MODE16
• Framed Slave
(SPIxCON<11:10>), define the mode of operation. To
• 8, 16, 32-bit Data Width Transfers change the mode of operation on the fly, the SPI mod-
• Slave Select (Slave mode only) ule must be idle, i.e., not performing any transactions.
Below is a typical system Master – Slave connection If the SPI module is switched off (SPIxCON<15> = 0),
diagram. the new mode will be available when the module is
again switched on.
The number of clock pulses at the SCKx pin are depen-
dent on the selected mode of operation. For 8-bit mode,
8 clocks; for 16-bit mode, 16 clocks; and for 32-bit mode,
32 clocks are required.
FIGURE 17-2: SPI MASTER/SLAVE CONNECTION
PIC32MX3XX/4XX PROCESSOR 2
[SPI Master] [SPI Slave]
SDOx SDIx
Serial Receive Buffer Serial Receive Buffer

(SPIxRXB)(2) (SPIxRXB)
SDIx SDOx
Shift Register Shift Register
(SPIxSR) (SPIxSR)
MSB LSB MSB LSB
Serial Transmit Buffer Serial Transmit Buffer

(SPIxTXB)(2) (SPIxTXB)
Serial Clock
SCKx SCKx SPI Buffer
SPI Buffer
(SPIxBUF) (SPIxBUF)
GPIO/SSx SSx(1)
.
MSTEN (SPIxCON<5>) =1 SSEN (SPIxCON<7>) = 1 and

MSTEN (SPIxCON<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to SPIxBUF and read received data from SPIxBUF. The SPIxTXB and SPIxRXB
registers are memory mapped to SPIxBUF.

PIC32MX3XX/4XX
17.2.2 MASTER MODE 17.2.2.3 Master Mode Initialization
In Master mode, data from the SPIxBUF register is The following steps should be performed to setup the
transmitted synchronously on the SDO (output) pin SPI module for the Master mode of operation:
while synchronous data is received from the slave 1. If interrupts are used, disable the SPI interrupts
device on the SDI (input) pin. In this mode, the Master in the respective IEC0/1 register.
controls the synchronous data transfer with the SCK
2. Stop and reset the SPI module by clearing the
clock pin by generating 8, 16 or 32 clock pulses,
ON bit.
depending on the selected data size.
3. Clear the receive buffer.
17.2.2.1 Master Mode Operations 4. If interrupts are used, the following additional
In Master mode the SCK and SDO pins are outputs and steps are performed:
the SDI pin is an input. Setting the control bit, DISSDO • Clear the SPIx interrupt flags/events in the
(SPIxCON<12>), disables transmission at the SDO pin respective IFS0/1 register.
if Receive Only mode of operation is desired. Refer to • Set the SPIx interrupt enable bits in the
Table 17-7. respective IEC0/1 register.
The SDI (input) must be configured to properly sample • Write the SPIx interrupt priority and subprior-
the data received from the slave device by configuring ity bits in the respective IPC5/7 register.
the sample bit, SMP (SPIxCON<9>). 5. Write the Baud Rate register, SPIxBRG.
In Master mode, the SCK clock edge and polarity must 6. Clear the SPIROV bit (SPIxSTAT<6>).
be configured properly for the master and slave device 7. Write the selected configuration settings to the
to correctly transfer data synchronously. Refer to the SPIxCON register.
timing diagram shown in Figure 17-3 to determine the 8. Enable SPI operation by setting the ON bit
appropriate settings. (SPIxCON<15>).
In Master mode, the data transfers can be 8, 16, or 32 9. Write the data to be transmitted to the SPIxBUF
bits and are configured using control bits, register. Transmission (and reception) will start
MODE<32,16> (SPIxCON<11:10>). Refer to Section as soon as data is written to the SPIxBUF
17.2.1 “8, 16, and 32-bit Operation”. register.
In Master mode, the system clock is divided and then
Note 1: When using the Slave Select mode, the
used as the serial clock. The division is based on the
SSx or another GPIO pin is used to con-
settings in the SPIxBRG register. Refer to
trol the slave’s SSx input. The pin must
Section 17.2.5 “SPI Master Mode Clock Fre-
be controlled in software.
quency”.
2: The user must turn off the SPI device
17.2.2.2 Master SPIxCON Configuration prior to changing the CKE or CKP bits.
The following bits must be configured as shown for the Otherwise, the behavior of the device is
Master mode of operation when configuring the not ensured.
SPIxCON register: 3: The SPI device must be turned off prior to
• Enable Master Mode changing the mode from Slave to Master.
MSTEN (SPIxCON<5>) = 1. 4: The SPIxSR register cannot be written to
• Disable Framed SPI support directly by the user. All writes to the
FRMEN (SPIxCON<31>) = 0 SPIxSR register are performed through
the SPIxBUF register.
The remaining bits are shown with example
configurations and may be configured as desired:
• Enable module control of SDO pin – DISSDO
(SPIxCON<12>) = 0
• Configure SCK clock polarity to idle high –
CKP (SPIxCON<6>) = 1
• Configure SCK clock edge transition from Idle to
active – CKE (SPIxCON<8>) = 0
• Select 16-bit data width –
MODE<32,16> (SPIxCON<11:10>) = 01
• Sample data input at middle –
SMP (SPIxCON<9>) = 0
• Enable SPI module when CPU idle –
SIDL (SPIxCON<13>) = 0

PIC32MX3XX/4XX
FIGURE 17-3: SPI MASTER MODE OPERATION IN 8-BIT MODE (MODE32 = 0, MODE16 = 0)
User writes
to SPIxBUF User writes new data
SPIxTXB to SPIxSR(3) during transmission
SPITBE
SCKx
(CKP = 0
CKE = 0)
SCKx 4 Clock modes

(CKP = 1
(clock output
CKE = 0)
at the SCKx
SCKx pin in Master
(CKP = 0 mode)(1)
CKE = 1)
SCKx
(CKP = 1
CKE = 0)
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)
SDIx(2)
(SMP = 0) bit 7 bit 0
Input
Sample(2) Two modes
(SMP = 0) available for
SMP control
SDIx bit(4)
Input
Sample
(SMP = 1)
SPIxRXIF
Approx. 2 SYSCLK latency to set

SPIxRXIF flag bit
SPIxSR moved
SPIRBF into SPIxRXB
(SPIxSTAT<0>)
User reads
SPIxBUF
Note 1: Four SPI Clock modes are shown here to demonstrate the functionality of bits CKP (SPIxCON<6>) and CKE
(SPIxCON<8>). Only one of the four modes can be chosen for operation.
2: The SDI and input samples shown here for two different values of the SMP bit (SPIxCON<9>) are strictly for
demonstration purposes. Only one of the two configurations of the SMP bit can be chosen during operation.
3: If there are no pending transmissions, SPIxTXB is transferred to SPIxSR as soon as the user writes to SPIxBUF.
4: The operation for 8-bit mode is shown. The 16-bit and 32-bit modes are similar.

PIC32MX3XX/4XX
EXAMPLE 17-1: INITIALIZATION FOR 16-BIT SPI MASTER MODE
/*
The following code example will initialize the SPI1 in master mode.
It assumes that none of the SPI1 input pins are shared with an analog input.
If so, the AD1PCFG and corresponding TRIS registers have to be properly configured.
*/
int rData;
IEC0CLR=0x03800000; // disable all interrupts

SPI1CON = 0; // Stops and resets the SPI1.
rData=SPI1BUF; // clears the receive buffer
IFS0CLR=0x03800000; // clear any existing event
IPC5CLR=0x1f000000; // clear the priority
IPC5SET=0x0d000000; // Set IPL=3, subpriority 1
IEC0SET=0x03800000; // Enable Rx, Tx and Error interrupts
SPI1BRG=0x1; // use FPB/4 clock frequency

SPI1STATCLR=0x40; // clear the Overflow
SPI1CON=0x8220; // SPI ON, 8 bits transfer, SMP=1, Master Mode
// from now on, the device is ready to transmit and receive

data
SPI1BUF=’A’; // transmit an A character
17.2.3 SLAVE MODE 17.2.3.2 Slave SPIxCON Configuration

In Slave mode, data from the SPIxBUF register is The following bits must be configured as shown for the
transmitted synchronously on the SDO (output) pin Slave mode of operation when configuring the
while synchronous data is received from the Master SPIxCON register:
device on the SDI (input) pin. In this mode, the Master • Enable Slave Mode –
device controls the synchronous data transfer with the MSTEN (SPIxCON<5>) = 0.
SCK clock pin by generating 8, 16 or 32 clock pulses,
• Disable Framed SPI support – FRMEN
depending on the selected data size.
(SPIxCON<31>) = 0
17.2.3.1 Slave Mode Operations The remaining bits are shown with example configura-
The SDO pin is an output and the SPI pin is an input. tions and may be configured as desired:
Setting the control bit, DISSDO (SPIxCON<12>), • Enable module control of SDO pin –
disables transmission at the SDO pin if Receive Only DISSDO (SPIxCON<12>) = 0
mode of operation is desired. • Configure SCK clock polarity to Idle high –
Refer to Table 17-7. CKP (SPIxCON<6>) = 1
The SDI (input) must be configured to properly sample • Configure SCK clock edge transition from Idle to
the data received from the slave device by configuring active – CKE (SPIxCON<8>) = 0
the sample bit, SMP (SPIxCON<9>). • Disable Slave Select Pin –
SSEN (SPIxCON<7>) = 0
Refer to timing diagram shown in Figure 17-4 to deter-
mine the appropriate settings. • Select 16-bit data width –
MODE<32,16> (SPIxCON<11:10>) = 01
Data transfers can be 8, 16, or 32 bits and are
configured using control bits. MODE<32,16>
(SPIxCON<11:10>).
• Enable SPI module when CPU Idle –
Refer to Section 17.2.1 “8, 16, and 32-bit Operation” SIDL (SPIxCON<13>) = 0
for details.
Slave Select Synchronization: The SSx pin allows a
Synchronous Slave mode. If the SSEN (SPIxCON<7>)
bit is set, transmission and reception is enabled in
Slave mode only if the SSx pin is driven to a low state.
If the SSEN bit is not set, the SSx pin does not affect
the module operation in Slave mode.

PIC32MX3XX/4XX
17.2.3.3 Slave Mode Initialization
The following steps are used to set up the SPI module
for the Slave mode of operation:
1. If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
ON bit.
1. If using interrupts, the following additional steps
are performed:
• Clear the SPIx interrupt flags/events in the
respective IFS0/1 register.
• Set the SPIx interrupt enable bits in the
respective IEC0/1 register.
• Write the SPIx interrupt priority and subprior-
ity bits in the respective IPC5/7 register.
2. Clear the SPIROV bit (SPIxSTAT<6>).
3. Write the selected configuration settings to the
SPIxCON register with MSTEN
(<SPIxCON<5>) = 0.
4. Enable SPI operation by setting the ON bit
(SPIxCON<15>).
5. Transmission (and reception) will start as soon
as the master provides the serial clock.
Note 1: The user must turn off the SPI device

prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
2: The SPI device must be turned off prior to
changing the mode from Master to Slave.
3: The SPIxSR register cannot be written
into directly by the user. All writes to the
SPIxSR register are performed through

PIC32MX3XX/4XX
FIGURE 17-4: SPI SLAVE MODE OPERATION IN 8-BIT MODE WITH SLAVE SELECT PIN
DISABLED (MODE32 = 0, MODE16 = 0, SSEN = 0)
SCKx Input(1)
(CKP = 0
CKE = 0)
SCKx Input(1)
(CKP = 1
CKE = 0)

Output
SDIx Input
(3)
Input
Sample
(SMP = 0)
User writes to
SPIxBUF(2)
SPITBE
SPIxSR to
SPIxRXB
SPIRBF
approx. 2 SYSCLK latency to set

SPIxRXIF flag bit
SPIxRXIF
Note 1: Two SPI Clock modes shown only to demonstrate CKP (SPIxCON<6>) and CKE (SPIxCON<8>) bit functionality.
Any combination of CKP and CKE bits can be chosen for module operation.
2: If there are no pending transmissions or a transmission in progress, SPIxBUF is transferred to SPIxSR as soon as
the user writes to SPIxBUF.
3: The operation for 8-bit mode is shown. The 16-bit and 32-bit modes are similar.

PIC32MX3XX/4XX
EXAMPLE 17-2: FOR 16-BIT SPI SLAVE MODE INITIALIZATION
/*
The following code example will initialize the SPI1 in slave mode with SSEN.
It assumes that the SPI1 SS input pin on RB2 is shared with the AN2 analog input.
It thus properly configures the corresponding AD1PCFG and TRIS registers bits.
*/
int rData;
IEC0CLR=0x03800000; // disable all interrupts

TRISBSET = 0x4; // Set RB2 as a digital input
AD1PCFGSET = 0x4; // Analog input pin in digital mode

SPI1CON=0x8000; // SPI ON, 8 bits transfer, Slave Mode
// from now on, the device is ready to receive and transmit data

PIC32MX3XX/4XX
17.2.4 FRAMED SPI MODES The following framed SPI modes are supported by the
SPI module:
The module supports a very basic framed SPI protocol
while operating in either Master or Slave modes. The • Frame Master mode: The SPI module generates
following features are provided in the SPI module to the frame synchronization pulse and provides this
support Framed SPI modes: pulse to other devices at the SSx pin.
• The control bit, FRMEN (SPIxCON<31>), enables • Frame Slave mode: The SPI module uses a frame
Framed SPI mode and causes the SSx pin to be synchronization pulse received at the SSx pin.
used as a frame synchronization pulse input or The Framed SPI modes are supported in conjunction
output pin. The state of the SSEN (SPIxCON<7>) with the Master and Slave modes. Thus, the following
is ignored. framed SPI configurations are available:
• The control bit, FRMSYNC (SPIxCON<30>), • SPI Master mode and Frame Master mode
determines whether the SSx pin is an input or an
• SPI Master mode and Frame Slave mode
output (i.e., whether the module receives or
generates the frame synchronization pulse). • SPI Slave mode and Frame Master mode
• The FRMPOL (SPIxCON<29>) determines the • SPI Slave mode and Frame Slave mode
frame synchronization pulse polarity for a single These four modes determine whether or not the SPI
SPI clock cycle. module generates the serial clock and the frame
synchronization pulse.
FIGURE 17-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM
[SPI Master, Frame Master] [SPI Slave, Frame Slave]
SDOx SDIx
Serial Receive Buffer Serial Receive Buffer

(SPIxRXB)(3) (SPIxRXB)
Shift Register SDIx SDOx Shift Register

(SPIxSR) (SPIxSR)
MSb LSb MSb LSb
Serial Transmit Buffer Serial Transmit Buffer

(SPIxTXB)(3) (SPIxTXB)
Serial Clock
SPI Buffer SCKx SCKx SPI Buffer
(SPIxBUF) (SPIxBUF)
SSx SSx
Frame Sync
Pulse(1, 2)
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse.
2: Framed SPI modes require the use of all four pins, i.e., using the SSx pin is not optional.
3: The SPIxTXB and SPIxRXB registers are memory mapped to the SPIxBUF register.

PIC32MX3XX/4XX
17.2.4.1 SPI Master Mode and Frame Master • Select SSx active-low pin polarity – FRMPOL
Mode Operations (SPIxCON<29>) = 0
This Framed SPI mode is enabled by setting bits • Select 16-bit data width –
MSTEN (SPIxCON<5>) and FRMEN (SPIxCON<31>) MODE<32,16> (SPIxCON<11:10>) = 01
to ‘1’, and bit FRMSYNC (SPIxCON<30>) to ‘0’. In this • Sample data input at middle –
mode, the serial clock will be output continuously at the SMP (SPIxCON<9>) = 0
SCKx pin, regardless of whether the module is • Enable SPI module when CPU Idle – SIDL
transmitting. When SPIxBUF is written, the SSx pin will (SPIxCON<13>) = 0
be driven active, high or low depending on bit FRMPOL
(SPIxCON<29>), on the next transmit edge of the 17.2.4.3 Framed Master Mode Initialization
SCKx clock. The SSx pin will be active for one SCKx The following steps are used to set up the SPI module
clock cycle. The module will start transmitting data on for the Master mode of operation:
the same or on the next transmit edge of the SCKx,
depending on the SPIFE (SPIxCON<17>) setting, as 1. If interrupts are used, disable the SPI interrupts
shown in Figure 17-6. A connection diagram indicating in the respective IEC0/1 register.
signal directions for this operating mode is shown in 2. Stop and reset the SPI module by clearing the
Figure 17-5. ON bit.
The SCK, SDO and SSx pins are outputs, the SDI pin 3. Clear the receive buffer.
is an input. Setting the control bit, DISSDO 4. If using interrupts, the following additional steps
(SPIxCON<12>), disables transmission at the SDO pin are performed:
if Receive Only mode of operation is desired; refer to • Clear the SPIx interrupt flags/events in the
Table 17-7. respective IFS0/1 register.
The SDI (input) must be configured to properly sample • Set the SPIx interrupt enable bits in the
the data received from the slave device by configuring respective IEC0/1 register.
the sample bit, SMP (SPIxCON<9>). • Write the SPIx interrupt priority and subprior-
In Master mode, the SCK clock edge and polarity must ity bits in the respective IPC5/7 register.
be configured properly for the master and slave device 5. Clear the SPIROV bit (SPIxSTAT<6>).
to correctly transfer data synchronously. 6. Write the selected configuration settings to the
Refer to timing diagram shown in Figure 17-3 to deter- SPIxCON register.
mine the appropriate settings. 7. Enable SPI operation by setting the ON bit
(SPIxCON<15>).
17.2.4.2 Master SPIxCON Configuration
The following bits must be configured as shown for the
Master mode of operation when configuring the
Otherwise, the behavior of the device is
SPIxCON register:
not ensured.
• Enable Master Mode –
2: The SPIxSR register cannot be written
MSTEN (SPIxCON<5>) = 1
• Enable Framed SPI support – SPIxSR register are performed through
FRMEN (SPIxCON<31>) = 1 the SPIxBUF register.
• Select SSx pin as Frame Master (output) –
FRMSYNC(SPIxCON<30>) = 0
• Enable module control of SDO pin –
SDO (SPIxCON<12>) = 0
• Configure SCK clock polarity to Idle high –

PIC32MX3XX/4XX
FIGURE 17-6: SPI MASTER, FRAME MASTER MODE32 = 0, MODE16 = 1, SPIFE = 0,
FRMPOL = 1
SCKx
(CKP = 1)
SCKx
(CKP = 0)
SSx
SDOx bit 15 bit 14 bit 13 bit 12
SDIx bit 15 bit 14 bit 13 bit 12
Write to SPIxBUF Receive Samples at SDIx

Pulse generated at SSx

PIC32MX3XX/4XX
17.2.4.4 SPI Master Mode and Frame Slave • Select SSx active low pin polarity –
Mode Operations FRMPOL (SPIxCON<29>) = 0
This Framed SPI mode is enabled by setting bits • Select 16-bit data width –
MSTEN (SPIxCON<5>), FRMEN (SPIxCON<31>), MODE<32,16> (SPIxCON<11:10>) = 01
and FRMSYNC (SPIxCON<30>) to ‘1’. The SSx pin is • Sample data input at middle –
an input, and it is sampled on the sample edge of the SMP (SPIxCON<9>) = 0
SPI clock. When it is sampled active, high, or low • Enable SPI module when CPU Idle –
depending on bit FRMPOL (SPIxCON<29>), data will SIDL (SPIxCON<13>) = 0
be transmitted on the subsequent transmit edge of the
SPI clock, as shown in Figure 17-7. The interrupt flag 17.2.4.6 Framed Slave Mode Initialization
SPIxIF is set when the transmission is complete. The The following steps are used to set up the SPI module
user must make sure that the correct data is loaded into for the Slave mode of operation:
the SPIxBUF for transmission before the signal is
received at the SSx pin. A connection diagram 1. If interrupts are used, disable the SPI interrupts
indicating signal directions for this operating mode is in the respective IEC0/1 register.
shown in Figure 17-8. 2. Stop and reset the SPI module by clearing the
ON bit.
The SCK and SDO pins are outputs, the SDI and SSx
pins are inputs. Setting the control bit, DISSDO 3. Clear the receive buffer.
(SPIxCON<12>), disables transmission at the SDO pin 4. If using interrupts, the following additional steps
if Receive Only mode of operation is desired; refer to are performed:
Table 17-7. • Clear the SPIx interrupt flags/events in the
The SDI pin must be configured to properly sample the respective IFS0/1 register.
data received from the slave device by configuring the • Set the SPIx interrupt enable bits in the
sample bit, SMP (SPIxCON<9>). respective IEC0/1 register.
In Master mode, the SCK clock edge and polarity must • Write the SPIx interrupt priority and
be configured properly for the master and slave device subpriority bits in the respective IPC5/7
to correctly transfer data synchronously. register.
Refer to timing diagram shown in Figure 17-3 to
determine the appropriate settings. 6. Write the selected configuration settings to the
SPIxCON register.
17.2.4.5 Master SPIxCON Configuration 7. Enable SPI operation by setting the ON bit
(SPIxCON<15>).
The following bits must be configured as shown for the
Master mode of operation when configuring the
SPIxCON register:
• Enable Master Mode – Otherwise, the behavior of the device is
MSTEN (SPIxCON<5>) = 1 not ensured.
• Enable Framed SPI support – 2: The SPIxSR register cannot be written
FRMEN (SPIxCON<31>) = 1 into directly by the user. All writes to the
• Select SSx pin as Frame Slave (input) – SPIxSR register are performed through
FRMSYNC (SPIxCON<30>) = 1 the SPIxBUF register.
The remaining bits are shown with example 3: Receiving a frame sync pulse will start a
configurations and may be configured as desired: transmission, regardless of whether or
• Enable module control of SDO pin – not data was written to SPIxBUF. If a
DISSDO (SPIxCON<12>) = 0 write was not performed, zeros will be
transmitted.

PIC32MX3XX/4XX
FIGURE 17-7: SPI MASTER, FRAME SLAVE MODE32 = 0, MODE16 = 1, SPIFE = 0,
FRMPOL = 1
SCKx
(CKP = 1)
SCK
(CKP = 0)
FSYNC
SDO bit 15 bit 14 bit 13 bit 12
SDI bit 15 bit 14 bit 13 bit 12
Write to Sample SSx pin

SPIxBUF Receive Samples at SDIx
for Frame Sync Pulse
FIGURE 17-8: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM
[SPI Master, Frame Slave] [SPI Slave, Frame Master]
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse(1,2)
2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).

PIC32MX3XX/4XX
17.2.4.7 SPI Slave Mode and Frame Master 17.2.4.9 Framed Master Mode Initialization
Mode The following steps are used to set up the SPI module
This Framed SPI mode is enabled by setting bit for the Slave mode of operation:
MSTEN (SPIxCON<5>) to ‘0’, bit FRMEN 1. If interrupts are used, disable the SPI interrupts
(SPIxCON<31>) to ‘1’ and bit FRMSYNC in the respective IEC0/1 register.
(SPIxCON<30>) to ‘0’. The input SPI clock will be con-
tinuous in Slave mode. The SSx pin will be an output
ON bit.
when bit FRMSYNC is low. Therefore, when SPIBUF is
written, the module will drive the SSx pin active, high or 3. Clear the receive buffer.
low depending on bit FRMPOL (SPIxCON<29>), on the 4. If using interrupts, the following additional steps
next transmit edge of the SPI clock. The SSx pin will be are performed:
driven active for one SPI clock cycle. Data transmission • Clear the SPIx interrupt flags/events in the
will start on the next SPI clock transmit edge. A respective IFS0/1 register.
connection diagram indicating signal directions for this • Set the SPIx interrupt enable bits in the
operating mode is shown in Figure 17-9. respective IEC0/1 register.
The SDO and SSx pins are outputs and the SCK and • Write the SPIx interrupt priority and
SDI pins are inputs. Setting the control bit, DISSDO subpriority bits in the respective IPC5/7
(SPIxCON<12>), disables transmission at the SDO pin register.
if Receive Only mode of operation is desired; refer to 5. Clear the SPIROV bit (SPIxSTAT<6>).
Table 17-7. 6. Write the selected configuration settings to the
The SDI pin must be configured to properly sample the SPIxCON register.
data received from the slave device by configuring the 7. Enable SPI operation by setting the ON bit
sample bit, SMP (SPIxCON<9>). (SPIxCON<15>).
Refer to timing diagram shown in Figure 17-6 to 8. Transmission (and reception) will start as soon
determine the appropriate settings. as the master provides the serial clock.
17.2.4.8 Slave SPIxCON Configuration Note 1: The user must turn off the SPI device
The following bits must be configured as shown for the prior to changing the CKE or CKP bits.
Slave mode of operation when configuring the Otherwise, the behavior of the device is
SPIxCON register: not ensured.
• Enable Slave Mode – MSTEN (SPIxCON<5>) = 1 2: The SPIxSR register cannot be written
• Enable Framed SPI support – FRMEN
SPIxSR register are performed through
(SPIxCON<31>) = 1
• Select SSx pin as Frame Master (output) –
FRMSYNC(SPIxCON<30>) = 0
• Enable module control of SDO pin –
DISSDO (SPIxCON<12>) = 0
• Select SSx active low pin polarity –
FRMPOL (SPIxCON<29>) = 0
• Select 16-bit data width – MODE<32,16>
(SPIxCON<11:10>) = 01

PIC32MX3XX/4XX
FIGURE 17-9: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM
[SPI Slave, Frame Master] [SPI Master, Frame Slave]
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse(1)(2)
17.2.4.10 SPI Slave Mode and Frame Slave 17.2.4.11 Slave SPIxCON Configuration
Mode The following bits must be configured as shown for the
This Framed SPI mode is enabled by setting bits Slave mode of operation when configuring the
MSTEN (SPIxCON<5>) to ‘0’, FRMEN SPIxCON register:
(SPIxCON<31>) to ‘1’, and FRMSYNC • Enable Slave Mode –
(SPIxCON<30>) to ‘1’. Therefore, both the SCKx and MSTEN (SPIxCON<5>) = 0
SSx pins will be inputs. The SSx pin will be sampled on
• Enable Framed SPI support –
the sample edge of the SPI clock. When SSx is sam-
FRMEN (SPIxCON<31>) = 1
pled active, high or low depending on bit, FRMPOL
(SPIxCON<29>), data will be transmitted on the next • Select SSx pin as Frame Slave (input) –
transmit edge of SCKx. A connection diagram FRMSYNC(SPIxCON<30>) = 1
indicating signal directions for this operating mode is The remaining bits are shown with example
shown in Figure 17-10. configurations and may be configured as desired:
The SDO pins is an output and the SCK, SDI and SSx • Enable module control of SDO pin –
pins are inputs. Setting the control bit, DISSDO DISSDO (SPIxCON<12>) = 0
(SPIxCON<12>), disables transmission at the SDO pin • Configure SCK clock polarity to Idle high –
if Receive Only mode of operation is desired; refer to CKP (SPIxCON<6>) = 1
Table 17-7. • Configure SCK clock edge transition from Idle to
The SDI pin must be configured to properly sample the active – CKE (SPIxCON<8>) = 0
data received from the slave device by configuring the • Select SSx active-low pin polarity –
sample bit, SMP (SPIxCON<9>). FRMPOL (SPIxCON<29>) = 0
Refer to timing diagram shown in Figure 17-7 to • Select 16-bit data width –
determine the appropriate settings. MODE<32,16> (SPIxCON<11:10>) = ‘01’

PIC32MX3XX/4XX
17.2.4.12 Framed Slave Mode Initialization Note 1: The user must turn off the SPI device
The following steps are used to set up the SPI module prior to changing the CKE or CKP bits.
for the Slave mode of operation: Otherwise, the behavior of the device is
not ensured.
1. If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register. 2: The SPIxSR register cannot be written
2. Stop and reset the SPI module by clearing the into directly by the user. All writes to the
ON bit. SPIxSR register are performed through
4. If using interrupts, the following additional steps 3: Receiving a frame sync pulse will start a
are performed: transmission, regardless of whether or
not data was written to SPIxBUF. If a
• Clear the SPIx interrupt flags/events in the
write was not performed, zeros will be
respective IFS0/1 register.
transmitted.
• Set the SPIx interrupt enable bits in the
respective IEC0/1 register.
• Write the SPIx interrupt priority and
subpriority bits in the respective IPC5/7
register.
6. Write the selected configuration settings to the
SPIxCON register.
7. Enable SPI operation by setting the ON bit
(SPIxCON<15>).
8. Transmission (and reception) will start as soon
as the master provides the serial clock.
FIGURE 17-10: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM
[SPI Slave, Frame Slave] [SPI Master, Frame Master]
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse(1)(2)(3)
3: Slave Select is not available when using Frame mode as a slave device.

PIC32MX3XX/4XX
17.2.5 SPI MASTER MODE CLOCK
FREQUENCY
In Master mode, the SPI module clock source is the
peripheral bus clock (PBCLK) and the SCK clock baud
rate is derived from the PBCLK clock and the SPIxBRG
register.
Equation 17-1 defines the SCKx clock frequency as a
function of the SPIxBRG register settings.
EQUATION 17-1: SPI CLOCK FREQUENCY
FPB
FSCK =
2 * (SPIxBRG+1)
Note that the maximum possible baud rate is

FPB/2 (SPIXBRG = 0) and the minimum possible baud
rate is FPB /1024.
Sample SPI clock frequencies are shown in the table

Table 17-6.
Note: The SCKx signal clock is not free running
for nonframed SPI modes. It will only run
for 8, 16 or 32 pulses when the SPIxBUF
is loaded with data. It will however, be
continuous for Framed modes.
TABLE 17-6: SAMPLE SCKX FREQUENCIES

SPIxBRG setting 0 15 31 63 85 127
FPB = 50 MHz 25.00 MHz 1.56 MHz 781.25 KHz 390.63 KHz 290.7 KHz 195.31 KHz
FPB = 40 MHz 20.00 MHz 1.25 MHz 625.00 KHz 312.50 KHz 232.56 KHz 156.25 KHz
FPB = 25 MHz 12.50 MHz 781.25 KHz 390.63 KHz 195.31 KHz 145.35 KHz 97.66 KHz
FPB = 20 MHz 10.00 MHz 625.00 KHz 312.50 KHz 156.25 KHz 116.28 KHz 78.13 KHz
FPB = 10 MHZ 5.00 MHz 312.50 KHz 156.25 KHz 78.13 KHz 58.14 KHz 39.06 KHz
17.2.6 SPI Error Handling

When a new data word has been shifted into shift reg-
ister SPIxSR and the previous contents of receive reg-
ister SPIxRXB have not been read by the user
software, the SPIROV bit (SPIxSTAT<6>) will be set.
The module will not transfer the received data from
SPIxSR to the SPIxRXB. Further data reception is dis-
abled until the SPIROV bit is cleared. The SPIROV bit
is not cleared automatically by the module and must be
cleared by the user software.

PIC32MX3XX/4XX
17.3 SPI Interrupts An SPI device is enabled as a source of interrupts via
the respective SPI interrupt enable bits:
The SPI module has the ability to generate interrupts
reflecting the events that occur during the data commu- • SPI1RXIE (IEC0<25>) and SPI2RXIE (IEC1<7>)
nication. The following types of interrupts can be • SPI1TXIE (IEC0<24>) and SPI2TXIE (IEC1<6>)
generated: • SPI1EIE (IEC0<23>) and SPI2EIE (IEC1<5>)
• Receive data available interrupts, signalled by The interrupt priority level bits and interrupt subpriority
SPI1RXIF (IFS0<25>), SPI2RXIF (IFS1<7>). This level bits must be also be configured:
event occurs when there is new data assembled • SPI1IP (IPC5<28:26>), SPI1IS (IPC5<25:24>)
in the SPIxBUF receive buffer.
• SPI2IP (IPC7<28:26>), SPI2IS (IPC7<25:24>)
• Transmit buffer empty interrupts, signalled by
SPI1TXIF (IFS0<24>), SPI2TXIF (IFS1<6>). This In addition to enabling the SPI interrupts, an Interrupt
event occurs when there is space available in the Service Routine, ISR, is required. Example 17-3 is a
SPIxBUF transmit buffer and new data can be partial code example of an ISR.
written. Note: It is the user’s responsibility to clear the
• Receive buffer overflow interrupts, signalled by corresponding interrupt flag bit before
SPI1EIF (IFS0<23>), SPI2EIF(IFS1<5>). returning from an ISR.
This event occurs when there is an overflow
condition for the SPIxBUF receive buffer, i.e., new
receive data assembled but the previous one is
not read.
EXAMPLE 17-3: SPI INITIALIZATION WITH INTERRUPTS ENABLED

/*
The following code example illustrates an SPI1 interrupt configuration.
When the SPI1 interrupt is generated, the cpu will jump to the vector assigned to SPI1
interrupt.
It assumes that none of the SPI1 input pins are shared with an analog input.
If so, the AD1PCFG and corresponding TRIS registers have to be properly configured.
*/
int rData;
IEC0CLR=0x03800000; // disable all SPI interrupts

SPI1BRG=0x1; // use FPB/4 clock frequency

SPI1CON=0x8220; // SPI ON, 8 bits transfer, SMP=1, Master Mode

PIC32MX3XX/4XX
EXAMPLE 17-4: SPI1 ISR
/*
The following code example demonstrates a simple interrupt service routine for SPI1
interrupts. The user’s code at this vector should perform any application specific
operations and must clear the SPI1 interrupt flags before exiting.
*/
void __ISR(_SPI_1_VECTOR, ipl3) __SPI1Interrupt(void)

{
// ... perform application specific operations in response to the interrupt
IFS0CLR = 0x03800000; // Be sure to clear the SPI1 interrupt flags

}
Note: The SPI1 ISR code example shows

MPLAB® C32 C Compiler-specific syntax.
Refer to your compiler manual regarding
support for ISRs.

PIC32MX3XX/4XX
Enabling the SPI modules will configure the I/O pin
direction as defined by the SPI control bits (see
Table 17-7). The port TRIS and LATCH registers will be
overridden.
TABLE 17-7: I/O PIN CONFIGURATION FOR USE WITH SPI MODULES
Required Settings for Module Pin Control
Module Bit
IO Pin Name Required TRIS(4) Pin Type Buffer Type Description
Control(3) Field(3)
ON SPI1, SPI2 module Clock
SCK1, SCK2 Yes and — X O CMOS Output in Master Mode.
MSTEN
ON SPI1, SPI2 module Clock
SCK1, SCK2 Yes and — X(5) I CMOS Input in Slave Mode.
MSTEN
SDI1, SDI2 Yes ON — X(5) I CMOS SPI1, SPI2 module Data
Receive pin.
SDO1, SDO2 Yes(1) ON DISSDO X O CMOS SPI1, SPI2 module Data
Transmit pin.
ON
SS1, SS2 Yes(2) and SSEN X(5) I CMOS SPI1, SPI2 module Slave
FRMEN Select Control pin.
and
MSTEN
ON
SS1, SS2 Yes and — X(5) I CMOS SPI1, SPI2 Frame Sync
FRMEN Pulse input in Frame Mode.
and
FRMSYNC
ON
SS1, SS2 Yes and — X O CMOS SPI1,SPI2 Frame Sync
FRMEN Pulse output in Frame Mode.
and
FRMSYNC
Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input;
O = Output; X = Don’t Care
Note 1: The SDO pins are only required when SPI data output is needed. Otherwise, these pins can be used for
general purpose I/O and require the user to set the corresponding TRIS control register bits.
2: The Slave Select pins are only required when a select signal to the slave device is needed. Otherwise,
these pins can be used for general purpose I/O and require the user to set the corresponding
TRIS control register bits.
3: These bits are contained in the SPIxCON register.
4: The setting of the TRIS bit is irrelevant.
5: If the input pin is shared with an analog input, then the AD1PCFG and the corresponding TRIS register
have to be properly set to configure this input as digital.

PIC32MX3XX/4XX
18.0 INTER-INTEGRATED CIRCUIT 18.2 I2C Registers
(I2C™) The I2CxCON register allows control of the module’s
operation. The I2CxCON register is readable and writ-
able. I2CxSTAT register contains status flags indicating
the module’s state during operation.
ence source. Refer to the “PIC32MX Family I2CxRCV is the receive register. When the incoming
Reference Manual” (DS61132) for a data is shifted completely, it is moved to the I2CxRCV
detailed description of this peripheral. register. I2CxTRN is the transmit register to which
bytes are written during a transmit operation.
The Inter-Integrated Circuit (I2C) module provides
The I2CxADD register holds the slave address. A
complete hardware support for both Slave and Multi-
Status bit, ADD10, indicates 10-bit Addressing mode.
Master modes of the I2C serial communication
The I2CxBRG acts as the Baud Rate Generator (BRG)
standard. Figure 18-1 shows the I2C module block
reload value.
diagram.
In receive operations, I2CxRSR and I2CxRCV together
The PIC32MX3XX/4XX devices have up to two I2C
form a double-buffered receiver. When I2CxRSR
interface modules, denoted as I2C1 and I2C2. Each
receives a complete byte, it is transferred to I2CxRCV
I2C module has a 2-pin interface: the SCLx pin is clock
and an interrupt pulse is generated. The I2CxRSR shift
and the SDAx pin is data.
register is not directly accessable to the programmer.
Each I2C module ‘I2Cx’ (x = 1 or 2) offers the following
key features: 18.3 I2C Interrupts
2C
• I Interface Supporting both Master and Slave
The I2C module generates three interrupt signals:
Operation.
Slave Interrupt (I2CxSIF), Master Interrupt (I2CxMIF)
• I2C Slave Mode Supports 7 and 10-bit Address. and Bus Collision Interrupt (I2CxBIF).
• I2C Master Mode Supports 7 and 10-bit Address.
• I2C Port allows Bidirectional Transfers between 18.4 Baud Rate Generator
Master and Slaves.
• Serial Clock Synchronization for I2C Port can be In I2C Master mode, the reload value for the Baud Rate
used as a Handshake Mechanism to Suspend Generator (BRG) resides in the I2CxBRG register.
and Resume Serial Transfer (SCLREL control). When the BRG is loaded with this value, the BRG
counts down to ‘0’ and stops until another reload has
• I2C Supports Multi-master Operation; Detects Bus
taken place. If clock arbitration is taking place, for
Collision and Arbitrates Accordingly.
instance, the BRG is reloaded when the SCLx pin is
• Provides Support for Address Bit Masking. sampled high.
As per the I2C standard, FSCL may be 100 kHz or
18.1 Operating Modes 400 kHz. However, the user can specify any baud rate
The hardware fully implements all the master and slave up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing. EQUATION 18-1: SERIAL CLOCK RATE
2
The I C module can operate either as a slave or a
master on an I2C bus.
The following types of I2C operation are supported:
I2CxBRG = [ PBCLK
FSCL x 2 ] -2
• I2C Slave Operation with 7 or 10-bit Address

PBCLK is the peripheral clock speed. FSCL is the
• I2C Master Operation with 7 or 10-bit Address desired I2C bus speed.
For details about the communication sequence in each
of these modes, please refer to the “PIC32MX3XX/4XX
Reference Manual” (DS61132).

PIC32MX3XX/4XX
FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSB
SDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start and Stop

Bit Generation I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSB
Shift Clock Read
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
PBCLK

PIC32MX3XX/4XX
18.5 I2C Module Addresses 18.8 General Call Address Support
The I2CxADD register contains the Slave mode The general call address is used to address all devices.
addresses. The register is a 10-bit register. When this address is used, all devices should, in
If the A10M bit (I2CxCON<10>) is ‘0’, the address is theory, respond with an Acknowledgement.
interpreted by the module as a 7-bit address. When an The general call address is one of eight addresses
address is received, it is compared to the 7 Least reserved for specific purposes by the I2C protocol. It
Significant bits of the I2CxADD register. consists of all ‘0’s with R/W = 0.
If the A10M bit is ‘1’, the address is assumed to be a The general call address is recognized when the General
10-bit address. When the first address byte is received, Call Enable (GCEN) bit is set (I2CxCON<7> = 1). When
it will be compared with the binary value, ‘11110 A9 the interrupt is serviced, the source for the interrupt can
A8 R/W = 0 (where A9 and A8 are Most Significant bits be checked by reading the contents of the I2CxRCV to
of the 10-bit address stored in I2CxADD). If that value determine if the address was device-specific or a general
matches, the next address byte will be compared with call address. Upon detection of general call address,
the Least Significant 8 bits of I2CxADD, as specified in GCSTAT (I2CxSTAT<9>) bit is set. This method is
the 10-bit addressing protocol. available in both 7-bit and 10-bit Addressing modes.
TABLE 18-1: 7-BIT I2C™ SLAVE 18.9 Automatic Clock Stretch

ADDRESSES SUPPORTED BY
In Slave modes, the module can synchronize buffer
PIC32MX3XX/4XX
reads and writes to the master device by clock
0x00 General call address or Start byte stretching.
0x01-0x03 Reserved
18.9.1 TRANSMIT CLOCK STRETCHING
0x04-0x07 Hs mode Master codes
0x08-0x77 Valid 7-bit addresses Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
0x78-0x7b 10-bit address upper byte edge of the ninth clock, if the TBF bit is cleared,
0x7c-0x7f Reserved indicating the buffer is empty.
In Slave Transmit modes, clock stretching is always
18.6 Slave Address Masking performed, irrespective of the STREN bit. The user’s
ISR must set the SCLREL bit before transmission is
The I2CxMSK register (Register 18-4) designates
allowed to continue. By holding the SCLx line low, the
address bit positions as “don’t care” (= 1) for both 7-bit
user has time to service the ISR and load the contents
and 10-bit Addressing modes. Setting a particular bit
of the I2CxTRN before the master device can initiate
location (= 1) in the I2CxMSK register, causes the slave
another transmit sequence.
module to respond, whether the corresponding
address bit value is a ‘0’ or ‘1’. For example, when
18.9.2 RECEIVE CLOCK STRETCHING
I2CxMSK is set to ‘00110000’, the slave module will
detect both addresses, ‘0000000’ and ‘00100000’. The STREN bit in the I2CxCON register can be used to
enable clock stretching in Slave Receive mode. When
18.7 Strict Addressing Support the STREN bit is set, the SCLx pin will be held low at
the end of each data receive sequence.
The control bit, STRICT, enables the module to support The user’s ISR must set the SCLREL bit before recep-
the strict addressing. It enables the module to enforce tion is allowed to continue. By holding the SCLx line
all reserved addresses if they fall within the reserved low, the user has time to service the ISR and read the
address table. If the user wants to enforce the reserved contents of the I2CxRCV before the master device can
address space, the STRICT (I2CxCON<11>) bit must initiate another receive sequence. This will prevent buf-
be set to ‘1’. Once the bit is set, the device will not fer overruns from occurring.
acknowledge reserved addresses, regardless of the
address mask settings.
18.10 Software Controlled Clock
Stretching (STREN = 1)
When the STREN bit is ‘1’, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching.
If the STREN bit is ‘0’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.

PIC32MX3XX/4XX
18.11 Slope Control 18.13 Multi-Master Communication, Bus
2
The I C standard requires slope control on the SDAx
Collision and Bus Arbitration
and SCLx signals for Fast mode (400 kHz). The control Multi-Master mode support is achieved by bus
bit, DISSLW, enables the user to disable slew rate arbitration. When the master outputs address/data bits
control if desired. It is necessary to disable the slew onto the SDAx pin, arbitration takes place when the
rate control for 1 MHz mode. master outputs a ‘1’ on SDAx by letting SDAx float high
while another master asserts a ‘0’. When the SCLx pin
18.12 Clock Arbitration floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the
Clock arbitration occurs when the master deasserts the SDAx pin = 0, then a bus collision has taken place. The
SCLx pin (SCLx allowed to go high by external pull-up master will set the I2C master events interrupt flag and
resistors) during any receive, transmit or Restart/Stop reset the master portion of the I2C port to its Idle state.
condition. When the SCLx pin is allowed to float high,
the Baud Rate Generator (BRG) is suspended from
counting until the SCLx pin is actually sampled high.
When the SCLx pin is sampled high, the Baud Rate
Generator is reloaded with the contents of I2CxBRG
and begins counting. This ensures that the SCLx high
time will always be at least one BRG rollover count in
the event that the clock is held low by an external
device.
FIGURE 18-2: TYPICAL I2C™ INTERCONNECTION BLOCK DIAGRAM
VDD VDD
PIC32MX3XX/4XX 4.7 kΩ 24LC256

(typical)
SCLX SCL
SDAX SDA

PIC32MX3XX/4XX
TABLE 18-2: I2C1 SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_5000 I2C1CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN
7:0 GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
BF80_0004 I2C1CONCLR 31:0 Clears selected bits of I2C1CON, read yields undefined value
BF80_5008 I2C1CONSET 31:0 Sets selected bits of I2C1CON, read yields undefined value
BF80_500C I2C1CONINV 31:0 Inverts selected bits of I2C1CON, read yields undefined value
BF80_5010 I2C1STAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
7:0 IWCOL I2COV D/A P S R/W RBF TBF
BF80_5014 I2C1STATCLR 31:0 Clears selected bits of I2C1STAT, read yields undefined value
BF80_5018 I2C1STATSET 31:0 Sets selected bits of I2C1STAT, read yields undefined value
BF80_501C I2C1STATINV 31:0 Inverts selected bits of I2C1STAT, read yields undefined value
BF80_5020 I2C1ADD 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — ADD<9:8>
7:0 ADD<7:0>
BF80_5024 I2C1ADDCLR 31:0 Clears selected bits of I2C1ADD, read yields undefined value
BF80_5028 I2C1ADDSET 31:0 Sets selected bits of I2C1ADD, read yields undefined value
BF80_502C I2C1ADDINV 31:0 Inverts selected bits of I2C1ADD, read yields undefined value
BF80_5030 I2C1MSK 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — MSK<9:8>
7:0 MSK<7:0>
BF80_5034 I2C1MSKCLR 31:0 Clears selected bits of I2C1MSK, read yields undefined value
BF80_5038 I2C1MSKSET 31:0 Sets selected bits of I2C1MSK, read yields undefined value
BF80_503C I2C1MSKINV 31:0 Inverts selected bits of I2C1MSK, read yields undefined value
BF80_5040 I2C1BRG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — I2C1BRG<11:8>
7:0 I2C1BRG<7:0>
BF80_5044 I2C1BRGCLR 31:0 Clears selected bits of I2C1BRG, read yields undefined value
BF80_5048 I2C1BRGSET 31:0 Sets selected bits of I2C1BRG, read yields undefined value
BF80_504C I2C1BRGINV 31:0 Inverts selected bits of I2C1BRG, read yields undefined value
BF80_5050 I2C1TRN 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 I2CT1DATA
BF80_5054 I2C1TRNCLR 31:0 Clears selected bits of I2C1TRN, read yields undefined value
BF80_5058 I2C1TRNSET 31:0 Sets selected bits of I2C1TRN, read yields undefined value
BF80_505C I2C1TRNINV 31:0 Inverts selected bits of I2C1TRN, read yields undefined value
BF80_5060 I2C1RCV 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 I2CR1DATA
TABLE 18-3: I2C1 INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10F0 IPC6 15:8 — — — I2C1IP<2:0> I2C1IS<1:0>
Note: This summary table contains partial register definitions that only pertain to the I2C1 peripheral. Refer to the “PIC32MX Family Reference

PIC32MX3XX/4XX
TABLE 18-4: I2C2 SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_5200 I2C2CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN
7:0 GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
BF80_5204 I2C2CONCLR 31:0 Clears selected bits of I2C2CON, read yields undefined value
BF80_5208 I2C2CONSET 31:0 Sets selected bits of I2C2CON, read yields undefined value
BF80_520C I2C2CONINV 31:0 Inverts selected bits of I2C2CON, read yields undefined value
BF80_5210 I2C2STAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
7:0 IWCOL I2COV D/A P S R/W RBF TBF
BF80_5214 I2C2STATCLR 31:0 Clears selected bits of I2C2STAT, read yields undefined value
BF80_5218 I2C2STATSET 31:0 Sets selected bits of I2C2STAT, read yields undefined value
BF80_521C I2C2STATINV 31:0 Inverts selected bits of I2C2STAT, read yields undefined value
BF80_5220 I2C2ADD 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — ADD<9:8>
7:0 ADD<7:0>
BF80_5224 I2C2ADDCLR 31:0 Clears selected bits of I2C2ADD, read yields undefined value
BF80_5228 I2C2ADDSET 31:0 Sets selected bits of I2C2ADD, read yields undefined value
BF80_522C I2C2ADDINV 31:0 Inverts selected bits of I2C2ADD, read yields undefined value
BF80_5230 I2C2MSK 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — MSK<9:8>
7:0 MSK<7:0>
BF80_5234 I2C2MSKCLR 31:0 Clears selected bits of I2C2MSK, read yields undefined value
BF80_5238 I2C2MSKSET 31:0 Sets selected bits of I2C2MSK, read yields undefined value
BF80_523C I2C2MSKINV 31:0 Inverts selected bits of I2C2MSK, read yields undefined value
BF80_5240 I2C2BRG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — I2C2BRG<11:8>
7:0 I2C2BRG<7:0>
BF80_5244 I2C2BRGCLR 31:0 Clears selected bits of I2C2BRG, read yields undefined value
BF80_5248 I2C2BRGSET 31:0 Sets selected bits of I2C2BRG, read yields undefined value
BF80_524C I2C2BRGINV 31:0 Inverts selected bits of I2C2BRG, read yields undefined value
BF80_5250 I2C2TRN 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 I2CT1DATA
BF80_5254 I2C2TRNCLR 31:0 Clears selected bits of I2C2TRN, read yields undefined value
BF80_5258 I2C2TRNSET 31:0 Sets selected bits of I2C2TRN, read yields undefined value
BF80_525C I2C2TRNINV 31:0 Inverts selected bits of I2C2TRN, read yields undefined value
BF80_5260 I2C2RCV 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 I2CR1DATA
TABLE 18-5: I2C2 INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1110 IPC8 15:8 — — — I2C2IP<2:0> I2C2IS<1:0>
Note: This summary table contains partial register definitions that only pertain to the I2C2 peripheral. Refer to the “PIC32MX Family Reference

PIC32MX3XX/4XX
REGISTER 18-1: I2CXCON: I2C™ CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

ON FRZ SIDL SCLREL STRICT A10M DISSLW SMEN
bit 15 bit 8

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:

bit 15 ON: I2C Enable bit
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables I2C module; all I2C pins are controlled by PORT functions
bit 14 FRZ: Freeze in Debug Mode Control bit
1 = Freeze module operation when in Debug mode
0 = Do not freeze module operation when in Debug mode
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12 SCLREL: SCL Release Control bit
In I2C Slave mode only
Module Reset and (ON = 0) sets SCLREL = 1
If STREN = 0:
1 = Release clock
0 = Force clock low (clock stretch)
Note: Automatically cleared to ‘0’ at beginning of slave transmission.

If STREN = 1:
1 = Release clock
0 = Holds clock low (clock stretch). User may program this bit to ‘0’ to force a clock stretch at the
next SCL low.
Note: Automatically cleared to ‘0’ at beginning of slave transmission; automatically cleared to ‘0’
at end of slave reception.
bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device doesn’t respond to reserved address space or
generate addresses in reserved address space.
0 = Strict I2C Reserved Address Rule not enabled

PIC32MX3XX/4XX
REGISTER 18-1: I2CXCON: I2C™ CONTROL REGISTER (CONTINUED)
bit 10 A10M: 10-bit Slave Address Flag bit
1 = I2CxADD is a 10-bit slave address
0 = I2CADD is a 7-bit slave address
bit 9 DISSLW: Slew Rate Control Disable bit
1 = Slew rate control disabled for Standard Speed mode (100 kHz); also disabled for 1 MHz mode
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 8 SMEN: SMBus Input Levels Disable bit
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 7 GCEN: General Call Enable bit
In I2C Slave mode only
1 = Enable interrupt when a general call address is received in I2CSR. Module is enabled for reception
0 = General call address disabled
bit 6 STREN: SCL Clock Stretch Enable bit
In I2C Slave mode only; used in conjunction with SCLREL bit.
1 = Enable clock stretching
0 = Disable clock stretching
bit 5 ACKDT: Acknowledge Data bit
In I2C Master mode only; applicable during master receive. Value that will be transmitted when the
user initiates an Acknowledge sequence at the end of a receive.
1 = A NACK is sent
0 = ACK is sent
bit 4 ACKEN: Acknowledge Sequence Enable bit
In I2C Master mode only; applicable during master receive
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit; cleared by
module
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit
In I2C Master mode only.
1 = Enables Receive mode for I2C, automatically cleared by module at end of 8-bit receive data byte
0 = Receive sequence not in progress
bit 2 PEN: Stop Condition Enable bit
1 = Initiate Stop condition on SDA and SCL pins; cleared by module
0 = Stop condition idle
bit 1 RSEN: Restart Condition Enable bit
1 = Initiate Restart condition on SDA and SCL pins; cleared by module
0 = Restart condition idle
bit 0 SEN: Start Condition Enable bit
1 = Initiate Start condition on SDA and SCL pins; cleared by module
0 = Start condition idle

PIC32MX3XX/4XX
REGISTER 18-2: I2CXSTAT: I2C STATUS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R-0 R-0 r-x r-x r-x R/W-0 R-0 R-0

ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
bit 15 bit 8
R/W-0 R/W-0 R-0 R/W-0 R/W-0 R-0 R-0 R-0

IWCOL I2COV D/A P S R/W RBF TBF
bit 7 bit 0
Legend:

bit 15 ACKSTAT: Acknowledge Status bit
In both I2C Master and Slave modes; applicable to both transmit and receive.
1 = Acknowledge was not received
0 = Acknowledge was received
bit 14 TRSTAT: Transmit Status bit
In I2C Master mode only; applicable to Master Transmit mode.
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
bit 10 BCL: Master Bus Collision Detect bit
Cleared when the I2C module is disabled (ON = 0).
1 = A bus collision has been detected during a master operation
0 = No collision has been detected
bit 9 GCSTAT: General Call Status bit
Cleared after Stop detection.
1 = General call address was received
0 = General call address was not received
bit 8 ADD10: 10-bit Address Status bit
Cleared after Stop detection.
1 = 10-bit address was matched
0 = 10-bit address was not matched
bit 7 IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register collided because the I2C module is busy.
Must be cleared in software.
0 = No collision

PIC32MX3XX/4XX
REGISTER 18-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED)
bit 6 I2COV: I2C Receive Overflow Status bit
1 = A byte is received while the I2CxRCV register is still holding the previous byte.
I2COV is a “don’t care” in Transmit mode. Must be cleared in software.
0 = No overflow
bit 5 D/A: Data/Address bit
Valid only for Slave mode operation.
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
Updated when Start, Reset or Stop detected; cleared when the I2C module is disabled (ON = 0).
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit
Updated when Start, Reset or Stop detected; cleared when the I2C module is disabled (ON = 0).
1 = Indicates that a start (or restart) bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit
Valid only for Slave mode operation.
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive complete; I2CxRCV is full
0 = Receive not complete; I2CxRCV is empty
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit in progress; I2CxTRN is full (8-bits of data)
0 = Transmit complete; I2CxTRN is empty

PIC32MX3XX/4XX
REGISTER 18-3: I2CXADD: I2C SLAVE ADDRESS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — ADD<9:8>
bit 15 bit 8

ADD<7:0>
bit 7 bit 0
Legend:

bit 9-0 ADD<9:0>: I2C Slave Device Address bits
Either Master or Slave mode.

PIC32MX3XX/4XX
REGISTER 18-4: I2CXMSK: I2C ADDRESS MASK REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — MSK<9:8>
bit 15 bit 8

MSK<7:0>
bit 7 bit 0
Legend:

bit 9-0 MSK<9:0>: I2C Address Mask bits
1 = Forces a “don’t care” in the particular bit position on the incoming address match sequence
0 = Address bit position must match the incoming I2C address match sequence
Note: MSK<9:8> and MSK<0> are only used in I2C 10-bit mode.

PIC32MX3XX/4XX
REGISTER 18-5: I2CXBRG: I2C BAUD RATE GENERATOR REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — I2CxBRG<11:8>
bit 15 bit 8

I2CxBRG<7:0>
bit 7 bit 0
Legend:

bit 11-0 I2CxBRG<11:0>: I2C Baud Rate Generator Value bits
A divider function of the Peripheral Clock.

PIC32MX3XX/4XX
REGISTER 18-6: I2CXTRN: I2C TRANSMIT DATA REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

I2CTXDATA<7:0>
bit 7 bit 0
Legend:

bit 7-0 I2CTXDATA<7:0>: I2C Transmit Data Buffer bits

PIC32MX3XX/4XX
REGISTER 18-7: I2CXRCV: I2C RECEIVE DATA REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

I2CRXDATA<7:0>
bit 7 bit 0
Legend:

bit 7-0 I2CRXDATA<7:0>: I2C Receive Data Buffer bits

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
19.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are:
RECEIVER TRANSMITTER • Full-duplex, 8-bit or 9-bit data transmission
(UART) • Even, odd or no parity options (for 8-bit data)
• One or two Stop bits
Note: This data sheet summarizes the features of • Hardware auto-baud feature
• Hardware flow control option
ence source. Refer to the “PIC32MX Family • Fully integrated Baud Rate Generator (BRG) with
Reference Manual” (DS61132) for a 16-bit prescaler
detailed description of this peripheral. • Baud rates ranging from 76 bps to 20 Mbps at 80
MHz
The Universal Asynchronous Receiver Transmitter
• 4-level-deep First-In-First-Out (FIFO) Transmit
(UART) module is one of the serial I/O modules avail-
Data Buffer
able in PIC32MX3XX/4XX family devices. The UART is
a full-duplex, asynchronous communication channel • 4-level-deep FIFO Receive Data Buffer
that communicates with peripheral devices and per- • Parity, framing and buffer overrun error detection
sonal computers through protocols such as RS-232, • Support for interrupt only on address detect (9th
RS-485, LIN 1.2 and IrDA®. The module also supports bit = 1)
the hardware flow control option, with UxCTS and • Separate transmit and receive interrupts
UxRTS pins, and also includes the IrDA encoder and
• Loopback mode for diagnostic support
decoder.
• LIN 1.2 protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 19-1 shows a simplified block diagram of the
UART.
FIGURE 19-1: UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA® BCLKx
UxRTS
Hardware Flow Control
UxCTS
UARTx Receiver UxRX
UARTx Transmitter UxTX

PIC32MX3XX/4XX
19.1 UART Registers
TABLE 19-1: UART1 SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_6000 U1MODE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL IREN RTSMD — UEN<1:0>
7:0 WAKE LPBACK ABAUD RXINV BRGH PDSEL<2:0> STSEL
BF80_6004 U1MODECLR 31:0 Write clears selected bits in U1MODE, read yields undefined value
BF80_6008 U1MODESET 31:0 Write sets selected bits in U1MODE, read yields undefined value
BF80_600C U1MODEINV 31:0 Write inverts selected bits in U1MODE, read yields undefined value
BF80_6010 U1STA 31:24 — — — — — — — ADM_EN
23:16 ADDR<7:0>
15:8 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
7:0 URXISEL<1:0> ADDEN RIDLE PERR FERR OERR RXDA
BF80_6014 U1STACLR 31:0 Write clears selected bits in U1STA, read yields undefined value
BF80_6018 U1STASET 31:0 Write sets selected bits in U1STA, read yields undefined value
BF80_601C U1STAINV 31:0 Write inverts selected bits in U1STA, read yields undefined value
BF80_6020 U1TXREG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — TX8
7:0 Transmit Register
BF80_6030 U1RXREG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — RX8
7:0 Receive Register
BF80_6040 U1BRG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 BRG<15:8>
7:0 BRG<7:0>
BF80_6044 U1BRGCLR 31:0 Write clears selected bits in U1BRG, read yields undefined value
BF80_6048 U1BRGSET 31:0 Write sets selected bits in U1BRG, read yields undefined value
BF80_604C U1BRGINV 31:0 Write inverts selected bits in U1BRG, read yields undefined value
TABLE 19-2: UART1 INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1060 IEC0 31:24 — — — U1TXIE U1RXIE U1EIE — —
BF88_1030 IFS0 31:24 — — — U1TXIF U1RXIF U1EIF — —
BF88_10F0 IPC6 7:0 — — — U1IP[2:0] U1IS[1:0]
Note 1: This summary table contains partial register definitions that only pertain to the UART peripheral. Refer to the PIC32MX Family Reference Man-
ual for a detailed description of these registers.

PIC32MX3XX/4XX
TABLE 19-3: UART2 SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_6200 U2MODE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL IREN RTSMD — UEN<1:0>
7:0 WAKE LPBACK ABAUD RXINV BRGH PDSEL<2:0> STSEL
BF80_6204 U2MODECLR 31:0 Write clears selected bits in U2MODE, read yields undefined value
BF80_6208 U2MODESET 31:0 Write sets selected bits in U2MODE, read yields undefined value
BF80_620C U2MODEINV 31:0 Write inverts selected bits in U2MODE, read yields undefined value
BF80_6210 U2STA 31:24 — — — — — — — ADM_EN
23:16 ADDR<7:0>
15:8 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
7:0 URXISEL<1:0> ADDEN RIDLE PERR FERR OERR RXDA
BF80_6214 U2STACLR 31:0 Write clears selected bits in U2STA, read yields undefined value
BF80_6218 U2STASET 31:0 Write sets selected bits in U2STA, read yields undefined value
BF80_621C U2STAINV 31:0 Write inverts selected bits in U2STA, read yields undefined value
BF80_6220 U2TXREG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — TX8
7:0 Transmit Register
BF80_6230 U2RXREG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — — RX8
7:0 Receive Register
BF80_6240 U2BRG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 BRG<15:8>
7:0 BRG<7:0>
BF80_6244 U2BRGCLR 31:0 Write clears selected bits in U2BRG, read yields undefined value
BF80_6248 U2BRGSET 31:0 Write sets selected bits in U2BRG, read yields undefined value
BF80_624C U2BRGINV 31:0 Write inverts selected bits in U2BRG, read yields undefined value
TABLE 19-4: UART2 INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1070 IEC1 15:8 — — — — — U2TXIE U2RXIE U2EIE
BF88_1040 IFS1 15:8 — — — — — U2TXIF U2RXIF U2EIF
BF88_1110 IPC8 7:0 — — — U2IP<2:0> U2IS<1:0>

PIC32MX3XX/4XX
REGISTER 19-1: UxMODE: UARTx MODE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

ON FRZ SIDL IREN RTSMD — UEN<1:0>
bit 15 bit 8

WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL
bit 7 bit 0
Legend:

bit 15 ON: UARTx Enable bit
1 = UARTx is enabled; UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN
control bits
0 = UARTx is disabled, all UARTx pins are controlled by corresponding PORT TRIS and LAT bits;
UARTx power consumption is minimal
Note: . FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode.
1 = Discontinue operation when device enters in Idle mode
bit 12 IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in simplex mode
0 = UxRTS pin is in flow control mode
bit 10 Unimplemented: Read as ‘0
bit 9-8 UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX, and UxBCLK pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS, and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
port latches
bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep mode bit
1 = Wake-up enabled
0 = Wake-up disabled

PIC32MX3XX/4XX
REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of SYNCH character
(0x55); cleared by hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX idle state is ‘0’
0 = UxRX idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = High speed mode – 4x baud clock enabled
0 = Standard speed mode – 16x baud clock enabled
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit

PIC32MX3XX/4XX
REGISTER 19-2: UxSTA: UARTx STATUS REGISTER
— — — — — — — ADM_EN
bit 31 bit 24

ADDR<7:0>
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1

UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL<1:0> ADDEN RIDLE PERR FERR OERR RXDA
bit 7 bit 0
Legend:

bit 24 ADM_EN: Automatic Address Detect Mode Enable bit
1 = Automatic Address Detect mode is enabled
0 = Automatic Address Detect mode is disabled
bit 23-16 ADDR<7:0>: Automatic Address Mask bits
When ADM_EN bit is ‘1’, this value defines the bits that are don’t care when comparing incoming
address reception
bit 15-14 UTXISEL<1:0>: Tx Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated when the Transmit buffer becomes empty
01 = Interrupt is generated when all characters are transmitted
00 = Interrupt is generated when the Transmit buffer contains at least one empty space
bit 13 UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMOD<12>) is ‘0’)
1 = UxTX idle state is ‘0’
0 = UxTX idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMOD<12>) is ‘1’)
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12 URXEN: Receiver Enable bit
1 = UARTx receiver is enabled, UxRX pin controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled, the UxRX pin is ignored by the UARTx module. UxRX pin controlled
by PORT
bit 11 UTXBRK: Transmit Break bit
1 = Send BREAK on next transmission – Start bit followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = BREAK transmission is disabled or completed

PIC32MX3XX/4XX
REGISTER 19-2: UxSTA: UARTx STATUS REGISTER (CONTINUED)
bit 10 UTXEN: Transmit Enable bit
1 = UARTx transmitter enabled, UxTX pin controlled by UARTx (if ON = 1)
0 = UARTx transmitter disabled, any pending transmission is aborted and buffer is reset. UxTX pin
controlled by PORT.
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit
11 = Interrupt flag bit is set when Receive Buffer is full (i.e., has 4 data characters)
10 = Interrupt flag bit is set when Receive Buffer is 3/4 full (i.e., has 3 data characters)
0x = Interrupt flag bit is set when a character is received
bit 5 ADDEN: Address Character Detect (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this control bit has no effect.
0 = Address Detect mode disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing Error has been detected for the current character
0 = Framing Error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed (clearing a previously set OERR bit will reset the receiver buffer
and Receive Shift Register (RSR) to an empty state)
bit 0 RXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty

PIC32MX3XX/4XX
REGISTER 19-3: UxRXREG: UART RECEIVE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
r-x r-x r-x r-x r-x r-x r-x R-0

— — — — — — — RX8
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RX<7:0>
bit 7 bit 0
Legend:

bit 8 RX8: Data bit 8 of the Received Character (in 9-bit mode)
bit 7-0 RX<7:0>: Data bits 7-0 of the Received Character

PIC32MX3XX/4XX
REGISTER 19-4: UxTXREG: UARTx TRANSMIT REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
r-x r-x r-x r-x r-x r-x r-x W-0

— — — — — — — TX8
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

TX<7:0>
bit 7 bit 0
Legend:

bit 8 TX8: Data bit 8 of the Character to be Transmitted (in 9-bit mode)
bit 7-0 TX<7:0>: Data bits 7-0 of the Character to be Transmitted

PIC32MX3XX/4XX
19.2 UART Baud Rate Generator (BRG) Equation 19-2 shows the formula for computation of
the baud rate with BRGH = 1.
The UART module includes a dedicated 16-bit Baud
Rate Generator. The BRGx register controls the period
EQUATION 19-2: UART BAUD RATE WITH
of a free-running 16-bit timer. Equation 19-1 shows the
BRGH = 1(1)
formula for computation of the baud rate with
BRGH = 0.
FPB
Baud Rate =
EQUATION 19-1: UART BAUD RATE WITH 4 • (UxBRG + 1)
BRGH = 0(1)
FPB
FPB UxBRG = –1
Baud Rate = 4 • Baud Rate
16 • (UxBRG + 1)
Note 1: FPB denotes the instruction cycle clock
FPB frequency.
UxBRG = –1
16 • Baud Rate
The maximum possible baud rate with BRGH = 1 is
Note 1: FPB denotes the peripheral bus clock FPB/4 for UxBRG = 0, and the minimum possible baud
frequency. rate is FPB/(4 * 65536).
Writing a new value to the UxBRG register causes the
Example 19-1 shows the calculation of the baud rate baud rate counter to be cleared. This ensures that the
error for the following conditions: BRG does not wait for a timer overflow before it
generates the new baud rate.
• FPB = 4 MHz
• Desired Baud Rate = 9600
The maximum possible baud rate with BRGH = 0 is
FPB/16.
The minimum possible baud rate is FPB/(16 * 65536).
EXAMPLE 19-1: BAUD RATE ERROR CALCULATION (BRGH = 0)

Desired Baud Rate = Fpb/(16 (UxBRG + 1))
Solving for UxBRG value:
UxBRG = ( (Fpb/Desired Baud Rate)/16) – 1
UxBRG = ((4000000/9600)/16) – 1
UxBRG = [25.042] = 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%

PIC32MX3XX/4XX
19.3 Transmitting in 8-bit Data Mode
1. Set up the UART:
a) Write appropriate values for data, parity and
Stop bits.
b) Write appropriate baud rate value to the
UxBRG register.
c) Set up transmit and receive interrupt enable
and priority bits.
2. Enable the UART.
3. Set the UTXEN bit (causes a transmit interrupt).
4. Write data byte to UxTXREG word. The value
will be immediately transferred to the Transmit
Shift Register (TSR), and the serial bit stream
will start shifting out with next rising edge of the
baud clock.
5. Alternately, the data byte may be transferred
while UTXEN = 0, and then the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
6. A transmit interrupt will be generated as per
interrupt control bit, UTXISEL<1:0>.
EXAMPLE 19-2: EXAMPLE 8-BIT DATA MODE

/* The following code example demonstrates configuring
UART1 for 8-bit Data Transmit mode.
*/
U1BRG = #BaudRate; // Set Uart baud rate.

U1MODESET= 0x8000; // Enable Uart for 8-bit Data, no Parity, and 1 Stop bit
U1STASET= 0x1400; // Enable Transmitter and Receiver
19.4 Transmitting in 9-bit Data Mode

1. Set up the UART (as described in Section 19.3).
2. Enable the UART.
3. Set the UTXEN bit (causes a transmit interrupt).
4. Write UxTXREG as a 16-bit value only.
5. A write to UxTXREG triggers the transfer of the
9-bit data to the TSR. Serial bit stream will start
shifting out with the first rising edge of the baud
clock.
6. A transmit interrupt will be generated as per the
setting of control bit, UTXISEL<1:0>.
EXAMPLE 19-3: EXAMPLE 9-BIT DATA MODE

/* The following code example demonstrates configuring
UART1 for 9-bit Data Transmit mode.
*/

U1STASET= 0x1211420; // Enable Address Detect, Set Address = 0x21, Enable Transmitter and
Receiver

PIC32MX3XX/4XX
19.5 Auto-Baud Support 19.8 Operation of UxCTS and UxRTS
The UART will begin an automatic baud rate measure-
Control Pins
ment sequence whenever a Start bit is received when UARTx Clear to Send (UxCTS) and Request to Send
the Auto-Baud Rate Detect is enabled (ABAUD = 1). (UxRTS) are the two hardware controlled pins that are
This feature is active only while the auto-wake-up is associated with the UART module. These two pins
disabled (WAKE = 0). In addition, LPBACK must equal allow the UART to operate in Simplex and Flow Control
‘0’ for the auto-baud operation. Following the Start bit, mode. They are implemented to control the transmis-
the auto-baud expects to receive an ASCII ‘U’ (0x55) sion and reception between the Data Terminal
in order to calculate the proper bit rate. On the 5th Equipment (DTE). The UEN<1:0> bits in the UxMODE
UxRX pin rising edge, an accumulated BRG counter register configure these pins.
value totaling the proper BRG period is transferred to
the UxBRG register. The ABAUD bit is automatically 19.9 Infrared Support
cleared.
The UART module provides two types of infrared UART
19.6 Break and Sync Transmit support:
Sequence • IrDA clock output to support external IrDA
encoder and decoder device (legacy module
The following sequence is performed to send a mes- support)
sage frame header that is composed of a Break char-
• Full implementation of the IrDA encoder and
acter, followed by an auto-baud Sync byte. This
decoder
sequence is typical of a LIN bus master:
1. Configure the UART for the desired mode. 19.10 External IrDA Support – IrDA
2. Set UTXEN and UTXBRK to set up the Break Clock Output
character.
3. Load the UxTXREG with a dummy character to To support external IrDA encoder and decoder devices,
initiate transmission (value is ignored). the BCLKx pin (same as the UxRTS pin) can be
4. Write ‘0x55’ to UxTXREG to load the Sync configured to generate the 16x baud clock. With
character into the transmit FIFO. UEN<1:0> = 11, the BCLKx pin will output the 16x
baud clock (if the UART module is enabled). It can be
After the Break has been sent, the UTXBRK bit is reset used to support the IrDA codec chip.
by hardware. The Sync character now transmits.
19.11 Built-In IrDA Encoder and Decoder
19.7 Receiving in 8-bit or 9-bit Data
Mode The UART has full implementation of the IrDA encoder
and decoder as part of the UART module. The built-in
1. Set up the UART (as described in Section 19.3). IrDA encoder and decoder functionality is enabled
2. Enable the UART. using the IREN bit (UxMODE<12>). When enabled
3. A receive interrupt will be generated when one (IREN = 1), the receive pin (UxRX) acts as the input
or more data characters have been received as from the infrared receiver. The transmit pin (UxTX) acts
per interrupt control bit, URXISEL<1:0>. as the output to the infrared transmitter.
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
5. Read UxRXREG.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.

PIC32MX3XX/4XX
19.12 UART Interrupts A UART device is enabled as a source of interrupts via
the respective UART interrupt enable bits:
The UART device has the ability to generate interrupts,
reflecting the events that occur during data communi- • U1RXIE (IEC0<27>) and U2RXIE (IEC1<9>)
cation. The following types of interrupts can be • U1TXIE (IEC0<28>) and U2TXIE (IEC1<10>)
generated: • U1EIE (IEC0<26>) and U2EIE (IEC1<8>)
• Receiver-data-available interrupts, signalled by The interrupt priority level bits and interrupt subpriority
U1RXIF (IFS0<27>), U2RXIF (IFS1<9>). This level bits must be also be configured:
event occurs when there is new data assembled • U1IP (IPC6<4:2>), U1IS (IPC6<1:0>)
in the UxRXBUF receive buffer.
• U2IP (IPC8<4:2>), U2IS (IPC8<1:0>).
• Transmitter-buffer-empty interrupts, signalled by
U1TXIF (IFS0<28>), U2TXIF (IFS1<10>). This In addition to enabling the UART interrupts, an Interrupt
event occurs when there is space available in the Service Routine (ISR) is required. Below is a partial
UxTXBUF transmit buffer and new data can be code example of an ISR.
written.
• Receiver-buffer-overflow interrupt, signalled by
U1EIF (IFS0<26>), U2EIF (IFS1<8>). This event
occurs when there is an overflow condition for the
UxRXBUF receive buffer, i.e., new receive data
assembled but the previous one not read.
EXAMPLE 19-4: UART INITIALIZATION WITH INTERRUPTS ENABLE

/*
The following code example illustrates a UART1 interrupt configuration.
When the UART1 interrupt is generated, the cpu will jump to the vector assigned to UART1
interrupt.
*/
IEC0CLR=0x1c000000; // disable all UART1 interrupts

IFS0CLR=0x1c000000; // clear any existing event
IPC6CLR=0x0000001f; // clear the priority
IPC6SET=0x000d; // Set IPL=3, subpriority 1
IEC0SET=0x1c000000; // Enable Rx, Tx and Error interrupts

U1STASET= 0x1400; // Enable Transmitter and Receiver
EXAMPLE 19-5: UART1 ISR

/*
The following code example demonstrates a simple interrupt service routine for UART1
operations and must clear the UART1 interrupt flags before exiting.
*/
void__ISR(_UART_1_VECTOR, ipl4)Uart1_IntHandler(void)
{
IFS0CLR = 0x1c000000; // Be sure to clear the UART1 interrupt flags

data = U1RXREG; // read data from the UART hardware buffer
}

PIC32MX3XX/4XX
The UART module shares pins with port input/output
control and, in some cases, with other modules. To
configure a pin for use by the UART, any modules shar-
ing the pin must be disabled. After configuring the
UART, the corresponding I/O pins must be configured
using the TRIS bit to be an input or output as is required
by the UART.
TABLE 19-5: PINS ASSOCIATED WITH A UART

Module Required TRIS Pin
Controlling
Pin Name bit Description
Control(2) Bit Field
Setting Type(1)
U1TX ON UTXEN(3), Output D, O UART1 Transmit pin

UEN(2)
U2RX ON URXEN(3), Input D, I UART1 Receive pin
UEN(2)
U1CTS ON UEN(2) Input D, I UART1 Clear to Send (CTS)
Duplex mode
U1RTS ON RTSMD(2), Output D, O UART1 Ready to Send (RTS)
Duplex mode
UEN(2)
BCLK1 ON IREN(2) Output D, O UART1 IRDA baud clock output
U2TX ON UTXEN(3), Output D, O UART2 Transmit pin
UEN(2)
U2RX ON URXEN(3), Input D, I UART2 Receive pin
UEN(2)
U2CTS ON UEN(2) Input D, I UART2 Clear to Send (CTS)
Duplex mode
U2RTS ON RTSMD(2), Output D, O UART2 Ready to Send (RTS)
Duplex mode
UEN(2)
BCLK2 ON IREN(2) Output D, O UART2 IRDA baud clock output
Legend:
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output A = Analog D = Digital
Note 1: All pins are subject to the Device Pin Priority Control.
2: Bits are contained in the UxMODE register.
3: Bits are contained in the UxSTA register.

PIC32MX3XX/4XX
20.0 PARALLEL MASTER PORT • Address auto-increment/auto-decrement
• Programmable address/data multiplexing
Note: This data sheet summarizes the features of • Programmable polarity on control signals
• Parallel Slave Port support
ence source. Refer to the “PIC32MX Family - Legacy addressable
Reference Manual” (DS61132) for a - Address support
detailed description of this peripheral. - 4-byte deep auto-incrementing buffer
The Parallel Master Port (PMP) is a parallel 8-bit/16-bit • Programmable Wait states
input/output module specifically designed to • Operate during CPU Sleep and Idle modes
communicate with a wide variety of parallel devices, • Fast bit manipulation using CLR, SET and INV
such as communications peripherals, LCDs, external registers
memory devices, and microcontrollers. Because the • Freeze option for in-circuit debugging
interface to parallel peripherals varies significantly, the
PMP module is highly configurable. Note: On 64-pin devices, data pins PMD<15:8>
Key features of the PMP module include: are not available.
• 8-bit,16-bit interface
• Up to 16 programmable address lines
• Up to two Chip Select lines
• Programmable strobe options
- Individual read and write strobes, or
- Read/write strobe with enable strobe
FIGURE 20-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
Control Lines
PIC32MX3XX/4XX PMA0
PMALL
Parallel
Master Port
PMA1
PMALH
Up to 16-bit Address FLASH
PMA<13:2> EEPROM
SRAM
PMA14
PMCS1
PMA15
PMCS2
PMRD
PMRD/PMWR
FIFO
PMWR Microcontroller LCD
PMENB buffer
PMD<7:0>
PMD<15:8>(1)
16/8-bit Data (with or without multiplexed addressing)
Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes

PIC32MX3XX/4XX
20.1 PMP Registers
TABLE 20-1: PMP SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_7000 PMCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON FRZ SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN
7:0 CSF<1:0> ALP CS2P CS1P — WRSP RDSP
BF80_7004 PMCONCLR 31:0 Write clears selected bits in PMCON, read yields undefined value
BF80_7008 PMCONSET 31:0 Write sets selected bits in PMCON, read yields undefined value
BF80_700C PMCONINV 31:0 Write inverts selected bits in PMCON, read yields undefined value
BF80_7010 PMMODE 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>
7:0 WAITB<1:0> WAITM<3:0> WAITE<1:0>
BF80_7014 PMMODECLR 31:0 Write clears selected bits in PMMODE, read yields undefined value
BF80_7018 PMMODESET 31:0 Write sets selected bits in PMMODE, read yields undefined value
BF80_701C PMMODEINV 31:0 Write inverts selected bits in PMMODE, read yields undefined value
BF80_7020 PMADDR 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 CS2EN/A15 CS1EN/A14 ADDR<13:8>
7:0 ADDR<7:0>
BF80_7024 PMADDRCLR 31:0 Write clears selected bits in PRx, read yields undefined value
BF80_7028 PMADDRSET 31:0 Write sets selected bits in PRx, read yields undefined value
BF80_702C PMADDRINV 31:0 Write inverts selected bits in PRx, read yields undefined value
BF80_7030 PMDOUT 31:24 DATAOUT<31:24>
23:16 DATAOUT<23:16>
15:8 DATAOUT<15:8>
7:0 DATAOUT<7:0>
BF80_7034 PMDOUTCLR 31:0 Write clears selected bits in PMDOUT, read yields undefined value
BF80_7038 PMDOUTSET 31:0 Write sets selected bits in PMDOUT, read yields undefined value
BF80_703C PMDOUTINV 31:0 Write inverts selected bits in PMDOUT, read yields undefined value
BF80_7040 PMDIN 31:24 DATAIN<31:24>
23:16 DATAIN<23:16>
15:8 DATAIN<15:8>
7:0 DATAIN<7:0>
BF80_7044 PMDINCLR 31:0 Write clears selected bits in PMDIN, read yields undefined value
BF80_7048 PMDINSET 31:0 Write sets selected bits in PMDIN, read yields undefined value
BF80_704C PMDININV 31:0 Write inverts selected bits in PMDIN, read yields undefined value
BF80_7050 PMAEN 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 PTEN<15:8>
7:0 PTEN<7:0>
BF80_7054 PMAENCLR 31:0 Write clears selected bits in PMAEN, read yields undefined value
BF80_7058 PMAENSET 31:0 Write sets selected bits in PMAEN, read yields undefined value
BF80_705C PMAENINV 31:0 Write inverts selected bits in PMAEN, read yields undefined value
BF80_7060 PMSTAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 IBF IBOV — — IB3F IB2F IB1F IB0F
7:0 OBE OBUF — — OB3E OB2E OB1E OB0E
BF80_7064 PMSTATCLR 31:0 Write clears selected bits in PMSTAT, read yields undefined value
BF80_7068 PMSTATSET 31:0 Write sets selected bits in PMSTAT, read yields undefined value
BF80_706C PMSTATINV 31:0 Write inverts selected bits in PMSTAT, read yields undefined value

PIC32MX3XX/4XX
TABLE 20-2: PMP INTERRUPT REGISTER SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1070 IEC1 7:0 SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE I2C1MIE
BF88_1040 IFS1 7:0 SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF I2C1MIF
BF88_1100 IPC7 7:0 — — — PMPIP<2:0> PMPIS<1:0>
Note: This summary table contains partial register definitions that only pertain to the PMP peripheral. Refer to the “PIC32MX Family Reference

PIC32MX3XX/4XX
REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 R/W-0

ON FRZ SIDL ADRMUX1 ADRMUX0 PMPTTL PTWREN PTRDEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 R/W-0

CSF1(1) CSF0(1) ALP(1) CS2P(1) CS1P(1) — WRSP RDSP
bit 7 bit 0
Legend:

bit 15 ON: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 13 SIDL: Stop in Idle Mode
bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits
11 = All 16 bits of address are multiplexed on PMD<15:0> pins
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt input buffers
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
Note 1: These bits have no effect when their corresponding pins are used as address lines

PIC32MX3XX/4XX
REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 7-6 CSF<1:0>: Chip Select Function bits(1)
11 = Reserved
10 = PMCS2 and PMCS1 function as Chip Select
01 = PMCS2 functions as Chip Select, PMCS1 functions as address bit 14
00 = PMCS2 and PMCS1 function as address bits 15 and 14
bit 5 ALP: Address Latch Polarity bit(1)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4 CS2P: Chip Select 1 Polarity bit(1)
1 = Active-high (PMCS2)
0 = Active-low (PMCS2)
bit 3 CS1P: Chip Select 0 Polarity bit(1)
1 = Active-high (PMCS1/PMCS)
0 = Active-low (PMCS1/PMCS)
bit 1 WRSP: Write Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):
1 = Write Strobe active-high (PMWR)
0 = Write Strobe active-low (PMWR)
For Master Mode 1 (PMMODE<9:8> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):
1 = Read strobe active-high (PMRD)
0 = Read strobe active-low (PMRD)
For Master Mode 1 (PMMODE<9:8> = 11):
1 = Read/Write strobe active-high (PMRD/PMWR)
0 = Read/Write strobe active-low (PMRD/PMWR)
Note 1: These bits have no effect when their corresponding pins are used as address lines

PIC32MX3XX/4XX
REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>
bit 15 bit 8

WAITB1<1:0>(1) WAITM<3:0> WAITE1<1:0>(1)
bit 7 bit 0
Legend:

bit 15 BUSY: Busy bit (Master modes only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Reserved – do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only)
10 = Decrement ADDR<15:0> by 1 every read/write cycle(2,5)
01 = Increment ADDR<15:0> by 1 every read/write cycle(2,5)
00 = No increment or decrement of address
bit 10 MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer(4)
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
Note 1: Whenever WAITM3:WAITM0 = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: When ADDR15 and ADDR14 are used as CS2 and CS1, or ADDR15 is used as CS2, these bits are not
subject to auto-increment/decrement.
3: In Master Mode 1 or Master Mode 2, data pins PMD<15:0> are active when MODE16 = 1; data pins
PMD<7:0> are active when MODE16 = 0.
4: On 64-pin devices, data pins PMD<15:8> are not available.
5: The PMADDR register is always incremented/decremented by 1, regardless of the transfer data width.

PIC32MX3XX/4XX
REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 9-8 MODE1:MODE0: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<15:0>)(3,4)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<15:0>)(3,4)
01 = Addressable Slave Mode, control signals (PMRD, PMWR, PMCS, PMD<7:0>, PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS, PMD<7:0>)
bit 7-6 WAITB1:WAITB0: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (DEFAULT)
bit 5-2 WAITM3:WAITM0: Data Read/Write Strobe Wait States bits
1111 = Wait of 16 TPB
...
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (DEFAULT)
bit 1-0 WAITE1:WAITE0: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
for Read operations:

11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
Note 1: Whenever WAITM3:WAITM0 = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: When ADDR15 and ADDR14 are used as CS2 and CS1, or ADDR15 is used as CS2, these bits are not
subject to auto-increment/decrement.
3: In Master Mode 1 or Master Mode 2, data pins PMD<15:0> are active when MODE16 = 1; data pins
PMD<7:0> are active when MODE16 = 0.
4: On 64-pin devices, data pins PMD<15:8> are not available.
5: The PMADDR register is always incremented/decremented by 1, regardless of the transfer data width.

PIC32MX3XX/4XX
REGISTER 20-3: PMADDR: PARALLEL PORT ADDRESS REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

CS2EN/A15 CS1EN/A14 ADDR<13:8>
bit 15 bit 8

ADDR<7:0>
bit 7 bit 0
Legend:

bit 15 CS2EN: Chip Select 2 bit
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (pin functions as PMA<15>)
bit 14 CS1EN: Chip Select 1 bit
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (pin functions as PMA<14>)
bit 13-0 ADDR13:ADDR0: Destination Address bits

PIC32MX3XX/4XX
REGISTER 20-4: PMDOUT: PARALLEL PORT DATAOUT REGISTER
DATAOUT<31:24>
bit 31 bit 24

DATAOUT<23:16>
bit 23 bit 16

DATAOUT<15:8>
bit 15 bit 8

DATAOUT<7:0>
bit 7 bit 0
Legend:
bit 15-0 DATAOUT<31:0>: Output Data Port bits for 8-bit write operations in Slave modes.

PIC32MX3XX/4XX
REGISTER 20-5: PMDIN: PARALLEL PORT DATAIN REGISTER
DATAIN<31:24>
bit 31 bit 24

DATAIN<23:16>
bit 23 bit 16

DATAIN<15:8>
bit 15 bit 8

DATAIN<7:0>
bit 7 bit 0
Legend:
bit 31-0 DATAIN<31:0>: Input and Output Data Port bits for 8-bit or 16-bit read/write operations in Master
modes; Input Data Port bits for read operations in Slave modes.

PIC32MX3XX/4XX
REGISTER 20-6: PMAEN: PARALLEL PORT PIN ENABLE REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

PTEN<15:8>
bit 15 bit 8

PTEN<7:0>
bit 7 bit 0
Legend:

bit 15-14 PTEN15:PTEN14: PMCSx Strobe Enable bits
1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-2 PTEN13:PTEN2: PMP Address Port Enable bits
1 = PMA<13:2> function as PMP address lines
0 = PMA<13:2> function as port I/O
bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads functions as port I/O
Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 are selected by bits CSF<1:0> in the PMCON
register.
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits, ADRMUX<1:0>, in the PMCON register.

PIC32MX3XX/4XX
REGISTER 20-7: PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODE ONLY)
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R-0 R/W-0 r-x r-x R-0 R-0 R-0 R-0

IBF IBOV — — IB3F IB2F IB1F IB0F
bit 15 bit 8
R-1 R/W-0 r-x r-x R-1 R-1 R-1 R-1

OBE OBUF — — OB3E OB2E OB1E OB0E
bit 7 bit 0
Legend:

bit 15 IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 11-8 IB3F:IB0F: Input Buffer n Status Full bit
1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte register (must be cleared in software)
0 = No underflow occurred
bit 3-0 OB3E:OB0E: Output Buffer n Status Empty bit
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted

PIC32MX3XX/4XX
20.2 Modes Of Operation 20.2.3 MASTER MODE SELECTION
The two Master modes are selected using MODE<1:0>
20.2.1 CONSIDERATIONS FOR PMP bits (PMCON<9:8>). Master Mode 1 is selected by con-
MODULE figuring MODE<1:0> bits = 11; Master Mode 2 is
• The PMP module is enabled and ready when the selected by configuring MODE<1:0> bits = 10.
ON bit (PMCON<15>) is set = 1, therefore it is
recommended to configure the desired operating 20.2.4 8, 16-BIT DATA MODES
mode prior to enabling the module. The PMP in Master mode supports data widths 8 and
• The PMP module is disabled and powered off 16 bits wide. By default, the data width is 8-bit,
when the ON bit (PMPCON<15>) = 0, thus pro- MODE16 (PMMODE<10>) bit = 0. To select 16-bit data
viding maximum power savings. width, set MODE16 = 1. When configured in 8-bit Data
• It is recommended to wait for any pending read or mode, the upper 8 bits of the data bus, PMD<15:8>, are
write operation to be completed before not controlled by the PMP module and are available as
enabling/disabling or re-configuring the module general purpose I/O pins.
Note: On 64-pin devices, data pins PMD<15:8>
20.2.2 CONSIDERATIONS FOR MASTER
are not available.
MODES
• Setting address bits A15 and A14 = 1 when 20.2.5 CHIP SELECTS
PMCS2 and PMCS1 are enabled as Chip Selects Two Chip Select lines, PMCS1 and PMCS2, are avail-
will cause both PMCS2 and PMCS1 to be active able for the Master modes. The two Chip Select lines
during a read or write operation. This may enable are multiplexed with the Most Significant bits of the
two devices simultaneously and should be address bus A14 and A15. If a pin is configured as a
avoided. Chip Select, it is not included in any PMA<15:0>
• It is always recommended to poll the PMP’s address auto-increment/decrement. It is possible to
BUSY bit prior to any read or write operation to enable both PMCS2 and PMCS1 as Chip Selects, or
ensure the prior PMP operation has completed. enable only PMCS2 as a Chip Select, allowing PMCS1
The PMP module offers two Master modes of operation to function strictly as address line A14. It is not possible
featuring 16-bit or 8-bit data (default), up to 16 bits of to enable only PMCS1. The Chip Select signals are
address, and all control signals to operate a variety of configured using the Chip Select Function bits
external parallel devices such as memory devices, CSF<1:0> (PMCON <7:6>).
peripherals, and slave microcontrollers. An example
using Master Mode 2 is shown in Figure 20-2. TABLE 20-3: CHIP SELECT CONTROL
CSF<1:0> FUNCTION
FIGURE 20-2: EXAMPLE: PMP MASTER
00 PMCS2 = A15, PMCS1 = A14
MODE 2, PARTIAL
MULTIPLEXED 01 PMCS2 = Enabled, PMCS1 = A14
INTERFACE 10 PMCS2, PMCS1 = Enabled
Refer to Section 20.2.16 “Addressing Consider-
PIC32MX3XX/4XX PMA<13:8> ations” for information regarding Chip Select address
mapping.
PMD<7:0>
20.2.6 PORT PIN CONTROL
PMD<15:8>
The PMAEN register controls the functionality of the
PMA14/PMCS1 address pins PMA<15:0>. Setting any PMAEN bit = 1
configures the corresponding PMA pin as an address
PMA15/PMCS2
line. Those bits set = 0 remain as general purpose I/O
PMA0/PMALL pins.
PMRD Refer to Section 20.5 “I/O Pin Control” regarding I/O

pin configuration.
ADRMUX<1:0> = 01 PMWR
Address Bus
Multiplexed Data
and Address Bus
Data Bus
Control Lines

PIC32MX3XX/4XX
20.2.7 READ/WRITE CONTROL If the Chip Select signals are disabled and configured
as address bits, the bits will participate in the increment
The PMP module supports two distinct read/write sig-
and decrement operations; otherwise, the PMCS2 and
naling methods. In Master Mode 1, Read and Write
PMCS1 bit values will be unaffected.
strobe are combined into a single control line,
PMRD/PMWR; a second control line, PMENB, deter-
20.2.10 WAIT STATES
mines when a read or write action is to be taken.
In Master modes, the user has control over the dura-
In Master Mode 2, Read and Write strobes (PMRD and
tion of the read, write, and address cycles by configur-
PMWR) are supplied on separate pins.
ing the module Wait states. Three portions of the
To enable the PMRD/PMWR and PMWR/PMENB pins, cycle, the beginning, middle, and end are configured
set PTRDEN bit (PMCON<8>) and PTWREN bit using the corresponding WAITB, WAITM, and WAITE
(PMCON<9>) = 1. bits in the PMMODE register.
20.2.8 CONTROL LINE POLARITY 20.2.11 ADDRESS MULTIPLEXING

All control signals (PMRD, PMWR, PMALL, PMALH, In either of the Master modes the address bus can be
PMCS2 and PMCS1) can be individually configured for multiplexed together with the data bus. There are three
either positive (active-high) or negative (active-low) Address Multiplexing modes available; Demultiplexed,
polarity. The polarity for each control line is controlled Partial Multiplexed and Full Multiplexed. The Address-
by separate bits in the PMCON register. ing Multiplex mode is configured using bits
ADRMUX<1:0> (PMCON<12:11).
TABLE 20-4: MASTER MODE PIN For detailed examples illustrating address multiplexing
POLARITY configurations, refer to the PMP chapter in the
CONTROL PMCON Active-High Active-Low “PIC32MX Family Reference Manual” (DS61132).
PIN Control Bit Select Select
TABLE 20-6: ADDRESS MULTIPLEX
PMRD RDSP 1 0
CONFIGURATIONS
PMWR WRSP 1 0
ADRMUX<1:0> Multiplex Modes
PMCS2 CS2P 1 0
PMCS1 CS1P 1 0 00 Demultiplexed
PMALL/H ALP 1 0 01 Partial (uses PMD<7:0>)
10 Full (uses PMD<7:0>)
Note that the polarity of control signals that share the
same output pin (for example, PMWR and PMENB) are 11 Full (uses PMD<15:0>)
controlled by the same bit; the configuration depends
on which Master Port mode is being used. Note: A design implementing partial or full multi-
plexed address and data bus allows the
20.2.9 AUTO-INCREMENT/DECREMENT
unused PMA address pins to be used as
While the module is operating in a Master mode, the general purpose I/O pins. However,
auto-address increment/decrement bits INCM<1:0> depending on the Multiplexing mode, read
(PMMODE<12:11>) control the behavior of the address and write operations will be extended by
value that appears on the PMA<15:0> address pins. several peripheral bus clock cycles,
The address in the PMADDR register can be made to TPBCLK.
automatically increment or decrement by 1 (regardless
of the transfer data width) after each read and write 20.2.12 DEMULTIPLEXED MODE
operation is completed, and the BUSY bit goes to ‘0’.
In Demultiplexed mode, address bits are presented on
TABLE 20-5: ADDRESS AUTO- pins PMA<15:0>. Note, PMA15 is not available if
PMCS2 is enabled and PMA14 is not available if
INCREMENT/DECREMENT
PMCS1 is enabled. Data bits are presented on pins
CONFIGURATION
PMD<15:0> in 16-bit Data mode; pins PMD<7:0> in 8-
INCM<1:0> FUNCTION bit Data mode. Demultiplexed mode is selected by
configuring bits ADRMUX<1:0> = 00.
00 No Increment, No Decrement
01 Increment every R/W Cycle
10 Decrement every R/W Cycle

PIC32MX3XX/4XX
FIGURE 20-3: DEMULTIPLEXED 20.2.14 FULL MULTIPLEXED MODE (8-BIT
ADDRESSING DATA PINS)
In 8-bit Full Multiplexed mode, the entire 16 bits of the
PIC32MX3XX/4XX PMA<13:0> address are multiplexed with the data pins on
PMD<7:0>. The PMA<0> and PMA<1> pins are used
PMD<7:0>
to present Address Latch Low enable (PMALL) and
PMD<15:8> (1) Address Latch High enable PMALH strobes,
respectively. Pins PMA<13:2> are not used as address
PMA14/PMCS1 pins and can be used as general purpose I/O pins. In
PMA15/PMCS2 the event address bits PMA15 or PMA14 are
configured as Chip Selects, the corresponding address
PMRD bits PMADDR<15> and PMADDR<14> are
automatically forced = 0. Full 8-bit Multiplexed mode is
ADRMUX<1:0> = 00 PMWR
selected by configuring bits ADRMUX<1:0>
(PMCON<12:11>) = 10.
Address Bus
Data Bus
Control Lines FIGURE 20-5: FULL MULTIPLEXED
Note 1: PMA15 is not available if PMCS2 is enabled. ADDRESSING
PMA14 is not available if PMCS1 is enabled. (8-BIT BUS)
20.2.13 PARTIAL MULTIPLEXED MODE PIC32MX3XX/4XX PMD<7:0>

(1)
In Partial Multiplexed mode, the lower eight address
PMA14/PMCS1
bits are multiplexed with data pins PMD<7:0>. The
upper eight address bits are unaffected and are PMA15/PMCS2
presented on PMA<15:8>. Note, PMA15 is not
available if PMCS2 is enabled and PMA14 is not PMA0 / PMALL
available if PMCS1 is enabled. The PMA<0> pin is
PMA1 / PMALH
used as an Address Latch, and presents the Address
Latch Low enable strobe (PMALL). PMA<7:1> are PMRD
available as general purpose I/O pins. Partial
Multiplexed mode is selected by configuring bits ADRMUX<1:0> = 10 PMWR
ADRMUX<1:0> = 00.
Fully Multiplexed Address/Data Bus
FIGURE 20-4: PARTIAL MULTIPLEXED Control Lines
ADDRESSING Note 1: PMA15 is not available if PMCS2 is enabled.
PMA14 is not available if PMCS1 is enabled.
PIC32MX3XX/4XX PMA<13:8>
20.2.15 FULL MULTIPLEXED MODE (16-BIT
PMD<7:0>
DATA PINS)
PMD<15:8> (1)
In Full 16-bit Multiplexed mode, the entire 16 bits of the
PMA14/PMCS1 address are multiplexed with the data pins on
PMD<15:0>. Pins PMA<0> and PMA<1> provide
PMA15/PMCS2 Address Latch Low enable PMALL and Address Latch
PMA0 / PMALL
High enable PMALH strobes, respectively, and at the
same time. Pins PMA<13:2> are not used as address
PMRD pins and can be used as general purpose I/O pins. In
the event address bits PMA15 or PMA14 are config-
PMWR
ADRMUX<1:0> = 01 ured as Chip Selects, the corresponding address bits
PMADDR<15> and PMADDR<14> are automatically
Address Bus forced = 0. Full 16-bit Multiplexed mode is selected by
Multiplexed Address/Data Bus configuring bits:
Data Bus ADRMUX<1:0>(PMCON<12:11>) = 11
Control Lines
Note 1: PMA15 is not available if PMCS2 is enabled.
PMA14 is not available if PMCS1 is enabled.

PIC32MX3XX/4XX
FIGURE 20-6: FULL MULTIPLEXED When configured as Chip Selects, a 1 must be written
ADDRESSING into bit position 15 or 14 of the PMADDR register in
(16-BIT BUS) order for PMCS2 or PMCS1 to become active during a
read or write operation. Failing to write a 1 to PMCS2
or PMCS1 does not prevent address pins PMA<13:0>
PIC32MX3XX/4XX PMD<7:0> from being active as the specified address appears,
however, no Chip Select signal will be active.
PMD<15:8> (1)
PMA14/PMCS1
Note: When using Auto-Increment Address
mode, PMCS2 and PMCS1 do not partic-
PMA15/PMCS2 ipate and must be controlled by the user’s
software by writing to ‘ 1’ to
PMA0 / PMALL
PMADDR<15:14> explicitly.
PMA1 / PMALH
Disabling one or both Chip Selects PMCS2 and
PMRD
PMCS1 makes these pins available as address lines
ADRMUX<1:0> = 11 A15 and A14.
PMWR
In Full Multiplexed mode, address bits
Fully Multiplexed Address/Data Bus PMADDR<15:0> are multiplexed with the data bus and
Control Lines in the event address bits PMA15 or PMA14 are config-
Note 1: PMA15 is not available if PMCS2 is enabled.
PMA14 is not available if PMCS1 is enabled. ured as Chip Selects, the corresponding
PMADDR<15:14> address bits are automatically
forced = 0. Disabling one or both PMCS2 and PMCS1
20.2.16 ADDRESSING CONSIDERATIONS makes these bits available as address bits
PMADDR<15:14>.
PMCS2 and PMCS1 Chip Select pins share functional-
ity with address lines A15 and A14. It is possible to In any of the Master mode multiplexing schemes, dis-
enable both PMCS2 and PMCS1 as Chip Selects, or abling both Chip Select pins PMCS2 and PMCS1
enable only PMCS2 as a Chip Select, allowing PMCS1 requires the user to provide Chip Select line control
to function strictly as address line A14. It is not possible through some other I/O pin under software control. See
to enable only PMCS1. Figure 20-7.
FIGURE 20-7: PMP CHIP SELECT ADDRESS MAPPING (DEMULTIPLEXED AND PARTIAL
MULTIPLEXED MODES)
PMCS2, CS1 PMCS2, A14 A15, A14, IO-pin

0xFFFF
Both Devices
Selected 1 1 1 1 1 1 1
(INVALID) Device Device

0xC000 Selected Selected
PMCS2 = 1 IOpin = 1
Device 2
Selected 1 0 1 0 1
1 0
PMCS2 = 1
0x8000
Device 1
Selected 0 1 0 1 0 1 1
PMCS1 = 1
0x4000 No Device
Selected
No Device 0 0 0 0 0 0 1
Selected
0x0000
2 - Chip Selects 1 - Chip Select IO-pin = Software controlled CS
2 - 16K Address Ranges 1 - 32K Address Range 1 - 64K Address Range

PIC32MX3XX/4XX
20.3 Master Mode Timing The actual data rate of the PMP (the rate which user’s
code can perform a sequence of read or write opera-
A PMP Master mode cycle time is defined as the num- tions) will be highly dependent on several factors:
ber of PBCLK cycles required by the PMP to perform a
read or write operation and is dependent on PBCLK • a user’s application code content
clock speed, PMP address/data multiplexing modes • code optimization level
and the number of PMP wait states, if any. Refer to the • internal bus activity
PIC32MX Family Reference Manual, PMP Chapter, for • other factors relating to the instruction execution
various timing diagrams. For specific setup and hold speed.
timing characteristics, refer to Section 30.2 “AC Char-
acteristics and Timing Parameters” in this data Note: During any Master mode read or write
sheet. operation, the busy flag will always de-
assert 1 peripheral bus clock cycle
A PMP master mode read or write cycle is initiated by
(TPBCLK), before the end of the operation,
accessing (reading or writing) the PMDIN register. Sec-
including Wait states. The user’s applica-
tion TABLE 20-7: “PMP Read/Write Cycle Times”
tion must check the status of the busy flag
below provides a summary of read and write PMP cycle
to ensure it is = 0 before initiating the next
times for each multiplex configuration.
PMP operation.
TABLE 20-7: PMP READ/WRITE CYCLE TIMES

PMP Cycle Time
ADRMUX bit (PBCLK cycles)
Address/Data Multiplex Configuration
settings
Read Write
Demultiplexed 00 2 3
Partial Multiplex 01 5 6
Full Multiplexed (8-bit data) 10 8 9
Full Multiplexed (16-bit data) 11 5 6
Note: Wait states are not enabled
20.3.1 MASTER PORT CONFIGURATION • Select PMWR “active-low” pin polarity -

WRSP (PMCON<1>) = 0.
The Master mode configuration is determined primarily
by the interface requirements to the external device. • Select PMCS2, PMCS1 “active-low” pin polarity -
Address multiplexing, control signal polarity, data width CS2P (PMCON<4>) = 0 and CS1P
and Wait states typically dictate the specific configura- (PMCON<3>) = 0.
tion of the PMP master port. • Select 1 wait cycle for data setup -
WAITB<1:0>(PMMODE<7:6>) = 00.
The following illustrates example settings for Master
Mode 2 operation: • Select 2 wait cycles to extend PMRD/PMWR -
WAITM<3:0>(PMMODE<5:2>) = 01.
• Select Master Mode 2 -
• Select 1 wait cycle for data hold -
MODE<1:0> (PMMODE<9:8>) = 10.
WAITB<1:0>(PMMODE<1:0>) = 00.
• Select 16-bit Data mode -
• Enable upper 8 PMA<15:8> address pins -
MODE16 (PMMODE<10>) = 1.
PMAEN<15:8> = 1 (lower 8 can be used as
• Select partial multiplexed addressing - general purpose I/O).
ADRMUX<1:0> (PMCON<12:11>) = 01.
• Select auto-address increment -
INCM<1:0> (PMMODE<12:11>) = 01.
• Enable Interrupt Request mode -
IRQM<1:0> (PMMODE<14:13>) = 01.
• Enable PMRD strobe -
PTRDEN (PMCON<8>) = 1.
• Enable PMWR strobe -
PTWREN (PMCON<9>) = 1.
• Enable PMCS2 and PMCS1 Chip Selects -
CSF (PMCON<7:6>) = 10.
• Select PMRD “active-low” pin polarity -
RDSP (PMCON<0>) = 0.

PIC32MX3XX/4XX
20.3.2 MASTER PORT INITIALIZATION 4. If interrupts are used:
The Master mode initialization properly prepares the a) Clear interrupt flag bit PMPIF
PMP port for communicating with an external device. (IFS1<2>) = 0.
b) Configure the PMP interrupt priority bits
PMPIP<2:0> (IPC7<4:2>) and interrupt sub
configure the PMP port:
priority bits PMPIS (IPC7<1:0>.
1. If interrupts are used, disable the PMP interrupt c) Enable PMP interrupt by setting interrupt
by clearing the interrupt enable bit PMPIE enable bit PMPIE = 1.
(IEC1<2>) = 0.
5. Enable the PMP master port by setting control
2. Stop and reset the PMP module by clearing the bit ON = 1.
control bit ON (PMCON<15>) = 0.
3. Configure the desired settings in the PMCON,
PMMODE and PMAEN control registers.
EXAMPLE 20-1: PARALLEL MASTER PORT INITIALIZATION
IEC1CLR = 0x0004; //Disable PMP int
PMCON = 0x0BC0; //Stop and Configure
PMMODE = 0x2A04; //Config PMMODE reg
PMAEN = 0xFF00; //Config PMAEN reg
IPC7SET = 0x001C; //Priority level=7
IPC7SET = 0x0003; //subpriority=3

//Same as..
//IPC7SET=0x001F
IFS1CLR = 0x0004; //Clear PMP flag
IEC1SET = 0x0004; //Enable PMP int
PMCONSET = 0x8000; //Enable PMP
PMADDR = 0x4000; //Set external address
PMDIN = 0x1234; //Write to device

...
20.3.3 READ OPERATION Note: The read data obtained from the PMDIN
To perform a read on the parallel bus, the user reads register is actually the read value from the
the PMDIN register. The effect of reading the PMDIN previous read operation. Hence, the first
register retrieves the current value and causes the user read will be a dummy read to initiate
PMP to activate the Chip Select lines and the address the first bus read and fill the read register.
bus. The read line PMRD is strobed and the new data Also, the requested read value will not be
is latched into the PMDIN register, making it available ready until after the BUSY bit is observed
for the next time the PMDIN register is read. low. Therefore, in a back-to-back read
operation, the data read from the register
will be the same for both reads. The next
read of the register will yield the new
value.
Refer to the PIC32MX3XX/4XX Reference Manual for

a detailed description of the read operation and illus-
trated example.

PIC32MX3XX/4XX
20.3.4 WRITE OPERATION If a large number of wait-states are used, or if the
PBCLK clock is operating slower than the SYSCLK
To perform a write onto the parallel port, the user
clock, it is possible for the PMP module to be in the pro-
writes to the PMDIN register (same register used for a
cess of completing a read or write operation when the
read operation). This causes the module to first acti-
next CPU instruction is attempting to read or write the
vate the Chip Select lines and the address bus. The
PMP module. For this reason, it is highly recommended
write data from the PMDIN register is placed onto the
that the PMP’s BUSY bit be checked prior to any read
PMD data bus and the write line PMPWR is strobed.
or write operation and any user operation that modifies
20.3.5 PARALLEL MASTER PORT STATUS the PMADDR address register. See the following code
example.
In addition to the PMP interrupt, a BUSY bit is
provided to indicate the status of the module. This bit Note: During any Master mode read or write
is only used in Master modes. operation, the busy flag will always de-
While any read or write operation is in progress, the assert 1 peripheral bus clock cycle
BUSY bit is set for all but the very last peripheral bus (TPBCLK), before the end of the operation,
cycle of the operation. While the bit is set, any request including Wait states.
by the user to initiate a new operation will be ignored
(i.e., writing or reading the PMDIN register will not initi-
ate either a read nor a write).
EXAMPLE 20-2: POLLING THE BUSY FLAG

/*An generic C example PMP write function
utilizing the BUSY bit.
*/
pmpWrite(unsigned int value)
{
while(PMMODE & 0x8000); // PMP busy?
PMDIN = value; // perform write
}
/*An MPLAB C32 example PMP write function

utilizing BUSY bit.
*/

{
while(PMMODEbits.BUSY); // PMP busy?
}
In most applications, the PMP’s Chip Select pin(s) pro-

vide the Chip Select interface and are under the timing
control of the PMP module. However, some applica-
tions may require the PMP Chip Select pin(s) not be
configured as a Chip Select, but as a high-order
address line, such as PMA<14> or PMA<15>. In this
situation, the application’s Chip Select function must be
provided by an available I/O port pin under software
control. In these cases, it is especially important that
the user’s software poll the BUSY bit to ensure any
read or write operation is complete before de-asserting
the software controlled Chip Select.
The following example illustrates a common technique.

PIC32MX3XX/4XX
EXAMPLE 20-3: POLLING THE BUSY FLAG AND SOFTWARE CONTROLLED CHIP SELECT
/* An generic C example PMP write function

utilizing PORTD.RD1 as an active low
Chip Select and the BUSY bit.
*/
{
PORTDCLR = 0x0002; //CS enabled
while(PMMODE & 0x8000); // PMP busy?
PMDIN = value; //perform write
while(PMMODE & 0x8000); //wait for PMP

PORTDSET = 0x0002; //CS disabled
}
/* An MPLAB C32 example PMP write function
utilizing PORTD.RD1 as an active low
Chip Select and the BUSY bit.
*/
{
PORTDCLR = 0x0002; //CS enabled
while(PMMODEbits.BUSY); // PMP busy?
while(PMMODEbits.BUSY); // wait for PMP

PORTDSET = 0x0002; //CS disabled
}

PIC32MX3XX/4XX
20.3.6 SLAVE MODE Figure 20-8: Legacy Slave Mode Interface
20.3.6.1 Considerations for Slave Mode

Master PIC32MX3XX/4XX
• Do not enable or disable the module during any Slave
read or write operation D<7:0> PMD<7:0>
• Because of the asynchronous nature of the read
and write operations, it is highly recommended CS PMCS1
that the user rely on the PSP status bits prior to RD PMRD
any read or write operation.
WR PMWR
The PMP module provides 8-bit (byte) legacy Parallel
Slave Port functionality as well as new Buffered and
Addressable Slave modes.
20.3.7 MODE SELECTION 20.3.9 LEGACY SLAVE CONFIGURATION

The three Master modes are selected using The Legacy Slave mode configuration is determined
MODE<1:0> bits (PMCON<9:8>). Legacy Slave mode automatically and dedicated to the PSP module when
is selected by configuring MODE<1:0> bits = 00; Buff- the Legacy Slave mode is selected. The user only need
ered and Addressable Slave modes are selected by to configure the polarity of the PMCS1, PMRD and
configuring MODE<1:0> = 01. Additionally, Buffered PMWR signals.
Slave mode requires bits INCM<1:0> The following example illustrates which control bits are
(PMMODE<12:11>) = 11. to be set for Legacy Slave mode configuration:
• Configure Legacy Slave mode bits -
TABLE 20-8: Slave Mode Selection MODE<1:0> (PMMODE<9:8>) = 00
PMCON PMMODE • Select PMRD “active-low” pin polarity -
Slave Mode
MODE<1:0> INCM<1:0> RDSP (PMCON<0>) = 0.
Legacy 00 x = don’t care • Select PMWR “active-low” pin polarity -
WRSP (PMCON<1>) = 0.
Buffered 00 11
• Select PMCS2, PMCS1 “active-low” pin polarity -
Addressable 01 x = don’t care
CS2P (PMCON<4>) = 0 and CS1P
All Slave modes support 8-bit data only and the associ- (PMCON<3>) = 0.
ated module control pins are automatically dedicated to
the module when any of these modes are selected. The 20.3.10 SLAVE PORT INITIALIZATION
user only need to configure the polarity of the PMCS1, The Legacy Slave mode initialization properly prepares
PMRD and PMWR signals. the PMP port for communicating with an external mas-
ter device.
TABLE 20-9: Slave Mode Pin Polarity
1. If interrupts are used, disable the PMP interrupt
Configuration
by clearing the interrupt enable bit PMPIE
CONTROL PMCON Active-High Active-Low (IEC1<2>) = 0.
PIN Control Bit Select Select 2. Stop and reset the PMP module by clearing the
PMRD RDSP 1 0 control bit ON (PMCON<15>) = 0.
PMWR WRSP 1 0 3. Configure the desired settings in the PMCON
and PMMODE control registers.
PMCS1 CS1P 1 0
4. If interrupts are used:
20.3.8 LEGACY PARALLEL SLAVE MODE a) Clear interrupt flag bit PMPIF
(IFS1<2>) = 0.
In Legacy Slave mode, an external device can asyn-
chronously read and write data using the 8-bit data b) Configure the PMP interrupt priority bits
bus PMD<7:0>, the read PMRD, write PMWR, and PMPIP<2:0> (IPC7<4:2>) and interrupt sub
chip-select PMCS1 inputs. priority bits PMPIS (IPC7<1:0>.
c) Enable PMP interrupt by setting interrupt
enable bit PMPIE = 1.
5. Enable the PMP slave port by setting control bit
ON = 1.

PIC32MX3XX/4XX
EXAMPLE 20-4: EXAMPLE CODE: LEGACY PARALLEL SLAVE PORT INITIALIZATION
IEC1CLR = 0x0004 //Disable PMP int
PMCON = 0x0000 //Stop and Configure
PMMODE = 0x0000 //Config PMMODE
IPC7SET = 0x0003; //subpriority =3

//Same as...
//IPC7SET=0x001F
20.3.11 Buffered Slave Mode When the Buffered mode is active, the module uses the
PMDIN register as write buffers and the PMDOUT reg-
Buffered Parallel Slave Port mode is functionally iden-
ister as read buffers, with respect to the master device.
tical to the Legacy Parallel Slave Port mode with one
Each register is divided into four 8-bit buffer registers,
exception: the implementation of 4-level read and write
four read buffers in PMDOUT and four write buffers in
buffers. Buffered Slave mode is enabled by setting the
PMDIN. Buffers are numbered 0 through 3, starting
PMMODE<INCM1:INCM0> bits to ‘11’.
with the lower byte <7:0> and progressing upward
through the high byte <31:24>.
FIGURE 20-9: PARALLEL MASTER/SLAVE CONNECTION BUFFERED
PIC32MX3XX/4XX Slave
Master
PMD<7:0> Write Read
D<7:0> Address Address
Pointer Pointer
CS PMCS1
PMDOUT (0) PMDIN (0)
RD PMRD
WR PMWR
20.3.12 BUFFERED SLAVE • Select PMRD “active-low” pin polarity -

CONFIGURATION RDSP (PMCON<0>) = 0.
The Buffered Slave mode configuration is determined • Select PMWR “active-low” pin polarity -
automatically and dedicated to the PMP module when WRSP (PMCON<1>) = 0.
the Buffered Slave mode is selected. The user only • Select PMCS2, PMCS1 “active-low” pin polarity -
need to configure the polarity of the PMCS1, PMRD CS2P (PMCON<4>) = 0 and CS1P
and PMWR signals. (PMCON<3>) = 0.
The following example illustrates which control bits are
to be set for Buffered Slave mode configuration:
• Configure Buffered Slave mode bits -
MODE<1:0> (PMMODE<9:8>) = 00 and
INCM<1:0> (PMMODE<12:11>) = 11.

PIC32MX3XX/4XX
20.3.13 BUFFERED SLAVE MODE 3. Configure the desired settings in the PMCON
INITIALIZATION and PMMODE control registers.
The Buffered Slave mode initialization properly 4. If interrupts are used:
prepares the PSP port for communicating with an a) Clear interrupt flag bit PMPIF
external master device. (IFS1<2>) = 0.
The following steps should be performed to properly b) Configure the PMP interrupt priority bits
configure the PSP port: PMPIP<2:0> (IPC7<4:2>) and interrupt sub
1. If interrupts are used, disable the PMP interrupt
c) Enable PSP interrupt by setting interrupt
by clearing the interrupt enable bit PMPIE
(IEC1<2>) = 0.
2. Stop and reset the PMP module by clearing the
ON = 1.
control bit ON (PMCON<15>) = 0.
EXAMPLE 20-5: BUFFERED PARALLEL SLAVE MODE INITIALIZATION

IEC1CLR = 0x0004 //Disable PMP
PMMODE = 0x1800 //Configure PMMODE

//Same as...
//IPC7SET=0x001F

PIC32MX3XX/4XX
20.3.14 ADDRESSABLE SLAVE MODE TABLE 20-10: SLAVE MODE BUFFER
In the Addressable Parallel Slave Port mode, the mod- ADDRESSES
ule is configured with two extra inputs, PMA<1:0>. This Output Register
makes the 4-byte buffer space directly addressable as Input Register
PMA<1:0> PMDOUT
fixed pairs of read and write buffers. As with Buffered PMDIN (Buffer)
(Buffer)
Legacy mode, data is output from register PMDOUT
and is input to register PMDIN. Table 20-10 shows the 00 <7:0> (0) <7:0> (0)
address resolution for the incoming address to the 01 <15:8> (1) <15:8> (1)
input and output registers. 10 <23:16> (2) <23:16> (2)
11 <31:24> (3) <31:24> (3)
FIGURE 20-10: PARALLEL MASTER/SLAVE CONNECTION ADDRESSABLE BUFFER
Master PIC32MX3XX/4XX Slave

PMA<1:0>
A<1:0>
PMD<7:0> Write Read
D<7:0> Address Address
Decode Decode

CS PMCS1 PMDOUT (1) PMDIN (1)
RD PMRD PMDOUT (2) PMDIN (2)
WR PMWR PMDOUT (3) PMDIN (3)
20.3.15 ADDRESSABLE SLAVE 20.3.16 ADDRESSABLE SLAVE PORT

CONFIGURATION INITIALIZATION
The Addressable Slave mode configuration is deter- The Addressable Slave mode initialization properly
mined automatically and dedicated to the PSP module prepares the PSP port for communicating with an
when the Addressable Slave mode is selected. The external master device.
user only need to configure the polarity of the PMCS1, The following steps should be performed to properly
PMRD and PMWR signals. configure the PSP port:
The following example illustrates which control bits are 1. If interrupts are used, disable the PMP interrupt
to be set for Addressable Slave mode configuration: by clearing the interrupt enable bit PMPIE
• Configure Addressable Slave mode bits – (IEC1<2>) = 0.
MODE<1:0> (PMMODE<9:8>) = 01 2. Stop and reset the PMP module by clearing the
• Select PMRD “active-low” pin polarity – control bit ON (PMCON<15>) = 0.
RDSP (PMCON<0>) = 0 3. Configure the desired settings in the PMCON
• Select PMWR “active-low” pin polarity – and PMMODE control registers.
WRSP (PMCON<1>) = 0 4. If interrupts are used:
• Select PMCS2, PMCS1 “active-low” pin polarity – a) Clear interrupt flag bit PMPIF
CS2P(PMCON<4>)=0andCS1P(PMCON<3>)=0 (IFS1<2>) = 0.
b) Configure the PMP interrupt priority bits
PMPIP<2:0> (IPC7<4:2>) and interrupt sub
c) Enable PSP interrupt by setting interrupt
ON = 1.

PIC32MX3XX/4XX
EXAMPLE 20-6: ADDRESSABLE PARALLEL SLAVE PORT INITIALIZATION
IEC1CLR = 0x0004 //Disable PMP int
PMMODE = 0x0100 //Config PMMODE
//Same as...
//IPC7SET=0x001F
IFS1CLR = 0x0004; //Clear PMP int flag
PMCONSET = 0x8000; //Enable PMP module
20.4 PMP Interrupts

The PMP module has the ability to generate the follow-
ing types of interrupts reflecting the events that occur
during data transfers.
Master mode:
• Interrupt on every read and write operation.
Legacy Slave mode:
• Interrupt on every read and write byte
Buffered Slave mode:
• Interrupt on read or write byte of Buffer 3
(PMDOUT<31:24>)
Addressable Slave mode:
• Interrupt on read or write byte of Buffer 3
(PMDOUT<31:24>), PMA<1:0> = 11
The PMP module is enabled as a source of interrupt
using the PMP interrupt enable bit:
• PMPIE (IEC1<2>).
The interrupt priority level and subpriority level bits
must also be configured:
- PMPIP<2:0> (IPC7<4:2>)
- PMPIS<1:0> (IPC7<1:0>)
• The PMP interrupt status flag, PMPIF (IFS1<2>)
is typically cleared by the user’s software in the
ISR.
Below is a partial code example of an ISR.

PIC32MX3XX/4XX
EXAMPLE 20-7: PMP MODULE INTERRUPT INITIALIZATION
/*
The following code example illustrates a PMP interrupt configuration.
When the PMP interrupt is generated, the CPU will branch to the vector
assigned to PMP interrupt.
*/
// Configure PMP for desired mode of operation

...
// Configure the PMP interrupts
IPC7SET = 0x0014; // Set priority level=5
// operation by assigning IPC7SET = 0x0017
IFS1CLR = 0x0002; // Clear the PMP interrupt status flag

IEC1SET = 0x0002; // Enable PMP interrupts
PMCONSET = 0x8000; // Enable PMP module
EXAMPLE 20-8: PMP ISR
/*
The following code example demonstrates a simple interrupt
service routine for PMP interrupts. The user’s code at this
vector should perform any application specific operations and must
clear the PMP interrupt status flag before exiting.
*/
void __ISR(_PMP_VECTOR, ipl5) PMP_Interrupt_ISR(void)
{
IFS1CLR = 0x00002; // Be sure to clear the PMP interrupt status

// flag before exiting the service routine.
}
Note: The PMP ISR code example shows

MPLAB® C32 C compiler-specific syntax.
Refer to your computer manual regarding
support for ISRs.

PIC32MX3XX/4XX
TABLE 20-11: REQUIRED I/O PIN RESOURCES FOR MASTER MODES
I/O Pin De- Partial Full Functional Description
Name multiplex Multiplex Multiplex
PMPCS2 / PMA15 Yes(2) Yes(2) Yes(2) PMP Chip Select 2 / Address A15
(2) (2) (2)
PMPCS1 / PMA14 Yes Yes Yes PMP Chip Select 1 / Address A14
PMA<13:2> Yes(2) Yes(3) No(1) PMP Address A13..A2
PMA1 / PMALH No(1) No (1)
Yes(4)
PMP Address A1 / Address Latch High
PMA0 / PMALL No(1) Yes(2) Yes(4) PMP Address A0 / Address Latch Low
PMRD / PMWR Yes Yes Yes PMP Read / Write Control
PMWR / PMENB Yes Yes Yes PMP Write / Enable Control
PMD<15:0> Yes(5) Yes (5)
Yes(5)
PMP Bidirectional Data Bus D15..D0
Note: 1. “No” indicates the pin is not required and is available as a general purpose I/O pin when the corresponding
PMAEN bit is cleared, = 0.
2. Depending on the application, not all PMA<15:0> or CS2, CS1 may be required.
3. When Partial Multiplex mode is selected (ADDRMUX<1:0> = 01), the lower 8 Address lines are multiplexed
with PMD<7:0>, PMA<0> becomes (PMALL) and PMA<7:1> are available as general purpose I/O pins.
4. When Full Multiplex mode is selected (ADDRMUX<1:0> = 10 or 11), all 16 Address lines are multiplexed with
PMD<15:0>, PMA<0> becomes (PMALL), PMA<1> becomes (PMALH) and PMA<13:2> are available as
general purpose I/O pins.
5. If MODE16 = 0, then only PMD<7:0> are required. PMD<15:8> are available as general purpose
I/O pins.
6. Data pins PMD<15:0> are available on 100-pin PIC32MX3XX/4XX devices and larger. For all other device
variants, only pins PMD<7:0> are available.
When enabling any of the PMP module for Slave mode

operations, the PMPCS1, PMRD, PMWR control pins,
PMD<7:0> data pins and PMA<1:0> address pins are
automatically enabled and configured. The user is how-
ever responsible for selecting the appropriate polarity
for these control lines.
TABLE 20-12: REQUIRED I/O PIN RESOURCES FOR SLAVE MODES

I/O Pin Name Legacy Buffered Addressable Functional Description
PMPCS1 / PMA14 Yes Yes Yes Chip Select
PMA1 / PMALH No(1) No(1) Yes Address A1
PMA0 / PMALL No(1) No(1) Yes Address A0
PMRD / PMWR Yes Yes Yes Read Control
PMWR / PMENB Yes Yes Yes Write Control
PMD<7:0> Yes(2) Yes(2) Yes(2) Bidirectional Data Bus D7..D0
Note: 1. “No” indicates the pin is not required and is available as a general purpose I/O pin when the corresponding
PMAEN bit is cleared, = 0.
2. Slave modes use PMD<7:0> only. Pins PMD<15:8> are available as general purpose I/O pins. Control bit
MODE16 (PMMODE<10>) is ignored.

PIC32MX3XX/4XX
20.5.1 I/O PIN CONFIGURATION
The following table provides a summary of settings
required to enable the I/O pin resources used with this
module. The PMAEN register controls the functionality
of pins PMA<15:0>. Setting any PMAEN bit = 1 config-
ures the corresponding PMA pin as an address line.
Those bits set = 0 remain as general purpose I/O pins.
TABLE 20-13: I/O PIN CONFIGURATION

Pin Control
I/O Pin Module Pin Buffer

Required(1) Bit Field TRIS Description
Name Control Type Type(2)
PMPCS2 / Yes ON CSF<1:0>, CS2, — O ST/TTL PMP Chip Select 2 /
PMA15 PTEN15 Address A15
PMPCS1 / Yes ON CSF<1:0>, — O ST/TTL PMP Chip Select 1 /
PMA14 CS1 Address A14
PTEN14
PMA<13:2> Yes ON PTEN<13:2> — O ST/TTL PMP Address A13..A2
PMA1 / Yes ON PTEN<1> — I,O ST/TTL PMP Address A1 /
PMALH Address Latch Hi
PMA0 / Yes ON PTEN<0> — I,O ST/TTL PMP Address A0 /
PMALL Address Latch Lo
PMRD / Yes ON PTRDEN — O ST/TTL PMP Read / Write Control
PMWR
PMWR / Yes ON PTWREN — O ST/TTL PMP Write / Enable Control
PMENB
PMD<15:0> Yes ON MODE16, — I,O ST/TTL PMP Bidirectional Data Bus
ADRMUX<1:0> D15..D0
Legend: TTL = TTL compatible input or output, ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output
Note: 1. Depending on the PMP mode and the user’s application, these pins may not be required. If not enabled, these
pins can be used as general purpose I/O.
2. Default buffer type is ST.

PIC32MX3XX/4XX
21.0 REAL-TIME CLOCK AND • Alarm Intervals are configurable for Half of a
Second, One Second, 10 Seconds, One Minute,
CALENDAR (RTCC)
10 Minutes, One Hour, One Day, One Week, One
Note: This data sheet summarizes the features of Month and One Year
the PIC32MX3XX/4XX family of devices. It • Alarm Repeat with Decrementing Counter
is not intended to be a comprehensive refer- • Alarm with Indefinite Repeat: Chime
ence source. Refer to the “PIC32MX Family • Year Range: 2000 to 2099
• Leap Year Correction
• BCD Format for Smaller Firmware Overhead
The PIC32MX Real-Time Clock and Calendar (RTCC) • Optimized for Long-Term Battery Operation
module is intended for applications where accurate • Fractional Second Synchronization
time must be maintained for extended periods of time
• User Calibration of the Clock Crystal Frequency
with minimal or no CPU intervention. Low-power
with Auto-Adjust
optimization provides extended battery lifetime while
keeping track of time. • Calibration Range: ±0.66 Seconds Error per
Month
Following are some of the key features of this module:
• Calibrates up to 260 ppm of Crystal Error
• Time: Hours, Minutes and Seconds • Requirements: External 32.768 kHz Clock Crystal
• 24-Hour Format (Military Time) • Alarm Pulse or Seconds Clock Output on RTCC
• Visibility of One-Half-Second Period pin
• Provides Calendar: Weekday, Date, Month and
Year
FIGURE 21-1: RTCC BLOCK DIAGRAM
32.768 kHz Input

from SOSC Oscillator
RTCC Prescalers
0.5s YEAR, MTH, DAY
RTCC Timer RTCVAL WKDAY
Alarm HR, MIN, SEC
Event
Comparator
MTH, DAY
Compare Registers ALRMVAL WKDAY
with Masks
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
RTCOE

PIC32MX3XX/4XX
21.1 RTCC Registers
TABLE 21-1: RTCC SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0200 RTCCON 31:24 — — — — — — CAL<9:8>
23:16 CAL<7:0>
15:8 ON FRZ SIDL — — — — —
7:0 RTSECSEL RTCCLKON — — RTCWREN RTCSYNC HALFSEC RTCOE
BF80_0204 RTCCONCLR 31:0 Write clears selected bits in RTCCON, read yields undefined value
BF80_0208 RTCCONSET 31:0 Write sets selected bits in RTCCON, read yields undefined value
BF80_020C RTCCONINV 31:0 Write inverts selected bits in RTCCON, read yields undefined value
BF80_0210 RTCALRM 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0>
7:0 ARPT<7:0>
BF80_0214 RTCALRMCLR 31:0 Write clears selected bits in RTCALRM, read yields undefined value
BF80_0218 RTCALRMSET 31:0 Write sets selected bits in RTCALRM, read yields undefined value
BF80_021C RTCALRMINV 31:0 Write inverts selected bits in RTCALRM, read yields undefined value
BF80_0220 RTCTIME 31:24 HR10<3:0> HR01<3:0>
23:16 MIN10<3:0> MIN01<3:0>
15:8 SEC10<3:0> SEC01<3:0>
7:0 — — — — — — — —
BF80_0224 RTCTIMECLR 31:0 Write clears selected bits in RTCTIME, read yields undefined value
BF80_0228 RTCTIMESET 31:0 Write sets selected bits in RTCTIME, read yields undefined value
BF80_022C RTCTIMEINV 31:0 Write inverts selected bits in RTCTIME, read yields undefined value
BF80_0230 RTCDATE 31:24 YEAR10<3:0> YEAR01<3:0>
23:16 MONTH10<3:0> MONTH01<3:0>
15:8 DAY10<3:0> DAY01<3:0>
7:0 — — — — WDAY01<3:0>
BF80_0234 RTCDATECLR 31:0 Write clears selected bits in RTCDATE, read yields undefined value
BF80_0238 RTCDATESET 31:0 Write sets selected bits in RTCDATE, read yields undefined value
BF80_023C RTCDATEINV 31:0 Write inverts selected bits in RTCDATE, read yields undefined value
BF80_0240 ALRMTIME 31:24 HR10<3:0> HR01<3:0>
23:16 MIN10<3:0> MIN01<3:0>
15:8 SEC10<3:0> SEC01<3:0>
7:0 — — — — — — — —
BF80_0244 ALRMTIMCLR 31:0 Write clears selected bits in ALRMTIME, read yields undefined value
BF80_0248 ALRMTIMESET 31:0 Write sets selected bits in ALRMTIME, read yields undefined value
BF80_024C ALRMTIMEINV 31:0 Write inverts selected bits in ALRMTIME, read yields undefined value
BF80_0250 ALRMDATE 31:24 — — — — — — — —
23:16 MONTH10<3:0> MONTH01<3:0>
15:8 DAY10<3:0> DAY01<3:0>
7:0 — — — — WDAY01<3:0>
BF80_0254 ALRMDATECLR 31:0 Write clears selected bits in ALRMDATE, read yields undefined value
BF80_0258 ALRMDATESET 31:0 Write sets selected bits in ALRMDATE, read yields undefined value
BF80_025C ALRMDATEINV 31:0 Write inverts selected bits in ALRMDATE, read yields undefined value
TABLE 21-2: RTCC INTERRUPT REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1110 IPC8 31:24 — — — RTCCIP<2:0> RTCCIS<1:0>
Note: This summary table contains partial register definitions that only pertain to the RTCC peripheral. Refer to the “PIC32MX Family Reference

PIC32MX3XX/4XX
REGISTER 21-1: RTCCON: RTC CONTROL REGISTER(1)
— — — — — — CAL<9:8>
bit 31 bit 24

CAL<7:0>
bit 23 bit 16

bit 15 bit 8
R/W-0 R-0 r-x r-x R/W-0 R-0 R-0 R/W-0

RTSECSEL RTCCLKON — — RTCWREN RTCSYNC HALFSEC RTCOE
bit 7 bit 0
Legend:

bit 25-16 CAL<9:0>: RTC Drift Calibration bits
Contains a signed 10-bit integer value.
0111111111= Maximum positive adjustment, adds 511 RTC clock pulses every one minute
...
0000000001= Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000= No adjustment
1111111111= Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
...
1000000000= Minimum negative adjustment, subtracts 512 clock pulses every one minute
bit 15 ON: RTCC On bit
1 = RTCC module is enabled
0 = RTCC module is disabled
Note: The ON bit is only writable when RTCWREN = 1.
bit 14 FRZ: Freeze in Debug Mode bit
1 = When emulator is in Debug mode, module freezes operation
0 = When emulator is in Debug mode, module continues operation
1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode
0 = Continue normal operation in Idle mode
bit 7 RTSECSEL: RTCC Seconds Clock Output Select bit
1 = RTCC seconds clock is selected for the RTCC pin
0 = RTCC alarm pulse is selected for the RTCC pin
Note: Requires RTCOE == 1 (RTCCON<0>) for the output to be active.
bit 6 RTCCLKON: Status of the RTCC Clock Enable bit
1 = RTCC clock is actively running
0 = RTCC clock is not running

PIC32MX3XX/4XX
REGISTER 21-1: RTCCON: RTC CONTROL REGISTER(1) (CONTINUED)
bit 3 RTCWREN: RTC Value Registers Write Enable bit
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
Note: The RTCWREN bit can be set only when the write sequence is enabled. The register can be
written to a ‘0’ at any time.
bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading due to a roll over ripple that results in an invalid
data read. If the register is read twice and results in the same data, the data can be assumed to
be valid.
0 = RTC Value registers can be read without concern about a roll over ripple
bit 1 HALFSEC: Half-Second Status bit
1 = Second half period of a second
0 = First half period of a second
Note: This bit is read-only. It is cleared to ‘0’ on a write to the SECONDS register.
bit 0 RTCOE: RTCC Output Enable bit
1 = RTCC clock output enabled – clock presented onto an I/O
0 = RTCC clock output disabled
Note: This bit is ANDed with ON (RTCCON<15>) to produce the effective RTCC output enable.
Note 1: This register is only reset by Power-on Reset (POR).

PIC32MX3XX/4XX
REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER(1)
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

ALRMEN CHIME PIV ALRMSYNC AMASK<3:0>
bit 15 bit 8

ARPT<7:0>
bit 7 bit 0
Legend:

bit 15 ALRMEN: Alarm Enable bit
1 = Alarm is enabled
0 = Alarm is disabled
Note: Hardware clears ALRMEN anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0. This field should not be written when RTCCON = 1 (RTCCON<15>) and
ALRMSYNC = 1.
bit 14 CHIME: Chime Enable bit
1 = Chime is enabled – ARPT<7:0> is allowed to roll over from 00 to FF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 00
Note: This field should not be written when RTCCON = 1 (RTCCON<15>) and ALRMSYNC = 1.
bit 13 PIV: Alarm Pulse Initial Value bit
When ALRMEN = 0, PIV is writable and determines the initial value of the alarm pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the alarm pulse.
bit 12 ALRMSYNC: Alarm Sync bit
1 = ARPT<7:0> and ALRMEN may change as a result of a half-second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since
multiple bits may be changing, which are then synchronized to the PB clock domain.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because prescaler is
> 32 RTC clock away from a half-second rollover
Note: This assumes a CPU read will execute in less than 32 PBCLKs.

PIC32MX3XX/4XX
REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER(1) (CONTINUED)
bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
11XX = Reserved – do not use
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will trigger 256 times
...
00000000 = Alarm will trigger 1 time
The counter decrements on any alarm event. The counter only rolls over from 00 to FF if CHIME = 1.
Note 1: This register is only reset by POR.

PIC32MX3XX/4XX
REGISTER 21-3: RTCTIME: RTC TIME VALUE REGISTER(1)
R-0 R-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
HR10<3:0> HR01<3:0>
bit 31 bit 24
R-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

MIN10<3:0> MIN01<3:0>
bit 23 bit 16

SEC10<3:0> SEC01<3:0>
bit 15 bit 8

— — — — — — — —
bit 7 bit 0
Legend:
bit 31-28 HR10<3:0>: Binary Coded Decimal Value of Hours bits

10 digits; contains a value from 0 to 2.
Note: HR10<3:2> bits are always read ‘0’.
bit 27-24 HR01<3:0>: Binary Coded Decimal Value of Hours bits
1 digit; contains a value from 0 to 9.
bit 23-20 MIN10<3:0>: Binary Coded Decimal Value of Minutes bits
Note: MIN10<3> bit is always read ‘0’.
bit 19-16 MIN01<3:0>: Binary Coded Decimal Value of Minutes bits
bit 15-12 SEC10<3:0>: Binary Coded Decimal Value of Seconds bits
Note: SEC10<3> bit is always read ‘0’.
bit 11-8 SEC01<3:0>: Binary Coded Decimal Value of Seconds bits
Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>).

PIC32MX3XX/4XX
REGISTER 21-4: RTCDATE: RTC DATE VALUE REGISTER(1)
YEAR10<3:0> YEAR01<3:0>
bit 31 bit 24
R-0 R-0 R-0 R/W-x R/W-x R/W-x R/W-x R/W-x

MONTH10<3:0> MONTH01<3:0>
bit 23 bit 16

DAY10<3:0> DAY01<3:0>
bit 15 bit 8
r-x r-x r-x r-x R-0 R/W-x R/W-x R/W-x

— — — — WDAY01<3:0>
bit 7 bit 0
Legend:
bit 31-28 YEAR10<3:0>: Binary Coded Decimal Value of Years bits (10 digits)
bit 27-24 YEAR01<3:0>: Binary Coded Decimal Value of Years bits (1 digit)
bit 23-20 MONTH10<3:0>: Binary Coded Decimal Value of Months bits (10 digits; contains a value from 0 to 1)
Note: MONTH10<3:1> bits are always read ‘0’.
bit 19-16 MONTH01<3:0>: Binary Coded Decimal Value of Months bits (1 digit; contains a value from 0 to 9)
bit 15-12 DAY10<3:0>: Binary Coded Decimal Value of Days bits (10 digits; contains a value from 0 to 3)
Note: DAY10<3:2> bits are always read ‘0’.
bit 11-8 DAY01<3:0>: Binary Coded Decimal Value of Days bits (1 digit; contains a value from 0 to 9)
bit 3-0 WDAY01<3:0>: Binary Coded Decimal Value of Weekdays bits (1 digit; contains a value from 0 to 6)
Note: WDAY01<3> bit is always read ‘0’.
Note 1: This register is only writable when RTCWREN = 1 (RTCCON<3>).

PIC32MX3XX/4XX
REGISTER 21-5: ALRMTIME: ALARM TIME VALUE REGISTER
HR10<3:0> HR01<3:0>
bit 31 bit 24

MIN10<3:0> MIN01<3:0>
bit 23 bit 16

SEC10<3:0> SEC01<3:0>
bit 15 bit 8

— — — — — — — —
bit 7 bit 0
Legend:
bit 31-28 HR10<3:0>: Binary Coded Decimal Value of Hours bits (10 digit; contains a value from 0 to 2)
Note: HR10<3:2> bits are always read ‘0’.
bit 27-24 HR01<3:0>: Binary Coded Decimal Value of Hours bits (1 digit; contains a value from 0 to 9)
bit 23-20 MIN10<3:0>: Binary Coded Decimal Value of Minutes bits, (10 digit; contains a value from 0 to 5)
Note: MIN10<3> bit is always read ‘0’.
bit 19-16 MIN01<3:0>: Binary Coded Decimal Value of Minutes bits (1 digit; contains a value from 0 to 9)
bit 15-12 SEC10<3:0>: Binary Coded Decimal Value of Seconds bits (10 digit; contains a value from 0 to 5)
Note: SEC10<3> bit is always read ‘0’.
bit 11-8 SEC01<3:0>: Binary Coded Decimal Value of Seconds bits (1 digit; contains a value from 0 to 9)

PIC32MX3XX/4XX
REGISTER 21-6: ALRMDATE: ALARM DATE VALUE REGISTER
— — — — — — — —
bit 31 bit 24
R-0 R-0 R-0 R/W-x R/W-x R/W-x R/W-x R/W-x

MONTH10<3:0> MONTH01<3:0>
bit 23 bit 16

DAY10<3:0> DAY01<3:0>
bit 15 bit 8
r-x r-x r-x r-x R-0 R/W-x R/W-x R/W-x

— — — — WDAY01<3:0>
bit 7 bit 0
Legend:
bit 31-24 Reserved: Write ‘0’; ignore read.

Note: MONTH10<3:1> bits are always read ‘0’.
Note: DAY10<3:2> bits are always read ‘0’.
bit 3-0 WDAY01<3:0>: Binary Coded Decimal Value of Weekdays bits (1 digit; contains a value from 0 to 6)
Note: WDAY01<3> bit is always read ‘0’.

PIC32MX3XX/4XX
21.2 Clock Calendar Mode 21.2.2 SAFETY WINDOW FOR REGISTER
READS AND WRITES
The PIC32MX RTCC module provides clock and
calendar functions with the following features: The RTCTIME and RTCDATE registers can be safely
accessed when the RTCC module is disabled (ON bit
• 100-year clock and calendar with automatic leap
(RTCCON<15>) = 0). However, when the RTCC mod-
year detection.
ule is enabled (ON bit = 1), the module provides a single
• Clock range from 00:00:00 (midnight) on January RTCSYNC bit (RTCCON<2>) that the user must use to
1, 2000 to 23:59:59 on December 31, 2099. determine when it is safe to read and update the time
• Clock granularity of one second with half-second and date registers.
visibility to the user.
The RTCSYNC bit indicates a time window during which
the RTCC time registers (RTCTIME, RTCDATE) are not
21.2.1 RTCC CONFIGURATION
about to be updated and can be safely read and written.
The RTCTIME and RTCDATE registers can be
For read or write operations, the registers can be safely
programmed with the desired time and date numeric
accessed by the CPU when RTCSYNC = 0.
values expressed in Binary Coded Decimal (BCD)
format. This simplifies users’ firmware as each of the For a read operation when RTSYNC = 1, the user must
digit values is contained within its own 4-bit value (see employ a firmware solution to assure that the data read
Figure 21-2). did not fall on an update boundary, resulting in an
invalid or partial read. For example, reading and com-
FIGURE 21-2: TIMER DIGIT FORMAT paring a Timer register value twice can ensure in code
that the register read did not span an RTCC clock
DAY OF update.
YEAR MONTH DAY WEEK
Write operations to the Time and Date registers should
0-9 0-9 0-1 0-9 0-3 0-9 0-6 not be performed when RTCSYNC = 1. Refer to
Example 21-2 and Example 21-3.
1/2 SECOND
HOURS BIT
(24-hr format) MINUTES SECONDS (binary format)
0-2 0-9 0-5 0-9 0-5 0-9 0/1
The user can configure the current time by simply writing

the desired year, month, day, hour, minutes and seconds
to the RTCTIME and RTCDATE registers. However,
these registers are write-protected and require a spe-
cial “unlock” sequence to be performed prior to writing
to these registers. Additionally, the user should verify
that the RTCSYNC bit (RTCCON<2>) = 0 (safe to
access registers) for any read or write operations.
Refer to Section 21.2.3 “Write Lock” and
Example 21-3.

PIC32MX3XX/4XX
EXAMPLE 21-1: UPDATING THE RTCC TIME AND DATE
/*
The following code example will update the RTCC time and date.
*/
// assume the secondary oscillator is enabled and ready, i.e.
// OSCCON<1>=1, OSCCON<22>=1, and RTCC write is enabled i.e.
// RTCWREN (RTCCON<3>) =1;
unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec

unsigned long date=0x06102705;// set date to Friday 27 Oct 2006
RTCCONCLR=0x8000; // turn off the RTCC

while(RTCCON&0x40); // wait for clock to be turned off
RTCTIME=time; // safe to update the time
RTCDATE=date; // update the date
RTCCONSET=0x8000; // turn on the RTCC
while(!(RTCCON&0x40)); // wait for clock to be turned on
// can disable the RTCC write
EXAMPLE 21-2: UPDATING THE RTCC TIME USING THE RTCSYNC WINDOW
/*
The following code example will update the RTCC time and date.
*/
// assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1;
unsigned long time=0x04153300;// set time to 04 hr, 15 min, 33 sec

unsigned long date=0x06102705;// set date to Friday 27 Oct 2006
// disable interrupts, critical section follows

while((RTCCON&0x4)!=0); // wait for not RTCSYNC
RTCTIME=time; // safe to update the time
RTCDATE=date; // update the date
// restore interrupts, critical section ended

// can disable the RTCC write
21.2.3 WRITE LOCK Note that steps 2 through 4 must be followed exactly to
unlock RTCC write operations. If the sequence is not
In order to perform a write to any of the RTCC Time reg-
followed exactly, the RTCWREN bit will not be set.
isters, the RTCWREN bit (RTCCON<3>) must be set.
Refer to Example 21-3 for a “C” language
Setting of the RTCWREN bit is only allowed once the
implementation of the write unlock operation.
device level unlocking sequence has been executed.
The unlocking sequence is as follows:
1. Suspend or disable all initiators that can access
the peripheral bus and interrupt the unlock
sequence. (i.e., DMA and Interrupts).
2. Store 0xAA996655 to the SYSKEY register.
3. Store 0x556699AA to the SYSKEY register.
4. Set RTCWREN bit into the RTCCON register.
5. Perform the device relock by writing a dummy
value to the SYSKEY register.
6. Re-enable DMA and interrupts.

PIC32MX3XX/4XX
EXAMPLE 21-3: WRITE UNLOCK SEQUENCE
// assume interrupts are disabled

// assume the DMA controller is suspended
// assume the device is locked
// starting critical sequence

SYSKEY = 0xaa996655; // write first unlock key to SYSKEY
SYSKEY = 0x556699aa; // write second unlock key to SYSKEY
RTCCONSET = 0x8; // set RTCWREN in RTCCONSET
// end critical sequence
SYSKEY = 0x33333333; // perform device re-lock
// can resume the DMA controller activity

// can re-enable interrupts
Note: To avoid accidental writes to the RTCC time values, it is recommended that the RTCWREN bit
(RTCCON<3>) is kept clear at any other time.

PIC32MX3XX/4XX
21.3 Alarm Mode FIGURE 21-4: ALARM MASK SETTINGS
Alarm Mask Setting Day of the
The PIC32MX RTCC module provides alarm functions AMASK<3:0> Week Month Day Hours Minutes Seconds
with the following features: 0000 – Every half-second

0001 – Every second
• One-time alarm 0010 – Every 10 seconds s
• Repeat alarms 0011 – Every minute s s
• Indefinite alarm repetition

0100 – Every 10 minutes m s s
• Configurable from half-second to one year
0101 – Every hour m m s s
The RTCC alarm generates an alarm event when the
RTCC timer matches the masked alarm value. 0110 – Every day h h m m s s
The RTCC alarm functions are configurable from a 0111 – Every week d h h m m s s
half-second to one year and can repeat the alarm at 1000 – Every month d d h h m m s s
preconfigured intervals. The chime feature provides
(1)
indefinite repetition of the alarm. 1001 – Every year m m d d h h m m s s
To enable the alarm feature, configure the ALRMEN bit Note 1: Annually, except when configured for February 29.
(RTCALRM<15>) = 1. To disable the alarm feature,
configure the ALRMEN bit = 0. An alarm event is
generated when the RTCC timer matches the masked
21.3.2 ONE-TIME ALARM
alarm registers. A single, one-time alarm can be generated by configur-
ing the Alarm Repeat Counter bits, ARPT
Note 1: Once the timer value reaches the alarm
(RTCALRM<7:0>) = 0, and the CHIME bit,
setting, one RTCC clock period will (RTCALRM<14>) = 0. Once the alarm event occurs,
elapse prior to setting the alarm interrupt.
the ALRMEN bit is automatically cleared in hardware,
2: IF RTCC is off (RTCCON<15> = 0) the disabling future alarms. The user must re-enable this
writable fields in the RTCALRM register bit for any new alarm configuration.
can be safely modified. If RTCC is ON, It is suggested to read and verify the Alarm Sync bit,
the write of the RTCALRM register has to
ALRMSYNC (RTCALRM<12>) = 0, before performing
be done while ALRMSYNC = 0. Not fol-
the following configuration:
lowing the above steps can result in a
false alarm event. • Disable Alarm – ALRMEN (RTCALRM<15>) = 0.
3: The same applies to the ALRMTIME and • Disable Chime – CHIME (RTCALRM<14>) = 0.
ALRMDATE registers: They can be safely • Clear Alarm Repeat Counter – ARPT
modified only when ALRMSYNC = 0. (RTCALRM<7:0>) = 0.
The remaining bits are shown with example configura-
21.3.1 ALARM CONFIGURATION tions and may be configured as desired:
The ALRMTIME and ALRMDATE registers can be pro- • Configure alarm date and time – Load
grammed with the desired time and date numeric val- ALRMDATE and ALRMTIME registers with the
ues expressed in Binary Coded Decimal (BCD) format. desired alarm date/time values.
This simplifies users’ firmware as each of the digit • Configure mask – Load the desired AMASK
values is contained within its own 4-bit value (see value.
Figure 21-3).
• Enable Alarm – ALRMEN (RTCALRM<15>) = 0.
FIGURE 21-3: ALARM DIGIT FORMAT Refer to Example 21-4

MONTH DAY DAY OF WEEK
0-1 0-9 0-3 0-9 0-6
HOURS
(24-hr format) MINUTES SECONDS
0-2 0-9 0-5 0-9 0-5 0-9
The alarm interval selection is based on the settings of

the alarm mask, AMASK (RTCALRM<11:8>). The
AMASK bits determine which and how many digits of
the alarm must match the RTCC clock value for the
alarm event to occur (see Figure 21-4).

PIC32MX3XX/4XX
EXAMPLE 21-4: CONFIGURING THE RTCC FOR A ONE-TIME ALARM
/*
The following code example will update the RTCC one-time alarm.
Assumes the interrupts are disabled.
*/
unsigned long alTime=0x16153300;// set time to 04 hr, 15 min, 33 sec

unsigned long alDate=0x06102705;// set date to Friday 27 Oct 2006
// turn off the alarm, chime and alarm repeats; clear

// the alarm mask
while(RTCALRM&0x1000); // wait ALRMSYNC to be off

RTCALRMCLR=0xCFFF; // clear ALRMEN, CHIME, AMASK and ARPT;
ALRMTIME=alTime;
ALRMDATE=alDate; // update the alarm time and date
RTCALRMSET=0x8000|0x00000600; // re-enable the alarm, set alarm mask at once per day
21.3.3 REPEAT ALARM It is recommended to read and verify the Alarm Sync bit
ALRMSYNC (RTCALRM<12>) = 0, before performing
A repeat alarm can be generated by configuring the
the following configuration steps:
Alarm Repeat Counter bits, ARPT (RTCALRM<7:0>) =
0x00 to 0xFF (0 to 255), and the CHIME bit • Disable alarm – ALRMEN (RTCALRM<15>) = 0.
(RTCALRM<14>) = 0. Once the alarm is enabled and • Disable chime – CHIME (RTCALRM<14>) = 0.
an alarm event occurs, the ARPT count is decre- • Configure alarm repeat counter – ARPT
mented by one. Once the register reaches 0, the alarm (RTCALRM<7:0>) = 0x00 to 0xFF.
will be generated one last time; after which point,
• Configure alarm date and time – Load
ALRMEN bit is cleared automatically and the alarm will
ALRMDATE and ALRMTIME registers with the
turn off. The user must re-enable this bit for any new
desired alarm date/time values.
alarm configuration.
• Configure mask – Load the desired AMASK
Note: An alarm event is generated when ARPT value.
bits are = 0x00. • Enable alarm – ALRMEN (RTCALRM<15>) = 0.
EXAMPLE 21-5: CONFIGURING THE RTCC FOR A TEN TIMES PER HOUR ALARM
/*
The following code example will update the RTCC repeat alarm.
*/
unsigned long alTime=0x23352300; // set time to 23hr, 35 min, 23 sec

unsigned long alDate=0x06111301; // set date to Monday 13 Nov 2006

// the alarm mask
RTCALRMCLR=0xCFFF; // clear the ALRMEN, CHIME, AMASK and ARPT;
ALRMTIME=alTime;
RTCALRMSET=0x8000|0x0509; // re-enable the alarm, set alarm mask at once per hour
// for 10 times repeat

PIC32MX3XX/4XX
21.3.4 INDEFINITE ALARM • Disable alarm – ALRMEN (RTCALRM<15>) = 0.
An indefinite alarm can be generated by configuring the • Enable chime – CHIME (RTCALRM<14>) = 1.
CHIME bit (RTCALRM<14>) = 1; ARPT can be any • Configure alarm repeat counter – ARPT
value. Once the alarm is enabled and an alarm event (RTCALRM<7:0>) = 0 to 256.
occurs, the ARPT count is decremented by one. ARPT • Configure alarm date and time – Load
rolls over from 0x00 to 0xFF and continues to decre- ALRMDATE and ALRMTIME registers with the
ment on each alarm event indefinitely. The ALRMEN bit desired alarm date/time values.
is never automatically cleared in hardware. The user • Configure mask – Load the desired AMASK
must clear this bit to disable the indefinite alarm. value.
Note: An alarm event is generated when the • Enable Alarm – ALRMEN (RTCALRM<15>) = 0.
ARPT are = 0x00. Refer to Example 21-6.
It is recommended to read and verify the Alarm Sync
bit, ALRMSYNC (RTCALRM<12>) = 0, before
performing the following configuration:
EXAMPLE 21-6: CONFIGURING THE RTCC FOR INDEFINITE ALARM

/*
The following code example will update the RTCC indefinite alarm.
*/
unsigned long alTime=0x23352300; // set time to 23hr, 35 min, 23 sec

unsigned long alDate=0x06111301; // set date to Monday 13 Nov 2006

// the alarm mask
RTCALRMCLR=0xCFFF; // clear ALRMEN, CHIME, AMASK, ARPT;
ALRMTIME=alTime;
RTCALRMSET=0xC600; // re-enable the alarm, set alarm mask at once per
// hour, enable CHIME
21.4 RTCC Clock Source

The RTCC module is intended to be clocked by an
external Real-Time Clock crystal that is oscillating at
32.768 kHz. To allow the RTCC to be clocked by an
external 32.768 kHz crystal, the SOSCEN bit
(OSCCON<1>) must be set (see Section 4.0 “Oscilla-
tors”) or the FSOSCEN (DEVCFG1<5>) Configuration
bit must be programmed to ‘1’. This is the only bit
outside of the RTCC module with which the user must
be concerned of for enabling the RTCC. The status bit,
SOSCRDY (OSCCON<22>), can be used to check that
the secondary oscillator is running.
Note: The RTCC does not have an exclusive
access to use the SOSC oscillator. This
oscillator may be used by other peripher-
als, such as the CPU as a low-power clock
source or Timer1. Refer to the
“PIC32MX3XX/4XX Reference Manual”
(DS61132) regarding the operation of the
Secondary Low-Power Oscillator.

PIC32MX3XX/4XX
21.4.1 CALIBRATION
The real-time crystal input can be calibrated using the
periodic auto-adjust feature. When properly calibrated,
the RTCC can provide an error of less than 0.66 sec-
onds per month. Calibration has the ability to eliminate
an error of up to 260 ppm.
The calibration is accomplished by finding the number
of error clock pulses and writing this value into the CAL
field of the RTCCCON register (RTCCON<9:0>). This
10-bit signed value will either be added or subtracted
from the RTCC timer, once every minute. Refer to the
steps below for RTCC calibration:
1. Using another timer resource on the device, the
user must find the error of the 32.768 kHz
crystal.
2. Once the error is known, it must be converted to
the number of error clock pulses per minute.
EQUATION 21-1: ERROR CLOCKS PER

MINUTE
(Ideal Frequency (32,758) – Measured Frequency)
* 60 = Error Clocks per Minute
3. a) If the oscillator is faster than ideal (negative

result from step 2), the CAL bits register value
needs to be negative. This causes the specified
number of clock pulses to be subtracted from
the timer counter, once every minute.
b) If the oscillator is slower than ideal (positive
result from step 2), the CAL bits register value
needs to be positive. This causes the specified
number of clock pulses to be added to the timer
counter, once every minute.
4. Load the CAL bits (RTCCON<9:0>) with the cor-
rect value.
Writes to the CAL bits should only occur when the timer
is turned off, or immediately after the rising edge of the
seconds pulse (except when the seconds
(RTCTIME<15:8>) field is ‘00’ due to the possibility of
the auto-adjust event).
Note: It is up to the user, to include in the error
value, the initial error of the crystal drift,
due to temperature and drift due to crystal
aging.
A write to the seconds bits resets the state
of calibration (not its value). If an adjust-
ment just occurred, it will occur again
because of the minute roll over.

PIC32MX3XX/4XX
EXAMPLE 21-7: UPDATING THE RTCC CALIBRATION VALUE
/*
The following code example will update the RTCC calibration.
*/
int cal=0x3FD; // 10 bits adjustment, -3 in value
if(RTCCON&0x8000)
{ // RTCC is ON
unsigned intt0, t1;
do
{
t0=RTCTIME;
t1=RTCTIME;
}while(t0!=t1); // read valid time value
if((t0&0xFF)==00)
{ // we’re at second 00, wait auto-adjust to be performed
while(!(RTCCON&0x2)); // wait until second half...
}
}
RTCCONCLR=0x03FF0000; // clear the calibration

RTCCONSET=cal;
21.5 RTCC Interrupts The interrupt priority level bits and interrupt subpriority
The RTCC alarm can be configured to generate an
interrupt at every alarm event. Refer to Section 21.3 • RTCCIP<2:0> (IPC8<28:26>)
“Alarm Mode” for details regarding the various alarm • RTCCIS<1:0> (IPC8<25:24>)
events. In addition to enabling the RTCC interrupt, an Interrupt
The RTCC module is enabled as a source of interrupts Service Routine, ISR, is required (see Example 21-9).
via the respective RTCC interrupt enable bit: Note: It is the user’s responsibility to clear the
• RTCCIE (IEC1<15>). corresponding interrupt flag bit before
The alarm interrupt is signalled by the corresponding returning from an ISR.
RTCC interrupt flag bit:
• RTCCIF (IFS1<15>).
This interrupt flag must be cleared in software.

PIC32MX3XX/4XX
EXAMPLE 21-8: RTCC INITIALIZATION WITH INTERRUPTS
/*
The following code example illustrates an RTCC initialization with interrupts enabled.
When the RTCC alarm interrupt is generated, the cpu will jump to the vector assigned to
RTCC interrupt.
*/
// assume RTCC write is enabled i.e. RTCWREN (RTCCON<3>) =1;
IEC1CLR=0x00008000; // disable RTCC interrupts
RTCCONCLR=0x8000; // turn off the RTCC

while(RTCCON&0x40); // wait for clock to be turned off
IFS1CLR=0x00008000; // clear RTCC existing event

IEC1SET=0x00008000; // Enable RTCC interrupts
RTCTIME=0x16153300; // safe to update time to 16 hr, 15 min, 33 sec

RTCDATE=0x06102705; // update the date to Friday 27 Oct 2006
RTCALRMCLR=0xCFFF; // clear ALRMEN, CHIME, AMASK and ARPT;

ALRMTIME=0x16154300; // set alarm time to 16 hr, 15 min, 43 sec
ALRMDATE=0x06102705; // set alarm date to Friday 27 Oct 2006
RTCALRMSET=0x8000|0x00000600; // re-enable the alarm, set alarm mask at once per day
RTCCONSET=0x8000; // turn on the RTCC

while(!(RTCCON&0x40)); // wait for clock to be turned on
EXAMPLE 21-9: RTCC ISR
/*
The following code example demonstrates a simple interrupt service routine for RTCC
operations and must clear the RTCC interrupt flag before exiting.
*/
void__ISR(_RTCC_VECTOR, ipl3) __RTCCInterrupt(void)

{
// ... perform application specific operations
// in response to the interrupt
IFS1CLR=0x00008000; // be sure to clear RTCC interrupt flag

}
Note: The RTCC ISR code example shows MPLAB® C32 C compiler specific syntax. Refer to your compiler
manual regarding support for ISRs.

PIC32MX3XX/4XX
Enabling the RTCC modules configures the I/O pin
direction. When the RTCC module is enabled, config-
ured and the output enabled, the I/O pin direction is
properly configured as a digital output.
The RTCC pin can be configured to toggle at every
alarm or “seconds” event. To enable the RTCC pin out-
put, set the RTCOE bit (RTCCON<0>) = 1. To select
the output to toggle on an alarm event, configure
RTSECSEL bit (RTCCON<7>) = 0. To select the output
to toggle on every “seconds” update, configure
RTSECSEL bit = 1.
TABLE 21-3: I/O PIN CONFIGURATION FOR USE WITH RTCC MODULE
Required Settings for Module Pin Control
IO Pin Module Bit Pin Buffer
Required TRIS(4) Description
Name Control Field Type Type
ON RTCC Seconds Clock
RTCC Yes(1) and RTSECSEL = 1 X O CMOS
RTCOE(2)
ON RTCC Alarm Pulse
RTCC Yes(1) and RTSECSEL = 0 X O CMOS
RTCOE(2) and ALRMEN
and PIV(3)
Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input;
O = Output
Note 1: The RTCC pin is only required when seconds clock or alarm pulse output is needed. Otherwise, this pin can
be used for general purpose IO and require the user to set the corresponding TRIS control register bit.
2: The ON (RTCCON<15>) and RTCOE (RTCCON<0>) bits are always required to validate the output function
of the RTCC pin, either seconds clock or alarm pulse.
3: When RTSECSEL (RTCCON<7>) = 0, the RTCC pin output is the alarm pulse. If the ALRMEN
(RTCALRM<15>) = 0, PIV (RTCALRM<13>) selects the value at the RTCC pin. When the ALRMEN = 1, the
RTCC pin reflects the state of the alarm pulse.
4: The setting of the TRIS bit is irrelevant.

PIC32MX3XX/4XX
21.7 Updating the Time and Date
Registers
The following flowchart explains in detail the steps that
have to be performed in order to update the RTCTIME
and RTCDATE registers.
Updating the RTCCTIME, RTCCDATE registers logic flow
Start
RTCCON.ON Yes
?
di
No
(ALRMEN && AMASK==HALFSEC &&

Wait RTCC clock off
ALRMSYNC)||RTCSYNC?
No
Yes
Write RTCTIME, Write RTCTIME,

? Or, slower
RTCDATE RTCDATE
Pulse=ALRMSYNC
Or
Either, faster Pulse=RTCSYNC
ei ei
While(pulse);
RTCON.ON=0;
di
Wait RTCC clock off

pulse? No
Write RTCTIME, Write RTCTIME,

RTCDATE Yes RTCDATE
ei
ei
End

PIC32MX3XX/4XX
21.8 Updating the Alarm Registers
The following flowchart explains in detail the steps that
have to be performed in order to update the
ALRMTIME, ALRMDATE and RTCALRM registers.
Updating the ALRMTIME, ALRMDATE or RTCALRM registers logic flow
Start
No RTCC.ON? Yes
W ait RTCC clock off.

W hile(ALRMSYNC);
di
W rite RTCALRM, ALRMSYNC? No

ALRMTIME,
ALRMDATE
W rite RTCALRM,
Yes
ALRMTIME,
ALRMDATE
ei
ei
End

PIC32MX3XX/4XX
22.0 ANALOG-DIGITAL The analog inputs are connected through two multi-
plexers (MUXs) to one SHA. The analog input MUXs
CONVERTER
can be switched between two sets of analog inputs
Note: This data sheet summarizes the features of between conversions. Unipolar differential conversions
the PIC32MX3XX/4XX family of devices. It are possible on all channels, other than the pin used as
is not intended to be a comprehensive refer- the reference, using a reference input pin (see
ence source. Refer to the “PIC32MX Family Figure 22-1).
Reference Manual” (DS61132) for a The Analog Input Scan mode sequentially converts
detailed description of this peripheral. user-specified channels. A control register specifies
which analog input channels will be included in the
The PIC32MX3XX/4XX 10-bit Analog-to-Digital (A/D) scanning sequence.
converter (or ADC) includes the following features:
The 10-bit ADC is connected to a 16-word result buffer.
• Successive Approximation Register (SAR) Each 10-bit result is converted to one of eight, 32-bit
conversion output formats when it is read from the result buffer.
• Up to 500 kilo samples per second (ksps)
conversion speed
• Up to 16 analog input pins
• External voltage reference input pins
• One unipolar, differential Sample-and-Hold
Amplifier (SHA)
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Selectable Buffer Fill modes
• Eight conversion result format options
• Operation during CPU SLEEP and IDLE modes
A block diagram of the 10-bit ADC is shown in
Figure 22-1. The 10-bit ADC can have up to 16 analog
input pins, designated AN0-AN15. In addition, there are
two analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins and may be com-
mon to other analog module references. The actual
number of analog input pins and external voltage refer-
ence input configuration will depend on the specific
PIC32MX device. Refer to the device data sheet for
further details.

PIC32MX3XX/4XX
FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus
AVDD
VR+ 32
VR Select
AVSS
VREF+
VR-
VREF- Comparator
VINH
+ VR- VR+
SHA DAC
VINL -
AN0
AN1 VINH
10-bit SAR Conversion Logic
AN2 +
MUX A
AN3
AN4
–
AN5
VINL
AN6 CH0NA ADC1BUF0: Data
ADC1BUFF Formatting
AN7
AN8 AD1CON1
AD1CON2
AN9
AD1CON3
+
AN10 VINH AD1CHS
MUX B
AD1PCFG
AN11
AD1CSSL
AN12 –
VINL
AN13
CH0NB
AN14 Sample Control Control Logic
Conversion Control
AN15
Pin Config Control
Input MUX Control

PIC32MX3XX/4XX
22.1 Control Registers The AD1CSSL register selects inputs to be sequen-
tially scanned.
The ADC module includes the following Special Func-
tion Registers (SFRs): • AD1CSSL: ADC Input Scan Selection Register
AD1CSSLCLR, AD1CSSLSET, AD1CSSLINV:
The AD1CON1, AD1CON2 and AD1CON3 registers Atomic Bit Manipulation, Write-only Registers for
control the operation of the ADC module. AD1CSSL.
• AD1CON1: ADC Control Register 1 The ADC module also has the following associated bits
AD1CON1CLR, AD1CON1SET, AD1CON1INV: for interrupt control:
Atomic Bit Manipulation, Write-only Registers for
• Interrupt Request Flag Status bit (AD1IF) in IFS1:
AD1CON1.
Interrupt Flag Status Register 1
• AD1CON2: ADC Control Register 2 • Interrupt Enable Control bit (AD1IE) in IEC1:
AD1CON2CLR, AD1CON2SET, AD1CON2INV: Interrupt Enable Control Register 1
Atomic Bit Manipulation, Write-only Registers for • Interrupt Priority Control bits (AD1IP<2:0>) and
AD1CON2. (AD1IS<1:0>) in IPC6: Interrupt Priority Control
• AD1CON3: ADC Control Register 3 Register 6
AD1CON3CLR, AD1CON3SET, AD1CON3INV:
AD1CON3.
The AD1CHS register selects the input pins to be con-
nected to the SHA.
• AD1CHS: ADC Input Channel Select Register
AD1CHSCLR, AD1CHSSET, AD1CHSINV:
AD1CHS.
The AD1PCFG register configures the analog input
pins as analog inputs or as digital I/O.
• AD1PCFG: ADC Port Configuration Register
AD1PCFGCLR, AD1PCFGSET, AD1PCFGINV:
AD1PCFG.

PIC32MX3XX/4XX
22.1.1 SPECIAL FUNCTION REGISTERS
ASSOCIATED WITH THE 10-BIT
ADC
Table 22-1 provides a summary of all ADC-related reg-
isters, including their addresses and formats. Corre-
sponding registers appear after the summary, followed
by a detailed description of each register. All
unimplemented registers and/or bits within a register
read as zeros.
.
TABLE 22-1: ADC SFR SUMMARY
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_9000 AD1CON1 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 ON FRZ SIDL — — FORM2 FORM1 FORM0
7:0 SSRC2 SSRC1 SSRC0 CLRASAM — ASAM SAMP DONE
BF80_9004 AD1CON1CLR 31:0 Write clears selected bits in AD1CON1, read yields undefined value
BF80_9008 AD1CON1SET 31:0 Write sets selected bits in AD1CON1, read yields undefined value
BF80_900C AD1CON1INV 31:0 Write inverts selected bits in AD1CON1, read yields undefined value
BF80_9010 AD1CON2 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — —
7:0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
BF80_9020 AD1CON3 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
7:0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
BF80_9040 AD1CHS 31:24 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0
23:16 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0
15:8 — — — — — — — —
7:0 — — — — — — — —
BF80_9044 AD1CHSCLR 31:0 Write clears selected bits in AD1CHS, read yields undefined value
BF80_9048 AD1CHSSET 31:0 Write sets selected bits in AD1CHS, read yields undefined value
BF80_904C AD1CHSINV 31:0 Write inverts selected bits in AD1CHS, read yields undefined value
BF80_9060 AD1PCFG 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
7:0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
BF80_9064 AD1PCFGCLR 31:0 Write clears selected bits in AD1PCFG, read yields undefined value
BF80_9068 AD1PCFGSET 31:0 Write sets selected bits in AD1PCFG, read yields undefined value
BF80_906C AD1PCFGINV 31:0 Write inverts selected bits in AD1PCFG, read yields undefined value
BF80_9050 AD1CSSL 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
7:0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0

PIC32MX3XX/4XX
TABLE 22-1: ADC SFR SUMMARY (CONTINUED)
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_9054 AD1CSSLCLR 31:0 Write clears selected bits in AD1CSSL, read yields undefined value
BF80_9058 AD1CSSLSET 31:0 Write sets selected bits in AD1CSSL, read yields undefined value
BF80_905C AD1CSSLINV 31:0 Write inverts selected bits in AD1CSSL, read yields undefined value
BF80_9070 ADC1BUF0 31:0 ADC Result Word 0 (ADC1BUF0<31:0>)
BF80_90A0 ADC1BUF3 31:0 ADC Result Word 3 (ADC1BUF3<31:0>)
BF80_90B0 ADC1BUF4 31:0 ADC Result Word 4 (ADC1BUF4<31:0>)
BF80_90C0 ADC1BUF5 31:0 ADC Result Word 5 (ADC1BUF5<31:0>)
BF80_90D0 ADC1BUF6 31:0 ADC Result Word 6 (ADC1BUF6<31:0>)
BF80_90E0 ADC1BUF7 31:0 ADC Result Word 7 (ADC1BUF7<31:0>)
BF80_90F0 ADC1BUF8 31:0 ADC Result Word 8 (ADC1BUF8<31:0>)
BF80_9110 ADC1BUFA 31:0 ADC Result Word A (ADC1BUFA<31:0>)
BF80_9120 ADC1BUFB 31:0 ADC Result Word B (ADC1BUFB<31:0>)
BF80_9130 ADC1BUFC 31:0 ADC Result Word C (ADC1BUFC<31:0>)
BF80_9140 ADC1BUFD 31:0 ADC Result Word D (ADC1BUFD<31:0>)
BF80_9150 ADC1BUFE 31:0 ADC Result Word E (ADC1BUFE<31:0>)
BF80_9160 ADC1BUFF 31:0 ADC Result Word F (ADC1BUFF<31:0>)
TABLE 22-2: ADC INTERRUPT REGISTER SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_10F0 IPC6 31:24 — — — AD1IP<2:0> AD1IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the ADC peripheral. Refer to the PIC32MX Family Reference

PIC32MX3XX/4XX
REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 r-x r-x R/W-0 R/W-0 R/W-0

ON FRZ SIDL — — FORM<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 R/W-0 R/C-0

SSRC<2:0> CLRASAM — ASAM SAMP DONE
bit 7 bit 0
Legend:

bit 15 ON: ADC Operating Mode bit
1 = A/D converter module is operating
0 = A/D converter is off
Note: FRZ is writable in Debug Exception mode only. It reads ‘0’ in Normal mode.
bit 10-8 FORM<2:0>: Data Output Format bits
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = Timer 3 period match ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing SAMP bit ends sampling and starts conversion

PIC32MX3XX/4XX
REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 4 CLRASAM: Stop Conversion Sequence bit (when the first A/D converter interrupt is generated)
1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when
the ADC interrupt is generated.
0 = Normal operation, buffer contents will be overwritten by the next conversion sequence
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set.
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
1 = The ADC SHA is sampling
0 = The ADC sample/hold amplifier is holding
When ASAM = 0, writing ‘1’ to this bit starts sampling.
When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.
bit 0 DONE: A/D Conversion Status bit
1 = A/D conversion is done
0 = A/D conversion is not done or has not started
Clearing this bit will not affect any operation in progress.
Note: The DONE bit is not persistent in automatic modes. It is cleared by hardware at the
beginning of the next sample.

PIC32MX3XX/4XX
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 r-x r-x

VCFG<2:0> OFFCAL — CSCNA — —
bit 15 bit 8
R-0 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUFS — SMPI<3:0> BUFM ALTS
bit 7 bit 0
Legend:

bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
ADC VR+ ADC VR-
000 AVDD AVSS
001 External VREF+ pin AVSS
010 AVDD External VREF- pin
011 External VREF+ pin External VREF- pin
1xx AVDD AVSS
bit 12 OFFCAL: Input Offset Calibration Mode Select bit
1 = Enable Offset Calibration mode
VINH and VINL of the SHA are connected to VR-
0 = Disable Offset Calibration mode
The inputs to the SHA are controlled by AD1CHS or AD1CSSL
bit 10 CSCNA: Scan Input Selections for CH0+ SHA Input for MUX A Input Multiplexer Setting bit
1 = Scan inputs
0 = Do not scan inputs
bit 7 BUFS: Buffer Fill Status bit
Only valid when BUFM = 1 (ADRES split into 2 x 8-word buffers).
1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF

PIC32MX3XX/4XX
REGISTER 22-2: AD1CON2: ADC CONTROL REGISTER 2 (CONTINUED)
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
.....
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: ADC Result Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers, ADC1BUF(7...0), ADC1BUF(15...8)
0 = Buffer configured as one 16-word buffer ADC1BUF(15...0.)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and
MUX A input multiplexer settings for all subsequent samples
0 = Always use MUX A input multiplexer settings

PIC32MX3XX/4XX
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADRC — — SAMC<4:0>
bit 15 bit 8

ADCS<7:0>
bit 7 bit 0
Legend:

bit 15 ADRC: ADC Conversion Clock Source bit
1 = ADC internal RC clock
0 = Clock derived from Peripheral Bus Clock (PBClock)
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
11111 = 31 TAD
·····
00001 = 1 TAD
00000 = 0 TAD (Not allowed)
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits
11111111 = TPB • (ADCS<7:0> + 1) • 2 = 512 • TPB = TAD
······
00000001 = TPB • (ADCS<7:0> + 1) • 2 = 4 • TPB = TAD
00000000 = TPB • (ADCS<7:0> + 1) • 2 = 2 • TPB = TAD

PIC32MX3XX/4XX
REGISTER 22-4: AD1CHS: ADC INPUT SELECT REGISTER
R/W-0 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — — — CH0SB<3:0>
bit 31 bit 24
R/W-0 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0

CH0NA — — — CH0SA<3:0>
bit 23 bit 16

— — — — — — — —
bit 15 bit 8

— — — — — — — —
bit 7 bit 0
Legend:
bit 31 CH0NB: Negative Input Select for MUX B bit

1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 27-24 CH0SB<3:0>: Positive Input Select for MUX B bits
1111 = Channel 0 positive input is AN15
······
bit 23 CH0NA: Negative Input Select for MUX A Multiplexer Setting bit(2)
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VR-
bit 19-16 CH0SA<3:0>: Positive Input Select for MUX A Multiplexer Setting bits
······

PIC32MX3XX/4XX
REGISTER 22-5: AD1PCFG: ADC PORT CONFIGURATION REGISTER
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
— — — — — — — —
bit 31 bit 24
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0

— — — — — — — —
bit 23 bit 16

PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
bit 31-16 Reserved: Reserved for future use, maintain as ‘0’

bit 15-0 PCFG<15:0>: Analog Input Pin Configuration Control bits
1 = Analog input pin in Digital mode, port read input enabled, ADC input multiplexer input for this
analog input connected to AVss
0 = Analog input pin in Analog mode, digital port read will return as a ‘1’ without regard to the voltage
on the pin, ADC samples pin voltage

PIC32MX3XX/4XX
REGISTER 22-6: AD1CSSL: ADC INPUT SCAN SELECT REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W R/W-0

CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:
bit 31-16 Reserved: Write ‘0’

bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selection bits
1 = Select ANx for input scan
0 = Skip ANx for input scan

PIC32MX3XX/4XX
22.2 ADC Operation, Terminology, and Acquisition time can be controlled manually or auto-
Conversion Sequence matically. The acquisition time may be started manually
by setting the SAMP bit (AD1CON1<1>), and ended
This section will describe the operation the A/D con- manually by clearing the SAMP in the user software.
verter, the steps required to configure the converter, The acquisition time may be started automatically by
describe the special feature of the module, and provide the A/D converter hardware and ended automatically
examples of ADC configuration with timing diagrams by a conversion trigger source. The acquisition time is
and charts showing the expected output of the set by the SAMC bits (AD1CON3<12:8>). The SHA
converter. has a minimum acquisition period. Refer to the device
data sheet for acquisition time specifications
22.2.1 OVERVIEW OF OPERATION
Conversion time is the time required for the A/D con-
Analog sampling consists of two steps: acquisition and verter to convert the voltage held by the SHA. The A/D
conversion (see Figure 22-2). During acquisition the converter requires one ADC clock cycle (TAD) to con-
analog input pin is connected to the Sample and Hold vert each bit of the result, plus two additional clock
Amplifier (SHA). After the pin has been sampled for a cycles. Therefore, a total of 12 TAD cycles are required
sufficient period, the sample voltage is equivalent to the to perform the complete conversion. When the
input, the pin is disconnected from the SHA to provide conversion time is complete, the result is written into
a stable input voltage for the conversion process. The one of the 16 ADC result registers
conversion process then converts the analog sample (ADC1BUF0...ADC1BUFF).
voltage to a binary representation.
The sum of the acquisition time and the A/D conver-
An overview of the ADC is presented in Figure 22-1. sion time provides the total sample time (refer to
The 10-bit A/D converter has a single SHA. The SHA is Figure 22-2). There are multiple input clock options
connected to the analog input pins via the analog input for the A/D converter that are used to create the TAD
MUXs, MUX A and MUX B. The analog input MUXs are clock. The user must select an input clock option that
controlled by the AD1CHS register. There are two sets does not violate the minimum TAD specification.
of MUX control bits in the AD1CHS register. These two
The sampling process can be performed once, period-
sets of control bits allow the two different analog input
ically, or based on a trigger as defined by the module
to be independently controlled. The A/D converter can
configuration.
optionally switch between MUX A and MUX B configu-
rations between conversions. The A/D converter can
also optionally scan through a series of analog inputs
using a single MUX.
FIGURE 22-2: ADC SAMPLE/CONVERSION SEQUENCE
ADC Total Sample Time
Acquisition Time A/D Conversion Time
A/D conversion complete, result is written into the

ADC result buffer.
Optionally generate interrupt.
SHA is disconnected from input and holds the signal.

A/D conversion is started by the conversion trigger source.
SHA is connected to the analog input pin for sampling.

PIC32MX3XX/4XX
The start time for sampling can be controlled in soft- C-2. Select the sample clock source using
ware by setting the SAMP control bit. The start of the SSRC<2:0> (AD1CON1<7:5>), as described
sampling time can also be controlled automatically by in Section 22.3.3.1 “Selecting the Sample
the hardware. When the A/D converter operates in the Clock Source”.
Auto-Sample mode, the SHA is reconnected to the
D-1. Select the voltage reference source using
analog input pin at the end of the conversion in the
VCFG<2:0> (AD1CON2<15:13>), as
sample/convert sequence. The auto-sample function is
described in Section 22.3.6 “Selecting the
controlled by the ASAM control bit (AD1CON1<2>).
Voltage Reference Source”.
The conversion trigger source ends the sampling time D-2. Select the Scan mode using CSCNA
and begins an A/D conversion or a sample/convert (AD1CON2<10>), as described in Section
sequence. The conversion trigger source is selected by 22.3.7 “Selecting the Scan Mode”.
the control bits SSRC<2:0> (AD1CON1<7:5>). The D-3. Set the number of conversions per interrupt
conversion trigger can be taken from a variety of hard- SMPI<3:0> (AD1CON2<5:2>), if interrupts
ware sources, or can be controlled manually in soft- are to be used, as described in Section
ware by clearing the SAMP control bit. One of the 22.3.8 “Setting the Number of Conver-
conversion trigger sources is an auto-conversion. The sions per Interrupt”.
time between auto-conversions is set by a counter and
D-4. Set Buffer Fill mode using BUFM
the ADC clock. The Auto-Sample mode and auto-con-
(AD1CON2<1>), as described in Section
version trigger can be used together to provide endless
22.3.9 “Buffer Fill Mode”.
automatic conversions without software intervention.
D-5. Select the MUX to be connected to the ADC
An interrupt may be generated at the end of each sam- in ALTS (AD1CON2<0>), as described in
ple sequence or multiple sample sequences as deter- Section 22.3.10 “Selecting the MUX to be
mined by the value of the SMPI<3:0> Connected to the ADC (Alternating Sam-
(AD1CON2<5:2>). The number of sample sequences ple Mode)”.
between interrupts can vary between 1 and 16. The
E-1. Select the ADC clock source using ADRC
user should note that the A/D conversion buffer holds
(AD1CON3<15>), as described in Section
the results of a single conversion sequence. The next
22.3.11 “Selecting the ADC Conversion
sequence starts filling the buffer from the top even if the
Clock Source and Prescaler”.
number of samples in the previous sequence was less
than 16. The total number of conversion results E-2. Select the sample time using SAMC<4:0>
between interrupts is the SMPI value. The total number (AD1CON3<12:8>), if auto-convert is to be
of conversions between interrupts cannot exceed the used, as described in Section 22.3.12
physical buffer length. “Acquisition Time Considerations”.
E-3. Select the ADC clock prescaler using
ADCS<7:0> (AD1CON3<7:0>), as described
22.3 ADC Module Configuration
in Section 22.3.11 “Selecting the ADC
Operation of the ADC module is directed through bit Conversion Clock Source and Prescaler”.
settings in the appropriate registers. The following
instructions summarize the actions and the settings. F. Turn on ADC module using AD1CON1<15>,
Options and details for each configuration step are as described in Section 22.3.13 “Turning
provided in subsequent sections. the ADC On”.
1. To configure the ADC module, perform the Note: Steps A through E, above, can be per-
following steps: formed in any order, but Step F must be
the final step in every case.
A-1. Configure analog port pins in
AD1PCFG<15:0>, as described in Section 2. To configure ADC interrupt (if required).
22.3.1 “Configuring Analog Port Pins”.
A-1. Clear AD1IF bit (IFS1<1>), as described in
B-1. Select the analog inputs to the ADC MUXs in Section 8.0 “Interrupts”.
AD1CHS<32:0>, as described in Section A-2. Select ADC interrupt priority AD1IP<2:0>
22.3.2 “Selecting the Analog Inputs to the (IPC<28:26>) and sub priority AD1IS<1:0>
ADC MUXs”. (IPC<24:24>), as described in Section 8.0
“Interrupts”, if interrupts are to be used.
C-1. Select the format of the ADC result using
FORM<2:0> (AD1CON1<10:8>), as 3. Start the conversion sequence by initiating
described in Section 22.3.3 “Selecting the sampling, as described in Section 22.3.14 “Ini-
Format of the ADC Result”. tiating Sampling”.

PIC32MX3XX/4XX
22.3.1 CONFIGURING ANALOG PORT 22.3.3 SELECTING THE FORMAT OF THE
PINS ADC RESULT
The AD1PCFG register and the TRISB register control The data in the ADC Result register can be read as one
the operation of the ADC port pins. of eight formats. The format is controlled by
AD1PCFG specifies the configuration of device pins to FORM<2:0> (AD1CON1<10:8>). The user can select
be used as analog inputs. A pin is configured as an from integer, signed integer, fractional or signed
analog input when the corresponding PCFGn bit fractional as a 16-bit or 32-bit result.
(AD1PCFG<n>) = 0. When the bit = 1, the pin is set to
22.3.3.1 Selecting the Sample Clock Source
digital control. When configured for analog input, the
associated port I/O digital input buffer is disabled so it It is often desirable to synchronize the end of sampling
does not consume current. The AD1PCFG register is and the start of conversion with some other time event.
cleared at Reset, causing the ADC input pins to be The ADC module may use one of four sources as a
configured for analog input by default at Reset. conversion trigger. The selection of the conversion trig-
ger source is controlled by the SSRC<2:0>
TRIS registers control the digital function of the port
(AD1CON1<7:5>) bits.
pins. The port pins that are desired as analog inputs
must have their corresponding TRIS bit set, specifying
22.3.3.2 Manual Conversion
the pin as an input. If the I/O pin associated with an
ADC input is configured as an output, the TRIS bit is To configure the ADC to end sampling and start a con-
cleared and the ports digital output level (VOH or VOL) version when SAMP is cleared (= 0), SSRC is set to
will be converted. After a device Reset, all TRIS bits are ‘000’.
set.
22.3.3.3 Timer Compare Trigger
Notes: When reading a PORT register that The ADC is configured for this Trigger mode by setting
shares pins with the ADC, any pin config- SSRC<2:0> = 010. When a period match occurs for
ured as an analog input reads as a ‘0’ the 32-bit timer, TMR3/TMR2, or the 16-bit Timer3, a
when the PORT latch is read. special A/D converter trigger event signal is generated
Analog levels on any pin that is defined as by Timer3.
a digital input (including the AN15:AN0
22.3.3.3.1 External INT0 Pin Trigger
pins), but is not configured as an analog
input, may cause the input buffer to con- To configure the ADC to begin a conversion on an
sume current that is out of the device’s active transition on the INT0 pin, SSRC<2:0> is set to
specification. ‘001’. The INT0 pin may be programmed for either a
rising edge input or a falling edge input to trigger the
22.3.2 SELECTING THE ANALOG INPUTS conversion process.
TO THE ADC MUXS 22.3.3.3.2 Auto-Convert
The AD1CHS register is used to select which analog The ADC can be configured to automatically perform
input pin is connected to MUX A and MUX B. Each conversions at the rate selected by the Auto-Sample
MUX has two inputs referred to as the positive and the Time bits, SAMC<4:0>. The ADC is configured for this
negative input. The positive input to MUX A is con- Trigger mode by setting SSRC<2:0> = 111. In this
trolled by CH0SA<4:0> and the negative input is con- mode, the ADC will perform continuous conversions on
trolled by CH0NA. The positive input for MUX B is the selected channels.
controlled by CH0SB<4:0> and the negative input is
controlled by CH0NB.
The positive input can be selected from any one of the
available analog input pins. The negative input can be
selected as the ADC negative reference or AN0. The
use of AN0 as the negative input allows the ADC to be
used in a Unipolar Differential mode. Refer to the
device data sheet for AN0 input voltage restrictions
when used as a negative reference.

PIC32MX3XX/4XX
22.3.4 SYNCHRONIZING ADC 22.3.7.1 Scan Mode Enable
OPERATIONS TO INTERNAL OR Scan mode is enabled by setting CSCNA
EXTERNAL EVENTS (AD1CON2<10>). When Scan mode is enabled, the
The modes where an external event trigger pulse ends positive input of MUX A is controlled by the contents of
sampling and starts conversion the AD1CSSL register. Each bit in the AD1CSSL
(SSRC2:SSRC0 = 001, 010 or 011) may be used in register corresponds to an analog input. Bit 0 corre-
combination with auto-sampling (ASAM = 1) to cause sponds to AN0, bit 1 corresponds to AN1 and so on. If
the ADC to synchronize the sample conversion events a particular bit in the AD1CSSL register is ‘1’, the
to the trigger pulse source. For example, where corresponding input is part of the scan sequence.
SSRC = 010 and ASAM = 1, the ADC will always end
sampling and start conversions synchronously with the 22.3.7.2 Using Scan and Alternate Modes
timer compare trigger event. The ADC will have a Together
sample conversion rate that corresponds to the timer The Scan and Alternate modes may be combined to
comparison event rate. allow a vector of inputs to be scanned and a single
input to be converted every other sample.
22.3.5 SELECTING AUTOMATIC OR
This mode is enabled by setting the CSCNA bit = 1,
MANUAL SAMPLING
and setting the ALTS (AD1CON2<0>) bit = 1.
Sampling can be started manually or automatically
The CSCNA bit enables the scan for MUX A, and the
when the previous conversion is complete.
CH0SB<3:0> (AD1CHS<27:24>) and CH0NB
22.3.5.1 Manual (AD1CHS<31>) are used to configure the inputs to
MUX B. Scanning only applies to the MUX A input
Clearing the ASAM (AD1CON1<2>) bit disables the selection. The MUX B input selection, as specified by
Auto-Sample mode. Acquisition will begin when the CH0SB<3:0>, will still select a single input.
SAMP (AD1CON1<1>) bit is set by software. Acquisi-
tion will not resume until the SAMP bit is once again 22.3.8 SETTING THE NUMBER OF
set. CONVERSIONS PER INTERRUPT
22.3.5.2 Automatic The SMPI<3:0> bits (AD1CON2<5:2>) select how
many A/D conversions will take place before a CPU
Setting the ASAM (AD1CON1<2>) bit enables the interrupt is generated. This also defines the number of
Auto-Sample mode. In this mode, the sampling will locations that will be written in the result buffer stating
start automatically after the pervious sample has been with ADC1BUF0 (ADC1BUF0 or ADC1BUF8 for Dual
converted. Buffer mode). This can vary from 1 sample to 16 sam-
ples (1 to 8 samples for Dual Buffer mode). After the
22.3.6 SELECTING THE VOLTAGE
interrupt is generated, the sampling sequence restarts;
REFERENCE SOURCE with the result of the first sample being written to the
The user can select the voltage reference for the ADC first buffer location.
module. The reference can be internal or external. The data in the result registers will be overwritten by the
The VCFG<2:0> control bits (AD1CON2<15:13>) next sampling sequence. The data in the result buffer
select the voltage reference for A/D conversions. The must be read before the completion of the first sample
upper voltage reference (VR+) and the lower voltage after the interrupt is generated.
reference (VR-) may be the internal AVDD and AVSS
voltage rails, or the VREF+ and VREF- input pins.
22.3.7 SELECTING THE SCAN MODE
The ADC module has the ability to scan through a
selected vector of inputs. The CSCNA bit
(AD1CON2<10>) enables the MUX A input to be
scanned across a selected number of analog inputs.

PIC32MX3XX/4XX
22.3.9 BUFFER FILL MODE 22.3.10.2 Alternating Input Selections
The Buffer Fill mode allows the output buffer to be used The ALTS bit causes the module to alternate between
as a single, 16-word buffer or two, 8-word buffers. the two input MUXs.
When BUFM is ‘0’, the complete 16-word buffer is used The inputs specified by CH0SA<3:0> and CH0NA are
for all conversion sequences. Conversion results will called the MUX A inputs. The inputs specified by
be written sequentially in the buffer, starting at CH0SB<3:0> and CH0NB are called the MUX B inputs.
ADC1BUF0 until the number of samples as defined by When ALTS is ‘1’, the module will alternate between
SMPI<3:0> (AD1CON2<5:2>) is reached. The next the MUX A inputs on one sample and the MUX B inputs
conversion result will be written to ADC1BUF0 and the on the subsequent sample. When ALTS is ‘0’, only the
process repeats. If the ADC interrupt is enabled, an inputs specified by CH0SA<3:0> and CH0NA are
interrupt will be generated when the number of selected for sampling.
samples in the buffer equals SMPI<3:0>.
When the BUFM bit (AD1CON2<1>) is ‘1’, the 16-word 22.3.11 SELECTING THE ADC
results buffer (ADRES) will be split into two 8-word CONVERSION CLOCK SOURCE
groups. Conversion results will be written sequentially AND PRESCALER
into the first buffer starting at ADC1BUF0, BUFS
The ADC module can use the internal RC oscillator or
(AD1CON2<7>) will be cleared, until the number of
the PBCLK as the conversion clock source.
samples as defined by SMPI<3:0> (AD1CON2<5:2>)
is reached. The ADC interrupt flag will then be set. When the internal RC oscillator is used as the clock
source, ADRC (AD1CON3<15>) = 1, the TAD is the
After the ADC interrupt flag is set, the following result
period of the oscillator, no prescaler are used. When
will be written sequentially to the second buffer, starting
using the internal oscillator the ADC can continue to
at ADC1BUF8 The next conversion result will be writ-
function in SLEEP and in IDLE.
ten to the second buffer; starting at ADC1BUF8, BUFS
(AD1CON2<7>) will be set until the number of samples When the PBCLK is used as the conversion clock
as defined by SMPI<3:0> (AD1CON2<5:2>) is source, ADRC = 0, the TAD is the period of the PBCLK
reached. The ADC interrupt flag will then be set. after the prescaler ADCS<7:0> (AD1CON3<7:0>) is
applied.
The process then restarts with BUFS = 0 and the
results being written to the first buffer. The A/D converter has a maximum rate at which con-
versions may be completed. An analog module clock,
22.3.10 SELECTING THE MUX TO BE TAD, controls the conversion timing. The A/D conver-
CONNECTED TO THE ADC sion requires 12 clock periods (12 TAD).
(ALTERNATING SAMPLE MODE) The period of the ADC conversion clock is software
The ADC has two input MUXs that connect to the SHA. selected using a 8-bit counter. There are 256 possible
These MUXs are used to select which analog input is options for TAD, specified by the ADCS<7:0> bits
to be sampled. Each of the MUXs have a positive and (AD1CON3<7:0>).
a negative input. Equation 22-3 gives the TAD value as a function of the
ADCS control bits and the device instruction cycle
22.3.10.1 Single Input Selection clock period, TCY.
The user may select one of up to 16 analog inputs, as
determined by the number of analog channels on the EQUATION 22-3: ADC CONVERSION
device, as the positive input of the SHA. The CLOCK PERIOD
CH0SA<3:0> bits (AD1CHS<19:16>) select the posi-
tive analog input.
TAD = 2 • (TPB(AADCS + 1)
The user may select either VR- or AN1 as the negative
input. The CH0NA bit (AD1CHS<23>) selects the ana-
log input for the negative input of channel 0. Using AN1 ADCS = (TAD/(2 •TPB)) - 1
as the negative input allows unipolar differential mea-
surements.
The ALTS bit (AD1CON2<0>) must be clear for this For correct A/D conversions, the ADC conversion clock
mode of operation. (TAD) must be selected to meet the minimum TAD time.

PIC32MX3XX/4XX
EQUATION 22-4: AVAILABLE SAMPLING
TIME, SEQUENTIAL
SAMPLING
TSMP = Trigger Pulse Interval (TSEQ) –

Conversion Time (TCONV)
TSMP = TSEQ – TCONV
Note: TSEQ is the trigger pulse interval time.
22.3.12 ACQUISITION TIME

CONSIDERATIONS
Different acquisition/conversion sequences provide dif-
ferent times for the sample-and-hold channel to acquire
the analog signal. The user must ensure the acquisition
time meets the sampling requirements.
When SSRC<2:0> (AD1CON1<7:5>) = 111, the con-
version trigger is under ADC clock control. The
SAMC<4:0> bits (AD1CON3<12:8>) select the number
of TAD clock cycles between the start of acquisition and
the start of conversion. This trigger option provides the
fastest conversion rates on multiple channels. After the
start of acquisition, the module will count a number of
TAD clocks specified by the SAMC bits.
22.3.13 TURNING THE ADC ON

When the ON bit (AD1CON1<15>) is ‘1’, the module is
in Active mode and is fully powered and functional.
When ON is ‘0’, the module is disabled. The digital and
analog portions of the circuit are turned off for maxi-
mum current savings.
In order to return to the Active mode from the Off mode,
the user must wait for the analog stages to stabilize.
For the stabilization time, refer to the Electrical
Characteristics section of the device data sheet.
Note: Writing to ADC control bits other than ON

(AD1CON1<15>), SAMP (AD1CON1<1>),
and DONE (AD1CON1<0>) is not recom-
mended while the A/D converter is running.
22.3.14 INITIATING SAMPLING
22.3.14.1 Manual Mode

In manual sampling, a acquisition is started by writing a
‘1’ to the SAMP (AD1CON1<1>) bit. Software must
manually manage the start and end of the acquisition
period by setting SAMP and then clearing SAMP after
the desired acquisition period has elapsed.
22.3.14.2 Auto-Sample Mode
In Auto-Sample mode, the sampling process is started
by writing a ‘1’ to the ASAM (AD1CON1<2>) bit. In
Auto-Sample mode, the acquisition period is defined by
ADCS<7:0> (AD1CON3<7:0>). Acquisition is automat-
ically started after a conversion is completed. Auto-
Sample mode can be used with any trigger source
other than manual.

PIC32MX3XX/4XX
22.3.15 500 KSPS CONFIGURATION 22.3.15.1 500 ksps Configuration Procedure
GUIDELINE The following configuration items are required to
The configuration for 500 ksps operation is dependent achieve a 500 ksps conversion rate.
on whether a single input pin or multiple pins will be • Connect external VREF+ and VREF- pins following
sampled. the recommended circuit shown in Figure 22-4.
• Set SSRC<2:0> = 111 in the AD1CON1 register
to enable the auto convert option.
• Enable automatic sampling by setting the ASAM
control bit in the AD1CON1 register.
• Configure the ADC clock period by writing an
ADCS value = 2 to the ADCS<5:0> control bits in
the AD1CON3 register. Use the following formula:
FIGURE 22-3: 500 KSPS SAMPLE RATE CALCULATIONS
System clock of 80MHz and PBDIV = 2
TPB = ⎛ ------------------⎞ • 2 = 25ns

1
⎝ 80MHz⎠
1
--------- ksps = 2us period
500
Calculate number clocks required:

sample clocks = 2 (See Table 22-3)
therefore SAMPC = 1
convert = 12 ADC clock periods (See
Section 22.2.1)
sample clocks + convert clocks = adclks = 14
Calculate ADC clock period:

2us = 143ns = TAD (ADC clock period)
---------
14
143ns
------------------------ = 5.71 (Desired ADC clock divisor)
⎛ -----------------
1 ⎞
-
⎝ 40MHz⎠
Calculate desired ADCS value from result

5.71 = ( ADCS + 1 ) • 2 results in 1.85
closest higher value = 2
closest lower value 1
Calculate Actual sample rate:

ADC Clock divisor • adclks • TPB
Using ADCS = 1:
1
--------------------------------------------------------------------------------- = 714ksps
( ( ( ADCS + 1 ) • 2 ) • 14 ) • 25ns )
(exceeds device specifications)
Using ADCS = 2: results = 476 ksps

Conclusion: Select ADCS of 2
• Configure the sampling time to be 2 TAD by

writing: SAMC<4:0> = 00010.

PIC32MX3XX/4XX
FIGURE 22-4: CONVERTING 1 CHANNEL AT 400 KSPS, AUTO-SAMPLE START, 2 TAD
SAMPLING TIME
TSAMP TSAMP
= 2 TAD = 2 TAD
ADCLK
TCONV TCONV
= 12 TAD = 12 TAD
SAMP
DONE
ADC1BUF0
ADC1BUF1
Instruction Execution SET AD1CON1,ASAM
22.4 Miscellaneous ADC Functions 22.4.4 OFFSET CALIBRATION

The following section describes bits not covered in the The ADC module provides a method of measuring the
previous section. internal offset error. After this offset error is measured,
it can be subtracted, in software, from the result of an
22.4.1 Aborting Sampling A/D conversion. Use the following steps to perform an
offset measurement:
Clearing the SAMP (AD1CON1<1>) bit while in Manual
Sample mode will terminate sampling, but may also 1. Configure the A/D converter in the same manner
start a conversion if SSRC (AD1CON1<7:5>) = 000. as it will be used in the application.
Clearing the ASAM (AD1CON1<2>) bit while in Auto- 2. Set the OFFCAL bit (AD1CON2<12>). This
Sample mode will not terminate an ongoing overrides the input selections and connects the
acquire/convert sequence, however, sampling will not sample and hold inputs to AVss.
automatically resume after the current sample is 3. If auto-sample is used set the CLRASAM bit
converted. (AD1CON1<4>) to force conversions.
4. Enable the A/D converter and perform a conver-
22.4.2 ABORTING A CONVERSION
sion. The result that is written to the ADC result
Clearing the ON (AD1CON1<15>) bit during a conver- buffer is the internal offset error.
sion will abort the current conversion. The ADC Result 5. Clear the OFFCAL (AD2CON<12>) bit to return
register will NOT be updated with the partially com- the A/D converter to normal operation.
pleted A/D conversion sample. That is, the correspond-
ing result buffer location will continue to contain the Note: Only positive ADC offsets can be
value of the last completed conversion (or the last measured with this method.
value written to the buffer).
22.4.3 BUFFER FILL STATUS

When the conversion result buffer is split using the
BUFM control bit, the BUFS Status bit (AD1CON2<7>)
indicates which half of the buffer the A/D converter is
currently filling. If BUFS = 0, then the A/D converter is
filling ADC1BUF0-ADC1BUF7 and the user software
should read conversion values from ADC1BUF8-
ADC1BUFF. If BUFS = 1, the situation is reversed and
the user software should read conversion values from
ADC1BUF0-ADC1BUF7.

PIC32MX3XX/4XX
22.4.5 TERMINATE CONVERSION
SEQUENCE AFTER AN INTERRUPT
The CLRASAM bit provides a method to terminate
auto-sample after the first sequence is completed. Set-
ting the CLRASAM and starting an auto-sample
sequence will cause the A/D converter to complete one
auto-sample sequence (the number of samples as
defined by SMPI<3:0> (AD1CON2<5:2>)). Hardware
will clear ASAM (AD1CON1<2>) and set the interrupt
flag. This will stop the sampling process to allow
inspection of the result buffer without results being
overwritten by the next automatic conversion
sequence. The CLRASAM must be cleared by software
to disable this mode.
Note: Disabling interrupts or masking the ADC

interrupt has no effect on the operation
of the CLRASAM bit.
22.4.6 CONVERSION SEQUENCE

EXAMPLES
The following configuration examples show the ADC
operation in different sampling and buffering configura-
tions. In each example, setting the ASAM bit starts
automatic sampling. A conversion trigger ends sam-
pling and starts conversion.
22.4.7 MANUAL CONVERSION CONTROL

When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit
(AD1CON1<1>) starts the conversion sequence. See
Example 22-1 for sample code to manually control the
sampling of a single channel.
EXAMPLE 22-1: CONVERTING 1 CHANNEL, MANUAL SAMPLE START, MANUAL CONVERSION

START CODE
AD1PCFG = ~(1 << 5); // PORTB = Digital; RB5 = analog
AD1CON1 = 0x0000; // SAMP bit = 0 ends sampling ...
// and starts converting
AD1CHS = 5 << 16; // Connect RB5/AN5 as CH0 input ..
AD1CSSL = 0;
AD1CON3 = 0x0002; // Manual Sample, Tad = 6 TPB
AD1CON2 = 0;
AD1CON1SET = 0x8000; // turn ADC ON
while (1) // repeat continuously
{
AD1CON1SET = 0x0002; // start sampling ...
DelayNmSec(100); // for 100 mS
AD1CON1CLR = 0x0002; // start Converting
while (!(AD1CON1 & 0x0001)); // conversion done?
ADCValue = ADC1BUF0; // yes then get ADC value
}

PIC32MX3XX/4XX
22.4.8 AUTOMATIC ACQUISITION
Automatic acquisition control is enabled by setting the
ASAM (AD1CON1<2>) bit. Setting the ASAM bit initi-
ates automatic acquisition, and clearing the SAMP
(AD1CON1<1>) bit terminates sampling and starts
conversion. After the conversion completes, the mod-
ule will automatically return to an acquisition state. The
SAMP bit is automatically set at the start of the acquisi-
tion interval. The user software must time the clearing
of the SAMP bit to ensure adequate acquisition time of
the input signal, understanding that the time between
clearing of the SAMP bit includes the conversion time
as well as the acquisition time. See Example 22-2 for a
code example.
EXAMPLE 22-2: CONVERTING 1 CHANNEL, AUTOMATIC SAMPLE START, MANUAL

CONVERSION START CODE
AD1PCFG = ~(1 << 5); // all PORTB = Digital but RB5 = analog
AD1CON1 = 0x0004; // ASAM bit = 1 implies acquisition ..
// starts immediately after last conversion is done
AD1CHS = 5 << 16; // Connect RB5/AN5 as CH0 input
AD1CSSL = 0;
AD1CON2 = 0;
AD1CON3 = 0x0002; // Sample time manual, Tad = 6 TPB
{
DelayNmSec(100); // sample for 100 mS
AD1CON1CLR = 0x0002; // start Converting
} // repeat
22.4.9 CLOCKED CONVERSION TRIGGER

When SSRC<2:0> = 111, the conversion trigger is
under ADC clock control. The SAMC bits
(AD1CON3<4:0>) select the number of TAD clock
cycles between the start of acquisition and the start of
conversion. This trigger option provides the fastest
conversion rates on multiple channels. After the start of
acquisition, the module will count a number of TAD
clocks specified by the SAMC bits.
EQUATION 22-1: CLOCKED CONVERSION

TRIGGER TIME
TSMP = SAMC<4:0>* TAD
SAMC must always be programmed for at least one

clock cycle. See Example 22-3 for a code example.

PIC32MX3XX/4XX
EXAMPLE 22-3: CONVERTING 1 CHANNEL, MANUAL SAMPLE START, TAD-BASED
CONVERSION START CODE
AD1CON1 = 0x00E0; // SSRC bit = 111 implies internal
// counter ends sampling and starts converting.
AD1CSSL = 0;
AD1CON3 = 0x1F02; // Sample time = 31Tad
AD1CON2 = 0;
{
AD1CON1SET = 0x0002; // start sampling then
// after 31Tad go to conversion
} // repeat

PIC32MX3XX/4XX
22.4.10 Free-Running Sample
Conversion Sequence
The Auto-Convert Conversion Trigger mode
(SSRC = 111) in combination with the Automatic Sam-
pling Start mode (ASAM = 1), allows the ADC module
to schedule acquisition/conversion sequences with no
intervention by the user or other device resources. This
“Clocked” mode allows continuous data collection after
module initialization. See Example 22-4 for a code
example.
EXAMPLE 22-4: CONVERTING 1 CHANNEL, AUTO-SAMPLE START, AUTO-CONVERT CODE
AD1CON1 = 0x00E0; // SSRC bit = 111 internal
// counter ends sampling and starts
// converting.
// in this example RB2/AN2 is the input
AD1CSSL = 0;
AD1CON3 = 0x0F00; // Sample time = 15 Tad
AD1CON2 = 0x0004; // Interrupt after every 2 samples
AD1CON1SET = 0x0004; // auto start sampling
{
while (!IFS1 & 0x0002); // poll for interrupt

// flag for conversion done
IFS1CLR = 0x0002; // clear ADC interrupt flag
// result of conversions is available in ADC1BUF0
// and ADC1BUF1
}
22.4.11 SAMPLING A SINGLE CHANNEL 22.4.12 EXAMPLE: A/D CONVERSIONS

MULTIPLE TIMES WHILE SCANNING THROUGH
In this case, one ADC input, AN0, will be acquired and ANALOG INPUTS
converted. The results are stored in the ADC1BUF buf- A typical setup might include all available analog input
fer. This process repeats 15 times until the buffer is full, channels to be sampled and converted. The CSCNA
and then the module generates an interrupt. Then (AD1CON2<10>) bit specifies scanning of the ADC
entire process repeats. inputs. Other conditions are similar to the previous
With ALTS (AD1CON2<0>) clear, only the MUX A example (see Section 22.4.11 “Sampling a Single
inputs are active. The CH0SA (AD1CHS<19:16>) bits Channel Multiple Times”).
and CH0NA (AD1CHS<23>) bit are specified (AN0- Initially, the AN0 input is acquired and converted. The
VREF-) as the input to the sample/hold channel. Other result is stored in the ADC1BUF buffer. Then the AN1
input selection bits are not used. input is acquired and converted. This process of scan-
ning the inputs repeats 16 times until the buffer is full
and then the module generates an interrupt. Then the
entire process repeats.

PIC32MX3XX/4XX
22.4.12.1 Example: Using Dual 8-Word Buffers 22.5 Initialization
To enable the dual 8-word buffers and alternating the A simple initialization code example for the ADC
buffer fill, set the BUFM (AD1CON2<1>) bit. The BUFM module is provided in Example 22-5.
setting does not affect other operational parameters.
First, the conversion sequence starts filling the buffer at In this particular configuration, all 16 analog input pins,
ADC1BUF0 (buffer location 0 x 0). After the first inter- AN0-AN15, are set up as analog inputs. Operation in
rupt occurs, the buffer begins to fill at ADC1BUF8 (buf- IDLE mode is disabled, output data is in unsigned frac-
fer location 0 x 8). The BUFS (AD1CON2<7>) bit is tional format, and AVDD and AVSS are used for VR+ and
alternately set and cleared after each interrupt to show VR-. The start of acquisition, as well as start of conver-
which buffer is being filled. In this example, three ana- sion (conversion trigger), are performed manually in
log inputs are sampled and an interrupt occurs after software. The CH0 SHA is used for conversions. Scan-
every third sample. ning of inputs is disabled, and an interrupt occurs after
every acquisition/convert sequence (1 conversion
22.4.12.2 Example: Using Alternating MUX A, result). The ADC conversion clock is TPB/2.
MUX B Input Selections Since acquisition is started manually by setting the
Setting the ALTS (AD1CON2<0>) bit enables alternat- SAMP bit (AD1CON1<1>) after each conversion is
ing input selections. The first sample uses the MUX A complete, the auto-sample time bits, SAMC<4:0>
inputs specified by the CH0SA (AD1CHS<19:16>) and (AD1CON3<12:8>), are ignored. Moreover, since the
CH0NA (AD1CHS<23>) bits. The next sample uses the start of conversion (i.e., end of acquisition) is also trig-
MUX B inputs specified by the CH0SB gered manually, the SAMP bit needs to be cleared
(AD1CHS<27:24>) and CH0NB (AD1CHS<31>) bits. each time a new sample needs to be converted.
In the following example, one of the MUX B input

specifications uses 2 analog inputs as a differential
source to the sample/hold.
This example also demonstrates use of the dual 8-word
buffers. An interrupt occurs after every 4th sample,
which results in filling 4-words into the buffer on each
interrupt.
22.4.12.3 Example: Converting Three Analog

Inputs Using Alternating Sample
Mode and a Scan List
It is possible to sample by scanning through the input
channels and alternate between MUX A and MUX B.
When the Alternating Sample mode is selected, the
first input to be sampled will be the input selected for
MUX A, the second sample will be the input selected
for MUX B. Then the process repeats. When scanning
is combined with Alternating Input mode, the positive
input to MUX A is selected by the contents of the
AD1CSSL register, not CH0SA. For each sample that
MUX A is selected the next item in the scan list is sam-
pled. The positive input to MUX B is selected by
CH0SB (AD1CHS<27:24>).
When ASAM (AD1CON1<2>) is clear, sampling will not
resume after conversion completion, but will occur
when setting the SAMP (AD1CON1<1>) bit.

PIC32MX3XX/4XX
EXAMPLE 22-5: ADC INITIALIZATION CODE EXAMPLE
void __ISR(_ADC_VECTOR, ipl7) ADC_HANDLER(void)
{
// interrupt handler
unsigned long int result;
result = ADC1BUF0; // read the result

IFS1CLR = 2; // Clear ADC conversion interrupt flag
}
int main(void)
{
AD1PCFG = ~(1 << 5); // Configure RB5 as an analog input
AD1CON1 = (7 << 5) | 4; //Configure sample clock source and Trigger mode

// integer format, automatic conversion trigger,
// automatic start of sampling, No operation in IDLE mode.
AD1CON2 = 0x0000; // Configure ADC voltage reference

// and buffer fill modes.
// VREF from AVDD and AVSS,Inputs are not scanned,
// Interrupt every sample
AD1CON3 = (31 << 8) | 0xFF; // Configure ADC conversion clock

// sample for 31 TAD, TAD = Tpb / 512
AD1CHS = 5 << 16; // Configure input channels,

// CH0+ input is AN0. CHO- input is VREFL (AVss)
AD1CSSL = 0x0000; // No inputs are scanned.

// Note: Contents of AD1CSSL are ignored when CSCNA = 0
IPC6CLR = 0x1F << 24; // clear the ADC interrupt priority bits
IPC6SET = (0x07 << 26) | (1 << 24);
// Configure ADC interrupt priority bits
// priority = 3, sub-priority = 1
INTEnableSystemMultiVectoredInt(); // enable system interrupts

IFS1CLR = 2; // Clear ADC conversion interrupt
IEC1SET = 2; // Enable ADC conversion interrupt
AD1CON1SET = 0x8000; // Turn on the ADC module
while(1) {}
} // main

PIC32MX3XX/4XX
The pins used for analog input can also be used for dig-
ital I/O. Configuring a pin for analog input requires three
steps. Any digital peripherals that share the desired pin
must be disabled. The pin must be configured as a dig-
ital input, by setting the corresponding TRIS bit to a ‘1’
to disable the output driver. Then, the pin must be
placed in Analog mode by setting the corresponding bit
in the AD1PCFG register.
TABLE 22-3: PINS ASSOCIATED WITH THE ADC MODULE
Module Pin Buffer
Pin Name Controlling Bit Field TRIS Description
Control Type Type
AN0 ON AD1PCFG<0> A — Input Analog Input
VREF+ ON AD1CON2<15:13> P — — Positive Voltage Reference
VREF- ON AD1CON2<15:13> P — — Negative Voltage Reference
Legend: ST = Schmitt Trigger input with CMOS levels A = Analog
I = Input P = Power
O = Output

PIC32MX3XX/4XX
Figure 22-5: A/D Converter Voltage Reference Schematic
10 μF
VDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDD 1 75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
VDD 9 67
10 66
10K 11 65
12 64
VDD
13 63
14 62
VDD 15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
AVDD
25 51
R2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
10
VDD VDD
C2 C1 R1 AVSS
0.1 μF 0.01 μF 10
AVDD
AVSS AVSS
VDD VDD VDD
AVSS
C8 C7 C6
1 μF 0.1 μF 0.01 μF
VDD VDD VDD
C5 C4 C3
1 μF 0.1 μF 0.01 μF

PIC32MX3XX/4XX
22.6.1 ADC CONVERSION SPEEDS
The PIC32MX 10-bit A/D converter specifications per-
mit a maximum 500 ksps sampling rate. Table 22-4
summarizes the conversion speeds for the PIC32MX
10-bit A/D converter and the required operating
conditions.
TABLE 22-4: 10-BIT CONVERSION RATE PARAMETERS

PIC32MX 10-bit A/D Converter Conversion Rates
TAD Sampling
ADC Speed RS Max VDD Temperature ADC Channels Configuration
Minimum Time Min
500 ksps(1) 100 nsec 2 TAD 500Ω 3.0V to 3.6V -40°C to +85°C
VREF- VREF+
CHX
ANx
SHA ADC
Up to 400 200 nsec 1 TAD 5.0 kΩ 2.5V to 3.6V -40°C to +125°C

ksps VREF- VREF+
or or
AVSS AVDD
ANx CHX
SHA ADC
ANx or VREF-
Up to 300 256.41 nsec 1 TAD 5.0 kΩ 2.5V to 3.6V -40°C to +125°C

ksps VREF- VREF+
or or
AVSS AVDD
ANx CHX
SHA ADC
ANx or VREF-
Note 1: External VREF- and VREF+ pins must be used for correct operation.

PIC32MX3XX/4XX
22.6.2 ADC SAMPLING REQUIREMENTS within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D con-
The analog input model of the 10-bit A/D converter is
verter, the maximum recommended source imped-
shown in Figure 22-6. The total acquisition time for the
ance, RS, is 5 kΩ for the conversion rates of up to 400
A/D conversion is a function of the internal amplifier
ksps and a maximum of 500Ω for conversion rates of
settling time and the holding capacitor charge time.
up to 500 ksps). After the analog input channel is
For the A/D converter to meet its specified accuracy, selected (changed), this acquisition function must be
the charge holding capacitor (CHOLD) must be allowed completed prior to starting the conversion. The internal
to fully charge to the voltage level on the analog input holding capacitor will be in a discharged state prior to
pin. The analog output source impedance (RS), the each sample operation.
interconnect impedance (RIC) and the internal sam-
At least 1 TAD time period should be allowed between
pling switch (RSS) impedance combine to directly affect
conversions for the acquisition time. For more details,
the time required to charge the CHOLD. The combined
see the device electrical specifications.
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
FIGURE 22-6: 10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD RIC ≤ 250Ω RSS ≤ 3 kΩ

Sampling
Switch
VT = 0.6V
Rs ANx RSS
CHOLD
VA CPIN ILEAKAGE = DAC Capacitance
VT = 0.6V ± 500 nA = 4.4 pF
VSS
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
Legend
CPIN = input capacitance VT = threshold voltage
RSS = sampling switch resistance RIC = interconnect resistance
RS = source resistance CHOLD = sample/hold capacitance (from DAC)
ILEAKAGE = leakage current at the pin due to various junctions

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
23.0 POWER SAVING 23.2 CPU Halted Methods
Note: This data sheet summarizes the features of The device supports two power-saving modes, SLEEP
the PIC32MX3XX/4XX family of devices. It and IDLE, both of which halt the clock to the CPU.
is not intended to be a comprehensive refer- These modes operate with all clock sources, as listed
ence source. Refer to the “PIC32MX Family below:
Reference Manual” (DS61132) for a • POSC IDLE Mode: the system clock is derived
detailed description of this peripheral. from the POSC. The system clock source
continues to operate.
This section describes power saving for the
Peripherals continue to operate, but can
PIC32MX3XX/4XX. The PIC32MX devices offer a total
optionally be individually disabled.
of nine methods and modes that are organized into two
categories that allow the user to balance power con- • FRC IDLE Mode: the system clock is derived from
sumption with device performance. In all of the meth- the FRC with or without postscalers.
ods and modes described in this section, power saving Peripherals continue to operate, but can option-
is controlled by software. ally be individually disabled.
• SOSC IDLE Mode: the system clock is derived
23.1 Power Saving with CPU Running from the SOSC.
Peripherals continue to operate, but can
When the CPU is running, power consumption can be
optionally be individually disabled.
controlled by reducing the CPU clock frequency, lower-
ing the PBCLK, and by individually disabling modules. • LPRC IDLE Mode: the system clock is derived from
These methods are grouped into the following catego- the LPRC.
ries: Peripherals continue to operate, but can option-
ally be individually disabled. This is the lowest
• FRC RUN mode: the CPU is clocked from the FRC
power mode for the device with a clock running.
clock source with or without postscalers.
• SLEEP Mode: the CPU, the system clock source,
• LPRC RUN mode: the CPU is clocked from the
and any peripherals that operate from the system
LPRC clock source.
clock source, are halted.
• SOSC RUN mode: the CPU is clocked from the
Some peripherals can operate in SLEEP using
SOSC clock source.
specific clock sources. This is the lowest power
• Peripheral Bus Scaling mode: mode for the device.
Peripherals are clocked at programmable fraction
of the CPU clock (SYSCLK).

PIC32MX3XX/4XX
23.3 Power-Saving Modes Control
Registers
Power-Saving modes control consists of the following
Special Function Registers (SFRs):
• OSCCON: Control Register for the Oscillators
Module
OSCCONCLR, OSCCONSET, OSCCONINV:
Atomic Bit Manipulation Write-only Registers for
OSCCON
• WDTCON: Control Register for the Watchdog
Timer Module
WDTCONCLR, WDTCONSET, WDTCONINV:
Atomic Bit Manipulation Write-only Registers
for WDTCON
• RCON: Control Register for the Resets Module
RCONCLR, RCONSET, RCONINV: Atomic Bit
Manipulation Write-only Registers for RCON
The following table summarizes Power-Saving modes
registers. Corresponding registers appear after the
summary, followed by a detailed description of each
register.
TABLE 23-1: POWER-SAVING MODES SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_F000 OSCCON 31:24 — — PLLODIV<2:0> RCDIV<2:0>
23:16 — SOSCRDY — PBDIV<1:0> PLLMULT<2:0>
15:8 — COSC<2:0> — NOSC<2:0>
7:0 CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN
BF80_F004 OSCCONCLR 31:0 Write clears selected bits in OSCCON, read yields undefined value
BF80_F008 OSCCONSET 31:0 Write sets selected bits in OSCCON, read yields undefined value
BF80_F00C OSCCONINV 31:0 Write inverts selected bits in OSCCON, read yields undefined value
BF80_0000 WDTCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON — — — — — — —
7:0 — SWDTPS<4:0> — WDTCLR
BF80_0004 WDTCONCLR 31:0 Write clears selected bits in WDTCON; read yields undefined value
BF80_0008 WDTCONSET 31:0 Write sets selected bits in WDTCON; read yields undefined value
BF80_000C WDTCONINV 31:0 Write inverts selected bits in WDTCON; read yields undefined value
BF80_F600 RCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — CM VREGS
BF80_F604 RCONCLR 31:0 Write clears selected bits in RCON; read yields undefined value
BF80_F608 RCONSET 31:0 Write sets selected bits in RCON; read yields undefined value
BF80_F60C RCONINV 31:0 Write inverts selected bits in RCON; read yields undefined value

PIC32MX3XX/4XX
r-x r-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1
— — PLLODIV<2:0> FRCDIV<2:0>
bit 31 bit 24
r-0 R-0 r-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SOSCRDY — PBDIV<1:0> PLLMULT<2:0>
bit 23 bit 16
r-x R-0 R-0 R-0 r-x R/W-x R/W-x R/W-x

— COSC<2:0> — NOSC<2:0>
bit 15 bit 8
R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN
bit 7 bit 0
Legend:
bit 29-27 PLLODIV<2:0>: Output Divider for PLL

Note: On Reset these bits are set to the value of the FPLLODIV configuration bits
(DEVCFG2<18:16>)
bit 26-24 FRCDIV<2:0>: Fast Internal RC Clock Divider bits
001 = FRC divided by 2 (default setting)
bit 23 Reserved: Write ‘0’
bit 22 SOSCRDY: Secondary Oscillator Ready Indicator bit
1 = Indicates that the Secondary Oscillator is running and is stable
0 = Secondary oscillator is either turned off or is still warming up
bit 20-19 PBDIV<1:0>: Peripheral Bus Clock Divisor
11 = PBCLK is SYSCLK divided by 8 (default)
Note: On Reset these bits are set to the value of the FPBDIV Configuration bits DEVCFG1<13:12>

PIC32MX3XX/4XX
REGISTER 23-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 18-16 PLLMULT<2:0>: PLL Multiplier bits
Note: On Reset these bits are set to the value of the FPLLMULT Configuration bits
(DEVCFG2<6:4>).
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
001 = Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
001 = Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Fast Internal RC Oscillator (FRC)
bit 7 CLKLOCK: Clock Selection Lock Enable bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked.
0 = Clock and PLL selections are not locked and may be modified
If FSCM is disabled (FCKSM1 = 0):
Note: Clock and PLL selections are never locked and may be modified.
bit 6 ULOCK: USB PLL Lock Status bit
1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress
or USB PLL is disabled
bit 5 LOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM (Fail Safe Clock Monitor) has detected a clock failure
0 = No clock failure has been detected

PIC32MX3XX/4XX
REGISTER 23-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 2 UFRCEN: USB FRC Clock Enable bit
1 = Enable FRC as the clock source for the USB clock source
0 = Use the primary oscillator or USB PLL as the USB clock source
bit 1 SOSCEN: 32.768 kHz Secondary Oscillator (SOSC) Enable bit
Note: On Reset these bits are set to the value of the FSOSCEN Configuration bit DEVCFG1<5>
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to selection specified by NOSC2:NOSC0 bits
0 = Oscillator switch is complete

PIC32MX3XX/4XX
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

ON — — — — — — —
bit 15 bit 8
r-x R-0 R-0 R-0 R-0 R-0 r-0 R/W-0

— SWDTPS<4:0> — WDTCLR
bit 7 bit 0
Legend:
bit 15 ON: Watchdog Peripheral On bit

1 = Watchdog peripheral is enabled. The status of other bits in the register are not affected by setting
this bit. The LPRC oscillator will not be disabled when entering Sleep.
0 = Watchdog peripheral is disabled and not drawing current. SFR modifications are allowed. The
status of other bits in this register are not affected by clearing this bit.

PIC32MX3XX/4XX
REGISTER 23-3: RCON: RESETS CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
r-x r-x r-x r-x r-x r-0 R/W-0 R/W-0

— — — — — — CM VREGS
bit 15 bit 8

bit 7 bit 0
Legend:
bit 3 SLEEP: Wake from Sleep bit

1 = The device woke up from SLEEP mode
0 = The device did not wake from SLEEP mode
Note: Must clear this bit to detect future wake-ups from SLEEP.
bit 2 IDLE: Wake from IDLE bit
1 = The device woke up from IDLE mode
0 = The device did not wake from IDLE mode
Note: Must clear this bit to detect future wake-ups from IDLE.

PIC32MX3XX/4XX
23.4 Power-Saving Operation 23.5 SLEEP Mode
Note: In this data sheet, a distinction is made SLEEP mode has the lowest power consumption of
between a power mode as it is used in a the device Power-Saving operating modes. The CPU
specific module, and a power mode as it is and most peripherals are halted. Select peripherals
used by the device, e.g., Sleep mode of can continue to operate in SLEEP mode and can be
the Comparator and SLEEP mode of the used to wake the device from SLEEP. See the individ-
CPU. To indicate which type of power ual peripheral module sections for descriptions of
mode is intended, uppercase and lower- behavior in Sleep.
case letters (Sleep, Idle, Debug) signify a SLEEP mode includes the following characteristics:
module power mode, and all uppercase
• The CPU is halted.
letters (SLEEP, IDLE, DEBUG) signify a
device power mode. • The system clock source is typically shut down.
See Section 23.5.1 “Oscillator Shutdown In
The purpose of all power saving is to reduce power Sleep Mode” for specific information.
consumption by reducing the device clock frequency. • There can be a wake-up delay based on the
To achieve this, low-frequency clock sources can be oscillator selection (refer to Table 23-2).
selected. In addition, the peripherals and CPU can be
• The Fail-Safe Clock Monitor (FSCM) does not
halted or disabled to further reduce power consump-
operate during Sleep mode.
tion.
• The BOR circuit, if enabled, remains operative
during SLEEP mode.
• The WDT, if enabled, is not automatically cleared
prior to entering SLEEP mode.
• Some peripherals can continue to operate in
SLEEP mode. These peripherals include I/O pins
that detect a change in the input signal, WDT,
ADC, UART, and peripherals that use an external
clock input or the internal LPRC oscillator, e.g.,
RTCC and Timer 1.
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
SLEEP.
• The USB module can override the disabling of the
POSC or FRC. Refer to the USB section for spe-
cific details.
• Some modules can be individually disabled by
software prior to entering SLEEP in order to fur-
ther reduce consumption.
The processor will exit, or ‘wake-up’, from SLEEP on

one of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset.
• On a WDT time-out. See Section 23.10 “Wake-
Up from SLEEP or IDLE on Watchdog Time-
Out (NMI)”.
If the interrupt priority is lower than or equal to current
priority, the CPU will remain halted, but the PBCLK will
start running and the device will enter into IDLE mode.
Refer Example 23-1 for example code.
Note: There is no FRZ mode for this module.

PIC32MX3XX/4XX
23.5.1 OSCILLATOR SHUTDOWN IN 23.5.2 CLOCK SELECTION ON WAKE-UP
SLEEP MODE FROM SLEEP
The criteria for the device disabling the clock source in The processor will resume code execution and use the
SLEEP are: the oscillator type, peripherals using the same clock source that was active when SLEEP mode
clock source, and (for select sources) the clock enable was entered. The device is subject to a start-up delay if
bit. a crystal oscillator and/or PLL is used as a clock source
• If the CPU clock source is POSC, it is turned off in when the device exits SLEEP.
SLEEP. See Table 23-2 for applicable delays
23.5.3 DELAY ON WAKE-UP FROM SLEEP
when waking from SLEEP. The USB module can
override the disabling of the POSC or FRC. Refer The oscillator start-up and Fail-Safe Clock Monitor
to the USB section for specific details. delays (if enabled) associated with waking up from
• If the CPU clock source is FRC, it is turned off in SLEEP mode are shown in Table 23-2.
SLEEP. See Table 23-2 for applicable delays
when waking from SLEEP. The USB module can
override the disabling of the POSC or FRC. Refer
to the USB section for specific details.
• If the CPU clock source is SOSC, it will be turned
off if the SOSCEN bit is not set. See Table 23-2
for applicable delays when waking from SLEEP.
• If the CPU clock source is LPRC, it will be turned
off if the clock source is not being used by a
peripheral that will be operating in SLEEP, such
as the WDT. See Table 23-2 for applicable delays
when waking from SLEEP.
TABLE 23-2: DELAY TIMES FOR EXIT FROM SLEEP MODE

Oscillator
Clock Source FSCM Delay
Delay
EC, EXTRC — —
EC + PLL TLOCK TFSCM
XT + PLL TOST + TLOCK TFSCM
XT, HS, XTL TOST TFSCM
LP (OFF during Sleep) TOST TFSCM
LP (ON during Sleep) — —
FRC, LPRC — —
Note: Refer to Section 30.0 “Electrical Char-

acteristics” for TPOR, TFSCM, and TLOCK
specifications.

PIC32MX3XX/4XX
23.5.4 WAKE-UP FROM SLEEP MODE 23.5.5 FAIL-SAFE CLOCK MONITOR
WITH CRYSTAL OSCILLATOR DELAY AND SLEEP MODE
OR PLL The Fail-Safe Clock Monitor (FSCM) does not operate
If the system clock source is derived from a crystal while the device is in SLEEP. If the FSCM is enabled it
oscillator and/or the PLL, then the Oscillator Start-up will resume operation when the device wakes from
Timer (OST) and/or PLL lock times will be applied Sleep.
before the system clock source is made available to the
device. As an exception to this rule, no oscillator delays 23.5.6 SLOW OSCILLATOR START-UP
are applied if the system clock source is the POSC When an oscillator starts slowly, the OST and PLL lock
oscillator and it was running while in SLEEP mode. times may not have expired before FSCM times out.
If the FSCM is enabled, then the device will detect this
Note: In spite of the various delays applied the
condition as a clock failure and a clock event trap will
crystal oscillator (and PLL) may not be up
occur. The device will switch to the FRC oscillator and
and running at the end of the TOST, or
the user can re-enable the crystal oscillator source in
TLOCK delays. For proper operation the
the clock failure Interrupt Service Routine.
user must design the external oscillator
circuit such that reliable oscillation will If the FSCM is not enabled, then the device will simply
occur within the delay period. not start executing code until the clock is stable. From
the user’s perspective, the device will appear to be in
SLEEP until the oscillator clock has started.
23.5.6.1 The USB peripheral control of

Oscillators in Sleep mode
For devices with a USB peripheral, POSC and FRC will
remain active in Sleep if the USB module is not dis-
abled prior to entering Sleep. The Oscillators remain-
ing active will not stop the halting of the CPU or
peripherals in Sleep.
EXAMPLE 23-1: PUT DEVICE IN SLEEP, THEN WAKE WITH WDT

// Code example to put the Device in sleep and then Wake the device
// with the WDT
OSCCONSET = 0x10; // set Power-Saving mode to Sleep
WDTCONCLR = 0x0002; // Disable WDT window mode

WDTCONSET = 0x8000; // Enable WDT
// WDT timeout period is set in the device configuration
while (1)
{
... user code ...
WDTCONSET = 0x01; // service the WDT

asm volatile ( “wait” );// put device in selected Power-Saving mode
// code execution will resume here after wake
... user code ...

}
// The following code fragment is at the beginning of the ‘C’ start-up code
if ( RCON & 0x18 )

{
// The WDT caused a wake from Sleep
asm volatile ( “eret” );// return from interrupt
}

PIC32MX3XX/4XX
23.6 Peripheral Bus Scaling Method
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative
to the SYSCLK to minimize the dynamic power con-
sumed by the peripherals. The PBCLK divisor is con-
trolled by PBDIV<1:0> (OSCCON<20:19>), allowing
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All
peripherals using PBCLK are affected when the divisor
is changed. Peripherals such as the Interrupt Control-
ler, DMA, Bus Matrix, and Prefetch Cache are clocked
directly from SYSCLK, as a result, they are not affected
by PBCLK divisor changes.
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative
to the SYSCLK to minimize the dynamic power con-
sumed by the peripherals. The PBCLK divisor is con-
trolled by PBDIV<1:0> (OSCCON<20:19>), allowing
SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All
peripherals using PBCLK are affected when the divisor
is changed. Peripherals such as USB, Interrupt Con-
troller, DMA, Bus Matrix, and Prefetch Cache are
clocked directly from SYSCLK, as a result, they are not
affected by PBCLK divisor changes
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode this results in a latency of
one to seven SYSCLKs.
• The power consumption of the peripherals. Power
consumption is directly proportional to the fre-
quency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock require-
ments such as baud rate accuracy should be taken into
account. For example, the UART peripheral may not be
able to achieve all baud rate values at some PBCLK
divider depending on the SYSCLK value.

PIC32MX3XX/4XX
23.6.1 DYNAMIC PERIPHERAL BUS baud rate will be affected. Care should be taken to
SCALING METHOD ensure that no communication is currently in prog-
ress before disabling the peripherals as it may
The PBCLK can be scaled dynamically, by software, to
result in protocol errors.
save additional power when the device is in a low activ-
ity mode. The following issues need to be taken into • Update the Baud Rate Generator (BRG) settings
account when scaling the PBCLK: for peripherals as required for operation at the
new PBCLK frequency.
• All the peripherals clocked from PBCLK will scale
• Change the peripheral bus ratio to the desired
at the same ratio, at the same time. This needs to
value.
be accounted in peripherals which need to main-
tain a constant baud rate, or pulse period even in • Enable all communication peripherals whose
low-power modes. baud rate were affected.
• Any communication through a peripheral on the
Note: Modifying the peripheral baud rate is done
peripheral bus that is in progress when the
by writing to the associated peripheral
PBCLK changes may cause a data or protocol
SFRs. To minimize latency, the peripher-
error due to a frequency change during
als should be modified in the mode where
transmission or reception.
the PBCLK is running at its highest
The following steps are recommended if the user frequency.
intends to scale the PBCLK divisor dynamically:
• Disable all communication peripherals whose
EXAMPLE 23-2: CHANGING THE PB CLOCK DIVISOR

// Code example to change the PBCLK divisor
// This example is for a device running at 20 MHz
// Make sure that there is no UART send/receive in progress
... user code ...
U1BRG = 0x81; // set baud rate for UART1 for 9600
... user code ...

OSCCONCLR = 0x3 << 19; // set PB divisor to minimum (1:1)
... user code ...

// Change Peripheral Clock value
U1BRG = 0x0F; // set baud rate for UART1 for 9600 based on
// new PB clock frequency

OSCCONSET = 0x3 << 19; // set PB divisor to maximum (1:8)
// Reset Peripheral Clock

OSCCONCLR = 0x3 << 19; // set PB divisor to minimum (1:1)
U1BRG = 0x81; // restore baud rate for UART1 to 9600 based
// on new PB clock frequency

PIC32MX3XX/4XX
23.7 IDLE Modes The device enters IDLE mode when the SLPEN (OSC-
CON<4>) bit is clear and a WAIT instruction is
In the IDLE modes, the CPU is halted but the System executed.
clock (SYSCLK) source is still enabled. This allows
peripherals to continue operation when the CPU is The processor will wake or exit from IDLE mode on the
halted. Peripherals can be individually configured to following events:
halt when entering IDLE by setting their respective • On any interrupt event for which the interrupt
SIDL bit. Latency when exiting Idle mode is very low source is enabled. The priority of the interrupt
due to the CPU oscillator source remaining active. event must be greater than the current priority of
CPU. If the priority of the interrupt event is lower
Notes: Changing the PBCLK divider ratio than or equal to current priority of CPU, the CPU
requires recalculation of peripheral timing. will remain halted and the device will remain in
For example, assume the UART is config- IDLE mode.
ured for 9600 baud with a PB clock ratio of • On any source of device Reset.
1:1 and a POSC of 8 MHz. When the PB • On a WDT time-out interrupt. See Section 23.10
clock divisor of 1:2 is used, the input fre- “Wake-Up from SLEEP or IDLE on Watchdog
quency to the baud clock is cut in half; Time-Out (NMI)” and Section 26.0 “Watchdog
therefore, the baud rate is reduced to 1/2 Timer”.
its former value. Due to numeric truncation
in calculations (such as the baud rate divi-
sor), the actual baud rate may be a tiny
percentage different than expected. For
this reason, any timing calculation
required for a peripheral should be per-
formed with the new PB clock frequency
instead of scaling the previous value
based on a change in PB divisor ratio.
Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering
Sleep in order to save power. No oscilla-
tor start-up delay would be applied when
exiting Idle. However, when switching
back to POSC, the appropriate PLL and
or oscillator startup/lock delays would be
applied.

PIC32MX3XX/4XX
EXAMPLE 23-3: PLACING DEVICE IN IDLE AND WAKING BY ADC EVENT
// Code example to put the Device in Idle and then Wake the device when the ADC completes
// a conversion
OSCCONCLR = 0x10; // set Power-Saving mode to Idle
asm volatile ( “wait” ); // put device in selected Power-Saving mode

// code execution will resume here after wake and the ISR is complete
... user code ...
void __ISR(_ADC_VECTOR, ipl7) ADC_HANDLER(void)
{
unsigned long int result;
result = ADC1BUF0; // read the result

IFS1CLR = 2; // Clear ADC conversion interrupt flag
}
23.8 Interrupts Notes: A peripheral with an interrupt priority set-

There are two sources of interrupts that will wake the ting of zero cannot wake the device.
device from a Power-Saving mode: peripheral inter- Any applicable oscillator start-up delays
rupts, and a Non-Maskable Interrupt (NMI) generated are applied before the CPU resumes
by the WDT in Power-Saving mode. code execution.
23.9 Wake-Up from SLEEP or IDLE on

Peripheral Interrupt
Any source of interrupt that is individually enabled
using the corresponding IE control bit in the IECx reg-
ister and is operational in the current Power-Saving
mode will be able to wake-up the processor from
SLEEP or IDLE mode. When the device wakes, one of
two events will occur, based on the interrupt priority:
• If the assigned priority for the interrupt is less
than, or equal to, the current CPU priority, the
CPU will remain halted and the device enters, or
remains in, IDLE mode.
• If the assigned priority level for the interrupt
source is greater than the current CPU priority,
the device will wake-up and the CPU will jump to
the corresponding interrupt vector. Upon
completion of the ISR, the CPU will start
executing the next instruction after WAIT.
The IDLE Status bit (RCON<2>) is set upon wake-up
from IDLE mode. The SLEEP Status bit (RCON<3>) is
set upon wake-up from SLEEP mode.

PIC32MX3XX/4XX
23.10 Wake-Up from SLEEP or IDLE on 23.11 Interrupts Coincident with
Watchdog Time-Out (NMI) Power-Saving Instruction
When the WDT times out in SLEEP or IDLE mode, an Any peripheral interrupt that coincides with the execu-
NMI is generated. The NMI causes the CPU code exe- tion of a WAIT instruction will be held off until entry into
cution to jump to the device Reset vector. Although the SLEEP or IDLE mode has completed. The device will
CPU executes the Reset vector, it is not a device then wake-up from SLEEP or IDLE mode.
Reset, peripherals and most CPU registers do not
change their states. 23.12 I/O Pins Associated with
Power-Saving Modes
Note: Any applicable oscillator start-up delays
are applied before the CPU resumes code No device pins are associated with Power-Saving
execution. modes.
To detect a wake from a Power-Saving mode caused
by WDT expiration, the WDTO (RCON<4>), SLEEP
(RCON<3>), and IDLE (RCON<2>) bits must be
tested. If the WDTO bit is ‘1’ the event was due to a
WDT time-out. The SLEEP and IDLE bits can then be
tested to determine if the WDT event occurred in Sleep
or Idle.
To use a WDT time-out during SLEEP mode as a wake-
up interrupt, a return from interrupt (ERET) instruction
must be used in the start-up code after the event was
determined to be a WDT wake-up. This will cause code
execution to continue from the instruction following the
WAIT instruction that put the device in Power-Saving
mode.
Note: If a peripheral interrupt and WDT event

occur simultaneously, or in close proxim-
ity, the NMI may not occur, due to the
device being awakened by the peripheral
interrupt. To avoid unexpected WDT
Reset in this scenario, the WDT is auto-
matically cleared when the device
awakens.
See Section 26.0 “Watchdog Timer” for detailed
information on the WDT operation.

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
24.0 COMPARATOR Following are some of the key features of this module:
• Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
is not intended to be a comprehensive refer- - On-chip internal absolute voltage reference
ence source. Refer to the “PIC32MX Family (IVREF)
Reference Manual” (DS61132) for a - Comparator voltage reference (CVREF)
detailed description of this peripheral. • Outputs can be inverted
• Selectable interrupt generation
The PIC32MX3XX/4XX Analog Comparator module
contains one or more comparator(s) that can be config- A block diagram of the comparator module is shown in
ured in a variety of ways. Figure 24-1.
FIGURE 24-1: COMPARATOR BLOCK DIAGRAM
Comparator 1
CREF COUT (CM1CON)

ON C1OUT (CMSTAT)
CPOL
C1IN+(2)
CVREF(3)
C1OUT
CCH<1:0> C1
C1IN-
COE
C1IN+
C2IN+
IVREF(3)
Comparator 2
CREF COUT (CM2CON)

ON C2OUT (CMSTAT)
CPOL
C2IN+
CVREF(3)
C2OUT
CCH<1:0> C2
C2IN-
COE
C2IN+
C1IN+
IVREF(3)
Note 1: IVref is the internal 1.2V reference.

2: On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not
available as a comparator input.
3: Internally connected.

PIC32MX3XX/4XX
24.1 Comparator Control Registers Table 24-1 provides brief summaries of all comparator
related registers. Corresponding registers appear after
Note: Each PIC32MX device variant may have the summary, followed by a detailed description of each
one or more Comparator modules. An ‘x’ register.
used in the names of pins, control/status
bits and registers denotes the particular
module. Refer to the specific device data
sheets for more details.
A Comparator module consists of the following Special
• CMxCON: Comparator Control Register
• CMxCONCLR, CMxCONSET, CMxCONINV:
Atomic Bit Manipulation Registers for CMxCON
• CMSTAT: Comparator Status Registers
• CMSTATCLR, CMSTATSET, CMSTATINV: Atomic
Bit Manipulation Registers for CMSTAT
The comparator module also has the following interrupt
control registers:
• IFS1: Interrupt Flag Status Register
• IEC: Interrupt Enable Control Register
• IPC7: Interrupt Priority Control Register
TABLE 24-1: COMPARATOR SFRS SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_A000 CM1CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON COE CPOL — — — — COUT
7:0 EVPOL<1:0> — CREF — — CCH<1:0>
BF80_A004 CM1CONCLR 31:0 Write clears selected bits in CM1CON, read yields undefined value
BF80_A008 CM1CONSET 31:0 Write sets selected bits in CM1CON, read yields undefined value
BF80_A00C CM1CONINV 31:0 Write inverts selected bits in CM1CON, read yields undefined value
BF80_A010 CM2CON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON COE CPOL — — — — COUT
7:0 EVPOL<1:0> — CREF — — CCH<1:0>
BF80_A014 CM2CONCLR 31:0 Write clears selected bits in CM2CON, read yields undefined value
BF90_A018 CM2CONSET 31:0 Write sets selected bits in CM2CON, read yields undefined value
BF80_A01C CM2CONINV 31:0 Write inverts selected bits in CM2CON, read yields undefined value
BF80_A060 CMSTAT 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — FRZ SIDL — — — — —
7:0 — — — — — — C2OUT C1OUT
BF80_A064 CMSTATCLR 31:0 Write clears selected bits in CMSTAT, read yields undefined value
BF80_A068 CMSTATSET 31:0 Write sets selected bits in CMSTAT, read yields undefined value
BF80_A06C CMSTATINV 31:0 Write inverts selected bits in CMSTAT, read yields undefined value

PIC32MX3XX/4XX
TABLE 24-2: COMPARATOR INTERRUPT REGISTER SUMMARY(1)
Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1100 IPC7 23:16 — — — CMP2IP<2:0> CMP2IS<1:0>
15:8 — — — CMP1IP<2:0> CMP1IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Comparator peripheral. Refer to the
PIC32MX Family Reference Manual (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
REGISTER 24-1: CM1CON: COMPARATOR 1 CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x R-0

ON COE CPOL — — — — COUT
bit 15 bit 8
R/W-1 R/W-1 r-x R/W-0 r-x r-x R/W-1 R/W-1

EVPOL<1:0> — CREF — — CCH<1:0>
bit 7 bit 0
Legend:

bit 15 ON: Comparator ON bit
1 = Module is enabled. Setting this bit does not affect the other bits in this register.
0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits
in this register.
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is driven on the output C1OUT pin
0 = Comparator output is not driven on the output C1OUT pin
bit 13 CPOL: Comparator Output Inversion bit
1 = Output is inverted
0 = Output is not inverted
Note: Setting this bit will invert the signal to the to the comparator interrupt generator as well. This will
result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
bit 8 COUT: Comparator Output bit
1 = Output of the comparator is a ‘1’
bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator
output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled

PIC32MX3XX/4XX
REGISTER 24-1: CM1CON: COMPARATOR 1 CONTROL REGISTER (CONTINUED)
bit 4 CREF: Comparator 1 Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the C1IN+ pin
bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator 1
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the C2IN+ pin
00 = Comparator inverting input is connected to the C1IN- pin

PIC32MX3XX/4XX
REGISTER 24-2: CM2CON: COMPARATOR 2 CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x R-0

ON COE CPOL — — — — COUT
bit 15 bit 8
R/W-1 R/W-1 r-x R/W-0 r-x r-x R/W-1 R/W-1

EVPOL<1:0> — CREF — — CCH<1:0>
bit 7 bit 0
Legend:

bit 15 ON: Comparator ON bit
1 = Module is enabled. Setting this bit does not affect the other bits in this register.
0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits
in this register.
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is driven on the output C2OUT pin
0 = Comparator output is not driven on the output C2OUT pin
bit 13 CPOL: Comparator Output Inversion bit
1 = Output is inverted
0 = Output is not inverted
Note: Setting this bit will invert the signal to the to the comparator interrupt generator as well. This will
result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.
bit 8 COUT: Comparator Output bit
bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the
comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled

PIC32MX3XX/4XX
REGISTER 24-2: CM2CON: COMPARATOR 2 CONTROL REGISTER (CONTINUED)
bit 4 CREF: Comparator 1 Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the C2IN+ pin
bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator 2
11 = Comparator inverting input is connected to the IVREF
00 = Comparator inverting input is connected to the C2IN- pin

PIC32MX3XX/4XX
REGISTER 24-3: CMSTAT: COMPARATOR CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
r-x R/W-0 R/W-0 r-x r-x r-x r-x r-x

— FRZ SIDL — — — — —
bit 15 bit 8
r-x r-x r-x r-x r-x r-x R-0 R-0

— — — — — — C2OUT C1OUT
bit 7 bit 0
Legend:

bit 14 FRZ: Freeze Control bit
Note: FRZ is writable in Debug Exception mode only. It always reads ‘0’ in normal mode.
bit 13 SIDL: Stop in Idle Control bit
1 = All comparator modules are disabled in IDLE mode
0 = All comparator modules continue to operate in IDLE mode.
bit 1 C2OUT: Comparator Output bit
1 = Output of comparator 2 is a ‘1’
bit 0 C1OUT: Comparator Output bit

PIC32MX3XX/4XX
24.2 Comparator Operation 24.3 Comparator Inputs
24.2.1 COMPARATOR CONFIGURATION Depending on the Comparator Operating mode, the
inputs to the comparators may be from two input pins
The Comparator module has a flexible input and output or a combination of an input pin and one of two internal
configuration to allow the module to be tailored to the voltage references. The analog signal present at VIN- is
needs of the application. The PIC32MX3XX/4XX com- compared to the signal at VIN+ and the digital output of
parator module has individual control over the enables, the comparator is set or cleared according to the result
output inversion, output on I/O pin and input selections. of the comparison (see Figure 24-2).
The VIN+ pin of each comparator can select from an
input pin or the CVREF. The VIN- input of the compara-
FIGURE 24-2: SINGLE COMPARATOR
tor can select from one of 3 input pins or the IVREF. In
addition, the module has two individual comparator
event generation control bits. These control bits can be
used for detecting when the output of an individual VIN+ +
comparator changes to a desired state or changes Output
VIN- –
states.
If the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
change delay (refer to the device data sheet for more
information). VIN+
Note: Comparator interrupts should be disabled VIN-

during a Comparator mode change;
otherwise, a false interrupt may be gener-
ated.
A single comparator is shown in the upper portion of
Output
Figure 24-2. The lower portion represents the relation-
ship between the analog input levels and the digital out-
put. When the analog input at VIN+ is less than the
analog input at VIN-, the output of the comparator is a
digital low level. When the analog input at VIN+ is 24.3.0.1 External Reference Signal
greater than the analog input VIN-, the output of the An external voltage reference may be used with the
comparator is a digital high level. The shaded areas of comparator by using the output of the reference as an
the output of the comparator in the lower portion of input to the comparator. Refer to the device data sheet
Figure 24-2 demonstrate the uncertainty that is due to for input voltage limits.
input offsets and the response time of the comparator.
24.3.0.2 Internal Reference Signals
The CVREF module and the IVREF can be used as
inputs to the comparator (see Figure 24-1). The CVREF
provides a user-selectable voltage for use as a compar-
ator reference. Refer to 25.0 “Comparator Refer-
ence” of this manual for more information on this
module. The IVREF has a fixed, 1.2V output that does
not change with the device supply voltage. Refer to the
device data sheet for specific details and accuracy of
this reference.

PIC32MX3XX/4XX
24.4 Comparator Outputs 24.5 Analog Input Connection
The comparator output is read through the CMSTAT
Considerations
register and the COUT bit (CM2CON<8> or A simplified circuit for an analog input is shown in
CM1CON<8>). This bit is read-only. The comparator Figure 24-3. A maximum source impedance of 10 kΩ
output may also be directed to an I/O pin via the is recommended for the analog sources. Any external
CxOUT bit; however, the COUT bit is still valid when component connected to an analog input pin, such as
the signal is routed to a pin. For the comparator output a capacitor or a zener diode, should have very little
to be available on the CxOut pin, the associated TRIS leakage current. See the device data sheet for input
bit for the output pin must be configured as an output. voltage limits. If a pin is to be shared by two or more
When the COUT signal is routed to a pin the signal is analog inputs that are to be used simultaneously, the
the unsynchronized output of the comparator. loading effects of all the modules involved must be
The output of the comparator has a degree of uncer- taken into consideration. This loading may reduce the
tainty. The uncertainty of each of the comparators is accuracy of one or more of the modules connected to
related to the input offset voltage and the response the common pin. This may also require a lower source
time, as stated in the specifications. The lower portion impedance than is stated for a single module with
of Figure 24-2 provides a graphical representation of exclusive use of a pin in Analog mode.
this uncertainty. Notes: When reading the PORT register, all pins
The comparator output bit, COUT, provides the latched configured as analog inputs will read as a
sampled value of the comparator’s output- when the ‘0’. Pins configured as digital inputs will
register was read. There are two common methods convert an analog input according to the
used to detect a change in the comparator output: Schmitt Trigger input specification.
• Software polling Analog levels on any pin defined as a
• Interrupt generation digital input may cause the input buffer to
consume more current than is specified.
24.4.1 CHANGING THE POLARITY OF
COMPARATOR OUTPUTS
The polarity of the comparator outputs can be changed
using the CPOL bit (CMxCON<13>). CPOL appears
below the comparator Cx on the left side of Figure 24-1.
FIGURE 24-3: COMPARATOR ANALOG INPUT MODEL
VDD
RS < 10k RIC

Comparator
Input
AIN
CPIN ILEAKAGE
VA ±500 nA
5 pF
VSS
Legend: CPIN = Input Capacitance

LEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage

PIC32MX3XX/4XX
24.6 Interrupts
EXAMPLE 24-1: COMPARATOR INITIALIZATION WITH INTERRUPTS ENABLED CODE EXAMPLE

// Configure both comparators to generate an interrupt on any
// output transition
CM1CON = 0xC0D0; // Initialize Comparator 1
// Comparator enabled, output enabled, interrupt on any output
// change, inputs: CVref, C1IN-
CM2CON = 0xA0C2; // Initialize Comparator 2
// Comparator enabled, output enabled, interrupt on any output
// change, inputs: C2IN+, C1IN+
// Enable interrupts for Comparator modules and set priorities

// Set priority to 7 & sub priority to 3
IPC7SET = 0x00000700; // Set CMP1 interrupt sub priority
IFS1CLR = 0x00000008; // Clear the CMP1 interrupt flag
IEC1SET = 0x00000008; // Enable CMP1 interrupt
IPC7SET = 0x00070000; // Set CMP2 interrupt sub priority

IEC1SET = 0x000000010; // Enable CMP2 interrupt
EXAMPLE 24-2: COMPARATOR ISR CODE EXAMPLE

// Insert user code here
void__ISR(_COMPARATOR_2_VECTOR, ipl4)Cmp2_IntHandler(void)
{
// Insert user code here
}
void__ISR(_COMPARATOR_1_VECTOR, ipl4)Cmp1_IntHandler(void)
{
// Insert code user here
}

PIC32MX3XX/4XX
TABLE 24-3: PINS ASSOCIATED WITH A COMPARATOR

Module Required Pin Buffer
Pin Name Controlling Bit Field Description
Control TRIS Bit Setting Type Type
C1IN+(3) ON CVREF(1), CCH<1:0>(1), Input A, I — Analog Input for C1IN+

CCH<1:0>(2), AD1PCFG
C1IN- ON CCH<1:0>(1), AD1PCFG Input A, I — Analog Input for C1IN-
C2IN+ ON CVREF(2), CCH<1:0>(1), Input A, I — Analog Input for C2IN+
CCH<1:0>(2), AD1PCFG
C2IN- ON CCH<1:0>(2), AD1PCFG Input A, I — Analog Input for C2IN-
C1OUT ON COE(1) Output D, O — Digital Output of the C1
C2OUT ON COE(2) Output D, O — Digital Output of the C2
Note 1: In CM1CON register.
2: In CM2CON register.
3: On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not
available as a comparator input.

PIC32MX3XX/4XX
25.0 COMPARATOR REFERENCE A block diagram of the module is shown in Figure 25-1.
The resistor ladder is segmented to provide two ranges
Note: This data sheet summarizes the features of of voltage reference values and has a power-down func-
the PIC32MX3XX/4XX family of devices. It tion to conserve power when the reference is not being
is not intended to be a comprehensive refer- used. The module’s supply reference can be provided
ence source. Refer to the “PIC32MX Family from either device VDD/VSS or an external voltage refer-
Reference Manual” (DS61132) for a ence. The CVREF output is available for the comparators
detailed description of this peripheral. and typically available for pin output. Please see the
specific device data sheet for information.
The Comparator Voltage Reference (CVREF) is a 16-
tap, resistor ladder network that provides a selectable The comparator voltage reference has the following
reference voltage. Although its primary purpose is to features:
provide a reference for the analog comparators, it also • High and low range selection
may be used independently of them. • Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+
AVDD
CVRSS = 0 8R
CVR3:CVR0
CVREN R
R CVREFIN
R
16-to-1 MUX
R
16 Steps
CVREF
CVRCON<CVROE-
R
R
R
CVRR 8R
CVRSS = 1
VREF-
AVSS
CVRSS = 0

PIC32MX3XX/4XX
25.1 Comparator Voltage Reference Table 25-1 provides a brief summary of all CVREF
Control Registers module related registers. Corresponding registers
appear after the summary, followed by a detailed
The CVREF module consists of the following Special description of each register.
• CVRCON: Control Register for the Module
• CVRCONCLR, CVRCONSET, CVRCONINV:
atomic Bit Manipulation Registers for CVRCON
TABLE 25-1: COMPARATOR VOLTAGE REFERENCE SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_9800 CVRCON 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 ON — — — — —
7:0 — CVROE CVRR CVRSS CVR<3:0>
BF80_9804 CVRCONCLR 31:0 Write clears selected bits in CVRCON, read yields undefined value
BF80_9808 CVRCONSET 31:0 Write sets selected bits in CVRCON, read yields undefined value
BF80_980C CVRCONINV 31:0 Write inverts selected bits in CVRCON, read yields undefined value

PIC32MX3XX/4XX
REGISTER 25-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

ON — — — — — — —
bit 15 bit 8
r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CVROE CVRR CVRSS CVR<3:0>
bit 7 bit 0
Legend:

bit 15 ON: CVREF Peripheral On bit
1 = Module is enabled; setting this bit does not affect the other bits in the register
0 = Module is disabled and does not consume current; clearing this bit does not affect the other bits
in the register
bit 6 CVROE: CVREF Output Enable bit
1 = Voltage level is output on CVREF pin
0 = Voltage level is disconnected from CVREF pin
Note: CVROE overrides the TRIS bit setting; see Section 12.0 “I/O Ports” for more information.
bit 5 CVRR: CVREF Range Selection bit
1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 CVRSS: CVREF Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0>: CVREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/24) • (CVRSRC)
When CVRR = 0:
CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)

PIC32MX3XX/4XX
25.2 Operation The equations used to calculate the CVREF output are
as follows:
The CVREF module is controlled through the CVRCON
register (Register 25-1). The CVREF provides two If CVRR = 1:
ranges of output voltage, each with 16 distinct levels. Voltage
The range to be used is selected by the CVRR bit Reference = ((CVR3:CVR0)/24) x (CVRSRC)
(CVRCON<5>). The primary difference between the If CVRR = 0:
ranges is the size of the steps selected by the CVREF Voltage
Value Selection bits, CVR3:CVR0, with one range Reference = (CVRSRC/4) + ((CVR3:CVR0)/32)
offering finer resolution and the other offering a wider x (CVRSRC)
range of output voltage. The typical output voltages are The CVREF Source Voltage (CVRSRC) can come from
listed in Table 25-2. either VDD and VSS, or the external VREF+ and VREF-
pins that are multiplexed with I/O pins. The voltage
source is selected by the CVRSS bit (CVRCON<4>).
The voltage reference is output to the CVREF pin by set-
ting the CVROE (CVRCON<6>) bit; this will override
the corresponding TRIS bit setting.
The settling time of the CVREF must be considered
when changing the CVREF output (refer to the data
sheet for your device).
TABLE 25-2: TYPICAL VOLTAGE REFERENCE WITH CVRSRC = 3.3

Voltage Reference
CVR<3:0>
CVRR = 0 (CVRCON <5>) CVRR = 1 (CVRCON <5>
0 0.83V 0.00V
1 0.93V 0.14V
2 1.03V 0.28V
3 1.13V 0.41V
4 1.24V 0.55V
5 1.34V 0.69V
6 1.44V 0.83V
7 1.55V 0.96V
8 1.65V 1.10V
9 1.75V 1.24V
10 1.86V 1.38V
11 1.96V 1.51V
12 2.06V 1.65V
13 2.17V 1.79V
14 2.27V 1.93V
15 2.37V 2.06V

PIC32MX3XX/4XX
25.2.1 CVREF OUTPUT CONSIDERATIONS
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 25-1) keep the voltage reference from
approaching the reference source rails. The voltage
reference is derived from the reference source; there-
fore, the voltage reference output changes with
fluctuations in that source. Refer to the product data
sheet for the electrical specifications. Table 25-3
contains the typical output impedances for the CVREF
module.
TABLE 25-3: TYPICAL CVREF OUTPUT IMPEDANCE IN OHMS
Voltage Reference
CVR<3:0>
CVRR = 0 (CVRCON <5>) CVRR = 1 (CVRCON <5>
0 12k 500
1 13k 1.9k
2 13.8k 3.7k
3 14.4k 5.3k
4 15k 6.7k
5 15.4k 7.9k
6 15.8k 9k
7 15.9k 9.9k
8 16k 10.7k
9 15.9k 11.3k
10 15.8k 11.7k
11 15.4k 11.9k
12 15k 12k
13 14.4k 11.9k
14 13.8k 11.7k
15 12.9k 11.3k
25.2.2 INITIALIZATION
This initialization sequence, shown in Example 25-1,
configures the CVREF module for: module enabled, out-
put enabled, high range, and set output for maximum
(2.37V).
EXAMPLE 25-1: VOLTAGE REFERENCE CONFIGURATION
CVRCON = 0x804F; //Initialize Voltage Reference Module

//enable module, enable output, set
// range to high, set output to maximum

PIC32MX3XX/4XX
25.3 Interrupts
There are no Interrupt configuration registers or bits for
the CVREF module. The CVREF module does not
generate interrupts.

The CVREF module has the ability to output to a pin.
When the CVREF module is enabled and CVROE
(CVRCON<6>) is ‘1’, the output driver for the CVREF
pin is disabled and the CVREF voltage is available at the
pin. For proper operation, the TRIS bit corresponding to
the CVREF pin must be a ‘1’ when CVREF is to be output
to a pin. This disables the Digital Input mode for the pin
and prevents undesired current draw resulting from
applying an analog voltage to a digital input pin. The
output buffer has very limited drive capability. An exter-
nal buffer amplifier is recommended for any application
that uses the CVREF voltage externally. An output
capacitor may be used to reduce output noise. Use of
an output capacitor will increase settling time.
TABLE 25-4: PINS ASSOCIATED WITH A COMPARATOR

Required
Module Controlling Pin Buffer
Pin Name TRIS Bit Description
Control Bit Field Type Type
Setting
CVREF ON CVROE Input A, O — CVREF Output


PIC32MX3XX/4XX
26.0 WATCHDOG TIMER The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
Note: This data sheet summarizes the features of used to detect system software malfunctions by reset-
the PIC32MX3XX/4XX of devices. It is not ting the device if the WDT is not cleared periodically in
intended to be a comprehensive reference software. Various WDT time-out periods can be
source. Refer to the “PIC32MX Family selected using the WDT postscaler. The WDT can also
Reference Manual” (DS61132) for a be used to wake the device from Sleep or Idle mode.
detailed description of this peripheral. Refer to Figure 26-1.
This section describes the operation of the Watchdog The following are some of the key features of the WDT
Timer (WDT) and Power-Up Timer of the module:
PIC32MX3XX/4XX. • Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
TABLE 26-1: RESULTS OF A WDT TIME-OUT EVENT FOR AVAILABLE MODES OF

DEVICE OPERATION
Non-
Device
Device Reset Maskable WDTO(1) Bit SLEEP(1) Bit
Device Mode
Generated Interrupt IDLE(1) Bit Set Registers
Set Set Reset
Generated
Awake Yes No Yes No No Yes
Sleep No Yes Yes Yes No No
Idle No Yes Yes No Yes No
Note 1: Status bits are in the RCON register.
FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable LPRC

WDT Enable Control
PWRT Enable
LPRC 1:64 Output

PWRT
Oscillator
Clock
25-bit Counter
WDTCLR = 1
25
WDT Enable
0 Device Reset
WDT Counter Reset
Wake 1
NMI (Wake-up)
Power Save
Decoder
FWDTPS<4:0>(DEVCFG1<20:16>)

PIC32MX3XX/4XX
26.1 Watchdog Timer Registers
TABLE 26-2: WDT SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_0000 WDTCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 ON — — — — — — —
7:0 — SWDTPS — WDTCLR
BF80_0004 WDTCONCLR 31:0 Write clears selected bits in WDTCON, Read yields an undefined value
BF80_0008 WDTCONSET 31:0 Write sets selected bits in WDTCON, Read yields an undefined value
BF80_000C WDTCONINV 31:0 Write inverts selected bits in WDTCON, Read yields an undefined value
TABLE 26-3: RESET REGISTER SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_F600 RCON 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 — — — — — — CM VREGS
BF80_F604 RCONCLR 31:0 Write clears selected bits in RCON, Read yields an undefined value
BF80_F608 RCONSET 31:0 Write sets selected bits in RCON, Read yields an undefined value
BF80_F60C RCONINV 31:0 Write inverts selected bits in RCON, Read yields an undefined value
Note 1: This summary table contains partial register definitions that only pertain to the Watchdog Timer peripheral. Refer to the PIC32MX Family
Reference Manual (DS61132) for a detailed description of these registers.
TABLE 26-4: DEVICE CONFIGURATION SUMMARY(1)

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BFC0_2FF8 DEVCFG1 23:16 FWDTEN — — WDTPS<4:0>
Note 1: This summary table contains partial register definitions that only pertain to the Watchdog Timer peripheral. Refer to the PIC32MX Family
Reference Manual (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

ON — — — — — — —
bit 15 bit 8
r-x R-x R-x R-x R-x R-x r-0 R/W-0

— SWDTPS — WDTCLR
bit 7 bit 0
Legend:

bit 15 ON: Watchdog Timer Enable bit(1)
1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if is was enabled in software.
bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Post-Scaler Value from Device Configuration bits
bit 0 WDTCLR: Watchdog Timer Reset bit

1 = Writing a ‘1’ will reset the WDT.
0 = Software cannot force this bit to a ‘0’.
Note 1: A read of this bit will result in a ‘1’ if the WDT is enabled by the device configuration or by software.

PIC32MX3XX/4XX
REGISTER 26-2: RCON: RESETS CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16
R/W-0 r-x r-x r-x r-x R-0 R/W-0 R/W-0

— — — — — — CM VREGS
bit 15 bit 8

bit 7 bit 0
Legend:
bit 4 WDTO: Watchdog Time-Out bit

1 = A WDT time-out has occurred since the device was powered up
0 = A WDT time-out has not occurred since the WDTO bit was cleared by software
bit 3 SLEEP: Sleep Mode Status bit
1 = The device has been in Sleep mode since the device was powered up
0 = The device has not been in Sleep mode since the SLEEP bit was cleared by software
bit 2 IDLE: Idle Mode Status bit
1 = The device has been in Idle mode since the device was powered up
0 = The device has not been in Idle mode since the Idle bit was cleared by software

PIC32MX3XX/4XX
REGISTER 26-3: DEVCFG1: DEVICE CONFIGURATION WORD 1
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
R/P-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FWDTEN — — WDTPS<4:0>
bit 23 bit 16

bit 15 bit 8
R/P-1 r-1 R/P-1 r-1 r-1 R/P-1 R/P-1 R/P-1

IESO — FSOSCEN — — FNOSC<2:0>
bit 7 bit 0
Legend:

bit 23 FWDTEN: WatchDog Timer Hardware Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled. It can be enabled in software
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscaler Selection bits(1)
These bits are used to set the WDT time-out period.
10100 = 1:1,045,876
10011 = 1:524,288
10010 = 1:262,144
10001 = 1:131,072
10000 = 1:65,536
01111 = 1:32,768
01110 = 1:16,384
01101 = 1:8,192
01100 = 1:4,096
01011 = 1:2,048
01010 = 1:1,024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
Note 1: All combinations not listed result in operation as if the selection was 10100.
2: Do not disable POSC (POSCMD = 00) when using this oscillator source.

PIC32MX3XX/4XX
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
the External Clock (EC) mode for the CLKO to be active (POSCMD<1:0> = 11 or 00)
11 = Primary oscillator is disabled
10 = HS Oscillator mode selected
01 = XT Oscillator mode selected
00 = External Clock mode selected
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode enabled (Two-Speed Start-Up enabled)
0 = Internal External Switchover mode disabled (Two-Speed Start-Up disabled)
bit 5 FSOSCEN: Secondary Oscillator Enable bits
1 = Enable secondary oscillator
0 = Disable secondary oscillator
bit 2-0 FNOSC<2:0>: Oscillator Selection bits
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV + PLL)
010 = Primary Oscillator (XT, HS, EC)(2)
011 = Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL)(2)
100 = Secondary Oscillator
110 = FRCDIVIG Fast RC Oscillator with fixed divide-by-16 postscaler
Note 1: All combinations not listed result in operation as if the selection was 10100.
2: Do not disable POSC (POSCMD = 00) when using this oscillator source.

PIC32MX3XX/4XX
26.2 Watchdog Timer and Power-Up 26.2.5 WDT OPERATION IN POWER SAVE
Timer Operation MODES
This describes the operation of the Watchdog Timer The WDT, if enabled, will continue operation in Sleep or
operation and the Power-Up Timer Idle modes. The WDT may be used to wake the device
from Sleep or Idle. When the WDT times out in a Power
26.2.1 WATCHDOG TIMER OPERATION Save mode, a Non-Maskable Interrupt (NMI) is gener-
ated and the WDTO (RCON<4>) bit is set. The NMI
If enabled, the WDT will increment until it overflows or vectors execution to the CPU start-up address but does
“times out”. A WDT time-out will force a device Reset, not reset registers or peripherals. If the device was in
except during Sleep or Idle modes. To prevent a WDT Sleep, the SLEEP (RCON<3>) status bit will also be
time-out Reset, the user must periodically clear the set. If the device was in Idle, the IDLE (RCON<2>) sta-
Watchdog Timer by setting the WDTCLR tus bit will also be set. These bits allow the start-up
(WDTCON<0>) bit. code to determine the cause of the wake-up.
The WDT uses the LPRC oscillator for reliability.
26.2.6 TIME DELAYS ON WAKE
Note: The LPRC is enabled whenever the WDT
is enabled. There will be a time delay between the WDT event in
Sleep and the beginning of code execution. The dura-
26.2.2 ENABLING AND DISABLING THE tion of this delay consists of the Start-up time for the
WDT oscillator in use and the Power-Up Timer delay, if it is
enabled.
The WDT is enabled or disabled by the device configu-
ration or controlled via software by writing to the Unlike a wake-up from Sleep mode, there are no time
WDTCON register. delays associated with wake-up from Idle mode. The
system clock is running during Idle mode; therefore, no
26.2.3 DEVICE CONFIGURATION start-up delays are required at wake-up.
CONTROLLED WDT
26.2.7 RESETTING THE WDT TIMER
If the FWDTEN Configuration bit is set, then the WDT
is always enabled. The WDT ON control bit The WDT is reset by any of the following:
(WDTCON<15>) will reflect this by reading a ‘1’. In this • On ANY device Reset
mode, the ON bit cannot be cleared in software. This bit • By a WDTCONSET = 0x01 or equivalent
will not be cleared by any form of Reset. To disable the instruction during normal execution.
WDT in this mode, the configuration must be rewritten • Execution of a DEBUG command
to the device.
• Exiting from Idle or Sleep due to an interrupt
Note: The default state for the WDT on an Note: The WDT timer is not reset when the
unprogrammed device is WDT enabled. device enters a Power Save mode. The
WDT should be serviced prior to entering
26.2.4 SOFTWARE CONTROLLED WDT
a Power Save mode.
If the FWDTEN Configuration bit is a ‘0’, then the WDT
can be enabled or disabled (the default condition) by 26.2.8 WDT TIMER PERIOD SELECTION
software. In this mode, the ON (WDTCON<15>) bit The WDT clock source is the internal LPRC oscillator,
reflects the status of the WDT under software control. which has a nominal frequency of 32 kHz. This creates
A ‘1’ indicates the WDT is enabled and a ‘0’ indicates it a nominal time-out period for the WDT (TWDT) of 1
is disabled. millisecond when no postscaler is used.
The WDT is enabled in software by setting the WDT
Note: The WDT time-out period is directly
ON control bit. The WDT ON control bit is cleared on
related to the frequency of the LPRC
any device Reset, The bit is not cleared upon a wake
oscillator. The frequency of the LPRC
from Sleep or exit from Idle mode. The software WDT
oscillator will vary as a function of device
option allows the user to enable the WDT for critical
operating voltage and temperature.
code segments and disable the WDT during noncritical
Please refer to the specific
segments for maximum power savings. This bit can
PIC32MX3XX/4XX device data sheet for
also be used to disable the WDT while the part is
LPRC clock frequency specifications.
awake to eliminate the need for WDT servicing, and
then re-enable it before the device is put into Idle or
Sleep to wake the part at a later time.

PIC32MX3XX/4XX
26.2.9 WDT POSTSCALERS TABLE 26-5: WDT TIME-OUT PERIOD VS.
The WDT has a 5-bit postscaler to create a wide variety POSTSCALER SETTINGS
of time-out periods. This postscaler provides 1:1 Postscaler Time-out
FWDTPS<4:0> Period
through 1: 1048576 divider ratios. Time-out periods Ratio
that range between 1 ms and 1048.576 seconds
00000 1:1 1 ms
(nominal) can be achieved using the postscaler.
00001 1:2 2 ms
The postscaler settings are selected using the WDTPS
00010 1:4 4 ms
bits in the DEVCFG1 Configuration register. The time-
out period of the WDT is calculated as follows: 00011 1:8 8 ms
00100 1:16 16 ms
EQUATION 26-1: WDT TIME-OUT PERIOD 00101 1:32 32 ms
CALCULATIONS 00110 1:64 64 ms
00111 1:128 128 ms
WDT Period = 1 ms • 2 Prescaler 01000 1:256 256 ms
01001 1:512 512 ms
01010 1:1024 1.024 s
01011 1:2048 2.048 s
01100 1:4096 4.096 s
01101 1:8192 8.192 s
01110 1:16384 16.384 s
01111 1:32768 32.768 s
10000 1:65536 65.536 s
10001 1:131072 131.072 s
10010 1:262144 262.144 s
10011 1:524288 524.288 s
10100 1:1045876 1048.576 s
Note 1: All other combinations will result in an
operation as if the prescaler was set to
10100.
2: The periods listed are based on a 32 kHz
(nominal) input clock.

PIC32MX3XX/4XX
26.3 Interrupts and Resets 26.3.2 WATCHDOG TIMER NMI
The WDT will cause an NMI or a device Reset when it When the WDT expires in Sleep or Idle, a NMI is gen-
expires. The Power Save mode of the device erated. The NMI causes the CPU code execution to
determines which event occurs. The PWRT does not jump to the device Reset vector. Though the NMI share
generate interrupts or Resets. the same vector as a device Reset, registers and
peripherals are not reset.
26.3.1 WATCHDOG TIMER RESET To detect a wake from a Power Save mode by WDT, the
When the WDT expires and the device is not in Sleep WDTO (RCON<4>), SLEEP (RCON<3>) and IDLE
or Idle, a device Reset is generated. The CPU code (WDTCON<2>) bits must be tested. If the WDTO bit is
execution jumps to the device Reset vector and the a ‘1’ the event was caused by a WDT time-out. The
Registers and Peripherals are forced to their Reset SLEEP and IDLE bits can then be tested to determine
values. if the WDT event occurred in Sleep or Idle.
To detect a WDT Reset, the WDTO (RCON<4>), To cause a WDT time-out in Sleep to act like an inter-
SLEEP (RCON<3>) and IDLE (WDTCON<2>) bits rupt, a return from interrupt instruction may be used in
must be tested. If the WDTO bit is a ‘1’, the event was the start-up code after the event was determined to be
do to a WDT time-out. The SLEEP and IDLE bits can a WDT wake-up. This will cause code execution to con-
then be tested to determine if the WDT event occurred tinue with the opcode following the WAIT instruction
while the device was awake or if it was in Sleep or Idle. that put the device into Power Save mode. See
Example 26-2.
EXAMPLE 26-1: SAMPLE WDT INITIALIZATION AND SERVICING

//This code fragment assumes the WDT was not enabled by the device configuration
// The Postscaler value must be set with the device configuration
WDTCONSET = 0x8000; // Turn on the WDT
main
{
WDTCONSET = 0x01; // Service the WDT
... User code goes here ...

}

PIC32MX3XX/4XX
EXAMPLE 26-2: SAMPLE CODE TO DETERMINE THE CAUSE OF A WDT EVENT
// sample code to determine the cause of a WDT event
// Unlock the OSCCON register

SYSKEY = 0x12345678; //write invalid key to force lock
SYSKEY = 0xAA996655; //write Key1 to SYSKEY
SYSKEY = 0x556699AA; //write Key2 to SYSKEY
OSCCONSET = 0x10; // set power save mode to Sleep
// Alternate relock code in ‘C’

SYSREG = 0x33333333;
WDTCONSET = 0x8000; //Enable WDT
while (1)
{
... user code ...
WDTCONSET = 0x01;// service the WDT

asm volatile ( “wait” ); // put device is selected power save mode
// code execution will resume here after wake
... user code ...

}
// The following code fragment is at the top of the device start-up code
if ( RCON & 0x18 )

{
// The WDT caused a wake from sleep
asm volatile ( “eret” ); // return from interrupt
}
if ( RCON & 0x14 )

{
// The WDT caused a wake from idle
asm volatile ( “eret” ); // return from interrupt
}
if ( RCON & 0x10 )

{
// WDT timed-out
(device may have been awake or may have been in sleep/idle mode)
}

PIC32MX3XX/4XX
27.0 SPECIAL FEATURES
the PIC32MX3XX/4XX of devices. It is not
intended to be a comprehensive reference
source. Refer to the “PIC32MX Family
PIC32MX3XX/4XX devices include several features

intended to maximize application flexibility and reliabil-
ity, and minimize cost through elimination of external
components. These are:
• Flexible Device Configuration
• Code Protection
• Internal Voltage Regulator
TABLE 27-1: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BFC0_2FF0 DEVCFG3 31:24 — — — — — — — —
23:16 — — — — — — — —
15:8 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8
7:0 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0
BFC0_2FF4 DEVCFG2 31:24 — — — — — — — —
23:16 — — — — — FPLLODIV<2:0>
15:8 FUPLLEN — — — — FUPLLIDIV<2:0>
7:0 — FPLLMULT<2:0> — FPLLIDIV<2:0>
BFC0_2FF8 DEVCFG1 31:24 — — — — — — — —
23:16 FWDTEN — — WDTPS<4:0>
15:8 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMD<1:0>
7:0 IESO — FSOSCEN — — FNOSC<2:0>
BFC0_2FFC DEVCFG0 31:24 — — — CP — — — BWP
23:16 — — — — PWP19 PWP18 PWP17 PWP16
15:8 PWP15 PWP14 PWP13 PWP12 — — — —
7:0 — — — — ICESEL — DEBUG<1:0>
TABLE 27-2: DEVID SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_F220 DEVID 31:24 VER11 VER10 VER9 VER8 VER7 VER6 VER5 VER4
23:16 VER3 VER2 VER1 VER0 DEV7 DEV6 DEV5 DEV4
15:8 DEV3 DEV2 DEV1 DEV0 MANID11 MANID10 MANID9 MANID8
7:0 MANID7 MANID6 MANID5 MANID4 MANID3 MANID2 MANID1 1

PIC32MX3XX/4XX
r-0 r-1 r-1 R/P-1 r-1 r-1 r-1 R/P-1
— — — CP — — — BWP
bit 31 bit 24
r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1

— — — — PWP19 PWP18 PWP17 PWP16
bit 23 bit 16
R/P-1 R/P-1 R/P-1 R/P-1 r-1 r-1 r-1 r-1

PWP15 PWP14 PWP13 PWP12 — — — —
bit 15 bit 8
r-1 r-1 r-1 r-1 R/P-1 r-1 R/P-1 R/P-1

— — — — ICESEL — DEBUG1 DEBUG0
bit 7 bit 0
Legend:

bit 28 CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external
programming device.
1 = Protection disabled
0 = Protection enabled
bit 24 BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable

PIC32MX3XX/4XX
REGISTER 27-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 19-12 PWP<19:12>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution.
The PWP bits represent the one’s compliment of the number of write protected program Flash memory
pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
...
01111111 = 0xBD07_FFFF
bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = In-Circuit Emulator uses EMUC2/EMUD2 pins; In-Circuit Debugger uses
PGC2/PGD2 pins
0 = In-Circuit Emulator uses EMUC1/EMUD1 pins; In-Circuit Debugger uses
PGC1/PGD1 pins
bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger disabled
10 = Debugger enabled
01 = Reserved (same as ‘11’ setting)

PIC32MX3XX/4XX
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
R/P-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

FWDTEN — — WDTPS<4:0>
bit 23 bit 16

bit 15 bit 8
R/P-1 r-1 R/P-1 r-1 r-1 R/P-1 R/P-1 R/P-1

IESO — FSOSCEN — — FNOSC<2:0>
bit 7 bit 0
Legend:

bit 23 FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = ‘10100’

PIC32MX3XX/4XX
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 OR 00)
11 = Primary oscillator disabled
10 = HS oscillator mode selected
01 = XT oscillator mode selected
00 = External clock mode selected
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled)
0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled)
bit 5 FSOSCEN: Secondary Oscillator Enable bit
bit 2-0 FNOSC<2:0>: Oscillator Selection bits
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
Note 1: Do not disable POSC (POSCMD = 00) when using this oscillator source.

PIC32MX3XX/4XX
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
r-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1

— — — — — FPLLODIV<2:0>
bit 23 bit 16
R/P-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1

FUPLLEN — — — — FUPLLIDIV<2:0>
bit 15 bit 8
r-1 R/P-1 R/P-1 R/P-1 r-1 R/P-1 R/P-1 R/P-1

— FPLLMULT<2:0> — FPLLIDIV<2:0>
bit 7 bit 0
Legend:

bit 18-16 FPLLODIV[2:0]: Default Postscaler for PLL bits
bit 15 FUPLLEN: USB PLL Enable bit
1 = Enable USB PLL
0 = Disable and bypass USB PLL
bit 10-8 FUPLLIDIV[2:0]: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider

PIC32MX3XX/4XX
bit 6-4 FPLLMULT[2:0]: PLL Multiplier bits
bit 2-0 FPLLIDIV[2:0]: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider

PIC32MX3XX/4XX
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
bit 31 bit 24
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1

— — — — — — — —
bit 23 bit 16
R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x

USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8
bit 15 bit 8
R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x R/P-x

USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0
bit 7 bit 0
Legend:

bit 15-0 USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSP™ and JTAG

PIC32MX3XX/4XX
REGISTER 27-5: DEVID: DEVICE ID REGISTER
R R R R R-0 R-0 R-0 R-0
VER11 VER10 VER9 VER8 VER7 VER6 VER5 VER4
bit 31 bit 24
R-1 R-0 R-0 R-1 R R R R

VER3 VER2 VER1 VER0 DEV7 DEV6 DEV5 DEV4
bit 23 bit 16
R R R R R-0 R-0 R-0 R-0

DEV3 DEV2 DEV1 DEV0 MANID11 MANID10 MANID9 MANID8
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-1

MANID7 MANID6 MANID5 MANID4 MANID3 MANID2 MANID1 1
bit 7 bit 0
Legend:
bit 31-20 VER<11:0>: Revision Identifier bits

bit 19-12 DEVID<7:0>: Device ID
78h = PIC32MX460F512L
74h = PIC32MX460F256L
6Dh = PIC32MX440F128L
56h = PIC32MX440F512H
52h = PIC32MX440F256H
4Dh = PIC32MX440F128H
42h = PIC32MX420F032H
38h = PIC32MX360F512L
34h = PIC32MX360F256L
2Dh = PIC32MX340F128L
2Ah = PIC32MX320F128L
16h = PIC32MX340F512H
12h = PIC32MX340F256H
0Dh = PIC32MX340F128H
0Ah = PIC32MX320F128H
06h = PIC32MX320F064H
02h = PIC32MX320F032H
bit 11-1 MANID<11:0>: JEDEC Manufacturer’s Identification Code for Microchip Technology Inc.
bit 0 Fixed Value: Read as ‘1’

PIC32MX3XX/4XX
27.1 Device Configuration 27.2 Device Code Protection
In PIC32MX3XX/4XX devices, the Configuration The PIC32MX features a single device code protection
Words select various device configurations. These bit, CP that when programmed = 0, protects boot Flash
Configuration Words are implemented as volatile mem- and program Flash from being read or modified by an
ory registers and must be loaded from the nonvolatile external programming device. When code protection is
programmed configuration data mapped in the last four enabled, only the Device ID registers is available to be
words (32-bit x 4 words) of boot Flash memory, read by an external programmer. Boot Flash and pro-
DEVCFG0-DEVCFG3. These are the four locations an gram Flash memory are not protected from self-pro-
external programming device programs with the appro- gramming during program execution when code
priate configuration data (see Table 27-3). protection is enabled. See Section 27.3 “Program
TABLE 27-3: DEVCFG LOCATIONS Write Protection (PWP)”.
Configuration Word Address

27.3 Program Write Protection (PWP)
DEVCFG0 0xBFC0_2FFC
In addition to a device code protection bit, the
DEVCFG1 0xBFC0_2FF8
PIC32MX also features write protection bits to prevent
DEVCFG2 0xBFC0_2FF4 boot Flash and program Flash memory regions from
DEVCFG3 0xBFC0_2FF0 being written during code execution.
On Power-on Reset (POR) or any Reset, the Configu- Boot Flash memory is write protected with a single
ration Words are copied from boot FLASH memory to Configuration bit, BWP (DEVCFG0<24>), when
their corresponding Configuration registers. A Configu- programmed = 0.
ration bit can only be programmed = 0 (unprogrammed Program Flash memory can be write-protected entirely
state = 1). During programming, a Configuration Word or in selectable page sizes using Configuration bits
can be programmed a maximum of two times before a PWP<7:0> (DEVCFG0<19:12>). A page of Program
page erase must be performed. Flash memory is 4096 bytes (1024 words). The PWP
After programming the Configuration Words, the user bits represent the one’s complement of the number of
should reset the device to ensure the Configuration protected pages. For example, programming PWP bits
registers are reloaded with the new programmed data. = 0xFF selects 0 pages to be write-protected, effec-
tively disabling the program Flash write protection. Pro-
27.1.1 CONFIGURATION REGISTER gramming PWP bits = 0xFE selects the first page to be
PROTECTION write protected. When enabled, the write-protected
memory range is inclusive from the beginning of pro-
To prevent inadvertent Configuration bit changes dur-
gram Flash memory (0xBD00_0000) up through the
ing code execution, all programmable Configuration
selected page. Refer to Table 27-4.
bits are write-once. After a bit is initially programmed
during a power cycle, it cannot be written to again. Note: The PWP bits represent the one’s
Changing a device configuration requires changes to complement of the number of protected
the configuration data in the boot Flash memory and pages.
power to the device be cycled.
To ensure the 128-bit data integrity, a comparison is
continuously made between each Configuration bit and
its stored complement. If a mismatch is detected, a
Configuration Mismatch Reset is generated, causing a
device Reset.

PIC32MX3XX/4XX
TABLE 27-4: FLASH PROGRAM MEMORY

WRITE-PROTECT RANGES
PWP Bit Range Size Write Protected
Value (Kbytes) Memory Ranges(1)
0xFF 0 Disabled
0xFE 4 0xBD00_0FFF
0xFD 8 0xBD00_1FFF
0xFC 12 0xBD00_2FFF
0xFB 16 0xBD00_3FFF
0xFA 20 0xBD00_4FFF
0xF9 24 0xBD00_5FFF
0xF8 28 0xBD00_6FFF
0xF7 32 0xBD00_7FFF
0xF6 36 0xBD00_8FFF
0xF5 40 0xBD00_9FFF
0xF4 44 0xBD00_AFFF
0xF3 48 0xBD00_BFFF
0xF2 52 0xBD00_CFFF
0xF1 56 0xBD00_DFFF
0xF0 60 0xBD00_EFFF
0xEF 64 0xBD00_FFFF
...
0x7F 512 0xBD07_FFFF
Note 1: Write-protected memory range is inclusive
from 0xBD00_0000.
The amount of program Flash memory available for
write protection depends on the family device variant.

PIC32MX3XX/4XX
27.4 On-Chip Voltage Regulator FIGURE 27-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
All PIC32MX3XX/4XX device’s core and digital logic
are designed to operate at a nominal 1.8V. To simplify Regulator Enabled (ENVREG tied to VDD):
system designs, most devices in the
3.3V
PIC32MX3XX/4XX incorporate an on-chip regulator
providing the required core logic voltage from VDD. PIC32MX
VDD
The internal 1.8V regulator is controlled by the
ENVREG
ENVREG pin. Tying this pin to VDD enables the regu-
lator, which in turn provides power to the core. A low VDDCORE/VCAP
ESR capacitor (such as tantalum) must be connected CEFC
to the VDDCORE/VCAP pin (Figure 27-1). This helps to VSS
(10 μF typ)
maintain the stability of the regulator. The recom-
mended value for the filer capacitor is provided in
Section 30.1 “DC Characteristics”.
Tying the ENVREG pin to VSS disables the regulator. In
this case, separate power for the core logic at a nomi- Regulator Disabled (ENVREG tied to ground):
nal 1.8V must be supplied to the device on the
1.8V(1) 3.3V(1)
VDDCORE/VCAP pin.
PIC32MX
Alternatively, the VDDCORE/VCAP and VDD pins can be
VDD
tied together to operate at a lower nominal voltage.
Refer to Figure 27-1 for possible configurations. ENVREG
VDDCORE/VCAP
27.4.1 ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approxi- VSS
mately 10 μs for it to generate output. During this time,
designated as TSTARTUP, code execution is disabled.
Note 1: These are typical operating voltages. Refer
TSTARTUP is applied every time the device resumes
to Section 30.1 “DC Characteristics” for
operation after any power-down, including Sleep mode. the full operating ranges of VDD and
If the regulator is disabled, a separate Power-Up Timer VDDCORE.
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up.
27.4.2 ON-CHIP REGULATOR AND BOR

When the on-chip regulator is enabled,
PIC32MX3XX/4XX devices also have a simple brown-
out capability. If the voltage supplied to the regulator is
inadequate to maintain a regulated level, the regulator
Reset circuitry will generate a Brown-out Reset. This
event is captured by the BOR flag bit (RCON<1>). The
brown-out voltage levels are specific in Section 30.1
“DC Characteristics”.
27.4.3 POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.

PIC32MX3XX/4XX
28.0 PROGRAMMING AND • Simplified field programmability using two-wire In-
Circuit Serial Programming™ (ICSP™) interfaces
DIAGNOSTICS
• Debugging using ICSP
Note: This data sheet summarizes the features of • Programming and debugging capabilities using
the PIC32MX3XX/4XX of devices. It is not the EJTAG extension of JTAG
intended to be a comprehensive reference • JTAG boundary scan testing for device and board
source. Refer to the “PIC32MX Family diagnostics
detailed description of this peripheral. PIC32MX devices incorporate two programming and
diagnostic modules, and a trace controller, that provide
PIC32MX3XX/4XX devices provide a complete range a range of functions to the application developer. They
of programming and diagnostic features that can are summarized in Table 28-1.
increase the flexibility of any application using them.
These features allow system designers to include:
FIGURE 28-1: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING, AND TRACE PORTS
PGC1
PGD1
ICSP™
Controller
PGC2
PGD2
ICESEL
TDI
TDO JTAG
Controller Core
TCK
TMS
JTAGEN DEBUG<1:0>
TRCLK
TRD0
Instruction Trace
TRD1
Controller
TRD2
TRD3
DEBUG<1:0>
TABLE 28-1: COMPARISON OF PIC32MX3XX/4XX PROGRAMMING AND DIAGNOSTIC

FEATURES
Functions Pins Used Interface
Boundary Scan TDI, TDO, TMS and TCK pins JTAG
Programming and Debugging TDI, TDO, TMS and TCK pins EJTAG
Programming and Debugging PGCx and PGDx pins ICSP™

PIC32MX3XX/4XX
28.1 Control Registers
The programming and diagnostics module consists of
the following Special Function Registers (SFRs):
• DDPCON: Control Register for the Diagnostic
Module
• DEVCFG0: Device Configuration Register
The following table summarizes all programming and
diagnostics related registers. Corresponding registers
appear after the summary, followed by a detailed
description of each register.
TABLE 28-2: PROGRAMMING AND DIAGNOSTICS SFR SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF80_F200 DDPCON 31:24 — — — — — — — —

23:16 — — — — — — — —
15:8 — — — — — — — —
7:0 DDPUSB DDPU1 DDPU2 DDPSPI1 JTAGEN TROEN — —
TABLE 28-3: DEVICE CONFIGURATION REGISTER SUMMARY

Name
Address 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BFC0_2FFC DEVCFG0 7:0 — — — — ICESEL — DEBUG1 DEBUG0

PIC32MX3XX/4XX
REGISTER 28-1: DDPCON: DEBUG DATA PORT CONTROL REGISTER
— — — — — — — —
bit 31 bit 24

— — — — — — — —
bit 23 bit 16

— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 r-x r-x

DDPUSB DDPU1 DDPU2 DDPSPI1 JTAGEN TROEN — —
bit 7 bit 0
Legend:

bit 7 DDPUSB: Debug Data Port Enable for USB
1 = USB peripheral ignores USBFRZ (U1CNFG1<5>) setting
0 = USB peripheral follows USBFRZ setting.
bit 6 DDPU1: Debug Data Port Enable for UART1 bit
1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting
0 = UART1 peripheral follows FRZ setting
bit 5 DDPU2: Debug Data Port Enable for UART2 bit
1 = UART2 peripheral ignores FRZ (U2MODE<14) setting
0 = UART2 peripheral follows FRZ setting
bit 4 DDPSPI1: Debug Data Port Enable for SPI1 bit
1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting
0 = SPI1 peripheral follows FRZ setting
bit 3 JTAGEN: JTAG Port Enable bit
1 = Enable JTAG Port
0 = Disable JTAG Port
bit 2 TROEN: Trace Output Enable bit
1 = Enable Trace Port
0 = Disable Trace Port

PIC32MX3XX/4XX
REGISTER 28-2: DEVCFG0: DEVICE CONFIGURATION REGISTER(1)
r-1 r-1 r-1 R/P-1 r-1 r-1 r-1 R/P-1
— — — CP — — — BWP
bit 31 bit 24
r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1

— — — — PWP19 PWP18 PWP17 PWP16
bit 23 bit 16
R/P-1 R/P-1 R/P-1 R/P-1 r-1 r-1 r-1 r-1

PWP15 PWP14 PWP13 PWP12 — — — —
bit 15 bit 8
r-1 r-1 r-1 r-1 R/P-1 r-1 R/P-1 R/P-1

— — — — ICESEL — DEBUG1 DEBUG0
bit 7 bit 0
Legend:
bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit

1 = In-Circuit Emulator uses EMUC2/EMUD2 pins; In-Circuit Debugger uses PGC2/PGD2
0 = In-Circuit Emulator uses EMUC1/EMUD1 pins; In-Circuit Debugger uses PGC1/PGD1
bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = In-Circuit Emulator/Debugger disabled
10 = In-Circuit Emulator/Debugger enabled
Note 1: This summary table contains partial register definitions that only pertain to the Debug peripheral. Refer to
the PIC32MX Family Reference Manual (DS61132) for a detailed description of these registers.

PIC32MX3XX/4XX
28.2 Operation nected. The MCLR pin, which is used with PGCx to
enter and control the programming process, must also
The PIC32MX3XX/4XX of devices has multiple be connected to the programmer.
programming and Debugging options including:
A typical In-Circuit Serial Programming connection is
• In-Circuit Serial Programming via ICSP shown in Figure 28-2.
• In-Circuit Programming EJTAG
• Debugging via ICSP FIGURE 28-2: TYPICAL IN-CIRCUIT
• Debugging via EJTAG SERIAL
• Special Debug modes for Select Communication PROGRAMMING™
Peripherals CONNECTION
• Boundary Scan
28.2.1 DEVICE PROGRAMMING OPTIONS

PIC32MX
ICSP™
Note: The following sections provide a brief
overview of each programming option. For VSS VSS
more detailed information, refer to VDD VDD
“PIC32MX Flash Programming Specifica- VPP MCLR/VPP
tion” (DS61145).
CLK PGCx
Data I/O PGDx

Note: For all device programming options, a
minimum VDD requirement for Flash erase
and programming operations is required.
Refer to Section 30.1 “DC Characteris-
tics”for details.
28.2.1.1 In-Circuit Serial Programming

ICSP is Microchip’s proprietary solution to providing
microcontroller programming in the target application. 28.2.1.3 ICSP Operation
ICSP is also the most direct method to program the ICSP uses a combination of internal hardware and
device, whether the controller is embedded in a system external control to program the target device. Program-
or loaded into a device programmer. ming data and instructions are provided on PGD. ICSP
uses a special set of commands to control the overall
28.2.1.2 ICSP Interface process, combined with standard PIC32MX3XX/4XX
ICSP uses two pins as the core of its interface. The instructions to execute the actual writing of the program
Programming Data (PGD) line functions as both an memory. PGD also returns data to the external
input and an output, allowing programming data to be programmer when responding to queries.
read in and device information to be read out on com- Users who are interested in a more detailed description,
mand. The Programming Clock (PGC) line is used to or who are considering designing their own
clock in data and control the overall process. programming interface for PIC32MX3XX/4XX devices,
PIC32MX3XX/4XX devices have more than one pair of should consult the appropriate PIC32MX3XX/4XX
PGC and PGD pins; these are multiplexed with other device programming specification.
I/O or peripheral functions. Individual ICSP pin pairs
are indicated by number (e.g., PGC1/PGD1, etc.), and 28.2.1.4 Enhanced In-Circuit Serial
are generically referred to as ‘PGCx’ and ‘PGDx’. The Programming
multiple PGCx/PGDx pairs provide additional flexibility The Enhanced In-Circuit Serial Programming (ICSP)
in system design by allowing users to incorporate ICSP protocol is an extension of the original ICSP. It uses the
on the pair of pins that is least constrained by the circuit same physical interface as the original, but changes
design. All PGCx and PGDx pins are functionally tied the location and execution of programming control to a
together and behave identically, and any one pair can software application written to the PIC32MX3XX/4XX
be used for successful device programming. The only device. Use of Enhanced ICSP results in significant
limitation is that both pins from the same pair must be decrease in overall programming time.
used.
For additional information on Enhanced ICSP and the
In addition to the PGCx and PGDx pins, ICSP requires program executive, refer to the appropriate
that all voltage supply (including voltage regulator pin PIC32MX3XX/4XX device programming specification.
ENVREG) and ground pins on the device must be con-

PIC32MX3XX/4XX
28.2.1.5 EJTAG Device Programming Using The external device also provides common clock and
the JTAG Interface control signals. Depending on the implementation,
access to all test signals is provided through a
The JTAG interface can also be used to program
standardized, 4-pin interface.
PIC32MX3XX/4XX devices in their target applications.
Using EJTAG with the JTAG interface allows application A typical application incorporating the JTAG boundary
designers to include a dedicated test and programming scan interface is shown in Figure 28-3. In this example,
port into their applications, with a single 4-pin interface, a PIC32MX3XX/4XX microcontroller is daisy-chained
without imposing the circuit constraints that the ICSP to a second JTAG compliant device. Note that the TDI
interface may require. line from the external tester supplies data to the TDI pin
of the first device in the chain (in this case, the micro-
28.2.1.6 Enhanced EJTAG Programming controller). The resulting test data for this two-device
Using the JTAG Interface chain is provided from the TDO pin of the second
device to the TDO line of the tester.
Enhanced EJTAG programming uses the standard
JTAG interface but uses a programming executive writ- This section describes the JTAG module and its gen-
ten to RAM. Use of the programming executive with the eral use. Users interested in using the JTAG interface
JTAG interface provides a significant improvement in for device programming should refer to the appropriate
programming speed. PIC32MX3XX/4XX device programming specification
for more information.
28.2.2 DEBUGGING
28.2.2.1 ICSP and In-Circuit Debugging

ICSP also provides a hardware channel for the In-Cir-
cuit Debugger (ICD) which allows externally controlled
debugging of software. Using the appropriate hardware
interface and software environment, users can force
the device to single step through its code, track the
actual content of multiple registers and set software
breakpoints.
The active ICSP debugger port is selected by the
ICESEL Configuration bit.
28.2.2.2 EJTAG Debugging

The industry standard EJTAG interface allows third
party EJTAG tools to be used for debugging. Using the
EJTAG interface, memory and registers can be viewed
and modified. Breakpoints can be set and the program
execution may be stopped, started or single stepped.
28.2.3 SPECIAL DEBUG MODES FOR

SELECT COMMUNICATIONS
PERIPHERALS
To aid in debugging applications certain I/O peripherals
have a user-controllable bit to override the Freeze func-
tion in the peripheral. This allows the module to
continue to send any data, buffered within the periph-
eral, even when a debugger attempts to halt the periph-
eral. The Debug mode control bits for these peripherals
are contained in the DDPCON register.
28.2.4 JTAG BOUNDARY SCAN

The JTAG boundary scan method is the process of
adding a Shift register stage adjacent to each of the
component’s I/O pins. This permits signals at the com-
ponent boundaries to be controlled and observed,
using a defined set of scan test principles. An external
tester or controller provides instructions and reads the
results in a serial fashion.

PIC32MX3XX/4XX
FIGURE 28-3: OVERVIEW OF PIC32MX3XX/4XX-BASED JTAG COMPLIANT APPLICATION
SHOWING DAISY-CHAINING OF COMPONENTS
PIC32MX Device-Based Application
PIC32MX PIC32MX
(or other
JTAG compliant
device)
TDO
TMS
TCK
TDO
TMS
TCK
TDI
TDI
JTAG
Controller
JTAG Connector
TDI
TDO
TCK
TMS
Note: Power and ground connections not shown.
In PIC32MX3XX/4XX devices, the hardware for the The PIC32MX3XX/4XX implements a 4-pin JTAG
JTAG boundary scan is implemented as a peripheral interface with these pins:
module (i.e., outside of the CPU core) with additional • TCK (Test Clock Input): Provides the clock for test
integrated logic in all I/O ports. A logical block diagram logic.
of the JTAG module is shown in Figure 28-1. It consists
• TMS (Test Mode Select Input): Used by the TAP
of the following key elements:
to control test operations.
• TAP Interface Pins (TDI, TMS, TCK and TDO) • TDI (Test Data Input): Serial input for test
• TAP Controller instructions and data.
• Instruction Shift register and Instruction Register • TDO (Test Data Output): Serial output for test
(IR) instructions and data.
• Data Registers (DR)
28.2.4.2 JTAG Registers
28.2.4.1 Test Access Port (TAP) and TAP The JTAG module uses a number of registers of vari-
Controller ous sizes as part of its operation. In terms of bit count,
The Test Access Port (TAP) on the PIC32MX3XX/4XX most of the JTAG registers are single bit register cells,
device is a general purpose port that provides test integrated into the I/O ports. Regardless of their loca-
access to many built-in support functions and test logic tion within the module, none of the JTAG registers are
defined in IEEE 1149.1. The TAP is enabled by the located within the device data memory space, and
JTAGEN bit in the DDPCON register. The TAP is cannot be directly accessed by the user in normal
enabled, JTAGEN = 1, by default when the device exits operating modes.
Power-on-Reset (POR) or any device Reset. Once
enabled, the designated I/O pins become dedicated
TAP pins.

PIC32MX3XX/4XX
28.2.4.3 Instruction Shift Register and 28.2.4.5 Boundary Scan Register (BSR)
Instruction Register The BSR is a large Shift register that is comprised of all
The Instruction Shift register is a 5-bit shift register the I/O Boundary Scan Cells (BSCs), daisy-chained
used for selecting the actions to be performed and/or together. Each I/O pin has one BSC, each containing 3
what data registers to be accessed. Instructions are BSC registers, an input cell, an output cell and a control
shifted in, Least Significant bit first, and then decoded. cell. When the SAMPLE/PRELOAD or EXTEST instruc-
tions are active, the BSR is placed between the TDI
A list and description of implemented instructions is
and TDO pins, with the TDI pin as the input and the
given in Section 28.2.4.6 “JTAG Instructions”.
TDO pin as the output.
28.2.4.4 Data Registers The size of the BSR depends on the number of I/O pins
Once an instruction is shifted in and updated into the on the device. For example, the 100-pin PIC32MX gen-
Instruction Register, the TAP controller places certain eral purpose parts have 82 I/O pins. With 3 BSC regis-
data registers between the TDI and TDO pins. Addi- ters for each of the 82 I/Os, this yields a Boundary Scan
tional data values can then be shifted into these data register length of 244 bits. This is due to the MCLR pin
registers as needed. being an input only BSR cell. Information on the I/O
port pin count of other PIC32MX3XX/4XX devices can
The PIC32MX3XX/4XX device supports three data be found in their specific device data sheets.
registers:
• BYPASS Register: A single bit register which 28.2.4.6 JTAG Instructions
allows the boundary scan test data to pass PIC32MX3XX/4XX devices support the mandatory
through the selected device to adjacent devices. instruction set specified by IEEE 1149.1, as well as sev-
The BYPASS register is placed between the TDI eral optional public instructions defined in the specifica-
and TDO pins when the BYPASS instruction is tion. These devices also implement instructions that
active. are specific to Microchip devices.
• DEVID Register: A 32-bit part identifier. It consists The mandatory JTAG instructions are:
of an 11-bit manufacturer ID assigned by the IEEE
(29h for Microchip Technology), device part num- • BYPASS (0x1F): Used for bypassing a device in a
ber and device revision identifier. When the test chain; this allows the testing of off-chip
IDCODE instruction is active, the device ID regis- circuitry and board level interconnections.
ter is placed between the TDI and TDO pins. The • SAMPLE/PRELOAD (0x02): Captures the I/O
device data ID is then shifted out on to the TDO states of the component, providing a snapshot of
pin, on the next 32 falling edges of TCK, after the its operation.
TAP controller is in the Shift_DR. • EXTEST (0x06): Allows the external circuitry and
• MCHP Command Shift Register: An 8-bit Shift interconnections to be tested, by either forcing
register that is placed between the TDI and TDO various test patterns on the output pins, or
pins when the MCHP_CMD instruction is active. capturing test results from the input pins.
This Shift register is used to shift in Microchip Microchip has implemented optional JTAG instructions
commands. and manufacturer-specific JTAG commands in
PIC32MX3XX/4XX devices. Please refer to Table 28-4,
Table 28-5, Table 28-6 and Table 28-7.
TABLE 28-4: JTAG COMMANDS

Opcode Name Device Integration
0x1F Bypass Bypasses device in test chain
0x00 HIGHZ Places device in a high-impedance state, all pins are forced to inputs
0x01 ID Code Shifts out the device’s ID code
0x02 Sample/Preload Samples all pins or loads a specific value into output latch
0x06 EXTEST Boundary scan

PIC32MX3XX/4XX
TABLE 28-5: MICROCHIP TAP IR COMMANDS
0x01 MTAP_IDCODE Shifts out the device’s ID code
0x07 MTAP_COMMAND Configures Microchip TAP controller for DR commands
0x04 MTAP_SW_MTAP Selects Microchip TAP controller
0x05 MTAP_SW_ETAP Selects EJTAG TAP controller
TABLE 28-6: MICROCHIP TAP 8-BIT DR COMMANDS

0x00 MCHP_STATUS Performs NOP and returns status
0xD1 MCHP_ASERT_RST Requests Assert Device Reset
0xD0 MCHP_DE_ASSERT_RST Requests Deassert Device Reset
0xFC MCHP_ERASE Performs a chip erase
0xFE MCHP_FLASH_ENABLE Enables fetches and loads to the Flash from the CPU
0xFD MCHP_FLASH_DISABLE Disables fetches and loads to the Flash from the CPU
0xFF MCHP_READ_CONFIG Forces device to reread the configuration settings and initialize accordingly
TABLE 28-7: EJTAG COMMANDS

Data Length for the
Following DR
0x00 Not used
0x01 IDCODE Selects the device’s ID Code register 32 bits
0x02 Not used
0x03 IMPCODE Selects Implementation register
(2)
0x04 MTAP_SW_MTAP Selects Microchip TAP controller
0x05(2) MTAP_SW_ETAP Selects EJTAG TAP controller(1)
0x06-0x07 Not used
0x08 ADDRESS Selects the Address register 32 bits
0x09 DATA Selects the Data register 32 bits
0x0A CONTROL Selects the EJTAG Control register(1) 32 bits
(1)
0x0B ALL Selects the Address, Data, EJTAG Control register 96 bits
0x0C EJTAGBOOT Forces the CPU to take a debug exception after boot 1 bit
0x0D NORMALBOOT Makes the CPU execute the reset handler after a boot 1 bit
0x0E FASTDATA Selects the Data and Fast Data registers 1 bit
0x0F-0x1B Reserved
0x1C-0xFE Not used
0xFF Selects the Bypass register
Note 1: For complete information about EJTAG commands and protocol, refer to the EJTAG Specification
available on MIPS Technologies web site, www.mips.com.
2: Not EJTAG commands but are recognized by the Microchip implementation.

PIC32MX3XX/4XX
28.2.5 BOUNDARY SCAN TESTING (BST) • The pinout and package configuration for the
particular device
Boundary Scan Testing (BST) is the method of control-
ling and observing the boundary pins of the JTAG com- • The physical location of the TAP pins
pliant device, like those of the PIC32MX3XX/4XX, • The Device ID register and the device ID
utilizing software control. BST can be used to test con- • The length of the Instruction Register
nectivity between devices by daisy-chaining JTAG • The supported BST instructions and their binary
compliant devices to form a single scan chain. Several codes
scan chains can exist on a PCB to form multiple scan
• The length and structure of the Boundary Scan
chains. These multiple scan chains can then be driven
register
simultaneously to test many components in parallel.
Scan chains can contain both JTAG compliant devices • The boundary scan cell definition
and non-JTAG compliant devices. Device-specific BSDL files are available at Microchip’s
A key advantage of BST is that it can be implemented web site, www.microchip.com.
without physical test probes; all that is needed is a 4- The name for each BSDL file is the device name and
wire interface and an appropriate test platform. Since silicon revision–for example, PIC32MX3XX/4XX
JTAG boundary scan has been available for many 320F128L_A2.BSD is the BSDL file for
years, many software tools exist for testing scan chains PIC32MX3XX/4XX 320F128L, silicon revision A2.
without the need for extensive physical probing. The
main drawback to BST is that it can only evaluate digital 28.3 Interrupts
signals and circuit continuity; it cannot measure input or
output voltage levels or currents. Programming and debugging operations are not
performed during code execution and are therefore not
28.2.5.1 Related JTAG Files affected by interrupts. Trace operations will report the
change in code execution when a interrupt occurs but
To implement BST, all JTAG test tools will require a
the trace controller is not affected by interrupts.
Boundary Scan Description Language (BSDL) file.
BSDL is a subset of VHDL (VHSIC Hardware Descrip-
tion Language), and is described as part of IEEE. 28.4 I/O Pins
1149.1. The device-specific BSDL file describes how In order to interface the numerous programming and
the standard is implemented on a particular device and debugging option available and still provide peripheral
how it operates. access to the pins, the pins are multiplexed with periph-
The BSDL file for a particular device includes the erals. Table describes the function of the programming
following: and debug related pins.
TABLE 28-8: PROGRAMMING AND DEBUGGING PIN FUNCTIONS

Function
Pin Name Boundary Program Debug Trace Description Comments
Scan Mode Mode Mode Mode
Used to enter ICSP™
MCLR MCLR Master Clear mode and to override
JTAGEN (DDPCON<3>)
PGC1 —
PGC1/EMUC1 General ICSP™ Clock
— EMUC1
Purpose I/O
PGD1 —
PGD1/EMUD1 or Peripheral ICSP™ Data Selected by ICESEL
EMUD1 (DEVCFG0<3>) and
PGC2 — DEBUG Configuration
PGC2/EMUC2 General Alternate ICSP™ Clock bits (DEVCFG0<1:0>)
EMUC1
Purpose I/O
PGD2 —
PGD2/EMUD2 or Peripheral Alternate ICSP™ Data
EMUD1

PIC32MX3XX/4XX
TABLE 28-8: PROGRAMMING AND DEBUGGING PIN FUNCTIONS
Function
Pin Name Boundary Program Debug Trace Description Comments
Scan Mode Mode Mode Mode
TRCLK TRCLK Trace Clock
TRD0 TRD0
Controlled by TROEN
TRD1 General Purpose I/O or Peripheral TRD1
Trace Data bit (DDPCON<2>)
TRD2 TRD2
TRD3 TRD3
TMS TMS TMS TMS TMS JTAG Test Mode Select
TCK TCK TCK TCK TCK JTAG Clock
Controlled by JTAGEN
TDO TDO TDO TDO TDO JTAG Data Out
bit (DDPCON<3>)
TDI TDI TDI TDI TDI JTAG Data In

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
29.0 DEVELOPMENT SUPPORT 29.1 MPLAB Integrated Development
Environment Software
The PIC® microcontrollers are supported with a full
range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
operating system-based application that contains:
• Assemblers/Compilers/Linkers
• A single graphical interface to all debugging tools
- MPASMTM Assembler
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- Programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - Emulator (sold separately)
- MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately)
• Simulators • A full-featured editor with color-coded context
- MPLAB SIM Software Simulator • A multiple project manager
• Emulators • Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
• High-level source code debugging
- MPLAB REAL ICE™ In-Circuit Emulator
• Visual device initializer for easy register
• In-Circuit Debugger
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
- PICSTART® Plus Development Programmer windows
- MPLAB PM3 Device Programmer • Extensive on-line help
- PICkit™ 2 Development Programmer • Integration of select third party tools, such as
• Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR
Boards and Evaluation Kits C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

PIC32MX3XX/4XX
29.2 MPASM Assembler 29.5 MPLAB ASM30 Assembler, Linker
The MPASM Assembler is a full-featured, universal
and Librarian
macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable
The MPASM Assembler generates relocatable object machine code from symbolic assembly language for
files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the
files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler
reference, absolute LST files that contain source lines generates relocatable object files that can then be
and generated machine code and COFF files for archived or linked with other relocatable object files and
debugging. archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler features include:
• Support for the entire dsPIC30F instruction set
• Integration into MPLAB IDE projects
• Support for fixed-point and floating-point data
• User-defined macros to streamline
assembly code • Command line interface
• Conditional assembly for multi-purpose • Rich directive set
source files • Flexible macro language
• Directives that allow complete control over the • MPLAB IDE compatibility
assembly process
29.6 MPLAB SIM Software Simulator
29.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code
C Compilers development in a PC-hosted environment by simulat-
The MPLAB C18 and MPLAB C30 Code Development ing the PIC MCUs and dsPIC® DSCs on an instruction
Systems are complete ANSI C compilers for level. On any given instruction, the data areas can be
Microchip’s PIC18 and PIC24 families of microcon- examined or modified and stimuli can be applied from
trollers and the dsPIC30 and dsPIC33 family of digital a comprehensive stimulus controller. Registers can be
signal controllers. These compilers provide powerful logged to files for further run-time analysis. The trace
integration capabilities, superior code optimization and buffer and logic analyzer display extend the power of
ease of use not found with other compilers. the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE The MPLAB SIM Software Simulator fully supports
debugger. symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
29.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside
MPLIB Object Librarian of the hardware laboratory environment, making it an
The MPLINK Object Linker combines relocatable excellent, economical software development tool.
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS61143E-page 590 PreliminaryPreliminary © 2008 Microchip Technology Inc.

PIC32MX3XX/4XX
29.7 MPLAB ICE 2000 29.9 MPLAB ICD 2 In-Circuit Debugger
High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low-cost, run-time development tool,
The MPLAB ICE 2000 In-Circuit Emulator is intended connecting to the host PC via an RS-232 or high-speed
to provide the product development engineer with a USB interface. This tool is based on the Flash PIC
complete microcontroller design tool set for PIC MCUs and can be used to develop for these and other
microcontrollers. Software control of the MPLAB ICE PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
2000 In-Circuit Emulator is advanced by the MPLAB the in-circuit debugging capability built into the Flash
Integrated Development Environment, which allows devices. This feature, along with Microchip’s In-Circuit
editing, building, downloading and source debugging Serial ProgrammingTM (ICSPTM) protocol, offers cost-
from a single environment. effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and
system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step-
ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and
the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables
different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB
ICE 2000 In-Circuit Emulator allows expansion to ICD 2 also serves as a development programmer for
support new PIC microcontrollers. selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with 29.10 MPLAB PM3 Device Programmer
advanced features that are typically found on more
expensive development tools. The PC platform and The MPLAB PM3 Device Programmer is a universal,
Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable
chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for
simple, unified application. maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
29.8 MPLAB REAL ICE In-Circuit
package types. The ICSP™ cable assembly is included
Emulator System as a standard item. In Stand-Alone mode, the MPLAB
MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program
Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set
Microchip Flash DSC and MCU devices. It debugs and code protection in this mode. The MPLAB PM3
programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable.
with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and
the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large
included with each kit. memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.

PIC32MX3XX/4XX
29.11 PICSTART Plus Development 29.13 Demonstration, Development, and
Programmer Evaluation Boards
The PICSTART Plus Development Programmer is an A wide variety of demonstration, development, and
easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC
connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func-
Integrated Development Environment software makes tional systems. Most boards include prototyping areas for
using the programmer simple and efficient. The adding custom circuitry and provide application firmware
PICSTART Plus Development Programmer supports and source code for examination and modification.
most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs,
Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232
PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers, and additional
The PICSTART Plus Development Programmer is CE EEPROM memory.
compliant.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
29.12 PICkit 2 Development Programmer
circuits, and for learning about various microcontroller
The PICkit™ 2 Development Programmer is a low-cost applications.
programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon-
an easy-to-use interface for programming many of stration/development board series of circuits, Microchip
Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software
Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN,
includes a prototyping development board, twelve IrDA®, PowerSmart battery management, SEEVAL®
sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate
Lite C compiler, and is designed to help get up to speed sensing, plus many more.
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop Check the Microchip web page (www.microchip.com)
applications using Microchip’s powerful, mid-range for the complete list of demonstration, development
Flash memory family of microcontrollers. and evaluation kits.
DS61143E-page 592 PreliminaryPreliminary © 2008 Microchip Technology Inc.

PIC32MX3XX/4XX
30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided
in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions
for extended periods may affect device reliability. Functional operation of the device at these or any other conditions
above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)
Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +5.5V
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 1)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 1) ....................................................................................................200 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.

PIC32MX3XX/4XX
30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS VS. VOLTAGE

VDD Range Temp. Range Max. Frequency
Characteristic
(in Volts) (in °C) PIC32MX3XX/4XX
DC5 2.3-3.6V -40°C to +85°C 80 MHz(1)
Note 1: 40 MHz maximum for PIC32MX 40MHz family variants.
TABLE 30-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typical Max. Unit
PIC32MX3XX/4XX
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL) )
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS

Characteristics Symbol Typical Max. Unit Notes
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) θJA 52.3 — °C/W 1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) θJA 38.3 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.3V to 3.6V
DC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
No.
Operating Voltage
DC10 Supply Voltage
VDD 2.3 — 3.6 V
DC12 VDR RAM Data Retention Voltage(2) — 1.75 — V
DC16 VPOR VDD Start Voltage 1.75 — 1.95 V
to Ensure Internal
Power-on Reset Signal
DC17 SVDD VDD Rise Rate 0.05 — — V/ms
to Ensure Internal
Power-on Reset Signal
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: This is the limit to which VDD can be lowered without losing RAM data.

PIC32MX3XX/4XX
TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)(1)
Parameter
Typical(3) Max. Units Conditions
No.
Operating Current (IDD)(2)
DC20 — 13 mA 2.3V
DC20a 8.5 — mA —
DC20b — 13 mA 3.6V 4 MHz
DC20c 4.0 — mA Code executing from —
SRAM
DC21 — 32 mA 2.3V
DC21a 23.5 — mA —
DC21b — 32 mA 3.6V 20 MHz
DC21c 16.4 — mA Code executing from
—
SRAM
DC22 — 61 mA 2.3V
DC22a 48 — mA —
DC22b — 61 mA 3.6V 60 MHz
DC22c 45 — mA Code executing from
—
SRAM
DC23 — 75 mA 2.3V
DC23a 55 — mA —
DC23b — 75 mA 3.6V 80 MHz
DC23c 55 — mA Code executing from
—
SRAM
DC24 — 97 µA -40°C
DC24a — 129 µA +25°C 2.3V
DC24b — 670 µA +85°C
DC25 94 — µA -40°C
DC25a 125 — µA +25°C
DC25b 302 — µA +85°C 3.3V LPRC (31 kHz)
DC25c 71 — µA Code executing from
SRAM
DC26 — 107 µA -40°C
DC26a — 180 µA +25°C 3.6V
DC26b — 697 µA +85°C
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type as well as temperature can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by
external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data mem-
ory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and
SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and FSCM are
disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.

PIC32MX3XX/4XX
TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Parameter
No.
Idle Current (IIDLE): Core OFF, Clock ON Base Current(1)
DC30 — 5 mA 2.3V
DC30a 1.4 — mA — 4 MHz
DC30b — 5 mA 3.6V
DC31 — 15 mA 2.3V
DC31a 13 — mA — 20 MHz
DC31b — 17 mA 3.6V
DC32 — 22 mA 2.3V
DC32a 20 — mA — 60 MHz
DC32b — 25 mA 3.6V
DC33 — 29 mA 2.3V
DC33a 24 — mA — 80 MHz
DC33b — 32 mA 3.6V
DC34 — 36 µA -40°C
DC34a — 62 µA +25°C 2.3V
DC34b — 392 µA +85°C
DC35 35 — µA -40°C
DC35a 65 — µA +25°C 3.3V LPRC (31 kHz)
DC35b 242 — µA +85°C
DC36 — 43 µA -40°C
DC36a — 106 µA +25°C 3.6V
DC36b — 414 µA +85°C
Note 1: The test conditions for base IDLE current measurements are as follows: System clock is enabled and
PBCLK divisor = 1:8. CPU in IDLE mode (CPU core halted). Only digital peripheral modules are enabled
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and
pulled to VSS. MCLR = VDD.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

PIC32MX3XX/4XX
TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
DC CHARACTERISTICS
Parameter
No.
Power-Down Current (IPD)(1)
DC40 — 28 μA -40°C
DC40a — 28 μA +25°C 2.3V
DC40b — 300 μA +85°C
DC40c 39 — μA
Base Power-Down Current
DC40d — 70 μA -40°C
DC40e — 70 μA +25°C
3.6V
DC40g — 300 (5)
μA +70°C
DC40f — 600 μA +85°C
Module Differential Current
DC41 — 10 μA -40°C
DC41a — 10 μA +25°C 2.3V
DC41b — 10 μA +85°C
DC41c 5 — μA Watchdog Timer Current: ΔIWDT(3)
DC41d — 10 μA -40°C
DC41e — 10 μA +25°C 3.6V
DC41f — 12 μA +85°C
DC42 — 10 μA -40°C
DC42a — 17 μA +25°C 2.3V
DC42b — 37 μA +85°C
RTCC + Timer1 w/32kHz Crystal:
DC42c 23 — μA
ΔIRTCC(3)
DC42e — 10 μA -40°C
DC42f — 30 μA +25°C 3.6V
DC42g — 44 μA +85°C
DC42 — 1100 μA -40°C
DC42a — 1100 μA +25°C 2.5V
DC42b — 1000 μA +85°C
DC42c 880 — μA ADC: ΔIADC(3,4)
DC42e — 1100 μA -40°C
DC42f — 1100 μA +25°C 3.6V
DC42g — 1000 μA +85°C
Note 1: Base IPD is measured with all digital peripheral modules enabled (ON bit = 1) and being clocked, CPU
clock is disabled. All I/Os are configured as outputs and pulled low. WDT and FSCM are disabled.
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.

PIC32MX3XX/4XX
TABLE 30-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
DC CHARACTERISTICS stated)
Param.
No.
VIL Input Low Voltage
DI10 I/O pins:
with TTL Buffer VSS — 0.15 VDD VSS
with Schmitt Trigger Buffer VSS — 0.2 VDD VSS
DI15 MCLR VSS — 0.2 VDD V
DI16 OSC1 (XT mode) VSS — 0.2 VDD V
DI17 OSC1 (HS mode) VSS — 0.2 VDD V
DI18 SDAx, SCLx VSS — 0.3 VDD V SMBus disabled
DI19 SDAx, SCLx VSS — 0.8 V SMBus enabled
VIH Input High Voltage
DI20 I/O pins:
with Analog Functions 0.8 VDD — VDD V
Digital Only 0.8 VDD — V
with TTL Buffer 0.25VDD + 0.8V — 5.5 VSS
with Schmitt Trigger Buffer 0.8 VDD — 5.5 VSS
DI25 MCLR 0.8 VDD — VDD V
DI26 OSC1 (XT mode) 0.7 VDD — VDD V
DI27 OSC1 (HS mode) 0.7 VDD — VDD V
DI28 SDAx, SCLx 0.7 VDD — VDD V SMBus disabled
DI29 SDAx, SCLx 2.1 — VDD V SMBus enabled,
2.3V ≤ VPIN ≤ VDD
DI30 ICNPU CNxx Pull up Current 50 250 400 μA VDD = 3.3V, VPIN = VSS
IIL Input Leakage Current(2,3)
DI50 I/O Ports — — +1 μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI51 Analog Input Pins — — +1 μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI55 MCLR — — +1 μA VSS ≤ VPIN ≤ VDD
DI56 OSC1 — — +1 μA VSS ≤ VPIN ≤ VDD,
XT and HS modes
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.

PIC32MX3XX/4XX
TABLE 30-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
DC CHARACTERISTICS stated)
Param.
No.
VOL Output Low Voltage
DO10 I/O Ports — — 0.4 V IOL = 7 mA, VDD = 3.6V
— — 0.4 V IOL = 6 mA, VDD = 2.3V
DO16 OSC2/CLKO — — 0.4 V IOL = 3.5 mA, VDD = 3.6V
— — 0.4 V IOL = 2.5 mA, VDD = 2.3V
VOH Output High Voltage
DO20 I/O Ports 2.4 — — V IOH = -12 mA, VDD = 3.6V
1.4 — — V IOH = -12 mA, VDD = 2.3V
DO26 OSC2/CLKO 2.4 — — V IOH = -12 mA, VDD = 3.6V
1.4 — — V IOH = -12 mA, VDD = 2.3V
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 30-10: DC CHARACTERISTICS: PROGRAM MEMORY

Param.
No.
Program Flash Memory
D130 EP Cell Endurance 1000 — — E/W -40°C to +85°C
D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating
voltage
D132 VPEW VDD for Erase or Write 3.0 — 3.6 V
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated
D135 IDDP Supply Current during — 10 — mA
Programming
TWW Word Write Cycle Time 20 — 40 μs
D136 TRW Row Write Cycle Time(2) 3 4.5 — ms
(128 words per row)
D137 TPE Page Erase Cycle Time 20 — 40 ms
TCE Chip Erase Cycle Time 20 — 40 ms
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus
loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The
default Arbitration mode is mode 1 (cpu has lowest priority).

PIC32MX3XX/4XX
TABLE 30-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
Required Flash wait states SYSCLK Units Comments
0 Wait State 0 to 30 MHz
1 Wait State 31 to 60
2 Wait States 61 to 80
Note 1: 40 MHz maximum for PIC32MX 40MHz family variants.
TABLE 30-12: COMPARATOR SPECIFICATIONS

Operating temperature-40°C ≤ TA ≤ +85°C for Industrial
Param.
Symbol Characteristics Min. Typical Max. Units Comments
No.
D300 VIOFF Input Offset Voltage — ±7.5 ±25 mV
D301 VICM Input Common Mode Voltage* 0 — VDD V
D302 CMRR Common Mode Rejection Ratio* 55 — — dB
D303 TRESP Response Time*(1) — 150 400 nsec
D304 TMC2OV Comparator Mode Change to — — 10 μs
Output Valid*
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
TABLE 30-13: VOLTAGE REFERENCE SPECIFICATIONS

Param.
No.
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — — 1/2 LSb
D312 TSET Settling Time(1) — — 10 μs
Note 1: Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.
TABLE 30-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Param.
No.
D320 VDDCORE Regulator Output Voltage 1.62 1.80 1.98 V
D321 CEFC External Filter Capacitor Value 4.7 10 — μF Capacitor must be low series
resistance (< 3 ohms)
D322 TPWRT — 64 — ms ENVREG = 0

PIC32MX3XX/4XX
30.2 AC Characteristics and Timing
Parameters
The information contained in this section defines PIC32MX3XX/4XX AC characteristics and timing parameters.
TABLE 30-15: AC CHARACTERISTICS

(unless otherwise stated)
AC CHARACTERISTICS
Operating voltage VDD range.
FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464Ω
CL = 50 pF for all pins
VSS 50 pF for OSC2 pin (EC mode)
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS (unless otherwise stated)
Param.
No.
DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode
and are not tested.

PIC32MX3XX/4XX
FIGURE 30-2: EXTERNAL CLOCK TIMING
OS20 OS30 OS31
OSC1
OS30 OS31
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.
No.
OS10 FOSC External CLKI Frequency DC — 50(3) MHz EC
(External clocks allowed only 4 — 50(3) MHz ECPLL(4)
in EC and ECPLL modes)
OS11 Oscillator Crystal Frequency 3 — 10 MHz XT
OS12 4 — 10 MHz XTPLL(4)
OS13 10 — 25 MHz HS
OS14 10 — 25 MHz HSPLL(4)
OS15 32 32.768 100 kHz SOSC
OS20 TOSC TOSC = 1/FOSC = TCY(2) — — — — See parameter
OS10 for FOSC
value
OS30 TOSL, External Clock In (OSC1) 0.45 x TOSC — — nsec EC
TOSH High or Low Time
OS31 TOSR, External Clock In (OSC1) — — 0.05 x TOSC nsec EC
TOSF Rise or Fall Time
OS40 TOST Oscillator Start-up Timer Period — 1024 — TOSC -40°C to +85°C
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
OS41 TFSCM Primary Clock Fail Safe — 2 — ms -40°C to +85°C
Time-out Period
and are not tested.
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an exter-
nal clock applied to the OSC1/CLKI pin.
3: 40 MHz maximum for PIC32MX 40 MHz family variants.
4: PLL input requirements: 4 MHZ ≤ FPLLIN ≤ 5 MHZ (use PLL prescaler to reduce FOSC).

PIC32MX3XX/4XX
TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Param.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
No.
OS50 FPLLI PLL Voltage Controlled 4 — 5 MHz ECPLL, HSPLL, MSPLL,
Oscillator (VCO) Input FRCPLL modes
Frequency Range
OS51 FSYS On-Chip VCO System 60 — 230 MHz
Frequency
OS52 TLOCK PLL Start-up Time (Lock Time) — — 2 ms
OS53 DCLK CLKO Stability (Jitter) -2 1 2 % Measured over 100 ms
period
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 30-19: INTERNAL FRC ACCURACY

Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param.
Characteristics Min. Typical Max. Units Conditions
No.
Internal FRC Accuracy @ 8.00 MHz(1)

F20 FRC -2 — +2 % -40°C ≤ TA ≤ +85°C VDD = 2.3 to 3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL RC ACCURACY

Param.
Characteristics Min. Typical Max. Units Conditions
No.
LPRC @ 31.25 kHz(1)

F21 -15 — +15 % -40°C ≤ TA ≤ +85°C VDD = 2.3 to 3.6V
Note 1: Change of LPRC frequency as VDD changes.

PIC32MX3XX/4XX
FIGURE 30-3: I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-21: I/O TIMING REQUIREMENTS

Param.
No.
DO31 TIOR Port Output Rise Time — 5 10 nsec
DO32 TIOF Port Output Fall Time — 5 10 nsec
DI35 TINP INTx Pin High or Low Time 10 — — nsec
DI40 TRBP CNx High or Low Time (input) 2 — — TSYSCLK
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

PIC32MX3XX/4XX
FIGURE 30-4: POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power Up Sequence
(See Note 2)
CPU starts fetching code

SY00
(TPU)
(See Note 1)

Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR (TSYSDLY)
SY02
Power Up Sequence
(See Note 2)

SY00 SY10
(TPU) (TOST)
(See Note 1)
External VDDCORE Provided

VDD
VPOR VDDCORE
(TSYSDLY)
SY02
Power Up Sequence
(See Note 3)
SY01
(TPWRT)
(See Note 1)
Note 1: The Power Up Period will be extended if the Power Up Sequence completes before the device
exits from BOR (VDD < VDDMIN).
2: Includes Interval Voltage Regulator stabilization delay.
3: Power-Up Timer (PWRT); only active when the Internal Voltage Regulator is disabled

PIC32MX3XX/4XX
FIGURE 30-5: EXTERNAL RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR (TSYSDLY)
(SY30) SY02
Reset Sequence
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY)

SY02
Reset Sequence

TOST
(SY10)
TABLE 30-22: RESETS TIMING

Param.
No.
SY00 TPU Power-up Period — 400 600 μs -40°C to +85°C
SY01 TPWRT Power-up Period 48 64 80 ms -40°C to +85°C
External VDDCORE Applied
(Power-Up-Timer Active)
SY02 TSYSDLY System Delay Period: — 1 μs — — -40°C to +85°C
Time required to reload Device +
Configuration Fuses plus SYSCLK 8 SYSCLK
delay before first instruction is cycles
fetched.
SY20 TMCLR MCLR Pulse Width (low) — 2 — μs -40°C to +85°C
SY30 TBOR BOR Pulse Width (low) — 1 — μs -40°C to +85°C
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.

PIC32MX3XX/4XX
FIGURE 30-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

Param.
Symbol Characteristics Min. Typical Max. Units Conditions
No.
TA10 TTXH TxCK High Time Synchronous, 10 — — nsec Must also meet
with prescaler parameter TA15
Asynchronous, 10 — — nsec
with prescaler
Asynchronous 10 — — nsec
TA11 TTXL TxCK Low Time Synchronous, 10 — — nsec Must also meet
with prescaler parameter TA15
Asynchronous, 10 — — nsec
with prescaler
TA15 TTXP TxCK Input Period Synchronous, Greater of: — — nsec
with prescaler 10 nsec or
(2 * TPB + 10)
Asynchronous, Greater of: — — — N = prescale
with prescaler 10 nsec or value
(2 * TPB + 10)/N (1, 8, 64, 256)
OS60 FT 1 SOSC1/T1CK Oscillator Input 32 — 100 kHz
Frequency Range (oscillator
enabled by setting TCS bit
(T1CON<1>))
TA20 TCKEXTMRL Delay from External TxCK Clock — 10 nsec
Edge to Timer Increment
Note 1: Timer1 is a Type A.

PIC32MX3XX/4XX
TABLE 30-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol Characteristics Min. Max. Units Conditions
No.
TB10 TTXH TxCK High Time Synchronous, Greater of: — nsec Must also meet parameter
no prescaler 10 nsec or TB15
(TPB + 5)
Synchronous, 20 — nsec
with prescaler
TB11 TTXL TxCK Low Time Synchronous, Greater of: — nsec Must also meet parameter
no prescaler 10 nsec or TB15
(TPB + 5)
Synchronous, 10 — nsec
with prescaler
TB15 TTXP TxCK Input Synchronous, Greater of: — nsec N = prescale value
Period no prescaler 10 nsec or (1, 2, 4, 8, 16, 32, 64, 256)
(2 * TPB + 10)
Synchronous, Greater of:
with prescaler 10 nsec or
(2*TPB + 10)/N
TB20 TCKEXTMRL Delay from External TxCK Clock — 5 nsec
Edge to Timer Increment

PIC32MX3XX/4XX
FIGURE 30-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10 IC11
IC15
TABLE 30-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS

Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
IC10 TCCL ICx Input Low Time No prescaler Greater of: — nsec
10 nsec or
(TPB + 5)
With prescaler 10 — nsec
IC11 TCCH ICx Input High Time No prescaler Greater of: — nsec
20 nsec or
(TPB + 5)
With prescaler 10 — nsec
IC15 TCCP ICx Input Period Greater of: — nsec N = prescale value
10 nsec or (1, 4, 16)
(2*TPB + 10)/N
FIGURE 30-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode) OC11 OC10

PIC32MX3XX/4XX
TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Param.
No.
OC10 TCCF OCx Output Fall Time — — — nsec See parameter DO32
OC11 TCCR OCx Output Rise Time — — — nsec See parameter DO31
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 30-9: OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
TABLE 30-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

Param
Symbol Characteristics(1) Min Typical(2) Max Units Conditions
No.
OC15 TFD Fault Input to PWM I/O — — 25 nsec
Change
OC20 TFLT Fault Input Pulse Width 50 — — nsec
and are not tested.

PIC32MX3XX/4XX
FIGURE 30-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11 SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SDOx MSb Bit 14 - - - - - -1 LSb
SP31 SP30
SDIx MSb In Bit 14 - - - -1 LSb In
SP40 SP41
TABLE 30-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Param.
No.
SP10 TSCL SCKx Output Low Time(3) TSCK/2 — — nsec
SP11 TSCH SCKx Output High Time(3) TSCK/2 — — nsec
SP20 TSCF SCKx Output Fall Time(4) — — — nsec See parameter DO32
SP21 TSCR SCKx Output Rise Time(4) — — — nsec See parameter DO31
SP30 TDOF SDOx Data Output Fall Time(4) — — — nsec See parameter DO32
SP31 TDOR SDOx Data Output Rise Time(4) — — — nsec See parameter DO31
SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 nsec
TSCL2DOV SCKx Edge
SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — nsec
TDIV2SCL to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — nsec
TSCL2DIL to SCKx Edge
3: The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.

PIC32MX3XX/4XX
FIGURE 30-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11 SP10 SP21 SP20
SCKX
(CKP = 1)
SP35
SP20 SP21
SDOX MSb Bit 14 - - - - - -1 LSb
SP30,SP31
SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41
TABLE 30-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Operating temperature -40°C ≤ TA ≤ +85°Cfor Industrial
Param.
No.
SP10 TSCL SCKx Output Low Time(3) TSCK/2 — — nsec
SP11 TSCH SCKx Output High Time(3) TSCK/2 — — nsec
SP20 TSCF SCKx Output Fall Time(4) — — — nsec See parameter DO32
SP21 TSCR SCKx Output Rise Time(4) — — — nsec See parameter DO31
SP30 TDOF SDOx Data Output Fall Time(4) — — — nsec See parameter DO32
SP31 TDOR SDOx Data Output Rise — — — nsec See parameter DO31
Time(4)
TSCL2DOV SCKx Edge
SP36 TDOV2SC, SDOx Data Output Setup to 15 — — nsec
TDOV2SCL First SCKx Edge
and are not tested.
3: The minimum clock period for SCKx is 40 nsec. Therefore, the clock generated in Master mode must not
violate this specification.

PIC32MX3XX/4XX
FIGURE 30-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP50 SP52
SCKX
(CKP = 0)
SP71 SP70
SP73 SP72
SCKX
(CKP = 1)
SP72 SP73
SP35
SDOX MSb Bit 14 - - - - - -1 LSb
SP30,SP31 SP51
SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41

PIC32MX3XX/4XX
TABLE 30-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Param.
No.
SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — nsec
SP71 TSCH SCKx Input High Time(3) TSCK/2 — — nsec
SP72 TSCF SCKx Input Fall Time — 5 10 nsec
SP73 TSCR SCKx Input Rise Time — 5 10 nsec
(4)
SP30 TDOF SDOx Data Output Fall Time — — — nsec See parameter DO32
SP31 TDOR SDOx Data Output Rise Time(4) — — — nsec See parameter DO31
TSCL2DOV SCKx Edge
SP50 TSSL2SCH, SSx ↓ to SCKx ↑ or SCKx Input 60 — — nsec
TSSL2SCL
SP51 TSSH2DOZ SSx ↑ to SDOx Output 5 — 25 nsec
High-Impedance(3)
SP52 TSCH2SSH SSx after SCKx Edge TSCK + 20 — — nsec —
TSCL2SSH
and are not tested.
3: The minimum clock period for SCKx is 40 nsec.

PIC32MX3XX/4XX
FIGURE 30-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP50 SP52
SCKx
(CKP = 0)
SP71 SP70 SP73 SP72
SCKx
(CKP = 1)
SP35
SP72 SP73
SP52
SDOx MSb Bit 14 - - - - - -1 LSb
SP30,SP31 SP51
SDIx
SDI
MSb In Bit 14 - - - -1 LSb In
SP40 SP41

PIC32MX3XX/4XX
TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Param
.No.
SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — nsec
SP71 TSCH SCKx Input High Time(3) TSCK/2 — — nsec
SP72 TSCF SCKx Input Fall Time — 5 10 nsec
SP73 TSCR SCKx Input Rise Time — 5 10 nsec
SP30 TDOF SDOx Data Output Fall Time(4) — — — nsec See parameter
DO32
SP31 TDOR SDOx Data Output Rise Time(4) — — — nsec See parameter
DO31
TSCL2DOV SCKx Edge
SP50 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ 60 — — nsec
TSSL2SCL Input
SP51 TSSH2DOZ SSx ↑ to SDOX Output 5 — 25 nsec
High-Impedance(4)
SP52 TSCH2SSH SSx ↑ after SCKx Edge TSCK + 20 — — nsec
TSCL2SSH
SP60 TSSL2DOV SDOx Data Output Valid after — — 25 nsec
SSx Edge
and are not tested.
3: The minimum clock period for SCKx is 40 nsec.

PIC32MX3XX/4XX
FIGURE 30-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
FIGURE 30-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM21

IM10
SCLx
IM11 IM26
IM10 IM25 IM33
SDAx
In
IM40 IM40 IM45
SDAx
Out

PIC32MX3XX/4XX
TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Param.
Symbol Characteristics Min.(1) Max. Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) — μs —
400 kHz mode TPB * (BRG + 2) — μs —
1 MHz mode (2)
TPB * (BRG + 2) — μs —
IM11 THI:SCL Clock High Time 100 kHz mode TPB * (BRG + 2) — μs —
400 kHz mode TPB * (BRG + 2) — μs —
1 MHz mode (2)
TPB * (BRG + 2) — μs —
IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 nsec CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 nsec from 10 to 400 pF
1 MHz mode(2) — 100 nsec
IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 nsec CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 nsec from 10 to 400 pF
IM25 TSU:DAT Data Input 100 kHz mode 250 — nsec —
Setup Time 400 kHz mode 100 — nsec
1 MHz mode(2) 100 — nsec
IM26 THD:DAT Data Input 100 kHz mode 0 — μs —
Hold Time 400 kHz mode 0 0.9 μs
1 MHz mode(2) 0 0.3 μs
IM30 TSU:STA Start Condition 100 kHz mode TPB * (BRG + 2) — μs Only relevant for
Setup Time 400 kHz mode — μs Repeated Start
TPB * (BRG + 2)
condition
1 MHz mode(2) TPB * (BRG + 2) — μs
IM31 THD:STA Start Condition 100 kHz mode TPB * (BRG + 2) — μs After this period, the
Hold Time 400 kHz mode — μs first clock pulse is
TPB * (BRG + 2)
generated
1 MHz mode(2) TPB * (BRG + 2) — μs
IM33 TSU:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — μs —
Setup Time 400 kHz mode — μs
TPB * (BRG + 2)
1 MHz mode (2)
TPB * (BRG + 2) — μs
IM34 THD:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — nsec —
Hold Time 400 kHz mode TPB * (BRG + 2) — nsec
(2)
1 MHz mode TPB * (BRG + 2) — nsec
IM40 TAA:SCL Output Valid 100 kHz mode — 3500 nsec —
From Clock 400 kHz mode — 1000 nsec —
1 MHz mode(2) — 350 nsec —
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be
400 kHz mode 1.3 — μs free before a new
transmission can start
1 MHz mode (2)
0.5 — μs
IM50 CB Bus Capacitive Loading — 400 pF
Note 1: BRG is the value of the I2C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC32MX3XX/4XX
FIGURE 30-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
FIGURE 30-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS21

IS10
SCLx
IS30 IS26
IS31 IS25 IS33
SDAx
In
IS40 IS40 IS45
SDAx
Out

PIC32MX3XX/4XX
TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Param.
Symbol Characteristics Min. Max. Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs PBCLK must operate at a
minimum of 800 KHz
400 kHz mode 1.3 — μs PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode(1) 0.5 — μs
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs PBCLK must operate at a
minimum of 800 KHz.
400 kHz mode 0.6 — μs PBCLK must operate at a
minimum of 3.2 MHz
IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 nsec CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 nsec 10 to 400 pF
IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 nsec CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 nsec 10 to 400 pF
IS25 TSU:DAT Data Input 100 kHz mode 250 — nsec
Setup Time 400 kHz mode 100 — nsec
1 MHz mode(1) 100 — nsec
IS26 THD:DAT Data Input 100 kHz mode 0 — nsec
Hold Time 400 kHz mode 0 0.9 μs
1 MHz mode (1)
0 0.3 μs
IS30 TSU:STA Start Condition 100 kHz mode 4700 — μs Only relevant for Repeated
Setup Time 400 kHz mode 600 — μs Start condition
1 MHz mode(1) 250 — μs
IS31 THD:STA Start Condition 100 kHz mode 4000 — μs After this period, the first
Hold Time 400 kHz mode 600 — μs clock pulse is generated
1 MHz mode(1) 250 — μs
IS33 TSU:STO Stop Condition 100 kHz mode 4000 — μs
Setup Time 400 kHz mode 600 — μs
1 MHz mode (1) 600 — μs
IS34 THD:STO Stop Condition 100 kHz mode 4000 — nsec
Hold Time 400 kHz mode 600 — nsec
1 MHz mode(1) 250 nsec
IS40 TAA:SCL Output Valid From 100 kHz mode 0 3500 nsec
Clock 400 kHz mode 0 1000 nsec
1 MHz mode(1) 0 350 nsec
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free
400 kHz mode 1.3 — μs before a new transmission
can start
IS50 CB Bus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

PIC32MX3XX/4XX
TABLE 30-34: ADC MODULE SPECIFICATIONS
Param.
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of — Lesser of V
VDD – 0.3 VDD + 0.3
or 2.5 or 3.6
AD02 AVSS Module VSS Supply VSS — VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.0 — AVDD V See Note 1
AD05a 2.5 — 3.6 V VREFH = AVDD
AD06 VREFL Reference Voltage Low AVSS — VREFH – V See Note 1
2.0
AD07 VREF Absolute Reference 2.0 — AVDD V
Voltage
(VREFH – VREFL)
AD08 IREF Current Drain — 250 400 μA ADC operating
— 3 μA ADC off
Analog Input
AD12 VINH-VINL Full-Scale Input Span VREFL — VREFH V
VINL Absolute VINL Input AVSS – 0.3 AVDD/2 V
Voltage
VIN Absolute Input Voltage AVSS – 0.3 AVDD + V
0.3
Leakage Current — +/- 0.001 +/-0.610 μA VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10KΩ
AD17 RIN Recommended — — 10K Ω
Impedance of Analog
Voltage Source
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr Resolution 10 data bits bits
AD21c INL Integral Nonlinearity — — <+/-1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL Differential Nonlinearity — — <+/-1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V(2)
AD23c GERR Gain Error — — <+/-1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD24n EOFF Offset Error — — <+/-1 LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c — Monotonicity — — — — Guaranteed
ADC Accuracy – Measurements with Internal VREF+/VREF-
AD20d Nr Resolution 10 data bits bits
AD21d INL Integral Nonlinearity — — <+/-1 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.

PIC32MX3XX/4XX
TABLE 30-34: ADC MODULE SPECIFICATIONS (CONTINUED)
Param.
No.
AD22d DNL Differential Nonlinearity — — <+/-1 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V(2)
AD23d GERR Gain Error — — <+/-4 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
AD24d EOFF Offset Error — — <+/-2 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
AD25d — Monotonicity — — — — Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.

PIC32MX3XX/4XX
TABLE 30-35: A/D CONVERSION TIMING REQUIREMENTS
Param.
No.
Clock Parameters
AD50 TAD A/D Clock Period(2) 75 — — nsec TPB = 75 nsec,
AVDD = 3.0V
AD51 TRC A/D Internal RC Oscillator Period — 250 — nsec See Note 3
Conversion Rate
AD55 TCONV Conversion Time — 12 TAD — — —
AD56 FCNV Throughput Rate — — 500 KSPS AVDD = 3.0V to 3.6V
(Sampling Speed) — — 400 KSPS AVDD = 2.5V to 3.6V
AD57 TSAMP Sample Time 1 — 31 TAD TSAMP must be ≥ 140
nsec
Timing Parameters
AD60 TPCS Conversion Start from Sample — 1.0 TAD — — Auto-Convert Trigger
Trigger(3) (SSRC<2:0> = 111)
not selected
AD61 TPSS Sample Start from Setting 0.5 TAD — 1.5 TAD — —
Sample (SAMP) bit
AD62 TCSS Conversion Completion to — 0.5 TAD — — —
Sample Start (ASAM = 1)(3)
AD63 TDPU Time to Stabilize Analog Stage — — 2 μs —
from A/D OFF to A/D ON(3)
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: Characterized by design but not tested.

PIC32MX3XX/4XX
FIGURE 30-18: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution Set SAMP Clear SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
TSAMP AD55 AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 7 8 5 6 7 8
1 – Software sets ADxCON. SAMP to start sampling.

2 – Sampling starts after discharge period. TSAMP is described in the “PIC32MX Family Reference Manual” (DS61132).
3 – Software clears ADxCON. SAMP to start conversion.

4 – Sampling ends, conversion sequence starts.
5 – Convert bit 9.
8 – One TAD for end of conversion.

PIC32MX3XX/4XX
FIGURE 30-19: A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001
AD50
ADCLK
Instruction
Execution Set ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP TSAMP
AD55 AD55 TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 7 3 4 5 6 8 3 4
1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0.
2 – Sampling starts after discharge period. 6 – One TAD for end of conversion.
TSAMP is described in the “PIC32MX
Family Reference Manual” (DS61132). 7 – Begin conversion of next channel.
3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>.

PIC32MX3XX/4XX
FIGURE 30-20: PARALLEL SLAVE PORT TIMING
CS
PS5
RD
PS6
WR
PS4 PS7
PMD<7:0>
PS1
PS3
PS2
TABLE 30-36: PARALLEL SLAVE PORT REQUIREMENTS

Param.
No.
PS1 TdtV2wrH Data In Valid before WR or CS Inactive 20 — — nsec
(setup time)
PS2 TwrH2dtI WR or CS Inactive to Data– 20 — — nsec
In Invalid (hold time)
PS3 TrdL2dtV RD and CS Active to Data– — — 60 nsec
Out Valid
PS4 TrdH2dtI RD Active or CS Inactive to Data– 0 — 10 nsec
Out Invalid
PS5 Tcs CS Active Time 25 — — nsec
PS6 TWR WR Active Time 25 — — nsec
PS7 TRD RD Active Time 25 — — nsec

PIC32MX3XX/4XX
FIGURE 30-21: PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PM4
PMA<13:18> Address
PM6
PMD<7:0> Address<7:0>
Address<7:0> Data
Data
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 30-37: PARALLEL MASTER PORT READ TIMING REQUIREMENTS

Param.
No.
PM1 TLAT PMALL/PMALH Pulse Width — 1 TPB — —
PM2 TADSU Address Out Valid to PMALL/PMALH — 2 TPB — —
Invalid (address setup time)
PM3 TADHOLD PMALL/PMALH Invalid to Address Out — 1 TPB — —
Invalid (address hold time)
PM4 TAHOLD PMRD Inactive to Address Out Invalid 1 — — nsec
(address hold time)
PM5 TRD PMRD Pulse Width — 1 TPB — —
PM6 TDSU PMRD or PMENB Active to Data In 5 — — nsec
Valid (data setup time)
PM7 TDHOLD PMRD or PMENB Inactive to Data In — 0 — nsec
Invalid (data hold time)

PIC32MX3XX/4XX
FIGURE 30-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PMA<13:18> Address
PM2 + PM3
PMD<7:0> Address<7:0> Data
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 30-38: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS

Param.
No.
PM11 TWR PMWR Pulse Width — 1 TPB — —
PM12 TDVSU Data Out Valid before PMWR or — 2 TPB — —
PMENB goes Inactive (data setup time)
PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out — 1 TPB — —
Invalid (data hold time)

PIC32MX3XX/4XX
TABLE 30-39: OTG TIMING REQUIREMENTS
Param.
Symbol Characteristics Min. Typ Max. Units Conditions
No.
USB313 VUSB USB Voltage 3.0 — 3.6 V Voltage on bus must
be in this range for
proper USB operation
USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V
USB316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V
USB318 VDIFS Differential Input Sensitivity — — 0.2 V
USB319 VCM Differential Common Mode Range 0.8 — 2.5 V The difference
between D+ and D-
must exceed this value
while VCM is met
USB320 ZOUT Driver Output Impedance 28.0 — 44.0 Ω
USB321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kΩ load connected
to 3.6V
USB322 VOH Voltage Output High 2.8 — 3.6 V 1.5 kΩ load connected
to ground

PIC32MX3XX/4XX
FIGURE 30-23: EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold Trf

Trf
TDO
TRST*
TTRST*low
TTDOout TTDOzstate
Defined Undefined
Trf
TABLE 30-40: EJTAG TIMING REQUIREMENTS

Param.
Symbol Description Min. Max. Units Conditions
No.
EJ1 TTCKCYC TCK Cycle Time 25 — nsec
EJ2 TTCKHIGH TCK High Time 10 — nsec
EJ3 TTCKLOW TCK Low Time 10 — nsec
EJ4 TTSETUP TAP Signals Setup Time Before 5 — nsec
Rising TCK
EJ5 TTHOLD TAP Signals Hold Time After 3 — nsec
Rising TCK
EJ6 TTDOOUT TDO Output Delay Time From — 5 nsec
Falling TCK
EJ7 TTDOZSTATE TDO 3-State Delay Time From — 5 nsec
Falling TCK
EJ8 TTRSTLOW TRST Low Time 25 — nsec
EJ9 TRF TAP Signals Rise/Fall Time, All — — nsec
Input and Output

PIC32MX3XX/4XX
31.0 PACKAGING INFORMATION
31.1 Package Marking Information
64-Lead TQFP (10x10x1 mm) Example
PIC32MX360F
XXXXXXXXXX
512L-80I/PT
XXXXXXXXXX
e3
XXXXXXXXXX
YYWWNNN 0510017
100-Lead TQFP (12x12x1 mm) Example
XXXXXXXXXXXX PIC32MX360F
XXXXXXXXXXXX 256L-80I/PT
YYWWNNN e3
0510017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC32MX3XX/4XX
31.2 Package Details
The following sections give the technical details of the packages.

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PIC32MX3XX/4XX

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PIC32MX3XX/4XX

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PIC32MX3XX/4XX

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PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
APPENDIX A: REVISION HISTORY
Revision E (July 2008)

• Updated the PIC32MX340F128H features in
Table 2 to include 4 programmable DMA
channels.

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MX 3XX F 512 H T - 80 I / PT - XXX Examples:
Microchip Brand PIC32MX320F032H-40I/PT:

General purpose PIC32MX, 32 KB program
Architecture
memory, 64-pin, Industrial temp.,
Product Groups TQFP package.
Flash Memory Family PIC32MX360F256L-80I/PT:
Program Memory Size (KB) General purpose PIC32MX, 256 KB program
memory, 100-pin, Industrial temp.,
Pin Count
TQFP package.
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Flash Memory Family
Architecture MX = 32-bit RISC MCU core
Product Groups 3xx = General purpose microcontroller family

4xx = USB
Flash Memory Family F = Flash program memory
Program Memory Size 32 = 32K

64 = 64K
128 = 128K
256 = 256K
512 = 512K
Pin Count H = 64-pin

L = 100-pin
Temperature Range I = -40°C to +85°C (Industrial)
Package PT = 64-Lead, 100-Lead (10x10x1 mm)

TQFP (Thin Quad Flatpack)
PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
Pattern Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)
ES = Engineering Sample

PIC32MX3XX/4XX
NOTES:

PIC32MX3XX/4XX
INDEX
Numerics C
12-Bit A/D C Compilers
ADPCFG ................................................................... 491 MPLAB C18.............................................................. 590
MPLAB C30.............................................................. 590
A Clearing USB OTG Interrupts ........................................... 244
A/D Clock Switching Operation.................................................. 79
Enabling the Module ................................................. 507 Enabling...................................................................... 79
How to Start Sampling .............................................. 505 Entering Sleep Mode .................................................. 81
Sampling Requirements............................................ 519 Sequence ................................................................... 79
A/D Conversion Speeds.................................................... 518 Code Examples
A/D Converter Voltage Reference Schematic................... 517 Aborting a Clock Switch........................................ 76, 81
A/D Module Configuration ................................................. 503 Erasing a Program Memory Block............................ 120
A/D Terminology and Conversion Sequence .................... 502 Initialization Code for 16-bit Asynchronous
AC Characteristics ............................................................ 601 Counter Mode Using an External
Internal RC Accuracy ................................................ 603 Clock Input ....................................................... 334
AC Electrical Specifications Initialization Code for 16-bit Synchronous
Parallel Master Port Read Requirements ................. 627 Counter Mode Using an External
Parallel Master Port Write Requirements.................. 628 Clock Input ....... 193, 349, 351, 456, 460, 461, 463
Parallel Slave Port Requirements ............................. 626 Initialization Code for 16-bit Timer Using
ADC System Clock..... 88, 169, 170, 175, 193, 325, 336,
Converting 1 Channel at 400 ksps............................ 509 350, 353, 393, 396, 437
Assembler Initialization Code for 32-bit Gated Time
MPASM Assembler................................................... 590 Accumulation Mode ......................... 239, 326, 336,
Automatic Clock Stretch.................................................... 411 354, 364, 406, 407, 437, 464, 485
Receive Mode ........................................................... 411 Initiating a Programming Sequence ......................... 122
Transmit Mode .......................................................... 411 PWM Mode Pulse Setup and
Interrupt Servicing .................................... 377, 380
B Setting the RTCWREN Bit ........................ 231, 233, 479
Baud Rate Error Calculation (BRGH = 0) ......................... 434 Voltage Reference Configuration ............................. 553
Block Diagrams Comparator
10-bit High-Speed A/D Converter ............................. 490 Analog Input Connection Considerations ................. 546
Comparator Analog Input Model ............................... 546 Configuration ............................................................ 545
Comparator I/O Operating Modes............................. 537 External Reference Signal........................................ 545
Comparator Voltage Reference ................................ 549 Internal Reference Signal ......................................... 545
Connections for On-Chip Voltage Regulator............. 576 Interrupts .................................................................. 547
Crystal or Cermaic Resonator Operation Operation.................................................................. 545
(XT or HS)........................................................... 71 Outputs ..................................................................... 546
External Clock Input (OSCIOFCN = 0) ....................... 72 Reference ................................................................. 545
External Clock Input (OSCIOFCN = 1) ....................... 72 Comparator Voltage Reference
Input Capture ............................................................ 355 Accuracy and Error................................................... 553
JTAG Compliant Application Showing Configuring ............................................................... 552
Daisy-Chaining of Components ................ 577, 583 Initialization............................................................... 553
Output Compare Module........................................... 365 Control Registers ...................................................... 243, 491
Overview of USB Implementation as a Device ......... 287 Conversion Sequence Examples...................................... 510
Overview of USB Implementation as a Host............. 288 Core Features....................................................................... 9
Overview of USB Implementation for 16-bit Architecture ........................................................ 9
OTG (Dual Role) ............................................... 289 Easy Migration.............................................................. 9
Reset System.............................................................. 83 Oscillator Options, Features ....................................... 10
RTCC ........................................................................ 467 Power-Saving Technology............................................ 9
Shared Port Structure ....................................... 305, 306 CPU Module ....................................................................... 33
Single Comparator .................................................... 545
Type B Timer .............................................. 34, 177, 340 D
Typical I2C Interconnection....................................... 412 DC Characteristics............................................................ 594
UART ........................................................................ 425 I/O Pin Input Specifications ...................................... 598
WDT.......................................................................... 555 I/O Pin Output Specifications.................................... 599
Boundary Scan Register (BSR) ........................................ 584 Idle Current (IIDLE) .................................................... 596
Boundary Scan Testing (BST) .......................................... 586 Operating Current (IDD) ............................................ 595
Brown-out Reset (BOR) Power-Down Current (IPD)........................................ 597
and On-Chip Voltage Regulator................................ 576 Program Memory...................................................... 599
Temperature and Voltage Specifications.................. 594
Development Support ....................................................... 589
Device Reset Times............................................................ 91

PIC32MX3XX/4XX
E J
Electrical Characteristics................................................... 593 JTAG
AC ............................................................................. 601 Device Programming ................................................ 582
Enhanced In-Circuit Serial Programming (EICSP)............ 581 Instructions ............................................................... 584
Equations Registers .................................................................. 583
Calculating the PWM Period ..................................... 379 JTAG Boundary Scan ....................................................... 582
Calculation for Maximum PWM Resolution............... 379
Serial Clock Rate ...................................................... 409 L
UART Baud Rate with BRGH = 0 ............................. 434 Low-Power Secondary Oscillator (SOSC) .......................... 75
UART Baud Rate with BRGH = 1 ............................. 434 Continuous Operation................................................. 75
WDT Time-out Period ............................................... 562 Enabling...................................................................... 75
Errata .................................................................................... 8
M
F MPLAB ASM30 Assembler, Linker, Librarian ................... 590
Fail-Safe Clock Monitor (FSCM) MPLAB ICD 2 In-Circuit Debugger ................................... 591
and WDT ..................................................................... 79 MPLAB ICE 2000 High-Performance Universal
Delay ........................................................................... 79 In-Circuit Emulator .................................................... 591
Slow Oscillator Start-up .............................................. 79 MPLAB Integrated Development
Flash Program Memory..................................................... 115 Environment Software .............................................. 589
Control Registers ...................................................... 119 MPLAB PM3 Device Programmer .................................... 591
Operations ................................................................ 119 MPLAB REAL ICE In-Circuit Emulator System ................ 591
Programming Algorithm ............................................ 120 MPLINK Object Linker/MPLIB Object Librarian ................ 590
RTSP Operation........................................................ 119
N
I Non-Maskable Traps ........................................................ 126
I/O Pin Control............................ 92, 238, 240, 382, 408, 438,
486, 487, 516, 547, 548, 554
O
I/O Pins ............................................................................. 301 Open-Drain Configuration................................................. 323
I/O Ports .................................................................... 305, 425 Oscillator
Parallel I/O (PIO)............................................... 322, 434 OSC1, OSC2 Pin Functions in
I2C Non-Crystal Modes............................................. 81
Addresses ................................................................. 411 Output Compare ............................................................... 374
Baud Rate Generator ................................................ 409 Registers .................................................................. 382
General Call Address Support .................................. 411 Output Compare Registers ....................................... 538, 550
Interrupts ................................................................... 409
P
IPMI Support ............................................................. 411
Master Mode Operation Packaging ......................................................................... 631
Clock Arbitration................................................ 412 Details....................................................................... 632
Multi-Master Communication, Bus Marking ..................................................................... 631
Collision and Bus Arbitration..................... 412 Phase Locked Loop (PLL) ............................................ 73, 77
Operating Modes ...................................................... 409 Lock Status ........................................................... 75, 77
Registers ................................................................... 409 PIC32 Family USB Interface Diagram .............................. 242
Slave Address Masking ............................................ 411 PICSTART Plus Development Programmer..................... 592
Slope Control ............................................................ 412 Pinout Descriptions
Software Controlled Clock Stretching PIC32 Family ........................................................ 16, 24
(STREN = 1) ..................................................... 411 Power-on Reset (POR)
Idle Mode and On-Chip Voltage Regulator................................ 576
Wake-up from on Interrupt ........................................ 534 Power-Saving Modes Control Registers........................... 522
In-Circuit Serial Programming (ICSP) ............................... 581 Primary Oscillator (POSC)............................................ 71, 72
In-Circuit Debugging ................................................. 582 Operating Modes ............................................ 71, 74, 81
Interface .................................................................... 581 Selecting ..................................................................... 71
Operation .................................................................. 581 Pulse Width Modulation Mode .......................................... 380
Initialization ....................................................................... 514 Pulse-Width Modulation Mode.......................................... 378
Input Change Notification.................................................. 324 Duty Cycle ................................................................ 379
Internal Fast RC Oscillator (FRC) ....................................... 76 Period ....................................................................... 379
Postscaler Mode (FRCDIV) ........................................ 76
with PLL Mode (FRCPLL) ........................................... 76
Internal Low-Power RC Oscillator (LPRC) .......................... 76
Enabling ...................................................................... 77
Interrupts Coincident with Power Save Instructions.......... 535

PIC32MX3XX/4XX
R SPIx Slave Mode (CKE = 1) ..................................... 615
RCON Register Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 607
Bit Status During Initialization ..................................... 90 Timing Requirements
CLKO and I/O ........................................................... 604
Using the RCON Status Bits ....................................... 90
Refer ................................................................................. 236 Timing Specifications
Registers I2Cx Bus Data Requirements (Master Mode)........... 618
I2Cx Bus Data Requirements (Slave Mode)............. 619
10-bit A/D Converter Special Function...................... 492
AD1CON1 (A/D Control 1) ........ 494, 498, 499, 500, 501 Output Compare Requirements................................ 610
AD1CON2 (A/D Control 1) ........................................ 496 Simple OC/PWM Mode Requirements ..................... 610
SPIx Master Mode (CKE = 0) Requirements............ 611
ADCHS A/D Input Select .......................................... 499
ADPCFG A/D Port Configuration .............................. 500 SPIx Master Mode (CKE = 1) Requirements............ 612
CMCON (Comparator Control) ......................... 540, 542 SPIx Slave Mode (CKE = 1) Requirements.............. 616
OSCCON (Oscillator Control) ............................. 57, 523 U
RCON (Reset Control) ................................................ 86
UART
Reset
Infrared Support........................................................ 436
Brown-out Reset (BOR) .............................................. 89
IrDA
Configuration Mismatch .............................................. 89
Built-in Encoder and Decoder........................... 436
MCLR Reset ............................................................... 88
External Support, Clock Output ........................ 436
Power-on Reset (POR) ............................................... 88
Operation of UxCTS and UxRTS Control Pins ......... 436
Software RESET Instruction (SWR) ........................... 88
Receiving
Watchdog Time-out Reset (WDTR) ............................ 89
8-bit or 9-bit Data Mode.................................... 436
RTCC
Transmitting
Alarm
Break and Sync Sequence ............................... 436
Configuring ....................................................... 480
USB
Mask Settings ................................................... 480
Interrupts .................................................................. 298
Operation
Operation.................................................................. 278
Calibration......................................................... 483
Write Lock ......................................................... 478 V
S VDDCORE/VCAP Pin ........................................................... 576
Voltage Reference Specifications..................................... 600
Selecting A/D Conversion Clock ....................................... 506
Voltage Regulator (On-Chip) ............................................ 576
Selecting the Voltage Reference Source .......................... 505
Serial Peripheral Interface (SPI) ........................ 83, 197, 383, W
439, 467, 555
Watchdog Timer ............................................................... 561
Setup for Continuous Output Pulse Generation................ 378
Enabling and Disabling............................................. 561
Setup for Single Output Pulse Generation ........................ 376
Operation.................................................................. 561
Sleep Mode
Period Selection ....................................................... 561
and FSCM Delay....................................................... 530
Prescalers................................................................. 562
Clock Selection on Wake-up from............................. 529
Resetting .................................................................. 561
Delay on Wake-up from ............................................ 529
Software Controlled .................................................. 561
Delay Times for Exit.................................................. 529
WWW, On-Line Support ....................................................... 8
Slow Oscillator Start-up .................................................... 530
Software Simulator (MPLAB SIM)..................................... 590
Special Features ............................................................... 565
SPI
Error Handling........................................................... 405
T
Test Access Port (TAP), Controller ................................... 583
Timer1 Module .......................................... 125, 177, 327, 339
Timing Diagrams
10-bit A/D Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 0, SSRC = 000) ............ 624
I2Cx Bus Data (Master Mode) .................................. 617
I2Cx Bus Data (Slave Mode) .................................... 619
I2Cx Bus Start/Stop Bits (Master Mode) ................... 617
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 619
Input Capture (CAPx)................................................ 609
OC/PWM................................................................... 610
Output Compare (OCx)............................................. 609
Parallel Master Port Write ................................. 627, 628
Parallel Slave Port .................................................... 626
SPIx Master Mode (CKE = 0) ................................... 611
SPIx Master Mode (CKE = 1) ................................... 612
SPIx Slave Mode (CKE = 0) ..................................... 613

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01/02/08

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PIC32MX3XX/4XX Family

© 2008 Microchip Technology Inc. Preliminary DS61143E

Information contained in this publication regarding device Trademarks

Microchip received ISO/TS-16949:2002 certification for its worldwide

DS61143E-page ii Preliminary © 2008 Microchip Technology Inc.

• Atomic SET, CLEAR and INVERT Operation on Analog Features:

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 1

TABLE 2: PIC32MX GENERAL PURPOSE – FEATURES

PIC32MX320F032H 64 40 32/8 5/5/5 0 Yes No 2/2/2 16 2 Yes Yes

TABLE 3: PIC32MX USB – FEATURES

Program/Data Timers/ EUART/

PIC32MX420F032H 64 80 32/8 5/5/5 0 2 Yes No 2/1/2 16 2 Yes Yes

DS61143E-page 2 Preliminary © 2008 Microchip Technology Inc.

64-Pin TQFP (General Purpose)

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 3

100-Pin TQFP (General Purpose)

DS61143E-page 4 Preliminary © 2008 Microchip Technology Inc.

64-Pin TQFP (USB)

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 5

100-Pin TQFP (USB)

DS61143E-page 6 Preliminary © 2008 Microchip Technology Inc.

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 7

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS61143E-page 8 Preliminary © 2008 Microchip Technology Inc.

1.0 DEVICE OVERVIEW 1.2 Core Features

1.1 Easy Migration 1.4 Communications

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 9

1.7 Real-Time Clock/Calendar

1.8 Oscillator Options and Features

DS61143E-page 10 Preliminary © 2008 Microchip Technology Inc.

TABLE 1-1: DEVICE FEATURES, BLOCK DIAGRAMS AND PINOUT TABLES

Operating Frequency DC – 40 MHz DC – 80 MHz

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 11

Operating Frequency DC – 80 MHz

DS61143E-page 12 Preliminary © 2008 Microchip Technology Inc.

Operating Frequency DC – 40 DC – 80 MHz

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 13

Peripheral Bus Clocked by SYSCLK

Peripheral Bus Clocked by PBCLK

Peripheral Bus Clocked by PBCLK

Timer1 Timer2 Timer3 Timer4 Timer5 RTCC 10-bit ADC

DS61143E-page 14 Preliminary © 2008 Microchip Technology Inc.

Peripheral Bus Clocked by SYSCLK

Peripheral Bus Clocked by PBCLK

Peripheral Bus Clocked by PBCLK

Timer1 Timer2 Timer3 Timer4 Timer5 RTCC 10-bit ADC

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 15

AN0 16 25 I ANA A/D Analog Inputs

DS61143E-page 16 Preliminary © 2008 Microchip Technology Inc.

CN0 48 74 I ST Interrupt-on-Change Inputs

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 17

OC1 46 72 O — Output Compare/PWM Outputs

DS61143E-page 18 Preliminary © 2008 Microchip Technology Inc.

PMD2 62 98 I/O ST/TTL

© 2008 Microchip Technology Inc. Preliminary DS61143E-page 19

RA0 — 17 I/O ST PORTA Digital I/O

DS61143E-page 20 Preliminary © 2008 Microchip Technology Inc.