Chapter 1 -- Split Manufacturing Methods in Ranga Vemuri • Suyuan Chen

-- Split Manufacturing of Integrated Circuits for Hardware Security and

Trust Methods, Attacks and Defenses -- https://doi.org/10.1007/978-3-030-73445-9
Modern integrated circuit (IC) design and fabrication processes are both complex and expensive. In order to reduce
the cost and improve efficiency, supply chains based on fabless design houses and pure-play foundries have
evolved. Globalization of IC supply chains introduced several vulnerabilities which can be exploited by
unscrupulous attackers. Split manufacturing (SM), originally introduced for yield enhancement, offers a defence to
protect against some of these vulnerabilities.

A typical integrated circuit (IC) design process is illustrated in Fig. 1.1. While many variations of this process exist,
this prototypical process is sufficient for our purposes. IC design process usually begins with a register-transfer level
(RTL) model in a hardware description language such as Verilog. Often, a variety of pre-designed Intellectual
Property (IP) cores in the form of synthesizable RTL modules are integrated into the design at this stage. These IP
cores are termed soft cores. Following satisfactory simulation results, a logic synthesis tool is used to produce a
gate-level design subject to power, performance, and area (PPA) constraints. A library of gate-level components is
used during the synthesis process. These components are pre-characterized for performance and power under
various output load and input slew conditions. These characterization data are used during the technology mapping
step of logic synthesis to bind the abstract logic gates to implementation technology, we will discuss these topics in
terms of a prototypical CMOS process. Digital CMOS circuits consist of two types of transistors, the n-type and the
p-type, and wires to connect them together. Accordingly, in ICs targeted for implementation in a CMOS process,
layouts consist of two types of layers: device and interconnect. Device layers are comprised mainly of well,
diffusion, and poly-silicon layers. Wires in these layers together define the sizes and locations of the n-type and p-
type transistors in the design. Interconnect layers carry the metal wires for connecting the devices. Layout of
rectangles in these layers denotes the shape and location of the wire fragments and contacts among these wire
fragments. Contacts among the interconnect layers are called vias. While older processes allowed only two or three
metal layers for interconnect, state-of-the-art CMOS processes allow over a dozen metal layers. For more details
about the IC design process, the readers may refer to standard textbooks on CMOS IC design [ 1–3] and electronic
design automation (EDA) [4–7].
1.2 Integrated Circuit Fabrication
Once the mask layout is ready, the artwork is sent in the form of a GDSII file to a fabrication (fab) facility, also
called a foundry, where the IC is manufactured. Alternatively, a standard cell netlist can be sent to the manufacturer
and the layout can be produced at the fab. We discuss the steps in a typical CMOS fabrication process illustrated in
Fig. 1.2. IC fabrication begins with the preparation of slices, called wafers, of monocrystalline semiconductor
material. The fabrication process involves repetitive application of three types of operations to build a circuit on the
wafer: doping, deposition, and etching. Doping is the process of implanting n-type or p-type dopant materials in
selected regions of the wafer where transistors need to be formed. Deposition is the process of depositing layers of
conducting or insulating material across the wafer. Etching is the process of removing material. Chemical etching is
used to remove material selectively according to the layout geometry. Chemical etching or chemical-mechanical
polishing (CMP) can be used to remove material across the entire wafer surface. These operations are guided by the
layout geometry sent to the fabricator from the design house. In order to guide selective application of these steps, a
process called photo-lithography is used. In this process, first, the rectangular geometrical shapes defining various
layers in the layout are transferred onto a set of glass sheets called photo-masks or, simply, masks, or reticles. The
wafer is coated with a light sensitive film called photo-resist or, simply, resist.When a mask is exposed to light,
the image of the geometrical shapes patterned on the mask is projected on the resist. When positive (negative) resist
is used, exposed regions are removed (remain) and unexposed regions remain (are removed) after development. The
remaining resist is used as the mask for the next step. Optical alignment methods are used to precisely align various
masks to the wafer in each step so as to correctly and precisely transfer the layout onto the wafer. The fabrication
process can be divided into two distinct phases. In the first phase, termed front-end-of-line (FEOL), transistors and
other passive devices, if any, are implemented at the required locations using selective oxidation and doping steps.
In the second phase, termed back-end-of-line (BEOL), these devices are connected using several metal layers
interspersed with oxide layers and vias between the layers. A cross-sectional view of a typical interconnect structure
is shown in Fig. 1.3. For each metal layer in the interconnect, two physical layers are needed. An oxide layer is used
to separate neighboring metal layers. Vias are patterned at the required locations in the oxide layer. Required metal
wires are then patterned on top of the oxide layer. Entire routing structure in the layout is implemented in this
manner. Table 1.1 shows pitch values (minimum wire width + minimum spacing between neighboring wires) for
various metal layers in the Intel 10 nm process [8]. Using these steps, hundreds of ICs arranged in several rows are
simultaneously produced on each wafer. After processing, the wafer is cut into individual chips which are then
packaged. Following functional and performance evaluation, much of which can occur before packaging, the chips
are ready for use. Chips may be sold either in the packaged form for system integration on a printed circuit board or
in the unpackaged bare die form for system integration on other forms of multi-chip carriers [10]. While our highly
simplified description is sufficient to follow the topics in this book, interested readers may refer to the excellent texts
on IC fabrication for details [11–14].

1.3 Globalization of the IC Supply Chains

Capacity and complexity of integrated circuits have been steadily increasing since the advent of CMOS in early
1970s. The famed Moore’s Law [15] had correctly predicted a doubling of the number of transistors per die every 2
years or so, attained primarily by reducing the smallest manufacturable feature size by approximately half. Figure
1.4 shows the transistor count and feature size trends [16]. Today, over 50B transistors can be incorporated on a
single die in a typical 7 nm CMOS technology node. 5 nm products are expected shortly and semiconductor
manufacturers have already announced plans for commercial deployment of 3 nm and 2 nm process nodes. While
geometrical scaling of planar devices has been the trend until early 2000s, introduction of new materials and newer
“vertical” structures such as FinFETs and GAAFETs [17, 18] have helped maintain Moore-equivalent scaling since
then. Full 3D integration, discussed later in this chapter, is expected to continue to ensure the life of the CMOS as a
viable medium for integrated circuits for the next 10–15 years.

The growing capacity and complexity of CMOS ICs resulted in two important globalization trends: design reuse and
fabless design companies. Since designs have become extremely complex, in order to keep the design time and
design
cost under control, design methodologies and processes that encourage reuse of known-good modules across all
levels of design abstraction have been developed. The most important of these practices is the use of soft or hard
cores developed by other companies. Driven by a globalized economy, these so-called 3rd party IP cores (3PIP) are
often developed by companies incorporated or physically located in other countries. It is not uncommon for a system
developer to procure 3PIP cores from multiple foreign countries. Mishra et al. [19] show that the geographical
distribution of IP cores integrated in representative IC products could span across multiple continents. Even when
multiple cores developed within the same company are brought together in a system, those cores may have been
developed by multiple development teams located in multiple countries by employees many of whom could be
foreign nationals. IC fabrication facilities for advanced CMOS nodes are exceedingly expensive, costing upwards of
$10B for establishing a new state-of-the-art production plant with additional recurrent operating costs. This resulted
in a situation where it is no longer cost-effective for most IC design companies to own and maintain a foundry
exclusively devoted to their own products. On the other hand, to remain profitable, a fabrication facility needed to
produce sufficient quantities of ICs possibly for multiple design houses so that the fab can be kept busy. These
considerations led to fabless IC design companies that develop state-of-the-art IC products but do not own a fab and
pure-play foundries that do not produce significant IC products of their own but offer their fab services to other,
usually fabless, design houses. Tables 1.2, 1.3, and 1.4 show data pertaining to the top semiconductor sales leaders,
fabless design houses, and pure-play foundries. Three trends are evident from this data: (1) only a few leading IC
design companies own in-house fab facilities, (2) many fabless design houses are among the top IC developers and
several are headquartered in the USA, and (3) all, except one, of the pure-play foundries are located in countries
other than the USA. Taken together these data show the geographical dispersion of the IC supply chains. It is worth
noting many ICs used in military systems as well as consumer products are produced by the same supply chains.
Yield is the ratio of the number of functional dies to the total number of dies of an IC manufactured in a wafer run.
The motivation behind SM was to separately fabricate the FEOL and BEOL parts, test the two parts separately, and
then merge the known-good parts into a finished IC through an alignment and bonding procedure. In this way, parts
with faults in the BEOL metal layers are eliminated and only fault-free BEOL parts are bonded to the parametrically
tested good pieces from the FEOL process leading to a net increase in yield. Various instances of SM were
postulated based on this general idea. For example, the BEOL and FEOL layers could follow different design rules.
They can even be manufactured in different foundries. BEOL metal wires and vias could be made larger so as to
enhance their current carrying capacity and reliability. In addition to the devices, the FEOL part may consist of one
or more metal layers and the rest of the metal layers could be delegated to the BEOL part. It is also possible to
connect one FEOL piece with multiple BEOL pieces or even multiple FEOL pieces with multiple BEOL pieces. It is
recommended that the FEOL part should have at least one metal layer since it is then possible to form intra-cell
interconnections among the transistor devices which allows functional testing of the gates and reliable formation of
connections between the top metal layer in the FEOL part and the bottom metal layer in the BEOL part. Clearly, the
design and fabrication process for SM will have to be different than the one used for the traditional process. The
process for SM is illustrated in Fig. 1.6. At some point before or during the physical design stage, the FEOL and
BEOL designs should be separated. This separation is achieved through the identification and rerouting of some
wires through the BEOL layers. This process is called wire lifting or net lifting. The FEOL part consists of all the
transistors. When at least one metal layer is allowed in the FEOL part, as is usually the case in SM, all the logic
gates are in the FEOL part. It may even consist of some nets or portions of nets depending upon the number of metal
layers allowed in the FEOL part. The remaining nets or portions of nets are to be routed through the metal layers in
BEOL part. Once separated, layouts of both the parts are generated according to the respective design rules. The
FEOL part consists of the device layers and one or more of the lower level metal layers. The BEOL part consists of
the remaining upper level metal layers. Extracted netlists from both parts can be connected together to form a
complete circuit for analysis purposes. Following satisfactory simulations, layouts of the two parts are sent to the
respective fab lines. When traditional planar or 2D technology is used, the FEOL part is first fabricated at the
advanced open foundry and the BEOL fabrication is completed at the secure foundry using a compatible process.
When using 2.5D or 3D integration, both parts are manufactured and independently tested, faulty parts are
discarded, and good FEOL parts are combined with good BEOL parts to form complete ICs. Following functional
testing and packaging the ICs are ready for use.