8-Channel,

PDM to I2S/TDM Converter

Data Sheet ADAU7118
FEATURES FUNCTIONAL BLOCK DIAGRAM
1.10V TO 1.98V 1.70V TO 3.63V
8 channels of PDM audio inputs from digital microphones
16×, 32×, or 64× decimation ratio of PDM to PCM audio data
24-bit resolution to support high sound pressure level (SPL)
microphones DVDD GND IOVDD
126 dB A-weighted SNR
4 kHz to 192 kHz output sampling rate PDM_CLK0
Bit clock rates of 64×, 128×, 192×, 256×, 384×, or 512× the
output sampling rate PDM_CLK1
Dual output PDM clocks BCLK
Automatic PDM clock generation PDM
INPUT
DIGITAL
DECIMATION
I2S/TDM
OUTPUT
PDM_DAT0 FSYNC
Automatic power-down when BCLK removed PORT FILTERING PORT
SDATA
Selectable I2C control or hardware mode operation PDM_DAT1
1.2 mA DVDD operating current for 8 channels at 48 kHz
PDM_DAT2
frequency sampling rate and 1.8 V supply
Slave I2S or TDM output interface PDM_DAT3
Up to TDM-16 supported
Configurable TDM slot routing and sizes SDA I2C
I/O supply voltage from 1.70 V to 3.63 V SCL
CONTROL ADAU7118
DVDD supply voltage from 1.10 V to 1.98 V
<5 μA typical DVDD shutdown current

17230-001
16-lead, 3 mm × 3 mm, 0.50 mm pitch LFCSP ADDR/CONFIG EN
Power-on reset Figure 1.
APPLICATIONS
Microphone arrays
Mobile computing
Portable electronics
Consumer electronics
Professional electronics

GENERAL DESCRIPTION
The ADAU7118 converts four stereo pulse density modulation Note that throughout this data sheet, multifunction pins, such
(PDM) bitstreams into one pulse code modulation (PCM) output as ADDR/CONFIG, are referred to either by the entire pin
stream. The source for the PDM data can be eight microphones name or by a single function of the pin, for example, ADDR,
or other PDM sources. The PCM audio data is output on a serial when only that function is relevant.
audio interface port in either inter-IC serial (I2S) or time domain
multiplexed (TDM) format.
The ADAU7118 is specified over the commercial temperature
range (−40°C to +85°C). The ADAU7118 is available in a
16-lead, 3 mm × 3 mm, 0.40 mm pitch, lead frame chip scale
package (LFCSP).

Rev. A Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADAU7118 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 ADI Vendor ID Register ............................................................ 21
Applications ....................................................................................... 1 Device ID 1 Register .................................................................. 21
Functional Block Diagram .............................................................. 1 Device ID 2 Register .................................................................. 21
General Description ......................................................................... 1 Revision Code Register.............................................................. 21
Revision History ............................................................................... 2 Channel Pair and Clock Enables Register ............................... 22
Specifications..................................................................................... 3 Decimation Ratio and PDM Clock Mapping Controls
Absolute Maximum Ratings ............................................................ 7 Register ........................................................................................ 23

Thermal Resistance ...................................................................... 7 High-Pass Filter Controls Register........................................... 24

ESD Caution .................................................................................. 7 Serial Port Controls 1 Register ................................................. 25

Pin Configuration and Function Descriptions ............................. 8 Serial Port Controls 2 Register ................................................. 25

Typical Performance Characteristics ............................................. 9 Serial Port Routing and Drive Enable Channel 0 Register ... 26

Theory of Operation ...................................................................... 11 Serial Port Routing and Drive Enable Channel 1 Register ... 27

Power-Up and Initialization ...................................................... 11 Serial Port Routing and Drive Enable Channel 2 Register ... 28

Clocking ....................................................................................... 11 Serial Port Routing and Drive Enable Channel 3 Register ... 29

Power-Down State ...................................................................... 12 Serial Port Routing and Drive Enable Channel 4 Register ... 30

Standalone Hardware Mode...................................................... 12 Serial Port Routing and Drive Enable Channel 5 Register ... 31

Serial Audio Output Interface................................................... 13 Serial Port Routing and Drive Enable Channel 6 Register ... 32

I2C Control Interface .................................................................. 17 Serial Port Routing and Drive Enable Channel 7 Register ... 33

Output Pin Drive Strength ........................................................ 18 Output Pad Drive Strength Controls Register........................ 34

High-Pass Filter .......................................................................... 18 Software Reset Register ............................................................. 34

Applications Information .............................................................. 19 Outline Dimensions ....................................................................... 35

Register Summary .......................................................................... 20 Ordering Guide .......................................................................... 35

Register Details ............................................................................... 21

REVISION HISTORY
8/2019—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Changes to Ordering Guide .......................................................... 34

5/2019—Revision 0: Initial Version

Rev. A | Page 2 of 35
Data Sheet ADAU7118

SPECIFICATIONS
DVDD = 1.10 V to 1.98 V, IOVDD = 1.70 V to 3.63 V, TA = 25°C, and pins set to low drive setting, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUT
Input Voltage
High Level (VIH) 0.7 × V
IOVDD
Low Level (VIL) 0.3 × V
IOVDD
Input Leakage
High Level (IIH) 2.5 µA Digital input pins with pull-down resistor
Low Level (IIL) at 0 V 1 µA Digital input pins with pull-down resistor
Input Capacitance (CI) 2 pF Guaranteed by design
DIGITAL OUTPUT
Output Voltage
High Level (VOH) 0.85 × V Source current when output is high (IOH) = 1 mA
IOVDD
Low Level (VOL) 0.1 × V Source current when output is low (IOL) = 1 mA
IOVDD
Digital Output Pins, Digital output pins drive low impedance PCB traces to a high
Output Drive impedance digital input buffer
IOVDD = 1.8 V
Nominal
Drive Strength
Setting
2.5 mA 0.7 mA
5 mA 1.4 mA
10 mA 2.8 mA
15 mA 4.2 mA
IOVDD = 3.3 V
Nominal
Drive Strength
Setting
2.5 mA 2.5 mA
5 mA 5 mA
10 mA 10 mA
15 mA 15 mA
PERFORMANCE
Dynamic Range 126 dB 20 Hz to 20 kHz, −60 dB input, A-weighted filter (rms), relative to
0 dBFS output
Signal-to-Noise-Ratio 126 dB A-weighted filter, fifth-order input, relative to 0 dBFS output
(SNR)
Decimation Ratio 16× 64× 64×
Frequency Response −0.1 +0.01 dB DC to 0.45 × output sampling rate (fS)
Stop Band 0.566 × fS Hz
Stop Band Attenuation 75 dB
Group Delay 4.47 4.47 4.47 FSYNC 0.02 fS input signal, 64× decimation
cycles
5.02 5.02 5.02 FSYNC 0.02 fS input signal, 32× decimation
cycles
5.83 5.83 5.83 FSYNC 0.02 fS input signal, 16× decimation
cycles

Rev. A | Page 3 of 35
ADAU7118 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
Gain 0 0 0 dB PDM to PCM
Start-Up Time 63 64 64 FSYNC After power-up reset and initialization code runs
cycles
Bit Resolution 24 Bits Internal and output
Interchannel Phase 0 0 0 Degrees
High-Pass Filter −3 dB 0.23328 0.9312 242.4 Hz fS = 48 kHz, cutoff frequency set using the HPF_FC bits located
Point in the HPF_CONTROL register, typical value is default setting
CLOCKING
Output Sampling 4 48 192 kHz FSYNC pulse rate
Rate (fS)
Bit Clock Frequency 0.256 12.288 24.576 MHz
(fBCLK)
PDM_CLKx Frequency 0.256 3.072 6.144 MHz
(fPDM_CLK)
POWER
Supply Voltage
Digital Voltage 1.10 1.98 V Supply for digital circuitry
(DVDD Pin)
I/O Supply Voltage 1.70 3.63 V Supply for input/output (I/O) circuitry, including pads and level
(IOVDD Pin) shifters
Supply Current
I/O Current Dependent on the clock rates and characteristics of external loads
(IOVDD Pin)
Operation State 2 mA IOVDD = 3.3 V, 48 kHz fS, TDM-8 format, all channels driven,
default drive strength, 25 pF capacitance, only one PDM_CLKx
pin used
0.86 mA IOVDD = 1.8 V, 48 kHz fS, TDM-8 format, all channels driven,
default drive strength, 25 pF capacitance, only one PDM_CLKx
pin used
Shutdown 16 µA Power applied, frame and bit clocks applied, and then device
Current placed into power-down state using the procedure in Table 10
3 µA Power applied, frame and bit clocks applied, and then device
placed into power-down state using the procedure in Table 9
Digital Current
(DVDD Pin)
Operation State 1.4 mA Over all temperatures, full voltage range and silicon skews, 8
channels, 48 kHz fS
1.2 mA DVDD = 1.8 V, 8 channels, 48 kHz fS
0.8 mA DVDD = 1.2 V, 8 channels, 48 kHz fS
0.7 mA DVDD = 1.8 V, 4 channels, 48 kHz fS
0.4 mA DVDD = 1.2 V, 4 channels, 48 kHz fS
0.4 mA DVDD = 1.8 V, 8 channels, 16 kHz fS
0.27 mA DVDD = 1.2 V, 8 channels, 16 kHz fS
0.22 mA DVDD = 1.8 V, 4 channels, 16 kHz fS
0.14 mA DVDD = 1.2 V, 4 channels, 16 kHz fS

Shutdown 4 µA Power-down mode using either method in Table 9 or method in

Current Table 10

Rev. A | Page 4 of 35
Data Sheet ADAU7118
Serial Ports
TA = −40°C to +85°C, DVDD = 1.10 V to 1.98 V, and IOVDD = 1.70 V to 3.63 V, unless otherwise noted.

Table 2.
Parameter Min Max Unit Description
SERIAL PORT
fFSYNC 192 kHz FSYNC frequency, 1/tFSYNC
tFSYNC 5.21 µs FSYNC period
fBCLK 24.576 MHz BCLK frequency, sample rate ranging from 4 kHz to 192 kHz, 1/tBCLK
tBCLK 40.7 ns BCLK period
tBIL 18 ns BCLK low pulse width, slave mode, BCLK frequency = 24.576 MHz, BCLK period = 40.6 ns
tBIH 18 ns BCLK high pulse width, slave mode, BCLK frequency = 24.576 MHz, BCLK period = 40.6 ns
tLIS 10 ns FSYNC setup to BCLK input rising edge, slave mode, FSYNC frequency = 192 kHz
tLIH 10 ns FSYNC hold from BCLK input rising edge, slave mode, FSYNC frequency = 192 kHz
tSOD 20.63 ns SDATA delay from BCLK output falling edge, 25 pf load over entire range of IOVDD, all
temperatures and skews, default drive strength of 10 mA
11.71 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b00, with 25 pf load
10.37 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b01, with 25 pf load
9.03 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b10, with 25 pf load
8.72 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b11, with 25 pf load
31.02 ns IOVDD = 1.7 V to 1.89 V, drive strength set to 0b00, with 25 pf load
25.83 ns IOVDD = 1.7 V to 1.89 V, drive strength set to 0b01, with 25 pf load
20.63 ns IOVDD = 1.7 V to 1.89 V, drive strength set to 0b10, with 25 pf load
20.33 ns IOVDD = 1.7 V to 1.89 V, drive strength set to 0b11, with 25 pf load

tBIH tBCLK tLIH

BCLK

tBIL
tLIS
FSYNC

tFSYNC

SDATA
LEFT JUSTIFIED MODE MSB MSB – 1
(SPT_CTRL1[3:1],
(SPT_DATA_FORMAT) = 0b01)

SDATA
I2S MODE MSB
(SPT_CTRL1[3:1],
(SPT_DATA_FORMAT) = 0b00) tSOD

SDATA
ALL MODES 17230-002

Figure 2. Serial Port Timing Specifications

Rev. A | Page 5 of 35
ADAU7118 Data Sheet
I2C Interface—Slave
TA = −40°C to +85°C, DVDD = 1.10 V to 1.98 V, and IOVDD = 1.70 V to 3.63 V, unless otherwise noted.

Table 3.
Parameter Min Max Unit Description
I2C SLAVE PORT
fSCL 1000 kHz SCL clock frequency, not shown in Figure 3
tSCLH 0.26 µs SCL pulse width high
tSCLL 0.5 µs SCL pulse width low
tSCS 0.26 µs Start and repeated start condition setup time
tSCH 0.26 µs Start condition hold time
tDS 50 ns Data setup time
tDH 0.45 µs Data hold time
tSCLR 120 ns SCL rise time
tSCLF 120 ns SCL fall time
tSDR 120 ns SDA rise time
tSDF 120 ns SDA fall time
tBFT 0.5 µs Bus-free time between stop and start
tSUSTO 0.26 µs Stop condition setup time

tSCH
STOP START
tSDR tDS tSCH

SDA

tSCLH tSDF tBFT

tSCLR

SCL
tSCS tSUSTO

17230-004
tSCLL tSCLF
tDH

Figure 3. I2C Slave Port Timing Specifications

PDM Inputs
TA = −40°C to +85°C, DVDD = 1.10 V to 1.98 V, IOVDD = 1.70 V to 3.63 V, and PDM data is latched on both edges of the clock (see Figure 4),
unless otherwise noted.

Table 4.
Parameter tMIN tMAX Unit Description
Timing Requirements
tSETUP 9 ns Data setup time
tHOLD 3 ns Data hold time

PDM_CLKx

tSETUP tHOLD
17230-005

PDM_DATx R L R L

Figure 4. PDM Timing Diagram

Rev. A | Page 6 of 35
Data Sheet ADAU7118

ABSOLUTE MAXIMUM RATINGS

Table 5. THERMAL RESISTANCE
Parameter Rating Thermal performance is directly linked to printed circuit board
DVDD to Ground 1.98 V (PCB) design and operating environment. Careful attention to
IOVDD to Ground 3.63 V PCB thermal design is required.
Digital Inputs GND − 0.3 V to
IOVDD + 0.3 V Table 6. Thermal Resistance
Maximum Operating Ambient Temperature −40°C to +85°C Package Type θJA1 θJC2 Unit
Range CP-16-22 57 15 °C/W
Junction Temperature Range −65°C to +165°C 1
Thermal impedance simulated values are based on a JEDEC 1S0P thermal
Storage Temperature Range −65°C to +150°C test board. See JEDEC JESD-51.
Soldering (60 sec) 300°C 2
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD-51.
Electrostatic Discharge (ESD) Susceptibility 4.5 kV
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 7 of 35
ADAU7118 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16 IOVDD

14 DVDD
15 GND

13 EN
PDM_CLK0 1 12 ADDR/CONFIG
PDM_DAT0 2 ADAU7118 11 SDATA
TOP VIEW
PDM_DAT1 3 (Not to Scale)
10 BCLK
PDM_CLK1 4 9 FSYNC

SDA 8
SCL 7
PDM_DAT2 5
PDM_DAT3 6
NOTES
EXPOSED PAD. THE EXPOSED PAD MUST BE GROUNDED BY SOLDERING IT

17230-006
TO A GROUNDED COPPER PAD OF EQUIVALENT SIZE ON THE PCB.
THERMAL VIAS ARE NOT NECESSARY.

Figure 5. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description
1 PDM_CLK0 PDM Output Clock 0.
2 PDM_DAT0 PDM Input Data 0.
3 PDM_DAT1 PDM Input Data 1.
4 PDM_CLK1 PDM Output Clock 1.
5 PDM_DAT2 PDM Input Data 2.
6 PDM_DAT3 PDM Input Data 3.
7 SCL I2C Serial Clock Input.
8 SDA I2C Data.
9 FSYNC I2S/TDM Frame Sync or Left/Right Clock.
10 BCLK I2S/TDM Bit Clock.
11 SDATA I2S/TDM Serial Data Output.
12 ADDR/CONFIG I2C Address or Standalone Configuration Selection.
13 EN Chip Enable.
Ground this pin to disable the device and put it in low power mode.
Apply IOVDD to this pin to enable normal operation. All register settings are preserved when the device is
disabled. However, the bit clock counters, and the audio data resets, which is the same as performing a soft reset.
14 DVDD Internal Core Digital Power Supply.
15 GND Ground.
16 IOVDD Digital Input/Output Power Supply.
EP EPAD Exposed Pad. The exposed pad must be grounded by soldering it to a grounded copper pad of equivalent size
on the PCB. Thermal vias are not necessary.

Rev. A | Page 8 of 35
Data Sheet ADAU7118

TYPICAL PERFORMANCE CHARACTERISTICS

0 –100
–10 –102
–20 –104
–30 –106
–40 –108
–50 –110

THD + N LEVEL (dBFS)

–60 –112
–70 –114
LEVEL (dBFS)

–80 –116
–90 –118 CH1
–100 –120 CH2
–110 –122
–120 –124
–130 –126
CH1
–140 –128
CH2
–150 –130
–132
–160
–134
–170
–136
–180
–138
–190
–140

17230-007

17230-010
20 100 1k 10k 20k 20 100 1k 10k 20k
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 6. FFT, fS = 48 kHz, −60 dBFS Input, 64× Decimation, Fifth Order Figure 9. Total Harmonic Distortion + Noise (THD + N) vs. Frequency at
−10 dBFS Unweighted, fS = 48 kHz, 64× Decimation, Fifth Order

1.0
0.9 0
0.8
–20
0.7
0.6
–40
0.5
RELATIVE LEVEL (dB)

0.4
–60
MAGNITUDE (dB)
0.3
0.2 –80
0.1
0 –100
–0.1
–0.2 –120
–0.3
–0.4 –140
–0.5
–0.6 –160
–0.7
–0.8 –180
–0.9

17230-011
0 0.5 1.0 1.5
17230-008

20 100 1k 10k 20k

FREQUENCY (MHz)
FREQUENCY (Hz)

Figure 7. Relative Level vs. Frequency at −10 dBFS Normalized, 64× Figure 10. Magnitude vs. Frequency, 48 kHz Output, 64× Decimation
Decimation, fS = 48 kHz

160 0
150 –10
140 –20
130
–30
120
–40
THD + N LEVEL (dBFS)

110
GROUP DELAY (µs)

100 –50
90 –60
CH1
80 –70 CH2
70 –80
60 –90
50
–100
40
–110
30
20 –120
10 –130
0 –140
17230-012
17230-009

20 100 1k 10k 20k –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
MEASURED LEVEL (dBFS)
FREQUENCY (Hz)

Figure 8. Group Delay vs. Frequency, fS = 48 kHz, 64× Decimation Figure 11. THD + N Level vs. Measured Level, 1 kHz, Unweighted, 64×
Decimation, Fifth Order, fS = 48 kHz

Rev. A | Page 9 of 35
ADAU7118 Data Sheet
1.0
0 0.9
0.8
–20 0.7
0.6
0.5

RELATIVE LEVEL (dB)

–40
0.4
MAGNITUDE (dB)

0.3
–60
0.2
0.1
–80 0
–0.1
–100 –0.2
–0.3
–120 –0.4
–0.5
–0.6
–140
–0.7
–0.8
–160 –0.9
–1.0

17230-013

17230-016
0 0.5 1.0 1.5 20 100 1k 10k 20k
FREQUENCY (MHz) FREQUENCY (Hz)

Figure 12. Magnitude vs. Frequency, 48 kHz Output, 32× Decimation Figure 15. Relative Level vs. Frequency at −10 dBFS Normalized, 16×
Decimation, fS = 48 kHz

1.0 150
0.9 140
0.8
0.7 130
0.6 120
0.5
RELATIVE LEVEL (dB)

110
0.4 GROUP DELAY (µs)
0.3 100
0.2 90
0.1 80
0
–0.1 70
–0.2 60
–0.3 50
–0.4
–0.5 40
–0.6 30
–0.7 20
–0.8
–0.9 10
–1.0 0

17230-017
20 100 1k 10k 20k 20 100 1k 10k
17230-014

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 13. Relative Level vs. Frequency at −10 dBFS Normalized, 32× Figure 16. Group Delay vs. Frequency, fS = 48 kHz, 32× Decimation
Decimation, fS = 48 kHz

150
0 140
130
120
110
GROUP DELAY (µs)
MAGNITUDE (dB)

–50 100
90
80
70
60
–100 50
40
30
20
10
–150 0
17230-015

17230-018

0 0.5 1.0 1.5 20 100 1k 6k

FREQUENCY (MHz)
FREQUENCY (Hz)

Figure 14. Magnitude vs. Frequency, 48 kHz Output, 16× Decimation Figure 17. Group Delay vs. Frequency, fS = 48 kHz, 16× Decimation

Rev. A | Page 10 of 35
Data Sheet ADAU7118

THEORY OF OPERATION
The ADAU7118 provides up to 8 channels of decimation from a When the PDM clocks start, and after another 48 frame sync
1-bit PDM source to a 24-bit PCM audio. The downsampling cycles, the PDM data shows up on the SDATA pin. These 64
ratio is typically 64 × fS, with fS being the PCM output sampling frame sync cycles are listed in Table 1.
rate, but the downsampling ratio can also be set at 32 × fS or 16 × The ADAU7118 can operate in two modes of operation:
fS to facilitate higher output sampling rates. All channels decimate standalone hardware and I2C. See the Standalone Hardware
at the same ratio. The 24-bit downsampled PCM audio is output Mode section or the I2C Control Interface section for more details.
via standard I2S or TDM format.
CLOCKING
The input sources for the ADAU7118 can be any device that has
a slave PDM output, such as a digital microphone. The output pins After power is applied and the power-up initialization is complete,
of these microphones can connect directly to the input pins of the the device is ready to accept I2S clocks. At that point, it takes 16
ADAU7118. There are two separate PDM_CLKx outputs that are full frame sync cycles for the device to fully initialize and start
replications of the same signal to allow easier drive of multiple sending PDM clocks. If during normal operation the bit clock or
sources. Each PDM_CLKx can be disabled individually. frame sync is removed, the ADAU7118 PDM_CLKx outputs
stop immediately, and the ADAU7118 goes into a lower power
The PDM_DATx input pins are connected to the data output of state automatically. See the Power-Down State section for more
the PDM sources. Internally, there are 8 channels, Channel 0 details. When the clocks resume, the ADAU7118 relocks to the
through Channel 7. The mapping of PDM_DATx inputs to the bit clock and the frame sync signals and adjusts the PDM_CLKx
internal channels is detailed in Table 8. outputs accordingly. The length of time before the PDM clock
Table 8. PDM_DATx to Internal Channel Mapping outputs resume is 4 frames ± 1 frame to lock to the incoming
Input Pin PDM_CLK Edge Internal Channel signal. If the format of the clock signals change, the ADAU7118
detects this change at the end of the frame and stops the PDM
PDM_DAT0 Falling 0
clock outputs. Then, the device reconfigures and resumes sending
PDM_DAT0 Rising 1
PDM clocks with no user intervention. Again, the length of time
PDM_DAT1 Falling 2
before the PDM clock outputs resume usually takes 4 frames ±1
PDM_DAT1 Rising 3
frame to lock to the incoming signal.
PDM_DAT2 Falling 4
PDM_DAT2 Rising 5 The ADAU7118 requires a BCLK rate that is a minimum of 64×
PDM_DAT3 Falling 6 the frame sync (FSYNC) sample rate. BCLK rates of 128×, 192×,
PDM_DAT3 Rising 7 256×, 384×, and 512× the FSYNC rate are also supported. The
ADAU7118 automatically detects the ratio between BCLK and
Each internal channel pair associated with each PDM_DATx pin
FSYNC and generates a PDM clock output at 64 × the FSYNC
can be disabled to save power if those channels are not used.
rate by default. If lower decimation ratios are selected in
Each PDM data pin must be assigned to either the PDM_CLK0 or Register 0x05, DEC_RATIO_CLK_MAP, the PDM output clock
PDM_CLK1 clock sources, using the decimation ratio and PDM rate corresponds with the DEC_RATIO bits setting. The minimum
clock mapping controls register (DEC_RATIO_CLK_MAP), to sampling rate is 4 kHz, and the maximum sampling rate is 192
ensure compliance with timing specifications. The PDM_CLKx kHz. The PDM clock range is 256 kHz to 6.144 MHz. Internally,
assignment must be the actual PDM clock that is driving the PDM all processing is done at the PDM_CLK rate.
microphone. By default, PDM_DAT0 and PDM_DAT1 are mapped
The two PDM clock outputs, PDM_CLK0 and PDM_CLK1,
to PDM_CLK0, and PDM_DAT2 and PDM_DAT3 are mapped to
are separate buffered outputs of the same clock. However, the
PDM_CLK1. This mapping of the two clock sources to the four data
incoming PDM data is clocked in using the signal present at the
input pins can be modified by the PDM_DATx_CLK_MAP bits.
actual clock pin and not the internal clock going out to the pin.
POWER-UP AND INITIALIZATION The reason for this is to allow the clock rise time to be slowed
The ADAU7118 requires two power supplies to function: the by the external capacitance in a similar manner to the PDM data
IOVDD and the DVDD. Both power supplies can be applied at signal. It is recommended to associate the incoming PDM data
the same time. If the power supplies are applied at different times, with the clock output that is actually connected to the PDM
the IOVDD must be applied first and then the DVDD at any microphone. The DEC_RATIO_CLK_MAP register,
point after. There are no timing restrictions. Register 0x05, is used to assign one of the two clocks to each
PDM data input.
After the power supplies have stabilized, the device initializes
and is ready to accept incoming I2S clocks or I2C commands
based on the mode of operation.
After the initialization is complete, and I2S clocks are applied, it
takes 16 full frame sync cycles to begin sending out PDM clocks.

Rev. A | Page 11 of 35
ADAU7118 Data Sheet
POWER-DOWN STATE Table 10. Placing the ADAU7118 into the Power-Down State
The ADAU7118 can be placed into a power-down state by using when Operating in Standalone Mode
one of two methods available. The preferred method is by using Step Action
register writes to place the device into the lowest possible power- 1 Apply a low voltage to the EN pin
down state. However, for when the ADAU7118 operates in 2 Wait at least one frame period
standalone mode, use the second method, which uses the 3 Stop the frame and bit clocks
enable pin (EN). To come out of the power-down mode, the order for restarting
With a system controller and when entering the low power the clocks vs. enabling the device does not matter. Enabling the
state, disable the PDM clocks and disable the channel outputs device refers to either raising the EN pin or enabling the device
by writing a zero to Register 0x04 (ENABLES register). Then, the by writing to Register 0x04.
frame and bit clocks can be removed (stopped) to place the device STANDALONE HARDWARE MODE
in the power-down state. Allow enough time for the I2C write to
Because all channels default to enable and output, the device
complete before stopping the clocks. A minimum of one full
can be used with the default control settings without I2C and
frame after the I2C write completes is enough wait time. It is not
with any setting of the ADDR/CONFIG pin, except for
necessary to lower the EN pin, it does not lower the power draw
hardware mode. If the ADDR/CONFIG pin is left open, the device
any further. See Table 9 for more details.
is in standalone hardware mode and I2C communications are not
Table 9. Placing the ADAU7118 into the Power-Down State possible. See Table 14 for details on the ADDR/CONFIG pin
Using Register Writes settings. In standalone hardware mode, the settings of the I2C
Step Action SCL pin and SDA pin can select different functionality by
1 Write a zero into Register 0x04 changing the state of some registers from their default. See
2 Wait at least one frame period Table 11 for details of the differences from the default settings.
3 Stop the frame and bit clocks To achieve the lowest power in standalone hardware mode
When the ADAU7118 is in standalone mode, the device can be operation when a BCLK is present, the EN pin is still functional
placed into the power-down state by applying a low signal to the and can be pulled low, placing the device into a low power
EN pin and then waiting a minimum of one full frame to place mode. The EN pin also performs a soft reset but does not reset
the device into the power-down state. See Table 10 for more any of the register settings. Stopping the bit clock and frame
details. Note that if a pull-up resistor is used on the EN pin, the sync clocks also places the device into a low power state. See the
additional current through this pull-up resistor must be added Clocking section for more details.
to the values in Table 1.

Table 11. Standalone Hardware Mode Settings: Changes From Default Settings
SCL Pin SDA Pin Operation PDM Clock Settings: Channel Enables:
Tied to Tied to Settings ENABLES, Register 0x04 ENABLES, Register 0x04 Drive Strength
IOVDD IOVDD 4-channel PDM_CLK1_EN bit = 0, CHAN_45_EN bit = 0, Default setting = 10
disabled CHAN_67_EN bit = 0
IOVDD GND 8-channel high Default settings All channels enabled SDATA_DS = 11, PDM_CLK0_DS =
drive 11, PDM_CLK1_EN = 11
GND IOVDD 6-channel Default settings CHAN_67_EN = 0 Default setting = 10
GND GND 6-channel high Default settings CHAN_67_EN = 0 SDATA_DS = 11, PDM_CLK0_DS =
drive 11, PDM_CLK1_EN = 11

Rev. A | Page 12 of 35
Data Sheet ADAU7118
SERIAL AUDIO OUTPUT INTERFACE Bits[5:4] (SPT_SLOT_WIDTH), to result in 18 combinations of
The ADAU7118 supports I2S and TDM serial output formats. Up TDM formats that are supported. Note that some of these formats
to 16 TDM slots can be used. TDM slot widths of 16 bits, 24 bits, do not have an even number of full width slots (see Table 12).
and 32 bits are supported. Any internal channel can be routed to Note that as soon as the next frame sync edge is detected, the
any output slot via the SPT_Cx_SLOT bits. By default, each ADAU7118 restarts from Slot 0, and any data in the previous
channel is routed to its same number slot. For example, Channel 1 frame that was never reached is lost. This process is how to achieve
goes to Slot 1 and Channel 6 goes to Slot 6. Each channel can be set unusual TDM formats like TDM-5 or TDM-10. In addition, only
to drive during their set slot or not drive (tristate high impedance TDM-16 or less is supported for placing data into a TDM slot.
mode) via their respective SPT_Cx_DRV bit. I2S mode or TDM Data cannot be placed into slots above 16. The ADAU7118 can be
mode selection is via the SPT_SAI_MODE bit (Bit 0) in the SPT_ configured to tristate all unused TDM slots, which includes all the
CTRL1 register. The SDATA pin is in tristate high impedance slots above the first 16 slots for modes that have more than 16 slots.
mode, except when the port is driving serial data by default. It is In TDM mode, the frame sync is expected to be a positive going
possible for two or more channels to be set to the same TDM slot. pulse that is at least one bit clock period wide. The falling edge is
In that case, the lowest channel number wins and drives its data not important and is not looked at as long as it is low long enough
into the slot. The data of the other channel never appears anywhere. to meet the timing specification read as a low before going back
There is no cross-checking of register settings to prevent the high. The frame starts with the rising edge of this pulse. The data
user from doing this, but the device is not damaged, only the is clocked out according to the slot width and data format specified
data is missing from the output. in the SPT_CTRL1 register, Register 0x07. The ADAU7118
The SPT_CTRL1 register, SPT_SAI_MODE bit (Bit 0) sets the continues to send data until all active channels are sent and then
serial port audio interface mode. The two modes are stereo and the device waits for the next frame sync clock edge to start sending
TDM. The primary difference between these two modes is the the next set of frame samples. If TDM-16 is used and the
format of the frame sync clock that is expected and the polarity ADAU7118 is set to output Channel 0 to Channel 7 into Slot 0 to
of the active edge of the clock. Slot 7, the ADAU7118 can tristate for the remainder of the frame,
With the SPT_SAI_MODE bit set to 0, and the SPT_LRCLK_POL allowing another ADAU7118 to output its 8 channels on to Slot 8
bit (Bit 1, Register SPT_CTRL2) set to 0, the serial port is in stereo to Slot 15. These slots do not have to be consecutive. The two
mode with the clock polarity set to normal. In this mode, only two devices may interleave their respective data if properly set up to
channels of data are expected to be sent. The frame starts with the do this. The serial port can be set up to only drive when there is
falling edge of the frame sync, and the expected duty cycle is 50% data to drive into a data slot. If one or more of the eight channels is
high and 50% low. Channel 0 sends out its data when the clock is not used, the channel can be assigned to drive a slot or tristate
low, and as soon as the frame sync goes high, the data from during that data slot in the TDM data stream, which is done
Channel 0 is stopped, and Channel 1 begins sending. Both edges using Bit 0 in the SPT_Cx registers.
of the frame sync clock are used. If the duty cycle is not 50/50, The SPT_LRCLK_POL bit, left/right clock polarity, can be set to 1
there may be errors in the resulting data. In this mode of operation, and the bit inverts the expected frame clock. In stereo mode with
the ADAU7118 does not expect 32-bit clock transitions for each the SPT_LRCLK_POL bit set to 1, Channel 0 is sent out when the
channel. All bit clock to frame sync ratios are supported. frame sync is high so the start of the frame is a low to high transition.
With the SPT_SAI_MODE bit set to 1, and the SPT_LRCLK_ In TDM mode, with the SPT_LRCLK_POL bit set to 1, the
POL bit set to 0, the serial port is in TDM mode with the clock expected frame sync pulse is negative going so that the frame
polarity set to normal. In this mode, there can be as few as a single starts with the high to low transition.
channel transmitted or as many as 8 channels spread out across The SPT_DATA_FORMAT bits (Bits[3:1]) in the SPT_CTRL1
16 data slots of a TDM-16 format. register allow for the justification of the data within the 32-bit
The ADAU7118 can support six different bit clock rates of 64×, data slot. The left justified mode, delayed by one bit clock
128×, 192×, 256×, 384×, or 512× the output sampling rate. These period, and the right justified modes for 24-bit, 20-bit, and
bit clock rates are combined with the three different TDM slot sizes 16-bit data word sizes are all supported.
of 16-bit, 24-bit, or 32-bit slots, selected in the SPT_CTRL1 register,

Rev. A | Page 13 of 35
ADAU7118 Data Sheet
Table 12. Number of Slots in Supported TDM Bit Clock Rates vs. Slot Size Setting
SPT_CTRL1, Bits[5:4]
Bit Clock Rate 0b01, 16-Bit Slot 0b10, 24-Bit Slot 0b00, 32-Bit Slot
64 × fS 4 21 2
128 × fS 8 51 4
192 × fS 12 8 6
256 × fS 16 101 8
384 × fS 24 16 12
512 × fS 32 211 16
1
This combination produces a partial final TDM slot that is not included in the number of slots. The data in that final slot is invalid. The number of slots shown in the
table are the full width slots.

FSYNC

BCLK

SDATA I2S CH 0 TRISTATE I2S CH 1 TRISTATE

17230-019
24 8
BCLKs BCLKs

Figure 18. SPT_SIA_MODE = Stereo Mode (I2S), I2C Operation Only

FSYNC

BCLK

SDATA CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7

24
BCLKs

17230-020
SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7

Figure 19. TDM-8, Default Channel Assignments, Left Justified Delayed by Zero, 24-Bit Data, 32-Bit Slots, Normal Polarity Clocks

FSYNC

BCLK

SDATA CH 0 CH 1 CH 2 CH 3 TRISTATE TRISTATE TRISTATE TRISTATE

24
BCLKs
17230-021

SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7

Figure 20. TDM-8, Left Justified Zero BCLK Delay, Only Channel 0 to Channel 3 Enabled

Rev. A | Page 14 of 35
Data Sheet ADAU7118

FSYNC

BCLK

SDATA CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7

24
BCLKs

17230-022
SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7

Figure 21. TDM-8 Hardware Mode, SCL = 1, SDA = 0, I 2C Mode, One BCLK Delay, Normal Clock Polarity, Default Channel Assignments

FSYNC

BCLK

SDATA CH 0 CH 1 CH 2 CH 3 CH 4 CH 5

24
BCLKs

17230-023
SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5

Figure 22. TDM-6, Hardware Mode, SCL = 0, SDA = x, I2C Mode, One BCLK Delay, Normal Clock Polarity, Default Channel Assignments

FSYNC

BCLK

SDATA CH 0 CH 1 CH 2 CH 3

24
BCLKs
17230-024

SLOT 0 SLOT 1 SLOT 2 SLOT 3

Figure 23. TDM-4, Hardware Mode, SCL = 1, SDA = 1, I 2C Mode, One BCLK Delay, Normal Clock Polarity, Default Channel Assignments

FSYNC

BCLK

SDATA CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE

24
BCLKs
17230-025

SLOT 0 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SLOT 9 SLOT 10 SLOT 11 SLOT 12 SLOT 13 SLOT 14 SLOT 15

Figure 24. TDM-16, Default Channel Assignments, Left Justified Zero BCLK Delay, Normal Clock Polarity

Rev. A | Page 15 of 35
ADAU7118 Data Sheet

FSYNC

BCLK

SDATA CH 0 CH 1

24
BCLKs

17230-026
SLOT 0 SLOT 1

Figure 25. TDM-2, I 2C Mode, One BCLK Delay, Normal Clock Polarity, Default Channel Assignments

Rev. A | Page 16 of 35
Data Sheet ADAU7118
I2C CONTROL INTERFACE
The ADAU7118 supports a 2-wire serial bus (I2C-compatible) resides in the first 7 bits of the I2C write. The LSB of this byte
shared across multiple peripherals. Two signals, serial data (SDA) sets either a read or write operation. Logic Level 1 corresponds
and serial clock (SCL), carry information between the ADAU7118 to a read operation, and Logic Level 0 corresponds to a write
and the system I2C master controller. The ADAU7118 is always operation.
a slave on the bus and cannot initiate a data transfer. Each slave Both SDA and SCL are open-drain and require pull-up resistors
device is identified by a unique address. The address byte format to the IOVDD voltage. The ADAU7118 operates with I2C
is shown in Table 13 with the LSBs of the address determined by voltages over the full range of IOVDD
the state of the ADDR/CONFIG pin (see Table 14). The address

Table 13. I2C Device Address Byte Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 1 0 1 Bit 2 Bit 1 R/W

Table 14. Standalone Hardware Mode: ADDR/CONFIG Pin Options

I2C Address Bit 2 I2C Address Bit 1 ADDR Pin Configuration
1 1 Tie to IOVDD
0 0 Tie to GND
Hardware Mode 1 Hardware Mode 1 Open
1 0 Tie to IOVDD through a 47 kΩ resistor
0 1 Tie to GND through a 47 kΩ resistor

Rev. A | Page 17 of 35
ADAU7118 Data Sheet
OUTPUT PIN DRIVE STRENGTH HIGH-PASS FILTER
All output pins have configurable output drive strength that can There is a first order high-pass filter in the signal path that can
be set via their respective control registers. Drive strengths of be bypassed, if desired. The high-pass filter is disabled by default
2.5 mA, 5 mA, 10 mA, and 15 mA at 3.3 V IOVDD are possible. and can be enabled by setting HPF_EN (Bit 0, Register HPF_
The serial data output pin functions in slave mode at all valid CONTROL) = 1. The cutoff frequency can be adjusted using the
sample rates, provided that the external circuit design provides HPF_FC bits (Bits[7:4]) in the HPF_CONTROL register. The
sufficient electrical signal integrity. When operating at IOVDD = settings are relative to the output sampling rate. Table 15 shows
1.8 V nominal, take care to achieve sufficient timing margins at the setting and the cutoff frequency for common sampling rates.
BCLK frequencies over 12.288 MHz. The capacitance of the bit
clock and SDATA signal lines on the PCB, along with the length
of the trace, enter into the calculation of this timing margin.

Table 15. HPF Cutoff Frequency Selections

Cutoff Frequency in Hz
HPF_FC (Bits[7:4]) Setting Multiplication Factor For 48 kHz Sampling Rate For 32 kHz Sampling Rate
101 0.00505 242.4 161.6
110 0.00251 120.48 80.32
111 0.00125 60 40
1000 0.000623 29.904 19.936
1001 0.000311 14.928 9.952
1010 0.000155 7.44 4.96
1011 0.0000777 3.7296 2.4864
1100 0.0000389 1.8672 1.2448
1101 0.0000194 0.9312 0.6208
1110 0.00000971 0.46608 0.31072
1111 0.00000486 0.23328 0.15552

Rev. A | Page 18 of 35
 IOVDD
Data Sheet

IOVDD
C24
C6 0.10uF
0.10uF

IOVDD

IOVDD
1
1 LRSEL_IN VDD
5 DATA_OUT
LRSEL_IN VDD 4 PDM_DAT_3
5 DATA_OUT PDM_DAT_0 IOVDD PDM_CLK_1 2
CLK_IN GND M7
4 2
PDM_CLK_0 GND M1
CLK_IN 3 MEMS_MIC
C22
3 MEMS_MIC
0.10uF
IOVDD

IOVDD
IOVDD C25
1
LRSEL_IN 0.10uF
VDD IOVDD DVDD
DATA_OUT
APPLICATIONS INFORMATION

C7 5

IOVDD
4 PDM_DAT_2
PDM_CLK_1 2
0.10uF CLK_IN GND M5
1

IOVDD
3 MEMS_MIC LRSEL_IN
VDD
5 DATA_OUT
1 4 PDM_DAT_3
PDM_CLK_1 2
VDD IOVDD CLK_IN GND M8 C20
LRSEL_IN DATA_OUT
5 PDM_DAT_0 3 MEMS_MIC
4 C9 0.10uF
PDM_CLK_0 2
CLK_IN GND M2 C23 0.10uF
3 MEMS_MIC 0.10uF R14 0Ω

IOVDD
PDM_CLK_0 R15 0Ω U3
IOVDD
16
14

1 PDM_DAT_0 ADAU7118
LRSEL_IN
VDD
DATA_OUT R16 0Ω
5 PDM_DAT_2
C10 4 2 PDM_DAT_1 1
PDM_CLK_1 PDM_CLK0
DVDD

CLK_IN GND M6
IOVDD

0.10uF R17 0Ω 2
PDM_DAT0
3 MEMS_MIC PDM_CLK_1 3 R20 0Ω

IOVDD
PDM_DAT1 9
FSYNC FSYNC
R18 0Ω

Rev. A | Page 19 of 35
1 4
PDM_DAT_2 PDM_CLK1 10 R21 0Ω
5 BCLK
LRSEL_IN VDD R19 0Ω PDM_DAT2 BCLK
5 DATA_OUT PDM_DAT_1 6 11
4 2 IOVDD PDM_DAT_3 PDM_DAT3 SDATA
PDM_CLK_0 GND M3 R22 0Ω
CLK_IN

Figure 26. Example Application Circuit

R27 0Ω SDATA
3 MEMS_MIC SCL 7
8 SCL
SDA
ADDR/CONFIG
EN
GND
EP

R26 0Ω
IOVDD SCL
12
13
15
17

I2C PULL-UPS ARE ASSUMED TO EXIST ELSEWHERE R28 0Ω IOVDD

C11
0.10uF R27, R28, R29, R31 ARE
USED FOR SELECTING DATA FORMAT

IOVDD
OPTIONS IN HARDWARE MODE IOVDD
0Ω
0Ω
0Ω
0Ω

R29 0Ω R13
1 SDA 10k0
LRSEL_IN VDD
R4
R23
R24
R25

5 DATA_OUT PDM_DAT_1 IOVDD

R30 0Ω C21
4 2
PDM_CLK_0 GND M4 SDA 0.10uF
CLK_IN
R6
47k5

3 MEMS_MIC R31 0Ω

47k5 R5 ENABLE
ENABLE
INSTALL R4 FOR I2C ADDRESS “11”
INSTALL R24 FOR I2C ADDRESS “00”
DO NOT STUFF R4, R23, R24, R25 FOR HARDWARE MODE
INSTALL R23 FOR I2C ADDRESS “10”
INSTALL R25 FOR I2C ADDRESS “01”
17230-027
ADAU7118
ADAU7118 Data Sheet

REGISTER SUMMARY
Table 16. ADAU7118 Register Summary
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x00 VENDOR_ID [7:0] VENDOR 0x41 R
0x01 DEVICE_ID1 [7:0] DEVICE1 0x71 R
0x02 DEVICE_ID2 [7:0] DEVICE2 0x18 R
0x03 REVISION_ID [7:0] REV 0x00 R
0x04 ENABLES [7:0] RESERVED PDM_ PDM_ CHAN_ CHAN_ CHAN_23_EN CHAN_01_EN 0x3F R/W
CLK1_EN CLK0_ 67_EN 45_EN
EN
0x05 DEC_RATIO_ [7:0] PDM_ PDM_DAT2_ PDM_ PDM_ RESERVED DEC_RATIO 0xC0 R/W
CLK_MAP DAT3_ CLK_MAP DAT1_ DAT0_
CLK_MAP CLK_MAP CLK_
MAP
0x06 HPF_ [7:0] HPF_FC RESERVED HPF_EN 0xD0 R/W
CONTROL
0x07 SPT_CTRL1 [7:0] RESERVED SPT_TRI_STATE SPT_SLOT_WIDTH SPT_DATA_FORMAT SPT_SAI_MODE 0x41 R/W
0x08 SPT_CTRL2 [7:0] RESERVED SPT_LRCLK_POL SPT_BCLK_POL 0x00 R/W
0x09 SPT_C0 [7:0] SPT_C0_SLOT RESERVED SPT_C0_DRV 0x01 R/W
0x0A SPT_C1 [7:0] SPT_C1_SLOT RESERVED SPT_C1_DRV 0x11 R/W
0x0B SPT_C2 [7:0] SPT_C2_SLOT RESERVED SPT_C2_DRV 0x21 R/W
0x0C SPT_C3 [7:0] SPT_C3_SLOT RESERVED SPT_C3_DRV 0x31 R/W
0x0D SPT_C4 [7:0] SPT_C4_SLOT RESERVED SPT_C4_DRV 0x41 R/W
0x0E SPT_C5 [7:0] SPT_C5_SLOT RESERVED SPT_C5_DRV 0x51 R/W
0x0F SPT_C6 [7:0] SPT_C6_SLOT RESERVED SPT_C6_DRV 0x61 R/W
0x10 SPT_C7 [7:0] SPT_C7_SLOT RESERVED SPT_C7_DRV 0x71 R/W
0x11 DRIVE_ [7:0] RESERVED SDATA_DS PDM_CLK1_DS PDM_CLK0_DS 0x2A R/W
STRENGTH
0x12 RESETS [7:0] RESERVED SOFT_FULL_RESET SOFT_RESET 0x00 W

Rev. A | Page 20 of 35
Data Sheet ADAU7118

REGISTER DETAILS
ADI VENDOR ID REGISTER
Address: 0x00, Reset: 0x41, Name: VENDOR_ID

Table 17. Bit Descriptions for VENDOR_ID

Bits Bit Name Settings Description Reset Access
[7:0] VENDOR Not applicable ADI Vendor ID 0x41 R

DEVICE ID 1 REGISTER
Address: 0x01, Reset: 0x71, Name: DEVICE_ID1

Table 18. Bit Descriptions for DEVICE_ID1

Bits Bit Name Settings Description Reset Access
[7:0] DEVICE1 Not applicable Device ID 1 0x71 R

DEVICE ID 2 REGISTER
Address: 0x02, Reset: 0x18, Name: DEVICE_ID2

Table 19. Bit Descriptions for DEVICE_ID2

Bits Bit Name Settings Description Reset Access
[7:0] DEVICE2 Not applicable Device ID 2 0x18 R

REVISION CODE REGISTER

Address: 0x03, Reset: 0x00, Name: REVISION_ID

Table 20. Bit Descriptions for REVISION_ID

Bits Bit Name Settings Description Reset Access
[7:0] REV Not applicable Revision ID 0x0 R

Rev. A | Page 21 of 35
ADAU7118 Data Sheet
CHANNEL PAIR AND CLOCK ENABLES REGISTER
Address: 0x04, Reset: 0x3F, Name: ENABLES

Table 21. Bit Descriptions for ENABLES

Bits Bit Name Settings Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
5 PDM_CLK1_EN PDM Clock 1 Enable. 0x1 R/W
0 Disabled.
1 Enabled.
4 PDM_CLK0_EN PDM Clock 0 Enable. 0x1 R/W
0 Disabled.
1 Enabled.
3 CHAN_67_EN Channel 6/Channel 7 (PDM_DAT3) Enable. 0x1 R/W
0 Disabled.
1 Enabled.
2 CHAN_45_EN Channel 4/Channel 5 (PDM_DAT2) Enable. 0x1 R/W
0 Disabled.
1 Enabled.
1 CHAN_23_EN Channel 2/Channel 3 (PDM_DAT1) Enable. 0x1 R/W
0 Disabled.
1 Enabled.
0 CHAN_01_EN Channel 0/Channel 1 (PDM_DAT0) Enable. 0x1 R/W
0 Disabled.
1 Enabled.

Rev. A | Page 22 of 35
Data Sheet ADAU7118
DECIMATION RATIO AND PDM CLOCK MAPPING CONTROLS REGISTER
Address: 0x05, Reset: 0xC0, Name: DEC_RATIO_CLK_MAP

Table 22. Bit Descriptions for DEC_RATIO_CLK_MAP

Bits Bit Name Settings Description Reset Access
7 PDM_DAT3_CLK_MAP PDM Clock Mapping to PDM Data Pin 3. 0x1 R/W
0 PDM_CLK0 is used for PDM_DAT3.
1 PDM_CLK1 is used for PDM_DAT3.
6 PDM_DAT2_CLK_MAP PDM Clock Mapping to PDM Data Pin 2. 0x1 R/W
0 PDM_CLK0 is used for PDM_DAT2.
1 PDM_CLK1 is used for PDM_DAT2.
5 PDM_DAT1_CLK_MAP PDM Clock Mapping to PDM Data Pin 1. 0x0 R/W
0 PDM_CLK0 is used for PDM_DAT1.
1 PDM_CLK1 is used for PDM_DAT1.
4 PDM_DAT0_CLK_MAP PDM Clock Mapping to PDM Data Pin 0. 0x0 R/W
0 PDM_CLK0 is used for PDM_DAT0.
1 PDM_CLK1 is used for PDM_DAT0.
[3:2] RESERVED Reserved. 0x0 R
[1:0] DEC_RATIO Decimation Ratio. 0x0 R/W
0 64×.
1 32×.
10 16×.

Rev. A | Page 23 of 35
ADAU7118 Data Sheet
HIGH-PASS FILTER CONTROLS REGISTER
Address: 0x06, Reset: 0xD0, Name: HPF_CONTROL

Table 23. Bit Descriptions for HPF_CONTROL

Bits Bit Name Settings Description Reset Access
[7:4] HPF_FC High-Pass Filter Cutoff Frequency Relative to Output Sample Rate. 0xD R/W
0 Reserved.
1 Reserved.
10 Reserved.
11 Reserved.
100 Reserved.
101 0.00505.
110 0.00251.
111 0.00125.
1000 0.000623.
1001 0.000311.
1010 0.000155.
1011 0.0000777.
1100 0.0000389.
1101 0.0000194.
1110 0.00000971.
1111 0.00000486.
[3:1] RESERVED Reserved. 0x0 R
0 HPF_EN High-Pass Filter Enable. 0x0 R/W
0 HPF off.
1 HPF on.

Rev. A | Page 24 of 35
Data Sheet ADAU7118
SERIAL PORT CONTROLS 1 REGISTER
Address: 0x07, Reset: 0x41, Name: SPT_CTRL1

Table 24. Bit Descriptions for SPT_CTRL1

Bits Bit Name Settings Description Reset Access
7 RESERVED Reserved. 0x0 R
6 SPT_TRI_STATE Serial Port Output: Tristate (High Impedance Mode) Enable for Unassigned Slots. 0x1 R/W
1 Enabled.
0 Disabled.
[5:4] SPT_SLOT_WIDTH Selects serial port slot width, the number of bit clock periods in each data slot. 0x0 R/W
00 32 BCLKs per slot.
01 16 BCLKs per slot.
10 24 BCLKs per slot.
[3:1] SPT_DATA_FORMAT Selects serial port data delay from left/right/frame clock transition. 0x0 R/W
001 Left justified, delay by 0.
000 I2S mode, delay by 1.
010 Delay by 8.
011 Delay by 12.
100 Delay by 16.
0 SPT_SAI_MODE Selects Serial Port SAI Mode (Serial Audio Interface). 0x1 R/W
0 Stereo.
1 TDM.

SERIAL PORT CONTROLS 2 REGISTER

Address: 0x08, Reset: 0x00, Name: SPT_CTRL2

Table 25. Bit Descriptions for SPT_CTRL2

Bits Bit Name Settings Description Reset Access
[7:2] RESERVED Reserved. 0x0 R
1 SPT_LRCLK_POL Selects serial port left/right frame clock polarity. 0x0 R/W
0 Normal.
1 Inverted.
0 SPT_BCLK_POL Selects serial port bit clock polarity. 0x0 R/W
0 Capture on rising edge.
1 Capture on falling edge.

Rev. A | Page 25 of 35
ADAU7118 Data Sheet
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 0 REGISTER
Address: 0x09, Reset: 0x01, Name: SPT_C0

Table 26. Bit Descriptions for SPT_C0

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C0_SLOT Serial Port Channel 0 Slot Selection. 0x0 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C0_DRV Serial Port Channel 0 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 26 of 35
Data Sheet ADAU7118
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 1 REGISTER
Address: 0x0A, Reset: 0x11, Name: SPT_C1

Table 27. Bit Descriptions for SPT_C1

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C1_SLOT Serial Port Channel 1 Slot Selection. 0x1 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C1_DRV Serial Port Channel 1 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 27 of 35
ADAU7118 Data Sheet
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 2 REGISTER
Address: 0x0B, Reset: 0x21, Name: SPT_C2

Table 28. Bit Descriptions for SPT_C2

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C2_SLOT Serial Port Channel 2 Slot Selection. 0x2 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C2_DRV Serial Port Channel 2 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 28 of 35
Data Sheet ADAU7118
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 3 REGISTER
Address: 0x0C, Reset: 0x31, Name: SPT_C3

Table 29. Bit Descriptions for SPT_C3

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C3_SLOT Serial Port Channel 3 Slot Selection. 0x3 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C3_DRV Serial Port Channel 3 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 29 of 35
ADAU7118 Data Sheet
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 4 REGISTER
Address: 0x0D, Reset: 0x41, Name: SPT_C4

Table 30. Bit Descriptions for SPT_C4

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C4_SLOT Serial Port Channel 4 Slot Selection. 0x4 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C4_DRV Serial Port Channel 4 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 30 of 35
Data Sheet ADAU7118
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 5 REGISTER
Address: 0x0E, Reset: 0x51, Name: SPT_C5

Table 31. Bit Descriptions for SPT_C5

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C5_SLOT Serial Port Channel 5 Slot Selection. 0x5 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C5_DRV Serial Port Channel 5 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 31 of 35
ADAU7118 Data Sheet
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 6 REGISTER
Address: 0x0F, Reset: 0x61, Name: SPT_C6

Table 32. Bit Descriptions for SPT_C6

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C6_SLOT Serial Port Channel 6 Slot Selection. 0x6 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C6_DRV Serial Port Channel 6 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 32 of 35
Data Sheet ADAU7118
SERIAL PORT ROUTING AND DRIVE ENABLE CHANNEL 7 REGISTER
Address: 0x10, Reset: 0x71, Name: SPT_C7

Table 33. Bit Descriptions for SPT_C7

Bits Bit Name Settings Description Reset Access
[7:4] SPT_C7_SLOT Serial Port Channel 7 Slot Selection. 0x7 R/W
0 Slot 0.
1 Slot 1.
10 Slot 2.
11 Slot 3.
100 Slot 4.
101 Slot 5.
110 Slot 6.
111 Slot 7.
1000 Slot 8.
1001 Slot 9.
1010 Slot 10.
1011 Slot 11.
1100 Slot 12.
1101 Slot 13.
1110 Slot 14.
1111 Slot 15.
[3:1] RESERVED Reserved. 0x0 R
0 SPT_C7_DRV Serial Port Channel 7 Drive Select. This bit determines whether the associated 0x1 R/W
channel is driven in its assigned slot or if it is in a high impedance state floating
during the assigned slot.
0 Not driven.
1 Driving selected slot.

Rev. A | Page 33 of 35
ADAU7118 Data Sheet
OUTPUT PAD DRIVE STRENGTH CONTROLS REGISTER
Address: 0x11, Reset: 0x2A, Name: DRIVE_STRENGTH

Table 34. Bit Descriptions for DRIVE_STRENGTH

Bits Bit Name Settings Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:4] SDATA_DS SDATA Output Pad Drive Strength Control. 0x2 R/W
0 2.5 mA, 3.3 V.
1 5 mA, 3.3 V.
10 10 mA, 3.3 V.
11 15 mA, 3.3 V.
[3:2] PDM_CLK1_DS PDM_CLK1 Output Pad Drive Strength Control. 0x2 R/W
0 2.5 mA, 3.3 V.
1 5 mA, 3.3 V.
10 10 mA, 3.3 V.
11 15 mA, 3.3 V.
[1:0] PDM_CLK0_DS PDM_CLK0 Output Pad Drive Strength Control. 0x2 R/W
0 2.5 mA, 3.3 V.
1 5 mA, 3.3 V.
10 10 mA, 3.3 V.
11 15 mA, 3.3 V.

SOFTWARE RESET REGISTER

Address: 0x12, Reset: 0x00, Name: RESETS

Table 35. Bit Descriptions for RESETS

Bits Bit Name Settings Description Reset Access
[7:2] RESERVED Reserved. 0x0 R
1 SOFT_FULL_RESET Software Reset Including Register Settings. 0x0 W
0 Running.
1 In reset.
0 SOFT_RESET Software Reset Not Including Register Settings. 0x0 W
0 Running.
1 In reset.

Rev. A | Page 34 of 35
Data Sheet ADAU7118

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10 0.30
3.00 SQ 0.23
PIN 1
INDICATOR 2.90 0.18
AREA
P IN 1
13 16 IN D IC ATO R AR E A OP T IO N S
0.50 (SEE DETAIL A)
BSC 12 1

1.75
EXPOSED 1.60 SQ
PAD
1.45

9 4

0.50 8 5 0.20 MIN

TOP VIEW BOTTOM VIEW
0.40
0.30
0.80 FOR PROPER CONNECTION OF
0.75 SIDE VIEW THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.20 REF

08-24-2018-E
PKG-005138

COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6

Figure 27. 16-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Height
(CP-16-22)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Marking Code Package Option
ADAU7118ACPZRL −40°C to +85°C 16-Lead LFCSP, 13” Tape and Reel Y70 CP-16-22
ADAU7118ACPZRL7 −40°C to +85°C 16-Lead LFCSP, 7” Tape and Reel Y70 CP-16-22
EVAL-ADAU7118Z Evaluation Board
1
Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D17230-0-8/19(A)

Rev. A | Page 35 of 35