XTR300

SBOS336B − JUNE 2005 − REVISED MARCH 2006

Industrial Analog Current/Voltage

OUTPUT DRIVER
FEATURES APPLICATIONS
D USER-SELECTABLE: Voltage or Current D PLC OUTPUT PROGRAMMABLE DRIVER
Output D INDUSTRIAL CROSS-CONNECTORS
D +40V SUPPLY VOLTAGE D INDUSTRIAL HIGH-VOLTAGE I/O
D VOUT: ±10V (up to ±17.5V at ±20V supply) D 3-WIRE-SENSOR CURRENT OR VOLTAGE
D IOUT: ±20mA (linear up to ±24mA) OUTPUT
D SHORT- OR OPEN-CIRCUIT FAULT D ±10V 2- AND 4-WIRE VOLTAGE OUTPUT
INDICATOR PIN
Patents Pending
D NO CURRENT SHUNT REQUIRED
D OUTPUT DISABLE FOR SINGLE INPUT MODE DESCRIPTION
D THERMAL PROTECTION The XTR300 is a complete output driver for industrial and
D OVER-CURRENT PROTECTION process control applications. The output can be configured
D SEPARATE DRIVER AND RECEIVER as current or voltage by the digital I/V select pin. No
CHANNELS external shunt resistor is required. Only external
gain-setting resistors and a loop compensation capacitor
D DESIGNED FOR TESTABILITY are required.

CC
The separate driver and receiver channels provide
flexibility. The Instrumentation Amplifier (IA) can be used
for remote voltage sense or as a high-voltage, high-
impedance measurement channel. In voltage output
XTR300 V+ V−
mode, a copy of the output current is provided, allowing
IMON Current Copy
calculation of load resistance.
R IMON ICOPY
1kΩ
IDRV The digital output selection capability, together with the
Input Signal V IN error flags and monitor pins, make remote configuration
OPA
DRV and troubleshooting possible. Fault conditions on the
(Optional) SET
output and on the IA input as well as over-temperature
IA IN+
R OS RSET
conditions are indicated by the error flags. The monitoring
IIA RG 1
IA R GAIN Load pins provide continuous feedback about load power or
RG 2
V REF
GND1 impedance. For additional protection, the maximum output
IA OUT
IA IN−
current is limited and thermal protection is provided.
GND2
RIA OD EFCM
1kΩ EFLD
Digital communication like HART can be modulated onto
M1 Digital Error
M2 Control Flags EF OT the input signal. The receive signal applied to the output
GND3 DGND can be detected at the monitor pins in both current and
voltage output modes. In addition to HART
communication, the device offers system or sensor
configuration through the signal connector.
The XTR300 is specified over the −40°C to +85°C
Figure 1. XTR300 Basic Diagram industrial temperature range and for supply voltage up to
40V.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
HART is a registered trademark of the HART Communication Foundation.
All other trademarks are the property of their respective owners.

 

       
 Copyright  2005−2006, Texas Instruments Incorporated
            

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This integrated circuit can be damaged by ESD. Texas

ABSOLUTE MAXIMUM RATINGS(1) Instruments recommends that all integrated circuits be
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V handled with appropriate precautions. Failure to observe
Signal Input Terminals proper handling and installation procedures can cause damage.
Voltage(2) . . . . . . . . . . . . . . . . . . . . . . (V−) − 0.5V to (V+) + 0.5V
ESD damage can range from subtle performance degradation to
Current(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25mA complete device failure. Precision integrated circuits may be more
DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25mA susceptible to damage because very small parametric changes could
Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous cause the device not to meet its published specifications.
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ORDERING INFORMATION(1)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V PACKAGE PACKAGE
PRODUCT PACKAGE-LEAD DESIGNATOR MARKING
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
(1) Stresses above these ratings may cause permanent damage. QFN-20
XTR300 RGW XTR300
(5mm x 5mm)
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and (1) For the most current package and ordering information, see the
functional operation of the device at these or any other conditions Package Option Addendum at the end of this document, or see
beyond those specified is not supported. the TI web site at www.ti.com.
(2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current limited. PIN ASSIGNMENTS
(3) See the Driver Output Disable section in Application Information PIN NAME FUNCTION
section for thermal protection.
1 M2 Mode Input
2 M1 Mode Input
3 VIN Noninverting Signal Input
PIN CONFIGURATION
4 SET Input for Gain Setting; Inverting Input
5 IMON Current Monitor Output
Top View QFN
6 IAOUT Instrumentation Amplifier Signal Output
DGND
EFCM
EFOT

EFLD

7 IAIN− Instrumentation Amplifier Inverting Input

OD

8 IAIN+ Instrumentation Amplifier Noninverting Input

20 19 18 17 16 9 RG1 Instrumentation Amplifier Gain Resistor
10 RG2 Instrumentation Amplifier Gain Resistor
M2 1 Exposed 15 V+ 11 V− Negative Power Supply
Thermal 12 NC No Internal Connection
M1 2 Die Pad 14 NC
on 13 DRV Operational Amplifier Output
VIN 3 13 DRV
Underside. 14 NC No Internal Connection
SET 4 (Must be 12 NC 15 V+ Positive Power Supply
connected
IMON 5 to V−) 11 V− 16 DGND Ground for Digital I/O
17 EFCM Error Flag for Common-Mode Over-Range,
Active Low
6 7 8 9 10
18 EFLD Error Flag for Load Error, Active Low
Pad
IAIN+
IAOUT

IAIN−

RG1

RG2

19 EFOT Error Flag for Over Temperature, Active Low

20 OD Output Disable, Disabled Low
Pad Pad Exposed thermal pad must be connected to V−

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS: VOLTAGE OUTPUT MODE

Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at TA = +25°C, VS = ±20V, RLOAD = 800Ω, RSET = 2kΩ, ROS = 2kΩ, VREF = 4V, RGAIN = 10kΩ, Input Signal Span 0V to 4V, and CC = 100pF, unless
otherwise noted.

XTR300
PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE
Offset Voltage, RTI VOS ±0.4 ±1.9 mV
vs Temperature dVOS/dT ±1.6 ±6 µV/°C
vs Power Supply PSRR VS = ±5V to ±22V ±0.2 ±10 µV/V
INPUT VOLTAGE RANGE
Nominal Setup for ±10V Output See Figure 2
Input Voltage For Linear Operation (V−) + 3V (V+) − 3V V
NOISE
Voltage Noise, f = 0.1Hz to 10Hz, RTI 3 µVPP
Voltage Noise Density, f = 1kHz, RTI en 40 nV/√Hz
OUTPUT
Voltage Output Swing from Rail IDRV ≤ 15mA (V−) +3V (V+) − 3 V
Gain Nonlinearity ±0.01 ±0.1 %FS
vs Temperature ±0.1 ±1 ppm/°C
Gain Error IB ±0.04 ±0.1 %FS
vs Temperature ±0.2 ±1 ppm/°C
Output Impedance, dVDRV/dIDRV 7 mΩ
Output Leakage Current While Output Disabled Pin OD = L(1) 30 nA
Short-Circuit Current ISC ±15 ±20 ±24 mA
Capacitive Load Drive CLOAD CC = 10nF, RC = 15(2) 1 µF
Rejection of Voltage Difference between GND1 and GND2, RTO 130 dB
FREQUENCY RESPONSE
Bandwidth −3dB G=5 300 kHz
Slew Rate(2) SR 1 V/µs
SR CC = 10nF, CL = 1µF, RC = 15Ω 0.015 V/µs
Settling Time(2)(3), 0.1%, Small Signal VDRV = ±1V 8 µs
Overload Recovery Time 50% Overdrive 12 µs
(1) Output leakage includes input bias current of INA.
(2) Refer to Driving Capacitive Loads section in Application Information.
(3) 8µs plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.

CC

X TR3 00 V+ V−

I MON Cu rrent Copy

R IMON I COPY
1kΩ
I DRV
Input Sig nal
V IN = 0V to 4.0V GND 3 V IN
DRV
OPA Transfer Function:
S ET

VIN − VREF
RG
( V IN
)
IA IN+
R OS R SET IIA
V OUT = +
RG 1 2 RSET R OS
IA R GAIN Load
RG 2
V REF = 4.0V
IA IN−
IA OUT

OD EF CM
H
M1 D igital Error E F LD
L
Contro l Flags EF OT
M2
L
DGND

∆ V GND
GND1 GND2

Figure 2. Standard Circuit for Voltage Output Mode

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS: CURRENT OUTPUT MODE

Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at TA = +25°C, VS = ±20V, RLOAD = 800Ω, RSET = 2kΩ, ROS = 2kΩ, VREF = 4V, Input Signal Span 0 to 4V, and CC = 100pF, unless otherwise
noted.

XTR300
PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE
Input Offset Voltage VOS Output Current < 1µA ±0.4 ±1.8 mV
vs Temperature dVOS/dT ±1.5 ±6 µV/°C
vs Power Supply PSRR VS = ±5V to ±22V ±0.2 ±10 µV/V
INPUT VOLTAGE RANGE
Nominal Setup for ±20V Output See Figure 3
Maximum Input Voltage For Linear Operation (V−) + 3 (V+) − 3 V
NOISE
Voltage Noise, f = 0.1Hz to 10Hz, RTI 3 µVPP
Voltage Noise Density, f = 1kHz, RTI in 33 nV/√Hz
OUTPUT
Compliance Voltage Swing from Rail IDRV = ±24mA (V−) +3 (V+) − 3 V
Output Conductance, (dIDRV/dVDRV) dVDRV = ±15V, dIDRV = ±24mA 0.7 µA/V
Transconductance See Transfer Function
Gain Error IDRV = ±24mA ±0.04 ±0.12 %FS
vs Temperature IDRV = ±24mA ±3.6 ±10 ppm/°C
Linearity Error IB IDRV = ±24mA ±0.01 ±0.1 %FS
vs Temperature IDRV = ±24mA ±1.5 ±6 ppm/°C
Output Leakage Current While Output Disabled Pin OD = L 0.6 nA
Short-Circuit Current ISC ±24.5 ±32 ±38.5 mA
Capacitive Load Drive(1)(2) CLOAD 1 µF
FREQUENCY RESPONSE
Bandwidth −3dB 160 kHz
Slew Rate(2) SR 1.3 mA/µs
Settling Time(2)(3), 0.1%, Small Signal IDRV = ±2mA 8 µs
Overload Recovery Time CLOAD = 0, 50% Overdrive 1 µs
(1) Refer to Driving Capacitive Loads section in Application Information.
(2) With capacitive load, the slew rate can be limited by the short circuit current and the load error flag can trigger during slewing.
(3) 8µs plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.

CC

XTR300 V+ V−

IMON Current Copy

I COPY

Input Signal IDRV

VIN = 0V to 4.0V VIN
DRV
OPA
SET Transfer Function:
IAIN+
V IN − V REF
ROS RSET IIA
IA
RG1 IOUT = 10 ( VIN
RSET
+
ROS
)
RG2
VREF = 4.0V
IAIN−
IAO UT
IO UT
OD EFCM
H
M1 Digital Error EFLD
L
M2 Control Flags EFOT
H
DGND
GND1 GND2

Figure 3. Standard Circuit for Current Output Mode

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ELECTRICAL CHARACTERISTICS: OPERATIONAL AMPLIFIER (OPA)

Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at TA = +25°C, VS = ±20V, RLOAD = 800Ω, unless otherwise noted.
XTR300
PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE
Offset Voltage, RTI VOS IDRV = 0A ±0.4 ±1.8 mV
Drift dVOS/dT ±1.5 µV/°C
vs Power Supply PSRR VS = ±5V to ±22V ±0.2 ±5 µV/V
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V−) + 3 (V+) − 3 V
Common-Mode Rejection Ratio CMRR (V−) + 3V < VCM < (V+) − 3V 100 126 dB
INPUT BIAS CURRENT
Input Bias Current IB ±20 ±35 nA
Input Offset Current IOS ±0.3 ±10 nA
INPUT IMPEDANCE
Differential 108 || 5 Ω || pF
Common-Mode 108 || 5 Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL (V−) + 3V < VDRV < (V+) − 3V , IDRV = ±24mA 100 126 dB
OUTPUT
Voltage Output Swing from Rail IDRV = ±24mA (V−) + 3 (V+) − 3 V
Short-Circuit Current ILIMIT M2 = High ±25.5 ±32 ±38.5 mA
ILIMIT M2 = Low ±16 ±20 ±24 mA
Output Leakage Current While Output Disabled ILEAK_DRV Pin OD = L 10 pA
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW G=1 2 MHz
Slew Rate SR 1 V/µs

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ELECTRICAL CHARACTERISTICS: INSTRUMENTATION AMPLIFIER (IA)

Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at TA = +25°C, VS = ±20V, RIA = 2kΩ, and RGAIN = 2kΩ, unless otherwise noted. See Figure 4.
XTR300
PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE
Offset Voltage, RTI VOS IDRV = 0A ±0.7 ±2.7 mV
vs Temperature dVOS/dT ±2.4 ±10 µV/°C
vs Power Supply PSRR VS = ±5V to ±22V ±0.8 ±10 µV/V
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V−) + 3 (V+) − 3 V
Common-Mode Rejection Ratio CMRR RTI 100 130 dB
INPUT BIAS CURRENT
Input Bias Current IB ±20 ±35 nA
Input Offset Current IOS ±1 ±10 nA
INPUT IMPEDANCE
Differential 108 || 5 Ω || pF
Common-Mode 108 || 5 Ω || pF
TRANSCONDUCTANCE (Gain) IAOUT = 2 (IAIN+ − IAIN−)/RGAIN
Transconductance Error IAOUT = ±2.4mA, (V−) + 3V < VIAOUT < (V+) − 3V ±0.04 ±0.1 %FS
vs Temperature ±0.2 ppm/°C
Linearity Error (V−) + 3V < VIAOUT < (V+) − 3V ±0.01 ±0.1 %FS
Input Bias Current to G1, G2 ±20 nA
Input Offset Current to G1, G2(1) ±1 nA
OUTPUT
Output Swing to the Rail IAOUT = ±2.4mA (V−) + 3 (V+) − 3 V
Output Impedance IAOUT = ±2.4mA 600 MΩ
Short-Circuit Current ILIMIT M2 = High ±7.2 mA
ILIMIT M2 = Low ±4.5 mA
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW G = 1, RGAIN = 10kΩ, RIA = 5kΩ 1 MHz
Slew Rate SR G = 1, RGAIN = 10kΩ, RIA = 5kΩ 1 V/µs
IAOUT = ±40µA, RGAIN = 10kΩ, RIA = 5kΩ,
Settling Time(2), 0.1% 6 µs
CL = 100pF
Overload Recovery Time, 50% RGAIN = 10kΩ, RIA = 15kΩ, CL = 100pF 10 µs
(1) See Typical Characteristics curve.
(2) 6µs plus number of chopping periods. See Application Information section, Internal Current Sources and Settling Time.

ELECTRICAL CHARACTERISTICS: CURRENT MONITOR

Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at TA = +25°C, VS = ±20V, unless otherwise noted. See Figure 4.
XTR300
PARAMETER CONDITION MIN TYP MAX UNITS
OUTPUT
Offset Current IOS IDRV = 0A ±30 ±100 nA
vs Temperature dIOS/dT ±0.06 nA/°C
vs Power Supply PSRR VS = ±5V to ±22V ±0.1 ±10 nA/V
Monitor Output Swing to the Rail IMON = ±2.4mA (V−) + 3 (V+) − 3 V
Monitor Output Impedance IMON = ±2.4mA 200 MΩ
MONITOR CURRENT GAIN IMON = IDRV/10
Current Gain Error IDRV = ±24mA ±0.04 ±0.12 %FS
vs Temperature IDRV = ±24mA ±3.6 ppm/°C
Linearity Error IDRV = ±24mA ±0.01 ±0.1 %FS
vs Temperature IDRV = ±24mA ±1.5 ppm/°C

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS
Boldface limits apply over the temperature range, TA = −40°C to +85°C.
All specifications at TA = +25°C, VS = ±20V, unless otherwise noted. See Figure 4.
XTR300
PARAMETER CONDITION MIN TYP MAX UNITS
POWER SUPPLY
Specified Voltage Range VS ±5 ±20 V
Operating Voltage Range ±5 ±22 V
Quiescent Current IQ IDRV = IAOUT = 0A 1.8 2.3 mA
Over Temperature 2.8 mA
TEMPERATURE RANGE
Specified Temperature Range −40 +85 °C
Operating Temperature Range −55 +125(1) °C
Storage Temperature Range −55 +125 °C
Thermal Resistance
Junction-to-Case qJC 6 °C/W
Junction-to-Ambient qJA 38 °C/W
THERMAL FLAG (EFOT) Output
Alarm (EFOT pin LOW) 140 °C
Return to Normal Operation (EFOT pin HIGH) 125 °C
DIGITAL INPUTS (M1, M2, OD)
VIL Low-Level Input Voltage ≤0.8 V
VIH High-Level Input Voltage ≥1.4 V
Input Current ±1 µA
DIGITAL OUTPUTS (EFLD, EFCM, EFOT)
IOH High-Level Leakage Current (Open-Drain) −1.2 µA
VOL Low-Level Output Voltage IOL = 5mA 0.8 V
VOL Low-Level Output Voltage IOL = 2.8mA 0.4 V
DIGITAL GROUND PIN (V−) ≤ DGND ≤ (V+) − 7V
Current Input M1 = M2 = L, OD = H, All Digital Outputs H −25 µA
(1) EFOT not connected with OD.

Feedback
Network

XTR300 V+ V−

IMON Current Copy

ICOPY
IDRV
GND3
VIN
Input Signal DRV
OPA
SET
IAIN+
RSET IIA RG1
IA RGAIN
RG2
GND1
IAIN−
IAOUT
OD EFCM
RIA
M1 Digital Error EFLD
H
M2 Control Flags EFOT
DGND
GND3

Figure 4. Standard Circuit for Current Output Mode

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SBOS336B − JUNE 2005 − REVISED MARCH 2006

TYPICAL CHARACTERISTICS
At TA = +25°C and V+ = ±20V, unless otherwise noted.

QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE

3.0 1.90
1.88
2.5
1.86
1.84
2.0
1.82
IQ (mA)

IQ (mA)
1.5 1.80
1.78
1.0
1.76

0.5 1.74
1.72
0 1.70
−50 −25 0 25 50 75 100 125 10 15 20 25 30 35 40 45
Temperature (_C) Total Supply Voltage (V)

INPUT BIAS CURRENT vs TEMPERATURE

(VIN, SET, IAIN+, IAIN−, RG1, RG2) OPA OUTPUT SWING TO RAIL vs TEMPERATURE
0 2.2
IDRV = +24mA
I DRV = −24mA
−5 2.0
IDRV = +20mA
 VS − VOUT (V)

−10 1.8
IB (nA)

−15 1.6
IDRV = +10mA

−20 1.4
IDRV = −20mA I DRV = −10mA
−25 1.2

−30 1.0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Temperature (_C) Temperature (_C)

IA GAIN AND PHASE

OPA GAIN AND PHASE vs FREQUENCY vs FREQUENCY
180 0 80 0
160 −20 RGAIN = 10kΩ
60 −45
140 −40
RIA = 500kΩ
120 −60
Phase 40 −90
Phase (_ )
−80
Phase (_ )
Gain (dB)
Gain (dB)

100 R IA = 50kΩ
80 −100 20 −135
R IA = 10kΩ
60 −120
0 −180
40 −140 R IA = 5kΩ
Gain
20 −160
−20 −225
Gain RIA = 1kΩ
0 −180
Phase
−20 −200 −40 −270
0.001 0.01 0.1 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and V+ = ±20V, unless otherwise noted.

OPA CMRR AND PSRR vs FREQUENCY IA CMRR AND PSRR vs FREQUENCY

160 140

140 120
120
CMRR, PSRR (dB)

CMRR, PSRR (dB)

100
PSRR+
100
PSRR− 80
80 PSRR−
60
60
PSRR+ CMRR
40
40
CMRR
20 20

0 0
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

SMALL−SIGNAL STEP RESPONSE LARGE−SIGNAL STEP RESPONSE

CURRENT MODE CURRENT MODE
100mV/div

10V/div

IOUT = ±200µA IOUT = ±20mA

G=8 G=8
CL = 100nF || RL = 800Ω CL = 100nF || RL = 800Ω
CC = 4.7nF CC = 4.7nF
RSET = 1kΩ RSET = 1kΩ
RG = 10kΩ RG = 10kΩ
See Figure 3 See Figure 3

200µs/div 200µs/div

SMALL−SIGNAL STEP RESPONSE LARGE−SIGNAL STEP RESPONSE

VOLTAGE MODE VOLTAGE MODE
50mV/div

5V/div

G=5 G=5
CL = 100nF || RL = 800Ω CL = 100nF || RL = 800Ω
CC = 4.7nF CC = 4.7nF
RSET = 1kΩ RSET = 1kΩ
RG = 10kΩ RG = 10kΩ
See Figure 2 See Figure 2

200µs/div 200µs/div

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and V+ = ±20V, unless otherwise noted.

INPUT−REFERRED NOISE SPECTRUM

VOLTAGE OUTPUT MODE INPUT−REFERRED 0.1Hz to 10Hz NOISE
VOLTAGE OUTPUT MODE
1M
G =5
100k
Noise (nV/√Hz)

10k

1µV/div
1k

100

10

1
1 10 100 1k 10k 100k
1s/div
Frequency (Hz)

INPUT−REFERRED NOISE SPECTRUM

CURRENT OUTPUT MODE INPUT−REFERRED 0.1Hz to 10Hz NOISE
CURRENT OUTPUT MODE
1M
G = 10
Input−Referred Noise (nV/√Hz)

100k

10k
1µV/div

1k

100

10

1
1 10 100 1k 10k 100k
1s/div
Frequency (Hz)

IA INPUT−REFERRED NOISE SPECTRUM IA INPUT−REFERRED 0.1Hz to 10Hz NOISE

1M
G = 20
Input−Referred Noise (nV/√Hz)

100k

10k
1µV/div

1k

100

10

1
1 10 100 1k 10k 100k 1s/div
Frequency (Hz)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and V+ = ±20V, unless otherwise noted.

OPA OFFSET VOLTAGE DISTRIBUTION IA OFFSET VOLTAGE DISTRIBUTION

18 30
16
25
Percent of Population (%)

Percent of Population (%)

14
12 20
10
15
8
6 10
4
5
2
0 0
−2.0

−1.6

−1.2

−0.8

−0.4

−3.0

−2.4

−1.8

−1.2

−0.6
0

0.4

0.8

1.2

1.6

2.0

0.6

1.2

1.8

2.4

3.0
Offset Voltage (mV) Offset Voltage (mV)

OPA OFFSET VOLTAGE DRIFT DISTRIBUTION IA OFFSET VOLTAGE DRIFT DISTRIBUTION

60 40

35
50
Percent of Population (%)

Percent of Population (%)

30
40
25

30 20

15
20
10
10
5

0 0
−10

−8

−6

−4

−2

−10

−8

−6

−4

−2
0

10

10
Offset Voltage Drift (µV/_ C) Offset Voltage Drift (µV/_ C)

VOLTAGE MODE GAIN ERROR DISTRIBUTION CURRENT MODE GAIN ERROR DISTRIBUTION
40 30

35
25
Percent of Population (%)

Percent of Population (%)

30
20
25

20 15

15
10
10
5
5

0 0
−1000

−800

−600

−400

−200

200

400

600

800

1000

−1000

−800

−600

−400

−200

200

400

600

800

1000

Gain Error (ppm) Gain Error (ppm)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and V+ = ±20V, unless otherwise noted.

VOLTAGE MODE NONLINEARITY DISTRIBUTION CURRENT MODE NONLINEARITY DISTRIBUTION

60 60

50 50
Percent of Population (%)

Percent of Population (%)

40 40

30 30

20 20

10 10

0 0
−1000

−800

−600

−400

−200

200

400

600

800

1000

−1000

−800

−600

−400

−200

200

400

600

800

1000
Nonlinearity (ppm) Nonlinearity (ppm)

VOLTAGE MODE GAIN CURRENT MODE GAIN

ERROR DRIFT DISTRIBUTION ERROR DRIFT DISTRIBUTION
70 60

60 50
Percent of Population (%)

Percent of Population (%)

50
40
40
30
30
20
20

10 10

0 0
−1.0

−0.8

−0.6

−0.4

−0.2

−10

−8

−6

−4

−2
0

0.2

0.4

0.6

0.8

1.0

10
Gain Error Drift (ppm/_ C) Gain Error Drift (ppm/_C)

VOLTAGE MODE CURRENT MODE

NONLINEARITY DRIFT DISTRIBUTION NONLINEARITY DRIFT DISTRIBUTION
80 100
90
70
80
Percent of Population (%)
Percent of Population (%)

60
70
50 60
40 50
40
30
30
20
20
10 10
0 0
−1.0

−0.8

−0.6

−0.4

−0.2

−10

−8

−6

−4

−2
0

0.2

0.4

0.6

0.8

1.0

10

Nonlinearity Drift (ppm/_ C) Nonlinearity Drift (ppm/_ C)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C and V+ = ±20V, unless otherwise noted.

POSITIVE CURRENT LIMIT vs TEMPERATURE NEGATIVE CURRENT LIMIT vs TEMPERATURE

36 −16
34 −18
Voltage Mode
32 Current Mode −20
30 −22
−24
I LIMIT (mA)

ILIMIT (mA)
28
26 −26
24 −28
22 Voltage Mode −30
20 −32
Current Mode
18 −34
16 −36
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Temperature (_ C) Temperature (_C)

NONLINEARITY vs OUTPUT CURRENT NONLINEARITY vs OUTPUT CURRENT

(±24mA End Point Calibration) (±20mA End Point Calibration)
0.025 0.025 −55_C
+25_C
+25_ C −55_ C
0 0
Nonlinearity (%)

Nonlinearity (%)

−0.025 −0.025
+85_ C +125_C +85_C

−0.050 −0.050

−0.075 −0.075
+125_ C

−0.10 −0.10
−24 −20 −16 −12 −8 −4 0 4 8 12 16 20 24 −24 −20 −16 −12 −8 −4 0 4 8 12 16 20 24
Output Current (mA) Output Current (mA)

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APPLICATION INFORMATION
V+ V− GND

C2
100nF

C3
CC 100nF
47nF

GND1
(2)

XTR300 V+ V− Thermal
Pad
I MON Current Copy
I−MON
ICOPY
R3
1kΩ IDRV
VIN RC External Load
S−IN
15Ω
ROS DRV
OPA
2kΩ C4
SET
OS 100nF R6
IAIN+ GND1 2.2kΩ
RIMON
1kΩ RSET I IA CLOAD RLOAD
RG1
SG RGAIN C5
IA R7
10kΩ 10nF
GND1 RG2 2.2kΩ
IA−O
IAOUT IAIN−
GND2
OD EFCM
RIA
1kΩ M1 Digital Error EFLD Logic Supply
Control Flags EFOT (+2.7V to +5V)
M2
DGND
GND3
(1)
Pull−up Resistors
GND4 (10kΩ)

NOTE: (1) See the Electrical Characteristics and Digital Input and Output section for operating limits of DGND.
(2) Connect thermal pad to V−.

The following information should be considered during XTR300 circuit configuration:

D Recommended bypassing: 100nF or more for D R6, R7, and C5 protect the IA.
supply bypassing at each supply. D RLOAD and CLOAD represent the load resistance and
D RIMON can be in the kΩ-range or short-circuited if not load capacitance.
used. Do not leave this current output D RSET defines the transfer gain. It can be split to allow
unconnected—it would saturate the internal current a signal offset and, therefore, allow a 5V single-
source. The current at this IMON output is IDRV/10. supply digital-to-analog converter (DAC) to control a
Therefore, VIMON = RIMON (IDRV/10). ±10V or ±20mA output signal.
D R3 is not required but can match RSET (or RSET||ROS) The XTR300 can be used with asymmetric supply voltages;
to compensate for the bias current. however, the minimum negative supply voltage should be
D RIA can be short-circuited if not used. Do not leave equal to or more negative than −3V (typically −5V). This sup-
this current output unconnected. RGAIN is selected to ply value ensures proper control of 0V and 0mA with wire re-
10kΩ to match the output of 10V with 20mA for the sistance, ground offsets, and noise added to the output. For
equal input signal. positive output signals, the current requirement from this
negative voltage source is less than 5mA.
D RC ensures stability for unknown load conditions
and limits the current into the internal protection GND1 through GND4 must be selected to fulfill speci−
diodes. C4 helps protect the device. Over-voltage fied operating ranges. DGND must be in the range of
(V−) ≤ DGND ≤ (V+) −7V.
clamp diodes (standard 1N4002) might be
necessary to protect the output.
Figure 5. Standard Circuit Configuration

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Built on a robust high-voltage BI-CMOS process, the

XTR300 is designed to interface the 5V or 3V supply do-
CC
main used for processors, signal converters, and amplifi-
ers to the high-voltage and high-current industrial signal
environment. It is specified for up to ±20V supply, but can
also be powered asymmetrically (for example, +24V and XTR300 V+ V−

−5V). It is designed to allow insertion of external circuit IMON Current Copy

protection elements and drive large capacitive loads. I COPY
R IMON
I DRV

FUNCTIONAL FEATURES Input Signal GND3 V IN

DRV
OPA
The XTR300 provides two basic functional blocks: an in- SET

strumentation amplifier (IA) and a driver that is a unique IA IN+

operational amplifier (OPA) for current or voltage output. R SET IIA RG 1

This combination represents an analog output stage which IA
RG 2
R GAIN Load

can be digitally configured to provide either current or volt- GND1 IA IN−

age output to the same terminal pin. Alternatively, it can be IA OUT

configured for independent measurment channels. OD EFCM

GND2
M1 Digital Error EF LD
Three open collector error signals are provided to indicate L
M2
Control Flags EF OT
L
output related errors such as over-current or open-load DGND
(EFLD) or exceeding the common-mode input range at the
IA inputs (EFCM). An over-temperature flag (EFOT) can be
used to control output disable to protect the circuit. The
monitor outputs (IMON and IAOUT) and the error flags offer Figure 6. Simplified Voltage Output Mode
optimal testability during operation and configuration. The Configuration
IMON output represents the current flowing into the load in
voltage output mode, while the IAOUT represents the volt-
age across the connectors in current output mode. Both Applications not requiring the remote sense feature can
monitor outputs can be connected together when used in use the OPA in stand-alone operation (M1 = high). In this
current or voltage output mode because the monitor sig- case, the IA is available as a separate input channel.
nals are multiplexed accordingly. The IA gain can be set by two resistors, RGAIN and RSET:

R GAIN
VOLTAGE OUTPUT MODE V OUT + V
2RSET IN (1)
In voltage output mode (M1 and M2 are connected low or
left unconnected), the feedback loop through the IA pro-
or when adding an offset, VREF, to get bidirectional output
vides high impedance remote sensing of the voltage at the
with a single-ended input:
destination, compensating the resistance of a protection

ǒ Ǔ
circuit, switches, wiring, and connector resistance. The
RGAIN V IN V * V REF
output of the IA is a current that is proportional to the input V OUT + ) IN
voltage. This current is internally routed to the OPA sum- 2 R SET R OS (2)
ming junction through a multiplexer, as shown in Figure 6.
A 1:10 copy of the output current of the OPA can be moni- The RSET resistor is also used in current output mode.
tored at the IMON pin. This output current and the known Therefore, it is useful to define RSET for the current mode,
output voltage can be used to calculate the load resistance then set the ratio between current and voltage span with
or load power. RGAIN.
During an output short-circuit or an over-current condition
the XTR300 output current is limited and EFLD (load error,
active low) flag is activated.

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CURRENT OUTPUT MODE INPUT SIGNAL CONNECTION

The XTR300 does not require a shunt resistor for current It is possible to drive the XTR300 with a unidirectional input
control because it uses a precise current mirror arrange- signal and still get a bidirectional output by adding an addi-
ment. tional resistor, ROS, and an offset voltage signal, VREF. It
In current output mode (M1 connected low, or left uncon- can be a mid-point voltage or a signal to shift the output
nected and M2 connected high) a precise copy of 1/10th voltage to a desired value.
of the output is internally routed back to the summing junc- This design is illustrated in Figure 8a, Figure 8b, and
tion of the OPA through a multiplexer, closing the control Figure 8c. As with a normal operational amplifier, there are
loop for the output current. several options for offset-shift circuits. The input can be
The OPA driver can deliver more than ±24mA within a wide connected for inverting or noninverting gain. Unlike many
output voltage range. An open-output condition or high-im- op amp input circuits, however, this configuration uses cur-
pedance load that prevents the flow of the required current rent feedback, which removes the voltage relationship be-
activates the EFLD flag. tween the noninverting input and output potential because
there is no feedback resistor.
While in current output mode, a current (IIA) that is propor-
tional to the voltage at the IA input is routed to IAOUT and
a) Noninverting Input
can be used to monitor the load voltage. A resistor con-
verts this current into voltage. This arrangement makes
XTR300
level shifting easy. VIN
Alternatively, the IA can be used as an independent moni- (0 to VOFFSET)

toring channel. If this output is not used, connect it to GND

OPA
to maintain proper function of the monitor stage, as shown
VREF
in Figure 7. ROS RSET
2kΩ 2kΩ
I−Feedback

XTR300 V+ V−

IMON Current Copy

ICOPY b) Noninverting Input

IDRV
Input Signal XTR300
V IN
VIN
DRV
OPA (± VMIDSCALE)
SET

IAIN+
R SET
OPA
IIA RG 1
R GAIN
VMIDSCALE
IA Load
RG 2 RSET
GND1
IAIN−
1kΩ
IA OUT I−Feedback
GND2
OD EFCM
RIA
M1 Digital Error EF LD
L
Control Flags EFOT
M2
H
DGND
GND3

c) Inverting Input (VREF = VOFFSET)

Figure 7. Simplified Current Output Mode XTR300

Configuration
VREF
The transconductance (gain) can be set by the resistor, OPA
RSET, according to the equation: VIN
(± VOFFSET)
RSET
I OUT + 10 V IN 1kΩ
RSET (3) I−Feedback

or when adding an offset VREF to get bidirectional output

with a single-ended input:

I OUT + 10 ǒRV IN

SET
)
VIN * VREF
R OS
Ǔ (4)
Figure 8. Circuit Options for Op Amp Output
Level-Shifting

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The input bias current effect on the offset voltage can be ting. When M1 is high, the internal feedback connections
reduced by connecting a resistor in series with the positive are opened; IAOUT and IMON are both connected to the out-
input that matches the approximate resistance at the neg- put pins; and M2 only determines the current limit (ISC) set-
ative input. This resistor placed close to the input pin acts ting.
as a damping element and makes the design less sensitive
to RF noise. See R3 in Figure 5.
SUMMARY OF CONFIGURATION MODES(1)
M1 M2 MODE DESCRIPTION
EXTERNALLY-CONFIGURED MODE:
OPA AND IA L L VOUT Voltage Output Mode, ISC = 20mA
L H IOUT Current Output Mode, ISC = 32mA
It is possible to use the precision of the operational amplifi-
er (OPA) and instrumentation amplifier (IA) independently H L Ext IA and IMON on ext. pins, ISC = 20mA
from each other by configuring the digital control pins (M1 H H Ext IA and IMON on ext. pins, ISC = 32mA
high). In this mode, the IA output current is routed to IAOUT (1) OD is a control pin independent of M1 or M2. See the Driver
and the copy of the OPA output current is routed to IMON, Output Disable section.
as shown in Figure 4.
Table 1. Mode Configuration
This mode allows external configuration of the analog sig-
nal routing and feedback loop.
The current output IA has high input impedance, low offset M1 and M2 are pulled low internally with 1µA. Terminate
voltage and drift, and very high common-mode rejection these two pins to avoid noise coupling.
ratio. An external resistor (RIA) can be used to convert the
Output disable (OD) is internally pulled high with approxi-
output current of the IA (IIA) to an output voltage. The gain
mately 1µA.
is given by:

2 2RIA DRIVING CAPACITIVE LOADS AND LOOP

I IA + V IN or VIA + V
RGAIN RGAIN IN (5) COMPENSATION
For normal operation, the driver OPA and the IA are con-
The OPA provides low drift and high voltage output swing nected in a closed loop for voltage output. In current output
that can be used like a common operational amplifier by mode, the current copy closes the loop directly.
connecting a feedback network around it. In this mode, the
copy of the output current is available at the IMON pin (it in- In current output mode, loop compensation is not critical,
cludes the current into the feedback network). It provides even for large capacitive loads. However, in voltage output
an output current limit for protection, which can be set be- mode, the capacitive load, together with the source imped-
tween two ranges by M2. The error flag indicates an over- ance and the impedance of the protection circuit, gener-
current condition, as well as indicating driving the output ates additional phase lag. The IA input might also be pro-
into the supply rails. tected by a low-pass filter that influences phase in the
closed loop.
Alternatively, the feedback can be closed through the IMON
pin to create a precise voltage-to-current converter. The loop compensation low-pass filter consists of CC and
the parallel resistance of ROS and RSET. For loop stability
with large capacitive load, the external phase shift has to
be added to the OPA phase. With CC, the voltage gain of
DRIVER OUTPUT DISABLE the OPA has to approach zero at the frequency where the
The OPA output (DRV) can be switched to a high-imped- total phase approaches 180° + 135°.
ance mode by driving the OD control pin low. This input can The best stability for large capacitive loads is provided by
be connected to the over-temperature flag, EFOT, and a adding a small resistor, RC (15Ω). See the Output Protec-
pull-up resistor to protect the IC from over-temperature by tion section.
disconnecting the load.
An empirical method of evaluation is using a square wave
The output disable mode can be used to sense and mea- input signal and observing the settling after transients. Use
sure the voltage at the IA input pins without loading from small signal amplitudes only—steep signal edges cause
the DRV output. This mode allows testing of any voltage excessive current to flow into the capacitive load and may
present at the I/O connector. However, consider the bias activate the current limit, which hides or prevents oscilla-
current of the IA input pins. tion. A small-signal oscillation can be hidden from large ca-
The digital control inputs, M1 and M2, set the four opera- pacitive loads, but observing the IMON output on an ap-
tion modes of the XTR300 as shown in Table 1. When M1 propriate resistor (use a similar value like RSET||ROS) would
is asserted low, M2 determines voltage or current mode indicate stability issues. Note that noise pulses at IMON dur-
and the corresponding appropriate current limit (ISC) set-

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ing overload (EFLD active) are normal and are caused by

cycling of the current mirror. Current Mirror
The voltage output mode includes the IA in the loop. An
additional low-pass filter in the input reverses the phase IR IR
and therefore increases the signal bandwidth of the loop, IAIN+
but also increases the delay. Again, loop stability has to be A1

observed. Overloading the IA disconnects the closed loop

and the output voltage rails.

Current Mirror
INTERNAL CURRENT SOURCES,
SWITCHING NOISE, AND SETTLING TIME IR RGAIN

The accuracy of the current output mode and the DC per- IR

Current Mirror
formance of the IA rely on dynamically-matched current
mirrors. 2IR

Identical current sources are rotated to average out mis-

match errors. It can take several clock cycles of the internal 2IR
100kHz ocsillator (or a submultiple of that frequency) to A2 IIA
reach full accuracy. This may dominate the settling time to IAIN−
2IR 2IR
the 0.1% accuracy level and can be as much as 100µs in
current output mode or 40µs in voltage output mode.
Current Mirror
A small portion of the switching glitches appear at the DRV
output, and also at the IMON and IAMON outputs. The stan-
dard circuit configuration, with RC, C4, and CC, which are Figure 9. IA Block Diagram
required for loop compensation and output protection, also
helps reduce the noise to negligible levels at the signal out-
put. If necessary, the monitor outputs can be filtered with The output current, IAOUT, of the instrumentation amplifier
a shunt capacitor. is limited to protect the internal circuitry. This current limit
has two settings controlled by the state of M2 (see Electri-
cal Characteristics, Short-Circuit Current specification).
IA STRUCTURE, VOLTAGE MONITOR Note that if RSET is too small, the current output limitation
of the instrumentation amplifier can disrupt the closed loop
The instrumentation amplifier has high-impedance NPN
of the XTR300 in voltage output mode. With M2 = low, the
transistor inputs that do not load the output signal, which
nominal RGAIN of 10kΩ allows an input voltage of 20VPP,
is especially important in current output mode. The output
which produces an output current of 4mAPP. When using
signal is a controlled current that is multiplexed either to
lower resistors for RGAIN that can allow higher currents, the
the SET pin (to close the voltage output loop) or to IAOUT
IA output current limitation must be taken into account.
(for external access).
The principal circuit is shown in Figure 9. The two input
buffer amplifiers reproduce the input difference voltage CURRENT MONITOR
across RGAIN. The resulting current through this resistor is In current output mode (M2 = high), the XTR300 provides
bidirectionally mirrored to the output. That mirroring results high output impedance. A precision current mirror gener-
in the ideal transfer function of: ates an exact 1/10th copy of the output current and this cur-
rent is either routed to the summing junction of the OPA to
I IA + IAOUT + 2 (IA IN) * IA IN*)ńR GAIN (6) close the feedback loop (in the current output mode) or to
The accuracy and drift of RGAIN defines the accuracy of the the IMON pin for output current monitoring in other operating
voltage to current conversion. The high accuracy and sta- modes.
bility of the current mirrors result from a cycling chopper
technique.

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The high accuracy and stability of this current split results therefore removes the source of power. This
from a cycling chopper technique. This design eliminates connection acts like an automatic shut down, but
the need for a precise shunt resistor or a precise shunt- requires an external pull-up resistor to safely override
voltage measurement, which would require high common- the internal current sources. The IA channel is not
mode rejection performance. affected, which allows continuous observation of the
During a saturation condition of the DRV output (the error voltage at the output.
flag is active), the monitor output (IMON) shows a current
peak because the loop opens. Glitches from the current
mirror chopper appear during this time in the monitor sig- DIGITAL COMMUNICATION: HART
nal. This part of the signal cannot be used for measure-
The bandwidth and drive capability of the XTR300 are
ment.
sufficient to transmit communication signals such as
HART. The combination of current monitor and voltage
ERROR FLAGS sense with the IA circuit enables communication signal
transmission from the signal output connector to the
The XTR300 is designed for testability of its proper func- monitor pins in both current or voltage output mode. In
tion and allows observation of the conditions at the load
current output mode, the signal arrives at IAOUT; in voltage
connection without disrupting service.
output mode the communication signal modulates the
If the output signal is not in accordance to the transfer func- DRV current and arrives at IMON. Both IAOUT and IMON can
tion, an error flag is activated (limited by the dynamic re- be connected together because they are internally
sponse capabilities). These error flags are in addition to multiplexed according to the output mode (while M1 = low).
the monitor outputs, IMON and IAOUT, which allow the mo-
mentary output current (in voltage mode) or output voltage Driving a communication signal through the output
(in current mode) to be read back. connector back into the system or sensor, regardless of
the output mode, enables easy configuration, calibration,
This combination of error flag and monitor signal allows
diagnosis, and universal communication.
easy observation of the XTR300 for function and working
condition, providing the basis for not only remote control,
but also for remote diagnosis. DIGITAL I/O AND GROUND
All error flags of the XTR300 have open collector outputs CONSIDERATIONS
with a weak pull-up of approximately 1µA to an internal 5V.
The XTR300 offers voltage output mode, current output
External pull-up resistors to the logic voltage are required
mode, external configuration, and instrumentation mode
when driving 3V or 5V logic.
(voltage input). In addition, the internal feedback mode can
The output sink current should not exceed 5mA. This is just be disconnected and external loop connections can be
enough to directly drive optical-couplers, but a current-lim- made. These modes are controlled by M1 and M2 (see the
iting resistor is required. function table). The OD input pin controls enable or disable
There are three error flags: of the output stage (OD is active low).
D IA Common-Mode Over-Range (EFCM)—goes low The digital I/O is referenced to DGND and signals on this
as soon as the inputs of the IA reach the limits of the pin should remain within 5V of the DGND potential. This
linear operation for the input voltage. DGND pin carries the output low-current (sink current) of
This flag shows noise from the saturated current the logic outputs. DGND can be connected to a potential
mirrors which can be filtered with a capacitor to GND. within the supply voltage but needs to be 8V below the
D Load Error (EFLD)—indicates fault conditions driving positive supply. Proper connection avoids current from the
voltage or current into the load. In voltage output mode digital outputs flowing into the analog ground.
it monitors the voltage limits of the output swing and It is important to note that DGND has normally reverse-
the current limit condition caused from short or low biased diodes connected to the supply. Therefore, high
load resistance. In current output mode it indicates a and destructive currents could flow if DGND is driven
saturation into the supply rails from a high load beyond the supply rails by more than a diode forward
resistance or open load. voltage. Avoid this condition during power-on and
D Over-Temperature Flag (EFOT)—is a digital output power-off!
that goes low if the chip temperature reaches a
temperature of +140°C and resets as soon as it cools
down to +125°C. It does not automatically shut down
the output; it allows the user system to take action on
the situation. If desired, this output can be connected
to output disable (OD) which disables the output and

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OUTPUT PROTECTION RC is also part of the recommended loop compensation. C4

helps protect the output against RFI and high-voltage
The XTR300 is intended to operate in a harsh industrial
spikes.
environment. Therefore, a robust semiconductor process
was chosen for this design. However, some external
CC
protection is still required. 47nF V+

The instrumentation amplifier inputs can be protected by

external resistors that limit current into the protection cell D
behind the IC-pins, as shown in Figure 10. This cell XTR300 1N4002
RC
conducts to the power-supply connection through a diode 15Ω
DRV
as soon as the input voltage exceeds the supply voltage. OPA I/V OUT
The circuit configuration example shows how to arrange
D C4
these two external resistors. 1N4002 100nF
The bias current is best cancelled if both resistors are
equal. The additional capacitor reduces RF noise in the V−
input signal to the IA.
Figure 11. Example for DRV Output Protection

POWER ON/OFF GLITCH

R6
IAIN+ 2.2kΩ When power is turned on or off, most analog amplifiers
VSENSE+
generate some glitching of the output because of internal
RG1
IA RGAIN
C5
R7 circuit thresholds and capacitive charges. Characteristics
RG2 10nF
2.2kΩ of the supply voltage, as well as its rise and fall time, also
VSENSE− directly influence output glitches. Load resistance and
IAIN+
capacitive load affect the amplitude as well.
The output disable control (OD) allows good control over
the output during power-on, power-off, and system down
Figure 10. Current Limiting Resistors time by providing a high impedance to the output.
Figure 12a, Figure 12b, and Figure 12c show the output
voltage with the output disabled during power on and
The load connection to the DRV output must be low off—no glitch can be see on the output signal. Holding OD
impedance; therefore, external protection diodes may be low also prevents glitches in current output mode.
necessary to handle excessive currents, as shown in Figure 12c indicates no glitches when transitioning from
Figure 11. The internal protection diodes start to conduct disable to enable.
earlier than a normal external PN-type diode because they All measurements are made with a load resistance of 1kΩ
are affected by the higher die temperature. Therefore, and tested in the circuit configuration of Figure 5. OD has
either Schottky diodes are required, or an additional an internal pull-up of approximately 1µA; therefore, a
resistor (RC) can be placed in series with the input. An 100kΩ resistor provides safe pull-down during power
example of this protection is shown in Figure 11. Assuming on—make sure the logic controlling the OD pin does not
the standard diodes limit the voltage to 1.4V and the glitch.
internal diodes clamp at 0.7V, this resistor can limit the
current into the internal protection diodes to 50mA:
(1.4V * 0.7V)ń15W + 47mA (7)

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Power−Supply Voltage
Power−Supply Voltage 5.0V/div
5.0V/div

Output Output
0.5V/div 0.5V/div

Time (10ms/div) Time (10ms/div)

a) Power-on in voltage or current output mode. b) Power-off in voltage or current output mode.
CH 1 shows supply voltage; CH 2 output voltage across a 1kΩ load. CH 1 shows supply voltage; CH 2 output voltage across a 1kΩ load.

Output
0.5V/div

OD
2.0V/div

Time (10ms/div)

c) CH 2: Output signal during toggle of OD:

CH 1 voltage or current output mode across a 1kΩ load.

Figure 12. Output Signal with Output Disabled During Power On/Off

LAYOUT CONSIDERATIONS
V+ V−

Supply bypass capacitors should be close to the package

and connected with low-impedance conductors. Avoid L1 L2
noise coupled into RGAIN, and observe wiring resistance. 10µH 10µH
For thermal management, see the Heat Sinking section. CB1
100nF
Layout for the XTR300 is not critical; however, its internal
current chopping works best with good (low dynamic CB2
impedance) supply decoupling. Therefore, avoid through- 100nF
CB3
hole contacts in the connection to the bypass capacitors 1µF
or use multiple through-hole contacts. Switching noise
from chopper-type power supplies should be filtered CB4
1µF
enough to reduce influence on the circuit. Small resistors
(2Ω, for example) or damping inductors in series with the
supply connection (between the DC/DC converter and the V+ V−
XTR circuit) act as a decoupling filter together with the XTR300
bypass capacitor, as shown in Figure 13.

Figure 13. Suggested Supply Decoupling for

Noisy Chopper-Type Supplies

21
"#$$
www.ti.com
SBOS336B − JUNE 2005 − REVISED MARCH 2006

Resistors connected close to the input pins help dampen The QFN package was specifically designed to provide
environmental noise coupled into conductor traces. excellent power dissipation, but board layout greatly
Therefore, place the OPA input- and IA input-related influences the heat dissipation of the package. Refer to the
resistors close to the package. Also, avoid additional wire QFN Package section for further details.
resistance in series to RSET, ROS, and RGAIN (observe the
The XTR300 has a junction-to-ambient thermal resistance
reliability of the through-hole contacts), because this could
(qJA) value of 38°C/W when soldered to a 2-oz copper
produce gain and offset error as well as drift; 1Ω is already
plane. This value can be further decreased by the addition
0.1% of the 1kΩ resistor.
of forced air. See Table 2 for the junction-to-ambient
The exposed lead-frame die pad on the bottom of the thermal resistance of the QFN-20 package. Junction
package must be connected to V−, pin 11 (see the QFN temperature should be kept below +125°C for reliable
Package section for more details). operation. The junction temperature can be calculated by:
TJ = TA + PD • qJA
QFN PACKAGE where qJA = qJC + qCA
TJ = Junction Temperature (°C)
The XTR300 is available in a QFN package. This leadless, TA = Ambient Temperature (°C)
near chip-scale package maximizes board space and PD = Power Dissipated (W)
enhances thermal and electrical characteristics through qJA = Junction-to-Ambient Thermal Resistance
an exposed pad. qJC = Junction-to-Case Thermal Resistance
qCA = Case-to-Air Thermal Resistance
QFN packages are physically small, have a smaller
routing area, and improved thermal performance. For
optimal heat performance, the exposed power pad must HEATSINKING METHOD qJA
be connected to an adequate heat slug with at least six
The part is soldered to a 2-oz copper pad under the
thermal vias to a copper area. See the example land 38
exposed pad.
pattern RGW (S-PQFP-N20), available for download at
www.ti.com or at the end of this datasheet. Soldered to copper pad with forced airflow (150lfm). 36
Soldered to copper pad with forced airflow (250lfm). 35
The QFN package can be easily mounted using standard
Soldered to copper pad with forced airflow (500lfm). 34
printed circuit board (PCB) assembly techniques. See
Application Note, QFN/SON PCB Attachment (SLUA271) Table 2. Junction-to-Ambient Thermal Resistance
and Application Report, Quad Flatpack No−Lead Logic with Various Heatsinking Efforts
Packages (SCBA017), available for download at
www.ti.com, for more information. To appropriately determine the required heatsink area,
required power dissipation should be calculated and the
The exposed leadframe die pad on the bottom of the relationship between power dissipation and thermal
package must be connected to the V− pin, and proper heat resistance should be considered to minimize overheat
sinking has to be provided. conditions and allow for reliable long-term operation.
The efficiency of the heat sinking can be tested using the
HEAT SINKING EFOT output signal. This output goes low at nominally
+140°C junction temperature (assume 6% tolerance).
Power dissipation depends on power supply, signal, and With full-power dissipation—for example, maximum
load conditions. It is dominated by the power dissipation of current into a 0Ω load—the ambient temperature can be
the output transistors of the OPA. For DC signals, power slowly raised until the OT flag goes low; at this point, the
dissipation is equal to the product of output current, IOUT usable operation condition is determined.
and the output voltage across the conducting output
transistor (VS − VOUT). The recommended landing pattern is shown in document
RGW (S-PQFP-N20). The nine (not less than six) through-
It is important to note that the temperature protection will hole contacts of the inner heat sink solder pad connect to
not shut the part down in over-temperature conditions, a copper plane in any one layer. It must be large enough
unless the EFOT pin is connected to the output enable pin to efficiently distribute the heat into the PCB. This pad has
OD; see the section on Driver Output Disable. to be electrically connected to the V− pin to provide the
The power that can be safely dissipated by the package is required substrate connection.
related to the ambient temperature and the heatsink
design.

22
 PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2007

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
XTR300AIRGWR ACTIVE QFN RGW 20 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
XTR300AIRGWRG4 ACTIVE QFN RGW 20 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
XTR300AIRGWT ACTIVE QFN RGW 20 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
XTR300AIRGWTG4 ACTIVE QFN RGW 20 250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2008

TAPE AND REEL BOX INFORMATION

Device Package Pins Site Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Diameter Width (mm) (mm) Quadrant
(mm) (mm)
XTR300AIRGWR RGW 20 SITE 41 330 12 5.3 5.3 1.5 8 12 Q2
XTR300AIRGWT RGW 20 SITE 41 180 12 5.3 5.3 1.5 8 12 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2008

Device Package Pins Site Length (mm) Width (mm) Height (mm)
XTR300AIRGWR RGW 20 SITE 41 346.0 346.0 29.0
XTR300AIRGWT RGW 20 SITE 41 190.5 212.7 31.75

Pack Materials-Page 2
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