Verilog Lab

Department of Electronics and Communication Engineering
(ACADEMIC YEAR 2021-22)
LABORATORY MANUAL
By: Smt.Meenakshi A Hugar
E&CE Dept.
SUBJECT: HDL LABORATORY

SUB CODE: 20EC32P
SEMESTER:III
E&CE DEPT,HKES POLYTECHNIC-CAMP-RAICHUR

VERILOG LAB 20EC32P
8
PART A
1 Write a Verilog program for the following combinational designs

a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer.
4 bit binary to gray converter
2 Model in Verilog for a full adder and add functionality to perform logical operations of XOR,
XNOR, AND and OR gates. Write test bench with appropriate input patterns to verify the
modeled behaviour.
3 Write a Verilog code to model 32 bit ALU using the schematic diagram shown Below
 ALU should use combinational logic to calculate an output based on the four bit op-code
input.
 ALU should pass the result to the out bus when enable line in high, and tri-state the out
bus when the enable line is low.
 ALU should decode the 4 bit op-code according to the example given below.
OPCODE ALU
Operation
1. A+B
2. A-B
3. A
Complement
4. A*B
5. A AND B
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VERILOG LAB 20EC32P
8
6. A OR B
7. A NAND B
8. A XOR B
4 Write Verilog code for SR, D and JK and verify the flip flop.
5 Write Verilog code for 4-bit BCD synchronous counter.
6 Write Verilog code for counter with given input clock and check whether it works asclock
divider performing division of clock by 2, 4, 8 and 16. Verify the functionality of the code.
PART-B
7 Write a Verilog code to design a clock divider circuit that generates 1/2, 1/3rd and 1/4thclock from a
given input clock. Port the design to FPGA and validate the functionality through oscilloscope.
8 Interface a DC motor to FPGA and write Verilog code to change its speed and direction.
9 Interface a Stepper motor to FPGA and write Verilog code to control the Stepper motor rotation which in
turn may control a Robotic Arm. External switches to be used for different controls like rotate the Stepper
motor (i) +N steps if Switch no.1 of a Dip switch is closed (ii) +N/2 steps if Switch no. 2 of a Dip switch
is closed (iii) –N steps if Switch no. 3 of a Dip switch is closed etc.
10 Interface a DAC to FPGA and write Verilog code to generate Sine wave of frequency F KHz (eg. 200
11 KHz) frequency. Modify the code to down sample the frequency to F/2 KHz. Display the Original and
12 Down sampled signals by connecting them to an oscilloscope.
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Introduction to HDL
An HDL is a programming language used to describe electronic circuit essentially digital

logic circuits. It can be used to describe the operation, design and organization of a digital
circuit. It can also be used to verify the behaviour by means of simulations. The principle
difference between HDL and other programming languages is that HDL is a concurrent
language whereas the others are procedural i.e. single threaded. HDL has the ability to
model multiple parallel processes like adders, flip-flops etc which execute automatically and
independently of each other. It is like building many circuits that can operate independently
of each other.
The two widely used HDLs are:
VHDL: Very High Speed Integrated Circuits HDL
Verilog HDL
VHDL (VHSIC Hardware Description Language) is a hardware description language

used in electronic design automation to describe digital and mixed-signal systems such as
field-programmable gate arrays and integrated circuits. VHDL can also be used as a general
purpose parallel programming language.
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to
model electronic systems. It is most commonly used in the design and verification of digital
circuits at the register-transfer level of abstraction. It is also used in the verification of
analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.
Difference between Verilog and VHDL
1. VHDL is based on Pascal and ADA while Verilog is based on C language.

2. VHDL is strongly typed i.e., does not allow the intermixing, or operation of variables,
with different classes whereas Verilog is weakly typed.
3. VHDL is case insensitive and Verilog is case sensitive.
4. Verilog is easier to learn compared to VHDL.
5. Verilog has very simple data types, while VHDL allows users to create more complex
data types.
6. Verilog lacks the library management, like that of VHDL.
FPGA DESIGN FLOW

1. Design Entry – the first step in creating a new design is to specify it's structure and
functionality. This can be done either by writing an HDL model using some text editor or
drawing a schematic diagram using schematic editor.
2. Design Synthesis – next step in the design process is to transform design specification
into a more suitable representation that can be further processed in the later stages in the
design flow. This representation is called the netlist. Prior to netlist creation synthesis tool
checks the model syntax and analyse the hierarchy of your design which ensures that your
design is optimized for the design architecture you have selected. The resulting netlist is
saved to a Native Generic Circuit (NGC) file (for Xilinx® Synthesis Technology (XST)
compiler) or an Electronic Design Interchange Format (EDIF) file (for Precision, or
Synplify/Synplify Pro tools).
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3. Design Implementation
Implementation step maps netlist produced by the synthesis tool onto particular device's
internal structure. It consists from three steps:
3.1 Translate step – merges all incoming netlists and constraints into a Xilinx Native
Generic Database (NGD) file.
3.2 Map step - maps the design, specified by an NGD file, into available resources on
the target FPGA device, such as LUTs, Flip-Flops, BRAMs,... As a result, an Native
Circuit Description (NCD) file is created.
3.3 Place and Route step - takes a mapped Native Circuit Description (NCD) file,
places and routes the design, and produces an NCD file that is used as input for bit
stream generation.
Figure: FPGA Design Flow
4. Design Verification – is very important step in design process. Verification is

comprised of seeking out problems in the HDL implementation in order to make it compliant
with the design specification. A verification process reduces to extensive simulation of the
HDL code. Design Verification is usually performed using two approaches: Simulation and
Static Timing Analysis.
There are two types of simulation:

Functional (Behavioral) Simulation – enables you to simulate or verify a code syntax
and functional capabilities of your design. This type of simulation tests your design
decisions before the design is implemented and allows you to make any necessary
changes early in the design process. In functional (behavioral) simulation no timing
information is provided.
Timing Simulation – allows you to check does the implemented design meet all
functional and timing requirements and behaves as you expected. The timing simulation
uses the detailed information about the signal delays as they pass through various logic
and memory components and travel over connecting wires. Using this information it is
possible to accurately simulate the behaviour of the implemented design. This type of
simulation is performed after the design has been placed and routed for the target PLD,
because accurate signal delay information can now be estimated. A process of relating
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accurate timing information with simulation model of the implemented design is called
Back-Annotation.
 Static Timing Analysis – helps you to perform a detailed timing analysis on mapped,
placed only or placed and routed FPGA design. This analysis can be useful in evaluating
timing performance of the logic paths, especially if your design doesn't meet timing
requirements. This method doesn't require any type of simulation.
5. Generate Programming File – this option runs BitGen, the Xilinx bitstream generation
program, to create a bitstream file that can be downloaded to the device.
6. Programming – iMPACT Programmer uses the output from the Generate Programming File
process to configure your target device.
7. Testing – after configuring your device, you can debug your FPGA design using the Xilinx
ChipScope Pro tool or some external logic analyzer.
8. Estimate Power – after implementation, you can use the XPower Analyzer for estimation
and power analysis. XPower Analyzer is delivered with ISE Design Suite. With this tool you
can estimate power, based on the logic and routing resources of the actual design.
ABOUT XILINX ISE SOTWARE
Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx

for synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile")
their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to
different stimuli, and configure the target device with the programmer.
Xilinx ISE is a design environment for FPGA(Field programmable gate arrays)
products from Xilinx, and is tightly-coupled to the architecture of such chips, and cannot be
used with FPGA products from other vendors. The Xilinx ISE is primarily used for circuit
synthesis and design, while ISIM or the ModelSim logic simulator is used for system-level
testing
STEPS TO EXECUTE A PROGRAM
1) Starting the ISE software

Start _ program _ XILINX ISE 7 _ Project Navigator
2) Creating a New Project in ISE

A project is a collection of all files necessary to create and to download a design to a
selected FPGA or CPLD devices.
Project name:
Project location:
Top-Level Source Type: HDL
Click Next to move to the project properties page.
3) Fill in the properties in the table as shown below

Device Family: Spartan 3
Device: XC3S50
Package: PQ208Speed
Speed: -5
Top-Level Module Type: HDL

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HDL Synthesis Tool: XST(VHDL/VERILOG)

Simulator: ISE Simulator (VHDL/ Verilog)
4) Creating an HDL Source

Create a top-level HDL file for the design. Determine the language that you wish to
use(Verilog module or VHDL module).
This simple AND Gate design has two inputs: A and B. This design has one output called C
Click New Source in the New Project Wizard to add one new source to your project.
a) Select VERILOG MODULE as the source type in the New Source dialog box.
b) Type in the file name for ex: and_gate
c) Verify that the Add to project checkbox is selected.
d) Click Next.
e) Define the ports for your Verilog source.
In the Port Name column, type the port names on three separate rows: A, B and C.
In the Direction column, indicate whether each port is an input, output, or inout.
For A and B, select in from the list. For C, select out from the list.
5) Click next in the Define Verilog Source dialog box.
6) Click Finish in the New Source Information dialog box to complete the new source file
template. Click Next in the New Project Wizard. Click next again.
7) Click Finish in the New Project Information dialog box.
ISE creates and displays the new project in the Sources in Project window and adds the
and_gate.v file to the project.
8) Double-click on the and_gate.v file in the Sources in Project window to open the Verilog
file in the ISE Text Editor.
The and_gate.v file contains:
Module name with the inputs and outputs declared.
9) Add the relationship between input and output after the input and output declared in
module. Save the file by selecting File > Save.
10) When the source files are complete, the next step is to check the syntax of the
design. Syntax errors and typos can be found using this step.
a) Select the counter design source in the ISE Sources window to display the
related processes in the Processes for Source window.
b) Click the “+”next to the Synthesize-XST process to expand the hierarchy.
c) Double-click the Check Syntax process.
11) When an ISE process completes, you will see a status indicator next to the process name.
a) If the process completed successfully, a green check mark appears.
b) If there were errors and the process failed, a red X appears.

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c) A yellow exclamation point means that the process completed successfully, but
some Warnings occurred.
d) An orange question mark means the process is out of date and should be run again.
e) Look in the Console tab of the Transcript window and read the output and
status messages produced by any process that you run.
Caution! You must correct any errors found in your source files. If you continue
without valid syntax, you will not be able to simulate or synthesize your design.
12) After the successful check syntax in the process Examine RTL diagrams.
13) To Create Testbench waveform, Right click on file name in source window, and_gate.v
and add source.
14) Add testbench waveform source with a new file name and click next.
15) A timing window pops up. Click on combinatorial and click next.
16) A graphical window of input and output appears. Make changes according to the truth
table and save.
17) <file_name>.tb file is added to the project.
18) In source window change implementation to behavioral simulation.
19) In process window click on Xilix ISE simulator and RUN. Output window appears.
Analyze the waveforms according to the truth table.
20) Double-click the Assign Package Pins process found in the User Constraints process
group. ISE runs the Synthesis and Translate step and automatically creates a User Constraints
File(UCF). You will be prompted with the following message.
21) Click
Yes to add the UCF file to your project. The file is added to your project and is visible in
the Sources in Project.
22) Now the Xilinx Pin out and Area Constraints Editor (PACE) opens.
23) You can see your I/O Pins listed in the Design Object List window. Enter a pin location
for each pin in the Loc column as specified below
A: P1, B:P2, C:P3
24) Click on the Package View tab at the bottom of the window to see the pins you just
added. Put your mouse over grid number to verify the pin assignment.

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25) Close PACE

Creating Configuration Data
The Program File is a encoded file that is the equivalent of the design in a form that can be
downloaded into the CPLD device.
The final phase in the software flow is to generate a program file and configure the device
Generating a Program File
The Program File is created. It is written into a file called andgate.jed This is the actual
configuration data
1. Double Click the Generate Programming File process located near the bottom of the
Processes for Source window.
This section provides simple instructions for configuring a Spartan-3 xc3s200 device
connected to your PC.
Note: Your board must be connected to your PC before proceeding. If the device on your
board does not match the device assigned to the project, you will get errors. Please refer to
the IMPACT Help for more information. To access the help, select Help > Help Topics
To configure the device:
1. Click the “+” sign to expand the Generate Programming File processes.

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2. Double click on the Configure device IMPACT

3. In the Configure Devices dialog box, verify that Boundary-Scan Mode is selected and
Click Next
4. Verify that Automatically connect to cable and identify Boundary-Scan chain is selected
and click Finish.
5. If you get a message saying that there was one device found, click OK to continue
6. The iMPACT will now show the detected device, right click the device and select New
Configuration File.
7. The Assign New Configuration File dialog box appears. Assign a configuration file to
each device in the JTAG chain. Select the andgate.jed file and click Open
8. Right-click on the counter device image, and select Program... to open the Program
Options dialog box.
9. Click OK to program the device. ISE programs the device and displays Programming
Succeeded if the operation was successful
10. Close IMPACT without saving

VERILOGLAB 20EC32P
BASIC PROGRAM – ALL LOGIC GATES

Aim: Write Verilog code to realize all the logic gates
Learning Objective: To study the Verilog code for all the logic gates
Algorithm:
 Start
 Initialize Input & output ports. .
 Construct the truth table and extract the expression.
 Write the Verilog code using a dataflow modeling style.
 verify the functionality of design with the truth table
 observe the timing diagram and verify
 End the program.
Logic Gates and Truth Table:
VERILOG CODE :
1. AND gate
module and_gate
(a,b,c);
input a;
input b;
output c;
assign c= a&b;
endmodule
2. OR gate
module or_gate
(a,b,c);
input a;
input b;

VERILOGLAB 20EC32P
output c;
assign c= a|b;
endmodule

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3. NOT gate
module not_gate (a,c);

input a;
output c;
assign c= ~a;
endmodule
4. NAND gate
module nand_gate (a,b,c);

input a;
input b;
output c;
assign c= ~(a&b);
endmodule
5. NOR gate
module nor_gate
(a,b,c);
input a;
input b;
output c;
assign c= ~(a|b);
endmodule
6. XOR gate
module xor_gate
(a,b,c);
input a;
input b;
output c;
assign c= a^b;
endmodule
7. XNOR gate
module xnor_gate (a,b,c);

input a;
input b;
output c;
assign c= ~(a^b);
endmodule
VERILOG CODE

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module gates(a_in, b_in, not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op);

input a_in, b_in;
output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;

VERILOGLAB 20EC32P
assign not_op= ~a_in;

assign and_op=a_in&b_in; assign nand_op=~(a_in&b_in);
assign or_op=a_in|b_in;
assign nor_op=~(a_in|b_in); assign xor_op=a_in^b_in;
assign xnor_op=~(a_in^b_in);
endmodule
Result: The Simulation has carried out and verified with respect to truth table.
Outcomes: Familiar with Verilog HDL Program, usage of Xilinx software and understand
ISE Simulator.
VIVA QUESTIONS
1. What is HDL?
2. What is the importance of HDL?
3. What are the differences between CPLD & FPGA?
4. What are the different types of HD Language?
5. What is Module?
6. What is entity & architecture?
7. What is package?
8. What is port?
9. Whether VHDL is case sensitive or not?
10. What is bit?
11. What is keyword?
12. What is binding?
13. What is import?
14. What is out port?
15. What is buffer?
16. What is inout port?
17. What are the different types of operator?
18. What is operator?
19. What are the different types of operator?
20. What are logical operators?
21. What are relational operators?
22. What are arithemetic operator?
23. What are shift operator?
24. What are Boolean logical operator?
25. What are rotate operator?
26. What is data type?
27. What are the different types of data types?
28. What are the different types of scalar types?
29. What are files types?
30. What are the different verilog data types?
31. What are the different types of styles or architecture?
32. What is behavioral description?
33. What is structural description?
34. What is switch level description?
35. What is data flow description?
36. What is mixed-language description?

VERILOGLAB 20EC32P
37. What is simulation?

38. What is synthesis? What is wire?
39. What are the differences between VHDL & Verilog?
40. What is mixed-type description?
41. What is procedure?
42. What is function and task?

VERILOGLAB 20EC32P
PROGRAM 1 – COMBINATIONAL CIRCUITS

AIM: Write a Verilog program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer.
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
Learning Objective: To write Verilog code for different combinational circuits in any
modeling styles.
Algorithm:
 Start
 Construct the truth table.
 Write the Verilog code using a behavioral modeling style with respect to the truth
table
 verify the functionality of design referring to truth table
 observe the timing diagram
i) 2 to 4 decoder
Figure: 2 to 4 Decoder

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VERILOG CODE :
Structural code for 2 to 4 decoder
module 2to4dec( input [1:0] d_in, output [3:0] d_op);

wire d0_bar, d1_bar;
not a1(d0_bar, d_in[0]);
not a2(d1_bar, d_in[1]);
and a3(d_op[0],d1_bar,d0_bar);
and a4(d_op[1],d1_bar,d_in[0]);
and a5(d_op[2],d_in[1],d0_bar);
and a6(d_op[3],d_in[1],d_in[0]);
endmodule
ii a). 8:3 Encoder [Without Priority]
VERILOG CODE :
module encoder8_3(en, a_in, y_op);

input en;
input [7:0] a_in;
output [2:0] y_op;
reg [2:0] y_op;
always @ (a_in,en)
begin
if(en==1 )
y_op =3‟bzzz;
else
case (a_in)
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8'b00000001: y_op = 3'b000;

8'b00000010: y_op = 3'b001;
8'b00000100: y_op = 3'b010;
8'b00001000: y_op = 3'b011;
8'b00010000: y_op = 3'b100;
8'b00100000: y_op = 3'b101;
8'b01000000: y_op = 3'b110;
8'b10000000: y_op = 3'b111;
default: y_op =3'bxxx;
endcase
end
endmodule

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ii b) 8:3 Encoder [With Priority]
VERILOG CODE:
module prio_enco(en, a_in, y_op);
input en;
input [7:0] a_in;
output [2:0] y_op;
reg [2:0] y_op;
always @ (a_in,en)
begin
if(en==1) y_op = 3‟bzzz;
if(a_in[7] == 1) y_op = 3‟b000;
if(a_in[6] == 1) y_op = 3‟b001;
if(a_in[5] == 1) y_op = 3‟b010;
if(a_in[4] == 1) y_op = 3‟b011;
if(a_in[3] == 1) y_op = 3‟b100;
if(a_in[2] == 1) y_op = 3‟b101;
if(a_in[1] == 1) y_op = 3‟b110;
if(a_in[0] == 1) y_op = 3‟b111;
default: y_op=3'bxxx;
end
endmodule

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iii) 8:1 MULTIPLEXER
VERILOG CODE :
module mux8_1(en,i_in, sel, y_out);
input en;
input [7:0] a_in;
input [2:0] sel;
output y_out;
reg y_out;
always@ (i_in,sel )
begin
if(en==1)
y_out=1‟bz;
else
case (sel)
3'b000:y_out=i_in[0];
3'b001: y_out=i_in[1];
3'b010: y_out=i_in[2];
3'b011: y_out=i_in[3];
3'b100: y_out=i_in[4];
3'b101: y_out=i_in[5];
3'b110: y_out=i_in[6];
3'b111: y_out=i_in[7];

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default: y_out =3'bxxx;

endcase
end
endmodul
e
iv.a) 4 BIT BINARY TO GRAY

Logic Diagram :
Truth Table :
Binary Inputs (b_in) Gray Outputs (g_op)

b_in[3] b_in[2] b_in[1] b_in[0] g_op[3] g_op[2] g_op[1] g_op[0]
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 0 0 1 1 1
0 1 1 1 0 1 0 1
0 1 1 0 0 1 0 0
1 0 0 1 1 1 0 0
1 0 0 0 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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K-MAP FOR G2:

K-MAP FOR G3:
Equation for G2= B3‟ B2 + B3 B2‟

Equation for G3= B3
G2= B3 XOR B2
K-MAP FOR G1: K-MAP FOR G0:
Equation for G1= B1‟ B2 + B1 B2‟ Equation for G0= B1‟ B0 + B1 B0‟
G1= B1 XOR B2 G0= B1 XOR B0
VERILOG CODE:
module binary_gray(b_in, g_op);

input [3:0] b_in;
output [3:0] g_op;
assign g_op[3] = b_in[3];
assign g_op[2] = b_in[3] ^ b_in[2];

VERILOGLAB 20EC32P

endmodule
Outcomes: Be able to model digital systems at several levels of abstractions and also able to
write the Verilog HDL code for different combinational circuits by using truth table in
dataflow and behavioral model.
VIVA QUESTIONS:
1. What is package?
2. What is Library function?
3. What is process?
4. What is signal assignment operator?
5. What is signal?
6. What is Vector?
7. Why do we need Procedures, Tasks and Functions?
8. Explain the difference between Function and Procedure in VHDL?
9. Explain the difference between Function and Task in Verilog?
10. How do we specify the signals in Procedure‟s declaration?
11. Give an Example of a built-in Procedure?
12. Give an Example of a built-in Task?
13. Where the Procedures can be called from(from which part of the Program)?
14. Where the Tasks can be called from(from which part of the Program)?
15. Where the Functions can be called from(from which part of the Program) in VHDL?
16. Where the Tasks can be called from(from which part of the Program) in Verilog?
17. What does return statement do in Functions?
18. Give Examples for built-in Function?
19. What are the limitation for Mixed –Language Description?
20. What are the Advantages of Mixed-Language Description?

VERILOGLAB 20EC32P
PROGRAM - 2 ADDERS
AIM: Write a Verilog code to describe the functions of a Full Adder .
Learning Objective: To study the working and writing HDL code for Adders.
Algorithm:
 Start
 Construct the truth table and extract the expression also draw the logic circuit.
 Write the Verilog code using a dataflow, behavioral and structural modeling styles
with respect to the truth table, expression and logic circuit.
Block Diagram:

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CODE :
i) Verilog - Data Flow Style :
module fulladder(a_in, b_in, c_in, sum, carry);

input a_in, b_in,c_in;
output sum, carry;
assign sum = a_in ^ b_in ^ c_in;
assign carry = (a_in & b_in) | (b_in & c_in) | (a_in & c_in);
endmodule
ii) Verilog - Behavioral Style:
module fulladder(a,b,c, sum, carry);

input [2:0] a,b,c;
output sum,carry;
reg sum,carry;
always@(a,b,c)
begin
case ({a,b,c})
3‟b000:{sum,carry}=2‟b00;
default: {sum,carry}=2‟bxx;
endcase
end
endmodul
e

VERILOGLAB 20EC32P
iii)Verilog - Structural Style
module full_adder (a,b,c,sum,carry);

input a,b,c;
output sum,carry;
wire s1,c1,c2,c3;
xor(s1,a,b);
xor(s,c,s1);
and(c1,a,b);
and(c2,s1,cin);
or(carry,c1,c2);
endmodule
(Extra Stuff)
iii) Verilog - Structural Style (Using two half adders) :
module fulladder (a_in, b_in, c_in, sum,

carry); input a_in, b_in, c_in;
output sum, carry;
wire temp1, temp2, temp3;
halfadder ha1 (a_in, b_in, temp1, temp2);
halfadder ha2 (c_in, temp1, sum, temp3);
or g3 (carry,temp3,temp1);
endmodule
module halfadder(a, b, s, c);

input a, b;
output s, c;
xor g1 (s, a, b);
and g2 (c, a, b);
endmodule

VERILOGLAB 20EC32P
Outcomes: Be able to design a model in three modeling style such as dataflow, behavioral
and structural.
VIVA QUESTIONS
1. Give an Example of a built-in Procedure?

2. Give an Example of a built-in Task?
3. Where the Procedures can be called from(from which part of the Program)?
4. Where the Tasks can be called from(from which part of the Program)?
5. Where the Functions can be called from(from which part of the Program) in VHDL?
6. Where the Tasks can be called from(from which part of the Program) in Verilog?
7. What does return statement do in Functions?
8. Give Examples for built-in Function?
9. What are the limitations for Mixed –Language Description?
10. What are the Advantages of Mixed-Language Description?

VERILOGLAB 20EC32P
PROGRAM 3 - ARITHMETIC LOGIC UNIT

AIM: Write a Verilog code to a model for 32 bit ALU for given schematic diagram.
Learning Objective: Design of ALU unit and knowing the operation of ALU.
OP-CODE ALU OPERATION

1. A+B
2. A-B
3. A Complement
4. A*B
5. A AND B
6. A OR B
7. A NAND B
8. A XOR B
Algorithm:
 Start
 Write the Verilog code using a behavioral modeling style for a given opcode
VERILOG CODE:
module alu(a, b, opcode,en,y,y_mul);
input [31:0] a;
input [31:0] b;
input en;
input [2:0] opcode;
output [31:0] y;
output[63:0]y_mul;
reg [31:0] y;
reg [63:0] y_mul;
always @(a, b , opcode)
begin
if (en==1)
case (opcode)
3'b000:y=a+b;
3'b001:y=a-b;
3'b010:y=~a;
3'b011:y_mul=a*b
; 3'b100:y= a&b;
3'b101:y=a|b;
3'b110:y=~(a&b);
3'b111:y=a^b;
default:begin end
endcase

VERILOGLAB 20EC32P
else
begin
y=32‟bz;
y_mul=64‟bz
end
end
endmodul
e
Outcomes: Be able to design a small digital circuit and functional verification is learned.
VIVA QUESTIONS
1. How do you invoke a VHDL Entity from a Verilog Module?

2. How do you invoke a Verilog Entity from a VHDL Module?
3. List the VHDL data types that ate supported in Mixed-Language Description?
4. Which port type of VHDL is not supported in Mixed-Language Description?
5. Which is the only construct of VHDL that can invoke a Verilog Module?
6. A Verilog Module cannot invoke Procedures or Functions of VHDL Module-T/F?
7. What are the Conditions to be met to invoke a Verilog Module from a VHDL Module?
8. What are the Conditions to be met to invoke a VHDL Module from a Verilog Module?
9. What is Mixed language description?
10. How do you invoke VHDL entity from a Verilog module?
11. How do you invoke Verilog module from a VHDL module?
12. What are the limitations of Mixed Language description?
13. What is Synthesis?
14. Differentiate between Synthesis and Simulations?
15. What are the steps followed in Synthesis?

VERILOGLAB 20EC32P
PROGRAM 4 - FLIP FLOPS

AIM: Develop the Verilog code for the following Flip-Flops:
a. SR FF
b. D FF
c. JK FF
d. T FF
Learning Objective: To Study and write the Verilog code for mention Flip-Flops
Algorithm:
 Start
table
Note: The same Algorithm follows for all types of flip flops.
a. JK FLIP-FLOP
VERILOG CODE :
module jk_ff(jk, clk, rst, q, qb);

input [1:0]jk;
input rst, clk;
output q,qb;

VERILOGLAB 20EC32P
reg q,qb;
always @ (posedge clk)
begin
if (rst==1)
begi
n q=0;
qb=1;
end
else
case (jk)
2'b00: begin
q=q; qb=qb;
end
2'b01: begin
q=0; qb=1;
end
2'b10: begin
q=1; qb=0;
end
2'b11: begin
q=~q; qb=~qb;
end
default:begin end
endcase
end
endmodule
b. SR FLIPFLOP
VERILOG CODE :
module sr_ff(sr, clk, rst, q, qb);

input [1:0]sr;
input rst, clk;
VERILOGLAB 20EC32P
output q,qb;
reg q,qb;
begin
if (rst==1)
begin
q=0; qb=1;
end
else
case (sr)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=1'bx; qb=1'bx; end
default:begin end
endcase
end
endmodule
c. T-FLIPFLOP
Algorithm:
Start
Initialize T is reset and CLK as input ,a and qn as ouput
If clk=‟1‟ and an event on the positive pulse
If t=0 then q=1 else q=0 qb=1
Stop

VERILOGLAB 20EC32P
VERILOG CODE :
module tff (t,clk,rst, q,qb);

input t,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0)
begin
case(t)
1‟b0:q=q;
1‟b1:q= ~q;
endcase
qb=~q;
end
endmodule
D-FLIPFLOP
VERILOG CODE :
module d_ff(d, rst, clk, q, qb);

input d;
input rst;
input clk;
output q;
output qb;
reg q,qb;
always@(posedge clk)

VERILOGLAB 20EC32P
begin
if (rst==1)
begi
n q=0; qb=1;
end
else
begin
q=d; qb=~d;
end
end
endmodule
Outcomes: Be able to model a memory system with clock.
VIVA QUESTIONS
1. Which part of the Program provides information about the inputs, outputs and their types?
2. How do you map an array onto a logic diagram?
3. How the Sequential statements are mapped onto a logic diagram?
4. How the following codes can be mapped onto logic diagram?
a. Process(a,x,x1) b. Cases(ct) c. for i in 0 to 3 loop d. begin e. 1‟b0:4‟b d=a+b; f.
ifa(i)=‟1‟ g. then h. if(a = „1‟) then i. 1‟b1: ; j. result:=result+2**I k. endcase l. end if; m.
Else n.Y<=x1; o. end loop; p. End if;
5. How the Procedures/ tasks are mapped?
6. How the Functions are mapped?
7. Differentiate between procedure mapping and function mapping?
8. What is Simulation?
9. On what basis the codes are synthesized.
10. What is meant by mapping?
11. What are the functions of compiler?
12. Will different Simulators assign same number of gates for a single code?
13. Is there any differences between mapping or signal and variable assignment? Statement?
14. Differentiate between behavioral and structural descriptions?
15. In which applications behavioral desc is used?
16. Explain the Structure of behavioral?
17. Difference between process and always?
18. Explain Syntax of process?
19. What is Sensitivity list?
20. What is Event?
21. Is process a Concurrent or Sequential Statement?
22. What is “INITIAL”?
23. Why Label required for a statement?
24. Explain structure of IF-ELSE statement?
25. Explain structure of CASE statement?
26. Explain different Loops Structures?
27. How is For different from While?
28. How is 2‟s Compliment computed in VHDL?
29. Differentiate between Active High and Active Low Signal?
VERILOGLAB 20EC32P
30. Differentiate between Synchronous and Asynchronous Clear Signal?

VERILOGLAB 20EC32P
PROGRAM 5 - COUNTERS
AIM: Design 4 bit binary, BCD Counter (Synchronous reset and Asynchronous reset) and
“any sequence” Counters.
Learning Objective: To study and write the code for Sequential circuits.
Algorithm:
 Start
table
A. BINARY COUNTER
module binary_counter (clk, rst, bin_count);

input clk, rst;
output [3:0] bin_count;
reg [3:0] bin_count;
initial
bin_count =
4‟b0000; always @
(posedge clk)
begin
if (rst)
bin_count = 3'b0000;
else
bin_count = bin_count + 1'b1;
end
endmodule
B. BCD COUNTER
module BCD_Counter ( clk ,reset ,dout );

input clk ;
input reset ;
output [3:0] dout ;
reg [3:0] dout ;
initial
dout = 0 ;
begin
if (reset)
dout = 0;
VERILOGLAB 20EC32P
else
if (dout<=9)
dout = dout + 1;
else
if (dout==9) begin
dout <= 0;
end
end
endmodule
Synchronous Counter
C. SYNCHRONOUS With Reset - UP COUNTER

module syn_up_counter (clk ,rst ,enable ,up_ count);
input clk ;
input rst ;
input enable ;

VERILOGLAB 20EC32P
output [3:0] up_count;

wire clk ;
wire rst ;
wire enable ;
reg [3:0] up_count;
always @ (posedge clock)
begin
if (reset == 1'b1)
begin
up_count <= 4'b0000;
end
else
if (enable == 1'b1)
begin
up_count <= up_count+ 1;
end
end
endmodul
e
D. SYNCHRONOUS With Reset– DOWNCOUNTER

module syn_dwn_counter (clk ,rst ,enable ,dwn_ count);
input clk ;
input rst ;
input enable ;
output [3:0] dwn_count;
wire clk ;
wire rst ;
wire enable ;
reg [3:0] dwn_count;
always @ (posedge clock)
begin
if (reset == 1'b1)
begin
dwn_count <= 4'b0000;
end
else
if (enable == 1'b1)
begin
dwn_count <= dwn_count- 1;
end
end
endmodul
e
E. SYNCHRONOUS With Clear – UP-DOWN COUNTER
module sync_up_dwn_counter(cnt,clk,up_dwn,clr);
input clk,clr;
input up_dwn;
output [3:0] cnt;
VERILOGLAB 20EC32P
reg [3:0]cnt;

VERILOGLAB 20EC32P
initial cnt = 1'd0;

always @(posedge clk)
begin
case(clr)
1'b1 : cnt = 1'd0;
default : begin
case(up_dwn)
1'b0 : cnt = cnt - 4'b0001;
default : cnt = cnt + 1'b1;
endcase
end
endcase
end
endmodul
e
ASynchronous Counter
F. ASYNCHRONOUS With Reset - UP COUNTER
module counter (clk, clr, enable, asy_up);

input clk, clr, enable;
output [3:0] asy_up;
reg [3:0] tmp;
always @(posedge clk or posedge clr)

begin
if (clr)

VERILOGLAB 20EC32P
tmp = 4'b0000;

VERILOGLAB 20EC32P
else
if (enable)
tmp = tmp + 1'b1;
end
assign asy_up = tmp;
endmodule
G. ASYNCHRONOUS With Reset – DOWNCOUNTER
module counter (clk, clr, enable, asy_dwn);

input clk, clr, enable;
output [3:0] asy_dwn;
reg [3:0] tmp;
always @(posedge clk or posedge clr)

begin
if (clr)
tmp = 4'b0000;
else
if (enable)
tmp = tmp - 1'b1;
end
assign asy_dwn = tmp;
endmodule
H. ASYNCHRONOUS With Clear – UP-DOWN COUNTER
module async_up_dwn_counter (clk,cnt,up_dwn,clr);

input up_dwn,clr,clk;
output [3:0]cnt;
reg [3:0]cnt;
begin
if(clr == 1'b1)
cnt = 4'b0000;
else
begin
case(up_dwn)
1'b0 : begin
if(cnt[1:0] == 2'b10)
cnt[1:0] = 2'b01;
else if(cnt[2:0] == 3'b100)
cnt[2:0] = 3'b011;
else if(cnt[3:0] == 4'b1000)
cnt[3:0] = 4'b0111;
else if(cnt[3:0] == 4'b0000)
cnt[3:0] = 4'b1111;
else
cnt[0] = ~cnt[0];

VERILOGLAB 20EC32P
end
1'b1 : begin
if(cnt[1:0] == 2'b01)
cnt[1:0] = 2'b10;
else if(cnt[2:0] == 3'b011)
cnt[2:0] = 3'b100;
else if(cnt[3:0] == 4'b0111)
cnt[3:0] = 4'b1000;
else if(cnt[3:0] == 4'b1111)
cnt[3:0] = 4'b0000;
else
cnt[0] = ~cnt[0];
end
endcase
end
end
endmodul
e
I. N - SEQUENCE COUNTER
module NseqCounter(clk,reset, q);

input clk;
input reset;
output [3:0] q;
reg [3:0] N;
reg [3:0]temp;
initial
begin
N = 4'b1011; //:. At t = 0, let this module set N = 11
end
begin
if (reset)
temp <= 4'b0001;
else if (temp == N)
temp <= 4'b0001;
else begin
temp[0] <= ~(temp[0]);
if (temp[0]) begin
temp[1]<= ~(temp[1]);
if(temp[1]) begin
temp[2]<=~(temp[2]);
if(temp[2]) begin
temp[3]<=~(temp[3]);
end
end
end
VERILOGLAB 20EC32P
end
end
assign q = temp;
endmodule
Outcomes: Be able to model a memory system with clock Truth table implementation seen
VIVA QUESTIONS
1. What is meant by “Rising-Edge Signal”?
2. In Verilog how it is represented?
3. Differentiate between Casex and Casez?
4. Difference between Encoder with and without priority?
5. Difference between repeat and Forever in Verilog?
6. Difference between Next and Exit?
7. Difference between Syntax and Semantic Errors?
8. What is Port Map?
9. Explain different types of Mapping?
10. Does Verilog or VHDL have built in primitive Gates. Example?
11. What is Three state Output?
12. What is State mission?
13. Difference between Mealy and Moore Circuits?
14. Explain generate?

VERILOGLAB 20EC32P
PART B –INTERFACING
TRAINING BOARD [TK BASE] SPECIFICATION
1. JTAG parallel PC programming interface with cables.

2. XILINX Sparten to FPGA with JTAG accessible flash configuration EPROM.
3. XILINX JTAG programmable CPLD.
4. FPGA /CPLD support up to 208 input and output Pins
5. Every Input/Output pins can be shorted to ground &VCC.
6. Quad S2 Pin devices support for FPGA / CPLD.
7. Multiple power sources of 5V,3.3V,2.5V and 1.8V for daughter boards.
8. Fixed 10MHZ reference clock with clk divider circuit.
9. 4*4 array hex keypad with 2*5 pin.
10. LED array with 8 indicator LED‟S.
11. Interface for 14 Multiplexed 7 sequence displays.
12. Serial port interface on male DB connectors.
13. VGA port interface on female DB connectors.
14. Printer Port interface with centronicx 36 pin female connectors
15. LCD display interface connector.
16. IBM compatible PS2 keyboard and mouse interface
17. Dual Low Pass Filter.
18. 12-bit on board serial ADC with VOR potentiometer.
19. 26 pin general purpose interface for ADC, DAC, STEPPER MOTOR.
20. 10 pin general purpose connector for interface.
21. 10kΩ, 10 turns trim port for LCD &ADC input.
22. Compatible to week with logic analyzer and pattern generator.

VERILOGLAB 20EC32P
PROGRAM 1 – DC MOTOR INTERFACING

AIM: Write HDL code to control speed, direction of DC.
Learning Objective: To study and write the code to control speed, direction of DC Motor.
module dc_motor ( psw, pdcm, clk);

input [2:0] psw;
output pdcm;
input clk;
reg pdcm;
reg [7:0] cnt;
reg [11:0] sclkdiv;
wire clk1;
initial
begin : process_2
sclkdiv = {12{1'b 0}};
end
initial
begin : process_1
cnt = {8{1'b 0}};
end

begin : P1
cnt <= cnt + 1;
end
assign clk1 = cnt[7];

VERILOGLAB 20EC32P
always @(posedge clk1)

begin : P2
if (sclkdiv === 12'b 101011110000)
begin
sclkdiv <= 12'b 000000000000; // af0
end
else
begin
sclkdiv <= sclkdiv + 1;
end
end
always @(posedge clk1)

begin : P3
if (sclkdiv === 12'b 000000000000)
begin
pdcm <= 1'b 1;
// 1f4,320,44c,578,6a4,7d0,8fc,9c4, to vary the speeed of a dc motor
end
else if (psw === 3'b 000 & sclkdiv === 12'b 000111110100 )
begin
pdcm <= 1'b 0;
end
begin
pdcm <= 1'b 0;
end
begin
pdcm <= 1'b 0;
end
begin
pdcm <= 1'b 0;
end
begin
pdcm <= 1'b 0;
end
begin
pdcm <= 1'b 0;
end
begin
pdcm <= 1'b 0;
end
begin
pdcm <= 1'b 0;
end
end
endmodule

VERILOGLAB 20EC32P
User Constraint File (UCF):
NET "clk" LOC = "p79" | IOSTANDARD = LVTTL ;

NET "pdcm" LOC = "p203" | IOSTANDARD = LVTTL ;
NET "psw<0>" LOC = "p21" | IOSTANDARD = LVTTL ;
NET "psw<1>" LOC = "p27" | IOSTANDARD = LVTTL ;
NET "psw<2>" LOC = "p29" ;
Result: The Motor is successfully interfaced and run.
Outcomes: Learnt to interface a DC Motor with FPGA.
VIVA QUESTIONS
1. In CNKEY identify scan & return keys?

2. What is the role ULN2003 in the motherboard kit?
3. What do you mean by logic Analyzer?
4. Mention the configuration of CPLD & FPGA used as daughter boards?
5. What is the supply used for mother board?
6. What is the supply used for daughter board?

VERILOGLAB 20EC32P
PROGRAM 2 –STEPPER MOTOR

AIM: Write HDL code to control speed, direction of Stepper motor.
Learning Objective: To study and write the code to control speed, direction of stepper
Motor
Stepper Motor
module stepper ( dout, clk, reset, dir);
output [3:0] dout;
input clk;
input reset;
input dir;
wire [3:0] dout;
reg [20:0] div;
wire clkdiv;
reg [3:0] shift_reg;

begin : process_1
if (clk === 1'b 1)
begin
div <= div + 1'b 1;
end
end
assign clkdiv = div[16];
always @(negedge reset or posedge clkdiv)
begin : process_2
if (reset === 1'b 0)
begin
shift_reg <= 4'b 0001;
end
else if (clkdiv === 1'b 1 )
begin

VERILOGLAB 20EC32P
if (dir === 1'b 1)

begin
shift_reg <= {shift_reg[0], shift_reg[3:1]};
end
else
begin
shift_reg <= {shift_reg[2:0], shift_reg[3]};
end
end
end
assign dout = shift_reg;
endmodule
NET "clk" LOC = "p79" | IOSTANDARD = LVTTL ;

NET "rest" LOC = "p21" | IOSTANDARD = LVTTL ;
NET "dirl" LOC = "p29" | IOSTANDARD = LVTTL ;
NET "dout<0>" LOC = "p169" | IOSTANDARD = LVTTL ;
Result: The Motor is successfully interfaced and run.
Outcomes: Design, and interface a stepper motor using HDL Also control and reverse
directions of the motor using HDL.
VIVA QUESTIONS
1. Explain the working of stepper motor.

2. In CNKEY identify scan & return keys?
3. What is the role ULN2003 in the motherboard kit?
4. What do you mean by logic Analyzer?
5. Mention the configuration of CPLD & FPGA used as daughter boards?
6. What is the supply used for mother board?
7. What is the supply used for daughter board?

VERILOGLAB 20EC32P
PROGRAM 3 – GENERATION OF DIFFERENT WAVEFORM

AIM: Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)
using DAC - change the frequency.
Learning Objective: To Study and write HDL code to generate different wave forms (sine,
square, triangle, ramp) using DAC change the frequency and amplitude
Sine Wave
module sinewave (clk,rst,dac_out);
input clk;
input rst;
output reg [7:0] dac_out;
reg [7:0] counter [33:0];

reg [15:0] div;
reg flag;
wire clkdiv;
integer i=0;
initial begin
counter[0]= 8'd128; // 128+128sin(theta) * Theta in Degree give as 0,15,30,45,60,75 . .upto
34values
counter[1]= 8'd161;
counter[2]= 8'd192;
counter[3]= 8'd218;
counter[4]= 8'd232;
counter[5]= 8'd244;

VERILOGLAB 20EC32P
counter[6]= 8'd251;
counter[7]= 8'd255;
counter[8]= 8'd255;
counter[9]= 8'd251;
counter[10]= 8'd244;
counter[18]= 8'd94;
counter[19]= 8'd73;
counter[20]= 8'd54;
counter[21]= 8'd37;
counter[22]= 8'd23;
counter[23]= 8'd11;
counter[24]= 8'd4;
counter[25]= 8'd4;
counter[26]= 8'd11;
counter[27]= 8'd23;
counter[28]= 8'd37;
counter[29]= 8'd54;
counter[30]= 8'd73;
counter[31]= 8'd94;
end

begin
if (clk == 1'b1)
begin
div <= div + 1'b 1;
end
end
always @(posedge(clkdiv))
begin
if(i>34)
begin
i=0;
end
dac_out <= counter[i];
i = i + 1;
end
endmodule

VERILOGLAB 20EC32P
//Extra Stuff
Square
module sqwave (clk,rst,dac_out);
input clk;
input rst;
output reg [7:0] dac_out;
//reg [7:0] dac_out;

reg [7:0] counter;
reg [15:0] div;
wire clkdiv;

begin
if (clk == 1'b1)
begin
div <= div + 1'b 1;
end
end
begin
if (rst == 1'b1)
begin
counter <= 8'b 00000000;
end
counter <= counter + 1;
end
always @(counter)
begin
if (counter <= 128)
begin
dac_out <= 8'b 11111111;
end
else
begin
dac_out <= 8'b 00000000;
end
end
endmodule

VERILOGLAB 20EC32P
Triangle
module tri_wave ( clk, rst, dac_out);
input clk;
input rst;
output [7:0] dac_out;
reg [7:0] dac_out;

reg [7:0] counter;
reg [15:0] div;
wire clkdiv;

begin : process_1
if (clk == 1'b 1)
begin
div <= div + 1'b 1;
end
end
begin : process_2
if (rst == 1'b 1)
counter <= 8'b 00000000;
end
if(counter < 128)

dac_out = dac_out + 1;
else
dac_out = dac_out - 1;
end
endmodule
Ramp
Module ramp_wave ( clk, rst, dac_out);
input clk;
input rst;
output [7:0] dac_out;
reg [7:0] dac_out;

reg [7:0] counter;
reg [15:0] div;
wire clkdiv;

begin : process_1
if (clk == 1'b 1)
begin

VERILOGLAB 20EC32P
div <= div + 1'b 1;

end
end
begin : process_2
if (rst == 1'b 1)
begin
counter <= 8'b 00000000;
end

dac_out = dac_out - 1;
end
endmodule
NET "clk" LOC = "p79"

NET "rest" LOC = "p21"
NET "dout<0>" LOC = "p187"
Result: The different waveforms are generated and observed in CRO.
Outcomes: Design, and interface a DAC using HDL be able to generate different waveforms
using DAC on CRO

VERILOGLAB 20EC32P
PROGRAM 4 – ELEVATOR
AIM: Write HDL code to simulate Elevator operation.
Learning Objective: To study write HDL code to simulate elevator operations
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K : in std_logic);
end TKBELE;
architecture behavioral of TKBELE is

signal scurflr,snxtflr,skeyflr : integer range 0 to 15;
signal sdir, skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal sclkdiv : std_logic_vector(15 downto 0);
signal sflrclk,skeyclk : std_logic;
begin

VERILOGLAB 20EC32P
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(skeyscn = "1110" and pkeyret = "1110")
then skeyflr <= 0;
elsif(skeyscn = "1110" and pkeyret = "1101")
then skeyflr <= 1;
then skeyflr <= 2;
then skeyflr<= 3;
then skeyflr <= 4;
then skeyflr <= 5;
then skeyflr <= 6;
then skeyflr <= 7;
then skeyflr <= 8;
then skeyflr <= 9;
then skeyflr <= 10;
then skeyflr <= 11;
then skeyflr <= 12;
then skeyflr <= 13;
then skeyflr <= 14;
then skeyflr <= 15;
end if;

VERILOGLAB 20EC32P
end if;
end process;
-- process clk divider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
skeyclk <= sclkdiv(6);
sflrclk <= sclkdiv(15);
end process;
-- process for key scan clkscan

process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110"then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;
-- process floor motion

process(sflrclk)
begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;
end if;
end if;
end
if;
end process;
-- process display 7seg

process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval : tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000111
",
"1111111","1101111","1110111","1111100","1011000","1011110","1111001","11
10001");
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
end process;
VERILOGLAB 20EC32P
end behavioral;
NET "pclk" LOC = "P79";

NET "pdspseg<0>" LOC = "P196";
NET "pdspseg<1>" LOC = "p197";
NET "flrcal<0>" LOC = "p183";
NET "crnt_flr<0>" LOC = "P189";
Result: The Elevation from one point to another has interfaced by interfacing with evelator
unit in FPGA.
Outcomes: Design, and interface an Elevator using HDL Be able to display different floors
of an elevator in seven segment display.
VIVA QUESTIONS
1. What is structural description?

2. What is switch level description?
3. What is data flow description?
4. What is mixed-language description?
5. What is simulation?
6. What is synthesis?
7. What is wire?
8. What are the differences between VHDL & Verilog?
9. What is mixed-type description?
10. What is procedure?
11. What is function?
12. What is task?
13. What is package?
14.Explain the working of an Elevator.

VERILOGLAB 20EC32P
PROGRAM 5 – ANALOG TO DIGITAL CONVERTER

AIM: Write HDL code to accept Analog signal, Temperature sensor and display the data on
LCD or Seven segment displays..
Learning Objective: To study HDL code to simulate Analog to Digital Converter (ADC)
using temperature sensor.
library IEEE --analog to digital

converter use
IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adc is
Port ( addr : out std_logic_vector(1 downto 0);
chin: in std_logic_vector(1 downto 0);
strt : out std_logic;
EOC : in std_logic;
dout : in std_logic_vector(7 downto 0);
clk1: in std_logic;
oen1: out std_logic;
disp: out std_logic_vector(7 downto 0));
end adc;
architecture Behavioral of adc is

VERILOGLAB 20EC32P
type state is (state1,state2,state3,state4,state5);

VERILOGLAB 20EC32P
--locally used signals declaration

signal current_state, next_state:state;
signal soen1 : std_logic:='1';
signal soen2 : std_logic:='1';
signal clk_count : std_logic_vector(8 downto 0):= (others => '0');
signal clk_dsp : std_logic_vector(1 downto 0);
signal check : std_logic_vector(7 downto 0);
signal address : std_logic_vector(3 downto 0):="0000";
signal temp2 : std_logic_vector(7 downto
0):="00000000"; signal data : std_logic_vector(7 downto 0);
signal clk : std_logic;
begin
addr <= "00" when chin = "00"else
"01" when chin = "01" else
"10" when chin = "10"else
"11";
oen3 <= '0';

oen4 <= '0';
oen5 <= '0';
oen6 <= '0';
p1:process(clk1)
begin
if clk1'event and clk1 = '1' then
clk_count <= clk_count + 1;
clk_dsp <= clk_count(8 downto 7);
clk <= clk_count(6);
end if;
end process p1;
p2:process(clk_dsp)
begin
case clk_dsp is
when "00" => soen2 <= '1';
soen1 <= '0';
when "01" => soen1 <= '1';
soen2 <= '0';
when others => soen1 <= '0';
soen2 <= '0';
end case;
end process p2;
pp:process(clk)
begin
if clk'event and clk = '1' then

current_state <= next_state;

VERILOGLAB 20EC32P
case current_state is
when state1 =>
strt <= '1'; --enabling start/ale
next_state <= state2;
when state2 =>

--start/ale low (pulse width 5 usec)
strt <= '0';
--checking eoc
if EOC = '0' then

end if;
when state3 =>
--start/ale low (pulse width 5 usec)

-- making oe low to read eoc
--checking eoc
-- if dout(7) = '1' then
if EOC = '1' then

end if;
when state4 =>

when state5 => -- jump to start
check <= dout;
end case;
end if;
end process pp;
p4:process(clk1)
type t_mem is array(0 to 15) of std_logic_vector(7 downto 0);
variable mem_data: t_mem:=
("00111111", "00000110", "01011011", "01001111", --0123
"01100110", "01101101", "01111101", "00000111", --4567
"01111111", "01101111", "01110111", "01111100", --89ab
"00111001", "01011110", "01111001", "01110001"); --cdef
variable adv : integer := 0;
begin
adv := conv_integer(address(3 downto 0));
data <= mem_data(adv);
end if ;
end process p4;

VERILOGLAB 20EC32P
oen1 <= soen1;

oen2 <= soen2;
p5: process(clk)
begin
if ( soen2 = '1' ) then
address <= check(3 downto 0);
disp <= data;
else
if (soen1 = '1' ) then
address <= check(7 downto 4);
disp <= data;
end if;
end if;
end if;
end process p5 ;
end behavioral;
NET "addr<0>" LOC = "p171" | IOSTANDARD = LVTTL ;

NET "addr<1>" LOC = "p172" | IOSTANDARD = LVTTL ;
NET "chin<0>" LOC = "p29" | IOSTANDARD = LVTTL ;

NET "chin<1>" LOC = "p27" | IOSTANDARD = LVTTL ;
NET "clk1" LOC = "p79" | IOSTANDARD = LVTTL ;
NET "disp<0>" LOC = "p10" | IOSTANDARD = LVTTL ;


NET "dout<7>" LOC = "p187" | IOSTANDARD = LVTTL
;
NET "EOC" LOC = "p183" | IOSTANDARD = LVTTL ;

VERILOGLAB 20EC32P
NET "oen1" LOC = "p2" | IOSTANDARD = LVTTL ;

NET "strt" LOC = "p184" | IOSTANDARD = LVTTL ;
Result: The analog to digital conversion is observed and the values are displayed in segment.
Outcomes: Design, and interface of ADC using VHDL and display the measured values in
seven segment display.
VIVA QUESTIONS
1. What is ADC ?
2. How many types of ADC ?
3. Difference between ADC and DAC ?
4. A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the
analog output for the input code 0101.
5. What is the resolution of a digital-to-analog converter (DAC)?
6. The practical use of binary-weighted digital-to-analog converters is limited to..
7. Which is not an analog-to-digital (ADC) conversion error?

VERILOGLAB 20EC32P
Overall VIVA Questions

1. What type of language is VHDL?
2. What do all VHDL designs begin with?
3. Which block describes a design's interface and behavior?
4. What is the difference between simulation and synthesis?
5. Which data type defines a single logic signal and bus?
6. What two ways can a vector's range be described?
7. What are the IEEE STD_LOGIC_1164 data types for single logic signals and buses?
8. What are the only two values for a Boolean type?
9. What are the numerical data types?
10. What is SUBTYPING used for?
11. What type is use to create a user data type?
12. Create the use data type DAYS and assign it the values: MON, TUE, WED, THU, FRI,
SAT and SUN.
13. Which data type is used for a string of ASCII characters?
14. Which data type includes time units as values?
15. Create the entity block for a three input XOR gate.
16. Which symbol is used to end all VHDL statements?
17. What part of a port declaration defines signals in or out direction?
18. Which VHDL construct is used to define a literal constant in an entity block?
19. Create the integer constant included in an entity block called BUS_SIZE and assign it a
value of 32.
20. Which symbols are used as an assignment operator to assign a literal to an identifier
name?
21. What are the two primary ways to describe a logic circuits function within an
architecture block?
22. Create the architecture block for the 3-input XOR gate of question 21.
23. Which symbols are used to assign an expression's result to an output Interface signal?
24. What are the rules used to define an identifier name?
25. Write the statements that will allow a design to access all the contents of the IEEE
ARITH.
26. How does a transport delay differ from an inertial delay?
27. What is the purpose of a SIGNAL declaration?
28. Where are SIGNAL declarations placed in the design?
29. Write an assignment statement that assigns the contents of s(5) to t(2).
30. What is the purpose of a process' sensitivity
list? 31 Under what conditions is a process run?
32 What is an EVENT? What is the difference between event and non-event driven process
execution?
33. Which symbols are used to differentiate between logic 1 & an integer1?
34. What are the results of using CLK' event as a condition in the if statement of the DEF
example?
35. In an if..then..else construct, which statements are executed if the condition is TRUE and
which if it is FALSE?
36. Which reserved word is used to nest if..then..else statements?
37. Write the process block that separately tallies positive and negative transitions of the
signal TIME_OUT.
38. What are the requirements of a for loop?
39. Write a process block that uses a for loop to set a zero flag high if all the bits in a sixteen

VERILOGLAB 20EC32P
(16) bit word are low (zero).

VERILOGLAB 20EC32P
40. What is meant by instantiating a component?

41. How do signal declarations differ from port interface declarations?
42. What is the prime use of signals?
43. How many parameters can be passed into a function?
44. How many results can be returned from a function?
45. Write a function that returns the sum of two 8-bit words.
46. How do procedures differ from functions?
47. Which standard library does not require a library or use statement?
49. What is a PACKAGE?
50. What is the name of the library used by the current design to store compiled results?

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Department of Electronics and Communication Engineering

(ACADEMIC YEAR 2021-22)

SUBJECT: HDL LABORATORY

E&CE DEPT,HKES POLYTECHNIC-CAMP-RAICHUR

1 Write a Verilog program for the following combinational designs

Department of ECE, Page 2

12 Down sampled signals by connecting them to an oscilloscope.

Department of ECE, Page 3

An HDL is a programming language used to describe electronic circuit essentially digital

VHDL (VHSIC Hardware Description Language) is a hardware description language

Difference between Verilog and VHDL

1. VHDL is based on Pascal and ADA while Verilog is based on C language.

FPGA DESIGN FLOW

Dept. of ECE, Page 1

Figure: FPGA Design Flow

4. Design Verification – is very important step in design process. Verification is

There are two types of simulation:

ABOUT XILINX ISE SOTWARE

Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx

STEPS TO EXECUTE A PROGRAM

1) Starting the ISE software

2) Creating a New Project in ISE

3) Fill in the properties in the table as shown below

Dept. of ECE, Page 3

HDL Synthesis Tool: XST(VHDL/VERILOG)

4) Creating an HDL Source

b) Type in the file name for ex: and_gate

c) Verify that the Add to project checkbox is selected.

5) Click next in the Define Verilog Source dialog box.

7) Click Finish in the New Project Information dialog box.

Dept. of ECE, Page 4

17) <file_name>.tb file is added to the project.

18) In source window change implementation to behavioral simulation.

Dept. of ECE, Page 5

25) Close PACE

Generating a Program File

Dept. of ECE, Page 6

2. Double click on the Configure device IMPACT

Dept. of ECE, Page 7

BASIC PROGRAM – ALL LOGIC GATES

Logic Gates and Truth Table:

Dept. of ECE, Page 8

Dept. of ECE, Page 9

module not_gate (a,c);

module nand_gate (a,b,c);

module xnor_gate (a,b,c);

Dept. of ECE, Page 10

module gates(a_in, b_in, not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op);

Dept. of ECE, Page 11

assign not_op= ~a_in;

Dept. of ECE, Page 12

37. What is simulation?

Dept. of ECE, Page 13

PROGRAM 1 – COMBINATIONAL CIRCUITS

Dept. of ECE, Page 14

module 2to4dec( input [1:0] d_in, output [3:0] d_op);

ii a). 8:3 Encoder [Without Priority]

module encoder8_3(en, a_in, y_op);

Dept. of ECE, Page 16