UNIT 1

21EC914 Low Power VLSI Design

Dr. D. RUKMANI DEVI
Professor
RMDEC
Principles of Low Power VLSI Design

❖ Using the lowest possible supply voltage

❖ Using the smallest geometry, highest frequency devices but operating them at a lowest possible
frequency
❖ Using parallelism and pipelining to lower required frequency of operation
❖ Power management by disconnecting the power source when the system are idle
❖ Designing systems to have lowest requirements on subsystems performance for the given user level
functionality.

Hierarchy of Limits

1. Fundamental
2. Material
3. Device
4. Circuit
5. Systems

Two types of limit at each level

1. theoretical consideration
2. Practical consideration
Fundamental Limits
➢ independent of devices, materials, and circuits
➢ derived from the basic principles of thermodynamics, quantum mechanics, and electromagnetics

The limit from thermodynamic principles results from the need to have, at any node with an equivalent resistor
R to the ground, the signal power P, exceed the available noise power Pavail

Ps = Pavail = ( en-2 /4 R) = ( 4kTRB/4R) =  kTB

where ' >= 1 is some constant factor
en-2 is open-circuit mean-square voltage
B is the bandwidth of the node It is states that it is impossible to determine simualtaneouly,the
Then at T= 300 K, P, must be larger than 0.104 eV. exact position and exact momentum(or velocity) of an electron
The quantum theoretic limit on low power comes from the Heisenberg uncertainty principle.
In order to be able to measure the effect of a switching transition of duration Δt ,
It must involve an energy greater than h / Δt
Where h is the Planck's constant
P  h/ (Δt)2
The fundamental limit Based on electromagnetic theory results in the velocity of propagation of a high-speed pulse
on an interconnect to be always less than the speed of light in free space co
L/  co

Where LIs the length of the interconnect and  Is the interconnect transit time.
Material limits
Material limits are independent of the particular devices built with the materials and, in turn, the
particular circuits composed from those devices.
The attributes of a semiconductor material are
(1) carrier mobility
(2) carrier saturation velocity
(3) self-ionizing electric field strength and
(4) thermal conductivity
Semiconductor material limits that are independent of the structures and the geometry of devices can be
calculated by considering a cube of the undoped material of dimension Δx that is imbedded in a three-
dimensional matrix of similar cubes.
❖ The voltage difference Vo across a pair of its opposite faces is just as large as necessary to produce an electric
field equal to the self-ionizing electric field strength

❖ The limit on switching energy and the switching time can then be calculated as the amount of electrostatic
energy stored in the cube and the transit time of a carrier through the cube:
The second material level limit arises from heat removal considerations. To derive this
limit, an isolated generic device that resides in an ideal heat sink maintained at temperature
To is considered.
The device is hemispherical in shape with a radius of rs = s td

The power or the rate of transfer of the heat energy from the device to the heat sink is then given by

❖ An interesting use of the above limit is to compare suitability of GaAs and Si for low-power applications
❖ Using representative values, P/td comes out to be 0.21 nS/W for Si and 0.69 ns/W for GaAs
❖ The interconnect material limit again arises from speed-of-light considerations. The propagation time through
an interconnect of length L of a material with a relative dielectric constant r must satisfy
Device Limits

The device limits are independent of the circuits that may have been composed with the devices.
As the MOSFET device is used significantly more than any other,
❖ short-channel effects in bulk MOSFETs can be controlled by using channels with lower impurity
concentration and abrupt retrograde doping profiles.

❖ MOSFET device leakage current and its overall reliability are affected by factors other than the threshold
voltage shift, for example, bulk punch through, gate-induced drain barrier lowering, and impact ionization.

❖ At the device level, a global interconnect can be modelled as a canonical distributed resistance-capacitance network.
When such a network is driven by an ideal voltage source that applies a unit step function, the 0 -
90% response time of the network is given by

 = RC = (/H ) ( /H) L2

The above expression specifies a limit on the minimum response time of an interconnect given its length.
 Circuit Limits
The circuit level limits are independent of the architecture of a particular system. There are
four principal circuit level limits

To be able to distinguish between the"zero"and"one” logic level switch very nearly zero error is the most basic requirement
of a digital logic gate.

For a static CMOS logic gate this means that at the transition point of the static transfer characteristics of the gate(i.e.,where
output voltage is equal to the input voltage),the incremental voltage gain av must exceed unity in absolute value. A CMOS
inverter can only satisfy this requirement if its supply voltage is larger than a minimum limit Vdd,min

In practice, a value of Vdd = 0.1V cannot be used because the threshold voltage would need to be so small that the drain
leakage current in the off state of the MOSFET would be unacceptably large.

In considering logic and memory circuit behavior, Vdd =1.0V appears to be a good compromise for small dynamic and static
power dissipation.
 The second generic circuit limit for CMOS technology is the switching energy per transition
Where Cro is taken as the total load capacitance of a ring oscillator stage, including output
diffusion capacitance, wiring capacitance, and input gate capacitance for an inverter that
occupies a substrate area of 100F 2 (F= Minimum feature size=0.1um).

The third generic circuit limit is on the intrinsic gate delay and is given by the time taken to
charge/discharge the load capacitance Cro

Hence

The fourth generic circuit limit considers a global (i.e., extending from one corner of the chip to the other)
interconnect represented as a distributed resistance-capacitance network. The response time of this interconnect
circuit

Where Rtr is the output resistance of the driving transistor and Rint and Cint are the total resistance and
capacitance, respectively, of the global interconnect. The circuit should be designed so that Rint < 2.3 Rtf
To ensure the delay due to wiring resistance is not excessive
System Limits
System limits depend on all the other limits and are the most restrictive ones in the hierarchy
There are five generic system limits that are given rise to by
(1) the architecture of the chip,
(2) the power-delay product of the CMOS technology used to implement the chip,
(3) the heat removal capacity of the chip package,
(4) the clock frequency, and
(5) its physical size.

The system switching energy limit is defined by a composite gate that characterizes the critical path with in a macrocell. The
critical path is assumed to pass through ncp

Random logic gates and a total interconnect length corresponding to the corner-to-corner Manhattan distance 2L.

The system heat removal limit is defined by the requirement that the average power dissipation of a composite gate P
Must be less than the cooling capacity of the packaging.
Practical Limits

The basis for practical limits is the opinion that beyond a certain point in
❖ scaling,
❖ the cost of designing,
❖ manufacturing, testing, and
❖ packaging will cause the cost per function to level off and begin to increase.

To facilitate further analysis, the number of transistors per chip N can be expressed as N = F -2D2 PE
The optimistic predictions for the minimum feature size F are to reach 0.0625um by the second decade of the
millennium, for the chip area D to reach over (50mm)2,and for the packing efficiency PE to reach one transistor per
minimum feature area.
This would make 100 billion transistor chips economically viable in addition to being technically possible
Quasi-Adiabatic Microelectronics

➢ In any thermodynamic system that proceeds from one equilibrium process to another, the entropy of a closed system
either remains unchanged or increases.
➢ During an adiabatic process no loss or gain of heat occurs-consequently the prospect of inventing quasi-
adiabatic computational technology and reducing the power dissipation to levels beyond the limits of
non adiabatic computation.
➢ Unlike the unchanging materials and device structures, the circuit configurations used for quasi-adiabatic
operations must change significantly. Without identifying specific circuit configurations and system architectures,
the respective limits cannot be analyzed
Basic Principle of Low Power Design.
Reduce Switching Voltage
The P = CV2f equation consists of three terms:
➢ voltage, capacitance and frequency.
➢ Due to the quadratic effect of the voltage term, reducing the switching voltage can achieve
dramatic savings.
➢ to reduce the operating voltage of the CMOS circuit.
➢ to reduce voltage swing by using well-known circuit techniques such as charge sharing,
transistor threshold voltage, etc. There are many trade-offs to be considered in voltage
reduction.
➢ Performance is lost because MOS transistors become slower at lower operating voltages
➢ The main reason is that the threshold voltages of the transistors do not scale accordingly
with the operating voltage to avoid excessive leakage current.
➢ Noise immunity is also a concern at low voltage swing.
➢ Special level converters are required to interface low swing signals to the full-swing ones.
Basic Principle of Low Power Design.
Reduce Capacitance
➢ Reducing parasitic capacitance in digital design has always been a good way to improve
performance as well as power. However, a blind reduction of capacitance may not achieve
the desired result in power dissipation.
➢ The real goal is to reduce the product of capacitance and its switching frequency.
➢ Signals with high switching frequency should be routed with minimum parasitic
capacitance to conserve power.
➢ Conversely, nodes with large parasitic capacitance should not be allowed to switch at high
frequency.
➢ Capacitance reduction can be achieved at most design abstraction levels: material, process
technology, physical design (floorplanning, placement and routing), circuit techniques,
transistor sizing, logic restructuring, architecture transformation and alternative
computation algorithms.
Basic Principle of Low Power Design.

Reduce Switching Frequency

➢ The techniques for reducing switching frequency have the same effect as reducing
capacitance. Again, frequency reduction is best applied to signals with large capacitance.
➢ The techniques are often applied to logic level design and above. Those applied at a higher
abstraction level generally have greater impact.
➢ Reduction of switching frequency also has the side effect of improving the reliability of a chip
as some failure mechanism is related to the switching frequency.
➢ One effective method of reducing switching frequency is to eliminate logic switching that is
not necessary for computation. Other methods involve alternate logic implementation since
there are many ways to design a logic network to perform an identical function.
➢ The use of different coding methods, number representation systems, counting sequences
and data representations can directly alter the switching frequency of a design.
Basic Principle of Low Power Design.
Reduce Leakage and Static Current Leakage current,
➢ Reverse biased junction or subthreshold current, is generally not very useful in digital design.
➢ Designers often have very little control over the leakage current of the digital circuit.
Fortunately, the leakage power dissipation of a CMOS digital circuit is several orders of
magnitude smaller than the dynamic power.
➢ The leakage power problem mainly appears in very low frequency circuits or ones with "sleep
modes" where dynamic activities are suppressed.
➢ Most leakage reduction techniques are applied at low-level design abstraction such as
process, device and circuit design. Memory chips that have very high device density are most
susceptible to high leakage power.
➢ Static current can be reduced by transistor sizing, layout techniques and careful circuit
design.
➢ Circuit modules that consume static current should be turned off if not used.
➢ Sometimes, static current depends on the logic state of its output, and we can consider
reversing the signal polarity to minimize the probability of static current flow.