AZ1045-04F

Ultra Low Capacitance ESD Protection Array

For High Speed I/O Port

Features
Consumer Electronics

ESD Protect for Transition Minimized Differential
Set Top Box
Signaling (TMDS) channels
DVDRW Players

Protects four I/O lines
Graphics Cards

Provide ESD protection for each line to

IEC 61000-4-2 (ESD) ±15kV (air), ±10kV (contact) Description
IEC 61000-4-5 (Lightning) 3.5A (8/20µs) AZ1045-04F is a design which includes ESD

For operating voltage of 5V and below rated diode arrays to protect high speed data

Ultra low capacitance : 0.5pF typical interfaces. The AZ1045-04F has been

Fast turn-on and Low clamping voltage specifically designed to protect sensitive

Array of ESD rated diodes with internal components which are connected to data and
equivalent TVS (Transient Voltage transmission lines from over-voltage caused by
Suppression) diode Electrostatic Discharging (ESD).

Simplified layout for HDMI connectors AZ1045-04F is a unique design which includes

Solid-state silicon-avalanche and active circuit ESD rated, ultra low capacitance steering diodes
triggering technology and a unique design of clamping cell which is an

Green part equivalent TVS diode in a single package. During
transient conditions, the steering diodes direct
Applications the transient to either the internal ESD line or to

High Definition Multi-Media Interface (HDMI) ground line. The internal unique design of
1.3 & 1.4 version clamping cell prevents over-voltage on the

DisplayPort interface internal ESD line and on the I/O line, which is

SATA and eSATA interface protecting any downstream components.

USB3.0 AZ1045-04F may be used to meet the ESD

Digital Visual Interface (DVI) immunity requirements of IEC 61000-4-2, Level 4

USB2.0 up to 480Mb/s (±15kV air, ±8kV contact discharge).

IEEE 1394 up to 3.2 Gb/s

Ethernet port: 10/100/1000 Mb/s

Desktop and Notebooks PCs

Circuit Diagram Pin Configuration

Line-1 1 10 NC

Line-2 2 9 NC

GND 3 8 GND

1 2 4 5
Line-3 4 7 NC
3,8 Line-4 5 6 NC

DFN2510P10E (Top View)

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNITS
Peak Pulse Current (tp =8/20µs) IPP 3.5 A
Peak Pulse Power (tp =8/20µs) PPP 30 W
Operating Voltage (I/O pin-GND) VDC (GND – 0.5) to 6 V
ESD per IEC 61000-4-2 (Air) 15
VESD kV
ESD per IEC 61000-4-2 (Contact) 10
o
Lead Soldering Temperature TSOL 260 (10 sec.) C
o
Operating Temperature TOP -55 to +85 C
o
Storage Temperature TSTO -55 to +150 C

ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Reverse Stand-Off
VRWM Pin-1,-2,-4,-5 to pin-3,-8, T=25 oC 5 V
Voltage
Channel Leakage
ICH-Leak VPin-1,-2,-4,-5 = 5V, VPin-3,-8 = 0V, T=25 oC 1.5 µA
Current
Reverse Breakdown IBV = 1mA, T=25 oC, Pin-1,-2,-4,-5 to
VBV 6 V
Voltage pin-3,-8
IF = 15mA, T=25 oC, pin-3,-8 to
Forward Voltage VF 0.9 1.1 V
pin-1,-2,-4,-5
ESD Clamping IEC 61000-4-2 +6kV,T=25 oC,
Vclamp 12 V
Voltage Contact mode, any I/O pin to Ground
ESD Dynamic IEC 61000-4-2, 0~+6kV,T=25 oC,
Rdynamic 0.3 Ω
Turn-on Resistance Contact mode, any I/O pin to Ground
Channel Input Vpin-3,-8 = 0V,VIN = 2.5V,f = 1MHz,T=25
CIN o
0.5 0.65 pF
Capacitance C, any I/O pin to Ground
Channel to Channel Vpin-3,-8 = 0V, VIN = 2.5V, f = 1MHz,
CCROSS 0.04 0.08 pF
Input Capacitance T=25 oC , between I/O pins

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

Typical Characteristics
Typical Variation of CIN vs. VIN Typical Variation of CIO-to-IO vs. VIN
1.0 0.10
0.9 0.09
0.8 0.08
Input Capacitance (pF)

Input Capacitance (pF)

0.7 o 0.07 f = 1MHz, T=25 oC,
f = 1MHz, T=25 C,
0.6 0.06
0.5 0.05
0.4 0.04
0.3 0.03
0.2 0.02
0.1 0.01
0.0 0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Input Voltage (V) Input Voltage (V)

insertion Loss S21 (I/O-to-GND) Analog Cross Talk

20
0
10
-3
0
Analog Cross Talk (dB)

-6
Insertion Loss (dB)

-9 -10

-12 -20

-15 -30

-18 -40
-21 -50
-24 -60
3GHz: -0.92dB
-27 4.3GHz: -3dB -70
-30 -80
1e+8 1e+9 1e+8 1e+9
Frequency (Hz) Frequency (Hz)

Transmission Line Pulsing (TLP) Measurement

Transmission Line Pulsing (TLP) Current (A)

18

16

14
V_pulse

12 Pulse from a
transmission line

TLP_I
10 100ns +

TLP_V DUT

8 -

4
I/O to GND
2

0
0 2 4 6 8 10 12 14
Transmission Line Pulsing (TLP) Voltage (V)

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

Applications Information

A. Device Connection

The AZ1045-04F is designed to protect four These pins should be directly connected to the
data lines from transient over-voltage (such as GND rail of PCB (Printed Circuit Board). To get
ESD stress pulse). The device connection of minimum parasitic inductance, the path length
AZ1045-04F is shown in the Fig. 1. In Fig. 1, the should keep as short as possible.
four protected data lines are connected to the AZ1045-04F can provide ESD protection for
ESD protection pins (pin1, pin2, pin4, and pin5) 4 I/O signal lines simultaneously. If the number of
of AZ1045-04F. The ground pins (pin3 and pin8) I/O signal lines is less than 4, the unused I/O pins
of AZ1045-04F are the negative reference pins. can be simply left as NC pins.

I/O 1 data line I/O 1

To To
I/O-port data line Protected
Connector IC
I/O 2 I/O 2
Line-1
1 10 NC
Line-2
2 9 NC
AZ1045-04F

GND GND
3 8

Line-3
4 7 NC
Line-4
5 6 NC
I/O 3 I/O 3
To To
data line Protected
I/O-port
Connector IC
I/O 4 data line I/O 4

Fig. 1 Data lines connection of AZ1045-04F.

B. Application ESD protection devices have an inherent

junction capacitance. Even a small amount of
AZ1045-04F is designed for protecting high added capacitance on a HDMI port will cause the
speed I/O ports from over-voltage caused by impedance of the differential pair to drop. Thus,
Electrostatic Discharging (ESD). Thus, a lot of some form of compensation to the layout will be
kinds of high speed I/O ports can be the required to bring the differential pairs back within
applications of AZ1045-04F, especially, the HDMI the required 100 Ohm +/- 15% range. The higher
port. the added capacitance, the more extreme the
HDMI Protection for High and Low speed modifications will need to be. If the added
signals capacitance is too high, compensation may not
The HDMI Compliance Test Specification even be possible. The AZ1045-04F presents
(CTS) requires sink (receiver) ports maintain a 0.5pF capacitance to each differential signal
differential impedance of 100 Ohms +/- 15%. while being rated to handle >8kV ESD contact

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

discharges (>15kV air discharge) as outlined in pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6). For
IEC 61000-4-2. Therefore, it is possible to make example, line 1 enters at pin 1 and exits at Pin 10
none adjustment to the board layout parameters and the PCB trace connects pin 1 and 10
to compensate for the added capacitance of the together. Lines 2, 3, and 4 have the same way of
AZ1045-04F. Figure 2 shows how to implement connection. The ground pins (pin3 and pin8) of
the AZ1045-04F in a HDMI application. AZ1045-04F are the negative reference pins.
The AZ1045-04F is designed for allowing the These pins should be directly connected to the
traces to run straight through the device to GND plane of PCB. To get minimum parasitic
simplify the PCB layout. As shown in Figure 2, inductance, the path length should keep as short
the best way to design the PCB trace is using the as possible. In Figure 2, the none-TMDS
flow through layout. The solid line represents the signals, DDC_CLK, DDC_DAT, CE_REMOTE,
PCB trace. Note that the PCB traces are used to and HOTPLUG_DET, can be protected with
connect the pin pairs for each line (pin 1 to pin 10, another low cost part, e.g., AZC199-04S.
TMDS_D2+
TMDS_D2+ Line -1 1 10 NC
TMDS_D2-
Line -2 2 9 NC
AZ1045-04F
TMDS_GND

TMDS_D2- GND 3 8 GND

TMDS_D1+ Line -3 4 7 NC
TMDS_D1+
TMDS_GND Line -4 5 6 NC
TMDS_D1-
TMDS_D1-
TMDS_D0+
TMDS_D0+ Line-1 1 10 NC
TMDS_D0-
Line-2 2 9 NC
AZ1045-04F

TMDS_GND

TMDS_D0- GND 3 8 GND

TMDS_CK+ Line-3 4 7 NC TMDS_CK+

TMDS_GND Line-4 5 6 NC
TMDS_CK-

TMDS_CK-

CE_REMOTE
CE_REMOTE
Via hole to GND
N/C
GND DDC_CLK
3 2 1
DDC_CLK
AZC199-04S
DDC_DAT
4 5 6
GND +5V DDC_DAT
Via hole to +5V
+5V OUT
Via hole to GND
C=100nF
HOTPLUG_DET
HOTPLUG_DET (optional)

HDMI
Connector

Fig. 2 HDMI Protection for High and Low speed signals.

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

C. Measurement Results on a HDMI port degradation of the differential impedance

Fig. 3a and 3b show the test boards for induced by the parasitic effects of AZ1045-04F is
measuring the differential impedance of a HDMI at the range of 12.8Ω to 14.2Ω. This
port without using ESD protection array, and with demonstrates when the PCB differential
using AZ1045-04F ESD protection array, impedance is designed at around 105Ω, then
respectively. none adjustment to the board layout parameters
is needed to compensate for the added ultra
Fig. 4 shows the differential impedance small capacitance of the AZ1045-04F and the
measurement results. The range of the test results can pass the spec of 100Ω +/- 15%.
differential impedance without ESD protection
array on it is from 96Ω to 106Ω, which meets the Fig. 5 shows the HDMI Eye Diagram
spec of 100 Ohms +/- 15%. And the range of the performance when the AZ1045-04F is under
differential impedance with AZ1045-04F ESD used. No apparent affection is shown due to the
protection array on it is from 88.9Ω to 104Ω, low capacitance feature of the AZ1045-04F.
which still meets the spec of 100 Ohms +/- 15%.
From the measured results shown in Fig. 4, the

Fig. 3a The test board for measuring the Fig. 3b The test board for measuring the
differential impedance of a HDMI port without differential impedance of a HDMI port with using
using ESD protection array. ESD protection array, AZ1045-04F.

Fig. 4a The measured differential impedance of Fig. 4b The measured differential impedance of
Data0- and Data0+ (103.3Ω without ESD Data1- and Data1+ (102.7Ω without ESD
protection array, and 89.1Ω with AZ1045-04F). protection array, and 89.1Ω with AZ1045-04F).

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

Fig. 4c The measured differential impedance of Fig. 4d The measured differential impedance of
Data2- and Data2+ (104.2Ω without ESD Clock- and Clock+ (101.7Ω without ESD
protection array, and 90.8Ω with AZ1045-04F). protection array, and 88.9Ω with AZ1045-04F).

Fig. 5 the HDMI Eye Diagram performance when the AZ1045-04F is under used. No apparent affection
is shown due to the low capacitance feature of the AZ1045-04F.

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

PACKAGE OUTLINE
(DFN2510P10E)

TOP VIEW (unit in mm)

BOTTOM VIEW (unit in mm)

SIDE VIEW (unit in mm)

Millimeters Inches
Symbol
min max min max
A 0.40 0.55 0.016 0.022
A1 0.00 0.05 0.000 0.002
A3 0.152REF. 0.006 BSC
D 2.45 2.55 0.096 0.100
E 0.95 1.05 0.037 0.041
D1 0.35 0.45 0.014 0.018
E1 0.35 0.45 0.014 0.018
b 0.15 0.25 0.006 0.010
e 0.5 BSC 0.019 BSC
L1 0.075 REF 0.0029 REF
L2 0.05 REF 0.0019 REF
b2 0.20 0.30 0.0079 0.012
L 0.35 0.45 0.014 0.018

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

LAND LAYOUT
D D1

Dimensions
Index Millimeter Inches
A B F
A 0.875 0.034
B 0.20 0.008
E C 0.50 0.02
C1 1.00 0.039
C
D 0.25 0.01
C1 D1 0.4 0.016
E 0.675 0.027
Notes: F 1.55 0.061
This LAND LAYOUT is for reference
purposes only. Please consult your
manufacturing partners to ensure your
company’s PCB design guidelines are met.

MARKING CODE

Part Number Marking Code

117XY
AZ1045-04F
117XY
(Green part)
117 = Device Code
Note. Green means Pb-free, RoHS, and
X = Date Code
Y= Control Code Halogen free compliant.

Ordering Information

PN# Material Type Reel size MOQ/interal box MOQ/carton

AZ1045-04F.R7G Green T/R 7 inch 4 reel= 12,000/box 6 box =72,000/carton

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 AZ1045-04F
Ultra Low Capacitance ESD Protection Array
For High Speed I/O Port

Revision History

Revision Modification Description

Revision 2008/12/09 Preliminary Release.
Revision 2009/01/16 The Initial Formal Release.
Revision 2009/05/15 Correct the typos at Package Outline.
Revision 2009/06/10 1. Correct the typos at the ABSOLUTE MAXIMUM RATINGS.
2. Update the information of the measurement results on a HDMI port.
Revision 2009/09/08 1. Update the bottom view indication of the Package Outline.
2. Update the “D” value of Land Layout.
Revision 2009/11/25 Increase the Lightning (8/20µs) spec.
Revision 2009/12/26 Update the PACKAGE DIMENSIONS.
Revision 2011/05/05 1. Update the Company Logo.
2. Add the Ordering Information.
Revision 2011/07/16 Add the Applications of USB3.0 and HDMI 1.4 version.
Modify the Bottom View of Package Outline to add three parameters,
Revision 2012/02/09
b2, L1, and L2.
Revision 2012/03/23 Add Fig. 5 of HDMI Eye Diagram.
Revision 2012/06/05 Update the diagram of the Pin Configuration on page 1.
Revision 2013/03/08 Update the “A” value of Package Outline.

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