INTERRUPTS

❑ An interrupt is an external or internal event that

interrupts the microcontroller to inform it that a device
needs its service
❑ A single microcontroller can serve several devices by
two ways
➢ Interrupts
▪ Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal
▪ Upon receiving an interrupt signal, the microcontroller
interrupts whatever it is doing and serves the device
▪ The program which is associated with the interrupt is called
the interrupt service routine (ISR) or interrupt handler

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Dr. K. Ghosh
INTERRUPTS

❑ Polling
▪ The microcontroller continuously monitors the status of a given
device
▪ When the conditions met, it performs the service
▪ After that, it moves on to monitor the next device until every
one is serviced
❑ Polling can monitor the status of several devices and
serve each of them as certain conditions are met
➢ The polling method is not efficient, since it wastes much of the
microcontroller’s time by polling devices that do not need service
➢ ex. JNB TF,target

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Dr. K. Ghosh
INTERRUPTS

❑ The advantage of interrupts is that the microcontroller

can serve many devices (not all at the same time)
➢ Each devices can get the attention of the microcontroller based
on the assigned priority
➢ For the polling method, it is not possible to assign priority since it
checks all devices in a round-robin fashion

❑ The microcontroller can also ignore (mask) a device

request for service
➢ This is not possible for the polling method

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Dr. K. Ghosh
ISR

❑ For every interrupt, there must be an interrupt

service routine (ISR), or interrupt handler
➢ When an interrupt is invoked, the micro- controller
runs the interrupt service routine
➢ For every interrupt, there is a fixed location in
memory that holds the address of its ISR
➢ The group of memory locations set aside to hold the
addresses of ISRs is called interrupt vector table

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Dr. K. Ghosh
STEPS

❑ Upon activation of an interrupt, the microcontroller

goes through the following steps
1. It finishes the instruction it is executing and saves the
address of the next instruction (PC) on the stack
2. It also saves the current status of all the interrupts internally
(i.e: not on the stack)
3. It jumps to a fixed location in memory, called the interrupt
vector table, that holds the address of the ISR

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Dr. K. Ghosh
CONTD…

4. The microcontroller gets the address of the ISR from

the interrupt vector table and jumps to it
▪ It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine which is RETI
(return from interrupt)
5. Upon executing the RETI instruction, the
microcontroller returns to the place where it was
interrupted
▪ First, it gets the program counter (PC) address from the
stack by popping the top two bytes of the stack into the PC
▪ Then it starts to execute from that address

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Dr. K. Ghosh
 ❑ Six interrupts are allocated as follows
➢ Reset – power-up reset
➢ Two interrupts are set aside for the timers: one for timer
0 and one for timer 1
➢ Two interrupts are set aside for hardware external
interrupts
▪ P3.2 and P3.3 are for the external hardware interrupts INT0
(or EX1), and INT1 (or EX2)
➢ Serial communication has a single interrupt that
belongs to both receive and transfer

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Dr. K. Ghosh
 ❑ Upon reset, all interrupts are disabled (masked), meaning
that none will be responded to by the microcontroller if
they are activated
❑ The interrupts must be enabled by software in order for
the microcontroller to respond to them
➢ There is a register called IE (interrupt enable) that is responsible for
enabling (unmasking) and disabling (masking) the interrupts
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Dr. K. Ghosh
INTERRUPT REGISTER

EA IE.7 Disables all interrupts. If EA = 0, no interrupt is acknowledged.

If EA = 1, each interrupt source is individually enabled or disabled
by setting or clearing its enable bit.

-- IE.6 Not implemented, reserved for future use.*

ET2 IE.5 Enables or disables Timer 2 overflow or capture interrupt (8052 only).
ES IE.4 Enables or disables the serial port interrupt.
ET1 IE.3 Enables or disables Timer 1 overflow interrupt.
EX1 IE.2 Enables or disables external interrupt 1.
ET0 IE.1 Enables or disables Timer 0 overflow interrupt.
EX0 IE.0 Enables or disables external interrupt 0.
*User software should not write 1s to reserved bits. These bits may be used
in future flash microcontrollers to invoke new features.

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Dr. K. Ghosh
 ❑ To enable an interrupt, we take the following steps:
1. Bit D7 of the IE register (EA) must be set to high to allow the
rest of register to take effect
2. The value of EA
➢ If EA = 1, interrupts are enabled and will be responded to
if their corresponding bits in IE are high
➢ If EA = 0, no interrupt will be responded to, even if the
associated bit in the IE register is high

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Dr. K. Ghosh
Show the instructions to (a) enable the serial interrupt, Timer 0 interrupt, and
external hardware interrupt 1 (EX1), and (b) disable (mask) the Timer 0 interrupt,
then (c) show how to disable all the interrupts with a single instruction.

(a)MOV IE,#10010110B ;enable serial, Timer 0, EX1

Since IE is a bit-addressable register, we can use the
following instructions to access individual bits of the
register.
(b)CLR IE.1 ;mask(disable) Timer 0 interrupt only
(c)CLR IE.7 ;disable all interrupts
Another way to perform the “MOV IE,#10010110B”
instruction is by using single-bit instructions as shown
below.
SETBIE.7 ;EA=1, Global enable
SETB IE.4 ;enable serial interrupt
SETB IE.1 ;enable Timer 0 interrupt
SETB IE.2 ;enable EX1
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Dr. K. Ghosh
 TIMER INTERRUPTS

❑ The timer flag (TF) is raised when the timer rolls over
➢ In polling TF, we have to wait until the TF is raised
▪ The problem with this method is that the microcontroller is tied
down while waiting for TF to be raised, and can not do anything
else
➢ Using interrupts solves this problem and, avoids tying down the
controller
▪ If the timer interrupt in the IE register is enabled, whenever the timer
rolls over, TF is raised, and the microcontroller is interrupted in
whatever it is doing, and jumps to the interrupt vector table to service
the ISR
▪ In this way, the microcontroller can do other until it is notified that the
timer has rolled over

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Dr. K. Ghosh
Example I-A

Write a program that continuously get 8-bit data from P0 and sends it
to P1 while simultaneously creating a square wave of 200 s period on
pin P2.1. Use timer 0 to create the square wave. Assume that XTAL =
11.0592 MHz.
Solution:
We will use timer 0 in mode 2 (auto reload). TH0 = 100/1.085 us = 92
;--upon wake-up go to main, avoid using
;memory allocated to Interrupt Vector Table
ORG 0000H
LJMP MAIN ;by-pass interrupt vector table

;--ISR for timer 0 to generate square wave

ORG 000BH ;Timer 0 interrupt vector table

CPL P2.1 ;toggle P2.1 pin
RETI ;return from ISR
...

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Dr. K. Ghosh
Example I-A contd…

...
;--The main program for initialization
ORG 0030H ;after vector table space
MAIN: MOV TMOD,#02H ;Timer 0, mode 2
MOV P0,#0FFH ;make P0 an input port
MOV TH0,#-92 ;TH0=A4H for -92
MOV IE,#82H ;IE=10000010 (bin) enable
;Timer 0
SETB TR0 ;Start Timer 0
BACK: MOV A,P0 ;get data from P0
MOV P1,A ;issue it to P1
SJMP BACK ;keep doing it loop
;unless interrupted by TF0
END

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Dr. K. Ghosh
Example I-B

Rewrite Example I-A to create a square wave that has a high portion of
1085 us and a low portion of 15 us. Assume XTAL=11.0592MHz. Use
timer 1.
Solution:
Since 1085 us is 1000  1.085 we need to use mode 1 of timer 1.
;--upon wake-up go to main, avoid using
;memory allocated to Interrupt Vector Table
ORG 0000H
LJMP MAIN ;by-pass int. vector table

;--ISR for timer 1 to generate square wave

ORG 001BH ;Timer 1 int. vector table
LJMP ISR_T1 ;jump to ISR
...

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Dr. K. Ghosh
Example I-B contd…
...
;--The main program for initialization
ORG 0030H ;after vector table space
MAIN: MOV TMOD,#10H ;Timer 1, mode 1
MOV P0,#0FFH ;make P0 an input port
MOV TL1,#018H ;TL1=18 low byte of -1000
MOV TH1,#0FCH ;TH1=FC high byte of -1000
MOV IE,#88H ;10001000 enable Timer 1 int
SETB TR1 ;Start Timer 1
BACK: MOV A,P0 ;get d ata
Lowfrom
portionP0
of the pulse is
MOV P1,A ;issue it to by
created P114 MC
SJMP BACK ;keep doing it us = 15.19 us
14 x 1.085
;Timer 1 ISR. Must be reloaded, not auto-reload
ISR_T1: CLR TR1 ;stop Timer 1
MOV R2,#4
CLR P2.1 ;P2.1=0, start of low portion
HERE: DJNZ R2,HERE ;4x2 machine cycle 8MC
MOV TL1,#18H ;load T1 low byte value 2MC
MOV TH1,#0FCH;load T1 high byte value 2MC
SETB TR1 ;starts timer1 1MC
SETB P2.1 ;P2.1=1,back to high 1MC
RETI ;return to main
END
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Dr. K. Ghosh
Example I-C

Write a program to generate a square wave if 50Hz frequency on pin

P1.2. Assume that XTAL=11.0592 MHz
Solution:

ORG 0
LJMP MAIN
ORG 000BH ;ISR for Timer 0
CPL P1.2
MOV TL0,#00
MOV TH0,#0DCH
RETI
ORG 30H
;--------main program for initialization
MAIN:MOV TM0D,#00000001B ;Timer 0, Mode 1
MOV TL0,#00
MOV TH0,#0DCH
MOV IE,#82H ;enable Timer 0 interrupt
SETB TR0
HERE:SJMP HERE
END
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Dr. K. Ghosh
EXTERNAL HARDWARE INTERRUPTS

❑ The 8051 has two external hardware interrupts

➢ Pin 12 (P3.2) and pin 13 (P3.3) of the 8051, designated as INT0 and
INT1, are used as external hardware interrupts
▪ The interrupt vector table locations 0003H and 0013H are set
aside for INT0 and INT1
➢ There are two activation levels for the external hardware
interrupts
▪ Level trigged Activation of INT0
Level-triggered
▪ Edge trigged
0
INT0 IT0 0003
(Pin 3.2)
1 IE0
Edge-triggered (TCON.1)

Activation of INT1
Level-triggered
0
INT1 IT1 0013
(Pin 3.3)
1 IE1
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Dr. K. Ghosh Edge-triggered (TCON.3)
 LEVEL-TRIGGERED INTERRUPTS

❑ In the level-triggered mode (INT0 and INT1)

➢ If a low-level signal is applied to them, it triggers the interrupt
➢ Then the microcontroller stops whatever it is doing and jumps to
the interrupt vector table to service that interrupt
➢ The low-level signal at the INT pin must be removed before the
execution of the last instruction of the ISR, RETI; otherwise,
another interrupt will be generated
❑ This is called a level-triggered or level- activated interrupt
and is the default mode upon reset of the 8051

Dr. K. Ghosh
Example I-D

Assume that the INT1 pin is connected to a switch that is normally high.
Whenever it goes low, it should turn on an LED. The LED is connected to P1.3
and is normally off. When it is turned on it should stay on for a fraction of a
second.
.
Vcc
Solution: P1.3 to LED
ORG 0000H INT1
LJMP MAIN ;by-pass inte rrupt
;vector table
;--ISR for INT1 to turn on LED
ORG 0013H ;INT1 ISR
SETB P1.3 ;turn on LED
MOV R3,#255
BACK: DJNZ R3,BACK ;keep LED on for a
CLR P1.3 ;turn off the LED
RETI ;return from ISR

;--MAIN program for initialization

ORG 30H
MAIN: MOV IE,#10000100B ;enable external INT 1
HERE: SJMP HERE ;stay here until get interrupted
END
Dr. K. Ghosh
❑ Pins P3.2 and P3.3 are used for normal I/O unless the
INT0 and INT1 bits in the IE register are enabled
➢ After the hardware interrupts in the IE register are enabled, the
controller keeps sampling the INTn pin for a low-level signal once
each machine cycle
➢ According to one manufacturer’s data sheet,
▪ The pin must be held in a low state until the start of the
execution of ISR
▪ If the INTn pin is brought back to a logic high before the start
of the execution of ISR there will be no interrupt
▪ If INTn pin is left at a logic low after the RETI instruction of
the ISR, another interrupt will be activated after one
instruction is executed

Dr. K. Ghosh
 ➢ To ensure the activation of the hardware interrupt at the
INTn pin, make sure that the duration of the low-level
signal is around 4 machine cycles, but no more
▪ This is due to the fact that the level-triggered interrupt is not
latched
▪ Thus the pin must be held in a low state until the start of the ISR
execution
1 MC
4 machine cycles To INT0 or
1.085us INT1 pins
4  1.085us
note: On reset, IT0 (TCON.0) and IT1 (TCON.2) are both
low, making external interrupt level-triggered

Dr. K. Ghosh
 EDGE-TRIGGERED INTERRUPTS

❑ To make INT0 and INT1 edge-triggered interrupts, we must

program the bits of the TCON register
➢ The TCON register holds, among other bits, the IT0 and IT1 flag bits
that determine level- or edge-triggered mode of the hardware
interrupt
▪ IT0 and IT1 are bits D0 and D2 of the TCON register
▪ They are also referred to as TCON.0 and TCON.2 since the
TCON register is bit- addressable.
❑ In edge-triggered interrupts
➢ The external source must be held high for at least one machine cycle,
and then held low for at least one machine cycle
➢ The falling edge of pins INT0 and INT1 are latched by the 8051
and are held by the TCON.1 and TCON.3 bits of TCON register
▪ Function as interrupt-in-service flags
▪ It indicates that the interrupt is being serviced now and on this INTn pin,
and no new interrupt will be responded to until this service is finished
Dr. K. Ghosh
Example I-E

Assume that pin 3.3 (INT1) is connected to a pulse generator, write a program in
which the falling edge of the pulse will send a high to P1.3, which is connected
to an LED (or buzzer). In other words, the LED is turned on and off at the same
rate as the pulses are applied to the INT1 pin.

Solution:
ORG 0000H
LJMP MAIN
;--ISR for hardware interrupt INT1 to turn on LED
ORG 0013H ;INT1 ISR
SETB P1.3 ;turn on LED
MOV R3,#255
BACK: DJNZ R3,BACK ;keep the buzzer on for a while
CLR P1.3 ;turn off the buzzer
RETI ;return from ISR
;------MAIN program for initialization
ORG 30H
MAIN: SETB TCON.2 ;make INT1 edge-triggered int.
MOV IE,#10000100B ;enable External INT 1
HERE: SJMP HERE ;stay here until get interrupted
END
Dr. K. Ghosh
EDGE-TRIGGERED INTERRUPTS

❑ Regarding the IT0 and IT1 bits in the TCON register, the
following two points must be emphasized
➢ When the ISRs are finished (that is, upon execution of RETI), these
bits (TCON.1 and TCON.3) are cleared, indicating that the interrupt
is finished and the 8051 is ready to respond to another interrupt on
that pin
➢ During the time that the interrupt service routine is being
executed, the INTn pin is ignored, no matter how many times it
makes a high-to-low transition
▪ RETI clears the corresponding bit in TCON register
(TCON.1 or TCON.3)
▪ There is no need for instruction CLR TCON.1
before RETI in the ISR associated with INT0

Dr. K. Ghosh
INTERRUPT PRIORITY

❑ When the 8051 is powered up, the priorities are assigned

according to the following
➢ In reality, the priority scheme is nothing but an internal polling
sequence in which the 8051 polls the interrupts in the sequence
listed and responds accordingly
Interrupt Priority Upon Reset

Highest To Lowest Priority

External Interrupt 0 (INT0)
Timer Interrupt 0 (TF0)
External Interrupt 1 (INT1)
Timer Interrupt 1 (TF1)
Serial Communication (RI + TI)

Dr. K. Ghosh
 Discuss what happens if interrupts INT0, TF0, and INT1 are activated at the same
time. Assume priority levels were set by the power-up reset and the external hardware
interrupts are edge- triggered.

Solution:
If these three interrupts are activated at the same time, they are latched and kept
internally. Then the 8051 checks all five interrupts according to the sequence listed in
Table. If any is activated, it services it in sequence. Therefore, when the above three
interrupts are activated, IE0 (external interrupt 0) is serviced first, then timer 0 (TF0),
and finally IE1 (external interrupt 1).

Dr. K. Ghosh
INTERRUPT PRIORITY

❑ We can alter the sequence of interrupt priority by assigning

a higher priority to any one of the interrupts by
programming a register called IP (interrupt priority)
➢ To give a higher priority to any of the interrupts, we make the
corresponding bit in the IP register high
➢ When two or more interrupt bits in the IP register are set to high
▪ While these interrupts have a higher priority than others, they
are serviced according to the sequence of Table

Dr. K. Ghosh
INTERRUPT PRIORITY REGISTER

Priority bit = 1 assigns high priority. Priority bit = 0 assigns low priority.

-- IP.7 Reserved
-- IP.6 Reserved
PT2 IP.5 Timer 2 interrupt priority bit (8052 only)
PS IP.4 Serial port interrupt priority bit
PT1 IP.3 Timer 1 interrupt priority bit
PX1 IP.2 External interrupt 1 priority bit
PT0 IP.1 Timer 0 interrupt priority bit
PX0 IP.0 External interrupt 0 priority bit

User software should never write 1s to unimplemented bits, since they may be
used in future products.

Dr. K. Ghosh
 (a) Program the IP register to assign the highest priority to INT1(external
interrupt 1), then
(b) discuss what happens if INT0, INT1, and TF0 are activated at the same time.
Assume the interrupts are both edge-triggered.

Solution:
(a)MOV IP,#00000100B ;IP.2=1 assign INT1 higher priority. The instruction SETB
IP.2 also will do the same thing as the above line since IP is bit-addressable.
(b) The instruction in Step (a) assigned a higher priority to INT1 than the others;
therefore, when INT0, INT1, and TF0 interrupts are activated at the same time, the
8051 services INT1 first, then it services INT0, then TF0. This is due to the fact
that INT1 has a higher priority than the other two because of the instruction in
Step (a). The instruction in Step (a) makes both the INT0 and TF0 bits in the IP
register 0. As a result, the sequence in Table is followed which gives a higher
priority to INT0 over TF0

Dr. K. Ghosh
 Assume that after reset, the interrupt priority is set the instruction
MOV IP,#00001100B. Discuss the sequence in which the
interrupts are serviced.

Solution:
The instruction “MOV IP #00001100B” (B is for binary) and timer 1 (TF1)to a higher
priority level compared with the reset of the interrupts. However, since they are
polled according to Table, they will have the following priority.

Highest Priority External Interrupt 1 (INT1)

Timer Interrupt 1 (TF1)
External Interrupt 0 (INT0)
Timer Interrupt 0 (TF0)
Lowest Priority Serial Communication (RI+TI)

Dr. K. Ghosh
Example

Generate from all pins of Port 0,a square wave which is half the frequency of
the signal applied at INT0 pin (Pin 3.2). (Crystal Freq 22 MHz)

Solution:
ORG 0000H
LJMP MAIN
;--ISR for hardware interrupt INT0
ORG 0003H ;INT0 ISR
CPL P0
RETI

;------MAIN program
ORG 30H
MAIN: SETB TCON.0 ;make INT0 edge-triggered int.
MOV IE,#81H ;enable External hardware INT0
HERE: SJMP HERE ;stay here until get interrupted
END

Dr. K. Ghosh