CHex) P-)

Rom An
gO51 Itemapts theovg (ocali'on
n tenzupt P3:2l1)
)INT O /Externol harelare ilerpt 0)
Auto
Auto(2) Timer o ürterrupt (TFo)
6o13P(13)
Exfernal hardoare inkanpt 1)
Auts(3) TNTT ( OoIB
1. ntmpt (TE)
|Auto () Tier
Auto (5) Reset
(RI ond TI) Oo
2.3
Serial Com Latempt
Progan6)
cleas
it
go51.
Intempt vs Poling RxD
(mohad. Mazidi ):
T3-0
TAD
P- 222 P31
P32
P3
ISR
executing an intenup
Steps in Maziti)
Mohd
5 (P- R2,
that js Suyposed to cause an ihtept
h g051, ohen r any nent ocCs
beComas 1
fist of all, some flag Satus of thetnnybs
this Flag to detmine the pexcding
We nec oceund,
Ohe aups hav
Ohile mbre Hha
evey intempt.Rst tho flag eooms 1 (Set).
Then are flags formpt occus
an inte
hanewa
tho 15R, this fog coill be
ohenever, t prozasso goes to forgetthase
Nos ppoasor thatdor't
Cleared. Jhis remihds the ard not cad ",
yet get sevi
jnde up hasre ocuTIAd
exfernal
hardwar inarut JNTo ond lNT1 tha
For the two, 61.
am called as |ED and
 In this chapter we explore the concept of the interrupt and interrupt
interrupts are discussed. In Section 11.2 interrupts belonging to Timersprogramming.
In Section 11.1
the basics of 808
0 and 1are discussed. External hardware inter
rupts are discussed in Section 11.3, while the interrupt related to serial communication is presented in Section 114
In Section 11.5, we cover interrupt priority in the 8051/52. Finally, C programming of 8051 interrupts is covered in
Section 11.6.

VSECTION 11.1: 8051 INTERRUPTS

In this section, first we examine the difference between polling and interupts and then describe the various inler.
rupts of the S051.

Interrupts vs. polling

A single microcontroller can serve several devices. There are two ways to do that: interrupts or p In the inter
rupt method., wheneverany device needs its service, the device notifies the microcontroller by sending it an
an interrupt
signal. Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and serves the device. The
program associated with the interrupt is called theinterrupt service routine(SR) or interrupt handler. In polling, themicto
controllercontinuously monitors the status of a given device; when the status condition is met,it performs the
Ater that, it moves on to monitor the next devic until each oneis serviced. Although polling can monitor the status of
several devices and serve each ofthem as certain conditions are met, it is notan eficient use of the microcontroler. The
advantage of interrupts is that the microcontroller can serve many devices (not all at the same time, of course); each
device can get the attention of the microcontroller based on the priority assigned to it. The pollingmethod cannot assign
priority since it checks all devices in around-robin fashion. More importantly, in the interrupt method the microcon
troller can also ignore(mask)a device request for service.This is again not possible with the polling method. Themost
important reason that the interrupt method is preferable is that the polling method wastes much of the microcontrol
ler's time by polling devices that do not need service. So in order to avoid tying down the microcontroller, interrupts
are used. For example, in discussing timers in Chapter 9 we used the instruction "JNB TP, target", and waited until
the timer rolled over, and while we were waiting we could not do anything else. That is a waste of the microcontroller's
time that could have been used to perform some tasks, In the case of the timer, if we use the interrupt method,
the microcontroller can go about doing other tasks, and when the TF flag is raised the timer will interrupt
controler in whatever it is doing. the micro

Lnterrupt service routine

For every interrupt, there must be an interrupt service routine (ISR), or interrupt
invoked, the micrOController runs the interrupt service routine. For every interrupt, therehandler. When an interrupt is
is a fixed location in memory
that holds the address of its ISR. The group of memory locations set aside to hold the
interrupt vector table, shown in Table 11-1. addresses of SRs is called the

Steps in executing an interrupt

Upon activation of an interrupt, the microcontroller goes through the
following steps.
It finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack.
It also saves the current status of all the interrupts internally (i.e., not on
the stack).
It jumps to a fixed location in memory called the interrupt vector
vice routine.
table that holds the address of the interrupt ser
4 The microcontroller gets the address of the 1SR from the interrupt vector table and
the interrupt service subroutine until it reaches the last instruction jumps to it. It starts to execute
of the subroutine, which is RETI (return from
interrupt).
5 Upon executing the RETI instruction, the
gets the program counter (PC) address from microcontroller returns to the place where it was interrupted. First, t
the stack by popping the top two bytes of the stack
it starts to execute from that address. into the PC. Then

272 THE 8051 MICROCONTROLLER AND EMBEDDED SYSTEMS

 te from Step 5the critical role of the stack. For this reason, we must be careful in manipulating the stack conternts
5R. Specifically, in the 1SR, just as in any CALL subroutine, the number of pushes and pops must be equal.

the 8051
Six interrupts in
reality, only five interrupts are available to the user in the 8051, but many manufacturers' data sheets state that
.are six interrupts since they include reset. The six interrupts in the 8051 are allocated as follows.

.Ret. When the reset pin is activated,the 8051 jumps to address location 0000. This is the power-up reset discussed
in Chapter 4.
TÚo interrupts are set aside for the timers: one for Timer0 and one for Timer 1. Memory locations 000BH and
01BH in the interrupt vector table belong to Timer Oand Timer 1, respectively.
a.wo interrupts are set aside for hardware external hardwareinterrupts.Pin numbers 12(P3.2)and 13 (P3.3) inport
3are for theexternal hardwareinterrupts INTO and INTI, respectively. These external interrupts arealso refered
to as EXl and EX2. Memory locations 0003H and 0013H intheinterrupt vector table are assigned to INTO and INTI,
respectively.
4. Serial communication has a single interrupt that belongs to both receive and transmit. The interrupt vector table
Jocation 0023H belongs to this interrupt.

Notice in Table 11-1 that a limited number of bytes is set aside forr
For example, a total of 8 bytes
each
from location 0003 to 0000A is set aside for INTO, external hardware interruptO
tion 000BH to 0012His reserved for TFO, Timer0interrupt.vector
If the table:
to fit in the memory space aliocated to it, it is placed in the
serviceotherwise, intelarly, topt
routine for a given
a
is
an LJMP instruction is shor
Bbytes from loca
enough
placed in the
In
vector table to point to the address of the ISR. In that case, the rest of the bytes allocated to that interrupt are unused.
the next three sections we will see many examples of interrupt programming that clarify these concepts.
From Table 11-1, also notice that only three bytes of ROM space are assigned to the reset pin. They are ROM address
locations 0, 1, and12. Address location 3 belongs to external hardware ínterrupt 0. For this reason, in our program we put
in 11-1.
the LJMPas the first instruction and redirect the processor away from the interrupt vector table, as shown Figure
In the next section we will see how this works in the con some examples.

Table 11-1: Interrupt Vector Table for the 8051

Interrupt ROM Location (Hex) Pi Flag Clearing
0000 Auto
Reset
0003 P3.2 (12) Auto
External hardware interrupt 0 (INTO)
000B Auto
imer 0interrupt (TFO) Auto
External hardware interrupt 1 (INT1) 0013 P3.3 (13)
001B Auto
LAmer 1 interrupt (TF1)
Serial COM interrupt (RI arnd TI) 0023 Programmer clears it

;wake-up ROM reset location

ORG
MAIN ;bypas8 interrupt vector table
JMP
---- the wake-up program
VORG 30H

MAIN:

END
Interrupt Vector Table at Power-up
Figure 11-1. Redirecting the 8051 from the

INTERRUPTS PROGRAMMING IN ASSEMBLY AN 273

 e They aye the part of Tco N register.
T Cone Sp
cOhichersr intarupt hap cccuad, the
onding
CNTO)
ioill become 1"ard
fug
(E)
I am
the proessop that
oill
o Üheneer proceSor goas to the SR the Fag
Joe automati cay. So that flag is auto cleaired.

Timers Intupts
TCoN
IE1
TI TO
= EetInteupt occummd
rofo
(Auto Cleared) CAucto cjkand)

the Rom lo cati s

and

s That Theans
qoto the SR Sored .
Supendo the
pregam
at bcalion 6003H.
0NT1 is stoed at oDBt
TSR of
Similay/PII
Litsdisabled
PC-
stoek

rtn
oddYess(RA
Po?Ints PCEre natlsethdck RETI
 P3
Trts having fxed 5e addrss an calle d vectornd
interupts.
ane vectoed .
eAl intamptr Of &051
Times1.are called Timer overfoo intemyb.
Timey 0 and
orerffo D, it coil Serd as
times iill
w The moment the
inteupt to th proaso.
the tmerofbo intent, tha flgs
wt also naeds a tlag.(fo TF)
are TÈD and
in brder that tha indpt
forget about the pending
procesr does n
thá timer overfloos, thes
TFL = 1 /indicates thot an jnteupt,

cq&qre.
thatlay oill be auto

0o18H
and: Rocaiv Tht-)
intenupt LTransrit Int
SerialCom
ScON
T Ri
trnsm;ted, T; becomes !
is
hen whole dat (8-bi ) is recenved Ri L(Cleand
-Comnoh 1SR

s1, you ll get a comnon

w ohfher T is 1 6r K ISR al 6023 t.
-intmrupt, Joul go to Commpn
 (P9)
K) (Ohen does Serial port Int occur ?
Occurs cue to too Conditi
s.
v) either the Complete Charactu (- bitb)
has beeh tronsmted.
V) o, th complate character has bees ncaived.

) T; and R; haVe a comnmon ISR of sorial port

interrupt
Suppose, Serial port Inteupk hs occusd,
and the proussor coil go to the ISR. tat
Kocated a 6023 H (T; and R share a common SR)
JSR (0023 H).
if CT; = )
INT: I| transmiss isn part

(Ri=1)

corily the 1SR (0023 H) for both

hepram has
FDnt and KecoiVe nt.s.
Drsicde the 1SR, we'l check eithey (T; = =1)

Ri aud for
nside ISR, wel check the flag T; and
tee to flas shod still be I.
thal
tor other intert (like TFI, TFO, IE, IED) ts
o
is not Yeqird.
INTO
AL O003H, he SR stored oas writen fr
MTo, So you. co ned that
that was only fr
flag Eo fo be 1 C IE=1) amre.
 (P5

e Gohile gsing to the TSRif the flag is theb,i is okay,

hmn Sure thal- TSR aas orilen
becarse, processs is,
for INTo.
e But in case of JSR at o023 H, proce Ssr may Come
to th TSR fo either of. the eases.
the flag would,"heen D (auto- netcleared) pocessor
w So if evn knoor o 77
in the whether
ooud be totally Lost
part oY (ohethes to do Ri pat .
Ri Can not become
Henca, T; nd
(Can hot be ato -cle arad)
bafor 1sR stats.
pogamn to
w Henc, itis the Yasponsiilty af the
claay the TË and Ri.

Reset Vector address; ohes th

locatin o0bo is S5) junps to addrgs
Tuset Pin is activated, the
locatisn Do00 H. pgran.
nd execule the Blas /monitor
wIt is used to initiais Th evtuud
fst pogran after being RESET.
w Blos Should be the ohich is sf 3
Biggast Tump is LJmp,
LImp Blos.ADDR)
be anyohere ig
that Blos. (ould (SImp)
7 LImP so 128to tl2?
ong we are using paeASo8e
cothin f -
2KB
Soneohere; H stored Somne hese
BIOS js stoe locotisn 0000 H,
the Bo5| jumps to thae
ek, on reset
from her itill jump to BIos location
 the
w locatin oD D3 4 oTJardo, ISRa bagin,

0003
(This is t spae for
Oo0 B
Thoseare
nof-
tha

aclual
locochisws

8 byks

w8 byt spac Kep a gap to Call ocha TSR

betwen eoch and to Tetum frn tR
Rom locodion sR
to octaal
D003 Call

RETI

Back t
Main Codi

CALL in stru ctio is of 3 bytao

RET
tofal4 byteo

’ This extha 4bytoo ar there if yo wat o do

 (P+
angting before th tsk.
NDO Ohy 4 byte?
6o hat you want to do is small
’ mase
maybe larye, titis lage frst
and than CsmebackCTefn).:
Call tnat, inish bhat
sans two set o f CALL and RET;
That m
thad!s nhy
Sfalemt
RET vs RET
CTotun fom an 1S8)
(felwn
fom su roadine)

oceurnd atE that tima PC was cntaning

hen the inteYpt inshuctin(Retuon addr)
nest
ths addr. of the this het um addr.(RA) cooudbeRres.
Ahe Bo51 neado PC
into the stack Sothat
Stor this RA SR a d d r e )
PC &% 61 put the
w No nto

th RA that t has
the go5l wans,, stack
Storad in the osm
oill pop th RA pe
cHora, it put it back into inotnet.
t stack , the ne<t
back
and come tha
in almostferpt twill di sabls all
I`R,
cohile oingts the
rinterrut g051 -is
terestd in daing y
mans
er Th at ahime..
a t
ne IsR
TSR is oer, notonly it oill Teterm
K ano the Ye -enable7 ale the ntemuph.
buf also
 Subroutine) Ps
t sland fron
frsm a Subrouthne It jist simPly
RET: rtun refu'n.
al retum statemen t. Ohen tks
RETI: It is a Speci
ISR is ovr, not snly it coill petunny
ISR) butalso r-enabd the intmpt1.
tis SFR decidog tOhich interup
(Irt.Enaba 2egiste) oill be enabled Gr disablod .

D2 DI
EAXET2 Es ErL B1ETO EXO |= Enable
DDiSabu

J= Enable A| ,

(eachintupt sswce
led
enab Enablu/Disakle ext-jnt 1
vidually seting i-a.) NTLi
írck
is disatledby
or Enab le/dis cbla
Enae dsnbl extenal interyto
the seria
6= Plsableall
bit) port inkmpt CINTO)
interis EnabledisabJe Tiner o
EA fag is Dwrfloa imferpt
usd toslobally
enasles rdisable,
Ena bladisab b Timarl
ihternyp
Overflo is interup t
futfure timer,
(Thuy have plom:d aDverlo inhno
This bit is Enabla/disabls. Timer2. sny)
Tesenvadfor interpt(8o52
2052 or captre next
This btis dont sud processor:
t nce we
case
 dicablud
Main PuSHP C -s’i a c k
INT.(EA)
fo the
Ai
ln t 5

PCe1sK
adds.
ohi e g has to
disable le tha iterupt
Cmaka EA =0)
gesal
pof PCE Stack RETI
iterrupts inchose
Youl Can
Iots -enablod ehable d , nDo nd

ena Coere (E A=Ithede) nes hich

anabl
are
ohich
nd pick dont wJent
chich ohe Jou
one you
coart

H into E g.
IPCharag
bled . Tf pngommerloado
heppen ? Explain.
(Interupt Priority ) hhoccumedsimultoneouy,
E0
iterip interup cOould be
too sr mae cohich
r When okcidep
mechanison
sprioriy
rviced f t . owar priaiy
cd fst
be pervithghitoill remain
Higher printy one toill
Cooutd not be lost
-inderptt nuspective lag bita)
in the
pding Dy DsD PL Do
D Do Ds
IP Pxd
xPT2 PS PT1 PX1PT
pricty bit priortty bid for
Resenved prorty bit fr Etemal Trierupt o
for Seri al Ext. Tnt1.
port interupl pioity bd fm
Timer o inknupt

inteupl
prioit
bit fr Timer 2 'intenupt
no} sed for 2051)
rsurvd for go52 only
 (P-)
all o's.
Opon pobier- up reset, the IP eg: contei priority
makig the pmority saquonce baszd n the defaut
toble as folloos;

Trderupt Priovity n Rest

Highert to lo secd Priesity
Ext. DntO (INTO
Timer Tht o (TFO)
Ext. t. 1 (INT1
Timer nt. 1 (TFI)
Serial Communicstion

Tihner 2 (eos2. My) (TFa)

exampl, that fexternad
Frm this tatle we Cas cee for
inteupt o and 1 ane activated al the
hard war ntemupt o(INTO) s respsncedfo
Some time, extema Sepvice is iNT1
INTO has been
finst. Ohly aftes prionity
Serv iced, as iNTI hos the.loKJOZ

the
Now, to gie a highr prion
correap sning bit in the
interpts) we make the
IP rgi sto high has tha value = 11#,
i-e.
No, Supp

IP |x x PT2| Ps| PTI

 (Pn)
that INTO und serial pat iterups have higher
means,
Cthey ar aetivatd at the saa tima)
prio ity
and the other iters upt have loo prioity Serial
beoees NTo and
Hene, ther is a clash /tie
port nte nupt s. bro ken by the defaut piori
This tie Cou ld be
tabie as discussd befor.

Ek: IE12 P 289 (nazidi)

assign he hig hest priosity to NTL
the, IP rg to
Cextenal Thrterzupt 4), then JNT1, and Tf0 ar
happend if INTD,
(b) iscu ohat
activad at the Same time. edge-ijjerd.
the intemupt ane both
Ass wme tnaf
DL00B3 IP. 2 =1
t0006
a) mov IP, Gssign hghst
bif-addnssable, we can also
Sine LP is
priority ko INTL
SETB IP. 2

stepa) asiged a hgher prioity to NT1

) Instuchom in JNTD, INTI, und TFo
than heohes; therefore oher
Same tme, +he g051 services
inteupt Ocur, al the
INT1 fisk, defaalt
ís followed)
then NTO ) thy TFO. (a
and
Interupt Program
Square ware
’ We a done it before hend, but we did if using
coheties
poling method (bere go5l Kept chee king
Himes has Anished wtr Count cr not and from real
wonld psint of vieo that is nof what we just wont
bacau se it keeps the proce(Sors busg in checking
-he timer oves low Hay the vohole idea of using
a timeg is to pro duce a hlo delaj cohue
the
imer produces the delay, Keeping, procasSoY (8o51)
free to do otner opatiss.
Which meas ohe, the de fay is oves, the times isspposcd
to ntemupt th pro casor.
So, this is the pram hese oe are
gsing fo use the timer terupt to generate
the delay
as ALp to zenerate a squan oarei cn
rite S'iedekep
uSing tma inteupt. Side by
pn PO. 0 Sending it out to poat
asing dala from pozt PLard
P2 continuousy 8D51 Thatsqure wave
delay cuR b bapprl
-in the background,
wthout the qcfir
invejvesnent of fhe
Precessr,
The proce Gor is
Constanty getiny
datafoon PI and stnding
that date to P2
Cin the foagrond )
 (P-Ls)
ORG 0000H

LJmP MAIN j bypas

inteupt vecty table
000BH
LJMP TDISR
OD3D H
ORG
Intlel
satiJ # OFf Hj port Pl as inpt por
mAI: mov PI, interpt
#82 4 j enab le TFO
Mov IE,
mode -
TmoD #OlH j Timen o
mov load. bwer bytfcont
nov TO, # 0C# 5 of count
H; load higher bjte
Lmov THO, #OFE Stert-inen o
SETB TRO
Po.o O
CLR Po"0

HERE: Mov A, PJ Drfintte loop,

(Bos1) coes
(hov P2, A sso
prainan infinle foep
HERE this
this
infinite Lntil imes ioteLupts t
ISR: CAL
of IKHtz fre CLR TRO

Sq: wave is mov TLO, ttocH

1 milli second(ors) nov THO,#OFEH

Tine period= SETB TRO
( durati on of RETI
Ge pule)

=0*5 ms= 500 ys

puse
dejay= dunatlon f half = 500 Cownt
2MH
bfwe asume TPL=
+na -mear (outing faquency = 12
that meano 1. Count is a delay of es )
 (P-l4

Count to be laade sl =(66635-56D t)

(650 36),, = FEO c#

e nac to enable the interupt (tiner intonzpt)

SFR is used to ehable /isable aL tha intmupt
e The nss (D4) 'EA' is a global enabl bit.
D3 D2
EA
ET2 Es ET|EXI|ETEKO|-g2#
0O.
individual enable /disas le
îh genesal
whan EA=1, jnten upts 1n genral are enablad
Py to D Hou can Choose which
ad fom intnupt you jast nd
u don't coant

Henca,
EA nust be 1

Tmop

mode-1
as a timu°,
tis cowrting the
nterna elock freq
 (P-15

Here:
M6v
A, PI
P2, A coill
cgntsor)
prgmn,
rmain hes fo
Here the rest of span
imeo
ba an Sntemupt;
Owrflows, thesa l
defouutt oi ! teka th program
the intmypt by to location 000BH.
ContofC procegso) to the actua/
Il gump
locatin (ooo BH), 051
bom that hee)
îSR lbcatio CTO ISR
labal ohich will get assignsd t
La
address by th asemblery

Tns; de TolSR, ented

ovoflousn, thatts cohy we
the timer has
the ISR. valu for the Square
We've slarte o h a lo
Cwave CCLR PO. D) Po.o (CPL Po.o)
Hena, cw hae to Complemet
w

CLR TRO
stops, you haato mae runbit o,
when inmer run bit 0.
imr oDht Take the
nexk tie hen gou want to start
SETB TRÝ, it on' t
the times by using Henee e shauld mate ito
becaue it was aready 1. beforhal;
 f-16

w Give he count of the iner ag n

alnay
have give h the mode, hence it js not aqu ired to
Set up th mode again. (mon)
start imer O.
Pf fhe end we've to rite RETI
RET

to a ISR all iteryh ae

disabled We have to enasle intempb gains
oHneroi<,
So, ve have to ont RETI at tha ed of TSR.

In timer program (earien), aftr Stautiag the

timer SETB TR, w (the processo) have to
watr ha tinas to DeofoD ( WAIT: JNS TFX WaT)
w but cwe (the pro Caiso) a not oarting here ?
Becau s, the Internapt coill automaically occun
ohen the tims oeg floos.
w Once you kno uo the hines has oVerfon, you hare
to Clear TRO So that we cah start the timer
agin earlier
we used do elea TFX in, timer prgTam,
.TFo oTFI)
but her oe id not -Timer Ovoftoo fug)
Because, it was merienet that TFX flags
Cuto ceared'vohen wa fo to the JSk.
 Dn the previ ous program , wedd not ase TSR,
Orselves.
So we had to clea the flags
Ghe pmogrnne)
the 15R CTo /SR), hence
Put hee, e ae Joiny to
need to clea TA0.
TEO is outo cleared, e do

6)7TOISR: CAL
Lomp MAIN CLR TRD
TLo, #oCH
ORG 000BH mov
2 (nov THO, #OFEH
LJMP TO ISR
D030 H SETB TRO
ORG
PI, #oFAH RETI
MAIN:
mo IE, #82t
nov TmO D,#OIH
THO,#OFEH DSRadass
gotothe o00BH
tt oillJunp
(Mov TLO,#ocH T h aISK
SETB TRO
fon
and to tra
PD.0
HERE: A, PI
mov P2., A
TFO HERE