Microprocessor I: Dr. Abouelmaaty M. Aly

ELE207/208: Microprocessor I
Dr. Abouelmaaty M. Aly

Chapter 2
The Microprocessor and Its Architecture
ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 2

Agenda: The Microprocessor and Its Architecture – Chapter 2 (Textbook)
o Internal Microprocessor Architecture.
o Real Mode Memory Addressing.
o Introduction to Protected Mode Memory Addressing.
o Memory Paging.
o Flat Mode Memory.

Internal Microprocessor Architecture
 Before a program is written or instruction investigated, internal configuration of

the microprocessor must be known.
 In a multiple core microprocessor each core contains the same programming
model.
 Each core runs a separate task or thread simultaneously.

Internal Microprocessor Architecture - The Programming Model
 8086 through Core2 considered program visible.

 registers are used during programming and are specified by the instructions.
 Other registers considered to be program invisible.

 not addressable directly during applications programming, but may be used indirectly during
system programming.

Internal Microprocessor Architecture - Basic Program Execution Registers
 Registers are high speed memory inside the CPU
 Eight 32-bit general-purpose registers.
 Six 16-bit segment registers.
 Processor Status Flags (EFLAGS) and Instruction Pointer (EIP).

Internal Microprocessor Architecture - General-Purpose Registers
 Used for arithmetic and data movement
- mov EAX, 10 move constant 10 into register EAX
 Specialized uses of Registers

- EAX – Accumulator register
• Automatically used by multiplication and division instructions
- ECX – Counter register
• Automatically used by LOOP instructions
- ESP – Stack Pointer register
• Used by PUSH and POP instructions, points to top of stack
- ESI and EDI – Source Index and Destination Index register
• Used by string instructions
- EBP – Base Pointer register
• Used to reference parameters and local variables on the stack

Internal Microprocessor Architecture - Accessing Parts of Registers
 EAX, EBX, ECX, and EDX are 32-bit Extended registers
8 8
 Programmers can access their 16-bit and 8-bit parts AH AL 8 bits + 8 bits
 Lower 16-bit of EAX is named AX

AX 16 bits
 AX is further divided into
o AL = lower 8 bits EAX 32 bits
o AH = upper 8 bits
 ESI, EDI, EBP, ESP have only 16-bit names for lower half

Internal Microprocessor Architecture - Special-Purpose & Segment Registers
 EIP = Extended Instruction Pointer
 Contains address of next instruction to be executed
 EFLAGS = Extended Flags Register
 Contains status and control flags
 Each flag is a single binary bit
 Six 16-bit Segment Registers
 Support segmented memory
 Six segments accessible at a time
 Segments contain distinct contents
o Code
o Data
o Stack

Internal Microprocessor Architecture - Multipurpose Registers
 RAX - a 64-bit register (RAX), a 32-bit register (accumulator: EAX), a 16-bit register (AX), or as
either of two 8-bit registers (AH and AL). The accumulator is used for instructions such as
multiplication, division.
 RBX, addressable as RBX, EBX, BX, BH, or BL.

• BX register (base index) sometimes holds offset address of a location in the memory system in
all versions of the microprocessor.
 RCX, addressable as RCX, ECX, CX, CH, or CL.

• a (count) general-purpose register that also holds the count for various instructions. The shift
and rotate instructions use CL as the count, the repeated string instructions use CX, and the
LOOP instructions use either CX or ECX.

 RDX, addressable as RDX, EDX, DX, DH, or DL.
• a (data) general-purpose register and holds a part of the result from a multiplication or part of
dividend before a division.
 RBP, addressable as RBP, EBP, or BP.

• points to a memory (base pointer) location or memory data transfers.
 RDI addressable as RDI, EDI, or DI.

• often addresses (destination index) string destination data for the string instructions.

 RSI used as RSI, ESI, or SI.
• the (source index) register addresses source string data for the string instructions like RDI, RSI
also functions as a general-purpose register.
 R8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled.
• data are addressed as 64-, 32-, 16-, or 8-bit sizes and are of general purpose.
 Most applications will not use these registers until 64-bit processors are common.
• the 8-bit portion is the rightmost 8-bit only.
• bits 8 to 15 are not directly addressable as a byte.

Internal Microprocessor Architecture - Special-Purpose Registers
 Include RIP, RSP, and RFLAGS
• segment registers include CS, DS, ES, SS, FS, and GS.
 RIP addresses the next instruction in a section of memory.

• defined as (instruction pointer) a code segment.
 RSP addresses an area of memory called the stack.

• the (stack pointer) stores data through this pointer.
 RFLAGS indicate the condition of the microprocessor and control its operation.
• Flags never change for any data transfer or program control operation.

Internal Microprocessor Architecture - EFLAGS Register with 8086 family
EFLAG and FLAG register counts for the entire 8086 and Pentium microprocessor family

Internal Microprocessor Architecture - EFLAGS Register
 Status Flags
 Status of arithmetic and logical operations
 Control and System flags
 Control the CPU operation
 Programs can set and clear individual bits in the EFLAGS register

Internal Microprocessor Architecture – Status Flags
 Carry Flag: Set when unsigned arithmetic result is out of range.
 Overflow Flag: Set when signed arithmetic result is out of range.
 Sign Flag: Copy of sign bit, set when result is negative.
 Zero Flag: Set when result is zero.
 Auxiliary Carry Flag: Set when there is a carry from bit 3 to bit 4.
 I (interrupt): controls operation of the INTR (interrupt request) input pin.
 D (direction): selects increment or decrement mode for the DI and/or SI registers.
 Parity Flag: Set when parity is even.
• if result is a word, only 8 low bits (Least-significant byte) are analyzed.
• If this result contains even number of 1s, this flag is set.
• if a number contains three binary one bits, it has odd parity (Logic 0).
• if a number contains no one bits, it has even parity (Logic 1).

Internal Microprocessor Architecture – Segment Registers
 Generate memory addresses when combined with other registers in the microprocessor.
 Four or six segment registers in various versions of the microprocessor.
 A segment register functions differently in real mode than in protected mode.
 Following is a list of each segment register, along with its function in the system.

Internal Microprocessor Architecture – Segment Registers
 CS (code) segment holds code (programs and procedures) used by the microprocessor.
 DS (data) contains most data used by a program.

• Data are accessed by an offset address or contents of other registers that hold the offset address.
 ES (extra) an additional data segment used by some instructions to hold destination data.
 SS (stack) defines the area of memory used for the stack.

• stack is determined by the stack segment and stack pointer registers.
• the BP register also addresses data within the stack segment.
 FS and GS segments are supplemental segment registers available in 80386 – Core2 microprocessors.
• allow two additional memory segments for access by programs.

Real Mode Memory Addressing – Modes of Operation
 Real-Address mode (original mode provided by 8086 processor)
• Only 1 MB of memory can be addressed, from 0 to FFFFF (hex).
• Programs can access any part of main memory.
• MS-DOS runs in real-address mode.
 Protected mode (introduced with the 80286 processor)
• Each program can address a maximum of 4 GB of memory.
• The operating system assigns memory to each running program.
• Programs are prevented from accessing each other’s memory.

Real Mode Memory Addressing – Modes of Operation
 Virtual 8086 mode
• Processor runs in protected mode, and creates a virtual 8086 machine with 1 MB of address
space for each running program.
 80286 processor and above operate in either the real or protected mode.
 Real mode operation allows addressing of only the first 1M byte of memory space — even in
Pentium 4 or Core2 microprocessor.
• the first 1M byte of memory is called the real memory, conventional memory, or DOS memory
system.

Real Mode Memory Addressing – Real Address Mode
 A program can access up to six segments at any time.
• Code segment
• Stack segment
• Data segment
• Extra segments (up to 3)
 Each segment is 64 KB
 Logical address
• Segment = 16 bits
• Offset = 16 bits
 Linear (physical) address = 20 bits

Logical to Linear Address Translation
Linear address = Segment × 10 (hex) + Offset
Example:
• segment = A1F0 (hex)
• offset = 04C0 (hex)
• logical address = A1F0:04C0 (hex)
• what is the linear address?
Solution:
A1F00 (add 0 to segment in hex)
+ 04C0 (offset in hex)
A23C0 (20-bit linear address in hex)

Your Turn …..
What linear address corresponds to logical address 028F:0030?
Solution: 028F0 + 0030 = 02920 (hex)
Always use hexadecimal notation for addresses
What logical address corresponds to the linear address 28F30h?
Many different segment:offset (logical) addresses can produce

the same linear address 28F30h. Examples:
28F3:0000, 28F2:0010, 28F0:0030, 28B0:0430, . . .

This Figure shows the real mode memory-addressing
scheme, using a segment address plus an offset.
• This shows a memory segment beginning at 10000H, ending at

location 1FFFFH.
• 64K bytes in length.
• Also shows how an offset address, called a displacement, of

F000H selects location 1F000H in the memory.

Default Segment and Offset Registers
 The microprocessor has rules that apply to segments whenever memory is addressed.
• these rules, which apply in the real and protected mode, define the segment and offset register
combination.
 The code segment register defines the start of the code segment.
 The instruction pointer locates the next instruction within the code segment.
 Another of the default combinations is the stack.

• stack data are referenced through the stack segment at the memory location addressed by either the
stack pointer (SP/ESP) or the pointer (BP/EBP).
 The next Figure shows a system that contains four memory segments.
• a memory segment can touch or overlap if 64K bytes of memory are not required for a segment.

This Figure shows a memory system showing the placement
of four memory segments.
• a program can have more than four or six segments, but

only access four or six segments at a time.

Introduction to Protected Mode Memory Addressing
 Protected mode memory addressing allows access to data and programs located within & above the first
1M byte of memory.
 Protected mode is where Windows operates.
 In place of a segment address, the segment register contains a selector that selects a descriptor from a
descriptor table.
 The descriptor describes the memory segment’s location, length, and access rights.
 Because the segment register and offset address still access memory, protected mode instructions are
identical to real mode instructions.
 In fact, most programs written to function in the real mode will function without change in the protected
mode.
 The difference between modes is in the way that the segment register is interpreted by the microprocessor
to access the memory segment.

Introduction to Protected Mode Memory Addressing - Selectors and Descriptors
 The selector, located in the segment register, selects one of 8192 descriptors from one of two tables
of descriptors. So, a total of 16,384 total descriptors are available to an application at any time.
 The descriptor describes the location, length, and access rights of the segment of memory.
 Indirectly, the segment register still selects a memory segment, but not directly as in real mode.
• For example, in the real mode, if CS = 0008H, the code segment begins at location 00080H. In
the protected mode, this segment number can address any memory location in the system for
the code segment, as explained in next slides.

Introduction to Protected Mode Memory Addressing - Segment Descriptor Tables
There are two descriptor tables used with the segment registers:
 Global Descriptor Table (GDT) or (System descriptor)
• It contains segment descriptors for all programs.
• Table is initialized during boot up.
• GDT table address is stored in the GDTR register.
• Modern operating systems (Windows-XP) use one GDT table.
 Local Descriptor Table (LDT) or (Application descriptor)
• It contains segment descriptors for only one program or application.
• LDT table address is stored in the LDTR register.
 Each descriptor is 8 bytes in length.
 Global and local descriptor tables are a maximum of 64K bytes in length.

This Figure shows the 80286

through Core2 64-bit descriptors.
 The base address portion of the descriptor

indicates the starting location of the memory
segment.
 For the 80286 microprocessor, the base
address is a 24-bit address, so segments
begin at any location in its 16M bytes of
memory.

Segment Descriptor Details
 Base Address
• 32-bit number that defines the starting location of the segment.
• 32-bit Base Address + 32-bit Offset = 32-bit Linear Address.
 Segment Limit
• 20-bit number that specifies the size of the segment.
• The size is specified either in bytes or multiple of 4 KB pages.
• Using 4 KB pages, segment size can range from 4 KB to 4 GB.
 Access Rights
• Whether the segment contains code or data.
• Whether the data can be read-only or read & written.
• Privilege level of the segment to protect its access.
 The G, or granularity bit allows a segment length of 4K to 4G bytes in steps of 4K bytes.

This Figure shows the access

rights byte for the 80286
through Core2 descriptor. It
controls access to the
protected mode segment.

 Descriptors are chosen from the descriptor table by the segment register.
• register contains a 13-bit selector field, a table selector bit, and requested privilege level field (2
bits).
 The TI bit selects either the global or the local descriptor table.
 Requested Privilege Level (RPL) requests the access privilege level of a memory
segment.

Upper 13 bits of segment selector are

used to index the descriptor table
TI = Table Indicator
Select the descriptor table
0 = Global Descriptor Table
1 = Local Descriptor Table
RPL = Requested privilege level

00 = highest PL
11 = lowest PL

 This Figure shows how the segment
register, containing a selector,
chooses a descriptor from the global
descriptor table.
 The entry in the global descriptor

table selects a segment in the
memory system.
 Descriptor zero is called the null

descriptor, must contain all zeros, and
may not be used for accessing
memory.

 This Figure using the DS

register to select a description
from the global descriptor
table.
 In this example, the DS register
accesses memory locations
00100000H–001000FFH as a
data segment.

Memory Paging
 The memory paging mechanism allows any physical memory location to be

assigned to any linear address.
 Linear address is defined as the address generated by a program.
 Physical address is the actual memory location accessed by a program.
 With memory paging, the linear address is invisibly translated to any physical
address.

Memory Paging - Paging
 Paging divides the linear address space into
• Fixed-sized blocks called pages, Intel IA-32 uses 4 KB pages.
 Operating system allocates main memory for pages
• Pages can be spread all over main memory.
• If main memory is full then pages are stored on the hard disk.
 OS has a Virtual Memory Manager (VMM)
• Uses page tables to map the pages of each running program.
• Manages the loading and unloading of pages.
 As a program is running, CPU does address translation.

Memory Paging - Paging
Main Memory
The operating
system uses Page m ... Page n
linear virtual address
linear virtual address

space of Program 1
space of Program 2
page tables to ... ...
map the pages
Page 2 Page 2
in the linear
virtual address Page 1 Page 1
space onto Page 0 Page 0
main memory
Hard Disk
Pages that cannot The operating system
Each running
fit in main memory swaps pages
program has its
are stored on the between memory
own page table
hard disk and the hard disk
As a program is running, the processor translates the linear virtual addresses onto real memory (called
also physical) addresses

Memory Paging - The Page Directory and Page Table
 Only one page directory in the system.
 The page directory contains 1024 double word addresses that locate up to 1024
page tables.
 Page directory and each page table are 4K bytes in length.
 Next Figure shows the page directory, a few page tables, and some memory
pages.

Memory Paging - The Page Directory and Page Table
The paging mechanism in

the 80386 through Core2
microprocessors.

Flat Mode Memory
 The memory system in a Pentium-based computer (Pentium 4 or Core2) that uses the
64-bit extensions uses a flat mode memory system.
 A flat mode memory system is one in which there is no segmentation.
 The address of the first byte in the memory is at 00 0000 0000H and the last location is
at FF FFFF FFFFH (address is 40-bits).
 The flat model does not use a segment register to address a location in the memory.
 The CS segment register is used to select a descriptor from the descriptor table that
defines the access rights of only a code segment.
 The flat model does not select the memory address of a segment using the base and
limit in the descriptor.

Flat Mode Memory
 In 64-bit mode the actual address is not
modified by the descriptor as in 32-bit
protected mode. The offset address is the
actual physical address in 64-bit mode.
Refer to next Figure for the flat mode
memory model.
The 64-bit flat mode memory model.

Flat Mode Memory - Programmer View of Flat Memory
 Same base address for all segments Linear address space of a
program (up to 4 GB)
• All segments are mapped to the same linear address space. 32-bit address
ESI
 EIP Register EDI DATA
• Points at next instruction. 32-bit address
EIP
CODE
 ESI and EDI Registers
32-bit address
• Contain data addresses. EBP STACK

ESP
• Used also to index arrays. CS
DS Unused
 ESP and EBP Registers
SS
• ESP points at top of stack. ES
base address = 0 for
• EBP is used to address parameters and variables on the stack. all segments


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ELE207/208: Microprocessor I

Dr. Abouelmaaty M. Aly

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 2

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 3

 Before a program is written or instruction investigated, internal configuration of

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 4

 8086 through Core2 considered program visible.

 Other registers considered to be program invisible.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 5

 Six 16-bit segment registers.

 Processor Status Flags (EFLAGS) and Instruction Pointer (EIP).

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 6

 Specialized uses of Registers

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 7

 Lower 16-bit of EAX is named AX

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 8

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 9

 RBX, addressable as RBX, EBX, BX, BH, or BL.

 RCX, addressable as RCX, ECX, CX, CH, or CL.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 10

dividend before a division.

 RBP, addressable as RBP, EBP, or BP.

 RDI addressable as RDI, EDI, or DI.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 11

• bits 8 to 15 are not directly addressable as a byte.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 12

 RIP addresses the next instruction in a section of memory.

 RSP addresses an area of memory called the stack.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 13

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 14

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 15

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 16

 Four or six segment registers in various versions of the microprocessor.

 A segment register functions differently in real mode than in protected mode.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 17

 DS (data) contains most data used by a program.

 SS (stack) defines the area of memory used for the stack.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 18

• Only 1 MB of memory can be addressed, from 0 to FFFFF (hex).

• Programs can access any part of main memory.

• MS-DOS runs in real-address mode.

 Protected mode (introduced with the 80286 processor)

• Each program can address a maximum of 4 GB of memory.

• The operating system assigns memory to each running program.

• Programs are prevented from accessing each other’s memory.

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 19

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 20

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 21

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 22

Solution: 028F0 + 0030 = 02920 (hex)

Always use hexadecimal notation for addresses

What logical address corresponds to the linear address 28F30h?

Many different segment:offset (logical) addresses can produce

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 23

• This shows a memory segment beginning at 10000H, ending at

• 64K bytes in length.

• Also shows how an offset address, called a displacement, of

ELE207/208: Microcontroller I Dr. Abouelmaaty M. Aly 24

 Another of the default combinations is the stack.