Scribd Logo
Upload

Welcome to Scribd!

  • 8 views

    Jana 22BLC1032

    Uploaded by

    janardhanan1711
    An XOR gate and 4x1 multiplexer are designed using pass transistors. The delay and power of the multiplexer circuit are analyzed. A CMOS inverter layout is produced and DRC, LVS, and parasitic extraction are performed to verify the layout.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Jana 22BLC1032

    Uploaded by

    janardhanan1711
    8 views26 pages
    An XOR gate and 4x1 multiplexer are designed using pass transistors. The delay and power of the multiplexer circuit are analyzed. A CMOS inverter layout is produced and DRC, LVS, and parasitic extraction are performed to verify the layout.

    Original Title

    Jana_22BLC1032.docx

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    An XOR gate and 4x1 multiplexer are designed using pass transistors. The delay and power of the multiplexer circuit are analyzed. A CMOS inverter layout is produced and DRC, LVS, and parasitic extraction are performed to verify the layout.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    8 views26 pages

    Jana 22BLC1032

    Uploaded by

    janardhanan1711
    An XOR gate and 4x1 multiplexer are designed using pass transistors. The delay and power of the multiplexer circuit are analyzed. A CMOS inverter layout is produced and DRC, LVS, and parasitic extraction are performed to verify the layout.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 26

    Name: Janardhanan V

    Reg. No. 22BLC1032

    EXPERIMENT NO. 5 IMPLEMENTATION OF CMOS COMBINATIONAL


    CIRCUITS - XOR GATE, HALF ADDER AND FULL ADDER
    Aim: 1. To construct a XOR gate and create a
    symbol for the same.
    2. To construct a Half Adder using the
    XOR symbol created above and
    perform delay and power analysis.
    Furthermore, construct a symbol for the
    Half Adder and analyse the same.
    3. Design and construct a Full Adder using
    basic gates and using the Half Adder
    symbol and compare the both the
    designs with respect to their power and
    delay analysis

    Software Tools required:


    Cadence Virtuoso and Spectre simulator

    Theory:

    XOR Gate:
    The XOR gate, also known as the Exclusive OR gate, performs a logical operation on
    two binary inputs. Unlike a regular OR gate, the XOR only outputs a 1 (TRUE) if exactly one of
    its inputs is 1 (TRUE).

    Functionality:
    Takes two binary inputs (0 or 1).
    Outputs a 1 (TRUE) only if one, and only one, of the inputs is 1 (TRUE).
    Outputs a 0 (FALSE) if both inputs are 0 (FALSE) or both are 1 (TRUE).

    Truth Table

    A B Y
    0 0 0
    0 1 1
    1 0 1
    1 1 0

    Half Adder:
    A half adder is a digital circuit that performs the basic addition of two single-bit binary
    numbers. It's the fundamental building block for more complex adders like full adders.
    Functionality:
    Takes two binary inputs (A and B, each 0 or 1).

    Outputs two bits:


    Sum (S): Represents the least significant bit (LSB) of the result (0 or 1).
    Carry (C): Indicates if there's a carry-over (overflow) from the addition (0 or 1).

    Truth Table

    A B Sum Carry
    0 0 0 0
    0 1 1 0
    1 0 1 0
    1 1 0 1

    Full Adder:
    A full adder is the workhorse of binary addition in digital circuits. It takes a step further
    than a half adder by considering a third input, allowing for multi-bit addition. Here's a deep dive
    into the theory of full adders:

    Functionality:
    Takes three binary inputs:
    Two bits to be added (A and B, each 0 or 1).
    Carry-in (Cin) from the previous addition stage (0 or 1).

    Outputs two binary bits:


    Sum (S): Represents the least significant bit (LSB) of the addition result (0 or 1).
    Carry-out (Cout): Indicates if there's a carry-over to the next higher bit position (0 or 1).

    Truth Table

    A B Cin Sum Carry


    0 0 0 0 0
    0 0 1 1 0
    0 1 0 1 0
    0 1 1 0 1
    1 0 0 1 0
    1 0 1 0 1
    1 1 0 0 1
    1 1 1 1 1

    Schematic design:

    1. XOR Gate

    Symbol:
    2. Half Adder:

    3. Full Adder:
    4. Full Adder Using Half Adders:

    Simulation Outputs And Performance Analysis:

    1. XOR Waveform:
    2. Half Adder Waveform:

    3. Delay for Half Adder:


    4. Average Power for Half Adder:

    FULL ADDERS:

    1. Waveform for Full Adders using gates:


    2. Delay for Full Adders using gates:

    3. Average Power for Full Adders using gates:


    5. Waveform for Full Adders using Half Adders:

    6. Delay for Full Adders using Half Adders:


    7. Average Power for Full Adders using Half Adders:

    Inferences:

    • As a result, an XOR gate is designed and given a symbol.


    • We have successfully developed and built a Half Adder circuit using the XOR
    gate, and a symbol for it has been created.
    • In addition, a Full Adder was created using two different methods:
    • Making use of simple gates
    • A transient analysis is performed using half adders to confirm its accuracy, and
    the truth table for every circuit mentioned above has been confirmed.
    An investigation of the average power and latency has been conducted to assess
    its performance.
    • Half Adder circuit delay: 200.1 E^-9
    • Full Adder circuit delay when using basic gates: 100.2 E^-9
    • When half adders are utilized, the full adder circuit delay is 100.1 E^-9.
    • Half Adder's Average Power
    Name: Ganapathi Karthik
    V
    Reg. No. 22BLC1346

    EXPERIMENT NO. 6 IMPLEMENTATION OF XOR GATE USING PASS


    TRANSISTORS - CPL BASED 4X1 MUX
    1. To construct a XOR gate using pass
    AIM:
    transistors.
    2. To construct a 4x1 Mux using a
    Complementary Pass Logic.
    3. Performance Analysis of the Mux circuit.

    Software Tools required:


    Cadence Virtuoso and Spectre simulator

    Theory:

    A 4x1 Multiplexer (MUX) is a digital circuit that allows you to select one out of four data
    inputs and route it to a single output. Here's a breakdown of the theory:

    Functionality:
    It has four data inputs (D0, D1, D2, D3).
    It has two selection lines (S0 and S1).
    These selection lines act as a control mechanism.
    Based on the binary value on the selection lines, the MUX picks one data input and connects it to
    the output (Y).

    S1 S0 A B C D Out
    0 0 0 x x X 0

    0 0 1 x x X 1

    0 1 x 0 x X 0

    0 1 x 1 x X 1

    1 0 x x 0 X 0

    1 0 x x 1 X 1

    Truth Table
    1 1 x x x 0 0

    1 1 x x x 1 1

    Schematic design:

    1. XOR Gate using pass transistor:


    2. 4x1 Mux using Complementary pass logic:

    Simulation Outputs and Performance Analysis:

    1. 4x1 Waveform:
    2. Delay for 4x1 Mux:

    3. Average Power for 4x1 Mux:


    Inferences:

    Pass transistor logic is thus used in the design of an XOR gate.

    Complementary pass logic is used in the design and construction of a 4x1 Mux,
    and its performance is examined.
    The truth table for every circuit mentioned above has been confirmed, and a
    transient analysis is performed to confirm that it is accurate.

    An investigation of the average power and latency has been conducted to assess
    its performance.
    • The 4x1 Mux's delay is 300. E^-9
    • The 4x1 Mux's average power is 401.3 E^-6.
    Name: Ganapathi Karthik
    V
    Reg. No. 22BLC1346

    EXPERIMENT NO. 7 PHYSICAL DESIGN OF CMOS INVERTER -


    LAYOUT DESIGN, DRC, LVS AND PARASITIC EXTRACTION
    AIM:
    1. To construct a CMOS inverter circuit and create a physical design.
    2. To perform DRC, LVS and Parasitic extraction for the same

    Software Tools required:


    Cadence Virtuoso and Spectre simulator

    Theory:

    Physical design in VLSI is the stage where the logical design of a circuit gets translated into a
    physical layout on a silicon chip. Theory in this domain focuses on optimizing this layout to
    achieve specific goals.

    Schematic design:

    1. CMOS inverter:
    2. Layout design view:

    3. AV extracted view:
    Simulation outputs:

    1. DRC

    2. LVS:
    3. Parasitic Extraction:

    Inferences:

    Consequently, a CMOS inverter is developed in order to produce a physical


    design.
    For the CMOS inverter, a layout has been made that essentially shows how the
    components are arranged and connected throughout the circuit.
    To ensure that our layout design is correct, DRC (design rule check), LVS, and
    parasitic extraction have been performed. It also demonstrates how the diffusion
    layer and all others are produced inside a chip.
    Name: Ganapathi Karthik
    V
    Reg. No. 22BLC1346

    EXPERIMENT NO. 8 CMOS IMPLEMENTATION OF SEQUENTIAL


    CIRCUITS - D FLIP-FLOP AND 4 BIT SISO SHIFT REGISTER
    1. To construct D Flip Flop in CMOS logic.
    AIM:
    2. To construct a 4-bit SISO Shift register using
    D flip-flops
    3. Performance Analysis of both circuits

    Software Tools required:


    Cadence Virtuoso and Spectre simulator

    Theory:

    D Flip-flop:
    The theory behind a D flip-flop revolves around its ability to store data and control its output
    based on a clock signal. Here's a breakdown of the key concepts:

    Functionality:

    A D-FF has two main inputs:


    Data (D): This single input determines the value the flip-flop will store.
    Clock (CP or CLK): This controls when the data is captured and reflected on the output.
    It has two outputs:
    Output (Q): This represents the current data stored in the flip-flop.
    Inverted Output (Q'): This is the logical complement of the output (Q = !Q').
    Operation:

    When the clock signal (CP/CLK) is LOW, the D-FF enters a hold mode. In this state, the circuit
    ignores the data input (D) and retains its current output state (Q).
    At the rising edge (positive transition) of the clock signal, the D-FF captures the value present at
    the data input (D) and stores it as its new output (Q).

    Truth Table:

    Clock (CP/CLK) Data (D) Output (Q)


    LOW X Q (previous state)
    HIGH (rising edge) 0 0
    HIGH (rising edge) 1 1
    4- bit SISO Shift Register:
    A 4-bit SISO shift register is a digital circuit that stores and manipulates 4 bits of data in a serial
    fashion.

    Components:

    Flip-Flops: The core component is four D flip-flops connected in a cascade. Each DFF stores a
    single bit of data.
    Serial Input (SI): This is a single-bit input where new data is entered into the register.
    Serial Output (SO): This is a single-bit output that provides the data that has been shifted out of
    the register.
    Clock (Clk): This is a control signal that synchronizes the movement of data within the register.

    Schematic design:

    1. D Flip-Flop:
    Symbol

    2. 4-bit SISO Shift Register:


    Simulation outputs:

    1. D Flip-Flop

    2. 4- bit SISO Shift Register


    3. Delay for D-Flip Flop:

    4. Delay for 4-bit SISO Shift Register:


    5. Average Power for D Flip-Flop:

    6. Average Power for 4-bit SISO Shift Register:


    Inferences:

    As a result, a CMOS logic implementation is used to build a D Flip-Flop, and a


    symbol is made for it.
    • Using the symbol produced for D-Flip Flop, a 4-bit SISO shift register was
    developed.
    Verification of the truth table and transient analysis have confirmed the
    operation of both circuits.
    • A performance analysis has been completed regarding average power and
    delay.
    o The D Flip-Flop has a 50.13 E^-9 delay.
    o The 4-bit SISO Shift Register's delay is 350.1 E^-9
    o The D Flip-Flop's average power is 2.726 E^-6.
    o The 4-bit SISO Shift Register's Average Power: 7.312 E^-6
    ●

    You might also like