Ts 5 MP 646

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TS5MP646
SCDS371E – JANUARY 2018 – REVISED APRIL 2019
TS5MP646 4 Data Lane 2:1 MIPI Switch (10-Channel, 2:1 Analog Switch)
1 Features 3 Description
•
1 Supply Range of 1.65 V to 5.5 V The TS5MP646 is a four data lane MIPI switch. This
device is an optimized 10-channel (5 differential)
• 10-Channel 2:1 Switch single-pole, double-throw switch for use in high speed
• Powered-Off Protection: applications. The TS5MP646 is designed to facilitate
I/Os Hi-Z when VDD = 0 V multiple MIPI compliant devices to connect to a single
• Low RON of 4.2-Ω Typical CSI/DSI, C-PHY/D-PHY module.
• Bandwidth of 3 GHz The device has a bandwidth of 3 GHz, low channel-
• Ultra Low Crosstalk of -40 dB to-channel skew with little signal degradation, and
wide margins to compensate for layout losses. The
• Low Power Disable Mode device's low current consumption meets the needs of
• 1.8-V Compatible Logic Inputs low power applications, including mobile phones and
• ESD Protection Exceeds JESD 22 other personal electronics.
– 2000-V Human Body Model (HBM)
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications
TS5MP646 DSBGA (YFP) 2.42 mm x 2.42 mm
• Mobile Phones
(1) For all available packages, see the orderable addendum at
• Tablet the end of the data sheet.
• PC/Notebook
• Virtual and Augmented Reality
• Drones
• Camera-based carcode scanner
• Medical
• IP Netcam
Simplified C-PHY Schematic
Simplified D-PHY Schematic
1.65 V ± 5.5 V
1.65 V ± 5.5 V
100 nF 2.2 µF
100 nF 2.2 µF
VDD
VDD Trio[1:3]
CLK
Data[1:4] CLK MIPI Module 1 Trio[1:3]
MIPI Module 1 50 Ÿ
Data[1:4] TS5MP646
TS5MP646 Processor
Processor Trio [1:3] MIPI Switch
CLK MIPI Switch 50 Ÿ
Data[1:4] MIPI Module 2

MIPI Module 2 SEL
SEL 50 Ÿ
/OE
/OE
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TS5MP646
SCDS371E – JANUARY 2018 – REVISED APRIL 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 19
2 Applications ........................................................... 1 9 Application and Implementation ........................ 20
3 Description ............................................................. 1 9.1 Application Information............................................ 20
4 Revision History..................................................... 2 9.2 Typical Application ................................................. 20
5 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 27
6 Specifications......................................................... 4 11 Layout................................................................... 28
6.1 Absolute Maximum Ratings ...................................... 4 11.1 Layout Guidelines ................................................. 28
6.2 ESD Ratings.............................................................. 4 11.2 Layout Example .................................................... 28
6.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 29
6.4 Thermal Information .................................................. 5 12.1 Documentation Support ....................................... 29
6.5 Electrical Characteristics........................................... 5 12.2 Receiving Notification of Documentation Updates 29
6.6 Typical Characteristics .............................................. 9 12.3 Community Resources.......................................... 29
7 Parameter Measurement Information ................ 10 12.4 Trademarks ........................................................... 29
12.5 Electrostatic Discharge Caution ............................ 29
8 Detailed Description ............................................ 16
12.6 Glossary ................................................................ 29
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 17
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2019) to Revision E Page
• Added min differential bandwidth specification 2.7 GHz ........................................................................................................ 8

• Changed typ differential bandwith specification to 4.1 GHz ................................................................................................... 8
Changes from Revision C (August 2018) to Revision D Page
• Added the Simplified D-PHY and C-PHY Schematic ............................................................................................................. 1

• Added the Typical D-PHY and C-PHY Application circuits .................................................................................................. 20
• Added Eye diagrams to the Application Curves section....................................................................................................... 22
• Added the MIPI D-PHY Application section ......................................................................................................................... 23
• Added the MIPI C-PHY Application section ......................................................................................................................... 25
Changes from Revision B (July 2018) to Revision C Page
• Changed the Applications list ................................................................................................................................................. 1
Changes from Revision A (March 2018) to Revision B Page
Changes from Original (January 2018) to Revision A Page
• Changed the BODY SIZE (NOM) in the Device Information table From: 2.459 x 2.459 To: 2.42 x 2.42 .............................. 1
2 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: TS5MP646

TS5MP646
www.ti.com SCDS371E – JANUARY 2018 – REVISED APRIL 2019
5 Pin Configuration and Functions
DSBGA Package
36 Pin (YFP)
Top View
1 2 3 4 5 6
A VDD GND DA4N DA4P OE SEL
B DB4N DB4P DA3N DA3P D4N D4P
C DB3N DB3P NC NC D3N D3P
D DB2N DB2P DA2N DA2P D2N D2P
E DB1N DB1P DA1N DA1P D1N D1P
F CLKBN CLKBP CLKAN CLKAP CLKN CLKP
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
VDD A1 PWR Power supply input
GND A2 GND Device Ground
DA4N A3 I/O Differential I/O
DA4P A4 I/O Differential I/O
OE A5 I Output enable (Active Low)
SEL A6 I Channel Select
DB4N B1 I/O Differential I/O
DB4P B2 I/O Differential I/O
DA3N B3 I/O Differential I/O
DA3P B4 I/O Differential I/O
D4N B5 I/O Differential I/O
D4P B6 I/O Differential I/O
DB3N C1 I/O Differential I/O
DB3P C2 I/O Differential I/O
NC C3 - No connect
NC C4 - No connect
D3N C5 I/O Differential I/O
D3P C6 I/O Differential I/O
DB2N D1 I/O Differential I/O
DB2P D2 I/O Differential I/O
DA2N D3 I/O Differential I/O
Copyright © 2018–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

TS5MP646
Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NO.
DA2P D4 I/O Differential I/O
D2N D5 I/O Differential I/O
D2P D6 I/O Differential I/O
DB1N E1 I/O Differential I/O
DB1P E2 I/O Differential I/O
DA1N E3 I/O Differential I/O
DA1P E4 I/O Differential I/O
D1N E5 I/O Differential I/O
D1P E6 I/O Differential I/O
CLKBN F1 I/O Differential I/O
CLKBP F2 I/O Differential I/O
CLKAN F3 I/O Differential I/O
CLKAP F4 I/O Differential I/O
CLKN F5 I/O Differential I/O
CLKP F6 I/O Differential I/O
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD Supply Voltage -0.5 6 V
Analog voltage range (DxN, CLKN, DxP, CLKP, DAxN, CLKAN,
VI/O -0.5 4 V
DAxP, CLKAP, DBxN, CLKBN, DBxP, CLKBP)
VSEL, VOE Digital Input Voltage (SEL, /OE) -0.5 6 V
TJ Junction temperature -65 150 °C
Tstg Storage temperature -65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±250
specification JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ± WWW V and/or ± XXX V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ± YYY V and/or ± ZZZ V may actually have higher performance.

TS5MP646
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply Voltage 1.65 5.5 V
Analog voltage range (DxN, CLKN, DxP, CLKP, DAxN, CLKAN, DAxP,
VI/O 0 3.6 V
CLKAP, DBxN, CLKBN, DBxP, CLKBP)
V(SEL)
Digital Input Voltage 0 5.5 V
V(OE)
II/O Continuous I/O current -35 35 mA
TA Operating ambient temperature -40 85 °C
TJ Junction temperature -65 150 °C
6.4 Thermal Information

TS5MP646
THERMAL METRIC (1) YFP UNIT
36
RθJA Junction-to-ambient thermal resistance 57.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.3 °C/W
RθJB Junction-to-board thermal resistance 12.6 °C/W
ΨJT Junction-to-top characterization parameter 0.2 °C/W
ΨJB Junction-to-board characterization parameter 12.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VDD = 1.65 V to 5.5 V
OE = 0 V
IDD VDD Active Supply Current 0 30 60 µA
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
VDD = 1.65 V to 5.5 V
OE = VDD
IDD_PD Power-down Supply current 0 0.1 1 µA
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
VDD = 1.65 V to 5.5 V
IDD_PD_1. OE = 1.8 V
Power-down Supply current 0 0.1 10 µA
8 SEL = 0 V to 5.5 V
Dn, CLKn = 0 V
DC CHARACTERISTICS
VDD = 1.65 V to 5.5 V
OE = 0 V
RON_HS On-state resistance Dn, CLKn = -8 mA, 0.2 V 6 9 Ω
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8
mA
VDD = 1.65 V to 5.5 V
OE = 0 V
RON_LP On-state resistance Dn, CLKn = -8 mA, 1.2 V 6 10 Ω
mA

TS5MP646
Electrical Characteristics (continued)

VDD = 1.65 V to 5.5 V
OE = 0 V
RON_flat_
On-state resistance flatness Dn, CLKn = -8 mA, 0 V to 0.3 V 0.1 Ω
HS
DAn, DBn, CLKAn, CLKBn = 0 V to 0.3
V, -8 mA
VDD = 1.65 V to 5.5 V
OE = 0 V
RON_flat_L
On-state resistance flatness Dn, CLKn = -8 mA, 0 V to 1.3 V 0.9 Ω
P
V, -8 mA
VDD = 1.65 V to 5.5 V
OE = 0 V
On-state resistance match between+and
DRON_HS Dn, CLKn = -8 mA, 0.2 V 0.1 Ω
- paths
mA
VDD = 1.65 V to 5.5 V
OE = 0 V
On-state resistance match between+and
DRON_LP Dn, CLKn = -8 mA, 1.3 V 0.1 Ω
- paths
mA
VDD = 1.65 V to 5.5 V
OE = 0 V to 5.5 V
SEL = 0 V to 5.5 V
IOFF Switch off leakage current -0.5 0.5 µA
Dn, CLKn = 0 V to 1.3 V
V
VDD = 0V1.5V,1.65V,3.3V,5.5V
/OE = 0V,1.5V,1.65V,3.3V,5.5V
IOFF_3_6 Switch off leakage current SEL= 0V,1.5V,1.65V,3.3V,5.5V -10 10 µA
DX,CLKX = 3.6V
DAX,DBx,CLKAX,CLKBX = 3.6V
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V to 5.5 V
ION Switch on leakage current -0.5 0.5 µA
Dn, CLKn = 0 V to 1.3 V
V
VDD = 1.5V,1.65V,3.3V,5.5V
/OE = 0V
ION_3_6 Switch on leakage current SEL= 0V,1.5V,1.65V,3.3V,5.5V -50 50 µA
DX,CLKX = 3.6V
DAX,DBx,CLKAX,CLKBX = 3.6V
DYNAMIC CHARACTERISTICS
VDD = 1.65 V to 5.5 V
OE = 0 V
tSWITCH Switching time between channels Dn, CLKn = 0.6 V 1.5 µs
DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
VDD = 1.5V,1.65V,3.3V,5.5V
/OE = 0V
tSWITCH_ Switching time between channels by
DX, CLKX = 0.6 V 50 µs
CP charge pump
DAX, DBX, CLKAX, CLKBX:
RL=50Ω,CL=5pF
VDD = 1.65 V to 5.5 V
Maximum toggling frequency for the SEL Dn, CLKn = 0.6 V
fSEL_MAX 100 kHz
line DAn, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF

TS5MP646

VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
tON_OE Device turnon-time OE to switch on 50 300 µs
CL = 1 pF
VDD = 0 V to 5.5 V
Dn, CLKn = 0.6 V
tON_VDD Device turnon-time VDD to switch on 50 300 µs
CL = 1 pF
VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
tOFF_OE Device turnoff time OE to switch off 0.5 1 µs
CL = 1 pF
VDD = 5 V to 0 V
VDD ramp rate = 250 µs
tOFF_VDD Device turnoff time VDD to switch off Dn, CLKn = 0.6 V 0.5 1 ms
CL = 1 pF
VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
tMIN_/OE Minimum pulse width for OE 500 ns
CL = 1 pF
VDD = 1.65 V to 5.5 V
OE = 0 V
tBBM Break before make time 50 ns
Dn, CLKn = RL = 50 Ω, CL = 1 pF
DAn, DBn, CLKAn, CLKBn: 0.6 V
VDD = 1.65 V to 5.5 V
OE = 0 V
tSKEW Intrapair skew Dn, CLKn = 0.3 V 1 ps
DnX, DBn, CLKAn, CLKBn: RL = 50 Ω,
CL = 1 pF
VDD = 1.65 V to 5.5 V
OE = 0 V
tSKEW Interpair Skew Dn, CLKn = 0.3 V 4 ps
CL = 1 pF
VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
tPD Propagation delay with 100 ps rise time 40 ps
CL = 1 pF
tRISE = 100 ps
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
OISO Differential off isolation Dn, CLKn, DAn, DBn, CLKAn, CLKBn: -20 dB
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 1250 MHz
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
XTALK Differential channel to channel crosstalk Dn, CLKn, DAn, DBn, CLKAn, CLKBn: -40 dB
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
f = 1250 MHz

TS5MP646

VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Differential Bandwidth
BW Dn, CLKn, DAn, DBn, CLKAn, CLKBn: 2.7 4.1 GHz
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
f = 1250 MHz
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
ILOSS Insertion Loss Dn, CLKn, DAn, DBn, CLKAn, CLKBn: -0.65 dB
RS = 50 Ω, RL = 50 Ω, CL = 1 pF
f = 100 kHz
VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
COFF Off capacitance 1.5 pF
Dn, CLKn, DAn, DBn, CLKAn, CLKBn =
0 V, 0.2 V
f = 1250 MHz
VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
CON On capacitance 1.5 pF
Dn, CLKn, DAn, DBn, CLKAn, CLKBn =
0 V, 0.2 V
f = 1250 MHz
DIGITAL CHARACTERISTICS
VIH Input logic high (SEL, OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF 1.425 5.5 V
VIL Input logic low (SEL, /OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF 0 0.5 V
IIH Input high leakage current (SEL, /OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF -5 5 µA
IIL Input low leakage current (SEL, /OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF -5 5 µA
Internal pull-down resistance on digital
RPD VI/O = 0.6 V RL = 50 Ω, CL = 5 pF 6 MΩ
input pins
CI Digital Input capacitance (SEL, /OE) f = 1 MHz 5 pF

TS5MP646
6.6 Typical Characteristics
7 7
RON (-40°C) RON (-40°C)
6.5 RON (25°C) 6.5 RON (25°C)
RON (85°C) RON (85°C)
6 6
5.5 5.5
RON (:)
RON (:)
5 5
4.5 4.5
4 4
3.5 3.5
3 3
0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4
Input Voltage (V) D001
Figure 1. RON vs Input Voltage. VDD = 1.65 V Figure 2. RON vs Input Voltage. VDD = 3.3 V
7 0
RON (-40°C)
-1
6.5 RON (25°C)
RON (85°C) -2
6 -0.33 dB
-3
-4
5.5
Gain (dB)
-5
RON (:)
-3.32 dB
5 -6
-7
4.5
-8
4 -9
-10
3.5
-11 Bandwidth
3 -12
0 0.2 0.4 0.6 0.8 1 1.2 1.4 300000 1E+7 1E+8 1E+9 1E+10
Frequency (Hz) D004
Figure 3. RON vs Input Voltage. VDD = 5.5 V Figure 4. Differential Bandwidth

0 0
-20
-20
-40
-40
Gain (dB)
Gain (dB)
-60
-80
-60
-100
-80
-120
Off Isolation Crosstalk
-100 -140
100000 1000000 1E+7 1E+8 1E+9 1E+10 200000 1000000 1E+7 1E+8 1E+9 1E+10
Frequency (Hz) D005
Frequency (Hz) D006
Figure 5. Off Isolation Figure 6. Differential Crosstalk

TS5MP646
7 Parameter Measurement Information

Channel ON
V
RON = V/ION
VI/O
Switch ION
Copyright © 2018, Texas Instruments Incorporated
Figure 7. On Resistance
VI/O VI/O
A A
Switch
Figure 8. Off Leakage
VI/O
A
Switch
Figure 9. On Leakage
VI/OA
VI/O
VI/OB CL RL
SEL
CL RL
VSEL
1.8 V 1.8 V
VSEL VIL VIH VSEL VIH VIL
0V 0V
tSWITCH tSWITCH tSWITCH tSWITCH
80 VI/O VI/O
VI/OA % VI/OB 80 %
20 % 20 %
0V 0V
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 3 ns,
tf = 3 ns.
(2) CL includes probe and jig capacitance.
Figure 10. tSWITCH Timing

TS5MP646
Parameter Measurement Information (continued)

1.65 V
VDD
VI/O VI/O 1.8 V
V/OE VIL VIH
CL RL 0V
/OE
tON tOFF
VI/O
V/OE VI/O 90 % 10 %
0V
tf = 3 ns.
Figure 11. tON and tOFF Timing for OE
Network Analyzer Switch
50
DXP
50
Source
Signal
50
DXN
50
Source
Signal
50
50
Figure 12. Off Isolation

TS5MP646

50 DXP
50
Source
Signal
50
50 DXN
50
Source
Signal
50
DXP
50
50
50
DXN
50
50
50
Figure 13. Crosstalk
50 DXN
50
Source
Signal
50 DXP
50
Source
Signal
50
50
Figure 14. Bandwidth and Insertion Loss

TS5MP646

Generator Switch
50 D1P
DX1P 50
Source 50
Signal
50 D1N
DX1N
50
Source 50
Signal
50 D2P
DX2P 50
Source 50
Signal
50 D2N
DX2N
50
Source 50
Signal
50 D3P
DX3P 50
Source 50
Signal
50 D3N
DX3N
50
Source 50
Signal
50 D4P
DX4P 50
Source 50
Signal
50 D4N
DX4N
50
Source 50
Signal
50 CLKP
CLKXP 50
Source 50
Signal
50 CLKN
CLKXN
50
Source 50
Signal
Figure 15. tPD, tSKEW(INTRA) and tSKEW(INTER) Setup

TS5MP646
DXX/CLKX 50% 50%
tPD tPD
DXXX/CLKXX 50% 50%
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr = 100
ps, tf = 100 ps.
Figure 16. tPD
DXX/CLKX 50% 50%
tSKEW tSKEW
DXXX/CLKXX 50% 50%
ps, tf = 100 ps.
Figure 17. tSKEW(INTRA)

TS5MP646

tSKEW
DX/CLKX
tSKEW tSKEW
DX1 50% 50%
DX2 50% 50%
DX3 50% 50%
DX4 50% 50%
CLK 50% 50%
ps, tf = 100 ps.
(3) tSKEW is the max skew between all channels. Diagram exaggerates tSKEW to show measurement technique
Figure 18. tSKEW(INTER)
0.6 V
VI/O
VSEL
CL RL
SEL
0.6 V
80 %
VI/O
VSEL
tBBM tBBM
tf = 3 ns.
Figure 19. tBBM

TS5MP646
8 Detailed Description
8.1 Overview
The TS5MP646 is a high-speed 4 data lane 2:1 MIPI Switch. The device includes 10 channels (5 differential)
with 4 differential data lanes and 1 differential clock lane for D-PHY, CSI or DSI. The switch allows a single MIPI
port to interface between two MIPI modules, expanding the number of potential MIPI devices that can be used
within a system that is MIPI port limited.
8.2 Functional Block Diagram
VDD
SEL
6 MO Control
Logic
/OE
6 MO
CLKAP
CLKP
CLKBP
CLKAN
CLKN
CLKBN
DA1P
D1P
DB1P
DA1N
D1N
DB1N
DA2P
D2P
DB2P
DA2N
D2N
DB2N
DA3P
D3P
DB3P
DA3N
D3N
DB3N
DA4P
D4P
DB4P
DA4N
D4N
DB4N
GND

TS5MP646
8.3 Feature Description

8.3.1 Powered-Off Protection
When the TS5MP646 is powered off (VDD = 0 V) the I/Os and digital logic pins of the device remains in a high
impedance state. The crosstalk, off-isolation, and leakage will remain within the electrical specifications. This
prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
Figure 20 shows an example system containing a switch without powered-off protection with the following system
level scenario.
1. Subsystem A powers up and starts sending information to Subsystem B that remains unpowered.
2. The I/O voltage back powers the supply rail in Subsystem B.
3. The digital logic is back powered and turns on the switch. The signal is transmitted to Subsystem B before it
is powered and damages it.
Powered Unpowered
LDO
2
VDD
1 ESD
Subsystem A SEL Subsystem B
Switch 3
Figure 20. System Without Powered-Off Protection
With powered-off protection, the switch prevents back powering the supply and the switch remains high-
impedance. Subsystem B remains protected.
Powered Unpowered
LDO
VDD
Protection
ESD
Subsystem A SEL Subsystem B
Hi-Z
Switch
Figure 21. System With Powered-Off Protection
This features has the following system level benefits.

• Protects the system from damage.
• Prevents data from being transmitted unintentionally
• Eliminates the need for power sequencing solutions reducing BOM count and cost, simplifying system design
and improving reliability.

TS5MP646
Feature Description (continued)

8.3.2 1.8-V Logic Compatible Inputs
The TS5MP646 has 1.8-V logic compatible digital inputs for switch control. Regardless of the VDD voltage the
digital input thresholds remained fixed, allowing a 1.8-V processor GPIO to control the TS5MP646 without the
need for an external translator. This saves both space and BOM cost.
An example setup for a system without a 1.8-V logic compatible input is shown in Figure 22. Here the supply
mismatch between the process and its GPIO output and the supply to the switch require a translator.
3.3 V
1.8 V
Processor VDD
1.8 V SEL
GPIO
Switch
Figure 22. System Without 1.8 V Logic Compatible Inputs
With the 1.8 V logic compatibility in the TS5MP646, the translator is built in to the device so that the external
components are no longer needed, simplifying the system design and overall cost.
3.3 V
1.8 V
Processor VDD
1.8 V
GPIO
SEL
Switch
Figure 23. System With 1.8 V Logic Compatible Inputs
8.3.3 Low Power Disable Mode

The TS5MP646 has a low power mode that places all the signal paths in a high impedance state and lowers the
current consumption while the device is not in use. To put the device in low power mode and disable the switch,
the output enable pin OE must be supplied with a logic high signal.

TS5MP646
8.4 Device Functional Modes

8.4.1 Pin Functions
The SEL and OE pins have a weak 6-MΩ pull-down to prevent floating input logic.
Table 1. Function Table

OE SEL Function
H X I/O pins High-Impedance
CLK(P/N) = CLKA(P/N)
L L
Dn(P/N) = DAn(P/N)
CLK(P/N) = CLKB(P/N)
L H
Dn(P/N) = DBn(P/N)
8.4.2 Low Power Disable Mode

While the output enable pin OE is supplied with a logic high, the device remains in low power disabled state. This
reduces the current consumption substantially and the switches are high impedance. The SEL pin is ignored
while the OE remains high. Upon exiting low power mode, the switch status reflects the SEL pin as seen in
Table 1.
8.4.3 Switch Enabled Mode

While the output enable pin OE is supplied with a logic low, the device remains in switch enabled mode.

TS5MP646
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application

Figure 24 represents a typical application of the TS5MP646 MIPI switch. The TS5MP646 is used to switch
signals between multiple MIPI modules and a single MIPI port on a processor. This expands the capabilities of a
single port to handle multiple MIPI modules.
1.65 V ± 5.5 V
100 nF 2.2 µF
VDD
CLK
Data[1:4] CLK
MIPI Module 1
Data[1:4]
TS5MP646
Processor
CLK MIPI Switch
Data[1:4]
MIPI Module 2 SEL
/OE
Figure 24. Typical D-PHY Application

TS5MP646
Typical Application (continued)
1.65 V ± 5.5 V
100 nF 2.2 µF
VDD
Trio[1:3]
MIPI Module 1 Trio[1:3]

50 Ÿ
TS5MP646
Processor
Trio [1:3] MIPI Switch
50 Ÿ
MIPI Module 2 SEL

50 Ÿ
/OE
Figure 25. Typical C-PHY Application
9.2.1 Design Requirements

Design requirements of the MIPI standard must be followed. Supply pin decoupling capacitors of 2.2 µF and 100
nF are recommended for best performance. The TS5MP646 has internal 6-MΩ pulldown resistors on SEL and
OE. The pulldown on these pins ensure that the digital remains in a non-floating state during system power-up to
prevent shoot through current spikes and an unknown switch status. By default the switch will power up enabled
and with the A path selected until driven externally by the processor.
9.2.2 Detailed Design Procedure

The TS5MP646 can be properly operated without any external components. However, TI recommends that
unused I/O signal pins be connected to ground through a 50 Ω resistor to prevent signal reflections and maintain
device performance. The NC pins of the device do not require any external connections or terminations and have
no connection to the rest of the device internally.
The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the
application. For example, the clock can be placed on the D1 channel and a data lane can be used on the CLK
channel if this improves the layout. In addition, the signal lines of the TS5MP646 are routed single ended on the
chip die. This makes the device suitable for both differential and single-ended high-speed systems.

TS5MP646

9.2.3 Application Curves
0
-1
-2
-0.33 dB
-3
-4
Gain (dB)
-5
-3.32 dB
-6
-7
-8
-9
-10
-11 Bandwidth
-12
300000 1E+7 1E+8 1E+9 1E+10
Frequency (Hz) D004
Figure 26. Differential Bandwidth
Figure 27. 2.5 Gbps with Signal Switch Figure 28. 2.5 Gbps Through Path

TS5MP646

9.2.3.1 MIPI D-PHY Application
application. In addition, the signal lines of the TS5MP646 are routed single ended on the chip die. This makes
the device suitable for both differential and single-ended high-speed systems. This also allows the positive and
negative lines to be interchanged as necessary to facilitate the best layout possible for the application.
D-PHY application includes a differential clock and 4 differential datalanes. All the channels of the device perform
similar and the clock or data signals may be interchanged as necessary to facilitate the best layout possible for
the application.

TS5MP646
VDD
SEL D-PHY
6M Module A
Control
Log ic
/OE D-PHY
Module B
6M
CLKAP MIP I_CSI_CLKP_Module A

MIP I_CSI_CLKP CLKP
CLKBP MIP I_CSI_CLKP_Module B
+/- Clock CLKAN MIP I_CSI_CLKN_Module A

MIP I_CSI_CLKN CLKN
CLKBN MIP I_CSI_CLKN_Module B
DA1P MIP I_CSI_DATA1P_Module A

MIP I_CSI_DATA1P D1P
DB1P MIP I_CSI_DATA1P_Module B
+/- DATA1 DA1N MIP I_CSI_DATA1N_Module A

MIP I_CSI_DATA1N D1N
DB1N MIP I_CSI_DATA1N_Module B



MIP I_CSI_DATA3N_Module A
+/- DATA3 DA3N


GND
Figure 29. MIPI D-PHY Example Pinout

TS5MP646

9.2.3.2 MIPI C-PHY Application
application. In addition, the signal lines of the TS5MP646 are routed single ended on the chip die. This
makes the device suitable for both differential and single-ended high-speed systems. This also allows the
positive and negative lines to be interchanged as necessary to facilitate the best layout possible for the
application.
C-PHY application includes 3 trios of signals which may be routed on any channel which means there will be
one unused channel on the TS5MP646. TI recommends that the unused I/O signal pin be connected to
ground through a 50 Ω resistor to prevent signal reflections and maintain device performance.

TS5MP646
VDD
SEL C-PHY
6M Module A
Control
Log ic
/OE C-PHY
Module B
6M
CLKAP MIP I_CSI_A0_Module A

MIP I_CSI_A0 CLKP
CLKBP MIP I_CSI_A0_Module B
CLKAN MIP I_CSI_B0_Module A

MIP I_CSI_B0 CLKN
Trio 0 CLKBN MIP I_CSI_B0_Module B
DA1P MIP I_CSI_C0_Module A

MIP I_CSI_C0 D1P
DB1P MIP I_CSI_C0_Module B
DA1N MIP I_CSI_A1_Module A

MIP I_CSI_A1 D1N
DB1N MIP I_CSI_A1_Module B
DA2P MIP I_CSI_B1_Module A

MIP I_CSI_B1 D2P
Trio 1 DB2P MIP I_CSI_B1_Module B
DA2N MIP I_CSI_C1_Module A

MIP I_CSI_C1 D2N
DB2N MIP I_CSI_C1_Module B
DA3P MIP I_CSI_A2_Module A

MIP I_CSI_A2 D3P
DB3P MIP I_CSI_A2_Module B
DA3N MIP I_CSI_B2_Module A
MIP I_CSI_B2 D3N

Trio 2 DB3N MIP I_CSI_B2_Module B
DA4P MIP I_CSI_C2_Module A
MIP I_CSI_C2 D4P

DB4P MIP I_CSI_C2_Module B
50 Ÿ
50 DA4N
D4N
DB4N
GND
50 Ÿ
GND
Figure 30. MIPI C-PHY Example Pinout

TS5MP646
10 Power Supply Recommendations

When the TS5MP646 is powered off (VDD = 0 V), the I/Os of the device remains in a high-Z state. The crosstalk,
off-isolation, and leakage remain within the electrical Specifications. Power to the device is supplied through the
VDD pin. Decoupling capacitors of 100 nF and 2.2 µF are recommended on the supply.

TS5MP646
11 Layout
11.1 Layout Guidelines

Place the supply de-coupling capacitors as close to the VDD and GND pin as possible. The spacing between the
power traces, supply and ground, and the signal I/O lines, clock and data, should be a minimum of three times
the race width of the signal I/O lines to maintain signal integrity.
The characteristic impedance of the trace(s) must match that of the receiver and transmitter to maintain signal
integrity. Route the high-speed traces using a minimum amount of vias and corners. This will reduce the amount
of impedance changes.
When it becomes necessary to make the traces turn 90°, use two 45° turns or an arc instead of making a single
90° turn.
Do not route high-speed traces near crystals, oscillators, external clock signals, switching regulators, mounting
holes or magnetic devices.
Avoid stubs on the signal lines.
All I/O signal traces should be routed over a continuous ground plane with no interruptions. The minimum width
from the edge of the trace to any break in the ground plane must be 3 times the trace width. When routing on
PCB inner signal layers, the high speed traces should be between two ground planes and maintain characteristic
impedance.
High speed signal traces must be length matched as much as possible to minimize skew between data and clock
lines.
11.2 Layout Example

Top Layer Routing
Bottom Layer Routing
VIA to VIA to
power plane ground plane Via
C
To Control
C Logic
DA4 DA4
VDD GND /OE SEL
N P
DB4 DB4 DA3 DA3

D4N D4P
N P N P
To MIPI DB3 DB3

N P
NC NC D3N D3P
To MIPI Port
Modules
DB2 DB2 DA2 DA2
D2N D2P
N P N P
DB1 DB1 DA1 DA1

D1N D1P
N P N P
CLK CLK CLK CLK CLK CLK

BN BP AN AP N P
Figure 31. Layout Example

TS5MP646
12 Device and Documentation Support
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 7-Jan-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TS5MP646YFPR NRND DSBGA YFP 36 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TS5MP646
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS5MP646YFPR DSBGA YFP 36 3000 330.0 12.4 2.58 2.58 0.62 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS5MP646YFPR DSBGA YFP 36 3000 335.0 335.0 25.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFP0036 SCALE 4.700
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
C
0.5 MAX
SEATING PLANE
0.19 BALL TYP

0.05 C
0.13
2 TYP
SYMM
E
D: Max = 2.45 mm, Min = 2.39 mm
D SYMM
2 E: Max = 2.45 mm, Min = 2.39 mm
TYP C
B
0.25
36X
0.21
A 0.015 C A B
0.4 TYP 1 2 3 4 5 6
0.4 TYP
4222013/A 04/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFP0036 DSBGA - 0.5 mm max height
36X ( 0.23) (0.4) TYP

1 2 3 4 5 6
A
(0.4) TYP
C
SYMM
SYMM
LAND PATTERN EXAMPLE

SCALE:25X
( 0.23) 0.05 MAX 0.05 MIN METAL UNDER

METAL SOLDER MASK
SOLDER MASK ( 0.23)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

NOT TO SCALE
4222013/A 04/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0036 DSBGA - 0.5 mm max height
(0.4) TYP
(R0.05) TYP
36X ( 0.25)
1 2 3 4 5 6
A
(0.4) TYP
B
METAL
TYP
C
SYMM
SYMM
SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222013/A 04/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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Data[1:4] MIPI Module 2

Changes from Revision D (January 2019) to Revision E Page

• Added min differential bandwidth specification 2.7 GHz ........................................................................................................ 8

Changes from Revision C (August 2018) to Revision D Page

• Added the Simplified D-PHY and C-PHY Schematic ............................................................................................................. 1

Changes from Revision B (July 2018) to Revision C Page

• Changed the Applications list ................................................................................................................................................. 1

Changes from Revision A (March 2018) to Revision B Page

Changes from Original (January 2018) to Revision A Page

2 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

Product Folder Links: TS5MP646

5 Pin Configuration and Functions

A VDD GND DA4N DA4P OE SEL

B DB4N DB4P DA3N DA3P D4N D4P

C DB3N DB3P NC NC D3N D3P

D DB2N DB2P DA2N DA2P D2N D2P

E DB1N DB1P DA1N DA1P D1N D1P

F CLKBN CLKBP CLKAN CLKAP CLKN CLKP

Copyright © 2018–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

Pin Functions (continued)

6.2 ESD Ratings

4 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

Product Folder Links: TS5MP646

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

Copyright © 2018–2019, Texas Instruments Incorporated Submit Documentation Feedback 5

Electrical Characteristics (continued)

6 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

Product Folder Links: TS5MP646

Electrical Characteristics (continued)

Copyright © 2018–2019, Texas Instruments Incorporated Submit Documentation Feedback 7

Electrical Characteristics (continued)

8 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

Product Folder Links: TS5MP646

6.6 Typical Characteristics

Figure 3. RON vs Input Voltage. VDD = 5.5 V Figure 4. Differential Bandwidth

Figure 5. Off Isolation Figure 6. Differential Crosstalk

Copyright © 2018–2019, Texas Instruments Incorporated Submit Documentation Feedback 9

7 Parameter Measurement Information

Copyright © 2018, Texas Instruments Incorporated

Figure 8. Off Leakage

Copyright © 2018, Texas Instruments Incorporated

Figure 10. tSWITCH Timing

10 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated

Product Folder Links: TS5MP646

Parameter Measurement Information (continued)

Copyright © 2018, Texas Instruments Incorporated

Figure 11. tON and tOFF Timing for OE

Network Analyzer Switch

Copyright © 2018, Texas Instruments Incorporated

Figure 12. Off Isolation

Copyright © 2018–2019, Texas Instruments Incorporated Submit Documentation Feedback 11

Parameter Measurement Information (continued)

Copyright © 2018, Texas Instruments Incorporated

Figure 13. Crosstalk

Network Analyzer Switch