CD 74 HC 4053

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CD54HC4051, CD74HC4051
CD54HCT4051, CD74HCT4051, CD54HC4052, CD74HC4052, CD54HCT4052
CD74HCT4052, CD54HC4053, CD74HC4053, CD54HCT4053, CD74HCT4053
SCHS122M – NOVEMBER 1997 – REVISED MAY 2019
CDx4HC405x, CDx4HCT405x High-Speed CMOS Logic Analog

Multiplexers and Demultiplexers
1 Features 3 Description
•
1 Wide Analog Input Voltage Range: ±5-V Maximum The CDx4HC405x and CDx4HCT405x devices are
digitally controlled analog switches that use silicon
• Low ON-Resistance gate CMOS technology to achieve operating speeds
– 70-Ω Typical (VCC – VEE = 4.5 V) similar to LSTTL with the low-power consumption of
– 40-Ω Typical (VCC – VEE = 9 V) standard CMOS integrated circuits.
• Low Crosstalk Between Switches These analog multiplexers and demultiplexers control
• Fast Switching and Propagation Speeds analog voltages that may vary across the voltage
supply range (for example, VCC to VEE). They are
• Break-Before-Make Switching
bidirectional switches that allow any analog input to
• Wide Operating Temperature Range: be used as an output and vice versa. The switches
–55°C to +125°C have low ON resistance and low OFF leakages. In
• CD54HC and CD74HC Types addition, all these devices have an enable control
that, when high, disables all switches to their OFF
– Operation Control Voltage: 2 V to 6 V
state.
– Switch Voltage: 0 V to 10 V
• CD54HCT and CD74HCT Types Device Information(1)
– Operation Control Voltage: 4.5 V to 5.5 V PART NUMBER PACKAGE BODY SIZE (NOM)
– Switch Voltage: 0 V to 10 V CD54HCx405xF CDIP (16) 19.56 mm × 6.92 mm

CD74HCx405xE PDIP (16) 19.30 mm × 6.35 mm
– Direct LSTTL Input Logic Compatibility
VIL = 0.8-V Max, VIH = 2-V Min CD74HCx405xM SOIC (16) 9.90 mm × 3.91 mm
CD74HCx405xNS SOP (16) 10.30 mm × 5.30 mm
– CMOS Input Compatibility
II ≤ 1 µA at VOL, VOH CD74HCx405xPW TSSOP (16) 5.00 mm × 4.40 mm
• On Products Compliant to MIL-PRF-38535, (1) For all available packages, see the orderable addendum at
the end of the data sheet.
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production Functional Diagram of HC4051 and HCT4051
Processing Does Not Necessarily Include Testing CHANNEL IN/OUT
of All Parameters. VCC A7 A6 A5 A4 A3 A2 A1 A0
16 4 2 5 1 12 15 14 13
2 Applications TG
TG
• Digital Radio S0 11
• Signal Gating TG
• Factory Automation S1 10
TG
A
BINARY 3 COMMON
• Televisions LOGIC
LEVEL
TO
1 OF 8 TG
OUT/IN
DECODER
CONVERSION
• Appliances S2 9
WITH
ENABLE
TG
• Programmable Logic Circuits

TG
• Sensors E 6
TG
8 7
GND VEE
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC4051, CD74HC4051
SCHS122M – NOVEMBER 1997 – REVISED MAY 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagrams ..................................... 20
2 Applications ........................................................... 1 8.3 Feature Description................................................. 22
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 22
4 Revision History..................................................... 2 9 Application and Implementation ........................ 23
9.1 Application Information............................................ 23
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 23
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6 10 Power Supply Recommendations ..................... 24
6.2 ESD Ratings ............................................................ 6 11 Layout................................................................... 25
6.3 Recommended Operating Conditions ...................... 6 11.1 Layout Guidelines ................................................. 25
6.4 Thermal Information .................................................. 7 11.2 Layout Example .................................................... 25
6.5 Electrical Characteristics: HC Devices...................... 7 12 Device and Documentation Support ................. 26
6.6 Electrical Characteristics: HCT Devices ................. 10 12.1 Documentation Support ........................................ 26
6.7 Switching Characteristics, VCC = 5 V...................... 12 12.2 Related Links ........................................................ 26
6.8 Switching Characteristics, CL = 50 pF .................... 13 12.3 Receiving Notification of Documentation Updates 26
6.9 Analog Channel Specifications ............................... 16 12.4 Community Resources.......................................... 26
6.10 Typical Characteristics .......................................... 17 12.5 Trademarks ........................................................... 26
7 Parameter Measurement Information ................ 18 12.6 Electrostatic Discharge Caution ............................ 26
12.7 Glossary ................................................................ 27
8 Detailed Description ............................................ 20
8.1 Overview ................................................................. 20 13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (February 2017) to Revision M Page
• Changed Feature From: 7-Ω Typical To: 70-Ω Typical ......................................................................................................... 1
Changes from Revision K (September 2015) to Revision L Page
• Changed Charged device model (CDM) value from: ±1000 V to: ±200 V ............................................................................. 6
• Added Receiving Notification of Documentation Updates section ...................................................................................... 26
Changes from Revision J (February 2011) to Revision K Page
• Removed Ordering Information table. .................................................................................................................................... 1

• Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Detailed
Description section, Applications and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
• Added Military Disclaimer to Features list. ............................................................................................................................. 1
2 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated
Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

CD54HCT4052 CD74HCT4052 CD54HC4053 CD74HC4053 CD54HCT4053 CD74HCT4053
CD54HC4051, CD74HC4051
www.ti.com SCHS122M – NOVEMBER 1997 – REVISED MAY 2019
5 Pin Configuration and Functions
CD54HC4051, CD54HCT4051, CD74HC4051, CD74HCT4051 J, N, D, NS, PW Packages

16-Pin CDIP, PDIP, SOIC, SO, TSSOP
Top View
CHANNEL A4 1 16 VCC
IN/OUT A6 2 15 A2
COM OUT/IN A 3 14 A1 CHANNEL

A7 4 13 A0 IN/OUT
CHANNEL
IN/OUT A5 5 12 A3
E 6 11 S0
VEE 7 10 S1 ADDRESS
SELECT
GND 8 9 S2
Pin Functions for CDx4HCx4051B

PIN
I/O DESCRIPTION
NO. NAME
1 CH A4 IN/OUT I/O Channel 4 in/out
3 COM OUT/IN I/O Common out/in
6 E I Enable Channels (Active Low). See Table 1.
7 VEE — Negative power input
8 GND — Ground
9 S2 I Channel select 2. See Table 1.
16 VCC — Positive power input
Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

CD54HC4051, CD74HC4051
CD54HC4052, CD74HC4052, CD74HCT4052 J, N, D, NS, PW Packages

16-Pin CDIP, PDIP, SOIC, SO, TSSOP
Top View
CHANNEL B0 1 16 VCC
IN/OUT B2 2 15 A2
CHANNEL
COM OUT/IN BN 3 14 A1 IN/OUT
CHANNEL B3 4 13 AN COM OUT/IN

IN/OUT B1 5 12 A0
CHANNEL
E 6 11 A3 IN/OUT
VEE 7 10 S0
GND 8 9 S1
Pin Functions for CDx4HCx4052B

PIN
I/O DESCRIPTION
NO. NAME
1 CH B0 IN/OUT I/O Channel B0 in/out
3 COM B OUT/IN I/O B common out/in
6 E I Enable channels (Active Low). See Table 2.
8 GND — Ground
11 CH A3 IN/OUT I/O Channel A3 in/out
13 COM A IN/OUT I/O A common out/in

CD54HC4051, CD74HC4051
CD54HC4053 CD74HC4053 CD74HCT4053 J, N, D, NS, PW Packages

16-Pin CDIP, PDIP, SOIC, SOP, TSSOP
TOP VIEW
B1 1 16 VCC
CHANNEL
B0 2 15 BN COM OUT/IN
IN/OUT
C1 3 14 AN COM OUT/IN
COM OUT/IN CN 4 13 A1
CHANNEL
IN/OUT C0 5 12 A0 IN/OUT
E 6 11 S0
VEE 7 10 S1
GND 8 9 S2
Pin Functions CDx4HCx4053B

PIN
I/O DESCRIPTION
NO. NAME
1 B1 IN/OUT I/O B channel Y in/out
2 B0 IN/OUT I/O B channel X in/out
3 C1 IN/OUT I/O C channel Y in/out
4 COM C OUT/IN I/O C common out/in
5 C0 IN/OUT I/O C channel X in/out
6 E I Enable channels (Active Low). See Table 3.
8 GND — Ground
12 A0 IN/OUT I/O A channel X in/out
13 A1 IN/OUT I/O A channel Y in/out
14 COM A OUT/IN I/O A common out/in
15 COM B OUT/IN I/O B common out/in

CD54HC4051, CD74HC4051
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC – VEE DC supply voltage –0.5 10.5 V
VCC DC supply voltage –0.5 7 V
VEE DC supply voltage 0.5 –7 V
IIK DC input diode current VI < – 0.5 V or VI > VCC + 0.5 V ±20 mA
IOK DC switch diode current VI < VEE – 0.5 V or VI > VCC + 0.5 V ±20 mA
DC switch current (2) VI > VEE – 0.5 V or VI < VCC + 0.5 V ±25 mA
ICC DC VCC or ground current ±50 mA
IEE DC VEE current –20 mA
TJMAX Maximum junction temperature 150 °C
TLMAX Maximum lead temperature Soldering 10 s 300 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to GND unless otherwise specified.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±500
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101 or V
±200
ANSI/ESDA/JEDEC JS-002 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
Supply voltage range CD54 and 74HC types 2 6
VCC (TA = full package temperature V
range) (2) CD54 and 74HCT types 4.5 5.5
VCC – Supply voltage range CD54 and 74HC types, CD54 and 74HCT
2 10 V
VEE (TA = full package temperature range) types (see Figure 1)
Supply voltage range
CD54 and 74HC types, CD54 and 74HCT
VEE (TA = full package temperature 0 –6 V
types (see Figure 2)
range) (3)
VI DC input control voltage GND VCC V
VIS Analog switch I/O voltage VEE VCC V
TA Operating temperature –55 125 °C
2V 0 1000
tr, tf Input rise and fall times 4.5 V 0 500 ns
6V 0 400
(1) For maximum reliability, nominal operating conditions must be selected so that operation is always within the ranges specified in the
Recommended Operating Conditions table.
(2) All voltages referenced to GND unless otherwise specified.
(3) In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC
current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed
0.6 V (calculated from rON values shown in Electrical Characteristics: HC Devices and Electrical Characteristics: HCT Devices tables).
No VCC current will flow through RL if the switch current flows into terminal 3 on the HC and HCT4051; terminals 3 and 13 on the HC
and HCT4052; terminals 4, 14, and 15 on the HC and HCT4053.

CD54HC4051, CD74HC4051
6.4 Thermal Information

CD74HC4051
THERMAL METRIC (1) N (PDIP) NS (SO) PW (TSSOP) UNIT
16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 49.0 83.0 107.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.3 41.2 42.4 °C/W
RθJB Junction-to-board thermal resistance 29.0 43.3 52.8 °C/W
ψJT Junction-to-top characterization parameter 21.2 9.2 4.2 °C/W
ψJB Junction-to-board characterization parameter 28.9 43.0 52.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: HC Devices

TEST CONDITIONS
PARAMETERS VIS VI VEE VCC MIN TYP MAX UNIT
TA
(V) (V) (V) (V)
25°C 1.5
–40°C to
1.5
2 +85°C
–55°C to
1.5
+125°C
25°C 3.15
–40°C to
3.15
VIH High-level input voltage 4.5 +85°C V
–55°C to
3.15
+125°C
25°C 4.2
–40°C to
4.2
6 +85°C
–55°C to
4.2
+125°C
25°C 0.5
–40°C to
0.5
2 +85°C
–55°C to
0.5
+125°C
25°C 1.35
–40°C to
1.35
VIL Low-level input voltage 4.5 +85°C V
–55°C to
1.35
+125°C
25°C 1.8
–40°C to
1.8
6 +85°C
–55°C to
1.8
+125°C

CD54HC4051, CD74HC4051
Electrical Characteristics: HC Devices (continued)

TEST CONDITIONS
TA
(V) (V) (V) (V)
25°C 70 160
–40°C to
200
0 4.5 +85°C
–55°C to
240
+125°C
25°C 60 140
–40°C to
175
VCC or VEE 0 6 +85°C
–55°C to
210
+125°C
25°C 40 120
–40°C to
150
–4.5 4.5 +85°C
–55°C to
VIL 180
ON IO = 1 mA +125°C
rON or Ω
resistance See Figure 21 25°C 90 180
VIH
–40°C to
225
0 4.5 +85°C
–55°C to
270
+125°C
25°C 80 160
–40°C to
200
VCC to VEE 0 6 +85°C
–55°C to
240
+125°C
25°C 45 130
–40°C to
162
–4.5 4.5 +85°C
–55°C to
195
+125°C
0 4.5 25°C 10
Maximum ON resistance
ΔrON 0 6 25°C 8.5 Ω
between any two channels
–4.5 4.5 25°C 5

CD54HC4051, CD74HC4051
Electrical Characteristics: HC Devices (continued)

TEST CONDITIONS
TA
(V) (V) (V) (V)
25°C ±0.1
–40°C to
1 and 2 ±1
0 6 +85°C
channels
–55°C to
±1
+125°C
25°C ±0.1
–40°C to
±1
4053 –5 5 +85°C
–55°C to
±1
+125°C
25°C ±0.1
For switch OFF: –40°C to
When VIS = VCC, ±1
4 channels 0 6 +85°C
VOS = VEE;
Switch When VIS = VEE, –55°C to
VIL ±1
ON/OFF VOS = VCC, +125°C
IIZ or µA
leakage For switch ON: 25°C ±0.2
VIH
current All applicable
combinations of –40°C to
±2
4052 VIS and VOS –5 5 +85°C
voltage levels –55°C to
±2
+125°C
25°C ±0.2
–40°C to
±2
–55°C to
±2
+125°C
25°C ±0.4
–40°C to
±4
4051 –5 5 +85°C
–55°C to
±4
+125°C
25°C ±0.1
VCC –40°C to
±1
IIL Control input leakage current or 0 6 +85°C µA
GND
–55°C to
±1
+125°C
25°C 8
–40°C to
When VIS = VEE, 80
0 6 +85°C
VOS = VCC
–55°C to
Quiescent VCC 160
+125°C
ICC device IO = 0 or µA
current GND 25°C 16
–40°C to
When VIS = VCC, 160
–5 5 +85°C
VOS = VEE
–55°C to
320
+125°C

CD54HC4051, CD74HC4051
6.6 Electrical Characteristics: HCT Devices

TEST CONDITIONS
PARAMETER VIS VI VEE VCC MIN TYP MAX UNIT
TA
(V) (V) (V) (V)
25°C 2
4.5 –40°C to
2
VIH High-level input voltage to +85°C V
5.5
–55°C to
2
+125°C
25°C 0.8
4.5 –40°C to
0.8
VIL Low-level input voltage to +85°C V
5.5
–55°C to
0.8
+125°C
25°C 70 160
–40°C to
200
0 4.5 +85°C
–55°C to
240
+125°C
VCC or VEE
25°C 40 120
–40°C to
150
–4.5 4.5 +85°C
–55°C to
VIL 180
IO = 1 mA +125°C
rON ON resistance or Ω
See Figure 6 25°C 90 180
VIH
–40°C to
225
0 4.5 +85°C
–55°C to
270
+125°C
VCC to VEE
25°C 45 130
–40°C to
162
–4.5 4.5 +85°C
–55°C to
195
+125°C
Maximum ON resistance 0 4.5 25°C 10

ΔrON Ω
between any two channels –4.5 4.5 25°C 5

CD54HC4051, CD74HC4051
Electrical Characteristics: HCT Devices (continued)

TEST CONDITIONS
PARAMETER VIS VI VEE VCC MIN TYP MAX UNIT
TA
(V) (V) (V) (V)
25°C ±0.1
–40°C to
1 and 2 ±1
0 6 +85°C
channels
–55°C to
±1
+125°C
25°C ±0.1
–40°C to
±1
4053 –5 5 +85°C
–55°C to
±1
+125°C
25°C ±0.1
For switch OFF: –40°C to
When VIS = VCC, ±1
VOS = VEE;
Switch When VIS = VEE, –55°C to
VIL ±1
ON/OFF VOS = VCC +125°C
IIZ or µA
leakage For switch ON: 25°C ±0.2
VIH
current All applicable
combinations of –40°C to
±2
4052 VIS and VOS –5 5 +85°C
voltage levels –55°C to
±2
+125°C
25°C ±0.2
–40°C to
±2
–55°C to
±2
+125°C
25°C ±0.4
–40°C to
±4
4051 –5 5 +85°C
–55°C to
±4
+125°C
25°C ±0.1
–40°C to
±1
IIL Control input leakage current See (1) 5.5 +85°C µA
–55°C to
±1
+125°C
25°C 8
–40°C to
When VIS = VEE, 80
0 5.5 +85°C µA
VOS = VCC
–55°C to
Quiescent VCC 160
+125°C
ICC device IO = 0 or
current GND 25°C 16
–40°C to
When VIS = VCC, 160
–4.5 5.5 +85°C µA
VOS = VEE
–55°C to
320
+125°C
25°C 100 360
Additional quiescent –40°C to
450
ΔICC device current per input pin: ΔICC (2) VCC – 2.1 4.5 to 5.5 +85°C µA
1 unit load (2)
–55°C to
490
+125°C
(1) Any voltage between VCC and GND.

(2) For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.

CD54HC4051, CD74HC4051
6.7 Switching Characteristics, VCC = 5 V

VCC = 5 V, TA = 25°C, input tr, tf = 6 ns
CL
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(pF)
CDx4HC4051 4
CDx4HCT4051 4
CDx4HC4052 4
tPHL, tPLH Switch IN to OUT 15 ns
CDx4HCT4052 4
CDx4HC4053 4
CDx4HCT4053 4
CDx4HC4051 19
CDx4HCT4051 19
CDx4HC4052 21
tPHZ, tPLZ Propagation delay Switch turn-off (S or E) 15 ns
CDx4HCT4052 21
CDx4HC4053 18
CDx4HCT4053 18
CDx4HC4051 19
CDx4HCT4051 23
CDx4HC4052 27
tPZH, tPZL Switch turn-on (S or E) 15 ns
CDx4HCT4052 29
CDx4HC4053 18
CDx4HCT4053 20
CDx4HC4051 50
CDx4HCT4051 52
Power dissipation CDx4HC4052 74
CPD pF
capacitance (1) CDx4HCT4052 76
CDx4HC4053 38
CDx4HCT4053 42
(1) CPD is used to determine the dynamic power consumption, per package. PD = CPD VCC2 fI + ∑ (CL + CS) VCC2 fO , fO = output frequency,
fI = input frequency, CL = output load capacitance, CS = switch capacitance, VCC = supply voltage

CD54HC4051, CD74HC4051
6.8 Switching Characteristics, CL = 50 pF

CL = 50 pF, input tr, tf = 6 ns
VEE VCC
PARAMETER TEST CONDITIONS MIN MAX UNIT
(V) (V)
TA = 25°C HC 60
0 2 TA = –40°C to +85°C HC 75
TA = –55°C to +125°C HC 90
TA = 25°C HC, HCT 12
0 4.5 TA = –40°C to +85°C HC, HCT 15
tPLH, Propagation delay, TA = –55°C to +125°C HC, HCT 18

ns
tPHL switch in to out TA = 25°C HC 10
0 6 TA = –40°C to +85°C HC 13
TA = –55°C to +125°C HC 15
–4.5 4.5 TA = –40°C to +85°C HC, HCT 10
TA = –55°C to +125°C HC, HCT 12
TA = 25°C HC 225
0 2 TA = –40°C to +85°C HC 280
TA = –55°C to +125°C HC 340
Maximum 0 4.5 TA = –40°C to +85°C HC, HCT 56

switch turn TA = –55°C to +125°C HC, HCT 68
tPHZ,
OFF delay 4051 ns
tPLZ TA = 25°C HC 38
from S or E
to switch output 0 6 TA = –40°C to +85°C HC 48
TA = –55°C to +125°C HC 57
–4.5 4.5 TA = –40°C to +85°C HC, HCT 40
TA = –55°C to +125°C HC, HCT 48
TA = 25°C HC 250
0 2 TA = –40°C to +85°C HC 315
TA = –55°C to +125°C HC 375
0 4.5 TA = –40°C to +85°C HC, HCT 63
TA = –55°C to +125°C HC, HCT 75
Maximum
TA = 25°C HC 43
switch turn
tPHZ,
OFF delay 4052 0 6 TA = –40°C to +85°C HC 54 ns
tPLZ
from S or E
TA = –55°C to +125°C HC 65
to switch output
HC 38
TA = 25°C
HCT 38
HC 48
–4.5 4.5 TA = –40°C to +85°C
HCT 48
HC 57
TA = –55°C to +125°C
HCT 57

CD54HC4051, CD74HC4051
Switching Characteristics, CL = 50 pF (continued)

VEE VCC
(V) (V)
TA = 25°C HC 210
0 2 TA = –40°C to +85°C HC 265
TA = –55°C to +125°C HC 315
HC 42
TA = 25°C
HCT 44
HC 53
0 4.5 TA = –40°C to +85°C
HCT 53
Maximum HC 63
TA = –55°C to +125°C
switch turn HCT 66
tPHZ,
OFF delay 4053 ns
tPLZ TA = 25°C HC 36
from S or E
TA = –55°C to +125°C HC 54
HC 29
TA = 25°C
HCT 31
HC 36
–4.5 4.5 TA = –40°C to +85°C
HCT 39
HC 44
TA = –55°C to +125°C
HCT 47
TA = 25°C HC 225
0 2 TA = –40°C to +85°C HC 280
TA = –55°C to +125°C HC 340
HC 45
TA = 25°C
HCT 55
HC 56
0 4.5 TA = –40°C to +85°C
HCT 69
Maximum HC 68
TA = –55°C to +125°C
switch turn HCT 83
tPZL,
ON delay 4051 ns
tPZH TA = 25°C HC 38
from S or E
TA = –55°C to +125°C HC 57
HC 32
TA = 25°C
HCT 39
HC 40
–4.5 4.5 TA = –40°C to +85°C
HCT 49
HC 48
TA = –55°C to +125°C
HCT 59

CD54HC4051, CD74HC4051
Switching Characteristics, CL = 50 pF (continued)

VEE VCC
(V) (V)
TA = 25°C HC 325
0 2 TA = –40°C to +85°C HC 405
TA = –55°C to +125°C HC 490
HC 65
TA = 25°C
HCT 70
HC 81
0 4.5 TA = –40°C to +85°C
HCT 68
Maximum HC 98
TA = –55°C to +125°C
switch turn HCT 105
tPZL,
ON delay 4052 ns
from S or E
TA = –55°C to +125°C HC 83
HC 46
TA = 25°C
HCT 48
HC 58
–4.5 4.5 TA = –40°C to +85°C
HCT 60
HC 69
TA = –55°C to +125°C
HCT 72
TA = 25°C HC 220
0 2 TA = –40°C to +85°C HC 275
TA = –55°C to +125°C HC 330
HC 44
TA = 25°C
HCT 48
HC 55
0 4.5 TA = –40°C to +85°C
HCT 60
Maximum HC 66
TA = –55°C to +125°C
switch turn HCT 72
tPZL,
ON delay 4053 ns
from S or E
TA = –55°C to +125°C HC 56
HC 31
TA = 25°C
HCT 34
HC 39
–4.5 4.5 TA = –40°C to +85°C
HCT 43
HC 47
TA = –55°C to +125°C
HCT 51
Input (control)
CI TA = –40°C to +85°C HC, HCT 10 pF
capacitance
TA = –55°C to +125°C HC, HCT 10

CD54HC4051, CD74HC4051
6.9 Analog Channel Specifications

Typical values at TA = 25°C
VEE VCC
PARAMETER TEST CONDITIONS HC, HCT TYPES TYP UNIT
(V) (V)
CI Switch input capacitance All 5 pF
4051 25
CCOM Common output capacitance 4052 12 pF
4053 8
4051 145
4052 –2.25 2.25 165
Minimum switch frequency
response at –3 dB 4053 200
fMAX See Figure 10 (1) (2) MHz
(see Figure 3, Figure 5, and 4051 180
Figure 7)
4052 –4.5 4.5 185
4053 200
All –2.25% 2.25% 0.035%
Sine-wave distortion See Figure 12
All –4.5% 4.5% 0.018%
4051 –2.25 2.25 –73
4052 –65
Switch OFF signal feedthrough 4053 –64
(see Figure 4, Figure 6, and See Figure 14 (2) (3) dB
Figure 8) 4051 –4.5 4.5 –75
4052 –67
4053 –66
(1) Adjust input voltage to obtain 0 dBm at VOS for fIN = 1 MHz.
(2) VIS is centered at (VCC – VEE) / 2.
(3) Adjust input for 0 dBm.
8
VCC − GND (V)
6
HCT
4 HC
0
0 2 4 6 8 10 12
VCC − VEE (V)
Figure 1. Recommended Operating Area as a Function of (VCC – VEE)
8
VCC − GND (V)
6
HCT
4 HC
0
0 −2 −4 −6 −8
VEE − GND (V)
Figure 2. Recommended Operating Area as a Function of (VEE – GND)

CD54HC4051, CD74HC4051
6.10 Typical Characteristics
0 0
VCC = 4.5 V
−2 GND = −4.5 V −20
VEE = −4.5 V VCC = 2.25 V
RL = 50 Ω GND = −2.25 V
PIN 12 TO 3 VEE = −2.25 V
−4 −40 RL = 50 Ω
VCC = 2.25 V
PIN 12 TO 3
dB
dB
GND = −2.25 V
VEE = −2.25 V
−6 RL = 50 Ω −60
PIN 12 TO 3 VCC = 4.5 V
GND = −4.5 V
−8 −80 VEE = −4.5 V
RL = 50 Ω
PIN 12 TO 3
−10 −100
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 3. Channel ON Bandwidth Figure 4. Channel OFF Feedthrough
(HC and HCT4051) (HC and HCT4051)
0 0
VCC = 2.25 V
VCC = 4.5 V
GND = −2.25 V
−2 GND = −4.5 V −20
VEE = −2.25 V
VEE = −4.5 V
RL = 50 Ω
RL = 50 Ω
PIN 4 TO 3
PIN 4 TO 3
−4 −40
VCC = 2.25 V
dB
dB
GND = −2.25 V
VEE = −2.25 V
−6 −60
RL = 50 Ω
PIN 4 TO 3 VCC = 4.5 V
GND = −4.5 V
VEE = −4.5V
−8 −80
RL = 50 Ω
PIN 4 TO 3
−10 −100
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M
0
0
VCC = 2.25 V
−20 GND = −2.25 V
VCC = 4.5 V VEE = −2.25 V
−1
GND = −4.5 V RL = 50 Ω
VEE = −4.5 V PIN 5 TO 4
RL = 50 Ω −40
PIN 5 TO 4
dB
−2
dB
VCC = 4.5 V
−60
GND = −4.5 V
−3 VCC = 2.25 V VEE = −4.5 V
GND = −2.25 V RL = 50 Ω
VEE = −2.25 V PIN 5 TO 4
−80
RL = 50 Ω
−4 PIN 5 TO 4
−100
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M

CD54HC4051, CD74HC4051
7 Parameter Measurement Information

VCC
tr = 6ns tf = 6ns
90%
SWITCH INPUT 50%
10%
tPLH tPHL VEE
90%
SWITCH OUTPUT 50%
10%
(FIGURE A)
6ns 6ns 6ns tr tf 6ns

VCC 3V
90% 2.7
E OR Sn 50% E OR Sn 1.3
10% 0.3
GND GND
tPLZ tPZL tPLZ tPZL
OUTPUT LOW OUTPUT LOW

TO OFF 50% TO OFF 50%
10% 10%
tPHZ tPZH tPHZ tPZH
90% 90%
OUTPUT HIGH 50% OUTPUT HIGH 50%
TO OFF TO OFF
SWITCH ON SWITCH OFF SWITCH ON SWITCH ON SWITCH OFF SWITCH ON
(FIGURE B) HC TYPES (FIGURE C) HCT TYPES
Figure 9. Switch Propagation Delay, Turn-On, Turn-Off Times
VCC VCC
VIS
VOS R
SWITCH SWITCH
VIS VOS1
ON ON
0.1μF INPUT 0.1µF
dB
50Ω 10pF R C
METER
fIS = 1MHz SINEWAVE
R = 50Ω
VCC /2 VCC /2
C = 10pF
VCC
R
SWITCH
VOS2
OFF
dB
VCC /2 R C
METER
VCC /2
Figure 10. Frequency Response Test Circuit Figure 11. Crosstalk Between Two Switches
Test Circuit

CD54HC4051, CD74HC4051
VCC
E
VI = VIH VIS
VCC
SWITCH VP−P
SINE− VOS
ON VOS
WAVE 10µF
VIS 600Ω SWITCH
10kΩ 50pF DISTORTION ALTERNATING VOS
METER ON AND OFF
VCC /2 tr, tf ≤ 6ns
VCC /2 fCONT = 1MHz 600Ω 50pF
fIS = 1kHz TO 10kHz SCOPE
50% DUTY
CYCLE
VCC /2
Figure 12. ¼Sine-Wave Distortion Test Circuit Figure 13. Control to Switch Feedthrough Noise
Test Circuit
fIS ≥ 1MHz SINEWAVE

R = 50Ω
VCC C = 10pF
VC = VIL
0.1µF VOS
SWITCH
VIS
OFF
dB
R R C METER
VCC /2 VCC /2
Figure 14. Switch OFF Signal Feedthrough
VEE FOR VCC FOR

tPLZ AND t PZL RL = 1kΩ tPLZ AND t PZL
TG
VCC FOR IN CL OUT VEE FOR
tPHZ AND t PZH 50pF tPHZ AND t PZH
Figure 15. Switch ON/OFF

Propagation Delay Test Circuit
IN TG OUT
50pF
Figure 16. Switch In to Switch Out

Propagation Delay Test Circuit

CD54HC4051, CD74HC4051
8 Detailed Description
8.1 Overview
The CDx4HCx4051 devices are a single 8-channel multiplexer having three binary control inputs, S0, S1, and S2
and an ENABLE input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8
inputs to the output.
The CDx4HCx4052 devices are a differential 4-channel multiplexer having two binary control inputs, S0 and S1,
and an ENABLE input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect
the analog inputs to the outputs.
The CDx4HCx4053 devices are a triple 2-channel multiplexer having three separate digital control inputs, S0, S1,
and S2 and an ENABLE input. Each control input selects one of a pair of channels that are connected in a single-
pole, double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.
8.2 Functional Block Diagrams
CHANNEL IN/OUT
VCC A7 A6 A5 A4 A3 A2 A1 A0
16 4 2 5 1 12 15 14 13
TG
TG
S0 11
TG
TG
S1 10 A
BINARY 3 COMMON
TO OUT/IN
LOGIC
1 OF 8 TG
LEVEL
DECODER
CONVERSION
WITH
ENABLE
S2 9
TG
TG
E 6
TG
8 7
GND VEE
All inputs are protected by standard CMOS protection network.
Figure 17. CDx4HCx4051 Functional Block Diagram

CD54HC4051, CD74HC4051
Functional Block Diagrams (continued)
A CHANNELS IN/OUT
A3 A2 A1 A0
VCC
11 15 14 12
16
TG
TG
TG
BINARY COMMON A
TG 13
TO OUT/IN
LOGIC
S1 9 1 OF 4
LEVEL
CONVERSION DECODER
COMMON B
WITH TG 3
ENABLE OUT/IN
S0 10
TG
E 6
TG
TG
8 7 1 5 2 4
GND VEE B0 B1 B2 B3
B CHANNELS IN/OUT
BINARY TO IN/OUT
VCC 1 OF 2
C1 C0 B1 B0 A1 A0
LOGIC LEVEL DECODERS
16
CONVERSION WITH ENABLE 3 5 1 2 13 12
TG
A COMMON
14
OUT/IN
S0 11
TG
TG
S1 10 B COMMON
15 OUT/IN
TG
TG
S2 9
C COMMON
4
OUT/IN
TG
E 6
8 7
GND VEE

CD54HC4051, CD74HC4051
8.3 Feature Description

The CDx4HCx405x line of multiplexers and demultiplexers can accept a wide range of analog signal levels from
–5 to +5 V. They have low ON resistance, typically 70-Ω for VCC – VEE = 4.5 V and 40-Ω for VC – VEE = 4.5 V,
which allows for very little signal loss through the switch.
Binary address decoding on chip makes channel selection easy. When channels are changed, a break-before-
make system eliminates channel overlap.
8.4 Device Functional Modes

Table 1. CD54HC4051, CD74HC4051, CD54HCT4051, CD74HCT4051 Function Table (1)
INPUT STATES ON
ENABLE S2 S1 S0 CHANNEL
L L L L A0
L L L H A1
L L H L A2
L L H H A3
L H L L A4
L H L H A5
L H H L A6
L H H H A7
H X X X None
(1) X = Don't care

INPUT STATES ON
ENABLE S1 S0 CHANNELS
L L L A0, B0
L L H A1, B1
L H L A2, B2
L H H A3, B3
H X X None
(1) X = Don't care

INPUT STATES ON
ENABLE S2 S1 S0 CHANNELS
L L L L C0, B0, A0
L L L H C0, B0, A1
L L H L C0, B1, A0
L L H H C0, B1, A1
L H L L C1, B0, A0
L H L H C1, B0, A1
L H H L C1, B1, A0
L H H H C1, B1, A1
H X X X None
(1) X = Don't care

CD54HC4051, CD74HC4051
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The CDx4HCx405x line of multiplexers and demultiplexers can be used for a wide variety of applications.
9.2 Typical Application

One application of the CD74HC4051 device is used in conjunction with a microcontroller to poll a keypad.
Figure 20 shows the basic schematic for such a polling system. The microcontroller uses the channel-select pins
to cycle through the different channels while reading the input to see if a user is pressing any of the keys. This is
a very robust setup that allows for simultaneous key presses with very little power consumption. It also uses very
few pins on the microcontroller. The down side of polling is that the microcontroller must frequently scan the keys
for a press.
Microcontroller
Polling Input Channel Select

3.3V
S2 S1 S0 k0
E Ch 0
S2S1S0
000 Ch 1 k1
001
Ch 2 k2
010
Ch 3 k3
011
COM
100 Ch 4 k4
101 k5
VCC Ch 5
110
Ch 6 k6
VEE 111
Ch 7 k7
GND CD74HC4051
Pull-down resistors (10NŸ)
Figure 20. CD74HC4051 Being Used to Help Read Button Presses on a Keypad
9.2.1 Design Requirements

These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads, so routing and load conditions must be considered to prevent ringing.

CD54HC4051, CD74HC4051
Typical Application (continued)

See Table 4 for the input loading details.
Table 4. HCT Input Loading Table

TYPE INPUT UNIT LOADS (1)
4051, 4053 All 0.5
4052 All 0.4
(1) Unit load is ΔICC limit specified in Specifications, for example, 360-mA MAX at 25°C.
9.2.2 Detailed Design Procedure

1. Recommended input conditions:
– For switch time specifications, see propagation delay times in Electrical Characteristics: HC Devices.
– Inputs must not be pushed more than 0.5 V above VDD or below VEE.
– For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics: HC
Devices.
2. Recommended output conditions:
– Outputs must not be pulled above VDD or below VEE.
3. Input and output current consideration:
– The CDx4HCx405x series of parts do not have internal current-drive circuitry, and thus cannot sink or
source current. Any current will be passed through the device.
9.2.3 Application Curve

120
100
ON RESISTANCE (Ω)
80
VCC − VEE = 4.5V
60
VCC − VEE = 6V
40
VCC − VEE = 9V
20
1 2 3 4 5 6 7 8 9
INPUT SIGNAL VOLTAGE (V)
Figure 21. Typical ON Resistance vs Input Signal Voltage
10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Electrical Characteristics: HC Devices.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. A 0.1-μF and a 1-μF capacitor are commonly used in parallel. For best results, the
bypass capacitor or capacitors must be installed as close as possible to the power terminal.

CD54HC4051, CD74HC4051
11 Layout
11.1 Layout Guidelines

Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change in width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
change in width upsets the transmission line characteristics, especially the distributed capacitance and self-
inductance of the trace, thus resulting in the reflection. Not all PCB traces can be straight, so they will have to
turn corners. Figure 22 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
11.2 Layout Example

WORST BETTER BEST
2W
1W min.
W
Figure 22. Trace Example

CD54HC4051, CD74HC4051
12 Device and Documentation Support
12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
CD54HC4051 Click here Click here Click here Click here Click here
CD54HCT4051 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

CD54HC4051, CD74HC4051
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
5962-8775401EA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8775401EA Samples
& Green CD54HC4053F3A
5962-8855601EA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8855601EA Samples
5962-9065401MEA ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9065401ME Samples
& Green A
CD54HCT4051F3A
CD54HC4051F ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC4051F Samples
& Green
CD54HC4051F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC4051F3A Samples
& Green
& Green
CD54HC4052F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8855601EA Samples
& Green
CD54HC4053F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8775401EA Samples
CD54HCT4051F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9065401ME Samples
& Green A
CD54HCT4051F3A
CD74HC4051E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E Samples
CD74HC4051EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E Samples
CD74HC4051M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96G3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
Addendum-Page 1
(6)
CD74HC4051ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051NSRE4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M Samples
CD74HC4051PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4051PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4051PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4051PWTG4 ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051 Samples
CD74HC4052M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M Samples
CD74HC4052PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052 Samples
Addendum-Page 2
(6)
CD74HC4053M96G3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M Samples
CD74HC4053PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053 Samples
CD74HCT4051E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4051E Samples
CD74HCT4051M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
CD74HCT4051MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M Samples
Addendum-Page 3
(6)
CD74HCT4053M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053ME4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M Samples
CD74HCT4053PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HK4053 Samples
CD74HCT4053PWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 Samples
CD74HCT4053PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 Samples
CD74HCT4053PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 4
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4051, CD54HC4052, CD54HC4053, CD54HCT4051, CD74HC4051, CD74HC4052, CD74HC4053, CD74HCT4051 :
• Catalog : CD74HC4051, CD74HC4052, CD74HC4053, CD74HCT4051

• Automotive : CD74HC4051-Q1, CD74HCT4051-Q1, CD74HC4051-Q1, CD74HCT4051-Q1
• Enhanced Product : CD74HC4051-EP, CD74HC4051-EP
• Military : CD54HC4051, CD54HC4052, CD54HC4053, CD54HCT4051
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC4051M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4051NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC4051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4051PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4051PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4052M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4052M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4052M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4052NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC4053M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053M96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053M96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4053NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HCT4051M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT4052M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT4053M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT4053PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4053PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4053PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4053PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4051M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4051M96 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4051M96G3 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4051M96G4 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4051NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC4051PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4051PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4051PWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4051PWT TSSOP PW 16 250 356.0 356.0 35.0
CD74HC4052M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4052M96 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4052M96G4 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4052NSR SO NS 16 2000 356.0 356.0 35.0
CD74HC4052PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4052PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4052PWT TSSOP PW 16 250 356.0 356.0 35.0
CD74HC4053M96 SOIC D 16 2500 364.0 364.0 27.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4053M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4053M96G3 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4053M96G4 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4053NSR SO NS 16 2000 356.0 356.0 35.0
CD74HC4053PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HC4053PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4053PWT TSSOP PW 16 250 356.0 356.0 35.0
CD74HCT4051M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HCT4052M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HCT4053M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HCT4053PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HCT4053PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HCT4053PWRG4 TSSOP PW 16 2000 356.0 356.0 35.0
CD74HCT4053PWT TSSOP PW 16 250 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC4051M D SOIC 16 40 507 8 3940 4.32
CD74HC4051ME4 D SOIC 16 40 507 8 3940 4.32
CD74HC4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4052M D SOIC 16 40 507 8 3940 4.32
CD74HC4052PW PW TSSOP 16 90 530 10.2 3600 3.5
CD74HC4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4053M D SOIC 16 40 507 8 3940 4.32
CD74HC4053ME4 D SOIC 16 40 507 8 3940 4.32
CD74HC4053MG4 D SOIC 16 40 507 8 3940 4.32
CD74HC4053PW PW TSSOP 16 90 530 10.2 3600 3.5
CD74HCT4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4051E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4051M D SOIC 16 40 507 8 3940 4.32
CD74HCT4051ME4 D SOIC 16 40 507 8 3940 4.32
CD74HCT4051MG4 D SOIC 16 40 507 8 3940 4.32
CD74HCT4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4052E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4052M D SOIC 16 40 507 8 3940 4.32
CD74HCT4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4053E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4053M D SOIC 16 40 507 8 3940 4.32
CD74HCT4053ME4 D SOIC 16 40 507 8 3940 4.32
PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP
8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1
10.4 2X
10.0 8.89
NOTE 3
8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4
0.15 TYP
SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1
0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)
4220735/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP
16X (1.85) SEE

SYMM DETAILS
1 16
16X (0.6)
SYMM
14X (1.27)
8 9
(R0.05) TYP
(7)
LAND PATTERN EXAMPLE

SCALE:7X
SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4220735/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP
16X (1.85) SYMM
1 16
16X (0.6)
SYMM
14X (1.27)
8 9
(R0.05) TYP (7)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220735/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1 4.55
4.9
NOTE 3
8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16
SYMM
14X (0.65)
8 9
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16
SYMM
14X (0.65)
8 9
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated

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CDx4HC405x, CDx4HCT405x High-Speed CMOS Logic Analog

– Switch Voltage: 0 V to 10 V CD54HCx405xF CDIP (16) 19.56 mm × 6.92 mm

of All Parameters. VCC A7 A6 A5 A4 A3 A2 A1 A0

• Programmable Logic Circuits

Changes from Revision L (February 2017) to Revision M Page

• Changed Feature From: 7-Ω Typical To: 70-Ω Typical ......................................................................................................... 1

Changes from Revision K (September 2015) to Revision L Page

Changes from Revision J (February 2011) to Revision K Page

• Removed Ordering Information table. .................................................................................................................................... 1

2 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

5 Pin Configuration and Functions

CD54HC4051, CD54HCT4051, CD74HC4051, CD74HCT4051 J, N, D, NS, PW Packages

COM OUT/IN A 3 14 A1 CHANNEL

Pin Functions for CDx4HCx4051B

Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

CD54HC4052, CD74HC4052, CD74HCT4052 J, N, D, NS, PW Packages

CHANNEL B3 4 13 AN COM OUT/IN

Pin Functions for CDx4HCx4052B

4 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

CD54HC4053 CD74HC4053 CD74HCT4053 J, N, D, NS, PW Packages

Pin Functions CDx4HCx4053B

Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 5

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

6.4 Thermal Information

6.5 Electrical Characteristics: HC Devices

Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 7

Electrical Characteristics: HC Devices (continued)

8 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

Electrical Characteristics: HC Devices (continued)

Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 9

6.6 Electrical Characteristics: HCT Devices

Maximum ON resistance 0 4.5 25°C 10

10 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

Electrical Characteristics: HCT Devices (continued)

(1) Any voltage between VCC and GND.

Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 11

6.7 Switching Characteristics, VCC = 5 V

12 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

6.8 Switching Characteristics, CL = 50 pF

tPLH, Propagation delay, TA = –55°C to +125°C HC, HCT 18

Maximum 0 4.5 TA = –40°C to +85°C HC, HCT 56

Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 13

Switching Characteristics, CL = 50 pF (continued)

14 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

Switching Characteristics, CL = 50 pF (continued)

Copyright © 1997–2019, Texas Instruments Incorporated Submit Documentation Feedback 15

6.9 Analog Channel Specifications

Figure 1. Recommended Operating Area as a Function of (VCC – VEE)

Figure 2. Recommended Operating Area as a Function of (VEE – GND)

16 Submit Documentation Feedback Copyright © 1997–2019, Texas Instruments Incorporated

Product Folder Links: CD54HC4051 CD74HC4051 CD54HCT4051 CD74HCT4051 CD54HC4052 CD74HC4052

6.10 Typical Characteristics