RTL2GDSII WORKSHOP

4 BIT FULL ADDER

Abstract
This Document contains the ASIC chip design process, From the RTL stage to Timing analysis.

Maheshwaraa B S
MYSORE BATCH-1
maheshwaras05@gmail.com
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Table of Contents
I. Tools Summary …………………………………………2
i) Frontend Tools (2)
ii) Backend Tools (2)
II. Verilog ………………………………………………………3
i) Verilog code (3)
ii) Testbench (4)
III. DC Tool ……………………………………………………………6
i) RTL to Gate level conversion (6)
ii) Conversion flow (7)
IV. ICC Tool …………………………………………………………..13
i) Floor plan (14)
ii) Power plan (16)
iii) Placement (21)
iv) CTS (Clock tree synthesis) (23)
v) Routing (24)
V. PT Tool ……………………………………………………………27
i) STA (27)

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Tools Summary
Language details
Use of TCL
I. TCL contains the tool automated commands, this files
minimize the work timing.
II. The best tcl commands produce better results in PD
Use of Verilog
I. Verilog is a Hardware description language, it’s used to
describe the functionality of digital circuit.
II. It’s used to describe digital and mixed signal circuit.

PD Tools details
Frontend tools
Use of VCS
I. Verilog code simulator
Use of Verdi
I. Testbench simulation
II. wave viewer

Backend tools
Use of Design Vision
I. Convert the HDL into a GTECH and Design ware Lib file
II. Time, power, area and data path optimization.
III. Input Lib: Std cell lib, Verilog file and Technology file.
Use of Integrated Circuit compiler
I. Floor plan
II. Power plan
III. Placement
IV. CTS (Clock tree synthesis)
V. Route
Use of Prime Time
I. Static timing analysis (Sign off tool)

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VERILOG CODE
(i) 4 Bit Full adder Verilog code
module full_adder (A, B, C_in, C_out, Clock, SUM);

input [3:0] A, B;

input Clock, C_in;

output reg [3:0] SUM;

output reg C_out;

reg [3:0] reg1, reg2, sum_i;

reg c_in, c_out;

always @ (posedge Clock)

begin

reg1 <= A;

reg2 <= B;

c_in <= C_in;

end

always @ (posedge Clock)

begin

SUM <= sum_i;

C_out <= c_out;

end

always @ *

begin

{c_out, sum_i} = reg1 + reg2 + c_in;

end

endmodule

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(ii) Test bench code

`include "full_adder_1.v"

module tb;

reg [3:0] A, B;

reg Clock, C_in;

wire [3:0] SUM;

wire C_out;

full_adder dut (.A(A), .B(B), .Clock(Clock), .C_in(C_in), .SUM(SUM), .C_out(C_out) );

always #5 Clock = ~Clock;

initial begin

// $fsdbDumpvars();

$dumpfile("tb.vcd");

$dumpvars(0,tb);

A <= 0;

B <= 0;

C_in <= 0;

Clock <= 0;

#20 A <= 4'b0001; B <= 4'b0001; C_in <= 0; // 1 + 1 = 2 (binary: 10)

$display("A = %b, B = %b, C_in = %b, SUM = %b, C_out = %b", A, B, C_in, SUM, C_out);

#20 A <= 4'b0110; B <= 4'b1010; C_in <= 1; // 6 + 10 + 1 = 17 (binary: 10001)

$display("A = %b, B = %b, C_in = %b, SUM = %b, C_out = %b", A, B, C_in, SUM, C_out);

#20 A <= 4'b1000; B <= 4'b1111; C_in <= 1; // 8 + 15 + 1 = 24 (binary: 11000)

$display("A = %b, B = %b, C_in = %b, SUM = %b, C_out = %b", A, B, C_in, SUM, C_out);

#100 $finish;

End

Endmodule

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Verilog
• Verilog is hardware description language (HDL) that’s used to describe
the functionality in code format.
• Verilog is widely used for design and verify the digital and mixed signal
systems.
• For compile the Verilog code we use VCS and Veridi is used to simulate
the hdl.

✓ RTL Simulation using Verdi tool (Image1 : Schematic & Image2 : Output wave view)

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DC SHELL
(iii) RTL TO GATE LEVEL CONVERSION
Required files for Conversion
➢ Verilog files (HDL file in .v format)
➢ Process development kit
➢ SDC Constraints (Std cell constraints)

1. PDK File consists of

a. Library file –
i. Std cell details (RVT, HVT and LVT) and tech details
about the std cells,
ii. Clock (PLL),
iii. Input and output details
iv. sram details
v. ndm file details – consists of ()
b. Tech Lib - Tech base details (Ex – 45nm, 32nm, 7nm)
i. Mikyway
ii. RC file
iii. Hspice
iv. Drc
v. Lvs
vi. TLU Plus and Map files

Steps involved in conversion

➢ In this synthesis process design compiler convert the RTL into a Gate
level format. Here the Design compiler use GTech and Design ware lib
a. Gtech and Designware:
i. G Tech is a technology independent library and it’s contains basic
logic gates and flipflop.
ii. Designware is a technology independent library and it’s contains
of more complex cells
➢ After GTech conversion, the design compiler optimize and map the
design to a specific technology and target library. Here designer feed the
timing constraint to the gate level netlist.
➢ Now the design is ready for test process. After completion of the test
process the gate level netlist is ready for the PnR tools. (PnR tool work
will be start with help of mapped .v file).

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Required files for #dc_shell

• Tested Verilog file (.v File)
• Reference methodology
• TCL file

(iv) Conversion flow

• dc_shell command is used to invoke the dc tools in linux environment

and dc tools consists of,

• start_gui is a command used to invoke the design tool,

• With help of Tool automated commands, we convert the RTL code

into a Gate level netlist
(1) First step of conversion, Provide the path for the tool, to get the
.lib files and .tf technology files in pdk directory.

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(2) Followed by we need to provide the reference methodology. This

reference methodology file give the exact file path for the tool.
(i) Here, we mention the target library, technology library,
additional library search path, resistance and capacitance
library, interconnect technology library, milkyway
library(metal and poly layer details) and voltage variables.
(ii) Apart from the library details, here the application variable
setup and paths to save the executed result and report files.
(iii) On the other hand we provide some application
variable to save the files after execute the previous scripts.
(3) After execute the reference methodology file, we set the path for
Verilog file.
(4) Here we have the privilege to restrict the tool for utilize the logic
gates and complex cell.
(a) set_dont_use [get_lib_cells */<cell_name>*], help of this
command we can restricted the tool.
(b) After executed this command we can able to concluded where
the tool get the cell details, timing and designware details

(5) After execute previous commands, now we are analyze the Verilog
and elaborate the design. In this stage tool generate some file.
(i) Analyze – Generate one intermediate file with extension of
.pvl .
(ii) The .pvl intermediate file read and gtech design is build with
help of Elaborate and we get the register details also
available in this stage.
(iii) Apart from .pvl file we get .mr and .syn files also.
(6) Now the Gtech design was generated. After got the gtech file we
include the time constraint to check the timing.
(7) Followed by the compile_ultra is used to convert the gtech into a
gate level netlist.
(8) The final stage of conversion, we write or save the mapped Verilog
netlist in the format of mapped.v

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Various stages in the time of command execution

✓ Sourcing the Verilog HDL file

✓ G TECH Library conversion

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✓ Elaborate the design

• Compile_Ultra consists of,

(1) Power optimization
(2) Alib library (area and delay optimization solution)
(3) Timing information
(4) Mapping optimization
(5) Global optimization
(6) Delay optimization
(7) WLM(Wire load model) optimization
(8) Design rule checking
(9) Leakage power optimization

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✓ Gate level netlist final stage of DC

✓ Mapped Verilog file conversion

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✓ Timing report

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ICC2 – PnR Stage

✓ ICC2 consists of
(1) Floorplan
(2) Powerplan
(3) Placement
(4) Clock tree synthesis
(5) Routing
(6) Physical verification
(7) GDS2 Conversion
✓ Primary setup and reference file
(a) Before getting into the floorplan, we need show the path of the
technology file and mapped Verilog file to the tool.
(b) In Floorplan stage we use ndm (new data module) lib. This ndm
library contains logical, physical and technology library files.

✓ Reading mapped Verilog file

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✓ Std cells in Gui

(v) Floor plan

Floorplan is a process to places the std cells and macros. The floorplan
determines the quality of the chip.
✓ Initialize_floorplan -core_utilization 0.7

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✓ Core area in Icc2 tool

✓ create_placement – floorplan: icc2 view

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✓ Floorplan consists of,

i) Floorplan creation stage
ii) Reports are,
(1) Wire length report
(2) Physical hierarchy violations report
(3) Voltage area violations report
(4) Hard macro to hard macro overlap report

✓ Floorplan conversion

(vi) Power plan

• Powerplan is used to provide the proper power supply to the macros and
std cells. The metals layers are used to distribute the power for each and
every cells.
• Before start the power plan, must we ensure the std cells and macros are
placed inside the core area and first step of powerplan is creating ring
distribution for the entire core area.
• In this stage must we ensure the what kind of metal we are going to use
and width of the metal layer, pitch distance between the metal layers.
• First step of powerplan is create the ring for the entire core area. The
tool do some process to create a power ring for core area. That steps are
available in below imgae.
• Second step of power plan is create a mesh for core area. This mesh
distribute constant power to std cells and macros with help of cell rails.
• Third stage of power plan is create a power distribution rails for cells.
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✓ Ring Compilation

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✓ Images shows us, the ring was created.

✓ Mesh compilation in core area

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✓ Image shows the mesh availability in core area.

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✓ Powerplan compliation

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✓ Final Powerplan

(vii) Placement

✓ Placement is a process to find the suitable location for the std cells and
macros. And the placement is done by two way.
(1) Coarse placement
(2) Legalization
✓ Goal of the placement
(1) Timing, area and power optimization
(2) Routable design
✓ First stage of placement, determine the operating mode and operating
corners. After completion of the first setup we need to provide the
parasitic files to check the best and worst case operation.
✓ Global or pre-routing is done at this stage.
✓ Below we can see the cell are routing and std cell are placed in tracks.

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✓ Placement and pre routing

✓ Std cell proper placement

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(viii) Clock tree synthesis

• In placement stage we get idle clock.

• CTS is a process of connecting the clock to the all clock pins of sequential
blocks.
• Two different
• In this stage idle clocks are convert into a propagated clocks
• Goal of the CTS is
i) Balance the skew
ii) Minimize the insertion delay

✓ Clock path for Sequential circuit

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(ix) Routing

• Routing is a process to create a physical connection based logical

connectivity. Signal pins are connected with help of route interconnect
metal layer and in this stage track assignment also done.
• Type of route
i) Pre – route or global route
ii) Detailed route (Assign clock and data or signal path)
• Goal of route
i) Minimize the interconnection wire length
ii) Avoid DRC and LVS
iii) Meet timing

✓ Routed Clock path

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✓ Routed Data or signal path

✓ Connection between data path and Input path

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✓ Finalize Routed design

• Before getting into the static timing analysis, we need to write the output
files from the routing stage. That’s files are routed Verilog file (routed.v),
SDC (.sdc) and Parasitic(.spef) file.

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Timing analysis
• Timing analysis is process for check the circuit meets the target timing or
not.
• Two type of analysis are available
i) Static timing analysis
ii) Dynamic timing analysis

Static timing analysis

• STA is kind of technique to check the timing.
• STA analysis is a type and the design carried out statically and does not
depend upon the data value, which are applied in input pin.

(x) Prime Time - STA

• Keep the technology file as a base, here we check the best and worst
timing.

✓ Timing violation details

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✓ Cell base Violation report

✓ Violation area schematic

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