ECS 301 COMPUTER ORGANIZATION

INPUT-OUTPUT ORGANIZATION

• Peripheral Devices

• Input-Output Interface

• Asynchronous Data Transfer

• Modes of Transfer

• Priority Interrupt

• Direct Memory Access

• Input-Output Processor

• Serial Communication

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INPUT OUTPUT DEVICES

• The input-output subsystem of a computer, referred
to as I/O, provides an efficient mode of
communication between the central system and the
outside environment.
• Devices that are under the direct control of the
computer are said to be connected on-line.
– These devices are designed to read information into or out of the
memory unit upon command from the CPU and are considered to
be part of the total computer system.
• Input or output devices attached to the peripheral
computer are also called peripherals.
– Among the most common peripherals are keyboards, display units,
and printers. Peripherals that provide auxiliary storage for the
system are magnetic disks and tapes.

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I/O ORGANIZATION
• The input-output organization of a computer is a
function of the size of the computer and the devices
connected to it.
• The difference between a small and a large system is
mostly dependent on the amount of hardware the
computer has available for communicating with
peripheral units and the number of peripherals
connected to the system.

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Peripheral Devices

PERIPHERAL DEVICES
Input Devices Output Devices
• Keyboard
• Card Puncher, Paper Tape Puncher
• Optical input devices
• CRT
- Card Reader
• Printer (Impact, Ink Jet,
- Paper Tape Reader
Laser, Dot Matrix)
- Bar code reader
• Plotter
- Digitizer
• Analog
- Optical Mark Reader
• Voice
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices

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Input Output Interface

• Designing logic circuits (Hardware) and writing

instructions (Software) to enable the
processor to communicate with peripherals is
called interfacing, and the logic circuits are
called I/O ports or interfacing devices.

• I/O system and I/O module or I/O interface

• Each device also has an individual controller

that supervises the operation of the particular
mechanism in the peripheral

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A Single Bus System

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Input/Output Interfaces

INPUT/OUTPUT INTERFACE
• Provides a method for transferring information between internal
storage (such as memory and CPU registers) and external I/O
devices
• Resolves the differences between the computer and peripheral
devices
– Peripherals – Electromechanical/Electromagnetic Devices
– CPU or Memory - Electronic Device
• Conversion of signal values required
– Data Transfer Rate
» Peripherals - Usually slower
» CPU or Memory - Usually faster than peripherals
• Some kinds of Synchronization mechanism may be needed

– Unit of Information
» Peripherals – Byte, Block, …
» CPU or Memory – Word

– Data representations and operating modes may differ

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Device Interface

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Input/Output Interfaces

I/O BUS AND INTERFACE MODULES

Each peripheral device has associated with it an interface unit.

Each interface decodes the address and control received from
the I/O bus, interprets them for the peripheral, and provides
signals for the peripheral controller. It also synchronizes the
data flow and supervises the transfer between peripheral and
processor. Each peripheral has its own controller that
operates the particular electromechanical device.

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I/O Process
• The I/O bus from the processor is attached to all peripheral interfaces.
• To communicate with a particular device, the processor places a device
address on the address lines.
• Each interface attached to the I/O bus contains an address decoder that
monitors the address lines.
• When the interface detects its own address, it activates the path between the
bus lines and the device that it controls.
• All peripherals whose address does not correspond to the address in the bus
are disabled by their interface.
• At the same time that the address is made available in the address lines, the
processor provides a function code in the control lines. The interface selected
responds to the function code and proceeds to execute it.
• The function code is referred to as an I/O command and is in essence an
instruction that is executed in the interface and its attached peripheral unit.
• The interpretation of the command depends on the peripheral that the
processor is addressing.
• There are four types of commands that an interface may receive. They are
classified as control, status, data output, and data input.

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Command Types
• A control command is issued to activate the
peripheral and to inform it what to do.
» For example, a magnetic tape unit may be instructed to backspace the
tape by one record, to rewind the tape, or to start the tape moving in
the forward direction.
– The particular control command issued depends on the peripheral,
and each peripheral receives its own distinguished sequence of
control commands, depending on its mode of operation.
• A status command is used to test various status
conditions in the interface and the peripheral.
» For example, the computer may wish to check the status of the
peripheral before a transfer is initiated. During the transfer, one or
more errors may occur which are detected by the interface. These
errors are designated by setting bits in a status register that the
processor can read at certain intervals.

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Command Types
• A data output command causes the interface to
respond by transferring data from the bus into one of
its registers.
» Consider an example with a tape unit. The computer starts the tape
moving by issuing a control command. The processor then monitors
the status of the tape by means of a status command. When the tape is
in the correct position, the processor issues a data output command.
The interface responds to the address and command and transfers the
information from the data lines in the bus to its buffer register. The
interface then communicates with the tape controller and sends the
data to be stored on tape.

• The data input command is the opposite of the data

output. In this case the interface receives an item of
data from the peripheral and places it in its buffer
register.
– The processor checks if data are available by means of a status
command and then issues a data input command. The interface
places the data on the data lines, where they are accepted by the
processor.

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I/O MODULE
• Interfaces
– Internal Interface to the CPU and memory via the system Bus
– External Interface to one or more I/O devices by tailored data links.
• Requirements
– Control & Timing
» To coordinate the flow of traffic between internal resources
and external devices
– CPU Communication
» Control signal to the I/O module over the control bus
» Exchange of data between CPU and I/O module over data bus
» Status signals like BUSY, READY needed as the data transfer
rates of the CPU and the peripherals vary
» Address of the various peripherals connected to CPU
– Device Communication
» Commands, status information and data
– Data Buffering
– Error Detection

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I/O Versus Memory Bus

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ISOLATED I/O

Isolated I/O

- Separate I/O read/write control lines in addition to memory read/write control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions
- Memory address values are not affected by interface register assignment

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Memory Mapped IO

• Both the memory and I/O devices are connected to the CPU through the
same bus
• The device addresses are a part of the memory address space.
• The load and store instructions used with memory operands can be used as
the read and write instructions with respect to those addresses configured for
I/O devices.
• Separate I/O instructions are not needed
• Some of the memory address space is used up by the I/O, and it can be
difficult to distinguish between the memory and I/O – oriented operations in a
program.

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ISOLATED I/O Vs. MEMORY MAPPED I/O

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Input/Output Interfaces

I/O INTERFACE
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

CPU Chip select CS

I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register

• The interface may work with an I/p, an o/p or an I/o device.

• A command is passed to the I/O device by sending a word to the appropriate interface register.
• The transfer of data, control and status information is always via the common data bus, the
distinction is determined from the particular interface register with which the CPU
communicates.
• By placing appropriate control bits in the control register, the interface and device can be placed
in different modes.

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Asynchronous Data Transfer

ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations
Synchronous - All devices derive the timing information from
common clock line
Asynchronous - No common clock
Asynchronous Data Transfer
Asynchronous data transfer between two independent units requires
that control signals be transmitted between the communicating units
to indicate the time at which data is being transmitted
Two Asynchronous Data Transfer Methods
Strobe pulse
A strobe pulse is supplied by one unit to indicate the other unit
when the transfer has to occur
Handshaking
A control signal is accompanied with each data being
transmitted to indicate the presence of data
The receiving unit responds with another control signal to
acknowledge receipt of the data
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Asynchronous Data Transfer

STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or
the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe

e.g. I/O Write CPU  I/O(Strobe) e.g. I/O Read CPU  I/O (strobe)
CPU  I/O(data) I/O  CPU (data)

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Asynchronous Data Transfer

HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data

Destination-Initiated

The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus

To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply
to the unit that initiates the transfer

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Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).

* Allows arbitrary delays from one state to the next

* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
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Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism

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TRANSMISSON MODES
• The transfer of data between two units may be done in parallel or serial.
– In parallel data transmission, each bit of the message has its own path and the total
message is transmitted at the same time. This means that an n-bit message must be
transmitted through n separate conductor paths.
– In serial data transmission, each bit in the message is sent in sequence one at a time.
This method requires the use of one pair of conductors or one conductor and a
common ground.
– Parallel transmission is faster but requires many wires. It is used for short distances
and where speed is important.
– Serial transmission is slower but is less expensive since it requires only one pair of
conductors.
• Serial transmission can be synchronous or asynchronous.
– In synchronous transmission, the two units share a common clock frequency and bits
are transmitted continuously at the rate dictated by the clock pulses. In long- distant
serial transmission, each unit is driven by a separate clock of the same frequency.
Synchronization signals are transmitted periodically between the two units to keep
their clocks in step with each other.
– In asynchronous transmission, binary information is sent only when it is available and
the line remains idle when there is no information to be transmitted.
– This is in contrast to synchronous transmission, where bits must be transmitted
continuously to keep the clock frequency in both units synchronized with each other.

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Asynchronous Serial Transfer

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Asynchronous Communication Interface

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ASYNCHRONOUS INTERFACE
• The interface is initialized for a particular mode of transfer by means of a
control byte that is loaded into its control register.
– The transmitter register accepts a data byte from the CPU through the data bus. This byte is
transferred to a shift register for serial transmission.
– The receiver portion receives serial information into another shift register, and when a complete
data byte is accumulated, it is transferred to the receiver register. The CPU can select the receiver
register to read the byte through the data bus.
• The bits in the status register are used for input and output flags and for
recording certain errors that may occur during the transmission. The CPU
can read the status register to check the status of the flag bits and to
determine if any errors have occurred.
– Two bits in the status register are used as flags. One bit is used to indicate whether the transmitter
register is empty and another bit is used to indicate whether the receiver register is full.
• The chip select and the read and write control lines communicate with the
CPU. The chip select (CS) input is used to select the interface through
the address bus.
• The register select (RS) is associated with the read (RD) and write (WR)
controls. Two registers are write-only and two are read-only. The register
selected is a function of the RS value and the RD and WR status, as
listed in the table accompanying the diagram.
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ASYNCHRONOUS INTERFACE - TRANSMITTER

• The CPU reads the status register and checks the flag to see if
the transmitter register is empty.
• If it is empty, the CPU transfers a character to the transmitter
register and the interface clears the flag to mark the register
full.
• The first bit in the transmitter shift register is set to 0 to
generate a start bit. The character is transferred in parallel from
the transmitter register to the shift register and the appropriate
number of stop bits are appended into the shift register.
• The transmitter register is then marked empty. The character
can now be transmitted one bit at a time by shifting the data in
the shift register at the specified baud rate.
• The CPU can transfer another character to the transmitter
register after checking the flag in the status register.
• The interface is said to be double buffered because a new
character can be loaded as soon as the previous one starts
transmission.

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ASYNCHRONOUS INTERFACE - RECEIVER

• The receive data input is in the 1-state when the line is idle.
• The receiver control monitors the receive-data line for a 0 signal to
detect the occurrence of a start bit.
• Once a start bit has been detected, the incoming bits of the
character are shifted into the shift register at the prescribed baud
rate.
• After receiving the data bits, the interface checks for the parity and
stop bits.
• The character without the start and stop bits is then transferred in
parallel from the shift register to the receiver register.
• The flag in the status register is set to indicate that the receiver
register is full.
• The CPU reads the status register and checks the flag, and if set, it
reads the data from the receiver register.
• The interface checks for any possible errors during transmission
and sets appropriate bits in the status register. The CPU can read
the status register at any time to check if any errors have occurred.

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ERRORS
• Three possible errors that the interface checks
during transmission are
– parity error,
– framing error, and
– overrun error.
• Parity error occurs if the number of l's in the received
data is not the correct parity.
• A framing error occurs if the right number of stop
bits is not detected at the end of the received
character.
• An overrun error occurs if the CPU does not read the
character from the receiver register before the next
one becomes available in the shift register. Overrun
error results in a loss of characters in the received
data stream.
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MODES OF TRANSFER
• Binary information received from an external device is
usually stored in memory for later processing.
• Information transferred from the central computer into an
external device originates in the memory unit.
• The CPU merely executes the I/O instructions and may
accept the data temporarily, but the ultimate source or
destination is the memory unit.
• Data transfer between the central computer and I/O devices
may be handled in a variety of modes.
• Some modes use the CPU as an intermediate path; others
transfer the data directly to and from the memory unit. Data
transfer to and from peripherals may be handled in one of
three possible modes:
– 1. Programmed I/O
– 2. Interrupt-initiated I/O
– 3. Direct memory access (DMA)
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Modes of Transfer

Program Controlled I/O

• Programmed I/O operations are the result

of I/O instructions written in the computer
program.
• Each data item transfer is initiated by an
instruction in the program.
• Usually, the transfer is to and from a CPU
register and peripheral.
• Other instructions are needed to transfer
the data to and from CPU and memory.
• In the programmed I/O method, the I/O
device does not have direct access to
memory. A transfer from an I/O device to
memory requires the execution of several
instructions by the CPU, including an input
instruction to transfer the data from the
device to the CPU and a store instruction
to transfer the data from the CPU to
memory.

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Programmed I/O
• The benefit of using this approach is that we
have programmatic control over the behavior
of each device. Program changes can make
adjustments to the number and types of
devices in the system as well as their polling
priorities and intervals.
• Constant register polling, however, is a
problem. The CPU is in a continual “busy
wait” loop until it starts servicing an I/O
request. It doesn’t do any useful work until
there is I/O to process.
• Owing to these limitations, programmed I/O
is best suited for special-purpose systems
such as automated teller machines and
systems that control or monitor
environmental events.

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EXAMPLE

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PROCESS

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Modes of Transfer

INTERRUPT INITIATED I/O

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Interrupt Driven I/O

• The CPU responds to the interrupt
signal by storing the return address
from the program counter into a
memory stack and then control
branches to a service routine that
processes the required I/O transfer.
• The way that the processor chooses
the branch address of the service
routine varies from one unit to
another.
• In a nonvectored interrupt, the branch
address is assigned to a fixed location
in memory.
• In a vectored interrupt, the source that
interrupts supplies the branch
information to the computer. This
information is called the interrupt
vector.

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Priority Interrupt

Interrupts and ISR

In a number of conditions the processor may be interrupted from its normal
processing activity. Some of these conditions are :

1. Power failure as detected by a sensor

2. Arithmetic conditions such as overflow and underflow
3. Illegal data or illegal instruction code
4. Errors in data transmission and storage
5. Software-generated interrupts (as intended by the user)
6. Normal completion of asynchronous transfer.

An interrupt service routine is a program preloaded into the machine memory that
performs the following functions:

1. Disables further interrupts temporarily.

2. Saves the processor status (all registers).
3. Enables further interrupts.
4. Determines the cause of interrupt.
5. Services the interrupt.
6. Disables interrupts.
7. Restores processor status.
8. Enables further interrupts.
9. Returns from interrupt.

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Modes of Transfer

DIRECT MEMORY ACCESS (DMA)

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Direct Memory Access

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Direct Memory Access

The DMA controller is a piece of hardware that controls one or more peripheral devices. It
allows devices to transfer data to or from the system’s memory without the help of the
processor. In a typical DMA transfer, some event notifies the DMA controller that data needs
to be transferred to or from memory. Both the DMA and CPU use memory bus and only one
or the other can use the memory at the same time. The DMA controller then sends a request
to the CPU asking its permission to use the bus. The CPU returns an acknowledgment to the
DMA controller granting it bus access. The DMA can now take control of the bus to
independently conduct memory transfer. When the transfer is complete the DMA relinquishes
its control of the bus to the CPU.

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Direct Memory Access

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DMA H/W and Signals

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Typical DMA Operation

1. The processor initiates the DMA controller by identifying the I/O device and
supplying the memory address, byte count, and type of operation (input or
output). This is referred to as channel initialization. Once initialized, the
channel is ready for data transfer between the associated I/O device and
memory.

2. When the I/O device is ready to transfer data, it informs the DMA controller. The
DMA controller starts the transfer operation. This step consists of the following
substeps.
a) Obtain the bus by going through the bus arbitration process
b) Place the memory address and generate the appropriate read and write control
signals;
c) Complete the transfer and release the bus for use by the processor or other DMA
devices;
d) Update the memory address and count value;
e) If more bytes are to be transferred, repeat the loop from Step (a).

3. After completing the operation, the processor is notified. This notification is

done by an interrupt mechanism. The processor can then check the status of
the transfer (i.e., successful or failure).

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IOP

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Input/Output Processor

CHANNEL / CPU COMMUNICATION

CPU operations IOP operations

Send instruction
to test IOP.path
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP. Access memory
for IOP program

CPU continues with

another program Conduct I/O transfers
using DMA;
Prepare status report.

I/O transfer completed;

Interrupt CPU
Request IOP status

Transfer status word

Check status word to memory location
for correct transfer.

Continue

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IOP Types
• A Selector Channel controls several
devices, but handles transfers for a
single device at a time.

• A selector channel is typically used

for high speed devices like hard
disks.

• A multiplexor channel handles

transfers for several devices at a
time.

• A multiplexor channel comes in two

forms:

• a byte multiplexor, which interleaves

bytes from a number of low speed
devices into a single stream,

• block multiplexor, which interleaves

blocks from a number of high speed
devices into a single stream.

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