Input-Output Organization 1

INPUT-OUTPUT ORGANIZATION

• Peripheral Devices

• Input-Output Interface

• Asynchronous Data Transfer

• Modes of Transfer

• Priority Interrupt

• Direct Memory Access

• Input-Output Processor

• Serial Communication

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Input-Output Organization 2 Peripheral Devices

PERIPHERAL DEVICES

Input Devices Output Devices

• Keyboard • Card Puncher, Paper Tape Puncher
• Optical input devices • CRT
- Card Reader • Printer (Impact, Ink Jet,
- Paper Tape Reader Laser, Dot Matrix)
- Bar code reader • Plotter
- Digitizer • Analog
- Optical Mark Reader • Voice
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices

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Input-Output Organization 3 Input/Output Interfaces

INPUT/OUTPUT INTERFACE
• Provides a method for transferring information between internal
storage (such as memory and CPU registers) and external I/O
devices
• Resolves the differences between the computer and peripheral
devices
– Peripherals - Electromechanical Devices
– CPU or Memory - Electronic Device

– Data Transfer Rate

» Peripherals - Usually slower
» CPU or Memory - Usually faster than peripherals
• Some kinds of Synchronization mechanism may be needed

– Unit of Information
» Peripherals – Byte, Block, …
» CPU or Memory – Word

– Data representations may differ

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Input-Output Organization 4 Input/Output Interfaces

I/O BUS AND INTERFACE MODULES

I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

Each peripheral has an interface module associated with it

Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)

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Input-Output Organization 5 Input/Output Interfaces

I/O BUS AND MEMORY BUS

Functions of Buses

* MEMORY BUS is for information transfers between CPU and the MM

* I/O BUS is for information transfers between CPU
and I/O devices through their I/O interface

Physical Organizations
* Many computers use a common single bus system
for both memory and I/O interface units
- Use one common bus but separate control lines for each function
- Use one common bus with common control lines for both functions
* Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces
I/O Bus
- Communication between CPU and all interface units is via a common
I/O Bus
- An interface connected to a peripheral device may have a number of
data registers , a control register, and a status register
- A command is passed to the peripheral by sending
to the appropriate interface register
- Function code and sense lines are not needed (Transfer of data, control,
and status information is always via the common I/O Bus)
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Input-Output Organization 6 Input/Output Interfaces

ISOLATED vs MEMORY MAPPED I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations

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Input-Output Organization 7 Input/Output Interfaces

I/O INTERFACE
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

Internal bus
CPU Chip select CS
I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
- Information in each port can be assigned a meaning
depending on the mode of operation of the I/O device
→ Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register
→ Allows CPU can define the mode of operation of each port
→ Programmable Port: By changing the bits in the control register, it is
possible to change the interface characteristics
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Input-Output Organization 8 Asynchronous Data Transfer

ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations
Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted

Two Asynchronous Data Transfer Methods

Strobe pulse
- A strobe pulse is supplied by one unit to indicate
the other unit when the transfer has to occur

Handshaking
- A control signal is accompanied with each data
being transmitted to indicate the presence of data
- The receiving unit responds with another control
signal to acknowledge receipt of the data
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Input-Output Organization 9 Asynchronous Data Transfer

STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or
the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe

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Input-Output Organization 10 Asynchronous Data Transfer

HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data

Destination-Initiated

The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus

To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply
to the unit that initiates the transfer

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Input-Output Organization 11 Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit

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Input-Output Organization 12 Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
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Input-Output Organization 13 Asynchronous Data Transfer

ASYNCHRONOUS SERIAL TRANSFER

Asynchronous serial transfer
Four Different Types of Transfer Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
Asynchronous Serial Transfer
- Employs special bits which are inserted at both
ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.

1 1 0 0 0 1 0 1
Start Character bits Stop
bit bits
(1 bit) (at least 1 bit)

A character can be detected by the receiver from the knowledge of 4 rules;

- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected
by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when
the line returns to the 1-state for at least 1 bit time
The receiver knows in advance the transfer rate of the
bits and the number of information bits to expect
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Input-Output Organization 14 Asynchronous Data Transfer
UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER

A typical asynchronous communication interface available as an IC

Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock
register control

Internal Bus
and clock
Chip select
CS
Register select Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether
to generate and check parity, and no. of stop bits

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Input-Output Organization 15 Asynchronous Data Transfer

FIRST-IN-FIRST-OUT(FIFO) BUFFER
* Input data and output data at two different rates
* Output data are always in the same order in which the data entered the buffer.
* Useful in some applications when data is transferred asynchronously

4 x 4 FIFO Buffer (4 4-bit registers Ri),

4 Control Registers (flip-flops Fi, associated with each Ri)
R1 R2 R3 R4

Data 4-bit 4-bit 4-bit 4-bit Data

input register register register register output

Clock Clock Clock Clock

Insert

S F1 S F2 S F3 S F4
Output
F'4 ready
R F'1 R F'2
F R F'3 R

Input ready Delete

Master clear

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Input-Output Organization 16 Modes of Transfer

MODES OF TRANSFER - PROGRAM-CONTROLLED I/O -

3 different Data Transfer Modes between the central
computer(CPU or Memory) and peripherals; Program-Controlled I/O
Interrupt-Initiated I/O
Direct Memory Access (DMA)
Program-Controlled I/O(Input Dev to CPU)
Data bus Interface I/O bus
Address bus Data register
Data valid I/O
CPU I/O read device
I/O write Status Data accepted
register F

Read status register

Check flag bit

=0 Polling or Status Checking

flag
=1 • Continuous CPU involvement
Read data register
• CPU slowed down to I/O speed
Transfer data to memory • Simple
• Least hardware
no Operation
complete?
yes
Continue with
program

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Input-Output Organization 17 Modes of Transfer

MODES OF TRANSFER - INTERRUPT INITIATED I/O & DMA

Interrupt Initiated I/O
- Polling takes valuable CPU time
- Open communication only when some data has
to be passed -> Interrupt.
- I/O interface, instead of the CPU, monitors the I/O device
- When the interface determines that the I/O device is
ready for data transfer, it generates an Interrupt Request to the CPU
- Upon detecting an interrupt, CPU stops momentarily
the task it is doing, branches to the service routine
to process the data transfer, and then returns to the
task it was performing

DMA (Direct Memory Access)

- Large blocks of data transferred at a high speed to
or from high speed devices, magnetic drums, disks, tapes, etc.
- DMA controller
Interface that provides I/O transfer of data directly
to and from the memory and the I/O device
- CPU initializes the DMA controller by sending a
memory address and the number of words to be transferred
- Actual transfer of data is done directly between
the device and memory through DMA controller
-> Freeing CPU for other tasks

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Input-Output Organization 18 Priority Interrupt

PRIORITY INTERRUPT
Priority
- Determines which interrupt is to be served first
when two or more requests are made simultaneously
- Also determines which interrupts are permitted to
interrupt the computer while another is being serviced
- Higher priority interrupts can make requests while
servicing a lower priority interrupt

Priority Interrupt by Software(Polling)

- Priority is established by the order of polling the devices(interrupt sources)
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts
all the interrupt requests to determine the highest priority request
- Fast since identification of the highest priority
interrupt request is identified by the hardware
- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine
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Input-Output Organization 19 Priority Interrupt

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

Processor data bus
VAD 1 VAD 2 VAD 3 * Serial hardware priority function
Device 1 Device 2 Device 3 * Interrupt Request Line
To next
PI PO PI PO PI PO
device
- Single common line
* Interrupt Acknowledge Line
- Daisy-Chain
Interrupt request INT
CPU
Interrupt acknowledge
INTACK

Interrupt Request from any device(>=1)

-> CPU responds by INTACK <- 1
-> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus
Among interrupt requesting devices the only device which is physically closest
to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device
One stage of the daisy chain priority arrangement
Priority in VAD
PI Enable
Vector address
Interrupt Priority out PI RF PO Enable
RF PO 0 0 0 0
request S Q
from device 0 1 0 0
R 1 0 1 0
1 1 1 1
Delay

Interrupt request to CPU

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Input-Output Organization 20 Priority Interrupt

PARALLEL PRIORITY INTERRUPT

Interrupt register Bus
Buffer
Disk 0 I0 y
Printer 1 I1 x
Priority 0
Reader 2 I 2 encoder
0 VAD
Keyboard 3 0 to CPU
I3
0
0
0 IEN IST
0
Mask
register 1 Enable

2
Interrupt
to CPU
3
INTACK
from CPU
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred. INTACK enables
tristate Bus Buffer to load VAD generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from
different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
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Input-Output Organization 21 Priority Interrupt

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt when

more than one interrupts take place

Priority Encoder Truth table

Inputs Outputs
I0 I1 I2 I3 x y IST Boolean functions
1 d d d 0 0 1
0 1 d d 0 1 1
0 0 1 d 1 0 1 x = I0' I1'
0 0 0 1 1 1 1 y = I0' I1 + I0’ I2’
0 0 0 0 d d 0 (IST) = I0 + I1 + I2 + I3

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Input-Output Organization 22 Priority Interrupt

INTERRUPT CYCLE

At the end of each Instruction cycle

- CPU checks IEN and IST
- If IEN  IST = 1, CPU -> Interrupt Cycle

SP SP - 1 Decrement stack pointer

M[SP]  PC Push PC into stack
INTACK  1 Enable interrupt acknowledge
PC  VAD Transfer vector address to PC
IEN  0 Disable further interrupts
Go To Fetch to execute the first instruction
in the interrupt service routine

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Input-Output Organization 23 Direct Memory Access

DIRECT MEMORY ACCESS

* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between
Memory and Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory
address and the block size(number of words)
CPU bus signals for DMA transfer


ABUS Address bus High-impedence
Bus request BR DBUS Data bus (disabled)
CPU when BG is
Bus granted BG RD Read
WR Write enabled

Block diagram of DMA controller

Address bus

Data bus Data bus Address bus

buffers buffers
Internal Bus

DMA select DS Address register

Register select RS
Read RD Word count register
Write WR Control
logic
Bus request BR Control register

Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device

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Input-Output Organization 24 Direct Memory Access

DMA TRANSFER

Interrupt
Random-access
3 BG
CPU memory unit (RAM)
BR
2
RD WR Addr Data RD WR Addr Data

5 Read control
bg = 1
5 Write control
4
Data bus
Address bus
7
Address 4
select bg = 0

RD WR Addr Data
DS DMA ack. 6

RS DMA I/O
2 Controller Peripheral
BR device
3 1
BG DMA request
Interrupt

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Input-Output Organization 25 Input/Output Processor

INPUT/OUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability

that communicates with I/O devices
- Channel accesses memory by cycle stealing
- Channel can execute a Channel Program
- Stored in the main memory
- Consists of Channel Command Word(CCW)
- Each CCW specifies the parameters needed
by the channel to control the I/O devices and
perform data transfer operations
- CPU initiates the channel by executing an
channel I/O class instruction and once initiated,
channel operates independently of the CPU
Central
processing
unit (CPU)
Memory Bus

Peripheral devices
Memory
unit PD PD PD PD

Input-output
processor
(IOP) I/O bus

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Input-Output Organization 26 Input/Output Processor

CHANNEL / CPU COMMUNICATION

CPU operations IOP operations

Send instruction
to test IOP.path
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP. Access memory
for IOP program

CPU continues with

another program Conduct I/O transfers
using DMA;
Prepare status report.

I/O transfer completed;

Interrupt CPU
Request IOP status

Transfer status word

Check status word to memory location
for correct transfer.

Continue

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