High Accuracy Electronics Christopher I Daykin

Part 0: Acknowledgements and preface
High Accuracy Electronics
(at room temperature)
Faraday’s toroidal transformer – the first on record (Picture courtesy of IET)
A collection of monographs on inductive voltage dividers, ratio transformers and

related circuits plus some nice maths
Version 1.0 (May 2020)
Christopher I. Daykin MA
1
High Accuracy Electronics V1.0
Acknowledgements
For Di, with sincere thanks, in memory of John David Yewen FRAS (JDY): friend and former colleague. “Hairy”
John taught me the art of engineering and deserves most of the credit for the ingenious designs herein.
Thanks, also, to former ASL colleague: Peter Caleb Frederick Wolfendale FIEE [1].
Other contributions came from: -

 Don White [2] for extensive and valuable input on high accuracy resistors and guidance on publishing in
general.
 Paul Bramley [3] for feedback on the monograph: The Isotech MicroK “Bridge”.
 Professor Stephen Donnelly [4], for encouraging me to publish “for the benefit of mankind”.
Thank you, also, Isothermal Technology Ltd and WIKA Alexander Wiegand SE & Co. KG for your permission to
include certain images.
Thanks guys!
More feedback would be appreciated.
1. Inspirational founder and former Managing Director of Automatic Systems Laboratories Ltd.
2. Measurement Standards Laboratory of New Zealand and co-inventor (with Keith Jones) of the
resistance bridge calibrator (RBC) - one of the most significant contributions to this field in recent
years (Patent: PCT/NZ95/00022). See part 1, monograph 1, section 4.3 and 4.3.2
3. Metrosol Ltd and Project Manager of the MicroK Bridge design team.
4. University of Huddersfield and a genuine scholar.
2
Part 0: Acknowledgements and preface
Preface
“High Accuracy” in the title refers to measurement uncertainty in the range of ten parts per million (10ppm) to ten
parts per billion (10ppb). The subtitle “at Room Temperature” emphasises the fact that this level of accuracy is
possible with readily available components, materials and tools. Whereas greater accuracy can be achieved at very
low (cryogenic) temperature, such techniques are very expensive. A bridge based on the (superconducting)
cryogenic current comparator [1], for example, exploits the Meissner effect and uses a superconducting quantum
interference detector (SQUID) [2] to measure the ratio of resistors to better than 10ppb.
This collection is aimed, primarily, at students, teachers and researchers in the physical sciences. Some of the
content could, for example, form the basis of a module at first degree (final year) level in electronic engineering.
More advanced topics are suited to a Masters level course in metrology or instrumentation. Researchers could
apply some of the techniques and practical tips to construct cutting edge instrumentation at minimal cost.
Part 1 introduces the concepts of accurate lumped impedance: resistors and capacitors at low frequency. Three-
terminal capacitors, for example, can be constructed for which the AC version of Ohm’s law is accurate to within a
few parts per billion. The theory is underpinned by Maxwell’s field equations, surely one of the greatest scientific
achievements of the nineteenth century, if not of all time.
The fundamental mechanism that gives rise to the concept of resistance, on the other hand, is much more
complicated. Fortunately we have decades of technological development and empirical evidence, at low frequency,
to underpin our faith in Ohm’s law, at least to the level of 10ppb, for many types of materials and components.
Part 2 also deals with (mainly) passive components – in circuits to form high accuracy filters. These are not only
useful but also instructive - the models developed and “nice” matrix maths is applied in later monographs (for the
analysis of two and three-stage inductive voltage dividers and ratio transformers).
Parts 3 and 4 are the core of the collection: inductive voltage dividers (IVDs), ratio transformers (RTs) and related
accurate circuits, especially the “inside-out” high accuracy voltage follower (HAVF). A review of basic principles
is provided for students but the advanced specialist may also find some useful ideas which have remained
unpublished for over 35 years.
Parts 5 and 6 are concerned with other circuits which, despite not being inherently accurate, are indispensible. A
well matched low noise pre-amplifier and filtering for potentially large amounts of interference are, for example,
essential ingredients of a good null detector. Included in the miscellany are a couple of unusual circuits which may
not be found in any text book or application note: A simulated large capacitor and a simulated negative capacitor
are further examples of JDY’s ingenuity.
Most of the content should be uncontroversial but there are a few notable exceptions. This author “begs to differ”
with the generally accepted definition of a four-terminal-pair lumped impedance [3]. An alternative is proposed.
Also, the term “Bridge” as in [4] is debatable; The MicroK “Bridge” is based on a high accuracy analogue to digital
converter (ADC) with 10ppb linearity. An attempt is made to explain how this incredible performance is achieved.
Similarly, the HP3458A digital multi-meter (DMM) is based on a proprietary “multi-slope” ADC technique. Much
of its workings remain “trade secret”. The theory here is based on scraps of published information [5].
Some of the content is speculative – novel but untested designs. The interested reader is encouraged to contact the
author (email: hiaccelectronics@gmail.com).
1. Seppä, H. and Satrapinski, A.: “AC Resistance Bridge Based on the Cryogenic Current Comparator”.
IEEE Trans. on Inst. & Meas., Vol. 46, No 2, April 1997.
2. A SQUID can detect extremely low levels of magnetic flux density (typically  3 aT Hz ).
3. Part 1, Monograph 1, section 2.1.
4. Part 4, Monograph 4: The Isotech MicroK “Bridge”.
5. Part 4. Monograph 5: The 3458A general purpose digital multi-meter.
3
CONTENTS
Part 1: High accuracy passive components
Monograph 1: High accuracy resistors
1. Introduction
2. Three-terminal resistors (two terminals plus screen)
2.1 Converting to a four-terminal pair resistor
3. Two-terminal-pair resistors
3.1 Analysis of parallel capacitance with quadrature balance
3.1.1 Example calculation
3.2 Analysis of parallel capacitance without quadrature balance
3.3 Quadrature due to series inductance
3.4 Two-terminal-pair zero-Ohm junctions
4. Two-terminal-pair resistor networks
4.1 Introduction
4.2 Balancing (potential sharing) resistors
4.3 Resistance bridge calibrators
4.3.1 The Hamon “build-up” network
4.3.2 The White/Jones resistance bridge calibrator
5. Four-terminal-pair resistors
5.1 Example calculations
5.1.1 Cable phase and magnitude errors
5.1.2 Zero-Ohm junction errors
5.1.3 HGB error voltage
5.1.4 Resistance in cable 4
5.2 4TP resistors with calculable quadrature
6. Johnson Noise
Monograph 2: High accuracy single capacitors

1. Introduction
2. Transfer standard air capacitors
3. Basic principles
4. The Thompson Lampard calculable capacitor
5. Industry standards
Monograph 3: Rotary capacitive displacement transducers

1. Introduction
1.1 The two main types
1.2 The basic principle of operation
2. Ratiometric operation
3. The charge amplifier
4. The cylindrical type transducer
5. Plate type transducers
5.1 A low cost limited angle example
5.2 A multi-segmented design
6. Low cost signal conditioning
7. Noise analysis
Monograph 4: Linear Capacitive Displacement Transducers

1. Introduction
1.1 The principle of operation
4. A low cost signal conditioner
5. Noise analysis
Monograph 5: Variable gap capacitive displacement transducers
1. Introduction
1.1 Profile measurement
2. The guard electrode and charge amplifier
2.1 The charge amplifier
3. The Ratio transformer/capacitance bridge
3.2 Earthing the target surface
4. Noise analysis
Monograph 6: Low phase error capacitors and inductors

1. Introduction
2. Polypropylene capacitors
3. Low phase error ferrite transformers
3.1 Example calculation
3.2 A practical differentiator circuit
Appendix: Magnetic circuit theory (basics)
Part 2: High Accuracy Filters

Monograph 1: Two-stage filters
1. Introduction
2. Two-stage low pass filters
2.1 Network analysis
2.2 A basic two-stage low pass filter
2.2.1 Phase shift at low frequency
2.3 Different values of resistors and capacitors
2.3.1 Example calculation: The minimum a  2
2.3.2 Example calculation 2: For a relatively high value a  4
2.3.3 Widely different values for resistors and capacitors
3. Actively driven low pass filters
3.2 Equal resistor and capacitor values
3.4 Widely different values of resistors and capacitors.
4. Two-stage high pass filters
4.2 A basic two-stage low pass filter
4.2.1 Phase shift at high frequency   N 
4.2.2 Equal resistor and capacitor values
5. Actively driven two-stage high pass filters
5.1 Circuit analysis
5.1.1 Phase error at high frequency
5.4 Widely different values of resistors and capacitors
5.5 Input impedance
6. An LCR low-pass filter with two-stage response
6.1 Introduction
6.3 Output impedance
2
Part 0: Contents
Monograph 2: Three-stage filters

1. Introduction
1.2 Cramer’s Rule
2. Actively driven three–stage bootstrapped high pass filter (type 1)
2.2 A basic type 1 filter
2.4 Errors at high frequency   N 
2.4.1 An interesting result
2.5 Calculating component values
3. Actively driven three–stage high pass filter (type 2)
3.5 Input impedance
Appendix 1: Cramer’s method for matrix inversion (Three-stage high-pass network)
Appendix 2: Calculating the determinant (Three-stage high-pass network)
Appendix 3: Calculating transfer functions
Appendix 4: Slide rule calculator for RC combinations
Monograph 3: An ultra-high input impedance high pass filter

1. Introduction
2. Outline design proposal
3. A low cost version
Part 3: Inductive Voltage Dividers and Ratio Transformers

Monograph 1: IVDs and RTs – the basics
1. Introduction
1.1 Applications
1.2 Leakage flux
1.3 Winding schemes
1.3.1 The “no-net-loop” (NNL) method
1.3.2 The “balanced no-net-loop” (BNNL) method
1.3.3 The NNL and BNNL methods applied to low number of turns of energising windings.
2. The basic inductive voltage divider
2.1 Multi-decade IVDs
2.2 The two-stage IVDs
2.3 The two-stage IVD with high accuracy voltage followers
3. The basic ratio transformer
4. The three-stage ratio transformer (e.g. ASL model F17)
5. An advanced three-stage ratio transformer (e.g. ASL model F18)
6. A three-stage current transformer (NPL’s “Knight” bridge)
7. Kusters’ comparator (e.g. Guildline model 6622T )
8. The double balanced potentiometer (e.g. The ASL “Cryo-bridge” [1])
3
Monograph 2: Single-stage inductors and transformers
1. Introduction
2. Calculating impedance from basic parameters
3. High levels of flux density and core saturation
4. Basic transformer theory
4.1 Current transformers
4.2 Voltage transformers
4.3 Input impedance
4.5 Capacitive load impedance
4.6 A single-stage resistance bridge
5. Inductive voltage dividers (auto-transformers)
6. Equalising windings
Appendix 1: Toroidal core data courtesy Telcon
Appendix 2: Copper wire data.
Monograph 3: Two-stage IVDs and RTs

1. Two-stage IVDs
2. Two-stage transformers
3. The matrix method and the equivalent circuit
4. Two-stage active drive and stability
4.1 Active drive for both primary windings
4.2 Active drive for the energising winding only
4.2.1 Network analysis
4.2.2 Stability analysis (approximate)
4.2.4 Errors in the energising follower
4.2.5 Follower noise
4.2.6 The effect on input impedance
4.3 Active drive with compensator (resistor/parallel capacitor)
4.3.1 Error analysis with compensator
4.3.3 Spreadsheet simulation
4.4 Extra turns around the top core
5. Loading effects
5.1 Loading the energising core
5.1.1 The effect on energising accuracy of loading the energising secondary
5.1.2 Loading the energising core and its effect on ratio accuracy
5.2 Loading the ratio secondary
7. Energising from the secondary
Appendix 1: Toroidal core data courtesy Telcon and copper wire data.
Appendix 2: detailed equation bashing (see section 4.3): -
Appendix 3: the inverse of a 3 × 3 matrix
4
Part 0: Contents
Monograph 4: Three-stage RTs

1. Introduction
1.1 The effects of follower errors, noise, loading and equalisation of windings
2. Active drive for all three primary windings
2.1 Input currents and impedances
2.2 The transfer function
3. Active drive for energising windings only
3.1 The importance of source resistance
3.2 Active drive with compensator
3.2.1 Error analysis
Appendix 1: Equation bashing
Monograph 5: Noise matching transformers

1. Introduction
2. A single-stage transformer
3. A possible two-stage transformer
3.1 Outline design
Appendix: Toroidal core data courtesy Telcon and copper wire data
Monograph 6: An F17 type ratio transformer bridge

1. Introduction
1.2 Active guard circuit
2. The main ratio transformer [2]
3. Quadrature servo and null detector
Monograph 7: An F18 type ratio transformer bridge

1. Introduction
2. The basic principle of operation
3. Active guard circuit
4. The divider
4.1 The ratio transformer 1 (decades 1 and 2)
4.3 The resistive multiplying R-2R DAC
6. Manual “tweeks”
6.1 The ratio tweek
6.2 The input impedance tweek
Monograph 8: A 16 bit binary differential capacitance bridge

1. Introduction
2. Design details [1]
2.1 The single stage ratio transformer (RT1)
2.2 The two-stage inductive voltage divider (RT/IVD2)
2.4 The MDAC
5
Work in progress: -
Monograph: 9_Coaxial AC bridges
Monograph: 10_A quadrature bridge
6
Part 0: Contents
Part 4: High accuracy active circuits

Monograph 1: High gain blocks
1. Introduction
2. Feedback, stability and accuracy (general theory)
2.1 The closed loop transfer function
2.2 The Bardayquist stability criterion.
2.3 Phase margin
2.4 The size of the resonant peak
3. Some operational amplifier circuits
3.1 Operational amplifiers
3.1.1 Op-amp models
3.2 The integrator
3.3 The one-plus-integrator (OPI)
3.4 The non-inverting amplifier and voltage follower
3.5 The inverting amplifier
3.6 A voltage follower with external compensation
3.7 An advanced OPI2
4. Multi-stage HGBs – some practical circuits
4.1 Type 1 HGBs
4.2 A type 2 two-stage HGB
Monograph 2: High accuracy voltage followers (HAVFs)

1. Introduction
2. Theory of operation
2.1 The limitations of a conventional voltage follower
2.2 Common mode rejection and the “inside-out” configuration
2.3 The floating power supply (FPSU)
2.4 Closed loop transfer functions
2.5 Error analysis
3. Power supply and signal wiring.
4. Measuring the accuracy of an inside-out follower
5. Stability considerations
6. Practical circuits
6.1 A two-stage HAVF
6.2 A three stage HAVF with low noise front end
6.3 A low cost follower with moderately high accuracy
7
Monograph 3: High accuracy amplifiers, integrators and differentiators
1. Introduction
2. General analysis
3. High accuracy amplifiers
3.2 Error analysis
4. High accuracy integrators
4.2 Error analysis
5. A high accuracy differentiator
5.2 Error analysis
6. A high gain differential amplifier
6.2 Errors due to resistor tolerance
6.3 Example application and calculations
Monograph 4: The Isotech microK “bridge”

1. Introduction
2. The microK measurement system (overview)
2.1 Introduction
2.2 Voltage (thermocouple) measuring mode
2.3 Resistance ratio measuring mode
3. The voltage controlled (ultra-constant) current source
4. The differential amplifier
5. The sigma-delta ADC
5.1 Overview
5.2 The summing junction and high gain block
5.3 The flash ADC and pulse width modulator
6. Feedback and comment from Paul Bramley
6.1 Noise performance
6.2 Performance compared to conventional null balance bridges
6.3 Is it a bridge?
6.4 Timing accuracy
6.5 Reversal frequency and 1/f noise
6.6 Master reference voltage device
6.7 The differential amplifier
6.8 Elimination of amplifier offset and thermal emfs
6.9 The need for certain components to have very good short term stability
6.10 The measuring currents are proportional to a master internal reference voltage, VREF, probably via a
12-bit multiplying digital to analogue converter
6.11 The current regulator
6.12 Is the current regulator second stage a “cascode” stage?
6.13 Suggested alternative design (Fig. 3.7): -
6.15 Bootstrapped PSU
6.16 The ADC
6.17 Further comments from PB
Appendix: More analysis of the microK sigma-delta ADC
8
Part 0: Contents
work in progress: -
Monograph 5: Multislope ADCs
9
Part 5: Null detector circuits

Monograph 1: Null detectors – the basics
1. Introduction
2. Low noise pre-amps
2.1 A basic pre-amp noise model
2.2 Amplifiers in parallel
2.3 Noise matching transformers
2.4 Charge amplifiers
3. AC gain and filtering
4. Synchronous rectifiers
4.1 The quad FET switch
4.2 Rejection of Noise and Interference
4.3 Output ripple
5. Low-pass filters
5.1 A combined low-pass/notch filter
5.2 A bridge as part of a control system
6. The quadrature servo
6.1 In-phase and quadrature
6.1.1 Example calculation: -
6.2 A practical quadrature servo
6.3 The servo as a control loop
Appendix 1: Basic noise theory
A1.1. Johnson noise
A1.2. Low noise pre-amps
A1.3 Optimum noise matching
A1.4. Some notes on Nyquist’s theory
Appendix 2: Band-pass filter analysis
A2.1 The transfer function
A2.2 Bandwidth
Appendix 3: Low-pass/notch filter analysis
A3.1 The basic low-pass filter
A3.2 A basic band-pass filter
Monograph 2: Low noise BJT pre-amplifiers

1. Introduction
2. A review of basic BJT theory (low frequency)
2.1 Current gain and output conductance
2.2 Base current
2.3 Emitter output resistance
2.4 BJT noise performance
3. Analysis of the long tail pair
3.1 Voltage gain
3.2 Differential input resistance
3.3 Common mode rejection (mismatched resistors)
3.4 Common mode rejection (mismatched transistors)
3.5 Input offset voltage and temperature coefficient
4.1 A basic current regulator
4.2 A fully differential pre-amp
4.3 A pre-amp with feedback
4.4 A low noise stage for an HAVF
4.4.1 Stability and the snubber
10
Part 0: Contents
4.5 A useful variant
Monograph 3: Low noise JFET pre-amplifiers

1. Introduction
2. The long tail pair
3. A differential source follower4. An ultra-low input current pre-amplifier
5. Charge amplifiers
5.1 Op-amp based charge amplifiers
5.2 A charge amplifier with long tail pair front end
5.3 A charge amplifier with source followers.
5.4 An ultra-low leakage charge amplifier
6. Transducers incorporating a charge amp or single JFET
Appendix: Long-tail pair theory
A1. Voltage gain
A2. Common mode rejection ratio
A2.1 Mismatched drain resistors
A2.2 Mismatched JFETs
A3. The long-tail pair in VCR mode
11
Monograph 4: JFET theory
1. Introduction
2. The theory
2.1 Basic theory of the PN junction
2.2 The model
2.3 Drain-source on resistance
2.4 Voltage controlled resistor mode
2.5 The general case
2.6 Pinched-off mode
2.7 Deviation from the model
2.8 Design rules of thumb
3. JFET noise performance
3.1 The basic model
Part 6: Miscellaneous circuits

Monograph 1: A simulated large capacitor circuit
1. Introduction
2. Basic analysis
3. Errors due to limited gain-bandwidth product
4. Practical considerations
Appendix 1: Error analysis (due to limited gain-bandwidth product)
Appendix 2: Snubber example calculations
Monograph 2: A simulated negative capacitor circuit

1. Introduction
1.1 The scale of the problem
2. Basic circuit analysis
3. A circuit with a simple first order filter
4. A circuit with a two-stage filter
4.2 A check on the output impedance
4.3 A practical circuit
Monograph 3: A circuit for measuring tanδ.

1. Introduction
1.1 The general complex representation
2. A practical circuit
2.1 Analysis of the borderline oscillator circuit (BOC)
2.2 Results (sustained oscillation method)
2.3 Results (decaying sinusoid method)
3. Some nice maths
4. A prototype
5. A voltage controlled high Q filter/oscillator
6. Compensating for tanδ
12
Part 1: Monograph 1
High accuracy resistors

1. Introduction
The world’s most accurate resistors are based on the (cryogenic) quantum Hall effect and beyond the scope of this
collection. Fortunately it is possible to construct practical (room temperature) resistors and resistive sensors which
obey Ohm’s law (within limits) with an accuracy approaching 1ppb. For the highest accuracy, however, operating
temperature must be controlled (including self-heating) to within ±0.01°C or better.
High accuracy resistors are constructed in three principal ways, depending on the resistor value and the length of
the connecting leads. The main issues are resistance and capacitance of the connecting leads, series inductance of
the resistor and the importance of phase error for the particular application: -
The three types are: -

1. Single-terminal-pair (1TP, sometimes referred to as “two-terminal-pair” resistors [1]).
2. Two-terminal-pair connection (2TP, sometimes referred to as “four-wire” or “Kelvin” connection).
3. Four-terminal-pair connection (4TP).
The first method is appropriate for high value resistors where the lead resistance is negligible. Parallel capacitance
and electrical interference may be a problem in which case the resistor and connections need to be screened. The
main application is transfer standards and high accuracy circuits (e.g. amplifiers, integrators and oscillators).
The second method is appropriate for low to medium value resistors where the lead resistance is significant. One
pair delivers the current while the other pair is used to measure the voltage. Bridge techniques can distinguish
between the in-phase and quadrature (real and imaginary) components of impedance and a small phase error (e.g.
due to parallel capacitance of the leads or series inductance) is not usually a problem. Clearly, however, the size of
the problem increases with frequency and high accuracy resistors and measurement techniques are designed to
operate at low (or very low) frequency (sinewave or alternating DC). Very low frequency measurement is severely
limited by thermal emfs and 1/f noise and so low frequency (10Hz – 1kHz) sine wave methods remain popular. The
main applications are transfer standards and resistance thermometry.
Current carrying terminals
Voltage sensing terminals
Fig. 1.1 The “Wilkins” type transfer standard 2TP resistor

(designed for immersion in a temperature controlled bath of mineral oil - courtesy ASL U.S.)
The third type is the ultimate method, for the very highest accuracy, reducing the effect of lead capacitance. The
main application is for medium to high value transfer standards.
1. Awan, S., Kibble, B., and Schurr, J: “Coaxial Circuits for Interference-free Measurements” Electrical
Measurements Series 13 published by the IET. www.theiet.org. For a different perspective see chapter 5
“General Principles of Accurate Impedance Measurement”. For “two-terminal–pair” see section 5.3.6.
1
2. Single-terminal-pair plus screen
If the resistance value is high, compared to the connecting leads, then a single pair of connections is all that is
required. Interference from electric and magnetic fields can be an issue but a screen around the resistor (fig. 2.1a)
and coaxial connections provide a simple solution (see, also, fig.2.4). It can easily be arranged that the screen/outer
conductor is at local 0V, at least approximately, with low impedance to “earth” (fig. 2.1a). The screen can also
provide the route for the return current in order to minimise external magnetic flux - the electric and magnetic
fields are contained within the coax cable (fig. 2.1b).
Screen Screen
a) or b)
Fig. 2.1 A screened resistor
Commercially available miniature component resistors, while not quite matching the long term stability of the
Wilkins type, have excellent temperature stability and AC characteristics. Single resistors, matched pairs and
networks with an initial tolerance of ±0.01% and temperature coefficients <1ppm/°C (20-30°C) are readily
available.
Fig. 2.2 High accuracy component resistors (picture courtesy Vishay Precision Group, Inc)
With pairs, triples and networks the accuracy and stability of ratio can be even better: -
Fig. 2.3 High accuracy 100:1 ratio resistor pair (courtesy Caddock Inc.)
The main applications are transfer standards and accurate amplifiers and integrators [1].
1. Part 4, Monograph 3: “High accuracy amplifiers, integrators and differentiators”.
2
Part 1: Monograph 1
One simple method for eliminating the effect of interference and stray capacitance (across the resistor) is to connect
one terminal to a virtual earth with the screen connected to 0V. An overall 0V screen around the high gain block
front-end may also be necessary: -
R1 R2
VIN
VOUT
HGB
Virtual earth
0V
0V
Fig. 2.4 High accuracy inverting amplifier with screened resistors [1]
If the resistor is at the end of a pair of coaxial cables the outer conductors (screens) should not be connected
together at the resistor end. If they are connected the current flowing through C1 (signal input side) can develop a
small voltage drop down the screen resistances (R1 and R2 in parallel) which then injects an in-phase current* into
the virtual earth via the cable capacitance C2: -
Resistor
coax cable coax cable Virtual
VIN earth
C1 C2
R1 R2
Screen break here
Fig. 2.5 Simplified equivalent circuit of a remote resistor
Magnetic interference can be kept to a minimum by routing a pair of coaxial cables together as a twisted pair. Any
stray AC magnetic flux passing through a loop formed by the cables induces a voltage which is added in series with
the resistor. Thin and flexible coax cable with a less than perfect screen (c.f. earphone cables) may be better, in
practice, than the more usual kind of high quality (less flexible) type. The twisted pair could always be routed
through a flexible metal conduit, connected to local 0V, if electric field interference is a particular problem.
*Such a current can also be eliminated with a high accuracy voltage follower/active guard [2]: -
VIN
HGB
Fig. 2.6 An active guard circuit
(Caution – this method involves an amount of positive feedback, depending on VIN source resistance)
1. Part 4, monograph 3: “High accuracy amplifiers, integrators and differentiators”.

2. Part 4, monograph 2: “High accuracy voltage followers (HAVFs)”. See section 1.
3
2.1 Converting a single to a four-terminal-pair resistor
For the very highest accuracy some experts advise that the effect of lead resistance can be significantly reduced by
adding coaxial T-connectors physically close to the device [1]. This is then “regarded” as a four-terminal-pair
resistor. The result is described as a complex network (fig. 2.1.2), conforming to the generally accepted definition,
though they do not include the resistance of the screen in the diagram. This must be included, therefore, in the
defining parameter Z (see section 5).
Fig. 2.1.1 Converting a 1TP plus screen into a 4TP (courtesy Awan et al)
Fig. 2.1.2 Equivalent circuit of fig. 2.1.1 (courtesy Awan et al)
This author begs to differ!

1. The device in fig. 2.1.1 is, in effect, a two-terminal-pair resistor with screen (see the next section).
2. It is far better to break the screen connection thus avoiding the problem cited in the previous section. The return
current is best routed via another conductor.
3. If it is unavoidable that the screen must carry the return current then it is important that the screen/connector
resistances are as small as possible.
4. If the manufacturers don’t know any better the experts should advise them accordingly.
A more satisfactory definition of a four-terminal-pair is offered in section 5.
This topic and the issues of “earth loops” and “chokes” are explored in the monograph “Coax AC bridges” [2]
1. According to Awan et al (see footnote page 1): “Many standard impedances made and sold for
measurements of the highest accuracy have two-terminal-pair terminations, and no information is available
for the length or impedance and shunt admittance of the internal cables between the impedance itself and
these terminations. To improve their electrical definition, T-connectors can be added at the terminations.
The impedance can then be regarded as being defined as a four terminal pair having its internal defining
points at these T-connectors.”
2. Part 3, monograph 9: “Coaxial AC bridges”.
4
Part 1: Monograph 1
3. Two-terminal-pair resistors
Most applications are for low to medium resistance measurement (1 - 1000Ω). Lead resistance is not negligible and
so an extra pair of voltage sensing connections is required. The effect of resistance in the current carrying pair is
eliminated as long as the current flowing in the voltage sensing leads is negligible. In most applications the effect
of resistance in the connecting leads is insignificant and so they are not usually shown: -
I
V V
I
Equivalent circuit Circuit symbol
Fig. 3.1 2TP connections
For high accuracy each pair needs to be co-axial or tightly twisted. This ensures that the magnetic flux transmitted
from the current carrying pair and the voltage induced in the voltage sensing pair by any stray flux are kept to a
minimum.
A typical bridge configuration is to use some kind of multiplier with sufficiently high input impedance (e.g. an
actively energised ratio transformer). The null balance ensures that no current flows in the voltage connections
from RT: -
CS VQ
RS VS
VD D
I
0V
RT VT
CT
Fig. 3.2 A typical bridge configuration for 2TP resistors
The main issue with two-terminal-pair resistors is the effect of parallel capacitance. One metre of coaxial or twisted
pair cable typically represents 100pF of capacitance. The two pairs act in parallel and so the total capacitance is
roughly 200pF per metre of connecting cable.
The real part (in-phase) is balanced by the main ratio device – usually a very accurate ratio transformer or similar.
The imaginary part (quadrature) is relatively small and balanced by a quadrature servo [1].
1. Part 5, monograph 1: “Null detectors – the basics”.
5
3.1 Analysis of parallel capacitance with quadrature balance
The quadrature servo adds a signal to the output of the ratio transformer so that a null is achieved to both in-phase
and quadrature components: -
VD  aVS  VT  VQ  0
NS
a is the transformer ratio setting. The phase error of a ratio transformer is usually much smaller than that due
NP
to the parallel capacitance and is simply added to it – equivalent to a small change in the capacitance. The second
order term (in-phase error) is negligible. One can assume, therefore, that a is a real number.
It is shown elsewhere [1] that a practical approach is to derive the quadrature servo signal from VS: -
VQ  jbVS  VD  a  jb VS  VT
VT
VD  0   a  jb
VS
Define parameters:  S  C RS CS and T  C RT CT . Both are small (typically <0.1mrad or 100ppm).
RT 1  j S R  1   ST  R   
With a little algebra: a  jb    a  T   and b  T  S 2T 
RS 1  jT RS  1  T2  RS  1  T 
Values for the quadrature components are typically <100ppm so that the effect on accuracy can be reduced to less
than 10ppb.
For the very highest accuracy it is quite simple to add capacitance or, better still, matching cable to one side or the
other so that the quadrature imbalance is reduced to almost zero. To a very good approximation, therefore: -
and b  T  S  T 
RT R
 S  T and  S  1 and T  1  a 
RS RS
Matching cable is the better choice because any loss factor (“tan(δ)”) of the dielectric, equivalent to a small
imaginary component for both  S and T , is the same for both numerator and denominator.
 S  T and  S   S 1  j  and T  T 1  j   a 
RT
RS
RS  25 with 1 metre of cable CS  200 pF  ; RT  100 at the end of 5 metres of cable CT  1nF  at an
operating frequency of 75Hz (   2f  471 radians per second).
 S  471 25  2  1010  2.4  106 T  471 100  109  4.7  105
a
 2.2  10 9 (2.2ppb and negligible)
a
1. Part 5, monograph 1: “Null detectors – the basics”. See section 6.1.
6
Part 1: Monograph 1
3.2 Analysis of parallel capacitance without quadrature balance
One of the main reasons for a quadrature balance is the necessity for filtering in the null detector. This usually
consists of a band pass filter at the operating frequency combined with notch filters at power supply frequency
harmonics. The filtering can introduce phase shift and any quadrature component in the out-of balance signal
appears, at the phase sensitive detector, as an in-phase error. The result is an error in the in-phase balance. In less
demanding applications, with low levels of both quadrature and interference expected, there may be no need for a
quadrature balance, in which case any phase error in the null detector needs to be kept low, as the following
analysis shows: -
Define the phase shift in the null detector:  D . The effect is equivalent to multiplying the bridge output by the
phase factor exp  j D   cos D   j sin D  .
 aR1 R2 
VOUT  cos D   j sin  D   
 1  j1 1  j 2 
The phase errors of the resistors are very small but the null detector phase error may not be negligible. One can
make only the following approximation: -
1 and  2  1  VOUT  cos D   j sin D aR1 1  j1   R2 1  j 2 
The bridge ratio, a, is adjusted so that the real part is zero.
ReVOUT   0  aR1cos D   1 sin D  R2 cos D    2 sin D   0
R2  cos D    2 sin  D   R2  1   2 tan D  

a    
R1  cos D   1 sin  D   R1  1  1 tan D  
The result is exact if the detector phase error is zero and/or if the resistor phase errors are the same.
To a useful degree of accuracy, assuming small phase errors: -
 1   2  1  D 
R2
1 ,  2 and  D  1  a
R1
a
The proportionate error is, therefore:   2  1  D
a
If one uses the same example as above with a null detector phase error of about 0.1 radians: -
1  2.4rad  2  47rad and tan D   0.1
a
 4.5 ppm
a
Clearly a bridge without a separate quadrature balance can only cope with a small amount of quadrature imbalance.
7
3.3 Quadrature due to series inductance
With low value resistors the problem is often the series inductance. Extra care needs to be taken in the construction
of low value resistors to keep the self-inductance and mutual inductance (between the current carrying pair and the
voltage sensing pair) as low as possible.
R L
Fig. 3.3.1 Equivalent circuit
The impedance is: Z  R  jL
The phase error is now positive and inversely proportional to the resistance: -
 L  L
  arctan  in radians
 R  R
The analysis is otherwise the same as with quadrature due to parallel capacitance.
8
Part 1: Monograph 1
3.4 Two-terminal-pair zero-Ohm junctions
The basic idea of a zero-Ohm junction (ZOJ) is that current passing through one pair of connections results in
negligible voltage developed across the other pair. In practice a junction resistance as low as a few nΩ is possible.
They are useful in the construction of two-terminal-pair resistor networks (see section 4) and four-terminal-pair
resistors (see section 5). The most basic type (type 1) is easy to construct (with bits of wire): The current carrying
pair and the voltage sensing pair are physically separated by a low value resistor. The pairs are interchangeable
V  I  but may not be mixed. Type 1 junctions are used in four-terminal-pair resistors.
Type 2 junctions, have one dedicated current and one dedicated voltage sensing terminal. The other two
connections can be used for either current carrying or voltage sensing. A high degree of symmetry is required
between the dedicated current terminal and the other three. The construction is typically a solid cylinder of copper
for the dedicated current terminal with the other three connections emerging radially at 120 degree intervals. Type
2 junctions are used in series connected (Hamon type) networks. See section 4.3.1 for more detail.
I or V V
V or I
Fig. 3.4.1 A type 2 zero-Ohm junction
Type three is fully symmetrical and requires much higher precision with regards to the (tetrahedral) symmetry of
construction. The main advantage is that all four connections are interchangeable (i.e. can be used for current
carrying or voltage sensing). Type 3 junctions are used in White/Jones type networks. See section 4.3.2 for more
detail.
V
I
I or V V or I I
I or V V or I
Type 1 (semi-symmetrical) Type 2 (symmetry about I) Type 3 (fully symmetrical)
All four terminals V or I
Fig. 3.4.2 Zero-Ohm junctions (equivalent circuits)
Good AC performance is achieved by ensuring, as near as possible, the voltage sensing pair is perpendicular to the
current carrying pair and the areas are kept to a minimum thus minimising mutual inductance.
9
4. Two-terminal-pair resistor networks
4.1 Introduction
Whereas connecting separately constructed two-terminal-pairs in parallel is possible it is not very practicable. This
is demonstrated in the next section. Connecting two or more in series is virtually impossible if high accuracy is
required. The solution is to construct two or more resistors with permanent series connections using zero-Ohm
junctions. The small resistance of the junction connections forms part of the accurately defined resistor which is
trimmed accordingly. The other two connections provide the means for measuring each individual resistor as a two-
terminal-pair resistor.
The main application is resistance bridge calibration with an accuracy approaching 10ppb (with accurate and stable
temperature control) from DC to 400Hz AC. The following, for example, provides the means of producing three
values of resistance (R1, R2 and R1+R2). The latter can be calculated as well as measured.
V I V I V I
R1 R2
Fig. 4.1.1 Two-terminal pair resistors in series
The basic idea of networks is that series and parallel combinations of two-terminal pair resistors can be calculated
and measured with great accuracy. They provide a convenient means for comparing transfer standards and
checking/calibrating DC and AC ratio measuring instruments.
4.2 Balancing (potential sharing) resistors
Connecting two separately constructed two-terminal pair resistors in parallel results in the following: -
V
I
RC1 RC2
RV1 V1 RV2
U1 U2
R1 R2
RV1 V2 RV2
U3 U4
RC1 RC2
I1 0V I2
Fig. 4.2.1 A pair of 2TP resistors in parallel
The aim is to be able to calculate the parallel combination accurately, in terms of the individual resistances: -
1 1 1
Ideally, for a parallel combination:  
RT R1 R2
10
Part 1: Monograph 1
From the symmetry it is clear that there can be no advantage in having different resistances in the voltage sensing
or current carrying connections (flip vertically and apply reductio ad absurdum). One can assume, therefore, that
both voltage sensing connections for R1 have resistance RV 1 and both current carrying connections have
resistances RC1 and similarly for R2 .
The trick is to adjust the resistance in the current carrying connections so that no current flows in the voltage
sensing resistances (i.e. V1 = U1 = U2 and V2 = U3 = U4).
RC1 RC 2
U3  U 4 V V
2 RC1  R1 2 RC 2  R2
R1 R
Divide by V and take the reciprocal:  2  2 2
RC1 RC 2
RC1 RC 2
From which one can derive the simple condition and define the parameter:  
R1 R2
From the symmetry the upper voltages must also be the same as the following confirms: -
RC1  R1 RC 2  R2
U1  V and U2  V
2 RC1  R1 2 RC 2  R2
In the first divide top and bottom by R1 and in the second by R2: -
 1  1
U1  V and U2  V QED
2  1 2  1
With no current flowing through the voltage sensing connections one can confirm that the aim is achieved.
According to Ohm’s law: -
U1  U 3 V1  V2 U 2  U 4 V1  V2 V1  V2
I1   I2   and I1  I 2  I 
R1 R1 R2 R2 RT
The net effective resistance is, therefore, exactly that for two basic resistors in parallel: -
1 I I 1 1
 1 2  
RT V1  V2 R1 R2
One could, of course, add a third resistor, or as many as required, as long as the resistance in the current carrying
pairs conforms to the requirement: -
RC1 RC 2 RC 3 R
   ...  CN
R1 R2 R3 RN
From the symmetry it would also make sense if the resistances in the voltage sensing pairs were also matched: -
RV 1 RV 2 RV 3 R
   ...  VN
R1 R2 R3 RN
11
This is made clear by more detailed analysis, not included here as the algebra is a little tedious. For two resistors
(see section 4.3.2 for a reference to the user manual): -
R1 R2  R1 R2  RV 1 RV 2  RC1 RC 2  1 
RT  1       
R1  R 2  R1  R 2  R1 R2  R1 R2  RV 1  RV 2 
It would seem a good idea, therefore, to match as closely as practicable both current carrying and voltage sensing
connections. The most practical solution, however, given that resistance matching is only feasible to about 1mΩ, is
to have very low resistance in the current connections (and switches) and larger, more closely matched resistances
in the voltage sensing connections. Typical values are 10mΩ ±1mΩ and 1 - 10Ω ±1mΩ respectively. This is the
basis of the White/Jones market leading resistance bridge calibrators.
4.3 Resistance bridge calibrators
There are two main types of resistor networks for bridge calibration: -
a). The Hamon type [1] was originally used to provide 10Ω and 100Ω transfer standards, calibrated against a 1Ω
primary standard. It also provided limited means for checking the accuracy of ratio measuring instruments. The
technique is now obsolete due to the development of the second type but is included for its ingenuity and for
historical interest.
b). The White/Jones type [2] and [3] provides a much more practical means for checking the accuracy of ratio
measuring instruments. Four accurate base resistors connected by a zero-Ohm junction provide a convenient
method for generating an additional 31 calculable resistance values. When compared with a stable transfer standard
resistor (e.g. a Wilkins) a full range of ratios can be measured and compared with calculated values. Unlike the
Hamon type commercially available resistance bridge calibrators (RBC) also retain high accuracy at higher
frequency (400Hz). Ratio accuracy can approach 10ppb especially with temperature control (±0.01°C).
The US National institute for Science and Technology (NIST) used the White/Jones type to compare five of the
world’s best selling resistance bridges with some very interesting results [4]: -
Fig 4.3.1 A report from NIST
1. Hamon, B. V.: “A 1-100Ω build-up resistor for the calibration of standard resistors”. J. Sci. Instr. 31,
450-453 (Dec 1954).
2. US Patent 5,867,018 (Inventors: Rod White and Keith Jones): PCT/NZ95/00022
3. White, D.R. Jones, K. Williams, J.M. and Ramsey, I.E.: “A simple resistance network for calibrating
resistance bridges”. IEEE trans. on inst. and meas. Vol.46(5): pp.1068-1074. (1997)
4. Chojnacky, M. Kosior, J. Chaves-Santacruz, L. and Strouse, G.: “Performance assessment of
thermometer resistance bridges”. NIST Thermodynamic Metrology Group, Sensor Science Division
12
Part 1: Monograph 1
4.3.1 The Hamon “build-up” network
The original Hamon network [1] consisted of eleven accurate 10Ω resistors permanently connected in series using
type two zero-Ohm junctions. The two connections to each junction provide for two-terminal-pair measurement
and comparison with a reference and with each other. Groups of resistors can then be connected in parallel or in
series-parallel combinations, with suitable external matching resistors, to produce a wide range of resistor values
(nominally 1Ω - 100Ω) and accurate ratios in the range 1:10 to 10:1. Hamon’s analysis, later confirmed in more
detail by Page [2] and Riley [3], showed that an accuracy of ±10ppb, or better, was “feasible”. Although obsolete
no monograph on high accuracy resistors would be complete without a mention of this ingenious design.
V I V I V I V I
…..
R1 Rn
Fig. 4.3.1.1 A Hamon type network
I
V
I
V
2RV RV RV 2RV
…
R R R
Fig. 4.3.1.2 The Hamon network with external matching resistors
N.B. The original design employed pots of mercury to provide the very low resistance connections!
1. Hamon, B.V.: “A 1-100Ω build-up resistor for the calibration of standard resistors”. J. Sci. Instr. 31,
450-453 (Dec 1954).
2. Page, C. H.: “Errors in the Series-Parallel Build up of Four-Terminal Resistors” Journal of research of
the National Bureau of Standards-C. Engineering and Instrumentation Vol. 69C, No.3, July-September
1965.
3. Riley, J. C.: “The accuracy of series and parallel connections of four terminal resistors.” IEEE Trans.
on Instr. & Meas. vol. IM-16. pp 258-268.
13
4.3.2 The White/Jones resistance bridge calibrator
This ingenious design [1] supercedes the Hamon type and, when automated [2] and kept in a temperature controlled
environment, provides a convenient method of checking resistance ratio measurement accuracy at the highest level.
The following omits the small resistor symbols for clarity.
R1 R2
RP1 RP2
RC1 RC2
RP3 RP4
RC3 RC4
R3 R4
Fig 4.3.2.1 The White/Jones resistance bridge calibrator
Manual RBC
Remote controlled RBC [2]
Fig. 4.3.2.2 Resistance bridge calibrators (courtesy Isotech Ltd [1])
(The USB controlled version is designed to be submerged in a temperature controlled oil bath)
Three models are available suitable for calibrating most commercially available resistance bridges, each with four
very accurate resistors, four moderately accurate potential sharing resistors and a fully symmetric (type 3) zero-
Ohm junction. The internal current carrying and switch contact resistances are kept very low. Each model is
designed to provide a suitable range of ratios with transfer standard resistors of typically 10Ω, 25Ω and 100 Ω
respectively, depending on the measuring range of the instrument being calibrated. The potential sharing resistors
are critical and are included below (resistance values in Ohms): -
Model R1 RP1 R2 RP2 R3 RP3 R4 RP4

RBC13 10.63652 2.635 6.26322 1.551 4.74705 1.176 4.06149 1.006
RBC100 81.81935 2.645 48.17864 1.558 36.51578 1.180 31.24221 1.010
RBC400 251.9874 3.177 147.9912 1.866 116.3731 1.467 40.4480 0.510
The values of the base resistors are chosen not only to provide an optimum range of ratios, when compared to a
suitable transfer standard resistor, but also to exercise all nine digits of each decade, at least once, for detecting
bridge malfunctions (e.g. a faulty relay).
1. The RBC User manual is available from Isothermal Technology Limited. www.isotech.co.uk
2. White, D.R., Edgar, H., McLennan, B.E., Saunders, P.: “Automation of the resistance bridge calibrator”.
AIP Conference Proceedings. Vol.1552, no. 8, pp 392-397 (2013).
14
Part 1: Monograph 1
Fig. 4.3.2.3 The internal connection scheme (the manual version has eight switches in total)
The four base resistors can be combined in various series, parallel and series-parallel combinations to provide an
additional 31 resistor values which can be calculated (35 values in total). The range of values provides a relatively
simple check on linearity of the instrument being tested to better than 100ppb. This is usually sufficient for most
applications (e.g. resistance thermometry) as absolute values of resistance are not required.
Even more information (e.g. absolute ratio accuracy) can be gleaned if two or more (i.e. external to the bridge)
transfer standard resistor values are available, providing more data points and permitting more complement and
three resistor checks, subject to the range of the instrument: -
R2 R1
Complement check (swap resistors):  1
R1 R2
R2 R1 R3
Three resistor check:   1
R1 R3 R2
15
5. Four-terminal-pair resistors
In much of the established literature the generally accepted definition of a four-terminal-pair resistor is a two-
terminal-pair resistor with overall screen. This dates back many years. In one of the earliest papers Cutkosky, for
example, regarded the screen connections as valid terminals of a four-terminal-pair device [1]. According to Awan
et al “The result… is a four-terminal-pair definition, which is precise enough for all present practical applications
and all values of impedances.” [2].
Fig. 5.1 A widely accepted definition of four-terminal-pair impedance [2]
The result, over the years, has been complex bridge designs with earth loops and associated problems [3].
Fortunately there is a better way. The basic idea is to combine a two-terminal-pair resistor with a zero-Ohm
junction (ZOJ type 1) plus an overall screen. The defining conditions remain the same: -
I I
V V + screen
Fig. 5.2 The author’s concept of a four-terminal-pair resistor
The measuring current is returned via the ZOJ in such a way that minimises the transmission of magnetic flux.
Similarly, the voltage sensing connections are routed to minimise induced voltages due to stray magnetic flux. The
screen is provided with a separate connection to local 0V and is insulated from the measuring terminals. Suitably
insulated connectors (e.g. BNC co-axial) and insulating washers are readily available.
1. Cutkosky, R. D.: “Four-terminal-pair networks as precision admittance and impedance standards”. Trans.
IEEE Commun. Electron. 1964; 83: pp19–22.
2. Awan et al. See footnote page 1.
3. Part 3, monograph 9: “Coaxial AC bridges”.
16
Part 1: Monograph 1
A typical measurement configuration is shown in fig. 5.3. The devices being measured are labelled as general
impedances but can be resistive with small phase errors. The configuration ensures accurate equal and opposite
currents and the minimal transmission of stray flux at the operating frequency without the need for high
permeability toroidal chokes [1]: -
IS
IC1 I1
IC2
V1A
V1B ≈ 0V
Z1 VJ1 Ф1
V2B ≈ 0V
I2
V2A ≈ 0V
IC3
IC4
IC5
V3A ≈ 0V
I3
V3B ≈ 0V Floating PSU
Z2 VJ2 Ф2
V4B ≈ 0V
I4 V4A
IC6
I5
IC7
Fig. 5.3 Scheme for measuring the ratio of two four-terminal-pair resistors
Notes: -
1. The current source is shown with the usual symbol for simplicity. See fig. 5.5 for details.
2. The action of feedback of the high gain block is to ensure that the voltage across and, therefore, the currents
through cable capacitances C3, C4, and C5 are very small but may not be negligible. According to the definitions
above the currents through Z1 and Z2 are, therefore: -
I Z1  I 2  IC 3 I Z 2  I 2  IC 4  IC5 with I C 3 , I C 4 and IC 5  I S  I1  I 2  I 3  I 4
3. Assume V1B  V2 B and V3 B  V4 B because the zero-Ohm junctions may not be perfect and stray flux Ф1 and Ф2
between the cables may not be negligible. The relevant voltages are, therefore: -
VZ 1  V1A  V1B   V2 A  V2 B   VJ 1 and VZ 2  V3 A  V3B   V4 A  V4 B   VJ 2
Where VJ 1 and VJ 2 are the voltage generated at the (imperfect) zero-Ohm junctions.
1. Homan, D.N.: ‘Applications of coaxial chokes to AC bridge circuits’.

J. Res. NBS – C. 1968; 72C: 161–65
(A “Choke” is when the coax cable is passed through a toroidal core the required number of times)
17
The circuit is basically an inverting amplifier [1] with a high gain block [2] with negligible input current providing
an accurate virtual earth: -
Virtual earth VZ2

Z2
VZ1
Z1 High gain block
IS
Primary 0V
C1+C2 C3+C4+C5 C6+C7
Fig. 5.4 The basic configuration
Notes: -
1. There is only one connection to earth – no earth loops. This is usually at the current source for practical reasons.
2. The non-inverting input of the HGB can be regarded as the primary 0V reference point for the bridge. The virtual
earth is maintained at this potential plus the DC offset and random noise of the HGB plus a very small carrier
signal depending on the open loop gain.
The current source and guard amp output stages are best constructed on the same PCB module with twisted triples
for their (separate) power supplies and twisted pairs for the carrier signals. The principle can be best understood by
considering the positive half cycle of the sine wave and following the route by which the current flows. Within the
module the PCB tracks are routed to keep the area depicted to a minimum: -
Twisted
Triple
V to I
Z1 Twisted
Pairs Minimal
Area PSU1
Minimal FPSU2
Area
Z2
Guard amp
Twisted
Triple
Fig. 5.5 Physical layout and separate power supplies
The current source is usually a “Howland pump” type voltage to current converter which takes and returns a small
but not negligible proportion of the total current back to the power supply hence the two pairs of arrows on PSU1.

2. Part 4, monograph 1: “High gain blocks”.
18
Part 1: Monograph 1
Analysis: -
According to Kirchhoff’s law (conservation of charge) the currents flowing through the lumped impedances are, in
the complex representation (phasors): -
I Z1  I 2  IC 3 I Z 2  I 2  IC 4  IC5 with I C 3 , I C 4 and I C 5  I 2  I S
One can take the current IS as the primary phase reference (i.e. a real number).
One can usually assume that any stray flux is sufficiently uniform so that the voltage induced between the
conductors of a pair (coax or twisted) is negligible. According to Kirchhoff’s laws, therefore: -
V1A  V2 A   VZ1  VI where VI  the induced voltage due to Ф1
V1B  V2 B   VJ 1  VI where VJ  the voltage error of the zero-Ohm junction.
 VZ1  V1A  V2 A  VI  V1A  V1B   V2 A  V2 B   VJ 1
Assume an ideal zero-Ohm junction though it would be wise to measure the voltage to be sure: -
VJ 1  0V  VZ1  V1A  V1B   V2 A  V2 B 
Similarly for cables 5 and 6: VZ 2  V3 A  V3B   V4 A  V4 B 
The ratio of impedances is, therefore: -
Z 2 VZ 2 I Z 1 V3 A  V3 B   V4 A  V4 B  I 2  IC 3
   
Z1 I Z 2 VZ 1 V1 A  V1B   V2 A  V2 B  I 2  I C 4  I C 5 
Define voltage ratio: 

V4 B  V4 A   Z 2
V1A  V1B  Z1
This is very nearly the required ratio and needs to be measured very accurately.
Define voltage ratio: 

V3 A  V3B   V3 A  V3B   1
V1A  V1B  VZ 1
The voltage difference V3 A  V3 B  is the error at the input of the high gain block and is very small.
Define voltage ratio: 

V2 A  V2 B   V2 A  V2 B   1
V1A  V1B  VZ 1
If one assumes an ideal HGB V3 A  V3 B  0V  the voltage difference V2 A  V2 B  is entirely due to the resistances
in cable 4 and is also quite small.
19
Also, if the capacitive currents through cables 3, 4 and 5 are very small compared to the main current, I2, then to a
very good approximation: -
I 2  IC3 I I I
I C 3 , I C 4 and I C 5  I 2   1 C3 C 4 C5
I 2  I C 4  I C 5  I2
The ratio thus simplifies. To a very good approximation: -
Z2       IC3  IC 4  IC5 
   1  
Z1  1     I2 
A further approximation is possible: -
 I I I 
  1       1  C 3 C 4 C 5 
Z2
 and   1 
Z1  I2 
The voltage ratio  must be measured very accurately as it is, by far, the major contributor. The much smaller
voltage ratios  and  can be measured with reduced accuracy.
In many cases, with fairly short lengths of cable, a two-stage high gain block and a low measuring frequency the
correction factors are negligible and one can assume, with sufficient accuracy, the simple result: -
Z2 V  V4 A
   4B
Z1 V1 A  V1B
20
Part 1: Monograph 1
5.1 Example calculations
This type of arrangement can be used for measuring the ratio of relatively high value resistors, usually for
comparing transfer standards. I shall assume that Z1 and Z2 are 10kΩ transfer standard resistors with small phase
errors. The current source is a generous 100μA (pk-pk) at 75Hz (ω = 471radians/s) resulting in voltage drops across
the resistors of VZ1 and VZ2 ≈ 1Vpk-pk.
The power dissipation is 0.1mW and, with a little care taken in the thermal design, self heating is not an issue.
5.1.1 Cable phase and magnitude errors
A reasonable assumption for the cables is 1m long with ≈ 0.1Ω series resistance (both conductors) and 100pF of
parallel capacitance. At low frequency each centimetre of cable can be approximated as a low pass filter with
≈1mΩ resistance and 1pF capacitance with a transfer function, for Ncm, in the complex representation s  j  : -
TN s  
1
 1  Ns with   RC  1m  1 pF  1015 s
1  s N
The total phase error (quadrature) for each 1m of cable is, therefore: N  4.71 1011 radians and
negligible. The real part (in-phase) is second order with respect to frequency and even smaller.
Also, electromagnetic signals travel along most types of cable at about two thirds the speed of
 
light  2  108 ms1 . which, at 100Hz (period 10ms) represents a phase shift of 5 × 10-7 radians per metre of cable.
Time delays are negligible.
Similarly, the loss factor (“tanδ”) of the insulating dielectric of reasonably good quality cable is very small
(typically <10-3 rad) and represents small phase errors in the currents IC1 – IC7. Cable phase and magnitude errors
are truly negligible.
5.1.2 Zero-Ohm junction errors
Type 1 zero-Ohm junctions are easily constructed and checked and, if necessary, adjusted to <10nΩ (with 1A
measuring current the output is <10nV). At an operating current of 100μA the error voltage is then negligible.
5.1.3 HGB error voltage
The recommended HGB is a two-stage (type 1) for which the main error voltage is in-phase [1]. An open loop gain
of 109 is readily achieved at 75Hz. With an output voltage of 1V (pk-pk) the input error voltage is less than 1nV
(pk-pk). The correction factor  is then very small and usually negligible: -
H 2 s  
V4 A
The transfer function of the HGB is defined by:
V3 B  V3 A
Z2
For an ideal inverting configuration: V4 A   V1 A
Z1
V3 A  V3 B V3 B  V3 A  Z 2  1  Z2 
Z 2  Z1 and V1B  0V           1 ppb
V1 A  V1B V4 A  Z1  H 2 s   Z1 
21
If one assumes negligible resistances in cable 4 the error voltage results in negligible currents through the
capacitances of cables 3, 4 and 5: -
and I C 3  I C 4  I C 5  V3 A  V3B sC3  C4  C5 

V4 B
I2  I4  
Z2
I C 3  I C 4  I C 5 j C3  C4  C5 Z 2
  (quadrature)
I2 H 2 s 
With a total cable capacitance of 300pF at 75Hz the error term is negligible (Z2 = 10kΩ): -
IC 3  IC 4  IC 5
 1.4  1012
I2
5.1.4 Resistance in cable 4
The measuring current flows through cable 4 creating a small voltage gradient and currents through C3 and
distributed C4. A basic model consists of half the conductor resistance either side of the actual capacitance of cable
4. Note that the measuring current does not flow through any part of cables 3 or 5: -
VZ2
VZ1 C4
C3 C5
Fig. 5.1.4.1 A basic model
This is worth checking as the distribution of resistance and capacitance is continuous. If one assumes an ideal
HGB: -
V(x)
…… C5 V(0)
V’(x) x
Fig. 5.1.4.2 A gradient model for cable 4
Define parameters: -
L  Length of cable 4 in metres
  Resistance per unit length of the inner conductor (Ωm-1)
   Resistance per unit length of the outer conductor (Ωm-1)
  Capacitance per unit length (Fm-1)
  Operating frequency (rads-1)
x  Distance from the HGB end in metres
22
Part 1: Monograph 1
According to Ohm’s law the voltages along the inner and outer conductors of cable 4 vary according to: -
V x   V 0  I 2 x and V x   V 0  I 2  I C 6  IC 7  x respectively
The currents caused by the capacitance of cables 6 and 7 are very small compared to the measuring current so that
the difference voltage is, to a sufficiently good approximation: -
I C 6  I C 7  I 2  V  V   I 2    x
The capacitive current over the infinitesimal distance dx is: dI C 4  I 2    sxdx
If one assumes that  and   are constant (uniform resistance along the cable), being careful to employ good
quality, low contact resistance connectors, the integral is simple: -
L2 R  R
    s
IC 4
  sC4
I2 2 2
Where R  R  total resistance (inner and outer) of cable 4, confirming the basic model of fig. 5.1.4.1. The voltage
across cable 3 also results in a current: -
 R  RsC3
IC 3
I2
IC 5
The voltage across cable 5 is zero so that: 0
I2
IC 3  IC 4  IC 5  C 
The correction factor is, therefore:  R  Rs C3  4 
I2  2 
With each cable 1m long (100pF) and a total resistance of 0.1Ω (inner plus outer) the correction factor is: -
IC 3  IC 4  IC 5
 j  0.1  471  150  1012  j 7.1 ppb (quadrature)
I2
This is easily rejected with a suitable quadrature null balance servo.
23
5.2 Calculable resistors
In recent years there has been a revival of interest in the link between the Farad (the SI unit of capacitance) and the
Ohm (the SI unit of resistance) via a quadrature bridge [1]. The traceability chain is nicely summarised in a
diagram: -
Fig. 5.2.1 Links in the traceability chain from Ohm to Farad (courtesy METAS [3])
The best QHR standards and cryogenic current comparators (CCC) employ alternating DC or very low frequency
AC (<1Hz) for comparing resistors. The reasons include: -
a). Power dissipation within the cryostat and heat conduction down the connections must be very low. One
consequence is long and very thin coaxial connections with significant series resistance and parallel capacitance.
Some of the capacitive current inevitably flows through part of the series resistance resulting in heat dissipation and
measurement errors which increase with frequency.
b). The very high magnetic field employed results in a force on any current carrying conductors. The result is
unwanted vibration which manifests as increased series inductance as well as more heat dissipation.
c). Stray capacitance within and from the QHR to its surroundings also result in errors which increase with
frequency [2].
The optimum frequency for measuring capacitance, on the other hand, is around 1-10 kHz. There is a need,
therefore, for a type of transfer standard resistor with calculable magnitude and phase as a function of frequency
(typically up to 10 kHz), based on a measured DC value and (“a priori”) fundamental principles.
The AC characteristics of a more robust (portable) type of resistor (e.g. Vishay) can then be established, with a
coaxial AC bridge, which is then passed around various NMIs for comparing with capacitors using a “quadrature”
bridge [1].
For a comprehensive review see [3].
1. Part 3, monograph 10: “A quadrature bridge”

2. Ahlers F. J., Jeanneret B., Overney F., Schurr J. and Wood B. M.:“Compendium for precise ac
measurements of the quantum Hall resistance.” Metrologia (Oct 2009). DOI: 10.1088/0026-1394/46/5/R01
3. Schurr, J. et al: “Final Report of the Supplementary Comparison EURAMET.EM-S31: Comparison of
capacitance and capacitance ratio (May 2017).
24
Part 1: Monograph 1
There are two main types of (a priori) calculable resistor. Both rely on relatively simple geometry so that the
impedance can be modelled analytically (in terms of “lumped” components – resistance, inductance and stray
capacitance) as well as calculated using finite element analysis:-
a) The coaxial or “Haddad” type [1].
b) The bifilar, quadrifilar and octofilar or “Gibbings” type [2].
Both are sensitive to shock and vibration and require very accurate temperature control. They must be moved, very
gently, between the QHR/CCC and adjacent higher frequency apparatus and back again whilst maintaining a
constant temperature. The more robust transfer standard resistors and/or capacitors can then be transported (usually
by hand) to other calibration labs.
Fig. 5.2.2 A coaxial type calculable resistor (courtesy METAS)
Fig. 5.2.3 Coaxial resistor – the final article (courtesy Kucera et al [3])
1. Haddad R. J.: “A resistor calculable from DC to ω = 105 rad/s,” Sch. Eng. Appl. Sci., George Washington
Univ., M. S. Thesis (Apr. 1969)
2. Gibbings, D. L. H.: “A design for resistors of calculable ac/dc resistance ratio” Proc. IEE vol. 110
pp. 335–347 (1963)
3. Kucera, J., Vollmer, E. and Schurr, J: “Precision Haddad-type Calculable Resistors”. Presentation to
CPEM/PTB 2008.
25
Fig. 5.2.4 Calculable resistors – basic construction and model (courtesy Pacheco-Estrada et al [1]): -
Fig. 5.2.5 Calculable resistors – construction details (courtesy Pacheco-Estrada et al [1]): -
1. Pacheco-Estrada, A. H. et al: “A Simple Methodology to Develop Bifilar, Quadrifilar and Octofilar

Calculable Resistors”. Appl. Sci. 2020, 10, 1595.
26
Part 1: Monograph 1
6. Johnson Noise
One of the main disadvantages of resistors is that they generate random noise. The free electrons within the resistor
behave much like a gas - flying about in random directions with a normal (i.e. Gaussian) energy distribution. With
a low noise amplifier it is possible to measure a small random voltage at the terminals. The open circuit noise
voltage (RMS) is: -
VJN  4kTBR
Where: -
k  1.38 1023 JK 1 is Boltzmann’s constant
T  Absolute temperature (K)
B  Bandwidth in Hz
R  Resistance in Ohms
4kTB
Similarly the closed circuit noise current (RMS) is: I JN 
R
The “noise power” is a useful concept: -
PJN  VJN I JN  4kTB
It is shown elsewhere [1] that the noise power is four times the heat energy which would flow down the conductors
from a warm source resistor to a matching cold resistor.
Similarly, best noise performance is obtained when the first stage amplifier is matched to the source resistance [1].
This occurs when the noise resistance (noise voltage divided by noise current) of the amplifier input stage is equal
to the source resistance. Bipolar transistors are best matched to resistances between 100Ω and 10kΩ [2]. Matching
to lower source resistance can be achieved with a suitable transformer [3]. Matching to higher value resistance is
typically improved by using a JFET transistor input stage (100kΩ – 10MΩ) [4].
1. Part 5, monograph 1: “Null detectors – the basics”. See appendix A1.1 and A1.3
2. Part 5, monograph 2: “Low noise BJT pre-amps”
3. Part 3, monograph 5: “Noise matching transformers”
4. Part 5, monograph 3: “Low noise JFET pre-amps”
27
7. Picture gallery
Fig. 7.1 A transportable 10kΩ transfer standard resistor (courtesy IET Labs inc.)
An alternative to accurate temperature control is either by measuring the temperature of the oil bath with a separate
thermometer (thermometer well provided) or by measuring the incorporated resistance thermometer (nominally
10kΩ) with a dedicated channel on a scanner. The calibration certificate provides the known dependence: -
Fig. 7.2 Calibration certificate for a 10kΩ transfer standard resistor
28
Part 1: Monograph 2
High accuracy single capacitors

1. Introduction
High accuracy single capacitors are used as calibration transfer standards and convenient reference devices for
capacitive sensors (e.g. variable gap, humidity and strain gauges). For some years a calculable capacitor was also a
serious contender as a primary standard for the Ohm [1 and 2]. Attempts have also been made to construct
capacitors with a fused quartz dielectric [3] but the most common types use air as a dielectric. The capacitance
varies slightly with temperature, pressure and humidity. Temperature sensitivity can be mitigated by choosing
materials and relative dimensions whereby the expansion coefficient is self-compensating, at least over normal lab
temperatures and with stable temperature control. An empirical formula can be used to compensate for variations in
atmospheric pressure and humidity [4]. For the very highest accuracy the capacitor can be flushed through with dry
air and then sealed.
According to Marina Santo Zarnik and Darko Belavic: “The permittivity of the air as a function of the relative
humidity can be calculated from the empirical relation [4]: -
where ε0 is the permittivity of vacuum, T is the absolute temperature (K), RH is the relative humidity (%), P (mm
Hg) is the pressure of the air, and PS (mm Hg) is the pressure of saturated water vapour at the temperature T”.
Fig. 1.1 A 1pF reference capacitor (picture courtesy ASL Ltd)
1. Raynor, G. H.: “NPL Calculable Capacitor.” IEEE Trans. Instrum. Meas. Vol IM-21. Pp 361 –
365, 1972.
2. Thomson, A. M. 1958.: “The precise measurement of small capacitances.”
IRE Trans. Instrum. I7 245-53.
3. Cutkosky, R. D. and Lee, L. H.: “Improved ten-picofarad fused silica dielectric capacitor.” NBS
J. Res., vol 69C, pp 173 – 179, July – Sept 1965.
4. Santo Zarnik, M. and Belavic, D.: “An Experimental and Numerical Study of the Humidity
Effect on the Stability of a Capacitive Ceramic Pressure Sensor”. Radioengineering, Vol. 21, No.
1, April 2012 201. http://www.radioeng.cz/fulltexts/2012/12_01_0201_0206.pdf
1
2. Transfer standard air capacitors
Transfer standard air capacitors are usually fabricated as concentric cylinders, machined to high precision and
mounted on ceramic insulators inside a screened metal enclosure.
Fig. 2.1 A 10pF transfer standard capacitor (picture courtesy ASL Ltd)
The electrode that connects to the signal generator output is the outer cylinder and acts as extra screening for the
(high impedance) output electrode. As the name implies the dielectric medium is simply air as this is adequate for
most applications.
The connections to the electrodes are usually BNC with the outer screen of only one coax cable connected to the
enclosure. The screen of the input BNC must be earthed at the signal generator but not to the enclosure. The
enclosure and screen of the output BNC must be earthed at the charge amplifier, hence the “third terminal”. This
ensures that the current due to the cable capacitance on the input side flows back to the signal generator and not
down the screen of the output cable. See fig 2.3.
Screen/
enclosure
Input side Output side

(signal generator) (charge amplifier)
BNC outer
isolated from
enclosure.
Fig. 2.2 Typical construction of a three terminal air capacitor
The main characteristics are: -

 Moderately accurate: usually specified to ±0.1% or ±0.01%
 Very stable with time and temperature (a few ppm).
 Very low loss tangent (typically less than 10-5 at 1.6kHz)
2
Part 1: Monograph 2
CS
Screen Output
Input
C1 C2
R1 R2
Earth break here
Fig. 2.3 Simplified equivalent circuit of a three terminal capacitor
A high voltage AC signal is applied to the input side while the output side is usually held at a virtual earth. The
current flowing through cable capacitance C1 must be routed back to earth through the small (but not negligible)
resistance R1. If the earth connection is not broken some of that current would flow down the screen of the output
cable, setting up a voltage across R2. This signal then produces a current flowing through the relatively large cable
capacitance C2. Whereas this error signal is substantially quadrature it can be sufficiently large to be a problem.
A more significant problem, at the very highest levels of accuracy, is the inductive component of the outer screens
which would, if the earth is not broken, introduce an in-phase component via C2.
3. Basic principles
Calculating capacitance from basic principles (e.g. Coulomb’s law) is relatively simple and demonstrates that
capacitance really is a fundamental concept (unlike resistance). Consider, for example, a conducting sphere with
uniformly distributed charge. From the symmetry one would expect Coulomb’s law to apply so that the electric
force field is uniformly radial outside the sphere - exactly the same as that produced by a point charge at the centre
(the “inverse square law”): -
 QS r
E ra
4 0 r 3
b X
Fig. 3.1 Concentric spherical conductors
3
Consider now a second concentric sphere. The work done in moving an infinitesimal test charge from the outer
sphere to the inner sphere along any radial is, therefore: -
Q Q   1
a
1 1 
a
QQ QQ
W   Fdr   S T 2 dr  S T    S T b  a 
b
4 0 r 4 0  r  b 4 0  
The voltage difference is defined as the increase in potential energy per unit of charge and, therefore: -
W Q 1 1 
V  S  b  a 
QT 4 0
QS 4 0 ab
From the definition of capacitance: C 
V b  a 
In the limit that the radii become infinite but with a fixed gap of g  b  a then the capacitance is: -
4 0 ab
C
g
The total surface area of the spheres tends to the limit: AS  4r 2  4ab
C 0
The capacitance per unit area is, therefore: 
AS g
If one takes a section of the spheres, small compared to the radius, then the plates, in the limit, become flat and
parallel and the capacitance is proportional to the area of the plates according to the familiar expression for the
capacitance of an “infinite parallel plate capacitor”: -
APP
CPP   0
g
In practice the capacitance can be a little more than this due to the fringe field at the edge of the plates. This can be
overcome, however, by the use of a guard electrode. This technique is often used in single capacitors and
capacitance transducers [1]. Similar analysis can be applied to other geometries (e.g. cylindrical electrodes) with
remarkably close agreement between calculated and measured capacitance.
Complete screen continues to

and around charge amplifier
Sensing electrode Concentric guard

electrode
Fringe field
Guard electrode and screen are
maintained at the same voltage
as the sensing electrode.
Target surface
Fig. 3.2 The principle of the guard electrode
1. Part 1, monograph 5: “Variable gap capacitive displacement transducers”.
4
Part 1: Monograph 2
4. The Thompson Lampard calculable capacitor
In the 1950s Thompson and Lampard discovered a mathematical property of parallel cylinders which makes it
possible to calculate the capacitance per metre, based only on a fundamental constant (the permittivity of vacuum)
[1].
This led to a practical device which could be used as a primary standard for capacitance [2].
A comparison between capacitors and resistors (including calculable resistors) at a known frequency (with a
“quadrature” bridge) also provides an independent way of checking the consistency of the definition and practical
implementation of the Farad and the Ohm [3]. At the time of writing (2022) there is a resurgence of interest and
research in this area [4].
Fig. 4.1 The basic geometry of a calculable capacitor

(image courtesy Gournay et al)
1. Thompson A.M., Lampard D.G.: “A New Theorem in Electrostatics and its Application to
Calculable Standards of Capacitance”. Nature, 1956, 177, 888
2. Clothier W.K.: “A Calculable Standard of Capacitance”. Metrologia, 1965, 1, 36
3. Thompson A.M.: “An Absolute determination of Resistance Based on a Calculable Standard of
Capacitance”. Metrologia, 1968, 4, 1
4. Gournay, P., Fletcher, N., Robertsson L., Stock M.: “Progress on the Thompson-Lampard
calculable capacitor project at BIPM”. 17th International Congress of Metrology, 12001 (2015)
5
5. Industry standards
One of the most widely employed transfer standards is the IET type 1404
Fig. 5.1 Transfer standard gas capacitors (courtesy IET Labs Inc.)
Fig. 5.2 An extract from the datasheet
6
Part 1: Monograph 2
Fig. 5.3 The internal construction of a 1nF transfer standard
7
Part 1: Monograph 3
Rotary capacitive displacement transducers

1. Introduction
Capacitive type rotary displacement transducers can be made with accuracies approaching 1ppm of range and sub-
arc second resolution and repeatability. The component parts need to be made with reasonably high precision and
assembled accurately but, otherwise, the technology required is well within the capabilities of a normal precision
engineering workshop, equipped for turning, milling and grinding. The metal components (usually stainless steel)
can be held together with epoxy resin or, for high temperature applications, with ceramic spacers for insulation.
Good quality ball bearings should be used, though these are readily available and not expensive.
N.B. Most other techniques for accurate measurement of angular displacement are incremental (e.g. incremental
optical encoders). Capacitive transducers measure absolute angle.
Fig. 1.1 A capacitive type rotary displacement transducer (picture courtesy ASL Ltd)
1.1 The two main types
There are two main types of variable capacitance transducer for the accurate measurement of angular displacement:
cylindrical and planar (flat plates). The cylindrical type has a diameter which is approximately the same as its
length (see fig. 1.1). The flat plate type can be much thinner (axially) but has a larger diameter (radially). The basic
transducer has limited angular range (up to ±45deg) but unlimited angle can be achieved by combining two
transducers, with overlapping ranges, and switching between them.
In both cases the stator usually consists of four energised electrodes, in symmetrically opposed pairs, and a single
sensor electrode attached to the stator (the stationary element). The rotor (the rotating element) consists of a screen
electrode, connected to 0V, usually via a rotating friction contact or slip ring. As the screen rotates it varies the area
of the sensor electrodes exposed to the energised electrodes. The capacitance is proportional to the area of exposure
and, therefore, varies in direct proportion to the angle. The symmetry of the technique makes both types insensitive
to non-concentricity of the rotor and stator. Stator and rotor can be supplied separately and fitted to a shaft, which
already has a bearing, without the need for special jigs, fixtures or gauges.
1
C1  C2
The ratio n  is accurately proportional to angular displacement for both types of transducer. This ratio
C1  C2
can be measured directly with a ratio transformer/inductive voltage divider bridge for the highest accuracy and
resolution. In the following, for example, the centre of a centre-tapped transformer is driven with a voltage, VC,
 V1  V2 
which is derived from a reference voltage VR   using an inductive voltage divider (IVD).
 2 
At null balance: V1C1  V2C2  0
 VC  VR C1  VC  VR C2  0

VC C  C2
With a little algebra one finds: n 1
VR C1  C2
For more detail see the monograph “A 20 bit binary differential capacitance bridge” by the same author.
Reduced performance is possible with a low cost signal conditioner (see section 6).
C1 CF
V1
VP VC
C2 VOUT
NP
V2
NS
0V
Fig. 2.1 A typical bridge configuration
Ratiometric operation has a number of advantages. Specifically: -

 The ratio of capacitance and, therefore, the overall measurement accuracy, is independent of certain
manufacturing tolerances, specifically: actual dimensions.
 The ratio is independent of the dielectric medium, between the electrodes, as long as it is uniform. The effect
due to small changes in the dielectric constant of air, due to humidity, is negligible. The transducer will also
function satisfactorily while submersed in non-conducting liquid with a uniform dielectric constant.
 The ratio is independent of temperature, as long as it is uniform throughout the body of the transducer.
 Linearity depends on the uniformity of the cylindricity, flatness and/or circularity of the electrode surfaces. In
practice these are quite easy to achieve using finish grinding and honing techniques.
 The rotor and stator must be reasonably accurately coaxial, though the design affords some self-compensation
for small errors. Fairly basic jigs and fixtures usually suffice.
N.B. repeatability depends mainly on the quality of the ball bearing. With a really good bearing this can be down to
the sub arc-second level (micro-radians).
Stability over time is also excellent so that any non-linearity can be measured and compensated.
2
Part 1: Monograph 3
Accurate measurement of the capacitance ratio relies on the sensor electrode being maintained at 0V by the action
of feedback of an operational amplifier (aka “virtual earth”). See fig. 3.1.
N.B. This is called a charge amplifier because the output voltage is proportional to the electrical charge on the
feedback capacitor.
The sensor electrodes, charge amplifier and the connection between them must be completely surrounded by a
conducting screen connected to local 0V. This is to prevent electrical interference from external sources and also to
prevent disturbance of the electric field and, therefore, the capacitances, due to the proximity of external objects.
This is the concept of a “three terminal capacitance” – even though there is a considerable stray capacitance
between the screen and the sensor electrode/virtual earth, there is no voltage difference and no current flows. The
capacitances C1 and C2 are thereby accurately defined.
C1 Virtual earth CF
V1
C2 VCA
V2
JFET input
0V
0V
screen
Fig. 3.1 A differential capacitive transducer and charge amplifier
At null balance: -
V1C1  V2C2
VCA  0
CF
 V1C1  V2C2  0
Lowest noise is best achieved with a composite op-amp – with a dual matched JFET pair front end [1].
1. Part 5, monograph 3: “Low noise JFET pre-amplifiers
3
4. The cylindrical type transducer
The following design was invented and patented by Peter Wolfendale. The first application was as part of a very
high performance servo-mechanism, using a high speed limited angle torque motor to position a small mirror.
The sensing electrode is a simple cylinder, mounted on the stator body member (SBM). The energised electrodes
also start life as a simple cylinder but end up as four electrically isolated segments of approximately 90 degrees
each. Electrical connections are made via holes in the SBM with studs, spot welded onto the electrodes. The
rotating screen electrode is part of a cylinder and is mounted on the rotating shaft. Reliable electrical connection to
0V is made via a rotating precious metal contact at the end of the shaft.
Although the manufacture of the cylindrical type is quite involved (i.e. expensive in low volumes), its high
performance and robustness makes it an excellent choice for demanding, high value applications.
Energised electrode electrical connection

Epoxy resin
Stator body member (SBM)
Rotating screen
electrode Leaf spring
Rotating shaft
axis Rotating contact
Sensor electrode
electrical connection
Fixing boss
Stator body member (SBM)
Fig. 4.1 Cylinder type transducer (radial view cross section)
Energised electrodes
C1 C2
Rotating screen
electrode
Sensor
electrode
C2 C1
Energised electrodes
Fig. 4.2 Cylinder type transducer (axial view)
Opposing electrodes are connected in parallel to form two variable capacitors. As the rotor screen electrode rotates
clockwise (see fig. 4.2) capacitance C1 increases and C2 decreases.
4
Part 1: Monograph 3
5. Plate type transducers
Plate types can be subdivided into quadrant types, like the cylindrical example above, or multi-segmented types.
5.1 A low cost limited angle example
This type is ideal for one-off projects or low volume applications as it can be fabricated from readily available
materials (e.g. double-sided copper clad PCB material). If high accuracy is required then precisely machined metal
parts with epoxy resin, ceramic and/or glass insulators may be used.
The following example, constructed from double sided PCB material, consists of two fixed plates for the stator
(energised electrodes and sensor electrode) and a symmetrically cut rotating screen electrode between the two (the
rotor). As with the cylinder type the screen varies the area between the energised electrodes and the sensor
electrode.
The energised electrode plate is chemically etched to leave four

conducting quadrants. The dots indicate electrical connection to
form the two capacitors. The hole in the centre allows the shaft
to pass through. The holes on the periphery are for fixing.
C2 C1 The thickness, uniformity and straightness of the etching is not
C1 C2 critical but the plate surfaces need to be flat.
The copper on the reverse side is usually left and connected to

0V to provide screening of the energised electrodes.
Fig. 5.1.1 Energised electrode plate
The sensor electrode plate is also chemically etched to remove two thin
circles of copper, leaving two concentric annular rings.
0V The inner ring and the copper remaining on the periphery are connected to
0V to act as “guard electrodes”.
The larger annular ring is the sensing electrode and is connected to the
preamplifier. This can be done with a through-hole-plated “via” or a fine
wire soldered to the surface which remains under the rotor screen. The
copper on the reverse side is left and connected to 0V to provide screening.
It is advantageous if the preamp is mounted on the reverse side – as near to

the sensing electrode as possible, to minimise ground capacitance.
Fig. 5.1.2 Sensor electrode plate
5
The rotor can also be fabricated from PCB material or thin sheet metal.
The shape and thickness do not have to be precise, as long as it is

sufficiently flat and stiff.
The rotor must be reliably connected to 0V, either through the shaft and a
good quality metallic ball bearing or a rotating contact as with the
cylinder type.
Fig. 5.1.3 The rotor plate
0V
C1 C2
C2 C1
Fig. 5.1.4 The assembled transducer
The range of the transducer is limited to just less than the angle of the rotor screen due to the fringing effect - when
the edge of the rotor approaches the boundary between C1 and C2. The maximum range is, therefore, a little less
than ± 45 degrees, depending on the width of the gap. As a rule of thumb the fringe effect is negligible when the
edge of the screen electrode is five times the gap width from the energised electrode boundary.
If one defines clockwise as the positive direction for angle (see fig. 5.1.4) then for an angle +45 degrees C2 is
totally obscured and C1 totally exposed. The resulting ratio is: -
C1  C2 C1  0
n  45    1
C1  C2 C1  0
Similarly for a counter-clockwise angle of -45 degrees, C1 is totally obscured and C2 exposed.
C1  C2 0  C2
n  45    1
C1  C2 0  C2
The sensitivity of the transducer is, therefore: -
n45  n 45 2

 
1
per degree  n  
C1  C2
   
90 90 45 C1  C2 45
Clearly the cylindrical type has the same slope.
6
Part 1: Monograph 3
The width of the rotor does not affect the sensitivity. Fig. 5.1.5 illustrates two cases: with rotor widths of 90
degrees and 45 degrees. The slope is the same but the range is reduced for the latter (maximum ratio of ±0.5). It is
often useful to reduce the size of the rotor if the maximum range is not required – to minimise its moment of
inertia.
90 deg. rotor Ratio, n

45 deg. rotor
+1
-45 Angle (deg.)
-180 -135 -90 45 90 135 180
-1
Fig. 5.1.5 Ratio versus angle in degrees for a quadrant type transducer (plate or cylindrical)
Note that the ratio does not depend on the actual diameter of the electrodes or the size of the gap. In practice the
insulating gaps between the electrodes need to be as thin as possible and the sensor electrode as circular as possible.
Deviations from the ideal formula are small and highly repeatable and so the transducer can be calibrated and any
non-linearity compensated.
7
5.2 A multi-segmented design
It is possible to reduce the size of the segments and increase their number while retaining the balanced structure.
Using more segments reduces the accuracy required of the ratio measurement. Fig. 5.2.1 is an example of a multi-
segmented type. An absolute range of 360 degree can be achieved with two transducers, separated by one quarter of
a cycle.
Fig. 5.2.1 A high accuracy multi-segment transducer (picture courtesy ASL Ltd)
There are 18 electrode segments of 20 degrees each (9 pairs with one cycle per pair)). A rotor screen of the same
size (each side) provides a maximum range of ±10 degrees. When transducer 1 gets to, say, +6 deg. the
measurement is switched to transducer 2, which is then at -4 degrees of its range. As the rotor continues the second
transducer gets to 6 deg. of its range (16 deg. absolute) and the measurement is switched back. The same overlap is
applied in the reverse direction. The hysteresis is necessary to avoid rapid switching back and forth on the
boundary. Hysteresis is easily implemented using a microcontroller.
Transducer 1 Ratio, n
Transducer 2
+1
-10
-40 -30 -20 10 20 30 40
-1
Fig. 5.2.2 The principle of overlapping ranges
Each transducer covers 9 cycles of 20 degrees per cycle (180 deg. each). The technique is inherently stable and
repeatable with very high resolution and it is possible, therefore, to calibrate such a device to achieve an accuracy
of sub-arc second (about 1ppm) with a modest ratio transformer.
8
Part 1: Monograph 3
6. Low cost signal conditioning
Remarkably high accuracy can be achieved without large and expensive IVD or ratio transformer techniques. The
signal conditioner, fig. 6.1, for example, employs negative feedback in a simple and elegant null balance circuit.
Semiconductor switches (MOSFETs) convert the output DC voltage and a reference DC voltage into square wave
signals which drive the energised electrodes (this usually referred to as a “modulator”). The output from the charge
amplifier is amplified, filtered and converted to DC by the synchronous rectifier [1] (also MOSFET switches). The
high gain block (HGB [2]) is an integrator (and, possibly, one or more one-plus-integrators in series). The output
ramps up or down until the output of the synchronous rectifier is zero. The action of the negative feedback,
therefore, is to achieve a null balance. The result is a high level DC output voltage, related to capacitance ratio as
required: -
VOUT C1  C2

VR C1  C2
The only critical parts of the circuit are the modulator and the synchronous rectifier. The overall gain inside the
loop affects the closed loop bandwidth and stability but can vary by 10% with no problem. The effect of any DC
error due to the HGB is reduced by the AC gain before it.
The modulator switches and synchronous rectifier can operate accurately up to a frequency of 100kHz or more,
offering high speed as well as high accuracy (there is a trade-off here). An operating bandwidth of 1kHz is readily
achievable.
The closed loop bandwidth and frequency response are determined by the type of HGB and its frequency response.
A simple integrator, for example, results in a first order low pass response. A two-stage HGB results in a response
the same as a two-stage low pass filter (i.e. lower phase error). A three-stage HGB results in a response the same as
a three-stage low pass filter (i.e. low phase and magnitude error).
The energising voltage, VR, may be derived from a very stable reference (e.g. a 10V regulator chip) for a simple DC
VOUT
output. Alternatively it is possible to use a ratiometric type digital voltmeter to measure the ratio directly,
VR
thus eliminating any variations in VR over time (including low frequency noise) and temperature. An accuracy of
0.001% (10ppm) can be achieved using a readily available high quality DC voltmeter.
For more details on signal conditioning see part 5.
1. Part 5, monograph 3: “Low noise JFET pre-amplifiers”.

2. Part 4, monograph 1: “High gain blocks”
9
At null balance (from fig. 1)

+VR
V1 V1C1  V2 C 2  0
VOUT  VR  VOUT C1  VOUT  VR C 2  0
 VR C1  C 2   VOUT C1  C 2 
+VR
VOUT
V2 VOUT C1  C 2
 
Q
C1 -VR VR C1  C 2
V1
Not Q
Band VOUT
Charge pass Amplifier Synchronous High gain
amplifier filter rectifier Block
Not Q
V2
Q Not Q
Q
Q C2
Not Q
-VR
Fig. 6.1 Ratiometric signal conditioner employing feedback
10
Part 1: Monograph 3
7. Noise analysis
The resolution (smallest detectable change in angle) is usually limited by the noise voltage, VN, generated at the
input of the charge amplifier. The effect of this noise is increased by the “noise gain” of the charge amp, GN. One
can choose to place the noise voltage in series with either of the inputs. When in series with the non-inverting input
it is easy to see that the noise gain is that of a non-inverting amplifier (see fig. 7.1 and imagine V1 and V2 connected
to 0V). The noise gain is, therefore, largely determined by the stray capacitance to ground (in the transducer, the
charge amp and, most significantly, any interconnecting cable). It is important, therefore, to keep this to a minimum
- hence the reason for locating the charge amp as near as possible to the transducer. If the contribution from the
noise current [1] is negligible (usually the case) the output of the charge amplifier is: -
V1C1  V2C2
VCA   VN GN
CF
C1  C 2  CG CG
With: GN  1  
CF CF
The approximation is valid in most cases as the ground capacitance is usually much larger than the transducer
capacitance.
CF
C1
V1
C2 VCA
V2
CG VN
0V
0V
Fig. 7.1 Noise analysis
If one employs the approximation the algebra is simplified and the result will be sufficiently accurate in most cases.
The action of the feedback loop is to adjust V1 and V2 until the output is zero, therefore: -
V1C1  V2C2 C
At null balance: VCA   VN G  0
CF CF
 VR C1  C2   VOUT C1  C2   VN CG  0

The output is, therefore: -
C1  C2 CG
VOUT  VR  VN
C1  C2 C1  C2
The first component is due to the variation in angle (as before) but the second element is due to the noise.
This appears as random fluctuations in the output signal and is usually specified in terms of root mean square
(RMS) voltage.
11
The resolution in terms of angular displacement with the known value of k is: -
CG 1 4
VOUT  NOISE   VN  VR k N with k deg.-1 or k rad-1
C1  C2 45 
The noise, in terms of angle (in radians) is, therefore: -
 VN CG
N 
4 VR C1  C2
Example: -
Sensor electrode: inner radius 2cm and outer radius 5cm operating with a gap of 2mm.
Charge amp with input noise level of 5nV (RMS) in 1Hz of bandwidth.
Ground capacitance; CG = 100pF
Reference voltage: VR = 10V
Permittivity constant: ε0 = 8.85 × 10-12 Fm-1
0 A 0
For a parallel plate capacitor in the form of an annular ring: C 
d

d
r 1
2
 r22 
Half of the capacitance is obscured by the screen so: -
 0  8.85  10 12 25  4

C1  C 2  r
1
2
 r22    15 pF
2 d 2 0.002 10 4
The RMS angular resolution in 1Hz of bandwidth is, therefore: -
 VN CG  5 109 100
N      2.6 109 radians (RMS)
4 VR C1  C2 4 10 15
This is about 0.5 milli-arc seconds! One could easily achieve ten times better using a ratio transformer, with ten
times the operating voltage
12
Part 1: Monograph 4
Linear Capacitive Displacement Transducers

1. Introduction
Capacitive type linear displacement transducers can be made with an accuracy approaching 1ppm of range
and sub-micron resolution and repeatability. The component parts need to be made and assembled with
reasonably high precision but the technology required is well within the capabilities of a normal precision
engineering workshop, equipped for turning, milling grinding and honing. The metal components (usually
stainless steel) can be held together with epoxy resin or, for high temperature applications, with ceramic
spacers for insulation. The most critical component is the linear ball bushing.
N.B. Most other techniques for accurate measurement of linear displacement are incremental (e.g. Laser
interferometry and Moiré fringe). Capacitive transducers measure absolute displacement.
Fig. 1.1 A Linear capacitive displacement transducer
1
1.1 The principle of operation
The following design was invented and patented by Peter Wolfendale. Its principle of operation is very
simple and elegant. Fig. 1.1.1 illustrates the main elements
Reference capacitor
Variable capacitor CV CR
Moving earthed screen Sensing electrode
Fig. 1.1.1 The principle of operation
Two cylindrical capacitors are formed with concentric cylinders with a common co-axial central cylinder. A
fourth concentric cylinder acts as an earthed screen to vary the area of one of the capacitors. The ratio of
capacitance is accurately related to the linear displacement over a useful range: -
CV
 kx with k a constant.
CR
Linearity falls off when the edge of the screen electrode approaches the ends of the variable capacitor due to
the fringe field effect. As a rule of thumb the fringe field effect is negligible when the edge is five times the
gap width from the nominal limit.
The slope depends on the value of the reference capacitor and, therefore, the length of the reference
capacitor electrode, with a small but stable difference due to fringe field effects. The other dimensions are
the same, however, and the value of k is, therefore, approximately the reciprocal of the length: -
CV x

C R xR
N.B. The extra length required due to the fringe field effect, the reference capacitor, the bearing and, often,
the space at the end for connections and the charge amplifier, tend to make the overall length of the
transducer considerably more than incremental types (e.g. Moiré fringe). This is, perhaps the one and only
disadvantage of this type of transducer.
Ball bushing Variable capacitor Reference capacitor
Sensing electrode
Moving earthed screen
Fig.1.1.2 Cross section illustrating the construction (gaps exaggerated)
2
Part 1: Monograph 4
Ratiometric operation has a number of advantages. Specifically: -

 The ratio of capacitance and, therefore, the overall measurement accuracy, is independent of certain
manufacturing tolerances, specifically: actual dimensions. For interchangeability, at the level of 0.01%,
it is sufficient for the internal diameters of the variable and reference electrodes to be accurately the
same and the external diameter of the sensing electrode to be uniform and accurately co-axial. The first
condition is easily achieved if the two electrodes are first machined as one piece and then divided.
 The ratio is independent of temperature, as long as it is uniform throughout the body of the transducer.
 Linearity depends on the uniformity of the cylindricity of the electrode surfaces. They must be
reasonably accurately coaxial, though the design affords some self-compensation for small errors.
 The ratio is independent of the dielectric medium, between the electrodes, as long as it is uniform. The
effect due to small changes in dielectric constant of air, due to humidity, is negligible. The transducer
will also function satisfactorily while submersed in non-conducting liquid.
N.B. repeatability depends mainly on the quality of the ball bushing. With a really good bearing this can be
down to the sub-micron level.
For the highest accuracy the ratio can be measured using a ratio transformer bridge technique.
Ratio winding
screen
Energising winding CR CF
Virtual earth
V1
VS
0V VCA
V2
CV JFET input
0V
Fig. 2.1 Outline schematic of a typical ratio transformer/capacitance bridge
V1CR  V2CV
At null balance: VCA  0
CF
V1 CV
n   kx
V2 CR
N.B. The secondary windings are connected in anti-phase so that the ratio is numerically positive.
The linearity of the transducer falls significantly as CV approaches zero and maximum, due to the fringe
field effect. It is usual, therefore, to provide a small, fixed offset in order to make best use of the range of the
variable winding. The accuracy of ratio from primary to secondary is not critical but the secondary and
subsequent decades are. For more detail on basic ratio transformers see the monograph “Single stage
inductors and transformers” by the same author.
3
Accurate measurement of the capacitance relies on the sensor electrode being maintained at 0V by the action
of feedback of an operational amplifier (aka “virtual earth”).
N.B. This is called a charge amplifier because the output voltage is proportional to the electrical charge on
the feedback capacitor.
The sensor electrode, charge amplifier and the connection between them must be completely surrounded by
a conducting screen connected to 0V. This is to prevent electrical interference from external sources and
also to prevent disturbance of the electric field and, therefore, the capacitances, due to the proximity of
external objects. This is the concept of a “three terminal capacitance” – even though there is a considerable
stray capacitance between the screen and the sensor electrode/virtual earth, there is no voltage difference
and no current flows. The capacitances CV and CR are thereby accurately defined.
An effective screen could be maintained by connecting the transducer to the charge amplifier with a good
quality co-axial cable, though it is better to place the charge amplifier (or at least the first stage - usually a
low noise JFET) as close as possible to the sensor electrode. Best noise performance is achieved with
minimum ground capacitance. See section 5 for more details.
CR CF
V1 Virtual earth
VCA
V2
CV JFET input
0V
screen
Fig. 3.1 A ratiometric capacitive transducer and charge amplifier
V1CR  V2CV
At null balance: VCA  0
CF
4
Part 1: Monograph 4
4. A low cost signal conditioner
Remarkably high accuracy can be achieved without large and expensive IVD or ratio transformer
techniques. The signal conditioner, fig. 4.1, for example, employs negative feedback in a simple and elegant
null balance circuit.
Semiconductor switches (MOSFETs) convert the output DC voltage and a reference DC voltage into square
wave signals which drive the energised electrodes (this usually referred to as a “modulator”). The output
from the charge amplifier is amplified, filtered and converted to DC by the synchronous rectifier (also
usually MOSFET switches). The high gain block (HGB), consisting of one or more integrators in series,
ramps up or down until the DC error is zero. The action of the negative feedback is to achieve a null
balance. The result is a high level DC output voltage, related to capacitance ratio as required: -
VOUT CV

VR CR
The only critical parts of the circuit are the modulator and the synchronous rectifier. The overall gain inside
the loop affects the closed loop bandwidth and stability but can vary by 10% with no problem. The effect of
any DC error due to the HGB is reduced by the AC gain before it.
The modulator switches and synchronous rectifier can operate accurately up to a frequency of 10kHz or
more, offering high speed as well as high accuracy (there is a trade-off here). An operating bandwidth of
1kHz is readily achievable.
The closed loop bandwidth and frequency response are determined by the type of HGB and its frequency
response. A simple integrator, for example, results in a first order low pass response. A two-stage HGB
results in a response the same as a two-stage low pass filter (i.e. lower phase error). A three-stage HGB
results in a response the same as a three-stage low pass filter (i.e. low phase and magnitude error).
The energising voltage, VR, may be derived from a very stable reference (e.g. a 10V regulator chip) for a
simple DC output. Alternatively it is possible to use a ratiometric type digital voltmeter to measure the ratio
VOUT
directly, thus eliminating any variations in VR over time (including low frequency noise) and
VR
temperature. An accuracy of 0.001% (10ppm) can be achieved using a readily available high quality DC
voltmeter.
For more details on signal conditioning see part 5.
5
At null balance: -
+VOUT
V1
0V V1C R  V2CV  0
VOUT  VOUT C R  VR CV  0
0V VOUT CV
V2  
Q VR CR
CR -VR
V1
Not Q
Band VOUT
0V Charge pass Amplifier Synchronous High gain
amplifier filter rectifier block
Not Q
V2
Q Not Q
Q CV Q
Not Q
-VR
Fig. 4.1 A simple, low cost signal conditioner
6
Part 1: Monograph 4
5. Noise analysis
The resolution (smallest detectable change in displacement) is usually limited by the noise voltage, VN, generated
at the input of the charge amplifier. The effect of this noise is increased by the “noise gain” of the charge amp, GN.
One can choose to place the noise voltage in series with either of the inputs. When in series with the non-inverting
input it is easy to see that the noise gain is that of a non-inverting amplifier (imagine V1 and V2 connected to 0V).
The noise gain is, therefore, largely determined by the stray capacitance to ground (in the transducer, the charge
amp and, most significantly, any interconnecting cable). It is important, therefore, to keep this to a minimum -
hence the reason for locating the charge amp as near as possible to the transducer. If the contribution from the
noise current is negligible the output of the charge amplifier is, therefore: -
V1CR  V2CV
VCA   VN GN
CF
CV  CR  CG CG
With: GN  1  
CF CF
The approximation is valid in most cases as the ground capacitance is usually much larger than the transducer
capacitance.
CF
CR
V1
CV VCA
V2
CG VN
0V
0V
V1CR  V2CV C
At null balance, therefore: VCA   VN G  0
CF CF
 V1CR  V2CV  VN CG  0
Divide by CR and V2: -
V1 CV VN CG
   0
V2 CR V2 CR
x VN CG
n  0
xR V2 CR
The second component is clearly the random error in the ratio measurement. In terms of displacement the noise is,
therefore: -
VN CG
x N  xR
V2 CR
7
CR 4 0
The factor  is the capacitance per unit length, for a cylindrical capacitor. The noise, in terms of
xR b
ln  
a
V CG V C b
displacement is, therefore: xN  N  N G ln  
V2 CR xR V2 4 0  a 
Example calculation: -
Sensor electrode: outer diameter a = 6mm
Variable and reference electrodes: inner diameter b = 10mm
Reference electrode length: xR = 20mm
Charge amp with input noise level of 5nV (RMS) in 1Hz of bandwidth.
Ground capacitance; CG = 100pF
Reference voltage: V2 = 10V
Permittivity constant: ε0 = 8.85 × 10-12 Fm-1
CR 4 0
For a cylindrical capacitor the capacitance per unit length is:   218 pFm 1
xR b
ln  
a
The RMS angular resolution in 1Hz of bandwidth is, therefore: -
5 109 100 pF
xN    0.23nm (RMS)
10 218 pFm 1
One could easily achieve ten times better using a ratio transformer, with ten times the operating voltage.
The contribution due to noise current of the charge amplifier is small because of the relatively large ground
capacitance. Suitable JFETs with the required noise resistance are readily available. If the charge amplifier is
incorporated into the transducer (small CG) then a higher noise resistance charge amplifier is recommended. For
more detail see the monographs “Low noise JFET pre-amplifiers” and “An ultra-high input impedance high pass
filter” by the same author.
8
Part 1: Monograph 5
Variable gap capacitive displacement transducers

1. Introduction
Whereas variable gap capacitive displacement transducers are not inherently accurate, they are frequently used as
part of very accurate measurement and/or control systems. The capacitance is usually small (around a picofarad)
but can be measured to the nearest attofarad (10-18F). Sub-nanometre resolution is possible with stable mechanics.
Capacitance also allows non-contacting operation at the point of measurement and the transducer may be fabricated
with robust materials (stainless steel or nimonic alloys, epoxy resin or ceramic insulation etc). This can be very
useful in certain applications and especially in hostile environments (e.g. high temperature and corrosive
atmosphere).
Fig. 1.1 Variable gap capacitive sensors (picture courtesy Physik Instrumente GmbH)
In the example above the transducer in the middle has a linearity better than ±0.1% over a range of 25-75µm and a
resolution of 1nm (RMS) in a bandwidth of 10kHz with their ordinary signal conditioner (E-852.10).
Fig. 1.2 A typical non-linearity curve (courtesy Physik Instrumente GmbH)
1
1.1 Profile measurement
A number of variable gap sensors may be incorporated in a single transducer for measuring small deviations from a
simple geometric profile. Fig 1.1.1, for example, is a bore gauge for measuring internal diameters or cylindricity.
Fig.1.1.1 Four sensors arranged as a bore gauge
The sensors can be made very small. In fig. 1.1.2, for example, chemical milling of thin sheet metal was employed
to construct a cone gauge for the precisely ground seat of a diesel fuel injector.
Fig. 1.1.2 Sixteen tiny senors (eight the other side) for gauging a conical profile
2
Part 1: Monograph 5
2. The guard electrode and charge amplifier
An active guard electrode is essential for high accuracy and stability. It is held at the same voltage as the sensing
electrode in order to substantially remove the effect of the fringe field (to the edge of the guard electrode) and to
shield the sensor from nearby moving objects. The action of the feedback in a charge amplifier performs this
function, as well as providing a voltage output with low source impedance (no longer sensitive to interference). The
following diagram depicts the effect of the fringe field:-
Complete screen continues to

and around charge amplifier
Sensing electrode Concentric guard

electrode
Fringe field
Guard electrode and
screen at the same
voltage as the sensing
electrode – no current
flows.
Target surface
Fig. 2.1 Capacitive transducer with active guard electrode and screen
The target surface needs to be a reasonably good electrical conductor and it is necessary to make electrical
connection to it, possibly through a bearing.
The capacitance of a parallel plate capacitor, with active guard electrode, is accurately related to the area and gap,
thanks to the removal of the fringe capacitance [1]: -
A
C   R 0
x
Where: -
 0  8.85 1012 Fm 1
 R  the relative permittivity of the dielectric medium, usually air.
A = the area in m2
x = the gap in m.
If one assumes that the area is constant then the sensitivity is: -
dC d 1 1 C
  0 A     0 A 2  
dx dx  x  x x
dC dx
Alternatively, a more useful expression is: 
C x
I.e. a 1% increase in gap results in a 1% decrease in capacitance.
1. Part 1, monograph 2: “High accuracy single capacitors”. For a derivation of this formula see section 3.
3
2.1 The charge amplifier
The high gain of the op-amp and feedback operates to maintain zero volts difference between its two inputs [1]. If
the target surface can be isolated from earth and driven with an AC signal the guard electrode is connected to earth.
The sensor electrode is, therefore, maintained at earth potential without a direct connection, hence the commonly
used term “virtual earth”. The rest of the metalwork around the transducer is also earthed though in a way to avoid
earth loops [2]. Any current caused by energising the target surface must be carefully managed and routed back to
the supply in a controlled way.
Virtual earth
+/-15V supply
sensor electrode
output
JFET op-amp
active guard
guard screen (0V)
Epoxy resin earthed screen/casing

Fig 2.1.1 Typical construction of a variable gap capacitative displacement transducer with integral pre-amp
The main features include: -

 Overall earthed screen for mounting (often threaded) and EMC.
 Active guard with thin glue layer for accuracy and reduction of side influences.
 JFET pre-amp for low noise/high resolution.
 Conical sensor electrode for ease of manufacture and to minimize ground capacitance.
 Overall separate screen, which can be earthed if the guard electrode is driven (earthed target)
Analysis shows [1] that best noise performance and, therefore, resolution is achieved when the charge amplifier is
mounted as near as possible to the transducer (minimum capacitance to ground from the virtual earth). In most
cases there is sufficient space to incorporate a small op-amp or a single JFET transistor in the transducer housing. If
high temperature is expected, however, the transducer needs to be remote and connected via good quality co-axial
cable with 100% effective screening. A good choice is semi-rigid PTFE insulated co-axial cable often used by RF
engineers.
1. Part 5, monograph 3: “Low noise JFET pre-amps”.

2. Part 1, monograph 2: “High accuracy single capacitors”. For the avoidance of earth loops see section 2.
4
Part 1: Monograph 5
3. The Ratio transformer/capacitance bridge
A ratio transformer bridge provides the most accurate and stable measurement of capacitance ratio. The reference
capacitor is best positioned near to the transducer so that it shares the same air dielectric. Better still is to
incorporate it as part of the mechanics in such a way as to provide compensation for temperature variations.
Alternatively, materials with very low coefficients of thermal expansion (e.g. Zerodur® with ≈0.02ppm/degC) can
be used. A pair of transducers may also be operated in opposing pairs and the differential ratio measured. For more
detail on differential ratio measurement see the relevant monographs [1 and 2]. Repeatability, stability and,
therefore, accuracy are potentially better than one part per million (1ppm) of range.
Ratio winding
screen
V1 Virtual earth
VS
0V VCA
V2
CV JFET input
0V
Fig. 3.1 Outline schematic of a typical ratio transformer/capacitance bridge
The analysis of the circuit is quite simple. The output of the charge amplifier is: -
V1CR  V2CV
VCA 
CF
V1 CV
At null balance, therefore: 
V2 C R
The connections could be reversed so that the ratio is inversely proportional to transducer capacitance and,
therefore, proportional to displacement. The only disadvantage is the variation in the gain which complicates the
bridge balance algorithm.
V1CR  V2CV dV V
In the above configuration: VCA   CA  2 which is constant.
CF dCV CF
V1CV  V2CR dV V
With reference and variable interchanged: VCA   CA  1 which varies.
CF dCV CF
In practice the displacement is easily calculated, including any corrections for non-linearity, using a digital
computer.
1. Part 1, monograph 3: “Rotary capacitive displacement transducers”.

2. Part 3, monograph 8: “A 16 bit binary differential capacitance bridge”.
5
3.2 Earthing the target surface
It is often unavoidable that the target surface is at earth potential. This is not a major problem and a simple solution
is to provide the charge amplifier with a separate floating power supply and a transformer coupled output. The
interwinding capacitance of the output transformer needs to be kept to a minimum to ensure a high level of
common-mode rejection.
Floating PSU
screen
CR CF
V1-V2 Virtual earth
-V2
VCA
CV JFET input
0V
0V
Fig. 3.2.1 A capacitance bridge with the target surface earthed
With a 1:1 output transformer the output is exactly the same: -
V1CR  V2CV
VCA 
CF
6
Part 1: Monograph 5
4. Noise analysis
The resolution (smallest detectable change in gap) is usually limited by the noise voltage, VN, generated at the input
of the charge amplifier. The effect of this noise is increased by the “noise gain” of the charge amp, GN. One can
choose to place the noise voltage in series with either of the inputs. When in series with the non-inverting input it
is easy to see that the noise gain is that of a non-inverting amplifier (see fig. 4.1 and imagine V1 and V2 connected to
0V). The noise gain is, therefore, largely determined by the stray capacitance to ground (in the transducer, the
charge amp and, most significantly, any interconnecting cable). It is important, therefore, to keep this to a minimum
- hence the reason for locating the charge amp as near as possible to the transducer. If the contribution from the
noise current is negligible the output of the charge amplifier is [1 and 2]: -
V1CR  V2CV
VCA   VN GN
CF
CV  CR  CG CG
With: GN  1  
CF CF
The approximation is valid in most cases as the ground capacitance is usually much larger than the transducer and
reference capacitance.
CF
CR
V1
CV VCA
V2
CG VN
0V
0V
V1CR  V2CV C
At null balance, therefore: VCA   VN G  0
CF CF
 V1CR  V2CV  VN CG  0
Divide by CR and V2: -
V1 CV VN CG
   0
V2 CR V2 CR
 V1 
The ratio  n    is defined so that it is numerically positive (V1 and V2 have opposite polarity): -
 V2 
CV VN CG
n 
CR V2 CR

2. Part 2, monograph 3: “An ultra-high input impedance high-pass filter”
7
The first component is the capacitance ratio, as expected, and inversely proportional to the gap. The second
component is clearly the random error in the ratio measurement. In terms of transducer capacitance: -
CV  CV VN
n with CV  CG
CR V2
The transducer capacitance is inversely proportional to the displacement and so, for small variations (see section 2
for the derivation): -
CV x

CV x
Expressed in terms of displacement the random component is, therefore: -
CG VN
x   x
CV V2
VN is usually specified as the RMS value and so the magnitude of the resolution is: -
CG VN
x  x
CV V2
Example calculation: -
Transducer capacitance: CV = 1pF

Operating gap: x = 1mm
Total ground capacitance: CG = 50pF
Reference voltage : V2 = 10VRMS.
Charge amplifier noise voltage : VN = 5nVRMS Hz
CG VN 50 pF 5 109VRMS
x  x  103 m    25 pm (RMS in 1Hz)
CV V2 1 pF 10VRMS
If the ground capacitance is very small the noise current may become an issue. For details see [1] and [2].

8
Part 1: Monograph 6
Low phase error capacitors and inductors

1. Introduction
Low phase error capacitors and inductors have a number of applications in high accuracy electronics. One
important component in null balance bridges, for example, is used to generate a phase shift of precisely 90 degrees
as part of a quadrature servo [1]. Other applications include high accuracy passive filters [2], active filters [3] and
oscillators [3]. The best capacitors and inductors have phase errors of around 0.2mradians (2 × 10-4). Whereas one
might expect a capacitor to be the obvious (cost-effective) choice, with a wide range of values available, the most
practical for the quadrature servo application turns out to be a low phase error ferrite pot core (with air gap) [4].
2. Polypropylene capacitors
The ideal capacitor has purely negative imaginary impedance. In practice, however, even high quality polymer
dielectric capacitors have impedance with a real part, which can be modelled as a small series or large parallel
resistance, which varies with frequency. The series model is used in this monograph as it simplifies the algebra: -
C RS
Fig. 2.1 Equivalent circuit for a practical capacitor
1
The impedance is, in the complex representation: Z  RS 
jC
The ratio of the real part to the imaginary part is known as the “tanδ”: the tangent of the acute angle to the negative
imaginary axis of the complex number which represents the impedance: -
tan   RS C
Imaginary axis
R
RS
Real axis
j
Z
C
Fig. 1.3 The complex representation of a capacitor (real part exaggerated)
The angle is very small so that, to a very good approximation (in radians): tan   

2. Part 2, monographs 1 and 2: “Two-stage filters” and “Three-stage filters”
3. Part 6, monograph 3: “A circuit for measuring tanδ”.
4. Part 4, monograph 4: “High accuracy amplifiers, integrators and differentiators”. See section 5.
1
The phase error is constant at low frequency - consistent with a lower limit due to the intrinsic characteristic of the
dielectric material. The mechanism is believed to be energy loss as the molecules are rotated, stretched and
compressed (c.f. friction in a spring) [1]. At higher frequency the impedance of the capacitor drops so that the
actual resistance of the connections and thin foil electrodes becomes significant. This hypothesis fits the available
evidence: -
Fig. 2.2 Tanδ for polypropylene dielectric capacitors (courtesy EPCOS AG 2015 [1])
We are concerned, primarily, with low frequency behaviour and a suitable model is a complex capacitance: -
  1 1  j
f  1kHz    RS C is constant  RS   Z  
C C jC jC
In a typical circuit analysis one can, therefore, replace any symbol for an ideal capacitor, C, with the complex
equivalent: -
 C 1  j 
C
C
1  j 
1. Film Capacitors: General technical information, Sept 2015. See section 2.3.2
2
Part 1: Monograph 6
3. Low phase error ferrite transformers
Despite the extra labour cost of winding a transformer a ferrite pot core can provide a cost-effective means of
implementing an accurate 90 degree phase shift of a sinusoidal voltage signal. A differentiator or integrator based
on a low phase error capacitor and resistor would be possible but, for a quadrature servo, it would require a low
phase error isolating transformer (i.e. two-stage) and be less cost-effective. The best choice is a gapped ferrite RM
type pot core made with a manganese-zinc type material. For a brief review of magnetic circuit theory see the
appendix.
Fig. 3.1 The RM type pot core and accessories
Space for
bobbin Air gap
Fig. 3.2 The magnetic circuit of a gapped RM core
Whereas the intrinsic phase error of the best ferrite material is of the order 2mradians (2 × 10-3) the presence of the
air gap results in a reduction, by an order of magnitude, in the phase error at the expense of reducing the effective
permeability of the magnetic circuit. The reluctance of each part of a magnetic circuit depends on the length, cross-
sectional area and permeability [1]: -
L
R
0  R A
0  Permeability of the vacuum 4  107 Hm1
 R  Relative permeability
The total reluctance of the magnetic circuit is the sum of reluctances of each section: -
1 LF 1 LG 1 LE
RT  RF  RG 
0  R
A  
0 AG 0  E AE
F
Where: -
RF and RG are the reluctances of the ferrite sections and air gap respectively.
LF and AF are the lengths and areas of the ferrite sections.
LG and AG are the length and area of the gap section.
 E , LE and AE are the effective permeability, length and area of the equivalent uniform magnetic circuit [2].
1. Part 3, monograph 2: “Single stage inductors and transformers”. See section 2.

2. E.g. a large diameter, small cross-section toroid resulting in uniform magnetic flux.
3
The reluctance allows one to calculate the magnetic flux for the given magneto-motive force (ampere-turns): -
MMF  NI  RT 
In practice the parameters specified and tested in production include the reciprocal of the reluctance (the
“permittance”), the effective relative permeability of each ferrite component and the loss factor for each type of
material. The permittance allows one to calculate the number of turns required for a given inductance and the loss
factor provides, albeit approximately, the tanδ of the resulting inductance: -
1 tan  I
AL  with L  N 2 AL and tan  E  E
RT I
tan  I and  I are the intrinsic phase error and relative permeability of the ferrite material.
The ratio tan  I  I is called the “loss factor” by most manufacturers.
The validity of the latter equation can be demonstrated as follows: -
The phase error can be modelled as a complex permeability: I  I 1 j tan  I 
1 LE 1 LF 1 LG
The effective reluctance is: 
0  E AE 0  R
 
AF 0 AG
The cross-sectional area of the circuit is approximately the same around the circuit and the length of the air gap is
much smaller than the length of the ferrite part of the circuit: -
1
1 1
L  L 
AE  A  AG and LE   LF    G   E   R 1   R G 
 E  R LE  LE 
The multiplying factor depends on the choice of gap and typically varies from 0.02 to 0.1. The tanδ is reduced by
the same factor as the effective permeability: -
1
 L 
1   R G   k  E 1  j tan  E   kI 1  j tan  I 
 LE 
A widely available component is the RM10 core in P11 material (MMG: Magnetic Materials Group) with an air
gap of 0.21mm and the following characteristics: -
 E 160 tan  I
AL  400 nH turn2 I  2250 E  160  k    0.071 and  1.5  10 6
 I 2250 I
The effective tanδ is comparable to the best available polypropylene capacitors: tan  E  2.4  104
The bobbin can comfortably accept 50 turns for both primary and secondary (on separate sections to minimise
capacitance). Each section has ≈ 20mm2 so that 0.3mm diameter enamelled copper wire would be satisfactory.
The self inductance of the primary and mutual inductance (primary to the secondary) are: -
L  N P2 AL  1mH and LM  N P N S AL  1mH  L  0.157 at 25Hz
4
Part 1: Monograph 6
3.2 A practical differentiator circuit
For the detailed analysis see the monograph “High accuracy amplifiers, integrators and differentiators” [1].
The basic idea is to employ the transformer primary as the feedback element in an inverting configuration with a
high gain block so that the input (sine wave) voltage is converted into a current.
The transformer output voltage is proportional to the rate of change of the flux/current and the mutual inductance of
the transformer (Faraday’s law). It is also, therefore, proportional to the rate of change of the input voltage (i.e.
differentiation). The resistance of the primary winding is relatively unimportant as the current is accurately in-
phase with the input voltage. The error contribution due to the high gain block is negligible and the phase accuracy
is largely determined by the pot core [1].
I RL
VE
CS
R RS VOUT
VIN
I
V1
0V
Fig. 3.2.1 A differentiator circuit
As frequency increases the impedance of transformer primary increases as does the gain, limited only by the open
loop gain of the high gain block (HGB). This could result in significant noise and interference at the output. The
snubber (capacitor in series with a resistor) in parallel with the winding has little effect at low frequency but limits
the gain at higher frequency.
The transfer function, in the complex representation s  j  is [1]: -
T s  
VOUT sLM

VIN R
Where LM is the mutual inductance of the transformer.
With a mutual inductance of 1mH (see previous example, section 3.1) and a 10kΩ input resistor the transfer
function is: -
T s   j1.57  105
If the input voltage is the (in-phase) reference voltage in a resistance bridge this represents the maximum range of
the quadrature servo [2]. This is insufficient in many cases and the range can be increased with a differential
amplifier between the reference voltage and the differentiator [3]. This is more practicable than increasing the
mutual inductance or reducing the input resistance.
5
Appendix: Magnetic circuit theory (basics)
In the following analysis I shall assume that the core material is linear with a constant value of permeability. I also
assume that the effect of inter-winding capacitance is negligible and that the applied voltage is a sine wave. A more
in-depth analysis of particular RT and IVD designs, including inter-winding capacitance is undertaken in the
relevant monographs.
Fig. 1 defines the main parameters of a basic inductor with winding resistance: -
R
Magnetic circuit
V
N Φ
Winding with N turns

Fig. 1 An inductor with winding resistance
The magneto-motive force (MMF) generated by the current flowing through the winding is defined as:-
MMF  NI (units: “Ampere-turns”)
The resulting magnetic flux is determined by the reluctance RL of the magnetic circuit.
(c.f. Ohm’s law: V = IR): -
MMF  RL
Reluctance depends on the cross-sectional area, length and permeability of the magnetic circuit: -
LE
RL 
 0  R AE
N.B. The formula for reluctance can be compared with that for the resistance of a conductor with length LE, cross-
sectional area, AE, and conductivity, σ: -
LE
R
AE
Clearly the permeability is analogous to conductivity.
In practice the parameter provided in most data sheets for soft magnetic components is the reciprocal of reluctance.
I call this the “permittance” [1]: -
1   A
AL   0 R E
RL LE
The flux is, therefore:   NIAL
1. According to Wikipedia this term was originally used by Oliver Heaviside for the imaginary part of
admittance, the reciprocal of impedance. That parameter is now widely referred to as the “susceptance”.
6
Part 1: Monograph 6
The changing flux induces a “back EMF”, according to Faraday’s Law: -
d dI
VB  N  N 2 AL
dt dt
dI
If one assumes that the applied voltage is sinusoidal then using the complex representation:  jI  sI
dt
VB  N 2 AL sI  sLI
Where L is the inductance: -
L  N 2 AL
The applied voltage is balanced by the back-EMF plus the resistive voltage drop: -
V  IR  VB  I R  sL
The total impedance is, therefore, the sum of winding resistance and inductive impedance: -
V
Z  R  sL
I
The reader will not be surprised that a key parameter is the relative value of the resistance and inductive
impedance. A useful measure of this is the natural frequency: -
R
N  2f N 
L
In virtually all cases a lower natural frequency is better – lots of turns of thick copper wire. The art of
inductor/transformer design, in this context, is to find the best practical compromise – minimum size and number of
turns that is guaranteed to achieve the accuracy required.
High levels of flux density and core saturation
The effective cross-sectional area of the magnetic circuit, AE, and the number of turns, N, determine the maximum
voltage that can be applied at a given frequency. The limitation is set by the maximum flux density, BMAX, of the
magnetic material. Above this the permeability of the material drops quite sharply, resulting in “saturation”. The
inductance drops accordingly and the current increases. If BMAX is the maximum flux density then the maximum
amount of flux is AEBMAX.
The maximum (sine wave) voltage, at frequency, ω, is, therefore: -
d MAX
VMAX  N  NAE BMAX .
dt
In practical RT and IVD design the BMAX is often set quite low (though not in all cases), compared to power
transformer applications. As a rule of thumb a BMAX of 500mT is the most one can tolerate for mumetal and similar
alloys.
7
Part 2: Monograph 1
Two-stage filters
1. Introduction
High accuracy in this context refers to low phase error, at a frequency sufficiently below (low pass) or above (high
pass) the cut-off frequency of the filter.
The problem with conventional (single-stage) filters is that the phase error, in the pass-band, is first order with
respect to frequency. For a low-pass filter, for example, in the complex representation s  j  : -
T s   T s   1  s   2 s 2
1
and s  1 
1  s
Whereas the in-phase error (the real component) is proportional to frequency squared (very small) the phase error
(imaginary and often referred to as “quadrature”) is directly proportional to frequency often a problem.
Low phase error is achieved by using the “bootstrap” principle: one filter sits upon and is bootstrapped by another.
Two stage low-pass filters, for example, are based on the following structure: -
R1 I1
V1
U1
C1
R2 I2
V2 U2
C2
Fig. 1.1 A generalised two-stage low-pass filter network
The resistors and capacitors can be interchanged to provide a high pass filter: -
C1 I1
V1 U1
R1
C2 I2
V2 U2
R2
Fig. 1.2 A generalised two-stage high-pass filter network
The most basic filters are when both resistors and capacitors are the same and both inputs are connected to the same
low impedance source. The second input (V2) can, however, be driven from the main output (U1) via a voltage
follower to provide higher input impedance and low output impedance, both useful in some circumstances.
1
2. Two-stage low-pass filters
According to Ohm’s and Kirchhoff’s Laws the output voltages are (see fig. 1.1): -
U2 
1
 I1  I 2  U1 
1
 I1  I 2   I 1
sC2 sC2 sC1
From this one can construct the matrix equivalent of Ohm’s Law. To stop the algebra becoming too messy one can
also make a substitution for the impedance of the capacitors  X  1 sC  , restricting the equations to single or, at
most, double-deckers: -
 U1   X 1  X 2 X 2  I1 
      i.e. U  XI
U 2   X 2 X 2  I 2 
This defines the output impedance matrix X . It also proves useful when one replaces the capacitors with inductors
in the analysis of two-stage inductors (see part 3: “Two-stage IVDs and RTs” [1]).
The input impedance matrix equation can also be constructed by noting: -
 V1   U1   R1 0  I1   R1  X 1  X 2 X 2  I1 
             i.e. V  ZI
V2  U 2   0 R2  I 2   X2 R2  X 2  I 2 
This defines the input impedance matrix Z . The inverse of this matrix can be calculated resulting in the matrix
equation for the currents. This is also useful for calculating input impedances: -
I  Z 1V
Combine with the output impedance matrix to obtain the matrix equivalent of the transfer function equation (output
versus input): -
U  XI  XZ 1V  TV
Where T is the transfer function matrix. Define the matrix Y so that: Y  Z Z 1
The inverse of a 2×2 matrix is easy to remember (from “A” level days?): -
1
a b  1  d  b
    
c d  ad  bc   c a 
 R  X2  X2 
Y   2 
R1  X 1  X 2 
The result is:
  X2
1
Define the matrix Ω so that: Ω  Z T  XY so that U ΩV
Z
To find the output voltages, in terms of the inputs, it is now a simple case of calculating only the required
components of Ω and the determinant Z .
1. Part 3, monograph 3: “Two-stage inductive voltage dividers and ratio transformers”
2
Part 2: Monograph 1
2.2 A basic two-stage low-pass filter
R1
VIN VOUT
R2 C1
C2
Fig. 2.2.1 A basic two-stage low-pass filter
If, for example, both inputs are connected to the same low resistance source V1  V2  VIN  the output is: -
Ω11V1  Ω12V2 Ω11  Ω12

VOUT  U1   VIN
Z Z
From above it is not difficult (unlike larger matrices) to calculate all four components: -
 X  X2 X 2  R2  X 2  X2 
Ω   1  
 X2 X 2   X 2 R1  X 1  X 2 
Ω Ω12   X 1 R2  X 2 R2  X 1 X 2 X 2 R1 
Ω   11    
 Ω21 Ω22   X 2 R2 X 2 R1  X 1 X 2 
R1  X 1  X 2 X2
The determinant is: Z  R1R2  R1 X 2  X 1R2  X 1 X 2  X 2 R2  X 2 X 2  X 2 X 2
X2 R2  X 2
Note that the last two terms cancel. The transfer function is, therefore: -
T s  
Ω11  Ω12   X 1R2  X 2 R2  X 1 X 2  X 2 R1
with X1  1 etc.
Z R1R2  R1 X 2  X 1R2  X 1 X 2  X 2 R2 sC1
Divide top and bottom by X 1 X 2 and it is easy to see: -
1  R2C2  R2C1  R1C1 s

T s  
1  R2C2  R2C1  R1C1 s  R1R2C1C2 s 2
1  as
In normalised form s  j  N  : T s  
1  as  s 2
a  R2C2  R2C1  R1C1 N
1
With: N 
R1 R2C1C2
3s  1
If both resistors and capacitors are the same: a  3 and T s  
s  3s  1
2
3
This is the most basic two-stage low pass filter which is useful in many applications.
R
VIN VOUT
C
R
Fig. 2.2.2 A basic two-stage bootstrapped filter
The result is similar to a conventional low pass filter (first order) but with a slight peaking near to the natural
frequency and a very much reduced phase shift at low frequency. See section 2.3 for examples.
2.2.1 Phase shift at low frequency   N 

1  as s2
From above in normalised form s  j  N  : T s    1 
1  as  s 2 1  as  s 2
To a good approximation, therefore, retaining both real and imaginary error components [1]: -
T s   1  s 2  as3
In more convenient form, with frequency in Hz: -
2 3
 f   f 
T  f   1     ja  
1
f  f N  with fN 
 fN   fN  2 R1C1R2C2
Whereas the real component is second order with respect to frequency (the same as a single stage filter) the
imaginary component is now third order and, therefore, very small. This is the phase error, in radians.
One may ask if the phase error of the capacitors is significant. Typical capacitors (polypropylene or polyester
dielectric) have “tanδ” of 1-5mrad. Similarly, stray capacitance in parallel with large resistors would introduce a
phase error. Either would be equivalent to adding a small imaginary component to the parameter a. The algebra
remains valid for complex numbers and the result would be a very small contribution to the real (in phase) error
component. Consider, for example, the transformation: -
3 3 3 3
 f   f   f   f 
ja    ja 1  j    ja    a 
 fN   fN   fN   fN 
In practice, therefore, the operating frequency need only be a factor of 20 or 30 below the natural frequency for the
phase shift to be negligible (< 0.5mrad).
1 1  z 1  z 1  z 2 
1. The method of approximation is:   ... etc
1  z 1  z2 1  z4
1
Now z 1  z 4  1   1  z  z2
1 z
This is usually a sufficiently close approximation to calculate, accurately, both real (in-phase) and imaginary
(quadrature) components of the error.
4
Part 2: Monograph 1
The parameter a determines the degree of resonant peaking. A lower value of a results in a higher peak (c.f. the
“damping ratio” in conventional second order systems): -
At the natural frequency s  j  : T s  

1
1
aj
A higher value results in higher phase error (see previous section) and less attenuation at high frequency: -
At high frequency   N  : T s  
a
s
The issue of different R and C values reduces, therefore, to the question of how much resonant peaking can be
tolerated. In practice a value between 2 and 4 is found to be a good compromise. The following plots are for values
of a = 4 (lowest peak), 2, 1, 0.5 and 0.12 (highest peak): -
Fig. 2.3.1 Examples of peak response versus high frequency attenuation (for dB ×20).
Given the component values the transfer function, natural frequency and accuracy are easily calculated. In the
design process the problem is the other way round. Given the (highest) operating frequency the required accuracy
can be obtained by first selecting the natural frequency. One may be a bit conservative but the obvious trade-off is
the level of attenuation provided at high frequency. The choice of parameter a depends on the application. This
author has employed a value of 2 or 3 with no problems The choice of practical capacitor values is also a
consideration as the range of values is best kept limited (or else hold stock of unusual values): -
Typical capacitor values (each decade): 1 1.5 2.2 3.3 4.7 6.8 10 etc…
Whereas good quality capacitors are available in only a limited range of standard values (up to a maximum of 2.2
μF or possibly 4.7μF in extremis) the range of standard resistor values is much greater: -
Standard resistor values (E24 rage): -
1 1.1 1.2 1.3 1.5 1.6 1.8 2 2.2 2.4 2.7 3

3.3 3.9 4.3 4.7 5.1 5.6 6.2 6.8 7.5 8.2 and 9.1
5
The trick is, therefore, to first choose a practical combination of capacitors, usually with a bit of “trial and error”,
and then calculate the resistances required which give the chosen value for natural frequency and a. The resistors in
the E24 range are about 5% apart and should get one sufficiently close to the target in the vast majority of cases.
For greater precision choose resistors from the E96 range.
Selecting the best combination can also be made easier with a “slide rule component calculator” (see appendix 1).
It is also worth noting that from the available capacitors, the following pairs can make selection much simpler: -
1 1 1 1
0.1  0.22  0.33  0.68  and vice versa. The worst case error is about 10%.
10 4.7 3.3 1.5
The following method is one way to avoid too much “trial and error”: -
1
Define a baseline capacitor, C, and resistor value, R, so that: fN 
2RC
If possible choose cardinal values (e.g. f N  1.6kHz ; R  10k ; C  10nF ) or else use the slide rule calculator.
Define parameters    and  (all >0) such that: -
R1  R R2  R C1  C C2  C and   1
Substitution into the equation for a results in a much simpler expression (the baseline values R, C cancel): -
a  R2C2  R1C1  R2C1 N       and   1
One can remove any explicit involvement of  by noting: -
1 1
   a     and   1
 
This proves that one can choose  as small as one likes (a sufficiently small capacitor for C2) so that the other
parameters are as big as one likes and there is no upper limit to the value of parameter a . The usual problem,
however, is finding a combination of practical values for a nearer to the minimum.
2.3.1 Example calculation: The minimum a  2 : -
The terms in  occur in such a way that the minimum contribution and, therefore, the minimum value is a  2 .
This is easily shown by basic calculus with a change of variable   x  : differentiate and solve for zero (slope):
1 y 1
y x    2 1  0 (at the minimum)
x x x
1
 x  1    1 and    2 (at the minimum) QED.

Clearly the positive result is the only sensible one as all the parameters must be numerically positive. This uses up
one more constraint but the remaining constraint allows us to choose a practical combination of  and  for almost
any value of a (above 2): -
1 1 1
choose    a  2   and  
  
6
Part 2: Monograph 1
For very nearly the minimum choose, therefore: -
   1 and   1    1
Example:   0.01    100 (easy decade values)  a  2.01
For a natural frequency of 10kHz choose, therefore: -
C  1nF R  16k R1  16k R2  160 C1  1nF C2  100nF
2.3.2 Example calculation 2: For a relatively high value a  4
One can still retain the simplification which comes from choosing: -
1 1 1
    2 and  
  
Now   1 so choose   2.2 (standard value capacitor) for reasons which will become apparent.
1 2 1
  2.2     0.47   0.91   1 (near enough)
2.2  0.91
For a natural frequency of 16kHz choose nearest preferred value resistors (E24 range) based on the same baseline
values as before: -
C  1nF  R  10k C1  2.2nF C2  1nF
R1  0.47  10k  4.7k R2  0.91 10k  9.1k
The natural frequency is slightly out (by 2.5%): -
1
fN   16.4kHz
2 R1C1R2C2
The resulting value for a is also very close to target. The most convenient way to calculate it is with the actual
parameter values chosen (in order to coincide with preferred values): -
  2.2   0.47   0.91  1
 a        0.91  1  0.91 2.2  3.9
2.3.3 Widely different values for resistors and capacitors
It is interesting to note the practical consequence of section 2.3.1. The interaction between the bootstrap stage (R2
and C2) and the upper stage is minimised by choosing a much larger value for C2 and a correspondingly lower
value for R2 to arrive at the required time constant: -
a  R2C2  R1C1  R2C1 N a  R2C2  R1C1 N 

R2C2 R1C1
and C2  C1  
R1C1 R2C2
The parameter, a, is seen to simplify and be a function of the ratio of time constants, in the way (as above) so that
the minimum value must be a = 2. This becomes a useful rule of thumb when it comes to actively driven filters…
7
3. Actively driven low-pass filters
A lower value for the parameter a (< 2) can be achieved by employing an active drive for V2. A lower value
reduces the phase error at the expense of a higher peak in the frequency response near to the natural frequency.
This approach also has the advantage of increasing the input impedance and provides very low output impedance. It
is also easier to calculate component values. The general circuit is as follows: -
R1 Voltage follower
VIN
I1 VOUT
C1
I2 R2
C2
0V
Fig. 3.1 A two-stage actively driven Low-pass filter
The input is: VIN  V1 but the other network input is now connected to the follower output: V2  VOUT
Ω11V1  Ω12VOUT Ω11

T s  
VOUT
VOUT  U1   
Z VIN Z  Ω12
The basic network analysis remains the same, with the matrix elements: -
Ω Ω12   X 1 R2  X 2 R2  X 1 X 2 X 2 R1 
Ω   11    
 Ω21 Ω22   X 2 R2 X 2 R1  X 1 X 2 
And Z  R1R2  R1 X 2  X1R2  X1 X 2  X 2 R2
X 1R2  X 2 R2  X 1 X 2
 T s   with X1  1 etc.
R1R2  X 1R2  X 1 X 2  X 2 R2 sC1
Divide top and bottom by X 1 X 2 and it is easy to see: -
1  R2C2  R2C1 s
T s  
1  R2C2  R2C1 s  R1R2C1C2 s 2
1  as
In normalised form s  j  N  the transfer function is of the same form as before: T s  
1  as  s 2
a  R2 C2  C1 N
1
With the same natural frequency: N  but this time:
R1 R2C1C2
If the resistors and capacitors are the same the result is a lower value a  2 which proves to be satisfactory in
many applications.
8
Part 2: Monograph 1
A two-stage filter can also be used as a feedback element for which the natural frequency and the value of a need
to be optimised for reasons of stability. See [1] for example. The method for calculating component values is
similar but much simplified. Define parameters    and  (all > 0) such that: -
R1  R R2  R C1  C C2  C and   1
 a       and   1
The parameter  is not included in the first expression so that one can choose any value of R1 and suitable values
for R2, C1 and C2 for any value of natural frequency. There is no longer a minimum value for parameter a . One
may as well choose cardinal values for the capacitors and then the resistors are in inverse proportion (and there are
lots to choose from).
1
   1  a  2 and 

I.e. given a value of a it is easy to calculate  and then  .
3.3.1 Example calculation: a  5 and    1    2.5 and   0.4
For a natural frequency of 1kHz choose, therefore: -
C  10nF  R  16k  R1  6.4k R2  40k and C1  C2  10nF
The nearest preferred E24 values are 6k2 and 39k for which: -
a  R2 C2  C1 N  5.0

1
fN   995Hz and
2 R1R2C1C2
N.B. One can understand the reason why there is no lower limit to the value of parameter a in terms of positive
feedback around the follower. If the input is connected to 0V it will be noted that the feedback network consists of
a low-pass filter followed by a high-pass filter, with some interaction between the two. The combination is a band-
pass filter. If the cut-off frequency of the high-pass filter is lower than the cut-off frequency of the low-pass filter
the peak loop gain approaches unity (i.e. 100% positive feedback) resulting in low stability margin.
As a rule of thumb, therefore: R1C1  R2C2
A practical approach, if one requires a low value for parameter a, is to simplify the calculation by choosing a much
higher value for C2 and a correspondingly lower value for R2. The interaction between the first and second stage is
much reduced: -
1 R2C2
    a   and    a and R1C1  R2C2
 R1C1
If the resistors and capacitors have the same preferred values other than, say, a factor of 10 the result is a low value
for parameter a: -
C2  10C1 and R1  10R2  a 1
Such pairs are easily obtained for any natural frequency with the slide rule calculator (see appendix 1).
1. Part 6, monograph 2: “A simulated negative capacitor circuit”
9
4. Two-stage high-pass filters
Swap resistors and capacitors and employ the same matrix method as above: -
C1 I1
V1 U1
R1
C2 I2
V2 U2
R2
Fig. 3.2 A generalised two-stage high-pass filter network
According to Ohm’s and Kirchhoff’s Laws the output voltages are: -
U 2  I1  I 2 R2 U1  I1  I 2 R2  I1R1
 U1   R1  R2 R2  I1 
      i.e. U  XI
U 2   R2 R2  I 2 
This defines the output impedance matrix X . The input impedance matrix equation can also be constructed. The
algebra is simplified with  X1  1 sC1  etc: -
 V1   U1   X 1 0  I1   X 1  R1  R2 R2  I1 
             i.e. V  ZI
V2  U 2   0 X 2  I 2   R2 X 2  R2  I 2 
This defines the input impedance matrix Z . The inverse of this matrix can be calculated resulting in the matrix
equation for the currents. This is also useful for calculating input impedances: -
I  Z 1V
Combine with the output impedance matrix equation to obtain the matrix equivalent of the transfer function
equation (output versus input): -
Where T is the transfer function matrix. Define the matrix Y so that: Y  Z Z 1
1
a b  1  d  b
    
ad  bc   c a 
The inverse of a 2×2 matrix is easy to remember:
c d 
 R  X2  R2 
Y   2 
R1  R2  X 1 
The result is:
  R2
Z  R2 R1  R2 R2  R2 X1  X 2 R1  X 2 R2  X 2 X1  R2 R2
10
Part 2: Monograph 1
1
Define the matrix Ω so that: Ω  Z T  XY so that U ΩV
Z
 R  R2 R2  R2  X 2  R2 
Ω   1  
R2   R2 R1  R2  X 1 
then
 R2
 R R  R1 X 2  R2 X 2 R2 X 1 
Ω   1 2 
 R2 X 2 R2 R1  R2 X 1 
To find any of the output voltages, in terms of the inputs, it is now a simple case of calculating only the required
components of Ω and the determinant Z .
Note that the result is identical to that for the two-stage low pass filter network with the substitutions: -
X1  R1 etc.
One can employ this shortcut, at least as a check, when it comes to the more complicated 3 × 3 matrices [1].
4.2 A basic two-stage high-pass filter
C1
VIN VOUT
R1
C2
R2
0V
Fig. 4.2.1 A basic two-stage high-pass filter
If, for example, both inputs are connected to the same low resistance source V1  V2  VIN  the output is: -
VOUT  U1 
Ω11V1  Ω12V2   Ω11  Ω12  V
IN
Z Z
The transfer function is, therefore: -
R1R2  R1 X 2  R2 X 2  R2 X 1
T s   with  X1  1 sC1  etc.
R1R2  R1 X 2  R2 X 2  R2 X 1  X 1 X 2
s 2C1C2 R1R2  sR1C1  sR2C1  sR2C2

Divide top and bottom by X 1 X 2 : T s   2
s C1C2 R1R2  sR1C1  sR2C1  sR2C2  1
as  s 2
 T s   with a  R1C1  R2C1  R2C2 N and  N 
1
1  as  s 2 R1C1R2C2
1. Part 2, monograph 2: “Three-stage filters”
11
4.2.1 Phase shift at high frequency   N 

One can employ the same method as before (see footnote in section 2.2.1). From above in normalised
form s  j  N  : -
as  s 2
T s  
1
1
1  as  s 2
1  as  s 2
T s   1 
1 1 a
To a good approximation, therefore: 1 2  3
 a 1 s s
s 2 1   2 
 s s 
2 3
f  f 
T  f   1   N   ja  N 
1
f  f N  with fN 
 f   f  2 R1C1R2C2
Whereas the real component is second order with respect to frequency (the same as a single stage filter) the
imaginary component is now third order and, therefore, very small. This is the phase error, in radians.
If the resistors and capacitors are the same the result is a basic two-stage high pass filter with a  3
The expressions for natural frequency and the parameter a are exactly the same as for the basic two-stage low pass
filter and the same method may be employed for calculating component values. See section 2.3 and its subsections.
The trade-off between resonant peaking and attenuation are similar: -
At the natural frequency s  j  : T s   1  At high frequency   N  : T s  

j a
a s
The following plots are for values of a = 4 (lowest peak), 2, 1, 0.5 and 0.12 (highest peak): -
Fig. 4.3.1 Examples of peaking versus low frequency attenuation (for dB ×20)
12
Part 2: Monograph 1
5. Actively driven two-stage high-pass filters
Active drive affords the same advantages as with the actively driven low pass filter. Specifically: -
a). An unlimited range of values for the parameter a (especially a value lower than 2).
b). High input impedance and low output impedance.
c). Easier to calculate component values.
Voltage follower
C1
VIN
I1 VOUT
R1
I2 C2
R2
0V
Fig. 5.1.1 A two-stage actively driven high pass filter
The input is: VIN  V1 but the other network input is now connected to the follower output: V2  VOUT
Ω11V1  Ω12VOUT Ω11

 T s  
VOUT
VOUT  U1  
Z VIN Z  Ω12
The basic network analysis remains the same, with the matrix elements (see section 4.1): -
 R R  R1 X 2  R2 X 2 R2 X 1  1
Ω   1 2  X1 
R2 R1  R2 X 1 
with etc: -
 R2 X 2 sC1
The determinant is: Z  R2 R1  R2 X1  X 2 R1  X 2 R2  X 2 X1
R1R2  R1 X 2  R2 X 2
T s  
R2 R1  R2 X 1  X 2 R1  X 2 R2  X 2 X 1  R2 X 1
One of the terms in the denominator cancels R2 X 1  . Divide top and bottom by X 2 X 1 with  X1  1 sC1  etc.
s 2C1C2 R1R2  sR1C1  sR2C1

T s  
s 2C1C2 R1R2  sR1C1  sR2C1  1
In normalised form s  j  N  : -
as  s 2
T s   a  R1  R2 C1
1
with and N 
1  as  s 2 R1C1R2C2
13
5.1.1 Phase error at high frequency
One can employ the same method of approximation. The (normalised) transfer function for high
 
frequency s  1 is, to a very good approximation: -
T s   1 
1 a

s 2 s3
In the more convenient form with frequency in Hz: -
2 3
f  f 
T  f   1   N   ja  N
1
f  f N   with fN 
 f   f  2 R1C1 R2C2
If the resistors and capacitors are the same the result is a lower value a  2 which proves to be satisfactory in
many applications.
The method for calculating component values is similar to the actively driven low pass filter and much simplified: -
Define parameters    and  (all > 0) such that: -
R1  R R2  R C1  C C2  C and   1
 a       and   1
The parameter  is not included in the first expression so that one can choose any value of C2 and suitable values
for R1, R2 and C1 for any value of natural frequency. There is no longer a minimum value for parameter a . One way
of simplifying the calculation is to choose widely different and reciprocal values (i.e. pairs of 10/0.1, 2.2/0.47 or
3.3/0.33) for the capacitors and then calculate resistor values according to: -
1 1 1 
Example:   0.47     2.2    and a  0.47   
   
 1
This provides for a minimum value a  0.47  with     1 although in most cases    1   and, to a
  
good approximation:   2.2a . I.e. given a value of a it is easy to calculate  and then  .
5.3.1 Example calculation: target a 1      2.2 and     0.47
For a natural frequency of 1Hz choose, therefore, base values: C  1F and R  159k
The nearest preferred values are: C1  470nF C2  2.2F R1  75k and R2  330k
a  R2 C2  C1 N  0.88

1
Result: fN   0.995Hz and
2 R1R2C1C2
The value for a is a bit low and so increase R2 to 390k. The natural frequency is reduced a little but that is less
critical: -
f N  0.915Hz a  1.04
14
Part 2: Monograph 1
If the input is connected to 0V it will be noted that the feedback network consists of a high-pass filter followed by a
low-pass filter, with some interaction between the two. The combination is a band-pass filter. If the cut-off
frequency of the high-pass filter is lower than the cut-off frequency of the low-pass filter the peak gain approaches
unity (i.e. 100% positive feedback) and very low stability margin (c.f. the actively driven two-stage low-pass filter,
section 3.4). As a rule of thumb, therefore: -
R1C1  R2C2
An alternative approach is to simplify the calculation by reducing the interaction by choosing a much higher value
for C2 and a lower value for R2: -
a       and   1
1 R1C1
    a   and    a and R1C1  R2C2
 R2C2
If the resistors and capacitors have the same preferred values other than, say, a factor of 10 the result is a low value
for parameter a: -
C2  10C1 and R1  10R2  a 1
Such pairs are easily obtained for any natural frequency with the slide rule calculator (see appendix 1).
5.5 Input impedance
From the network analysis we obtained the equations: I  Z1V with Y  Z Z 1 and: -
 R  X2  R2 
Y   2   X1  1 sC1  etc: -
R1  R2  X 1 
with
  R2
And Z  R2 R1  R2 X1  X 2 R1  X 2 R2  X 2 X1
The network is connected so that: V1  VIN and V2  VOUT  VIN T s 
Y11V1  Y12V2 Y11  Y12T s 

 I1   VIN
Z Z
I1 R  X 2  R2T s 
The input admittance (reciprocal of impedance) is, therefore: AIN   2
VIN Z
X 2  R2 1  T s 
 AIN 
Z
Z
Divide top and bottom by X1X2 and note from above:  s 2C1C2 R1R2  sR1C1  sR2C1  1
X1 X 2
One can express this factor in the normalised form s  j  N  : -
Z 1
 1  as  s 2 with N 
X1 X 2 R1C1R2C2
  1 
To reveal: AIN  
1

2 

R2
1  T s 
 1  as  s  X 1 X 1 X 2 
15
as  s 2
Also in normalised form, from above: T s   so that 1  T s  
1
1  as  s 2 1  as  s 2
R2 s2
This simplifies. In normalised form:  s 2 R2C1C2 
X1 X 2 R1
I shall retain the capacitive admittance term 1 X 1 for reasons that will become clear.
1  a
Note that, at high frequency, to a good approximation:   N   1
 2 1  
1  as  s 2
s  s
1  a  1 1  a 
 AIN  2 
1    1   
s  s  X 1 R1  s 
Now 1 X 1 is imaginary and 1/R1 is real and, therefore, the small corrections are insignificant. To a very good
approximation, therefore, the significant real and imaginary components are contained within: -
1 1 1 1
AIN   2   
Z IN s  X 1 R1 
This is how impedances add in parallel. The input appears, therefore, as a small negative capacitance (i.e.
inductive) in parallel with a large negative resistance. Both impedances are frequency dependent. In more
convenient form, with frequency in Hz: -
2
1 f  f  1
fN   AIN   j N 2f N C1   N 
2 R1C1R2C2  f   f  R1
The imaginary component of impedance increases in proportion to frequency, relative to the impedance of the
capacitor at the natural frequency. The impedance of the real component increases as the frequency squared.
Alternatively one can express the components of the parallel impedances due to the capacitor and resistor as
follows: -
2
1 1 1  f  1  f 
AIN    with Z C  j  and Z R    R1
Z IN ZC Z R  f N  2f N C1  fN 
For the previous example: C1  470nF and R1  75k with f N  0.915Hz
At 0.915Hz the impedance of the capacitor is: X 1  f N  

1 1
   j370k
sC1 j 2f N C1
 X 1  f N   j30M
75
At 75Hz this becomes: ZC 
0.915
2
 f 
The real component (in parallel) at 75Hz is: Z R    R1  500M
 fN 
At high frequency the real component is significantly larger than the imaginary component and the effect of the
capacitor dominates: the input “looks like” a very large inductor.
16
Part 2: Monograph 1
6. An LCR low-pass filter with two-stage response
6.1 Introduction
A useful variant, for high cut-off frequency, is a filter based on an inductor, capacitor and resistor. The dynamic
response is the same as a two-stage low-pass filter and its output impedance, at low frequency, is sufficiently low
(and mainly inductive) to connect directly to the feedback capacitor in a negative capacitor circuit [1].
L
VIN VOUT
C
0V
Fig. 6.1.1 An LCR filter with two-stage response
According to Kirchhoff’s and Ohm’s laws, in the complex representation: -
1
R
1  sRC
T s  
VOUT sC 

 sL 1  sRC  s CL
2
VIN 1
R
sC
1  as
1
with a  RCN and N 
1  as  s 2 LC
The stability (see section 2.3) and error analysis are the same. In convenient form, with frequency in Hz: -
2 3
 f   f 
T  f   1     ja  
1
 fN   fN  2 LC
The main application is in a circuit for simulating a negative capacitor. It is important that the output is sufficiently
low and, preferably, imaginary. When in series with a capacitor the effect is a small reduction in the capacitance
but not a phase error. The output impedance is the RC series combination in parallel with the inductance.
 1 
R   sL
Z OUT s    sC 

1  sRC sL
2
1
R
sC
At low frequency, the output impedance is, therefore, substantially the inductance: -
s 2CL  1  ZOUT s   sL
1. Part 6, monograph 2: “A simulated negative capacitor circuit”

17

Procedure: -
1. Calculate the required time constant τ = RC and write it in the form   10 N where α is between 1.0 and 9.9.
2. Record the required value for N.
3. Calculate X0 = log10 α (X0 should be between 0.0 and 1.0).
4. Place the Y1 marker at X0 on the X scale and look for the two values of R and C that most closely match.
1
Note: Apart from factors of 10 X 0  log 10 RC  log 10 R  log 10 C  log 10 R  log 10
C
1
The slide rule performs the addition X 0  log 10  log 10 R
C
5. Try the Y2 marker at X0 to see if there is a better match (equivalent to ten times smaller value)
6. Choose suitable values of A and B (R×10A and C×10B) so that RC × 10A+B = τ
Note: Depending on the application A is usually between 2 and 6 (i.e. R is between 100Ω and 1MΩ.) and B can range from
minus 12 (pico farads) to minus 2 (large electrolytics).
Example: τ = 2.04μs = 2.04 ×10-6s and so X0 = 0.31

The best fit is R = 3.0 and C = 6.8 so practical values are R = 3×103 and C = 6.8×10-10 i.e. 3kΩ and 680pF.
Note: The same method may be used for calculating inductor/capacitor combinations where LC  1 and fR is the
2f R 2
resonant frequency.
E24 Resistor values
1.0 1.1 1.2 1.3 1.5 1.6 1.8 2.0 2.2 2.4 2.7 3.0 3.3 3.6 3.9 4.3 4.7 5.1 5.6 6.2 6.8 7.5 8.2 9.1 10
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
X Scale
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Cut along here
1.0 8.2 6.8 5.6 4.7 3.9 3.3 2.7 2.2 1.8 1.5 1.2 1.0
Y1 Marker Y2 Marker
18
Part 2: Monograph 2
Three-stage filters
1. Introduction
High accuracy in this context refers to not only low phase error (c.f. two-stage filters) but also low magnitude error.
With three-stage filters the phase error (imaginary or “quadrature”) remains third order, with respect to frequency,
but the in-phase (real) error becomes fourth order and negligible at a frequency sufficiently far away from the cut-
off frequency.
The generalised networks for low-pass and high-pass filters are: -
R1 I1 C1 I1
V1 U1 V1 U1
C1 R1
R2 I2 C2 I2
V2 U2 V2 U2
C2 R2
R3 I3 C3 I3
V3 U3 V3 U3
C3 R3
0V 0V
Fig. 1.1 Generalised three-stage filter networks
In practice the only applications known to the author are for actively driven high-pass filters. If the reader is
interested, however, the matrices and equations for the low-pass network and circuits can be easily derived with the
substitutions: R1  X1 and X1  R1 etc. For the high-pass network, according to Ohm’s and Kirchhoff’s Laws, the
output voltages are: -
U 3  R3 I1  I 2  I 3  U 2  R3 I1  I 2  I 3   R2 I1  I 2  U1  R3 I1  I 2  I 3   R2 I1  I 2   R1I1
The output impedance matrix equation is, therefore: -
 U1   R1  R2  R3 R2  R3 R3  I1 
    
U 2    R2  R3 R2  R3 R3  I 2  or U  XI
U   R3  I 3 
 3  R3 R3
The input impedance matrix equation is: V  ZI
 V1   U1   X 1 0 0  I1 
       1
V2   U 2    0 X2 0  I 2  X1  etc
V  U   0 sC1
 3  3  0 X 3  I 3 
 V1   R1  R2  R3  X 1 R2  R3 R3  I1 
    
 V2    R2  R3 R2  R3  X 2 R3  I 2 
V   R3  X 3  I 3 
 3  R3 R3
1
Invert this equation to calculate the input currents and impedances.
Y
Define Y such that: Y  Z Z1  I V
Z
1.2 Cramer’s Rule
For the inverse matrix one can use Cramer’s Rule (see appendices 1 to 3): -
Z j 
Given Vi  Z ij I j then I j  where Z j  is the Z matrix with the jth column replaced by Vi .
Z
Each determinant Z j  is sorted into terms of Vi from which the components of the matrix Y can be extracted.
The process is laborious but not difficult. The algebra can be kept to a minimum if terms are retained in the
form R 2 , RX and X 2 then R 3 , R 2 X , RX 2 and X 3 . These later translate easily into the coefficients in the
polynomial in s .
The task is made easier and less error prone if all the equations required are first copied and pasted into a single
equation object. The terms can then be copied and pasted and the unnecessary stuff deleted.
The determinant is (see appendix 2): -
Z  R1R2 R3  R2 R3 X1  R1 R2  R3 X 3  R3 R1  R2 X 2  R1  R2  R3 X 2 X 3  R2  R3 X1 X 3  R3 X1 X 2  X1 X 2 X 3
The components of Y for a high-pass network are (see appendix 1): -
First row: -
Y11  R2 R3  R2  R3 X 3  R3 X 2  X 2 X 3
Y12   R2 R3  R2  R3 X 3
Y13   R3 X 2
Second row: -
Y21   R2 R3  R2  R3 X 3
Y22  R1  R2 R3  R3 X 1  R1  R2  R3 X 3  X 1 X 3
Y23   R1R3  R3 X 1
Third row: -
Y31   R3 X 2
Y32   R1R3  R3 X 1
Y33  R1 R2  R3   R2  R3 X 1  R1  R2  R3 X 2  X 1 X 2
Combine with the output impedance matrix equation to get the matrix equivalent of the transfer function equation
(output versus input): -
1
Define the matrix Ω so that: Ω  Z T  XY and, therefore: U ΩV
Z
For the various filter configurations one need only calculate the determinant and those components of Ω required.
2
Part 2: Monograph 2
2. Actively driven three–stage bootstrapped high pass filter (type 1)
The following is a JDY design used in an early version of the F18. The reason for connecting C3 to the input, rather
than being driven by the output (see type 2), remains a mystery.
C1 I1
VIN
VOUT
R1
I2 C2
R2 Voltage follower
C3 I3
R3
0V
Fig. 2.1.1 A three-stage actively driven high pass filter – the “JDY special”
For the circuit, fig. 2.1.1: VOUT  U1  V2 and VIN  V1  V3
The output is, therefore: VOUT  U1 

1
Ω11V1  Ω12V2  Ω13V3   Ω11  Ω13 VIN  Ω12VOUT
Z Z
Ω11  Ω13
Re-arrange and simplify for the transfer function: T s  
Z  Ω12
From appendix 2 the determinant is (with X1  1 sC1 ) etc: -
The required matrix elements are (from appendix 3): -
11  R1R2 R3  R1 R2  R3 X 3  R1  R2 R3 X 2  R1  R2  R3 X 2 X 3

12  R2 R3 X1  R2  R3 X1 X 3
13  R3 X1 X 2
R1R2 R3  R1 R2  R3 X 3  R1  R2 R3 X 2  R1  R2  R3 X 2 X 3  R3 X 1 X 2

 T s  
R1R2 R3  R1 R2  R3 X 3  R3 R1  R2 X 2  R1  R2  R3 X 2 X 3  R3 X 1 X 2  X 1 X 2 X 3
Divide top and bottom by X 1 X 2 X 3 for the more conventional form: -
R1R2 R3C1C2C3s 3  R1 R2  R3 C1C2  R3 R1  R2 C1C3 s 2  R1  R2  R3 C1  R3C3 s
T s  
R1R2 R3C1C2C3s 3  R1 R2  R3 C1C2  R3 R1  R2 C1C3 s 2  R1  R2  R3 C1  R3C3 s  1
3
If the Rs and Cs have the same values the normalised transfer function s  j  N  is much simpler and of the
form expected. Note that the coefficients are at the upper limit for a practical design:-
s 3  4s 2  4s
T s  
1
N 
s 3  4s 2  4s  1 RC

s 3  bs 2  as
The full transfer function is, in normalised form s  j  N  : T s   3
s  bs 2  as  1
With: a  R1  R2  R3 C1  R3C3 N b  R1 R2  R3 C1C2  R3 R1  R2 C1C3 N2
N  R1R2 R3C1C2C3  3
1
And
Simulation shows that acceptable values for a and b are between 2 and 4. As with the two-stage filter the lower the
value the greater is the resonant peaking and better attenuation at low frequency. Clearly, in this case, one needs to
avoid the combination a  b  1 which results in an infinite peak (the denominator is zero at the natural
frequency). The following depicts a range of values of pairs between a =2 b = 3 (highest peak), and a =3 b = 4
(lowest peak). See section 3.4 for a practical circuit and component values: -
Fig. 2.3.1 Examples of peak response versus attenuation at low frequency (for dB ×20)
T s   1 
1
Note that the transfer function may be expressed:
s  bs  as  1
3 2
At high frequency the magnitude of the second term is small and inversely proportional to frequency cubed. For a
full analysis one needs to extract the significant real (in-phase) and imaginary (quadrature) error components….
4
Part 2: Monograph 2
2.4 Errors at high frequency   N 
In normalised form s  j  N  being careful to retain terms at least down to order s-4: -
 
 
T s   1  3   1  3 1  
1 1 1 1 b
 1  
s  bs  as  1
2
s 1   
3
b a 1 s  s
 3 
 s s 2
s 
To a very good approximation, therefore: -

T s   1 
1 b
  N  
s3 s 4
The real error term is proportional to b and of fourth order with respect to frequency. The parameter a contributes
very little to the imaginary error (fifth order with respect to frequency). In more convenient form, with frequency in
Hz: -
3 4
f  f 
T  f   1  j N   b N
1
f  f N   with fN 
2 R1C1R2C2 R3C3 3
1
 f   f 
Note that the natural frequency is the geometric mean of three characteristic frequencies.
2.4.1 An interesting result
Note also that the phase error is numerically negative (phase lag) but this is only the case for high frequency. For
lower frequencies the phase shift is positive (phase lead) as one would expect for a high pass filter: -
Fig. 2.4.1.1 The phase shift is negative at high frequency (a = 4 so log a  0.301 )
5
The frequency at which the phase becomes zero is an interesting result. If one assumes that the natural frequency,
N  1(to simplify the algebra) then the transfer function is: -
T s  
 b 2  j a   3  
1  b 2  j a   3  
 
Multiply top and bottom by the complex conjugate 1  b 2  j a   3 to make the denominator real: -
T s  
 b 2
  
 j a   3 1  b 2  j a   3 
1  b   a   
2 2 3 2
The imaginary part is zero for zero phase shift: -
   
b 2 a   3  1  b 2 a   3  a   3  0 
a   3  0   0 or  a
Clearly the positive result is valid. More generally, for zero phase shift:   aN
Given the coefficients a and b one can determine the nearest preferred component values using a similar method as
with the two-stage design. This time it is a bit more complicated as there are six parameters to consider: -
1
Define a baseline capacitance and resistance value so that: fN 
2RC
If possible choose cardinal values (e.g. f N  1.6 Hz ; R  1M ; C  100nF ) or else use the slide rule calculator
(see appendix 4). Define, also, parameters       (all > 0) such that: -
R1  R R2  R R3  R C1  C C2  C C3  C
and   1
Substitution into the equations for a and b results in some simplification: -
a  R1  R2  R3 C1  R3C3 N b  R1 R2  R3 C1C2  R3 R1  R2 C1C3 N2
 a           b              and   1
The equations are still complicated, however, and it is not obvious how to choose the best combination of
parameters. Given a and b there are six “unknowns” but only three equations (constraints). One can afford to
introduce more constraints in order to simplify the problem. For example: -
In the equations for a and b the parameters  and  seem to play the main role. One could choose  and  to be
less than 1 in order to achieve near the minimum values – usually the case. One or more of the other parameters
must compensate by being greater than 1. Looking at how they combine the most likely candidates are  and  .
Consider the further constraints: -
1 1 1
 and   
  
6
Part 2: Monograph 2
The equations are now much simpler with the lower limits a  b  1 : -
 1  1
a  1         and b  1          b  a     
   
There are now three unknowns and only two equations. It is possible, in principle, therefore to select a value for
one of the unknowns and then calculate the others. The algebra turns out to be a bit complicated but, fortunately,
unnecessary. Simulation shows that a = b provides a useful range of choices. Consider one more constraint: -
   a  b  2     2
The minimum value for both a and b is now 2, but that is also OK. One can choose one of the limited practical
values for  and then calculate the value of  required to achieve the target a and b.
Consider one last constraint to make the calculation even simpler: -
   a  b  2  2 2
The range of choice is now quite restricted. Fortunately the range of standard capacitor values is sufficient for the
range of filter characteristics usually required 2  a, b  4 . A useful example is a design for operation at 75Hz
(1.5 × supply frequency). A natural frequency of 1.6Hz provides sufficiently low in-phase and quadrature errors:-
3 4
f  f 
f N  1.6Hz and f  75Hz  T  f   1  j N   b N   1  j105  b  2  10 7
 f   f 
It is no coincidence that a natural frequency of 1.6Hz allows for cardinal values for base values R and C and so the
reciprocal relations between the most common preferred values makes selection easy.
1 1 1 1
0.1  0.22  0.33  0.68  and vice versa, with a worst case error of 10%
10 4.7 3.3 1.5
    0.1 0.22 0.33 0.47 0.68 1.0

     10 4.7 3.3 2.2 1.5 1.0
a=b= 2.02 2.10 2.22 2.44 2.92 4
According to the strategy above the values of R1, C1 and R3 are kept low while R2, C2 and C3 are correspondingly
high relative to the base values: -
1 1 1
       a  b  2  2 2
  
This is equivalent to having a relatively low time constant R1C1, a high value for R2C2 and a medium value for R3C3
so that the geometric mean of the corresponding frequencies is the natural frequency.
1
fN 
2 R1C1R2C2 R3C3 3
1
As a rule of thumb, therefore, a low value for parameters a and b is obtained by a larger difference between the low
time constant and the high time constant (equivalent to a low value for  ). It should be noted, however, that the
parameters  and  do not appear in the equations in a symmetrical way and, therefore, the medium time constant
must be obtained by a low value for R3 and a correspondingly high value for C3.
7
For part of an early F18 design JDY found a nice combination by a method which remains a mystery.
R1  R2  160k R3  91k C1  680nF C2  1F C3  2.2F

1
fN   1.05Hz
2 R1C1R2C2 R3C3 3
1
Clearly a natural frequency of 1Hz was the target. The most convenient way to calculate a and b is now to choose
base values for 1.05Hz: -
C  1F and R  152k
a          
160  160  91  0.68  91 2.2  3.15
152
160 160  91 91 160  160 

b               0.68     2.2    3.07
152 152 152 152 
The lowest operating frequency is 25Hz and the application was for AC coupling the last three digits (decades 5, 6
and 7) from a multiplying R-2R DAC to a pair of two-stage transformers (each of 100:1 step down) with a low DC
error follower (AD547 op-amp). At 25Hz: -
3 4
f  f 
f N  1.0Hz  T  f   1  j N   b N   1  j 6  10 5  7  10 6
 f   f 
With 7ppm in-phase error the performance is well within the error budget required (i.e. 100ppm in-phase to be
safe) and the quadrature error is negligible (also reduced by a factor of 10,000). A natural frequency of 1.6Hz
would have been perfectly satisfactory. Using the method above with a slightly reduced target for a = b = 2.44: -
Choose base values: C  1F and R  100k f N  1.6Hz
      0.47       2.2
a  b  2  2 2  2.44
R1  47k R2  220k R3  47k C1  470nF C2  2.2F C3  2.2F
Alternatively one could increase the resistors and decrease the capacitors by a factor of ten. At 25Hz: -
3 4
f  f 
f N  1.6Hz  T  f   1  j N   b N   1  j 2.6  10 4  4.1  10 5
 f   f 
The in-phase error of 41ppm, reduced by a factor of 10,000, contributes an error of 4.1ppb!
The reader may ask “what about the voltage follower error?” At low frequency this is not usually an issue and
a reasonably good single op-amp should suffice [1]. There is always the option, however, to use a high accuracy
voltage follower [2], based on a two or three-stage high gain block [1].

2. Part 4, monograph 2: “High accuracy voltage followers”
8
Part 2: Monograph 2
3. Actively driven three–stage high-pass filter (type 2)
An interesting variant is to drive both lower stages of the network from the output. The filter characteristic is not
hugely different compared to type 1 but it does have much higher input impedance. It also opens up the possibility
of extremely high input impedance (very small C1 and very large R1). See the monograph “An ultra-high input
impedance high-pass filter” by the same author [1].
Voltage follower
C1
VIN
VOUT
R1
C2
R2
C3
R3
0V
Fig. 3.1.1 A three-stage actively driven high pass filter
Fortunately most of the analysis required has been done for the network (see section 1.1). For the circuit fig. 3.1,
assuming an ideal follower: -
VOUT  U1  V2  V3 and VIN  V1
The output is, therefore: -
11V1  12V2  13V3 11VIN  12  13 VOUT

VOUT  U1  
Z Z
11
Re-arrange and simplify for the transfer function: T s  
Z  12  13
The required matrix elements are (from appendix 3): -
11  R1R2 R3  R1 R2  R3 X 3  R1  R2 R3 X 2  R1  R2  R3 X 2 X 3

12  R2 R3 X1  R2  R3 X1 X 3
13  R3 X1 X 2
9
With the result: -
R1R2 R3  R1 R2  R3 X 3  R1  R2 R3 X 2  R1  R2  R3 X 2 X 3

T s  
R1R2 R3  R1 R2  R3 X 3  R3 R1  R2 X 2  R1  R2  R3 X 2 X 3  X 1 X 2 X 3
Divide top and bottom by X 1 X 2 X 3 : -
R1R2 R3C1C2C3 s 3  R1 R2  R3 C1C2  R3 R1  R2 C1C3 s 2  R1  R2  R3 C1s

T s  
R1R2 R3C1C2C3s 3  R1 R2  R3 C1C2  R3 R1  R2 C1C3 s 2  R1  R2  R3 C1s  1
If the Rs and Cs are the same the normalised transfer function is s  j  N  : -
s 3  4s 2  3s
T s   N  R1R2 R3C1C2C3  3
1
s 3  4s 2  3s  1
The result is a slight increase in peaking compared to the basic type 1 three-stage filter. The quadrature and in-
phase errors are the same: -
3 4
f  f 
T  f   1  j  N   4 N 
1
f  f N  fN 
 f   f  2RC

s 3  bs 2  as
The full transfer function is, in normalised form s  j  N  : T s  
s 3  bs 2  as  1
With a  R1  R2  R3 C1N b  R1 R2  R3 C1C2  R3 R1  R2 C1C3 N2
N  R1R2 R3C1C2C3  3
1
And
Note that the equation for b is the same as for a type 1 high pass filter but the equation for a has lost a term.
Note, also, that the transfer function may again be expressed as: -
T s   1 
1
s  bs  as  1
3 2
To a very good approximation, therefore, also in normalised form s  j  N  the error analysis is the same as for
a type 1 filter (see section 2.4): -
T s   1 
1 b
  N  
s3 s 4
3 4
f  f 
T  f   1  j N   b N
1
f  f N   with fN 
2 R1C1R2C2 R3C3 3
1
 f   f 
10
Part 2: Monograph 2
1
As before choose baseline capacitor and resistor values so that: N 
RC
Define parameters       (all > 0) such that: -
R1  R R2  R R3  R C1  C C2  C C3  C
and   1
Substitution into the equation for a and b results in some simplification: -
a         b             
N.B. The equation for a has lost the term  . To simplify further apply the same constraints as before: -
1 1 1
   
  
 1  1
a         b  1        
   
The difference is: b  a  1     
One could make a and b the same but further analysis shows that both would have to be large. Fortunately it is OK
to have b  a  1with the further simplification: -
   a  1     2 and b  2     2
1
Finally, consider the constraint:    a  22 and b  3 2

The range of choice is again restricted but the range of standard values is sufficient for most applications: -
1 1 1
     
  
    0.1 0.22 0.33 0.47 0.68 1.0

    10 4.55(4.7) 3.03(3.3) 2.13(2.2) 1.47(1.5) 1.0
a= 2.01 2.05 2.11 2.22 2.46 3
b= 3.01 3.05 3.11 3.22 3.46 4
11
N.B. In this case a good compromise is the simplest: the component values being the same (a = 3, b = 4) and
another advantage of the type 2 filter. The following includes, for the highest peak (a = 2, b = 3), middle (a = 2.46,
b = 3.46) and the lowest (a = 3, b = 4): -
Fig.3.4.1 Peaking versus attenuation (for dB ×20)
3.5 Input impedance
One of the main advantages of a type 2 high pass filter is the extra boost to the input impedance, compared to a
two-stage filter. The input current is: -
Y11V1  Y12V2  Y13V3

I1  with V1  VIN and V2  V3  VOUT  T s VIN
Z
The first row of the matrix consists of the following elements (see appendix 1): -
Y11  R2 R3  R2  R3 X 3  R3 X 2  X 2 X 3 Y12   R2 R3  R2  R3 X 3 and Y13   R3 X 2
Y11  Y12  Y13 T s 

I1  VIN
Z
R2 R3  R2  R3 X 3  R3 X 2  X 2 X 3  R2 R3  R2  R3 X 3  R3 X 2 T s 

 I1  VIN
Z
X 2 X 3  R2 R3  R2  R3 X 3  R3 X 2 1  T s 

 I1  VIN
Z
12
Part 2: Monograph 2
At high frequency the impedance of the capacitors is much smaller than the resistors and so, to a good
approximation, the input admittance is: -
I1 X X  R2 R3 1  T s 
AIN   2 3
VIN Z
Divide top and bottom by X 1 X 2 X 3 (with X1  1 sC1 ) etc but retain the term in 1/X1 for reasons that will become
clear. Retain, also, the second largest term in the denominator until it becomes clear when it is insignificant: -
1 X 1  s 3C1R2C2 R3C3 1  T s 
AIN 
s 3 R1C1R2C2 R3C3  s 2 R2C2 R3C3  R1 R2  R3 C1C2  R3 R1  R2 C1C3   ...
The factor 1  T s  is small at high frequency and, in normalised form s  j  N  : -
T s   1  N  R1R2 R3C1C2C3  3
1 b 1
From section 3.3:   N   with
s3 s 4
1  b
 1  T s   1  
s3  s 
s3
Also in normalised form: s C1R2C2 R3C3 
3
R1
 
And: s 3 R1C1R2C2 R3C3  s 2 R2C2 R3C3  R1 R2  R3 C1C2  R3 R1  R2 C1C3   s 3 1  
 s
With the dimensionless parameter: -
  R2C2 R3C3  R1 R2  R3 C1C2  R3 R1  R2 C1C3 N2
To a very good approximation, therefore, in normalised form s  j  N  : -
 1 1  b  1   
AIN    1    3 1  
 X 1 R1  s   s  s
Now 1 X 1 is imaginary and 1/R1 is real and the small corrections due to  and b are insignificant. To a very good
approximation, therefore, the significant real and imaginary components are contained within: -
1 1 1
AIN  
3 
 
s  X 1 R1 
The input admittance is the capacitance, C1, in parallel with resistance, R1 reduced in proportion to frequency
cubed and also subject to a phase shift. In more convenient form, with frequency in Hz: -
3
f  1 1
f  f N  AIN  j N    
 f   X 1 R1 
13
Alternatively one can express the components of the parallel impedances due to the capacitor and resistor as
follows: -
2 3
1 1 1  f  1  f 
AIN    with Z C    and Z R   j   R1
Z IN Z C Z R  f N  2f N C1  fN 
The component due to the capacitor becomes negative real and that due to the resistor is negative imaginary (i.e. a
very large negative resistance in parallel with a very small capacitance). Both are frequency dependent. In practice
the impedance of the capacitor is smaller than that of the resistor (i.e. its admittance is much larger) and the input
impedance is, therefore, substantially a large negative resistor.
It is entirely possible for a high input impedance (e.g. JFET input) follower to permit a value of R1 as high as 5GΩ.
Such resistors are readily available and quite accurate and stable. The corresponding capacitance value for a stable
filter with a natural frequency of 1Hz thus results in: -
R1  5G and f N  1Hz  C1  33 pF
The impedance of C1 at the natural frequency is: X 1  f N  

1 1
   j 4.8G
sC1 j 2f N C1
2
 75  1
At 75Hz this becomes: ZC      27T
 1  2f N C1
3
 f 
The imaginary component (due to the resistor) at 75Hz is: Z R   j   R1  2 jP (Peta = 1015)
 fN 
At high frequency the imaginary component is significantly larger than the real component and the effect of the
capacitor dominates. Clearly this is so large that other factors must be considered. It is possible, however, to
employ very good insulators (e.g. PTFE, ceramic or sapphire) an active guard and the “inside-out” configuration to
eliminate the effects of stray capacitance. See the monograph “An ultra-high input impedance high-pass filter” by
the same author [1].
14
Part 2: Monograph 2
Appendix 1: Cramer’s method for matrix inversion (Three-stage high-pass network)
Z j 
Given Vi  Z ij I j then I j  where Z j  = the Z matrix with the jth column replaced by Vi .
Z
The determinant is moved to the left hand side for simplicity: -
For I1 the Vi go in the first column  j  1 : -

V1 Z12 Z13
Z I1  V2 Z 22 Z 23  V1 Z 22Z 33  Z 23Z 32   Z12 Z 23V3  V2 Z 33   Z13 V2 Z 32  Z 22V3 
V3 Z 32 Z 33
 Z 22Z 33  Z 23Z 32 V1  Z13Z 32  Z12Z 33 V2  Z12Z 23  Z13Z 22 V3  Y11V1  Y12V2  Y13V3
Second column  j  2 : -
Z11 V1 Z13
Z I 2  Z 21 V2 Z 23  Z11V2 Z 33  Z 23V3   V1 Z 23Z 31  Z 21Z 33   Z13 Z 21V3  V2 Z 31 
Z 31 V3 Z 33
Third column  j  3 : -
Z11 Z12 V1
Z I 3  Z 21 Z 22 V2  Z11Z 22V3  V2 Z 32   Z12 V2 Z 31  Z 21V3   V1 Z 21Z 32  Z 22Z 31 
Z 31 Z 32 V3
 R1  R2  R3  X 1 R2  R3 R3 
 
The matrix for Z is restated for convenience: Z R2  R3 R2  R3  X 2 R3 
 R3  X 3 
 R3 R3
From which the first row of Y can be calculated: -
Y11  Z 22Z 33  Z 23Z 32   R2  R3  X 2 R3  X 3   R32  R2 R3  R2  R3 X 3  R3 X 2  X 2 X 3
Y12  Z13Z 32  Z12Z 33   R32  R2  R3 R3  X 3    R2 R3  R2  R3 X 3
Y13  Z12Z 23  Z13Z 22   R2  R3 R3  R3 R2  R3  X 2    R3 X 2
Second row: -
Y21  Z 23Z13  Z 21Z 33   R32  R2  R3 R3  X 3    R2 R3  R2  R3 X 3
Y22  Z11Z 33  Z13Z 31   R1  R2  R3  X 1 R3  X 3   R32  R1  R2 R3  R3 X 1  R1  R2  R3 X 3  X 1 X 3
Y23  Z13Z 21  Z11Z 23   R3 R2  R3   R1  R2  R3  X 1 R3   R1R3  R3 X 1
Third row: -
Y31  Z 21Z 32  Z 22Z 31   R2  R3 R3  R2  R3  X 2 R3   R3 X 2
Y32  Z12Z 31  Z11Z 32   R2  R3 R3  R1  R2  R3  X 1 R3   R1 R3  R3 X 1
Y33  Z11Z 22  Z12Z 21   R1  R2  R3  X 1 R2  R3  X 2   R2  R3 R2  R3 
 R1 R2  R3   R2  R3 X 1  R1  R2  R3 X 2  X 1 X 2
15
Appendix 2: Calculating the determinant (Three-stage high-pass network)
Z11 Z12 Z13

Z  Z 21 Z 22 Z 23  Z11Z 22Z 33  Z 21Z 32   Z12 Z 23Z 31  Z 21Z 33   Z13 Z 21Z 32  Z 22Z 31 
Z 31 Z 32 Z 33
Take each element in turn: -
Z11Z 22Z 33  Z 21Z 32 

 
 R1  R2  R3  X 1  R2  R3  X 2 R3  X 3   R32  R1  R2  R3  X 1 R2 R3  R2  R3 X 3  R3 X 2  X 2 X 3 
 R1  R2  R3 R2 R3  R2 R3 X 1  R1  R2  R3 R2  R3 X 3  R1  R2  R3 R3 X 2  R1  R2  R3 X 2 X 3  R2  R3 X 1 X 3  R3 X 1 X 2  X 1 X 2 X 3
Z12 Z 23Z 31  Z 21Z 33 

 
 R2  R3  R32  R2  R3 R3  X 3   R2  R3  R2 R3  R2  R3 X 3 
 R2  R3 R2 R3  R2  R3  X 3
2
Z13 Z 21Z 32  Z 22Z 31 

 R3 R2  R3 R3  R2  R3  X 2 R3 
  R32 X 2
Add together, cancelling terms (looking for matches of each type: R 3 , R 2 X , RX 2 and X 3 ): -
16
Part 2: Monograph 2
Appendix 3: Calculating transfer functions
 R1  R2  R3 R2  R3 R3 
 
The following is repeated for convenience: X   R2  R3 R2  R3 R3  with Ω  XY
 R3 
 R3 R3
The matrix elements of Ω and Y required for transfer functions are: -
Ω11  R11Y11  R12Y21  R13Y31 Ω12  R11Y12  R12Y22  R13Y32 Ω13  R11Y13  R12Y23  R13Y33
From appendix 1: -
Y11  R2 R3  R2  R3 X 3  R3 X 2  X 2 X 3 Y12   R2 R3  R2  R3 X 3 Y13   R3 X 2
Y21   R2 R3  R2  R3 X 3 Y22  R1  R2 R3  R3 X 1  R1  R2  R3 X 3 Y23   R1R3  R3 X 1
Y31   R3 X 2 Y32   R1R3  R3 X 1 Y33  R1 R2  R3   R2  R3 X 1  R1  R2  R3 X 2  X 1 X 2
With results: -
11  R1  R2  R3 R2 R3  R2  R3 X 3  R3 X 2  X 2 X 3   R2  R3  R2 R3  R2  R3 X 3   R32 X 2
 R1  R2  R3 R2 R3  R1  R2  R3 R2  R3 X 3  R1  R2  R3 R3 X 2  R1  R2  R3 X 2 X 3  R2  R3 R2 R3  R2  R3  X 3  R32 X 2
2
 R1R2 R3  R1 R2  R3 X 3  R1  R2 R3 X 2  R1  R2  R3 X 2 X 3
12  R1  R2  R3  R2 R3  R2  R3 X 3   R2  R3 R1  R2 R3  R3 X 1  R1  R2  R3 X 3  X 1 X 3   R3  R1R3  R3 X 1 

 R1  R2  R3 R2 R3  R1  R2  R3 R2  R3 X 3  R2  R3 R1  R2 R3  R2  R3 R3 X 1  R2  R3 R1  R2  R3 X 3  R1R32  R32 X 1
 R2 R3 X 1  R2  R3 X 1 X 3
13  R1  R2  R3  R3 X 2   R2  R3  R1R3  R3 X 1   R3 R1 R2  R3   R2  R3 X 1  R1  R2  R3 X 2  X 1 X 2 
 R3 X1 X 2
Lovely!
17

Procedure: -
1. Calculate the required time constant τ = RC and write it in the form   10 N where α is between 1.0 and 9.9.
2. Record the required value for N.
3. Calculate X0 = log10 α (X0 should be between 0.0 and 1.0).
4. Place the Y1 marker at X0 on the X scale and look for the two values of R and C that most closely match.
1
Note: Apart from factors of 10 X 0  log 10 RC  log 10 R  log 10 C  log 10 R  log 10
C
1
The slide rule performs the addition X 0  log 10  log 10 R
C
5. Try the Y2 marker at X0 to see if there is a better match (equivalent to ten times smaller value)
6. Choose suitable values of A and B (R×10A and C×10B) so that RC × 10A+B = τ
Note: Depending on the application A is usually between 2 and 6 (i.e. R is between 100Ω and 1MΩ.) and B can range from
minus 12 (pico farads) to minus 2 (large electrolytics).
Example: τ = 2.04μs = 2.04 ×10-6s and so X0 = 0.31

The best fit is R = 3.0 and C = 6.8 so practical values are R = 3×103 and C = 6.8×10-10 i.e. 3kΩ and 680pF.
Note: The same method may be used for calculating inductor/capacitor combinations where LC  1 2f R  and fR is the
2
resonant frequency.
E24 Resistor values

1.0 1.1 1.2 1.3 1.5 1.6 1.8 2.0 2.2 2.4 2.7 3.0 3.3 3.6 3.9 4.3 4.7 5.1 5.6 6.2 6.8 7.5 8.2 9.1 10
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
X Scale
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Cut along here
1.0 8.2 6.8 5.6 4.7 3.9 3.3 2.7 2.2 1.8 1.5 1.2 1.0
Y1 Marker Y2 Marker
18
Part 2: Monograph 3
An ultra-high input impedance high-pass filter

1. Introduction
It is shown elsewhere [1] that a three-stage high pass filter (type 2) has a high input impedance by virtue of the
“bootstrap” effect – a form of positive feedback. This property is not normally required but it does raise the
possibility of novel applications which may be of interest to the reader.
Voltage follower
C1
VIN
VOUT
R1
C2
R2
C3
R3
0V
Fig. 1.1 A three-stage high-pass filter
Analysis shows that the input impedance is boosted by a factor proportional to the frequency cubed. In normalised
form s  j  N  , at a frequency well above the natural frequency, the input admittance is [1]: -
1 1 1
  N  AIN  
3 
  with X1  1 sC1
s  X 1 R1 
This can be expressed as a parallel combination of a large negative resistor and small capacitor. In more convenient
form, with frequency in Hz: -
2 3
1 1 1  f  1  f 
AIN    With Z C    and Z R   j   R1
Z IN Z C Z R  f N  2f N C1  fN 
1
and fN 
2 R1C1R2C2 R3C3 3
1
With readily available components it is possible, in theory, to achieve an input impedance which is much higher
than conventional JFET or MOSFET devices. The input impedance of the follower then sets the upper limit. If, for
example [1] C1  33 pF , R1  5G and f N  1Hz .
At 75Hz: ZC  27  1012  and Z R  2 j  1015 
1. Part 2, monograph 2: “Three-stage filters”. See section 3.

1
2. Outline design proposal
One possibility is to employ an “inside-out” voltage follower [1], based on a two or three-stage high gain block
(HGB) [2], with a very low leakage input stage (MOSFET). Inside-out operation not only ensures very high
accuracy (no common mode at the inputs) but also bootstraps input capacitance and resistance - the floating power
supply and, therefore, the input stage of the HGB is driven to follow the AC input voltage.
Feedback
0V
VIN
VOUT
HGB
Floating PSU
Fig. 2.1 The inside-out voltage follower
The output of the follower is fed back, via suitable filters, to bootstrap a large resistor and stray/screen capacitance.
The upper limit of source resistance is determined by the need for stability: -
C1 Inside-out
CS2 Screen voltage follower
VOUT
CS1
RS
R1
VIN
F(s) G(s)
0V
Fig. 2.2 Outline schematic
The voltage follower is drawn in the conventional way to aid interpretation of the diagram. The screen (active
guard) must completely surround the high impedance nodes (usually both sides of C1, most of R1 and the first stage
of the voltage follower).
The high-pass filter, F(s), and low-pass filter, G(s), ensure stability. Each feedback route has a band-pass
characteristic so that the feedback factor is lower than 100% when the phase shift is zero.
The input capacitor could be a small parallel plate capacitor (air dielectric and typically ≈ 10pF) [3], constructed
with high resistivity insulators (PTFE or, better still, sapphire) [4].
1. Part 4, monograph 2: “High accuracy voltage followers”.

3. Part 1, monograph 5: “Variable gap capacitive displacement transducers”.
4. Yeager, John. & Hrusch-Tupta, Mary Anne et al: “Low Level Measurement”, 5th edition, available (free)
from Keithley Instruments Inc. For more practical tips on very high resistance and very low current
measurements see sections 2 and 4.
2
Part 2: Monograph 3
The very high input impedance  1T and low leakage  10 fA input stage permits the use of a higher value
resistor R1  100G reducing the natural frequency (typically ≈ 0.16Hz or N  1 ).
The large resistor provides a route for the DC leakage current but, at the operating frequency (typically 25Hz or
75Hz), the potential difference across it is very small and the current through it is substantially reduced. The stray
capacitance, from the high impedance node to the surrounding screen, is similarly “bootstrapped”.
For example: at the operating frequency the follower and filters can be accurate to better than 1ppm (e.g. with a
three-stage HGB and high accuracy filters). The potential difference across the resistance and stray/screen
capacitance is < 10-6 of the input voltage and their impedances are boosted by a factor of > 106. The impedance of
6pF stray capacitance, for example, has an impedance of 1GΩ at 25Hz. This would be boosted to over 1PΩ
(1015Ω)!
The filters, F(s) and G(s), are probably best made adjustable so that loop stability can be optimised for the
particular application (depending on the source resistance). Both can be two-stage filters for low phase error at the
operating frequency [1] or three-stage for low phase and low magnitude error [2].
The main problem is likely to be the gate-drain and gate-source capacitance of the HGB input stage. The positive
feedback through that route probably sets the upper limit on the impedance of source resistance, RS, and input
capacitor, C1. The equivalent feedback network is quite complicated: -
LPF
HPF
CS2 CS1
R1
C1
VOUT
×1
RF
RS
CF
0V
Fig. 2.3 The feedback model at the operating frequency
The solution could be a separate power supply for the first stage, bootstrapped via a suitable filter. The output of
the first stage and the input of the second stage of the HGB would need to be differential: -
Cascode 0V
VOUT
HGB
LPF
Fig. 2.4 A double bootstrapped inside-out follower
1. Part 2, monograph 1: “Two-stage filters”

2. Part 2, monograph 2: “Three-stage filters”
3
3. A low cost version
The high value resistor is a costly item. Also, MOSFETs tend to be noisy, compared to their JFET cousins. A
possible alternative is an ultra-low leakage pre-amplifier based on a pair of low cost JFETs operated in voltage
controlled resistor (VCR) mode [1]. The following ideas, dear reader, are untested – caveat emptor: -
100nF +15V
RC R1 RC
VOUT
VC K
Diff amp
R2 100k
100k
VIN ≈ 0V
0V
100Ω 10μF
Total input VS VC
capacitance, C
R4
R3
100nF -15V
Fig.3.1 An ultra-low leakage pre-amplifier
The basic idea is that the gate-drain and gate-source potential differences are small and (approximately) equal and
opposite, relative to the gate (at 0V). Small adjustments to the drain and source DC levels are made via the control
signal, VC. A slowly acting feedback loop operates to maintain the input gate at 0V. This is probably best
implemented with a microcontroller and adaptive algorithm [1 see section 4]. The average gate-drain and gate-
source leakage currents are not only equal and opposite but also inherently very small (typically I L  50 fA at
20ºC). The noise current is, therefore, also very small [2]: -
I N  2eI L B and I L  50 fA  I N  0.13 fA Hz
With discrete JFETs it would also be possible to incorporate the input JFET in the capacitor: -
Screen
VIN C1
Pre-amp
VG ≈ VIN
Fig. 3.2 A JFET in the capacitor
1. Part 5, monograph 3: “Low noise JFET pre-amps”.

2. Some proprietary low leakage devices employ extra circuitry to match the leakage current, including its
temperature dependent characteristic. The net average leakage current is then very small but the noise
current remains high.
4
Part 2: Monograph 3
The leakage control loop results in a second order high-pass characteristic, which is not ideal for operation within
an overall feedback loop, such as the inside-out voltage follower. It should be possible, however, to disable the
control loop for a few seconds while a measurement is made. The DC level at the pre-amp output will change
slowly but not sufficiently to affect the signal at the operating frequency.
During auto-zero mode the power supply centres are connected to local 0V. With a notch filter in the leakage
control loop it may not be necessary to disconnect the input signal.
The high-pass filter is no longer required but the second floating power supply and a band-pass filter for the
transistor leakage resistance and stray capacitance is probably necessary: -
C1
VOUT
Pre-amp
RS
VIN LPF
0V
Fig. 3.3 The filter in measurement mode
The circuit may be used as a low frequency AC high pass filter with sub-ppm accuracy even if the source resistance
is quite high source resistance (typically up to 100MΩ). It could also be used as the low noise front end of a null
detector in a bridge for comparing very high value resistors.
Another possible application is multi-phase electromagnetic flow tomography – measuring small AC signals
through a dielectric medium with an array of capacitive sensors.
If you are interested in building and testing a prototype please contact the author.
5
Part 3: Monograph 1
Inductive voltage dividers and ratio transformers – the basics
1. Introduction
Inductive voltage dividers (IVDs) and Ratio transformers (RTs) are very accurate electronic multipliers. With a
voltage transformer, for example, the output voltage is the input voltage, usually a sine wave, multiplied by a
number, set by the turns ratio: –
VOUT  VIN  n Where n is a number.
A number of stages can be combined to provide 6 or more decades so that the ratio may be set, for example, from n
= 0.0000000 to n = 0.9999999. Clearly, the accuracy of the first decade is most critical.
When used in a null balance “bridge” configuration with a very sensitive (low noise) null detector, the ratio of two
AC voltages or currents can be measured with an accuracy better than one part per million (1ppm or 0.0001%).
With care an accuracy approaching one part per billion (1ppb) is possible. The main disadvantages, compared to
resistive dividers are size and cost.
VIN
VIN VIN VOUT VOUT

VOUT VOUT
0V
Ratio transformers Inductive voltage dividers
Fig. 1.1 Frequently used circuit symbols (the dot indicates polarity)
High accuracy is made possible by the ready availability of soft magnetic materials (principally metallic glasses
with trade names such as “permalloy”, “mumetal” and “super-mumetal”) with extraordinarily high and sustainable
relative permeability (50,000 to 500,000). High permeability means that magnetic flux “flows” easily through the
material, compared to air, plastic or other non-magnetic materials. A number of companies supply toroidal cores
based on these alloys, in a variety of sizes and grades, which can be used to construct IVDs and RTs. The material
is manufactured in thin sheets and then wound, like a tight clock spring, into the shape of a toroid, with rectangular
cross-section, and encased in plastic.
Fig. 1.2 Toroidal cores are available in a variety of sizes
1
1.1 Applications
The main applications are in the areas of electrical primary and transfer standards, for measuring the ratio of
resistors and capacitors, platinum resistance thermometry and a wide variety of research activities, where pushing
the boundaries of accuracy or resolution is a key objective.
Fig. 1.1.1 The F900 resistance thermometry bridge (picture courtesy ASL Ltd)
Most commercially available IVDs are manually operated and are used mainly to construct ad-hoc bridge
configurations for research applications. At least two IVD sets are usually required, taking up a lot of bench space.
Whereas the first automatically balancing bridge was based on a pair of IVDs (ASL’s model A7 double Kelvin
thermometry bridge [1]) this has been superseded by RT based designs such as ASL’s F900.
Fig. 1.1.2 A 7-decade IVD (picture courtesy Tinsley)
A potential area of application is in ultra-precision engineering and nano-technology. Variable capacitance

displacement transducers, for example, have remarkable accuracy and resolution, which can be realised only with a
ratio transformer based capacitance bridge.
1. Hill J. J. and Miller A.P.: “An AC double Bridge with inductively coupled ratio arms for
precision platinum resistance thermometry.” Proc. I.E.E. 1963 110 No. 2 pp 453 - 458
2
Part 3: Monograph 1
1.2 Leakage flux
The high permeability and toroidal form ensure that a very high proportion of the magnetic flux is retained within
the body of the toroid. Some of the flux “leaks out” of the toroid, however, depending on the distribution of
currents flowing around the core. Some flux also leaks out at the ends of the high permeability metal strip (at one
point each on the OD and ID). The effect of the leakage flux on accuracy can be minimised by using a “rope” and a
symmetrical, evenly distributed, winding scheme. In practice an accuracy of 1ppm is easily achieved. Magnetic
screening is possible but there are more practicable ways of reducing errors to the ppb range.
1.3 Winding schemes
1.3.1 The “no-net-loop” (NNL) method
The method most widely used, for all types of winding, results in no net loop around the core. The winding is
started at point A and progresses around the core to complete the circle. The direction is then reversed - back to A
(see fig. 1.3.1). The art of IVD and RT design and construction is to choose the best combination of core size and
wire thickness that produces a uniform distribution. A good choice, for example, just fills the outer circumference
with a single layer and the inner circumference with a double layer with the required number of turns.
The NNL method ensures that any current carrying winding does not produce an external magnetic field (passing
through the centre of the toroid). This is a common problem with machine wound toroidal power transformers.
Similarly, any flux passing through the centre of the toroid does not result in an induced voltage in the winding.
Also, one or more net loops adds undesirable series inductance.
Rope
Toroidal
core
Rope wound A
CW to A then return Start/finish
Fig. 1.3.1 The “no-net loop” winding technique
The other key advantage of the NNL method is that the effects of interwinding capacitance can be minimised. An
energising winding, for example, can be driven by a balanced voltage source. Each part of the winding is in close
proximity to another part which is at equal but opposite voltage. Capacitive currents to a neighbouring winding
substantially cancel.
3
1.3.2 The “balanced no-net-loop” (BNNL) method
A practicable method for winding a large number of turns is to first wind the rope or wire on a shuttle: a wooden
batten with slots at each end. The batten and rope needs to be sufficiently thin to pass through the centre of the
core. This is not always possible for the whole winding and so a balanced no-net-loop (BNNL) method is
employed. Two shuttles are then required with half the rope on each.
Shuttle 1: half is wound in a clockwise direction - from A to B and back again. The other half of the rope (shuttle 2)
is then wound in a counter-clockwise (CCW) direction from A to B and back again (see fig. 1.3.2).
B Rope
Toroidal
core
Half of rope wound A Half of rope wound

clockwise to B then return Start/finish CCW to B then return
Fig. 1.3.2 The balanced zero loop winding technique
1.3.3 The NNL and BNNL methods applied to low number of turns of energising windings.
The same principles can be applied to energising windings with a low number of net turns. A number of windings
are applied, each covering a proportion of the circumference so that the whole core is covered uniformly. The
windings are then connected in parallel.
A practicable example is six windings of 40 turns each, each occupying one sixth of the core circumference with
fairly thin wire. The result approximates to a uniform sheet of energising current around the toroid and very low
leakage flux. A typical application would be a step-up transformer for a capacitance bridge. The high operating
frequency means that interwinding capacitance can be an issue and so the NNL method is employed.
4
Part 3: Monograph 1
2. The basic inductive voltage divider
The most basic design is an IVD with a single rope winding on a single toroidal core. A typical example has a 10
strand rope of 40 turns (a total of 400 turns) wound as in fig. 2.1.
The basic principle is that the self inductance and resistance of each strand of the rope is very nearly equal. The
former is achieved by selecting a suitably high permeability core and the latter by using wire with a uniformly
constant diameter, usually taken from the same reel. At a sufficiently high frequency the input impedance is high,
the current low and the resistive voltage drop small, compared to the induced voltage. The resistive voltage drop
errors are in quadrature (at 90 degrees relative phase) and would be largely rejected by a suitable phase sensitive
null detector and/or separate quadrature balance.
High permeability toroidal core

I
VS
0.9VS
etc.
0.2VS
R
0.1VS
R
0V
I
Fig. 2.1 The basic single-stage IVD
The result is a very simple device, easily manufactured, with a ratio accuracy of better than 1ppm over a frequency
range of 50Hz to 10 kHz. At low frequency the main problem is low input impedance and at higher frequency the
main problem is the interwinding capacitance.
The characteristics of IVDs have been thoroughly investigated with very good correlation between actual
performance and theoretical modelling. See, for example [1 and 2].
1. Hill, J. J. and Deacon, T.A. “Theory, design and measurement of inductive voltage dividers”. Proceedings
of the IEE, vol. 115, pp. 727-735 (May 1968).
2. Hill, J. J. and Deacon, T.A. “Voltage ratio measurements with a precision of parts in 109 and performance
of inductive voltage dividers”. IEEE Trans. Instrum. Meas., vol. IM-17, pp269-278, Dec 1968.
5
2.1 Multi-decade IVDs
Commercially manufactured IVDs are available with five or more decades of switching so that ratio settings
ranging from, for example, 0.000000 to 0.999999 are possible.
The basic idea is that the second decade IVD is energised by tapping one tenth of the voltage from the first decade
and so on for subsequent decades [1]. This is achieved with a two-pole ten-way switching mechanism, using good
quality, low contact resistance, manual rotary switches or electro-mechanical relays. The loading effect of the
second and subsequent decades depends on the source impedance and only those bridge configurations which
present low source impedance to the IVD input are practicable. This is one of the main limitations of the IVD. In
one of the main applications (measurement of resistance ratio) the result is a large and expensive bridge [2] with
two complete sets of IVDs. The relatively low input impedance of each IVD stage also requires quite low switch or
relay contact resistance - big, chunky switch contacts or mercury whetted reed relays and thick wire
interconnections are necessary.
VS
6
I ETC
4 .
0V
3
0.1VS 0.14VS 0.146VS VOUT = 0.1463VS
Fig.2.1.1 Four decades of a multi-decade IVD
Despite the practical problems the basic IVD can achieve ppb accuracy and commercial multi-decade IVD are still
used for ad-hoc bridge configurations to this day.
1. Often referred to in the literature as the “Kelvin–Varley method” by analogy with the original kelvin-
Varley resistive divider (ref. required: see Wikipedia).
2. The market leader for many years was the model A7 from Automatic Systems Laboratories Ltd, based
on the original design by Hill and Miller.
6
Part 3: Monograph 1
Fig. 2.1.2 The A7 employing two seven decade dividers (Picture courtesy ASL Ltd).
(N.B. weight about 70kg!)
7
2.2 Two-stage IVDs
The main disadvantage with the basic single stage IVD is the low input impedance at low frequency. The ratio
winding also carries the current to provide the flux in the core – acting as both energising and ratio winding. To
achieve high accuracy it is often necessary to use a large, expensive, high grade core (very high permeability e.g.
super-mumetal SM200), at least in the first decade, to achieve sufficiently high inductance. There is, however, a
much simpler solution - a two-stage design, where two toroidal cores and a separate energising winding are used.
The result is a much reduced current flowing in the ratio winding and connecting leads.
Historical note: This technique was first used by Brook and Holtz [1], early in the 20th century, to improve the
accuracy of current measuring transformers.
The two-stage IVD is best depicted, diagrammatically, by using the following convention: -
1. Cores and windings are depicted as vertical rectangles. It is fairly clear, even in monochrome, which is which –
the windings have connections. I shall adopt the convention of orange shading for windings and grey for cores.
2. A winding that is horizontally adjacent to one core is wound only around that core.
3. A winding that is horizontally adjacent to two or more cores is wound around all cores.
It will be seen later that this convention can be extended to much more complicated arrangements of windings and
cores.
In fig 2.2.1, for example, the energising winding is wound around one core only – the “bottom” core. The second
core is then placed on top and the ratio winding is wound around both cores. Both windings comply with the
BNNL winding scheme with exactly the same number of turns. If, for example, the ratio winding has ten strands
and 40 turns, the energising winding must have exactly 400 turns.
Ratio winding
VS
Energising
winding
Fig. 2.2.1 The “two-stage” technique with separate energising winding
The reduction in current flowing in the ratio winding makes it possible to use much thinner wire for the rope –
making construction much simpler. Thinner wire can also be used for interconnections and the resistance of
connectors, switches and relays is far less of a problem. The benefits to the designer are many. As a rule of thumb
the current in the ratio winding can be reduced by at least a factor of a hundred and up to one thousand over the low
audio frequency range (20 – 100Hz).
1. Brooks, H. B., and Holtz F. C., “The two stage current transformer”. AIEE Trans. Vol. 41, 1922, p382
8
Part 3: Monograph 1
The principle of operation is very simple – the current flowing through the energising winding sets up very nearly
the flux corresponding to the applied voltage. The difference is due to the resistance of the energising winding. The
ratio winding shares this flux and so a voltage is induced which is very nearly equal to the applied voltage. The
difference gives rise to very small current flowing in the ratio winding, setting up the remainder of the flux in the
top core. The ratio winding is thus “bootstrapped”, presenting much higher input impedance to the voltage source.
See the monograph “Two-stage IVDs and RTs” by the same author for more detailed analysis and example
calculations [1].
2.3 The two-stage IVD with high accuracy voltage followers
In the basic two-stage design the energising winding still presents low impedance to the voltage source. Any
current flowing through the connecting wires may cause a significant voltage drop, complicating the design of
bridge configurations. The effect can be eliminated completely by employing low noise, high accuracy voltage
followers with very high input impedance. The very high loop gain also ensures that the voltage followers have
very low output impedance - at the point where the feedback voltage is sensed. For more detail see the monograph
“High Accuracy Voltage Followers” by the same author [2]. The main disadvantage is the extra noise due to the
followers, which is significantly greater than the Johnson noise generated in the winding resistance. It is, however,
of the same order as the noise generated elsewhere (e.g. 100Ω source resistance:  1 2 nV Hz ) and sub-ppm
accuracy and resolution is still practicable in a modest bandwidth  0.1  1Hz  .
VOUT
VIN
Fig. 2.3.1The two-stage technique with voltage followers
Note the order of the negative feedback connection – the larger current flowing through the energising winding
should not flow through any part of the connection to the ratio winding.
1. Part 3, monograph 3: “Two-stage inductive voltage dividers and ratio transformers”.

9
3. The basic ratio transformer
The most basic ratio transformer has a primary winding plus a fixed and a variable secondary winding. The fixed
and variable windings are part of the same rope and so high accuracy of ratio is achieved. The primary winding is
used only to energise the core and does not usually require a high degree of ratio accuracy relative to the ratio
windings. The primary is usually, therefore, a single strand, in a single layer, with the number of turns to provide
the required secondary voltage. A high step up ratio can be achieved by having multiple primary windings, each
with a low number of turns, connected in parallel (see section 1.3.3). The primary winding must, however, be
uniformly distributed around the core, each complying with the NNL or BNNL scheme, to provide, as near as
possible, a uniform sheet of current around the core and minimum capacitive coupling to the secondary. The ratio
windings are then wound over the top. Capacitance between primary and secondary windings can be further
reduced with a thick layer of insulating tape (e.g. PTFE plumber’s tape or polyester ribbon). With a single core it is
easily possible to provide 2 or even 3 decades of a multi-decade bridge.
Ratio winding
screen
V1 Virtual earth
VS
0V VCA
V2
CV JFET input
0V
Fig. 3.1 The most basic ratio transformer in a capacitance bridge
V1
n With n variable (e.g. 0.000000 to 0.999999)
V2
V1CR  V2CV CV V
At null balance: VCA  0   1 n
CF CR V2
The basic ratio transformer is useful for measuring the ratio of high impedances (e.g. high value resistors or low
value capacitors). Capacitive loading of the ratio windings (e.g. due to long cables) is not usually a problem but
resistive loading can be, reducing accuracy.
Fig. 3.2 A commercial capacitance bridge (picture courtesy Andeen Hagerling)
10
Part 3: Monograph 1
A multi-decade transformer can be implemented by using an extra strand of a rope to energise subsequent cores. A
six decade capacitance bridge operating at moderately high frequency (1.6kHz) would, for example, look
something like the following: -
9×4t
9×4t 9×4t
9×40t
V1
10×40t 10×40t
VS
20t
0V
10×40t
9×40t 9×40t
4t 4t 0V
V2
Fig. 3.3 A six decade bridge (0.000000 to 0.999999)
Surprisingly accurate results (sub-ppm) can be obtained with a simple bridge (e.g. measuring the ratio of three
terminal capacitors) as long as the currents flowing in the ratio windings are kept low. If long connecting leads are
required the capacitance of the cables becomes an issue. Here again, however, the effect is mainly quadrature and
can be reduced significantly with a separate quadrature balance. For the highest possible accuracy tri-axial leads
can be used, with the inner screen driven to be at the same voltage as the inner conductor.
A useful variation is when used with a transducer which is inherently differential. In this case the selected winding
is connected to ground: -
C1 CF
V1
0V
VP
C2 VOUT
V2
0V
Fig. 3.4 Differential capacitance bridge
 V1  V2 
Define a reference voltage VR   and the ratio, n, such that: -
 2 
V1  VR 1  n and V2  VR 1  n
11
N.B. When the transformer tap is at the centre (n = 0): V1  VR and V2  VR
As n increases the tap moves towards the V1 end and AC voltage V1 reduces while V2 becomes increasingly
negative.
V1C1  V2C2
At balance: VOUT  0
CF
C1  C2
 VR 1  nC1  VR 1  nC2  0  n 
C1  C2
An alternative method has practical benefits. The centre of the centre-tapped ratio transformer is driven with a
voltage, VC, which is derived from the reference voltage VC  nVR using an IVD or RT so that: -
V1  VR  VC  VR 1  n V2  VR  VC  VR 1  n
C1  C2
As above, at null balance: n
C1  C2
This method has found application with a dual differential rotary capacitive transducer based servo system with sub
arc second accuracy and excellent dynamic response. For more detail see the monograph “A 16 bit binary
differential capacitance bridge” by the same author.
C1 CF
V1
VC
VP
C2 VOUT
NP V2
NS
0V
Fig. 3.5 An alternative differential capacitance bridge
For more detail see the monograph “Single stage IVDs and RTs” by the same author [2].
1. Part 3, monograph 8: “A 16 bit binary differential capacitance bridge”.

2. Part 3, monograph 2: “Single stage inductive voltage dividers and ratio transformers”.
12
Part 3: Monograph 1
4. The three-stage ratio transformer (e.g. ASL model F17)
The principle of a separate energising core can be taken further with a second energising stage. The bottom core
provides most of the flux and the second energising core makes up for most of the rest. The result is a massive
increase in input impedance of the ratio winding and much higher accuracy when used as a transformer. The
current flowing through the ratio winding is now so low that much more resistance can be tolerated and thinner
wire may be used. This allows for either a longer, thinner rope (more turns) and/or a rope with many more strands.
Some of the strands are connected in series to provide a primary winding while the remainder provide a tapped
secondary and, usually, an extra strand for equalisation of lower decades.
The main advantage, compared to the most basic ratio transformer, is that the voltage ratio between primary and
secondary is now very accurate. If the required operating voltage is low then smaller cores can be used and the
design can be quite compact.
With the addition of voltage followers the result is an elegant design, which is easy to construct, with ratio accuracy
better than 1ppm, even at low frequency (75 or 90Hz). The isolation between primary and secondary windings also
provide for a simple, elegant bridge configuration, suitable for measurement of resistance ratio, with long
connecting cables (e.g. for calibrating resistance thermometers).
nVR
RS VR
D
I
RT VT
Null detector
Fig. 3.1 A three-stage ratio transformer bridge (outline schematic)
The principle of operation is very simple: A current is passed through the transfer standard resistor, RS, and the
thermometer resistor, RT. The current flowing through the resistors is the same and so the resistance ratio is the
same as the voltage ratio. When the transformer ratio is adjusted for null balance: -
RT VT
nVR  VT   n
RS VR
The main disadvantage is the noise introduced by the followers. This limits speed and/or resolution to about 1ppm
in 1 Hz of bandwidth – equivalent to approximately 0.25mK for platinum resistance thermometry. This is more
than adequate for many commercial calibration requirements. For more see the monographs “Three-stage RTs” [1]
and “An F17 type ratio transformer bridge” [2] by the same author.
1. Part 3, monograph 4: “Three-stage ratio transformers”.

2. Part 3, monograph 6: “An F17 type ratio transformer bridge”
13
5. An advanced three-stage ratio transformer (e.g. ASL model F18)
In resistance thermometry the self heating of the thermometer can be a major issue. This limits the current that can
be used and, therefore, the voltage signal generated. This is why resistance thermometry is much more demanding
on noise performance compared to the calibration of transfer standard resistors, where self heating is much less of a
problem.
Similarly, for resistance thermometers with much lower resistance values (e.g. 0.25Ω at 0oC used for high
temperature applications) the noise level becomes a major limitation. Fortunately it is possible to use followers to
drive the energising windings only and still achieve sufficiently high input impedance on the ratio winding primary
so that it can be connected directly to the transfer standard resistor.
To take advantage of the much lower noise contribution of the followers, one of the consequences is the need to
reduce the noise level of the null detector also. This is possible, for low values of source resistance, by transformer
matching to a low noise preamplifier. The ASL type F18, for example, has provision for matching to 1Ω, 10Ω or
100Ω source resistance.
The result is a versatile bridge with better than 0.1ppm accuracy and resolution limited by Johnson noise of the
reference resistor and/or detector.
Negative capacitors
nVR
RS VR IL
D
I
Stability
compensator
RT VT
Fig. 4.1 An advanced three-stage ratio transformer bridge configuration
Historical note: A number of other workers produced multi-stage designs using a series of reference resistors to
drive the energising windings. Robert Cutkosky of NBS, for example, produced a five-stage design, for low
frequency operation (15Hz), with 10Ω reference resistors, for use with the recently developed 0.25Ω SPRT [1]. It
was necessary to go to 5 stages due to the input capacitances interacting with the source resistance – not a problem
with the very low output impedance of the voltage follower. He was also “forced” to adopt a doubly shielded fifth
stage. JDY got round the problem in a simple and elegant way, obviating the need for shielding – negative
capacitors, which cancel the inter-winding capacitance. Passively driven multi-stage transformers are, therefore, of
historical interest only – there are no advantages and numerous disadvantages compared to actively driven
transformers. For more detail see the monographs “Three-stage RTs” and “An F18 type ratio transformer bridge”
and “A simulated negative capacitor circuit” by the same author.
1. Cutkosky, R, D: “An Automatic Resistance Thermometer Bridge”. IEEE Trans. on Instrumentation

and Measurement, Vol. IM-29, No. 4, Dec. 1980.
14
Part 3: Monograph 1
6. A three-stage current transformer (NPL’s “Knight” bridge)
A well constructed three-stage ratio transformer works equally well as a current transformer. In an interesting case
of symmetry, compared to a voltage transformer bridge, the current source and detector are interchanged. The same
“bootstrapping” principle applies though, in the case of a multi-stage current transformer, the flux flowing in core
T3 is now very small. The following example is a three-stage current bridge originally developed at NPL [1] and
made available by Tinsley Ltd. As mentioned above passive drive is of historical interest only, though with an
advertised accuracy specification of ±2ppm with a 25Ω or 100Ω thermometer it is worth a mention.
N.B. For an ideal current transformer the flux cutting the ratio windings is zero and the currents are in the ratio of
the number of turns - the total magneto-motive force (MMF) generated by the ampere-turns cancel.
I1+I2+I3=nIR
T1 T2 T3
RS1 I1
RS2 I2
D
IR
RS3 I3
RT
0V
Fig. 5.1 A three-stage current transformer bridge (simplified schematic)
The bridge consists of three reference resistors which are ideally of the same value (= RS). RS1 is the main standard
resistor and must be very stable (<1ppm). RS2 is less critical (typically <100ppm) and RS3 is the least critical (<1%).
The current passing through the variable ratio winding results in currents I1, I2 and I3 in the fixed ratio windings.
Current I1 flows though RS1, I2 through RS2 etc.
To a very good approximation: I1  I 2  I 3  nI R
At balance: I R RT  I 3 RS 3  I 2 RS 2  I1RS1  0
I R RT  I1  I 2  I 3 RS
RT
To a good approximation, therefore:  n
RS
The main disadvantage of this approach is the source resistance presented to the primary windings (compared to
using followers) making it necessary to operate at the relatively high frequency of 400Hz. Also, in the commercial
version, the reference resistors are internal to the instrument and can’t be easily changed (e.g. for other applications
and for checks on bridge accuracy with a resistance bridge calibrator).
1. Knight R. B. D. “A precision bridge for resistance thermometry using a single inductive current
divider”. IEE Conference No 152 (Euromeas 77).
15
7. Kusters’ comparator (e.g. Guildline model 6622T)
Originally designed for calibrating transfer standard resistors [1] at relatively high measuring current this technique
was then developed for resistance thermometry [2]. Whereas the title of the original paper characterises it as a
“direct current” (DC) instrument it would be more accurate to describe it as operating at a very low frequency - in
practice the DC current has to be reversed to eliminate the effect of DC offsets (e.g. thermal EMFs). For the model
6622T, for example, the reversal rate is selectable from 2 – 1,637 seconds (i.e. a square wave of frequency 0.25Hz
or less). It is stated in [2], with unintended irony: “The reversing cycle of the bridge should be as short as possible
in order to be able to cope with changing thermal EMFs.”
The original electronic circuits and semi-automatic balance mechanism were also inept – introducing unnecessary
extra noise. The null detector, for example, operates for only half of the available time, waiting for transients to
settle after the “DC” current is reversed.
The main advantage is that it provides a means of comparing DC and AC measurements for resistance standards
and sensors. This is less important recently as designers now understand the importance of materials and
construction to minimise AC effects (e.g. insulators that do not exhibit dielectric absorption). The technique is also
well suited to high accuracy measurements over a very wide range of resistance values (up to 100kΩ as standard
and higher with a suitable extender unit and reference resistors).
The main disadvantage is the inevitably high noise level (mainly due to detector “1/f noise” and fluctuating thermal
EMFs) compared to higher frequency operation (e.g. 10 – 400Hz).
IT
NV RT
D1 D2
RS
Flux Detector
NS
IS
Fig. 7.1 The Kusters current comparator bridge (simplified schematic)
The transformer is a single stage device with a very large number of turns. The sensitive flux detector, D1, is used
to establish zero flux in the magnetic core. The magneto-motive force (MMF) generated by the fixed and variable
windings are adjusted for a null balance: -
NV IT  N S I S  0
The current IS is also adjusted for null balance at the detector D2: IT RT  I S RS  0
RT I S NV
To a very good approximation, therefore:  
RS I T N S
1. MacMartin M. P. and Kusters N.L.: “Direct-Current Comparator Ratio Bridge for four-terminal
resistance measurements” IEEE Trans. On Instrum. And Meas., vol. IM-15, pp 212-220, Dec 1966
2. Kusters N.L. and MacMartin M. P.: “Direct-Current Comparator Bridge for Resistance thermometry”.
IEEE Trans. on Instrum. And Meas., vol. IM-19, No. 4, Nov 1970
16
Part 3: Monograph 1
8. The double balanced potentiometer (e.g. The ASL “Cryo-bridge” [1])
Certain types of sensor (e.g. Germanium, used for cryogenic temperature measurements) have not only high
resistance values but also high resistance in the connecting leads. Currents flowing in the voltage sensing leads
must be negligible requiring an input resistance of the order 1012Ω. High impedance circuits employing JFETs
introduce too much noise - the signal level is severely constrained by heat dissipation in the sensor. Johnson noise
of the sensor and connections is low because they are at very low temperature. One practicable solution is to use a
ratio transformer with two sets of variable windings and a double balance. JFET input detectors can be transformer
matched to provide optimum noise performance [2]. Despite a relatively low detector input impedance null balance
ensures that the current passing through the detectors is negligible.
N1
RS D1
N2
RT D2
Fig. 8.1 The double balanced potentiometer (simplified schematic)
RT I S N1
At balance:  
RS I T N 2
In practice the bridge measuring current was made sufficiently stable for a single variable winding and detector to
be switched between the two resistors. Cable and inter-winding capacitances are significant issues, however, and a
low operating frequency of 25Hz was therefore chosen. In the original “Cryo-bridge” [1] the transformer primary
and secondary windings also had to be wound separately, reducing ratio accuracy to about ±1ppm. Quadrature is
quite high (due to cable capacitance) and an accurate quadrature servo proved necessary. The main challenge is
producing two sine waves with precisely 90 degrees phase difference (typically to within ±1 mRad) [3].
1. Wolfendale, P. C. F. “A precise automatic AC potentiometer for low temperature resistance

thermometry”. Journal of Scientific Instruments (Journal of Physics E) 1969, Series 2, vol. 2.
2. Part 3, monograph 5: “Noise matching transformers”.
17
Part 3: Monograph 2
Single stage inductors and transformers

1. Introduction
Inductors based on high permeability materials (typically μR > 50,000) exhibit significant non-linearity and
hysteresis. At high levels of flux density (> 0.5 Tesla) the material saturates and the incremental permeability drops
sharply. An applied sinusoidal voltage, for example, results in a distorted current waveform (and vice versa - see
figs.1.1 and 1.2). Fortunately this does not prevent us from constructing and employing high value inductors (> 1H)
as we normally rely only on a minimum inductance. This is readily achieved by designing magnetic circuits with a
sufficient cross-sectional area so that the maximum flux density remains well below saturation level.
If one assumes a linear model with a minimum value for permeability one can at least predict minimum
inductances and, therefore, maximum errors, which is the most important thing. Fortunately, measurements confirm
the validity of this approach for flux density levels up to about 0.5 Tesla.
The other main consideration is winding resistance. This adds a real component to the mainly inductive (imaginary)
impedance and is a major factor in the design of inductors and transformers. Whereas the resistance increases in
direct proportion to the number of turns the inductance increases according to the number squared.
Fig. 1.1 Voltage and current traces for a high permeability core winding at high flux level
Fig. 1.2 B-H trace for a high permeability core
Rule of thumb for a good quality inductor and transformer design: high inductance to resistance ratio and
low flux level (see sections 2 and 3).
1
2. Calculating impedance from basic parameters
In the following analysis I shall assume that the core material is linear with a constant value of permeability. I also
assume that the effect of inter-winding capacitance is negligible and that the applied voltage is a sine wave.
Fig. 2.1 defines the main parameters of a basic inductor with winding resistance: -
R
Magnetic circuit
V
N Φ
Winding with N turns

Fig. 2.1 An inductor with series resistance
The magneto-motive force (MMF) generated by the current flowing through the winding is defined as:-
MMF  NI (units: “Ampere-turns”)
The resulting magnetic flux is determined by the reluctance RL of the magnetic circuit.
(c.f. Ohm’s law: V=IR): -
MMF  RL
Reluctance depends on the cross-sectional area, length and permeability of the magnetic circuit: -
LE
RL 
 0  R AE
N.B. The formula for reluctance can be compared with that for resistance of a conductor length LE, cross-sectional
area, AE, and conductivity, σ: -
LE
R
AE
Clearly permeability is analogous to conductivity.
In practice the parameter provided in most data sheets for soft magnetic components is the reciprocal of reluctance.
I call this the “permittance” [1]: -
1   A
AL   0 R E
RL LE
The flux is, therefore:   NIAL
1. According to Wikipedia this term was originally used by Oliver Heaviside for the imaginary part of
admittance, the reciprocal of impedance. That parameter is now widely referred to as the “susceptance”.
2
Part 3: Monograph 2
The changing flux induces a “back EMF”, according to Faraday’s Law: -
d dI
VB  N  N 2 AL
dt dt
dI
If one assumes the applied voltage is sinusoidal then using the complex representation:  jI  sI
dt
VB  N 2 AL sI  sLI
Where L is the “self inductance”: L  N 2 AL
The applied voltage is balanced by the back-EMF plus the resistive voltage drop: -
V  IR  VB  I R  sL
The total impedance is, therefore, the sum of winding resistance and inductive impedance: -
V
Z  R  sL
I
The reader will not be surprised that a key parameter is the relative value of the resistance and inductive
impedance. A useful measure of this is the characteristic frequency at which the magnitude of the inductive
impedance is the same as the resistance: -
R
RL  2f RL 
L
In virtually all cases a lower characteristic frequency is better – lots of turns of very thick copper wire. The art of
inductor/transformer design, in this context, is to find the best practical compromise – minimum size and number of
turns that is guaranteed to achieve the accuracy required.
3. High levels of flux density and core saturation
The effective cross-sectional area of the magnetic circuit, AE, and the number of turns, N, determine the maximum
voltage that can be applied at a given frequency. The operating frequency is usually quite low (typically 25Hz,
75Hz or 400Hz) and saturation can be a major consideration. If BMAX is the maximum flux density then the
maximum amount of flux is AEBMAX. The maximum (sine wave) voltage, at frequency, ω, is, therefore: -
d MAX
VMAX  N  NAE BMAX .
dt
In practical RT and IVD design the BMAX is often set quite low (though not in all cases), compared to power
transformer applications. As a rule of thumb a BMAX of 500mT is the most one can tolerate for mumetal and similar
alloys.
See appendix 1: data for a range of commercially available magnetic cores including the maximum voltage per turn
per hertz assuming a BMAX of 500mT.
The following applies to a simple resistance bridge (see section 4.6).
A size 3A core with 128 turns at 400Hz: VMAX  2fN  AE BMAX   23V
This is well above the operating voltage anticipated (≈ 100mV) and the core operates well below saturation.
3
4. Basic (single-stage) transformer theory
Consider a transformer with an ideal (linear) magnetic circuit but with winding resistances, driving load impedance
ZL. Fig. 4.1 defines the main parameters: -
IP RP RS IS
VIN NP NS ZL VOUT
Fig. 4.1 Model of a basic transformer with load impedance
According to Ohm’s, Kirchhoff’s and Faraday’s laws in the complex representation s  j  : -
ZL
VIN  I P RP  sNP  VOUT  sN S  and VOUT  I S Z L
RS  Z L
The flux generated by the net magneto-motive force is proportional to permittance of the magnetic circuit: -
  N P I P  N S I S AL
4.1 Current transformers
From the above one can deduce: -
VOUT  sN S N P I P  N S I S AL
ZL
 IS ZL
RS  Z L
With a little algebra the current ratio is: -
IS sNS N P AL

I P RS  Z L  sNS2 AL
IS NP
If RS = ZL = 0 the result is an ideal current transformer: 
IP NS
I S N P  s  N S2 AL LS
Otherwise:    with  
I P N S  1  s  RS  Z L RS  Z L
Where: LS is the inductance of the secondary winding. This is the value of inductance that would be measured with
the primary winding open circuit.
4
Part 3: Monograph 2
There is a practical limit to how low one can make the winding resistance but it is possible to make the load
LS
impedance very small (e.g. with active circuitry), in which case   and is real. I call this the time constant of
RS
the secondary winding. The result is the transfer function with a first order high-pass characteristic: -
I S N P  s  LS
   with 
I P N S  1  s  RS
IS NP  1 1 
At high frequency, to a very good approximation: s  1   1   2 2 
I P N S  s  s 
More conveniently with frequency in Hz: -
I S N P  f N  f N  
2
RS
f  f N   1 j   fN 
f  f  
with
I P NS  2LS
 
The first error term is quadrature and inversely proportional to frequency. The in-phase error is inversely
proportional to frequency squared and is, in practice, too large for low frequency high accuracy applications
(typically 25Hz or 75Hz).
4.2 Voltage transformers
From above the voltage ratio is: -

VOUT sN S  ZL
 
VIN I P RP  sN P  RS  Z L
With no load current and zero primary winding resistance the result is an ideal voltage transformer: -
VOUT N S
ZL   and RP  0  
VIN NP
Neither is possible in practice and so one needs an approximation. One can eliminate the flux and current by
noting, from above: -
I S N P  s   s 
    N P I P  N S I S AL   N P I P  N P I P
N I A
   AL  P P L
I P N S  1  s   1  s  1  s
LS
with 
RS  Z L
VOUT N S sLP ZL
   
VIN N P RP 1  s   sLP RS  Z L
Where LP is the inductance of the primary winding: LP  N P2 AL
N.B. This is the inductance that would be measured with the secondary open circuit.
5
Consider a simple step-down transformer, ratio 100:1 consisting of 200 turns on the primary and 2 turns on the
secondary on a 5c SM100 toroidal core. The load is the primary of a similar transformer as often happens with a
multi-decade transformer: -
Size 5c core: case OD 41mm and case ID 23mm. axial length 15mm.
Inner circumference:    23  72mm with room for 200 turns in two layers of 0.7mm OD wire.
Outer circumference:    41  128mm with room for 200 turns in one layer of 0.64mm OD wire.
The outer circumference is the more critical so choose 24SWG enamelled copper wire with 0.56mm OD and
71mΩm-1 resistance.
Length of wire per turn is approximately: 2 15  41  23  48mm

For 200 turns: 200  48mm  9.6m of wire.
Primary resistance: 9.6m  71mm1  0.7
Primary inductance = 200  200  102 H turn2  4H
Primary impedance at 75Hz = 2  75  4  1.88k
The secondary resistance is mainly due to the connecting leads. If one assumes a 50cm long twisted pair then the
resistance is 1.096m  71mm1  78m
The secondary inductance is: 2  2  102 H turn2  400H
From above, repeated for convenience: -
VOUT N S sLP ZL LS
   with 
VIN N P RP 1  s   sLP RS  Z L RS  Z L
sLS sL sL
Z L  RS  s   S  S  10 4 i.e. the ratio of turns squared and negligible.
RS  Z L Z L sLP
The loading effect on the secondary is very small and substantially quadrature: -
2
R R  78m  78m 
2
ZL
 1  S   S   1  j  5
  1  j 4.1  10  1.7  10
9
RS  Z L ZL  ZL  1.88k  1.88k 
The errors are 41ppm of quadrature and a negligible in-phase component. It is reasonable to assume, therefore, at
low frequency: -
VOUT N S sLP
s  1    104 and Z L  RS   
VIN N P RP  sLP
This is a simple high pass filter characteristic due to the primary resistance and inductance and the main limitation
on accuracy in most cases. From above, in more convenient form (frequency in Hz) over a useful range of
frequency: -
VOUT N S  f N  f N  
2
104
f N  f  1.6kHz   1 j   fN 
RP
 0.028Hz
f  f  
with
2 VIN NP  2LP
 
At 75Hz: 
VOUT N S
VIN

NP

1  j3.7  10 4  1.4  10 7 
The main error is 370ppm of quadrature.
6
Part 3: Monograph 2
4.3 Input impedance
From above: -
N P I P AL VIN sN 2 A sLP
VIN  I P RP  sNP  and    ZP   RP  P L  RP 
1  s IP 1  s 1  s
LS
with 
RS  Z L
If the load impedance is infinite (open circuit secondary) the input impedance is, as expected, the primary
resistance in series with its inductance: -
Z L      0  Z P  RP  sLP
Otherwise, the load impedance is reflected back to the primary, acting in parallel with the primary inductance. As
above the input impedance is: -
sLP
Z P  RP 
1  s
IP RP
VIN ZR Open circuit
Fig. 4.3.1Equivalent circuit – load impedance reflected back to the primary
Expressed as admittance (the reciprocal of impedance) the primary winding inductance in parallel with the
reflected load impedance is: -
1 1  s 1 1 LS
  
Z P  RP sLP sLP LP RS  Z L 
The first component is the admittance of the primary winding, the second is, therefore the reflected admittance. The
reflected impedance is, therefore: -
ZR 
LP
RS  Z L 
LS
The ratio of inductance is the turns ratio squared: -
2
N 
 Z R   P  RS  Z L 
 NS 
Very often the load impedance is much greater than the secondary winding resistance and, therefore: -
2
N 
Z L  RS  Z R   P  Z L
 NS 
The square law is an important characteristic of ratio transformers and inductive voltage dividers.
7
One can model the effect, solely due to loading, as follows: -
ZOUT
VU VL ZL
Fig. 4.4.1 Circuit model for output impedance
From above, the loaded and unloaded output voltages are, respectively: -
NS sLP ZL NS sLP
VL  VIN  VU  VIN
N P RP 1  s   sLP RS  Z L
and
N P RP  sLP
LS
With:  
RS  Z L
The effect of loading due to the secondary output impedance is: -
VL ZL V 
  Z OUT  Z L  U  1
VU Z OUT  Z L  VL 
 R 1  s   sLP RS  Z L 
 Z OUT  Z L  P   1
 RP  sLP ZL 
RP RS  Z L   sRP RS  Z L   sLP RS  Z L   Z L RP  sLP 

 ZOUT 
RP  sLP
LS
Two terms cancel. Eliminate   for the simple result: -
RS  Z L
RP RS  sLS RP  sLP RS sRP LS

Z OUT   RS 
RP  sLP RP  sLP
As one might expect the output impedance is the secondary winding resistance in series with an extra term reflected
from the primary. It is the primary winding resistance in parallel with the winding inductance, multiplied by the
ratio of inductances. The latter is, again, the turns ratio squared: -
2
sRP LS L sLP RP  N  sLP RP
ZR   S   S 
RP  sLP LP RP  sLP  N P  RP  sLP
This is also an important characteristic of ratio transformers and inductive voltage dividers.
8
Part 3: Monograph 2
This can be represented as follows: -
RP
RS
ZR
VU LP VL ZL
Fig. 4.4.2 Equivalent circuit showing the reflected impedance, ZR
At a sufficiently high frequency (greater than the characteristic frequency of the winding) the inductive impedance
of the primary is much greater than the winding resistance and the expression simplifies further: -
2
N 
sLP  RP  Z OUT  RS   S  RP
 NP 
4.5 Capacitive load
In some cases (e.g. a capacitance bridge) the load impedance is capacitive, (e.g. due to interconnecting cables) with
a magnitude much greater than the winding resistance:-
1 sLS CL
ZL  and sRS CL  1     sLS CL
sCL 1  sRS CL
Also, if the operating frequency is much lower than the characteristic frequency of the secondary inductance/load
capacitance, then the value of  is also very small and, to a very good approximation: -
VOUT N S sLP 1
sLS CL  1    
VIN N P RP  sLP 1  sRS CL
The resulting transfer function can be summarised as a first order high-pass and low-pass characteristic: -
VOUT N S s 1 LP
   with  and   RS CL
VIN N P 1  s 1  s RP
It is often the case that one effect dominates and it is best to keep the effects separate. To a very good
approximation: -
VOUT N S  1 
s  1 and s 1 
VIN

1

1   2 2   1  s   2 s s
N P  s  s 

1 RP 1
In more convenient form: f   f RL and f   f RC
2 LP 2RS CL
 2
  2


VOUT N S
 1  j f RL   f RL    1  j f   f 
 
VIN NP  f  f    f RC  f RC  
   
9
The output of a ratio transformer is connected to a remote capacitive sensor via 10m of coaxial cable (100pFm-1).
The other side of the bridge is connected to a local reference capacitor, hence a significant imbalance.
The transformer includes a 20 turn primary and 200 turn secondary (ten strands with 20 turns) of 24SWG copper
wire on a 5c SM100 toroidal core. The primary consists of 5 sets of 20 turns (BNNL) connected in parallel (to
ensure a uniform sheet of current around the core). From the previous example, very approximately (the length of
wire and resistance is slightly higher due to the rope construction): -
Secondary inductance = 200  200  102 H turn2  4H

Secondary resistance:  1
Primary inductance = 20  20  102 H turn2  40mH
Primary resistance  0.02
N.B. to maintain a very low primary resistance the negative feedback connection (to the driving stage) is taken
from as close as possible to the transformer terminals, avoiding “tails”. From above: -
 2
  2

f  f RL f  f RC 
VOUT N S
 1  j f RL   f RL    1  j f   f 
 
f  f   
and
VIN NP  f RC  f RC  
   
1 RP 1
with f RL   0.08Hz and f RC   160MHz
2 LP 2RS CL
VOUT N S
VIN

NP
  
1  j5  105  2.5  10 9  1  j105  1010 
VOUT N S
VIN

NP

1  j 4  105  2.6  10 9 
40ppm of quadrature can be easily rejected with a suitable quadrature servo or accurate signal conditioner/phase
sensitive detector. The in-phase component is negligible.
4.6 A single stage resistance bridge
The relatively low input impedance and limited accuracy (primary to secondary), at low frequency, make single
stage RTs of limited application. The performance of IVDs and RTs is much improved with extra energising stages
[1 and 2].
The following, however, can be used as part of a simple (low cost) resistance thermometry bridge (accuracy ≈
10mK), operating at 400Hz, by employing a high accuracy voltage follower [3] with semiconductor switches. The
follower forces the reference voltage across a standard resistor. The resulting current flows through the
thermometer resistor which creates the second voltage. At null balance the ratio of voltages is the ratio of
resistances.
1. Part 3, monograph 3: “Two-stage IVDs and RTs”.

2. Part 3, monograph 4: “Three-stage RTs”.
3. Part 4, monograph 2: “High accuracy voltage followers”. See section 6.3.
10
Part 3: Monograph 2
128
W2 128
W1
RS
0V W2
T1
W2 0V
RT Output
T2 W3
Auxiliary core
W4
Fig. 4.6.1 A single-stage two-terminal pair resistance bridge
Winding1: 128 turns 0.315mm enamelled copper wire wound BNNL [1].
This carries the current to energise the main core. The precise number of turns is not important.
Winding 2: 128 turns of a 5 strand rope of 0.2mm wire (BNNL).

One of the strands provides the fixed reference voltage, VS. Another is connected across winding 3 which, with the
extra turns around the auxiliary core, ensures an accurate voltage match between VS and the outputs of winding 3
(“equalisation”: see section 6). The other 3 are connected in series and switched to provide the first (most
significant) two bits of the (binary) divider.
Winding 3: 8 turns (NNL) of a 16 strand rope of 0.2mm wire around the main core (size 3A mumetal) plus 3 turns
around the auxiliary core (size 1A mumetal). The 16 strands are connected in series and switched (0 – 15) to
provide the next four bits of the divider. The voltage developed across all 16 strands (total 128) may not be quite
the same as VS, due to flux leakage, hence the equalisation winding and auxiliary core.
Winding 4: 1 turn of 8 strand rope. The 8 strands are connected in series and switched (0 – 7) to provide the next
three bits of the divider. In this case the accuracy is sufficient not to require equalisation with winding 3.
The variable winding thus varies from 0 – 512 turns and a ratio in the range of 0 – 4 and more than sufficient to
cover the range of resistance of platinum resistance thermometers with a suitable standard resistor (typically 25Ω or
100Ω).
The auxiliary core ensures ratio accuracy between the two main ropes. See section 6 for details.
The ratio transformer provides the first 9 bits of a null balance bridge. Further accuracy and resolution could be
provided by an R-2R ladder 8 or 12 bit multiplying DAC or by interpolation with an analogue to digital converter.
5. Inductive voltage dividers (auto-transformers)
The analysis for single stage IVDs, often referred to as auto-transformers, is exactly the same. The result is a device
with usefully high input impedance and low output impedance, making multi-decade dividers relatively easy to
construct (i.e. the Kelvin-Varley method). See the monograph “IVDs and RTs – the basics” by the same author [2].
1. Part 3, monograph 1: “IVDs and RTs – the basics”. For balanced no-net-loop (BNNL) etc see section 1.3.
2. Ibid. For the Kelvin-Varley method see section 2.
11
A second decade variable winding can usually be provided by a second rope with one tenth the number of turns of
the first decade and employed as an IVD. Being part of the same rope the voltage of each strand should accurately
match. Unfortunately it is possible that flux leakage, particularly at the start and end of the magnetic strip that
makes up the “clock-spring” core, can result in a few parts per million (ppm) of difference between decades 1 and 2
because they are not on the same rope. The most practical solution is to include an extra strand to the first decade
rope (the “equalising” winding) and connect it in parallel with ten strands of the second decade. Extra inductance is
added in series with the decade 2 rope by winding extra turns around an auxiliary core. This is often represented,
employing the usual convention, as follows: -
Decade 1
extra strand
Φ1 Φ2 Decade 2
Auxiliary core
Fig. 6.1 Equalising voltages between the first and second decade
Unfortunately this representation is not particularly revealing and a more representative diagram is as follows: -
VU I3 VL
ZOUT
Φ1
Z4
V3
Z3
V2 Φ2
Z2
V1
Z1
Fig. 6.2 Detailed diagram of an equalising scheme (only four strands shown)
The flux through the main core is 1 . The flux in the auxiliary core is  2  N A I 3 AL 2
According to Ohm’s, Kirchhoff’s and Faraday’s laws in the complex representation s  j  d dt  : -
The unloaded voltage induced in the equalising winding is: VU  sNS 1
The loaded voltage includes the error voltage due to the flowing current: VL  VU  I3ZOUT
 sNS 1  VL  I3ZOUT
12
Part 3: Monograph 2
The total voltage in the rest of the circuit consists of the induced voltages, including the flux leakage represented as
a relative factor, δ, and the voltage dropped across all ten winding resistances and any reflected impedance from the
primary side. These are represented (in fig 6.2) as lumped impedances in series with each strand. As these are very
small (mainly the auxiliary winding resistance) and closely matched the second decade IVD remains very linear: -
VL  sNS 1 1     sN A2  I3Z A with Z A  Z1  Z2  ....  Z10
NS 1  VL  I3ZOUT and 2  N A I3 AL 2  VL  VL  I3ZOUT 1     I3 sLA  Z A 
The small voltage I 3ZOUT is negligible and the error, expressed as a ratio, is, therefore: -
I 3ZOUT ZOUT

VL ZOUT  sLA  Z A 
The impedance of the auxiliary windings is much greater than the output impedance of the equalising winding and
certainly much larger than the total impedances ZA. To a good approximation, therefore: -
I 3ZOUT Z
  OUT
VL sLA
A typical (competitive) target accuracy is an overall error of 0.1ppm and a reasonable target for the second decade
contribution is, therefore, also 0.1ppm (even though its effect is reduced by a factor of 10). With a worst case
mismatch of 10ppm due to flux leakage one can conclude: -
I 3ZOUT
 10 7 and   105  sLA  100ZOUT
VL
With a maximum source resistance of 100Ω which, when reflected to the first decade secondary, appears as an
output resistance of 1Ω. The auxiliary impedance at the operating frequency needs to be greater than 100Ω. This is
easily achieved with a sufficiently large auxiliary core with very few turns. The choice often reduces to one of
practicality and aesthetics (a nice fit that sits on top).
If the resistance of the energising winding becomes an issue then a simple solution is to include two or three
extra strands to the decade 1 rope and connect them in parallel.
13
VMAX/turn/Hz
Axial code
Core axial
Case axial
Circ./turn
Core OD
Case OD
Core ID
Case ID
Type
AL
LE AE
μH/turn2
0 a 18 11 5 18 16 13 3.2 45 5 14 1.6E-05
b 18 11 8 24 16 13 6.4 45 10 28 3.2E-05
1 a 21 11 5 21 19 13 3.2 50 10 26 3.2E-05
b 21 11 7 24 19 13 4.8 50 15 38 4.8E-05
c 21 11 8 27 19 13 6.4 50 20 51 6.4E-05
2 a 24 12 7 26 22 14 4.8 57 19 41 5.9E-05
b 24 12 8 29 22 14 6.4 57 25 55 7.9E-05
c 24 12 10 32 22 14 7.9 57 31 69 9.9E-05
3 a 31 17 7 29 29 19 4.8 75 23 38 7.1E-05
b 31 17 9 32 29 19 6.4 75 30 51 9.5E-05
c 31 17 10 36 29 19 7.9 75 38 63 1.2E-04
4 a 36 20 9 34 33 22 6.4 87 35 51 1.1E-04
b 36 20 10 37 33 22 7.9 87 44 63 1.4E-04
c 36 20 12 40 33 22 9.5 87 53 76 1.7E-04
5 a 41 23 9 36 38 25 6.4 100 40 51 1.3E-04
b 41 23 12 42 38 25 9.5 100 60 76 1.9E-04
c 41 23 15 48 38 25 12.7 100 81 102 2.5E-04
6 a 50 29 7 36 48 32 4.8 125 38 38 1.2E-04
b 50 29 10 42 48 32 7.9 125 63 63 2.0E-04
c 50 29 12 45 48 32 9.5 125 75 76 2.4E-04
d 50 29 15 52 48 32 12.7 125 100 101 3.2E-04
7 a 60 36 7 38 57 38 4.8 150 45 38 1.4E-04
b 60 36 12 48 57 38 9.5 150 91 76 2.9E-04
c 60 36 15 54 57 38 12.7 150 121 102 3.8E-04
8 a 69 42 10 48 67 45 7.9 174 88 64 2.8E-04
b 69 42 14 54 67 45 11.1 174 123 89 3.9E-04
c 69 42 17 61 67 45 14.3 174 159 115 5.0E-04
9 a 79 49 14 58 76 51 11.1 200 141 89 4.4E-04
b 79 49 17 64 76 51 14.3 200 182 114 5.7E-04
c 79 49 15 61 76 51 12.7 200 161 101 5.1E-04
10 a 90 54 15 65 86 57 11.1 224 158 89 5.0E-04
b 90 54 18 72 86 57 14.3 224 204 114 6.4E-04
c 90 54 23 81 86 57 19.1 224 272 153 8.6E-04
11 a 112 66 16 78 108 70 12.7 279 242 109 7.6E-04
b 112 66 19 85 108 70 15.9 279 303 136 9.5E-04
c 112 66 23 91 108 70 19.1 279 364 164 1.1E-03
12 a 132 78 18 90 127 83 14.3 329 317 121 1.0E-03
b 132 78 23 100 127 83 19.1 329 424 162 1.3E-03
c 132 78 29 112 127 83 25.4 329 564 215 1.8E-03
13 a 164 110 18 90 159 114 14.3 429 322 94 1.0E-03
b 164 110 23 100 159 114 19.1 429 430 126 1.4E-03
c 164 110 29 112 159 114 25.4 429 572 167 1.8E-03
14 a 28 17 6 23 25 19 3.2 70 10 18 3.1E-05
b 28 17 9 29 25 19 6.4 70 20 36 6.3E-05
Notes: -
1. All dimensions in mm or mm2
2. AL Assumes μR=100,000.
3. VMAX for sinusoidal peak flux density of 0.5T, one turn at 1Hz
14
Part 3: Monograph 2
Appendix 2:Copper winding data
Imperial standard wire gauge (SWG)
No. 16 18 20 22 24 26 28
Diameter
1.626 1.219 0.914 0.711 0.559 0.457 0.376
(mm)
mΩm-1 8.3 14.8 26.0 43.5 70.5 105 155
No. 30 32 34 36 38 40
Diameter
0.315 0.274 0.234 0.193 0.152 0.122
(mm)
mΩm-1 222 293 404 590 950 1480
Metric wire data
Diameter
50 63 80 100 125 160 200 250 315 400 500
(µm)
Ωm-1 8.78 5.53 3.43 2.20 1.41 0.86 0.55 0.35 0.22 0.137 0.088
15
Part 3: Monograph 3
Two-stage IVDs and RTs

1. Two-stage IVDs
The most practical way to increase input impedance and accuracy of an IVD ratio winding (at low frequency) is to
use an extra core with a separate energising winding. The energising winding is around one core, the ratio winding
around both. The basic idea is that the energising winding carries most of the current and the energising core most
of the flux. The voltage induced in the ratio winding opposes the applied voltage and thus “bootstraps” its input
impedance. This is represented diagrammatically in fig. 1.1
I1 R1
Ratio winding
V1 Φ1 Φ2
(N turns)
Energising I2 R2
winding V2
(N turns)
Fig. 1.1 A two-stage inductive voltage divider
I shall assume negligible flux leakage and a linear model for permeability.
V1  I1R1  sN 1   2  V2  I 2 R2  sN 2
For ideal magnetic circuits the fluxes are: -
1  NI1 AL1  2  N I1  I 2 AL 2
AL1  permittance of core 1. AL 2  permittance of core 2.
From the above: V1  I1R1  sN 2 I1 AL1  I1 AL 2  I 2 AL 2  V2  I 2 R2  sN 2 I1 AL 2  I 2 AL 2 
Define winding inductances: L1  N 2 AL1 and L2  N 2 AL 2
Then: V1  I1 R1  sL1  sL2   I 2 sL2 and V2  I1sL2  I 2 R2  sL2 
 V1   R1  sL1  sL2 sL2  I1 

In vector-matrix notation: V  ZI      
R2  sL2  I 2 
or
V2   sL2
1
a b  1  d  b
    
ad  bc   c a 
The inverse of a 2×2 matrix is:
c d 
 I1  1  R2  sL2  sL2  V1 
The inverse is: I  Z 1V      
R1  sL1  sL2 V2 
or
 I 2  Z   sL2
1
Where Z is the determinant of the input impedance matrix: -
R1  sL1  sL2 sL2

Z  R1R2  sL2 R1  sL1 R2  sL2 R2  s 2 L1 L2
sL2 R2  sL2
If both inputs are connected to the same voltage source, VIN then: -
R2 R  sL1
I1  VIN and I 2  1 VIN
Z Z
I1 R2
The ratio of the currents is an interesting result: 
I 2 R1  sL1
At a typical operating frequency the magnitude of the inductance is much greater than the winding resistances and
the current in the ratio winding is, therefore, much smaller than the current in the energising winding.
Also, one can conclude that the flux in the energising core is much greater than the flux in the ratio core:  2  1
This is advantageous – a low flux level ensures the highest permeability.
The input impedances are: -
VIN Z
Energising winding: Z2  
I2 R1  sL1
VIN Z R  sL1
Ratio winding: Z1    Z2  1
I1 R2 R2
At very low frequency (including DC) the result is just the winding resistances: -
R
s   Z1  R1 and Z 2  R2
L
At high frequency the energising winding looks like a simple inductor but the ratio winding looks like a large
(frequency dependent) negative resistor (increasing as frequency squared): -
R s 2 L1 L2
s   Z 2  sL2 and Z1 
L R2
Without the energising winding one would expect Z1  sL1 and so the impedance has been increased by a large
“bootstrap” factor. Put simply: -
R sL2
s   Z1  sL1 
L R2
As with single-stage inductors a general rule of thumb for the energising stage is to maximise the ratio of
inductance to resistance [1].
1. Part 3, monograph 2: “Single-stage inductors and transformers”. See sections 2 and 3.
2
Part 3: Monograph 3
The full analysis, in normalised form s  j  N  is: -

1  as  s 2

Z1  R1 1  as  s 2  and Z 2  R2
1  bs
R1 R2 L L L  R2 L1
With N  a   2  1  2  N and b 
L1 L2  R2 R1 R1  R1 L2
Note that, as usual, the natural frequency is the geometric mean of the two characteristic frequencies.
To a very good approximation, retaining both in-phase and quadrature components, therefore: -
s 
R
L
 
Z1  R1 as  s 2 
 f  f  
2
f  f N  
Z1  R1 ja   with fN 
1 R1 R2
 f N  f N   2 L1 L2
 
 Im   f  f
The phase of Z1 is:   arctan   arctan  a N     a N (radians).
 Re   f  f
I.e. just less than 180 degrees (predominantly negative real).
If one assumes that the inductances are the same (same size/permeability cores) but R1 is twice R2 (the most basic
design - the top winding is longer because it is around both cores): -
2 R2  R2  R2 1 2 R2
R1  2R2  a 2 2 b and fN 
2 R2 R2 2 2 L
fN
With a phase angle:   2 2 when expressed in radians.
f
Rule of thumb: A higher inductance to resistance ratio means a lower natural frequency and a lower phase
error (imaginary component), compared to a pure (negative) resistance.
This model works well for an operating frequency up to a few hundred Hz. At higher frequency the interwinding
capacitance becomes significant.
3
The following illustrates what is possible with 400 turns on a pair of medium sized SM100 cores for operation at
75Hz. This is fairly simple to construct by employing the BNNL winding technique [1].
Both cores type 7c (see appendix 1): -

OD = 60mm ID = 36mm axial = 15mm.
The length of wire per turn on the energising winding is approximately: 15 × 2 + 60 – 36 = 54mm
Inner circumference = 36mm × π = 113mm can accommodate 400 turns in two layers of 0.565mm OD wire.
Outer circumference = 60mm × π = 188mm can accommodate 400 turns of 0.47mm OD in a single layer.
The outer circumference is the limiting dimension: the largest wire diameter that is a comfortable fit is 26SWG
(enamelled) at 0.457mm diameter with a resistance of 105mΩm-1.
The energising winding requires: 400  54mm  22m of wire.

Resistance R2 would be approx: R2  22m 105mm1  2.3
Permittance of both cores: AL  102H turn 2
Inductance of both windings: L1  L2  N 2 AL  400  400 102 106  16H
The ratio winding consists of a rope with ten strands wound 40 times (also BNNL) of the same wire.
With 10 strands the rope is approximately 2mm in diameter. The inner diameter is reduced slightly: -
Inner circumference = 30mm × π = 94mm can accommodate 40 turns in a single layer (2.35mm/turn).
Outer circumference = 60mm × π = 188mm can easily accommodate 40 turns also in a single layer.
As a ball park estimate the length of wire, for the ratio winding, is roughly twice that of the energising winding,
partly because it is wound around both cores and partly because the strands are twisted into a rope. If one assumes
that the source resistance to both energising and ratio windings are negligible compared to the winding resistances
the natural frequency is: -
1 R1 R2
R1  2R2  4.6  fN   0.032 Hz
2 L1 L2
At 75Hz the inductive reactance of the energising winding is: X L  2fL  7.5k (inductive)
s 2 L1 L2
The bootstrapped input impedance of the ratio winding is: Z1   25M (negative resistive)
R2
The result is a much smaller device which is easier to wind than a comparable single stage IVD. In practice it
would be possible to experiment with thicker wire for the rope winding, in order to ensure a neat construction, with
an evenly distributed double layer on the inner circumference, and even better results.
N.B. The two-stage IVD has been investigated thoroughly and it is stated (in the synopsis) that “Single decade
dividers having in-phase errors of less than 5ppb of the input over the frequency band 40 – 400Hz have been
constructed”. The limiting factor is stated as being “due to inequalities in the core flux effectively linking each of
the ten sections of the divider” [2].
Historically the two-stage IVD led to a number of bridge configurations but these are now obsolete thanks to active
drive of the energising winding (see section 4) and the development of the three-stage ratio transformer [3].
1. Part 3, monograph 1: “IVDs and RTs – the basics”. For balanced no-net-loop technique see section 1.3.
2. Hill, J. J. and Deacon, T.A. “Two stage inductive voltage dividers” Proc. IEE 1968 vol. 115 part 6, pp888
– 892.
3. Part 3, monograph 4: “Three-stage RTs”
4
Part 3: Monograph 3
With the inductance and resistance values above a spreadsheet model confirms the predicted behaviour (real
component increasing second order and imaginary component first order with respect to frequency: -
 f  f  
2
f  f N  
Z1  R1 ja   with fN 
1 R1 R2
 f N  f N   2 L1 L2
 
Fig. 1.1.1 Real (blue) and imaginary (green) components of the input impedance (Ohms on a log scale).
5
2. Two-stage transformers
The ratio winding rope can easily accommodate extra strands for use as an isolated secondary winding. The
reduction of current in the ratio primary results in a significant improvement in ratio accuracy between primary and
secondary. In the following analysis I shall assume that no current is flowing in the secondary and, therefore, the
input impedances are the same as for the two-stage IVD.
I1 R1
Ratio primary
V1 NP Φ1 Φ2
NS VOUT
Energising I2 R2 Secondary
winding V2 NP (NS turns)
Fig. 2.1 A two-stage ratio transformer
According to Faraday’s law the output voltage is: VOUT  sNS 1   2 
I shall assume that both inputs are connected to the same voltage source, VIN. As before the input voltage is: -
VIN  I1R1  sNP 1   2 
sNS 1   2 
T s  
VOUT
The transfer function is, therefore: 
VIN I1R1  sN P 1   2 
Eliminate the fluxes with: 1  N P I1 AL1  2  N P I1  I 2 AL 2
sNS N P I1 AL1  I1 AL 2  I 2 AL 2 

 T s  
R1  sN P2 I1 AL1  I1 AL 2  I 2 AL 2 
I 2 R1  sL1
From section 1: 
I1 R2
Also, by definition, the inductances are: L1  N P2 AL1 and L2  N P2 AL 2
With a little algebra (divide top and bottom by I1 and multiply by R2 ) the transfer function is: -
NS  sR2 L1  R2 L2  R1L2   s 2 L1L2 

 T s    
N P  R1R2  sR2 L1  R2 L2  R1L2   s L1L2 
2
6
Part 3: Monograph 3
 as  s 2 
In normalised form s  j N  :
VOUT N S
  
2 
VIN NP  1  as  s 
R1 R2 L L L 
With N  and a   1  2  2  N
L1 L2  R1 R1 R2 
Note, again, the natural frequency is the geometric mean of the two characteristic frequencies.
Apart from the turns ratio this is exactly the same transfer function I derived for a two stage high-pass filter [1].
One can use the same approximation at high frequency: -
T s   1 
1 a
  N  
s 2 s3
In a more convenient form, with frequency in Hz: -
2 3
f  f 
T  f   1   N   ja  N 
1 R1 R2
 f   f  2 L1 L2
As with a basic (single-stage) transformer the in-phase error is second order and usually too large for the very
highest accuracy applications. The quadrature error, however, is now third order and very small at the operating
frequency. A two-stage transformer could be used, therefore, where only low phase error is required. (e.g. as a step-
down injector as part of a quadrature null balance system). They are also useful in the lower (less critical) decades
of a multi-decade bridge. At higher frequency two-stage transformers also prove useful for multi-decade
capacitance bridges by allowing a reduction in the required number of turns and a corresponding reduction in inter-
winding capacitance.
As with the previous example calculation (section 1.1) I shall assume the most basic design (same size/permeability
cores), R1 is twice R2 (the ratio winding is longer because it is around both cores and twisted into a rope) and both
primary windings are connected to the same low resistance source: -
L L L  R L  R2 L2  R1L2
R1  2R2 and L1  L2  a   1  2  2 N  2 1  2 2  2.8
 R1 R1 R2  R1R2 L1L2
1 R1R2 2 R2
The result is a small peak near the natural frequency. Also: f N  
2 L1L2 2 L2
With a pair of 7c SM100 cores with 400 turns of 26SWG wire for the windings: -
L1  L2  16H R2  2.3 f N  0.032Hz
2 3
f  f 
at 75Hz  T  f   1   N   ja  N   1  1.8 10 7  j 2.2 10 10
 f   f 
With up to 0.2ppm the in-phase error this is not quite good enough for some applications but the phase error is
negligible. For lower in-phase error see [2].
1. Part 2, monograph 1: “Two-stage filters”. See section 4.

7
3. The matrix method and the equivalent circuit
If one compares the impedance matrix of the two-stage IVD (page 1) and the two-stage RC low-pass filter one
observes that replacing the capacitors with inductors results in the required transfer function [1]. For example: -
 V1   R1  X 1  X 2 X 2  I1  1
      X1 
R2  X 2  I 2 
For the low-pass RC filter: etc
V2   X2 sC1
 V1   R1  sL1  sL2 sL2  I1 

      X 1  sL1 etc
R2  sL2  I 2 
From page 1:
V2   sL2
This suggests the equivalent circuit: -
R1 I1 U1
R1 V1
I1
V1
U1
C1 L1
R2 I2
V2 U2 R2 I2
becomes
V2 U2
C2
L2
0V
Fig. 3.1 Equivalent circuit for a two-stage voltage transformer
The bootstrap effect of the energising core is just the same as for two-stage filters. This proves useful for modelling
multi-stage transformers, especially when it comes to stability analysis of active drives. One can also re-use the
matrix analysis of high accuracy filters. According to Ohm’s and Kirchhoff’s Laws the output voltages are: -
U 2  sL2 I1  I 2  U1  sL2 I1  I 2   sL1I1
I shall again employ the general symbols  X 1  sL1  etc so that: -
 U1   X 1  X 2 X 2  I1 
      i.e. U  XI
U 2   X 2 X 2  I 2 
This defines the output impedance matrix X .
The input impedance matrix equation can also be constructed by noting: -
 V1   U1   R1 0  I1   R1  X 1  X 2 X 2  I1 
             i.e. V  ZI
V2  U 2   0 R2  I 2   X2 R2  X 2  I 2 
This defines the input impedance matrix Z .
8
Part 3: Monograph 3
The inverse is often useful (for calculating input currents and impedances): -
I  Z 1V
1
a b  1  d  b
    
ad  bc   c a 
The inverse of a 2×2 matrix is:
c d 
1  R2  X 2  X2 
Z 1   
Z   X2 R1  X 1  X 2 
R1  X 1  X 2 X2
Z is the determinant: Z   R1R2  R1 X 2  X 1 R2  X 1 X 2  R2 X 2
X2 R2  X 2
Combine with the output impedance matrix equation for the matrix equivalent of the transfer function equation
(outputs versus inputs): -
Where T is the transfer function matrix: T  XZ 1
1  X1  X 2 X 2  R2  X 2  X2 
T   
X 2   X 2 R1  X 1  X 2 
So that:
Z  X2
Multiply the matrices: -
 U1  1  X 1 R2  X 2 R2  X 1 X 2 X 2 R1  V1 
     
U 2  Z  X 2 R2 X 2 R1  X 2 X 1 V2 
This defines the matrix Ω so that: Ω  Z T  Z XZ 1
Replace the general symbols  X 1  sL1  etc so that: -
Ω Ω12   sL1  L2 R2  s 2 L1L2 sL2 R1 

Ω   11    
 Ω21 Ω22   sL2 R2 sL2 R1  s L1L2 
2
To find any of the output voltages, in terms of the inputs, it is now a simple case of calculating only the required
components of Ω and the determinant Z . Specifically: -
11V1  12V2 21V1   22V2

U1  and U 2 
Z Z
A spreadsheet with sliders for the main parameters and graphs for the frequency response and error terms (in-phase
and quadrature) is ideally suited to computer modelling. The calculations are reduced to bite-size chunks (e.g.
matrix elements) using complex number functions (IMSUM, IMPRODUCT, IMDIVIDE etc.) and then combined.
9
4. Two-stage active drive and stability
4.1 Active drive for both primary windings
With two-stage IVDs and ratio transformers both ratio and energising windings can be driven with, for example,
high accuracy voltage followers, with no stability problems. See fig. 4.1.1. Note the order of the negative feedback
connection – the larger current flowing through the energising winding should not flow through any part of the
connection to the ratio winding (i.e. it is a zero-Ohm junction, type 1 [1]). The followers need very low DC offset
in order to avoid DC current flowing through the (low resistance) windings.
VOUT
VIN
Fig. 4.1.1 A two-stage ratio transformer with high accuracy followers
The main advantage is the very high input impedance and extremely low output impedance of the followers. The
main disadvantage is extra noise due to the followers.
In this case both inputs are connected to the same low resistance source and the output (ratio 1:1) is: -
VOUT  U1 
Ω11V1  Ω12V2   Ω11  Ω12  V
IN
Z Z
Z  R1R2  sL2 R1  sL1R2  sL2 R2  s 2 L1L2
R2 sL1  R2 sL2  sL1sL2  R1sL2

T s  
VOUT
The transfer function required is, therefore: 
VIN R1R2  sL2 R1  sL1R2  sL2 R2  s 2 L1 L2
sL1  L2 R2  R1L2   s 2 L1L2

Reorganise into powers of s: T s  
R1R2  sL1  L2 R2  R1L2   s 2 L1L2
Divide top and bottom by R1R2 and express in normalised form s  j  N  . This agrees with the previous result
(pages 5 and 6) as long as one re-introduces the turns ratio: -
N S  as  s 2 
T s    
N P  1  as  s 2 
R1 R2 L L L 
With N  and a   1  2  2  N
L1 L2  R1 R1 R2 
The error analysis is the same as section 2.
1. Part 1, monograph 1: “High accuracy resistors”. See section 3.4.
10
Part 3: Monograph 3
4.2 Active drive for the energising winding only [1]
The problem of voltage follower voltage noise can largely be avoided by driving only the energising winding. The
follower current noise, however, flows through the source resistance and best performance is achieved when the
follower noise resistance is substantially greater than the source resistance. The main advantages of two-stage
construction (increase in input impedance and low phase error) are retained.
VIN VOUT
Fig. 4.2.1 Active drive of the energising winding only
The equivalent circuit again proves useful as a model (see section 3). If one assumes a transformer ratio setting of
1:1 the equivalent circuit is an actively driven two-stage high-pass filter: -
RS V1 I1 R1
VOUT
L1
R2
VIN I2
U2
V2
L2
Follower
0V
Fig. 4.2.2 Active drive of the energising winding only – equivalent circuit
The only problem with this approach is the peak in the frequency response at around the natural frequency due to
positive feedback. The size of the peak depends mainly on the source resistance.
If the voltage source is set to zero the feedback network consists of the energising winding (high-pass
characteristic) followed by the ratio winding and source resistance (low-pass characteristic). See fig. 4.2.3.
1. Gibbins, D. L. H.: “A circuit for reducing the exciting current of inductive devices”. Proc. IEE vol.
108B (1961) pp 339-343.
Gibbins was an early contributor to the development of active drive of two-stage IVDs though he did
not seem to understand the problem of (low frequency) feedback and stability. In his paper, cited by
many other experts, the first sentence begins “A negative feedback device is described…” Later,
however, he does identify “The technical difficulties of the device, regarded as an exercise in feedback-
amplifier design, reside in the fact that the external source impedance, which is not under the designer’s
control, appears in the feedback loop between two transformers (fig. 2)”. The diagram to which he
refers should have provided a strong clue – the feedback is positive! He achieved an increase in input
impedance by a very useful factor of 130 at 52.5Hz but there is no mention of stability margin. He does
anticipate, however, the possibility of accurate three-stage ratio transformers but finally admits:
“Whether it is possible to achieve a higher overall multiplication by this means before the feedback
problems become insuperable has not been investigated.”
11
The result is positive feedback with a band-pass characteristic whose peak magnitude can approach unity,
depending on the relative cut-off frequencies: -
R2 U2 L1 R1
V2
V1
Low pass
High pass L2 RS
0V
Fig. 4.2.3 The feedback network (input voltage VIN=0)
For adequate stability margin the high-pass cut-off frequency needs to be about the same or higher than the low-
pass cut-off: -
Fig. 4.2.4 Low-pass, high-pass and combined band-pass characteristic
Apart from the interaction between the high pass and low pass sections the cut-off frequencies are: -
R2 RS  R1 R2 RS  R1
HP  LP  required: HP  LP  
L2 L1 L2 L1
With a high source resistance (RS > 10Ω) it would seem that one needs to increase R2 with an extra component
resistor and/or increase L1 substantially relative to L2. Fortunately there is an ingenious solution which makes it
possible to retain a low natural frequency (high accuracy) as well as a good stability margin: a “compensator” - see
later. This proves particularly necessary for three-stage ratio transformers [1] where the source resistance can be up
to 100Ω. For higher source resistance (≈1kΩ) see the monograph “Noise matching transformers” [2].
1. Part 3, monograph 4: “Three-stage RTs”. See section 3.

2. Part 3, monograph 5: “Noise matching transformers”. See section 3.
12
Part 3: Monograph 3
4.2.1 Network analysis
The matrix equations for the transformer network are repeated for convenience (see section 3): -
 I1  1  R2  X 2  X2  V1 
      with X1  sL1 etc.
 I2  Z   X 2 R1  X 1  X 2 V2 
If one assumes an ideal voltage follower (V2 = V1) then I1 simplifies to: -
R2 R2
I1  V1  V1
Z R1R2  sL2 R1  sL1R2  sL2 R2  s 2 L1L2
 R2 RS  Z
But VIN  V1  I1 RS  V1 1   so that V1  V2  VIN
 Z  Z  R2 RS
 
From above: VOUT 

Ω11V1  Ω12V2   VOUT 
Ω11  Ω12   Z
VIN
Z Z Z  R2 RS
11  12
Resulting in: VOUT  VIN
Z  R2 RS
 Ω11 Ω12   sL1  L2 R2  s 2 L1L2 sL2 R1 

From above: Ω      
Ω
 21 Ω22   sL2 R2 sL2 R1  s 2 L1L2 
Also from above: Z  R1R2  R1 X 2  X 1R2  X 1 X 2  R2 X 2
The closed loop transfer function for the equivalent circuit is, therefore: -
sL1  L2 R2  R1L2   s 2 L1L2

T s  
VOUT

VIN R2 RS  R1   sL1  L2 R2  R1L2   s 2 L1L2
as  s 2
In normalised form s  j N  : T s  
1  as  s 2
R2 RS  R1   L  L2 R1L2 
With N  and a   1  N
L1 L2  RS  R1 R2 RS  R1  
The result is similar to the previous case (see pages 5 and 6) with two important differences. The resistance R1 is
replaced by R1 + RS in the formula for the natural frequency and in the denominator for parameters a and b.
Increasing source resistance results, therefore, in increasing natural frequency (lower accuracy) and
decreasing values of a and b (less stability margin).
13
4.2.2 Stability analysis (approximate)
This is the same transfer function as the two-stage high pass filter with the same trade-off [1]. A value of the
coefficient a between 2 and 4 results in peaking which is tolerable in most applications. A lower value results in a
higher resonant peak. If the inductances are the same, R1 is twice R2 (see example calculation page 4) and if one
assumes the minimum value of a = 2: -
R2
a4  2 then the maximum source resistance is: RS  2R2
RS  2 R2
Since a typical energising winding is ≈ 2Ω (or lower) this is only possible for some applications (e.g. for an IVD
based system with low source resistance). It would not be possible, for example, to connect the ratio winding
directly to a standard resistor or sensor or via a semiconductor switch with series resistance greater than 4Ω.
Increasing source resistance increases the cut-off frequency of the low pass section of the feedback network,
increasing the overlap with the high pass characteristic. Stability could be restored with a higher value for R2 thus
increasing the frequency of the high pass characteristic and reducing the overlap. Unfortunately this also increases
the natural frequency of the overall transfer function and reduces accuracy. Reminder: from above, the in-phase
error is only second order with respect to frequency: -
2 3
f  f 
T  f   1   N   ja  N 
1 R1 R2
 f   f  2 L1 L2
If, for example, one adds a component resistor in series with R2 so that the sum is the same value as the maximum
expected source resistance: -
R 4 R 4
R2  R  RS  a4  and RS  0  a4 
RS  2 R 3 0  2R 2
or 2.3  a  2.8
The result is reasonably stable though the increase in natural frequency could be a problem.
Rule of thumb: To improve stability add extra resistance in series with the energising winding. This should
be approximately the same as the source resistance.
It is also possible to add extra turns and/or select a larger, higher permeability core to increase the inductance L1 but
the latter improvement is modest (with much more expensive RM200 cores the inductance would increase only by
a factor of two). Doubling the number of turns (on the top core only), on the other hand, increases the inductance,
L1, by a factor of four (see section 4.4). Fortunately there is also a simple way of reducing the overall natural
frequency: a “compensator” (see section 4.3). This largely restores the bootstrap effect at the operating frequency
but retains stability at lower frequency.
Rule of thumb: To improve stability employ a thicker (axially) and higher permeability top core and add
extra turns to the ratio winding (around the top core only).
Rule of thumb: To improve accuracy add a compensator in series with the energising winding.
14
Part 3: Monograph 3
This example illustrates the problem of source resistance with the most basic two-stage IVD or RT with active
drive for the energising winding. It employs the same basic transformer design (size 7c SM100 cores with 400
turns. See section 1.1): -
Inductance of both windings: L1  L2  16H
Ratio (primary) winding resistance: R1  4.6
Energising winding resistance: R2  2.3
With three values of source resistance: RS  1 , RS  10 and RS  100

as  s 2
The transfer function is, in normalised form s  j N  : T s  
1  as  s 2
R2 RS  R1   L  L2 R1L2 
With N  and a   1  N
L1 L2  S
R  R1 R2  RS  R 
1 
The respective natural frequencies (in radians/s) are: N  0.224 N  0.362 and N  0.97
The normalised parameters are: a  2.6 (lowest peak) a  1.6 and a  0.59 (highest peak)
Fig. 4.2.3.1 Frequency response for various values of source resistance [1]
Clearly the highest peak corresponds to the highest value of source resistance (100Ω) and is borderline stable for
most applications. The results for 1Ω and 10Ω are tolerable.
The conclusion is that the most basic two-stage IVD or RT needs a low source resistance (RS < 10Ω). For
applications with a higher source resistance see sections 4.3 and 4.4.
1. Spreadsheet: “A two-stage ratio transformer”.

15
4.2.4 Errors in the energising follower
The following analysis investigates the effect on performance due to any error or noise of the follower (driving
only the energising winding). Define parameter   1 to describe the difference between the voltage applied to the
ratio winding and the voltage applied to the energising winding, such that: -
V2  1   V1
N.B.  can be a complex number to represent in-phase and/or quadrature errors or a random number to represent
noise. From the matrix analysis above: -
 Ω11 Ω12   sL1  L2 R2  s 2 L1L2 sL2 R1 

Ω      
Ω
 21 Ω22   sL2 R2 sL2 R1  s L1L2 
2
VOUT  U1 
Ω11V1  Ω12V2   Ω11  Ω12 1   V
IN
Z Z
The transfer function required is, therefore: -
R sL  R2 sL2  sL1sL2  R1sL2 1   

T s  
VOUT
 2 1
VIN R1R2  sL2 R1  sL1R2  sL2 R2  s 2 L1 L2
Divide top and bottom by R1R2 and multiply each term by the natural frequency to the appropriate power so that, in
normalised form s  j N  : -
T s  
a   s  s 2 
as  s 2

s
1  as  s 2 1  as  s 1  as  s 2
2
R1 R2 L L L  L2 LR
With N  a   1  2  2  N and   N   2 1
L1 L2  R1 R2 R2  R2 R2 L1
At high frequency the extra term in the transfer function represents a small additional error: -
s 
s  1  
1  as  s 2
s
The result is an extra first order error (in terms of frequency) but since δ can be made very small it is often
negligible at the operating frequency. From the previous error analysis: -

T s   1 
1 a
s  1   
s s 2 s3
In a more convenient form, with frequency in Hz: -
2 3
f  f  f 
T  f   1  j  N    N   ja  N 
1 R1 R2
 f   f   f  2 L1 L2
N.B. Remember that ε can be imaginary so that the extra error could be in-phase. With a little care the follower
errors can be made less than 1ppm and so the overall effect, at the operating frequency, is usually negligible.
16
Part 3: Monograph 3
If one follows the previous example (section 1.1) where the inductances are the same and R1 is twice R2 a typical
value would be: -
L2 R1
     2
R2 L1
For a single op-amp with a gain-bandwidth product fB the follower error is mainly quadrature and proportional to
frequency [1]: -
f f  f
 j   j  N   2 N
fB  f  fB
With a transformer natural frequency less than 1Hz and a gain-bandwidth product of 5MHz the error contribution is
less than 1ppm. A two stage follower would result in a truly negligible contribution.
4.2.5 Follower noise
If  is random (i.e. noise due to the follower) then the extra noise appearing at the output is also significantly
reduced: -
  f 2  f N  
3
f 
 T s VIN  1     ja   VIN  j  N 
V 
  NOISE  VOUT N
VIN   f   f    f 

In the limit that the input signal, VIN, tends to zero (noise remaining): -
VNOISE f 
 and    2  VOUT  2  N VNOISE
VIN  f 
Where VNOISE is a random number representing the follower noise. The contribution due to the active drive is thus
much reduced. The follower current noise, however, flows through the source resistance and appears across the
ratio primary. Best performance is achieved, therefore, when the noise resistance of the followers is
significantly greater than the source resistance.
4.2.6 The effect on input impedance
 I1  1  R2  sL2  sL2  V1 
      with V2  1   V1
R1  sL1  sL2 V2 
From section 1:
 I 2  Z   sL2
 I1 
V1
R2  sL2  sL2 1     V1 R2  sL2 
Z Z
N.B. Unfortunately the value of L2 is not well defined (only the minimum is guaranteed) and so it is not possible to
exploit this property to reduce the input current to zero. To ensure that the ratio winding input impedance remains
high, therefore, one must rely entirely on the bootstrapping effect. The input impedance is, therefore: -
V1 Z Z sL 
Z1   and, to a good approximation Z1  1   2 
I1 R2  sL2 R2  R2 
R2
For the effect to be negligible one needs to ensure:  
sL2
As above this is easily achieved in practice.
1. Part 4, monograph 1: “High gain blocks”. See section 3: “Some operational amplifier circuits”.
17
4.3 Active drive with compensator (resistor/parallel capacitor)
Stability margin can be improved by adding a compensator in series with the energising winding. The capacitor is
chosen to have little effect at low frequency but bypasses the extra resistor at the higher (operating) frequency. This
substantially restores the bootstrap effect and ensures high input impedance and low phase error.
RS V1 I1 R1
VOUT
C L1
R2
VS I2
U2
V2
R L2
compensator
0V
Fig. 4.3.1 Addition of a parallel capacitor improves accuracy while maintaining stability
From above, repeated for convenience, the transfer function (without compensating R and C) is: -
sR2 L1  R2 L2  R1L2   s 2 L1L2

T s  
R2 RS  R1   sR2 L1  R2 L2  R1L2   s 2 L1L2
The new transfer function can be obtained by replacing the symbol for resistance, R2, with Z, the symbol for the
total series impedance including compensator: -
R
R2  Z  R2 
1  sRC
The result is a third order transfer function (see appendix 2 for details): -
T s  
R  R2 L1  L2   R1L2 s  R2 RC L1  L2   R1L2 RC  L1L2 s 2  L1L2 RCs 3
R  R2 RS  R1   R2 RC RS  R1 s  R  R2 L1  L2   R1L2 s  R2 RC L1  L2   R1L2 RC  L1L2 s 2  L1L2 RCs 3
In normalised form s  j  N  , in which I anticipate that δ can be made small compared to a: -

as  bs 2  s 3
T s  
1  a   s  bs 2  s 3
1
 R  R2 RS  R1   3 R  R2 L1  L2   R1L2 
 N    a
 RCL1 L2  R  R2 RS  R1  N
b
R2 RC L1  L2   R1L2 RC  L1L2   2 
R2 RC

R  R2 RS  R1  N
R  R2  N
Once again the natural frequency is the geometric mean of three characteristic frequencies - this time including the
RC time constant RC  0 . The transfer function is (very nearly) of the same form as a three-stage high-pass filter
for which the analysis suggests ideal values for a and b between 2 and 4 [1]. For a computer model see [2].
1. Part 2, monograph 2: “Three-stage filters”. See section 3.4.

2. Spreadsheet: “A two-stage ratio transformer with compensator”
18
Part 3: Monograph 3
A typical compensator consists of a large capacitor (1-100mF) in parallel with a small resistor (1 -100Ω). A typical
design has: -
R  10 and C  10mF
The extra 2.3Ω is due to the energising winding resistance: -
Fig. 4.3.2 Impedance (magnitude) of a typical compensator versus frequency
This is a rather large capacitor. A pair of back-back aluminium electrolytic type capacitors is not a realistic option.
Fortunately, there is a practical solution: a simulated large capacitor circuit [1]: -
R2
VIN I
VOUT
Load
R1
VIN C1
0V
Fig. 4.3.3 A simulated large capacitor circuit [1]
Strictly speaking it is not just a large capacitor. The equivalent circuit also has the parallel resistance: -
R
VIN VOUT
C
Fig. 4.3.4 Equivalent circuit
1. Part 6, monograph 1: “A simulated large capacitor circuit”.
19
4.3.1 Error analysis with compensator
as  bs 2  s 3
T s  
R2 RC
In normalised form, repeated for convenience:    R C
1  a   s  bs 2  s 3 R  R2  N 2 N
Divide top and bottom by as  bs 2  s 3 so that: -
1
 1  s 
1
  1   b a 1 
T s   1  3 
 1    1    
 as  bs  s 
2   s 3 s 2  s s 2  
 
To a very good approximation at high frequency, neglecting terms smaller than s 4 : -
1
  1   b  
s  1  T s   1   3  2 1   
 s s  s  
 1   b 
Repeat the approximation: T s   1   3  2 1  
s s  s 
It is now clear that δ results in a second order error (in terms of frequency) and one can neglect contributions of
fourth order and higher as long as δ is not too small. The second order (in-phase) and third order (quadrature)
analysis is, therefore: -

T s   1 
1
b  1 and s  1  2

s s3
2 3
f  f 
In more convenient form: f  f N  T s   1    N   j N 
 f   f 
If one applies a compensator of 10Ω and 1.6mF to the previous example with a source resistance of up to 100Ω: -
Inductance of both windings: L1  L2  16H
Ratio (primary) winding resistance: R1  4.6

1
1  R  R2 RS  R1   3 R RC
fN     1.1Hz and   2 2f  0.020
2  RCL1L2  R  R2  N
f  75Hz  T s   1  4.3  106  j3.2  106
The result is stable - a small resonant peak which increases with source resistance. Quadrature error is very small
but the in-phase error (4.3ppm) is still too high for many applications.
20
Part 3: Monograph 3
4.3.3 Spreadsheet simulation
Algebraic analysis with a compensator is quite complicated and it is worth checking the conclusions by computer
simulation. The simplest approach is to perform the calculations in bite-size chunks based on the matrix method.
From above the inverse matrix and determinant, without a compensator, are: -
Ω Ω12   sL1  sL2 R2  s 2 L1L2 sL2 R1 

Ω   11    
 Ω21 Ω22   sL2 R2 sL2 R1  s L1L2 
2
R
One simply needs to make the substitution: R2  Z  R2 
1  sRC
The matrix and determinant become: -
Ω Ω12   sL1  L2 Z  s 2 L1L2 sL2 R1 

Ω   11    
Ω
 21 Ω22   sL2 Z sL2 R1  s 2 L1L2 
Z  R1Z  sL2 R1  sL1  L2 Z  s 2 L1L2
Also, from section 4.2.1, the source resistance affects the feedback factor and R2  Z so that: -
Z 11  12
V1  V2  VIN  VOUT  VIN
Z  ZRS Z  ZRS
U1 Ω11  Ω12
 T s   
VIN Z  ZRS
For a typical application: L1  16 H L2  2 H R1  6.9 R2  2.3 R  10 C  1.6mF
Fig. 4.3.3.1 Spreadsheet simulations for source resistance 1, 10, 25 and 100Ω
21
Adding extra turns around the top core can be represented, diagrammatically, according to the usual convention:
windings horizontally adjacent to cores are wound around those cores, at least in part. In this case NP turns of the
ratio winding rope are wound around the top core only then another NP turns are wound around both cores. The
bootstrapping voltage induced in the ratio winding is the same as before. Ratio accuracy is also maintained as the
secondary winding is part of the same rope as the primary and shares the same flux.
RS + R1
V1 I1
NP
Ratio winding
VOUT
NP Φ1 Φ2 NV
Secondary
I2 Z
V2 NP winding
Fig. 4.4.1 Extra turns around the top (ratio) core
V1  I1R1  s2 N P1  N P2  V2  I 2 R2  sNP2 etc.
Note that the extra factor of two is because of the extra turns around the top core. The expressions for V2 and V3
remain unaltered. Similarly, for ideal magnetic circuits, the magneto-motive force in the top core is also doubled so
that the fluxes are: -
1  2 N P I1 AL1 2  N P I1  N P I 2 AL 2
From the above: 

V1  I1R1  s 4 N P2 I1 AL1  N P2 I1 AL 2  N P2 I 2 AL 2 
Previously I defined the winding inductances: L1  N P2 AL1 and L2  N P2 AL 2
Then: V1  I1 R1  4sL1  sL2   I 2 sL2 etc
The rest of the analysis is exactly the same as before (see sections 1, 2 and 3) but with the
transformation: L1  4L1 . One may as well retain the formulae for the transfer function and input impedances and
calculate the inductance L1 with twice the number of turns (i.e. the actual number of turns around the top core): -
L1  2 N P  AL1
2
A further factor of two can be had by using a higher (SM200) permeability top core: -
L1  8L2
The extra turns also increase the winding resistance by approximately 50%: R1  3  R2
22
Part 3: Monograph 3
If one incorporate these changes (SM200 top core with extra turns) into the previous example the result is: -
Winding inductances: L1  128H and L2  16 H

 1

The increase in L1 by a factor of 8 reduces the natural frequency by the factor of two  8 3 
 
 
Ratio (primary) winding resistance also increases R1  3  R2  : R1  6.9
With three values of source resistance: RS  1 , RS  10 and RS  100
Compensator resistance for worst case source resistance RS  100 : RC  RS  100
To give the compensator a reasonable chance to restore the bootstrap effect at operating frequency (typically 25Hz)
the large parallel capacitor needs to be about the same as the compensator resistance at about 1Hz: -
1
 100 at f  1Hz  C  1.6mF
2fC
With a spreadsheet model (with sliders) the results exhibit an increasing natural frequency with a small resonant
peak for the worst case (RS = 100Ω). Increasing the compensator capacitance reduces ratio errors but increases the
size of the resonant peak.
Fig. 4.4.1.1 Frequency response with 1, 10 and 100Ω source resistance [1]
1. Spreadsheet: “Two-stage with compensator MK1”.
23
As expected the quadrature error is small and third order with respect to frequency. In-phase error is second order
(eventually) and also reduced because of the lower natural frequency.
2 3
f  f 
f  f N  T s   1    N   j N 
 f   f 
Real (blue) and imaginary (green)
Fig.4.4.1.2 Ratio errors with a compensator (100Ω and 1.6mF) and 100Ω source resistance.
24
Part 3: Monograph 3
5. Loading effects
Whereas the main ratio secondary is seldom required to deliver current to a load it is frequently the case that a
strand of the ratio winding is used to “equalise” the voltage of the next decade. This is often required because the
next decade is formed on a separate rope or even a separate transformer or IVD. Similarly, the energising core,
having the great majority of the flux, can be used, by means of a secondary winding, to drive the energising
winding of a subsequent two-stage IVD or transformer. The load, reflected back to the primary windings, results in
a small increase in current as shown in the case of single stage transformers [1]. The worst case is, not surprisingly,
when there is a large source resistance and corresponding stability compensator (active drive of energising winding
only). The analysis is much more complicated than for a single stage IVD/transformer but the algebraic approach is
worth it. The general principles revealed can also be applied to more complex systems (e.g. three-stage RTs)
without the need for detailed computer simulation.
5.1 Loading the energising core
In a typical application the third and fourth decades are obtained with a separate transformer or IVD. The second
energising core (decades 3 & 4) is powered by a secondary winding on the first energising core (decades 1 & 2).
I1 RS Decades 1 & 2 Decades 3 & 4
V1 NP Φ1 Φ2 VOUT
I3
I2 Z2
V2 NP NS ZL
Fig. 5.1.1 The first energising core supplies a second energising core
5.1.1 The effect on energising accuracy of loading the energising secondary
Whereas decades 3 & 4 are less critical than decades 1 & 2 it is still important that the energising secondary output
voltage should be accurate (typically the input voltage divided by 100). The source impedance of the secondary,
consisting of the winding resistance, R3, and, most likely, the source resistance and/or the compensator impedance
reflected to the secondary, must be kept very low compared to the load impedance (i.e. decades 3 & 4 energising
winding inductance). The best method for analysing the effect is to imagine applying a third voltage to the
secondary which then requires a 3 3 matrix description.
I1 RS
NP Φ1 Φ2
V1
R3 I3
I2 Z2
V2 NP NS V3
Fig. 5.1.1.1 Circuit model for analysing loading on the energising secondary
1. Part 3, monograph 2: “Single-stage IVD and RTs”. See sections 4.4 and 4.5.
25
V1  I1RS  sNP 1  2  V2  I 2 Z 2  sNP2 V3  I 3 R3  sNS  2
For ideal magnetic circuits the fluxes are: 1  N P I1 AL1 and 2  N P I1  N P I 2  N S I3 AL 2
From the above: 

V1  I1RS  s N P2 I1 AL1  N P2 I1 AL 2  N P2 I 2 AL 2  N P N S I3 AL 2 

V2  I 2 Z 2  s N P2 I1 AL 2  N P2 I 2 AL 2  N P N S I3 AL 2 

V3  I3 R3  s N S N P I1 AL 2  N S N P I 2 AL 2  N S2 I3 AL 2 
Define winding inductances: L1  N P2 AL1 and L2  N P2 AL 2
Then: V1  I1 RS  sL1  sL2   I 2 sL2  I 3

NS
sL2
NP
V2  I1sL2  I 2 Z 2  sL2   I 3
NS
sL2
NP
2
N N N 
V3  I1 S sL2  I 2 S sL2  I 3  S  sL2  I 3 R3
NP NP  NP 
Define a parameter (ratio of primary to secondary) to simplify the algebra   N S N P . In vector-matrix
notation: V  ZI : -
 V1   RS  sL1  L2  sL2 sL2  I1 
    
V2    sL2 Z 2  sL2 sL2  I 2 
V   sL2 sL2 R3   2 sL2  I 3 
 3 
The inverse is: I  Z 1V which one can calculate using Cramer’s rule (see appendix 3) but first the determinant: -
 
Z  RS  sL1  sL2  Z 2  sL2  R3   2 sL2   2 s 2 L22  
 sL  s L  sL R   sL 
2
2 2 2
2 2 3
2
2
 sL s L  Z  sL sL 

2
2 2
2 2 2 2
Tackle in three parts and re-arrange into powers of s in order to identify terms which may cancel: -
  
Z  Z 2 R3 RS  s Z 2 R3 L1  L2   L2 R3 RS  RS Z 2  2 L2  s 2 L2 R3 L1  L2   Z 2  2 L2 L1  L2  
 s 2 L22 R3
 Z 2  2 s 2 L22
Z  Z2 R3 RS  sZ2 R3 L1  L2   L2 R3 RS  RS Z2  2 L2  s 2 L1L2 R3  Z2  2 L1L2 
Y
Define Y such that: Y  Z Z 1 so that I  V
Z
26
Part 3: Monograph 3
If one assumes ideal followers (V1 = V2) then the current in the secondary is: I 3 
1
Y13V1  Y23V1  Y33V3 
Z
From Cramer’s rule (see appendix 3) the relevant components of Y can be calculated. The matrix is repeated for
convenience: -
 RS  sL1  L2  sL2 sL2 
 
Z sL2 Z 2  sL2 sL2 
 sL2 sL2 R3   2 sL2 

Y13  Z12Z 23  Z13Z 22   s 2 L22  sL2 Z 2  sL2   Z 2 sL2
Y23  Z13Z 21  Z11Z 23   s 2 L22  RS  sL1  sL2 sL2  RS  sL1 sL2
Y33  Z11Z 22  Z12Z 21   RS  sL1  sL2 Z 2  sL2   s 2 L22
 I3 
1
Z
 
RS  sL1  sL2 Z2  sL2   s 2 L22 V3  Z2 sL2  RS  sL1 sL2 V1 
If one holds V1 constant then the input admittance of the secondary is the (partial) derivative: -
I 3 RS  sL1  sL2 Z 2  sL2   s 2 L22


V3 Z
The reciprocal of the admittance is the input impedance as seen from the source V3. With a little algebra: -
Z3 
  
Z 2 R3 RS  s Z 2 R3 L1  L2   L2 R3 RS  RS Z 2  2 L2  s 2 L1L2 R3  Z 2  2 L1L2 
RS Z 2  sL2 RS  Z 2 L1  L2   s 2 L1L2
At sufficiently low frequency this is simply the winding resistance of the secondary: -
Z 2 RS
s 2   Z3  R3
L1L2
At sufficiently high frequency it is the winding resistance of the secondary plus the source impedance in series with
the energising winding, reduced by the turns ratio squared: -
Z 2 RS
s 2   Z3  R3   2 Z 2
L1L2
It is a useful check that one can arrive at the same result in a different way. If one imagines a load connected to the
secondary (for which one can think in terms of output impedance, ZOUT) one has the following model: -
ZOUT I3
Unloaded
ZL VL Loaded
Output VU
Output
Fig. 5.1.1.2 Circuit model for output impedance
27
From above, the loaded output voltage is (note the direction the current was defined), assuming ideal voltage
followers (V1 = V2): -
Z L Y13  Y23 
I3 
1
Y13V1  Y23V1  Y33V3  and ZL  
I3
 V3  VL   V1
Z V3 Z  Z LY33
If the load impedance is infinite the result is the unloaded output: Z L    V3  VU  

Y13  Y23 V
1
Y33
The effect of loading due to the secondary output impedance is: -
VL ZL V  Z
  Z OUT  Z L  U  1  Z OUT 
VU Z OUT  Z L  VL  Y33
1 I 3 Y33
This agrees with the result from the previous method (for admittance):   QED.
ZOUT V3 Z
One can conclude that the first energising core (decades 1 & 2) and its windings behave, at high frequency, very
much like a single stage transformer with a load. The compensator impedance reflects to the output, reduced by the
turns ratio squared, in series with the secondary resistance. The main source resistance (in series with the ratio
winding) has a negligible contribution. This makes sense since most of the flux is in the energising core.
In a typical application the secondary voltage is one hundredth the primary and the reflected load in parallel with
the first energising winding inductance is, therefore, 104 times the load impedance. As the load impedance, and its
reflection, is substantially inductive (with a small series resistance) and usually of the same order of magnitude the
effect is equivalent to a small reduction (typically < 0.01%) in the first energising winding inductance, L2 [1].
Similarly, the source impedance (substantially Z2) reflected to the secondary output [2] is reduced by a factor of 104
(Z2 drops from a maximum of typically100Ω at low frequency to the winding resistance, R2, at high frequency) and
its contribution to the output impedance is negligible. Decade 3 & 4 IVD can be analysed, therefore, as if the
energising winding were driven by a follower (i.e. very low source impedance). As the energising winding usually
has a small number of turns (2, 3 or 4 at most) it is usually sufficient to only use the same gauge of wire as the
subsequent energising primary.
The effect on the ratio primary input impedance/current and transformer accuracy is less obvious as the following
demonstrates: -
5.1.2 Loading the energising core and its effect on ratio accuracy
If one adds a ratio secondary with the same number of turns as the primary (ratio 1:1) then the output is the input
minus the voltage developed across the source resistance due to the current into the ratio primary. The transfer
function is, therefore: -
VOUT  VIN  I1RS and I1 

1
Y11V1  Y21V1  Y31V3   TL s   1  RS Y11  Y21   R3 V3 Y31
Z Z Z VIN
V3 Z Y  Y 
From the previous section:   L 13 23
VIN Z  Z LY33
The complete transfer function is, therefore: TL s   1 

RS
Y11  Y21  RS Z L Y13  Y23  Y31
Z Z Z  Z LY33
1. Part 3, monograph 2: “Single stage IVDs and RTs”. See section 4.3.
2. Ibid section 4.4.
28
Part 3: Monograph 3
From Cramer’s method (see appendix 3): -
 
Y11  Y21  Z 2 R3   2 sL1  L2    2 s 2 L1L2
Y31  s L  Z 2  sL2 sL1  L2 
2 2
2
Y13  Y23   sL2 Z 2  RS  sL1 

Y33  RS  sL1  sL2 Z 2  sL2   s 2 L22
Z  Z2 R3 RS  sZ2 R3 L1  L2   L2 R3 RS  RS Z2  2 L2  s 2 L1L2 R3  Z2  2 L1L2 
It is useful to check against the previous result in the case with no load: -
  0  Y31  0  TU s   1  Y11  Y21 

RS
Z
Also Y11  Y21  Z 2 R3 and Z  Z2 R3 RS  sZ2 R3 L1  L2   L2 R3 RS   s 2 L1L2 R3
TU s   1 
RS Z 2 R3
Z
 TU s   1 
RS Z 2
Z 2 RS  sZ 2 L1  L2   L2 RS   s 2 L1L2 
This is the same as the result obtained for the basic two-stage transformer (without source resistance and
compensator: see section 3, page 8) if one makes the substitutions: -
sR2 L1  R2 L2  R1L2   s 2 L1L2
Z 2  R2 and RS  R1 then T s  
R1R2  sR2 L1  R2 L2  R1L2   s 2 L1L2
Apart from the term Z 2 R3 contributions from Y11  Y21 and Y13  Y23 Y31 include factors  2 s and  2 s 2 .
At high frequency, therefore, the terms in s2 dominate so that, to a good approximation: -
Y11  Y21  Z 2 R3   2 s 2 L1L2 Y31  s 2 L1L2 Y13  Y23   s 2 L1L2 Y33  s 2 L1L2 Z  s 2 L1L2 R3  Z2  2 L1L2 
N.B. The contribution from Z 2 R3 depends on the value of  2 as well as frequency.
One can now substitute these into the full expression. At high frequency, to a good approximation: -
From above: TL s   1 
RS
Y11  Y21  RS Z L Y13  Y23  Y31
Z Z Z  Z LY33
Z 2 RS R Z L s 2 L1L2
 TL s   1 
RS Z 2 R3 RS 2 2
s 2    s L1L2  S s 2 L1L2
L1L2 Z Z Z Z  Z L s L1L2
2
The first two terms are the unloaded transfer function and the rest of the expression (keeping the symbol for Z for
the time being) simplifies nicely: -
 Z L s 2 L1L2 
TL s   TU s  
RS 2 2
 s L1L2 1 
Z  Z  Z L s 2 L1L2 
The expression in brackets simplifies further: -
Z
TL s   TU s  
RS 2 2
 s L1L2
Z Z  Z L s 2 L1L2
29
The determinant and factor s 2 L1L2 now cancel to obtain: -
TL s   TU   2
RS
R3   2 Z 2  Z L
The denominator is simply the total load impedance, including the actual load plus the winding resistance in series
with the source impedance (to the energising winding) reflected from the primary. In practice the former is much
larger than the latter two and one finds the final form: -
TL s   TU s    2
RS
ZL
One can interpret this as either reflected source impedance reduced or reflected load impedance increased by a
factor of the turns ratio squared.
The effect is reflection to/from the ratio primary as well as the energising primary. Fortunately, in practice,
the load impedance is likely to be mostly inductive and the error, therefore, mostly quadrature. It is
important, however, not to have a resistive load.
5.2 Loading the ratio secondary
Taking current from the ratio secondary is also a little more complicated and can result in significant ratio errors,
especially with high source resistance. The best method for analysing the effect is again (the same as loading the
energising core) to imagine applying a third voltage to the ratio secondary.
I1 RS R3 I3
NP Φ1 Φ2
V1 NS V3
I2 Z2
V2 NP
Fig. 5.2.1 Circuit model for analysing loading on the ratio secondary
V1  I1RS  sNP 1  2  V2  I 2 Z 2  sNP2 V3  I3 R3  sNS 1  2 
For ideal magnetic circuits the fluxes are: -
1  N P I1  N S I 3 AL1 2  N P I1  N P I 2  N S I3 AL 2
From the above: 

V1  I1RS  s N P2 I1 AL1  N P N S I3 AL1  N P2 I1 AL 2  N P2 I 2 AL 2  N P N S I3 AL 2 

V2  I 2 Z 2  s N P2 I1 AL 2  N P2 I 2 AL 2  N P N S I3 AL 2 

V3  I3 R3  s N S N P I1 AL1  N S2 I3 AL1  N S N P I1 AL 2  N S N P I 2 AL 2  N S2 I3 AL 2 
30
Part 3: Monograph 3
Define winding inductances: L1  N P2 AL1 and L2  N P2 AL 2
Then: V1  I1 RS  sL1  sL2   I 2 sL2  I 3 sL1  sL2 

NS
NP
V2  I1sL2  I 2 Z 2  sL2   I 3 S sL2

N
NP
2
N 
V3  I1 S sL1  sL2   I 2 S sL2  I 3  S  sL1  sL2   I 3 R3
N N
NP NP  NP 
NS
Define parameter (ratio of primary to secondary) to simplify the algebra   .
NP
In vector-matrix notation: V  ZI : -
 V1   RS  sL1  L2  sL2 sL1  L2   I1 

    
V2    sL2 Z 2  sL2 sL2  I 2 
 V   sL  L  sL2 R3   sL1  L2  I 3 
2
 3  1 2
The inverse is: I  Z 1V which can be calculated using Cramer’s rule (see appendix 3) but first the determinant: -
 
Z  RS  sL1  L2  Z 2  sL2  R3   2 sL1  L2    2 s 2 L22  
 
 sL2  2 s 2 L2 L1  L2   sL2 R3   2 sL1  L2  

 sL1  L2  s 2 L22  Z 2  sL2 sL1  L2  
Tackle in three parts and re-arrange into powers of s in order to identify terms which may cancel. Note that for the
first line there should be (2 × 2 × 2) + 2= 10 terms: -
Z  RS Z 2 R3

 s RS R3 L2  Z 2 R3 L1  L2   RS Z 2  2 L1  L2  

 s 2 L2 R3 L1  L2   L2 RS  2 L1  L2   Z 2  2 L1  L2   RS  2 L22
2

 s  L L  L    L L  L 
3 2 2 2 2
2 1 2 2 1 2
 s 2 R3 L22
 
 s 2 Z 2  2 L1  L2 
2
 s  L L  L   L  L  L  
3 2 2 2 2
2 1 2 2 1 2
There is some cancellation, including, as if by magic, all four terms in s3: -
Z  RS R3Z2  sL1  L2 R3Z2  RS R3 L2  RS  2 Z2 L1  L2  s 2 R3 L1L2  RS  2 L2 L1
If one assumes ideal followers (V1 = V2) then the current in the secondary is: I 3 
1
Y13V1  Y23V1  Y33V3 
Z
31
From Cramer’s rule the relevant components of Y are (see appendix 3): -
 RS  sL1  L2  sL2 sL1  L2  

 
Z sL2 Z 2  sL2 sL2 
 sL  L  sL2 R3   sL1  L2 
2
 1 2
Y13  Z12Z 23  Z13Z 22   s 2 L22   sL1  sL2 Z 2  sL2 

Y23  Z13Z 21  Z11Z 23   s 2 L1  L2 L2  sL2 RS  sL1  sL2    sL2 RS
Y33  Z11Z 22  Z12Z 21   RS  sL1  sL2 Z 2  sL2   s 2 L22
 I3 
1
Z
   
 RS  sL1  sL2 Z 2  sL2   s 2 L22 V3   sL1  sL2 Z 2  sL2   sL2 RS  s 2 L22 V1
If the voltage applied to the secondary is such that the current is zero, then one can check if the result is consistent
with previous analysis: -
I3  0 
V3 Y Y
  13 23 
V3 sL  sL2 Z 2  sL2   sL2 RS  s 2 L22
 1
V1 Y33 V1 RS  sL1  sL2 Z 2  sL2   s 2 L22
This is the same as the result obtained for the basic two-stage transformer (without source resistance and
compensator: see section 3, page 8) if one makes the substitutions: -
V3 sL2 R1  L1R2  L2 R2   s 2 L1L2

Z 2  R2 and RS  R1  
V1 R1R2  sL2 R1  L1R2  L2 R2   s 2 L1L2
If one holds the input voltages (V1 = V2) constant then the admittance of the secondary is the (partial) derivative: -
I 3 Y33 RS  sL1  sL2 Z 2  sL2   s 2 L22

 
V3 Z Z
The reciprocal of this is the impedance of the secondary, including that reflected from the ratio primary and
energising windings: -
Z
ZOUT 
RS  sL1  sL2 Z 2  sL2   s 2 L22
The result is rather complicated but the main features are evident.
ZOUT 
  
RS R3Z 2  s L1  L2 R3Z 2  RS R3 L2  RS  2 Z 2 L1  L2   s 2 R3 L1L2  RS  2 L2 L1 
RS Z 2  sRS L2  Z 2 L1  L2   s 2 L1L2
At sufficiently low frequency this is simply the winding resistance of the secondary: -
In the limit: s  0  ZOUT  R3
At sufficiently high frequency the output impedance simplifies to: -
RS Z 2
s   and typically s 2   ZOUT  R3   2 RS
L1L2
32
Part 3: Monograph 3
As with a single stage transformer the source resistance in series with the ratio primary is reflected to the output by
the square of the ratio. The stability compensator in series with the energising winding has a much reduced effect.
As in the previous section one can deduce the transfer function (with load): -
Z L Y13  Y23 
I3 
1
Y13V1  Y23V1  Y33V3  and I3  
V3
 V3  VL   V1
Z ZL Z  Z LY33
If the load impedance is infinite the result is the unloaded output: Z L    V3  VU  

Y13  Y23 V
1
Y33
This is the same as the condition I 3  0 as in the previous section.
It is again useful to confirm the previous result by a different method. The effect of loading due to the secondary
output impedance is: -
VL ZL V  Z
  Z OUT  Z L  U  1  Z OUT 
VU Z OUT  Z L  VL  Y33
1 I 3 Y33
This agrees with the result from the previous method (for admittance):   QED.
ZOUT V3 Z
As an extra check one can imagine the result in the limit that the energising current is zero.
In the limit Z 2   then Z OUT 


RS R3  s L1  L2 R3  RS  2 L1  L2  
RS  sL1  L2 
In the limit s  0 the result is the resistance of the secondary  ZOUT  R3
In the limit s   the result is the resistance plus the source resistance reflected from the primary: -
ZOUT  R3  RS  2
This is exactly what one would expect for a single stage transformer (i.e. without the energising winding).
Z Y  Y 
TL s  
VL
The loaded transfer function is, from above:   L 13 23
V1 Z  Z LY33
The difference between the loaded and the unloaded transfer function represents the error due only to the loading
effect: -
Y13  Y23 Z L Y13  Y23  Y  Y Z Y  Y 
TL s   TU s     TL s   TU s   13 23  L 13 23
Y33 Z  Z LY33 Y33 Z  Z LY33
Y13  Y23  Z LY33  Y13  Y23  Z 

 TL s   TU s   1   T s   T s   
Y33  Z  Z LY33  Y33  Z  Z LY33 
L U
 Z 
Finally: TL s   TU s 1  

 Z  Z Y
L 33 
33
Z
The factor in brackets includes the error due to loading only: EL s  
Z  Z LY33
As above, at a sufficiently high frequency, the relevant determinant and matrix element are, to a sufficiently good
approximation: -
Z  s 2 R3 L1L2  RS  2 L2 L1 Y33  s 2 L1L2
A factor of s 2 L1L2 cancels to give: -
Z R3   2 RS ZOUT
 
Z  Z LY33 Z L  R3   RS Z L  ZOUT
2
TL s  Z OUT
This confirms the previous results with: 1
TU s  Z L  ZOUT
With a load across the full secondary of, for example, a 1:1 transformer the load impedance must be very large
indeed if high accuracy is required. Even with a 10:1 reduction it is not possible to use an extra strand, for
example, to drive a subsequent energising winding.
Fortunately it is possible to fit two decades on the first transformer. With a reduction of 100:1 it is possible to
employ a decade 2 ratio secondary strand to supply the ratio primary (bootstrapped) of the third decade IVD [1].
It is also possible to use a 10:1 extra strand, with a sufficiently large auxiliary inductive load, to “equalise” a small
mismatch between the first and second decade rope windings as the next section describes.
A second or subsequent decade can be “equalised” to the first decade in exactly the same way as with single-stage
IVDs and RTs [2]. The loading effect on the ratio secondary is the same as for a single-stage transformer and so the
analysis is exactly the same. This is often represented, employing the usual convention for a two-stage design, as
follows: -
Decade 1
I1 RS extra strand
V1 NP Φ1 Φ2 Φ3 Decade 2
I2 Z2
V2 NP Auxiliary core
Fig. 6.1 Equalising voltages between the first and second decade
1. Part 3, Monograph 7: “An F18 type ratio transformer bridge”. See section 3.
2. Part 3, monograph 2: “Single-stage IVDs and RTs”. See section 6.
34
Part 3: Monograph 3
A useful variant is to supply the energising current from the output side. The input is fully differential and the input
impedance remains boosted but the output is relative to local 0V. A typical application is to provide the reference
input to an R-2R multiplying DAC for the last three decades of a resistance bridge. The input is derived from high
accuracy voltage followers [1]. In this case the source resistance is very low and stability is satisfactory with a
simple voltage follower driving the energising winding directly. The voltage follower needs very good DC
performance (low DC current through the low resistance of the energising winding) and a reasonably good gain-
bandwidth product (e.g. OP-27 or equivalent). A composite op-amp with matched pair front end would be even
better. With higher source resistance (e.g. a noise matching transformer) the current must be supplied through a
compensator [2].
I1 R1 Good DC op-amp
VOUT
VIN NP Φ1 Φ2
NS
R2 I2
Energising
NS winding
0V
Fig. 7.1 Energising drive from the secondary (low source resistance)
The equivalent circuit is the same as an actively driven two-stage high-pass filter and one can obtain the transfer
function by changing the capacitors into resistors and resistors into inductors [3]: -
X1  R1 and R1  sL1 etc.
R1 I1 U1
V1
VOUT
L1
R2 I2
L2
0V
0V
Fig. 7.2 The equivalent circuit
The transfer function becomes: T s  

L1R2  L2 R2 s  s 2 L1L2
R1R2  L1R2  L2 R2 s  s 2 L1L2
A useful parameter is the determinant: Z  R1R2  sL2 R1  L1  L2 R2   s 2 L1L2
1. Part 3, monograph 7: “An F18 type ratio transformer bridge”.

35
Divide top and bottom by R1R2 and it is easy to see that the normalised transfer function s  j  N  is: -
as  s 2  L1  L2 
T s  
R1 R2
with natural frequency: N  and a    N
1  as  s 2 L1 L2  R1 
Parameter a has one less component compared to the case of energising from the input side (see section 4.2). With
the same transformer (winding inductances and resistances are the same) the value of a is always lower and the
stability margin is reduced slightly. The error analysis is the same: -
s  1  T s   1 
1 a

s 2 s3
In the more convenient form, with frequency in Hz: -
2 3
f  f 
 T  f   1   N   ja  N 
1 R1 R2
f  f N with fN 
 f   f  2 L1 L2
The phase error (quadrature) is third order with respect to frequency and sufficiently low for most applications. The
in-phase error is second order and acceptable for some applications.
A compact transformer with sufficient accuracy for the last three decades of a low frequency (25Hz) resistance
bridge can be constructed with a pair of low cost 5c mumetal cores (μR ≈ 50,000). All three windings are 200 turns
BNNL of 0.457mm enamelled copper wire (26SWG).
Both cores type 5c (see appendix 1): -

Inner circumference = 23mm × π = 72mm can accommodate 200 turns in two layers of 0.72mm OD wire.
Outer circumference = 41mm × π = 129mm can accommodate 200 turns of 0.64mm OD in a single layer.
The outer circumference is the limiting dimension: A comfortable fit is 26SWG (enamelled) at 0.457mm diameter
with a resistance of 105mΩm-1.
The energising winding requires: 200  48mm  9.6m of wire.

Resistance R2 would be approx: R2  9.6m  105mm1  1
Permittance of both cores: AL  51H turn2
Inductance of both windings: L1  L2  N 2 AL  200  200  51 106  2H
The ratio windings consist of 200 turns of a twisted pair around both cores (BNNL) of the same wire.
The inner diameter is reduced slightly but the twisted pair is still a comfortable fit with two layers on the inner
circumference and a single layer on the outer.
36
Part 3: Monograph 3
As a ball park estimate the length of wire, for the ratio winding, is roughly twice that of the energising winding,
partly because it is wound around both cores and partly because the strands are twisted into a rope.
R1  2R2  2
1 R1R2  L  L2 
Natural frequency: fN   0.11Hz and a   1 N  1.4
2 L1L2  R1 
2 3
f  f 
The error analysis is the same: T  f   1   N   ja  N   1  19  10 6  j 0.12  10 6
 f   f 
The resulting frequency response has a slight peak close to the natural frequency [1]: -
Fig. 7.1.1 Bode plot
The real (in-phase: blue) and imaginary (quadrature: green) errors are second and third order, respectively: -
Fig. 7.1.2 Real (blue) and imaginary (green) error components
1. Spreadsheet: “Two-stage energised from output”.
37
VMAX/turn/Hz
Axial code
Core axial
Case axial
Circ./turn
Core OD
Case OD
Core ID
Case ID
Type
AL
LE AE
μH/turn2
0 a 18 11 5 18 16 13 3.2 45 5 14 1.6E-05
b 18 11 8 24 16 13 6.4 45 10 28 3.2E-05
1 a 21 11 5 21 19 13 3.2 50 10 26 3.2E-05
b 21 11 7 24 19 13 4.8 50 15 38 4.8E-05
c 21 11 8 27 19 13 6.4 50 20 51 6.4E-05
2 a 24 12 7 26 22 14 4.8 57 19 41 5.9E-05
b 24 12 8 29 22 14 6.4 57 25 55 7.9E-05
c 24 12 10 32 22 14 7.9 57 31 69 9.9E-05
3 a 31 17 7 29 29 19 4.8 75 23 38 7.1E-05
b 31 17 9 32 29 19 6.4 75 30 51 9.5E-05
c 31 17 10 36 29 19 7.9 75 38 63 1.2E-04
4 a 36 20 9 34 33 22 6.4 87 35 51 1.1E-04
b 36 20 10 37 33 22 7.9 87 44 63 1.4E-04
c 36 20 12 40 33 22 9.5 87 53 76 1.7E-04
5 a 41 23 9 36 38 25 6.4 100 40 51 1.3E-04
b 41 23 12 42 38 25 9.5 100 60 76 1.9E-04
c 41 23 15 48 38 25 12.7 100 81 102 2.5E-04
6 a 50 29 7 36 48 32 4.8 125 38 38 1.2E-04
b 50 29 10 42 48 32 7.9 125 63 63 2.0E-04
c 50 29 12 45 48 32 9.5 125 75 76 2.4E-04
d 50 29 15 52 48 32 12.7 125 100 101 3.2E-04
7 a 60 36 7 38 57 38 4.8 150 45 38 1.4E-04
b 60 36 12 48 57 38 9.5 150 91 76 2.9E-04
c 60 36 15 54 57 38 12.7 150 121 102 3.8E-04
8 a 69 42 10 48 67 45 7.9 174 88 64 2.8E-04
b 69 42 14 54 67 45 11.1 174 123 89 3.9E-04
c 69 42 17 61 67 45 14.3 174 159 115 5.0E-04
9 a 79 49 14 58 76 51 11.1 200 141 89 4.4E-04
b 79 49 17 64 76 51 14.3 200 182 114 5.7E-04
c 79 49 15 61 76 51 12.7 200 161 101 5.1E-04
10 a 90 54 15 65 86 57 11.1 224 158 89 5.0E-04
b 90 54 18 72 86 57 14.3 224 204 114 6.4E-04
c 90 54 23 81 86 57 19.1 224 272 153 8.6E-04
11 a 112 66 16 78 108 70 12.7 279 242 109 7.6E-04
b 112 66 19 85 108 70 15.9 279 303 136 9.5E-04
c 112 66 23 91 108 70 19.1 279 364 164 1.1E-03
12 a 132 78 18 90 127 83 14.3 329 317 121 1.0E-03
b 132 78 23 100 127 83 19.1 329 424 162 1.3E-03
c 132 78 29 112 127 83 25.4 329 564 215 1.8E-03
13 a 164 110 18 90 159 114 14.3 429 322 94 1.0E-03
b 164 110 23 100 159 114 19.1 429 430 126 1.4E-03
c 164 110 29 112 159 114 25.4 429 572 167 1.8E-03
14 a 28 17 6 23 25 19 3.2 70 10 18 3.1E-05
b 28 17 9 29 25 19 6.4 70 20 36 6.3E-05
Notes: -
1. All dimensions in mm or mm2
2. AL Assumes μR=100,000.
3. VMAX for sinusoidal peak flux density of 0.5T, one turn at 1Hz
38
Part 3: Monograph 3
Copper wire data
Imperial standard wire gauge (SWG)
No. 16 18 20 22 24 26 28
Diameter
1.626 1.219 0.914 0.711 0.559 0.457 0.376
(mm)
mΩm-1 8.3 14.8 26.0 43.5 70.5 105 155
No. 30 32 34 36 38 40
Diameter
0.315 0.274 0.234 0.193 0.152 0.122
(mm)
mΩm-1 222 293 404 590 950 1480
Metric wire data
Diameter
50 63 80 100 125 160 200 250 315 400 500
(µm)
Ωm-1 8.78 5.53 3.43 2.20 1.41 0.86 0.55 0.35 0.22 0.137 0.088
39
Appendix 2: Detailed equation bashing (see section 4.3): -
sR2 L1  R2 L2  R1L2   s 2 L1L2

The original transfer function is: T s  
R2 RS  R1   sR2 L1  R2 L2  R1L2   s 2 L1L2
R  R2  sR2 RC
I shall make the substitution: R2  Z 
1  sRC
R  R2  sR2 RC R  R2  sR2 RC
sL1  sL2  R1sL2  s 2 L1L2
T s   1  sRC 1  sRC
R  R2 RS  R1   sR2 RC RS  R1   R  R2  sR2 RC sL  R  R2  sR2 RC sL  R sL  s 2 L L
1  sRC 1  sRC 1  sRC
1 2 1 2 1 2
Multiply top and bottom by (1+sRC): -

R  R2  sR2 RC R  R2  sR2 RC
sL1  sL2  R1sL2 1  sRC   sL1sL2 1  sRC 
T s  
   
R  R2 RS  R1   sR2 RC RS  R1   R  R2  sR2 RC sL  R  R2  sR2 RC sL  R sL 1  sRC   sL sL 1  sRC 
  1
 2 1 2 1 2
Sort into powers of s noting the extra term in the denominator (in square brackets): -
T s  
R  R2 L1  L2   R1L2 s  R2 RC L1  L2   R1L2 RC  L1L2 s 2  L1L2 RCs 3
R  R2 RS  R1   R2 RC RS  R1 s  R  R2 L1  L2   R1L2 s  R2 RC L1  L2   R1L2 RC  L1L2 s 2  L1L2 RCs 3
Divide top and bottom by R  R2 RS  R1  then it is clear that, in normalised form, in which I shall anticipate that δ can be made small compared to a: -
1
as  bs  s
2 3
 R  R2 RS  R1   3 R  R2 L1  L2   R1L2  b  R2 RC L1  L2   R1L2 RC  L1L2   2
T s    N    a
1  a   s  bs 2  s 3 R  R2 RS  R1  R  R2 RS  R1 
N N
 RCL L
1 2 
R2 RC
 
R  R2  N
40
Part 3: Monograph 3
Appendix 3: the inverse of a 3 × 3 matrix
Z j 
Given Vi  Z ij I j then I j  where Z j  = the Z matrix with the jth column replaced by Vi .
Z
The determinant is moved to the left hand side for simplicity: -
For I1 the Vi go in the first column: -
V1 Z12 Z13
Z I1  V2 Z 22 Z 23  V1 Z 22Z 33  Z 23Z 32   Z12 Z 23V3  V2 Z 33   Z13 V2 Z 32  Z 22V3 
V3 Z 32 Z 33
 Z 22Z 33  Z 23Z 32 V1  Z13Z 32  Z12Z 33 V2  Z12Z 23  Z13Z 22 V3
 Y11V1  Y12V2  Y13V3
Second column: -
Z11 V1 Z13
Z I 2  Z 21 V2 Z 23  Z11V2 Z 33  Z 23V3   V1 Z 23Z 31  Z 21Z 33   Z13 Z 21V3  V2 Z 31 
Z 31 V3 Z 33
 Y21V1  Y22V2  Y23V3
Third column: -
Z11 Z12 V1
Z I 3  Z 21 Z 22 V2  Z11Z 22V3  V2 Z 32   Z12 V2 Z 31  Z 21V3   V1 Z 21Z 32  Z 22Z 31 
Z 31 Z 32 V3
 Y31V1  Y32V2  Y33V3
First row: - Second row: - Third row: -

Y11  Z 22Z 33  Z 23Z 32  Y21  Z 23Z13  Z 21Z 33  Y31  Z 21Z 32  Z 22Z 31 
Y12  Z13Z 32  Z12Z 33  Y22  Z11Z 33  Z13Z 31  Y32  Z12Z 31  Z11Z 32 
Y13  Z12Z 23  Z13Z 22  Y23  Z13Z 21  Z11Z 23  Y33  Z11Z 22  Z12Z 21 
The determinant is: -
Z11 Z12 Z13

Z  Z 21 Z 22 Z 23  Z11Z 22Z 33  Z 21Z 32   Z12 Z 23Z 31  Z 21Z 33   Z13 Z 21Z 32  Z 22Z 31 
Z 31 Z 32 Z 33
41
Part 3: Monograph 4
Three-stage ratio transformers

1. Introduction
The in-phase accuracy of a two-stage ratio transformer is not quite sufficient for the first decade of a low
frequency bridge. With the addition of a second energising core and winding, however, something wonderful
happens. The input impedance of the ratio winding is boosted further so that it can be connected directly to a
transfer standard resistor with negligible error. Also, the in-phase ratio accuracy (from primary to secondary)
becomes fourth order with respect to frequency and high accuracy can be achieved at half power supply frequency
(25 or 30Hz). The transformer requires fewer turns and the result is an elegant overall bridge design.
Ratio winding I1 R1
V1 Φ1 Φ2 Φ3
NP NS VOUT
I2 R2 Secondary
V2 NP
winding
Energising (NS turns)
windings
I3 R3
V3 NP
Fig. 1.1 A basic three-stage ratio transformer
Analysis of the three-stage transformer network reveals the same structure as the three-stage high-pass filter. For a
1:1 transformer the equivalent circuit is: -
R1 I1
V1 U1
L1
R2 I2
V2 U2
L2
R3 I3
V3 U3
L3
0V
Fig. 1.2 The equivalent circuit for a three stage voltage transformer
One can re-use the matrix analysis from the monograph “Three-stage filters” [1] with symbol substitutions: -
R1  sL1 etc X 1  R1 etc
1. Part 2, monograph 2: “Three-stage filters”. See appendices 1, 2 and 3.
1
High accuracy electronics
The input impedance matrix equation becomes: -
 V1   sL1  sL2  sL3  R1 sL2  sL3 sL3  I1 

    
V2    sL2  sL3 sL2  sL3  R2 sL3  I 2  or V  ZI
V   sL3  R3  I 3 
 3  sL3 sL3
The inverse matrix allows us to calculate input currents and impedances: I  Z 1V
Y
Define Y such that: Y  Z Z 1  I  V
Z
The inverse matrix can be derived using Cramer’s rule (see “Three-stage filters” Appendix 1 [1]) which, with the
symbol substitutions, supplies the components: -
Y11  s 2 L2 L3  sL2  sL3 R3  sL3 R2  R2 R3

Y12   s 2 L2 L3  sL2  sL3 R3 Y11  Y12  Y13  R2 R3
Y13   sL3 R2
Y21   s 2 L2 L3  sL2  sL3 R3
Y22  sL1  sL2 sL3  sL3 R1  sL1  sL2  sL3 R3  R1 R3 Y21  Y22  Y23  sL1R3  R1R3
Y23   s L1 L3  sL3 R1
2
Y31   sL3 R2
Y32   s 2 L1 L3  sL3 R1
Y33  sL1 sL2  sL3   sL2  sL3 R1  sL1  sL2  sL3 R2  R1 R2
Y31  Y32  Y33  s 2 L1L2  L2 R1  L1R2  L2 R2 s  R1R2
The determinant is (see “Three-stage filters” appendix 2): -
Z  R1R2 R3  sL1  L2  L3 R2 R3  L2  L3 R1R3  L3 R1R2  s 2 L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2  s3 L1L2 L3
To derive the transfer function one needs the output impedance matrix. Swapping symbols again one finds: -
 U1   sL1  sL2  sL3 sL2  sL3 sL3  I1 

    
U 2    sL2  sL3 sL2  sL3 sL3  I 2  or U  XI
U   sL3  I 3 
 3  sL3 sL3
From above: I  Z 1V so that: U  XZ 1V  TV
Where T is the transfer function matrix: T  XZ 1
Ω Ω
Define: Ω  Z XZ 1 so that U  V i.e. T and Ω  XY
Z Z
To calculate the output, in terms of the input, one only needs the relevant components of Ω .
1. Part 2, monograph 2: “Three-stage filters”.
2
Part 3: Monograph 4
1.1 The effects of follower errors, noise, loading and equalisation of windings
The effects of follower errors, noise and loading of the energising winding and ratio winding were analysed in
some detail in the monograph “Two-stage IVDs and RTs” [1]. Equalisation of the most significant decade and
subsequent decades was also analysed in the monograph “Single-stage IVDs and RTs”. In the case of a three-
stage structure detailed (mathematical) analysis would require the minimum of 4 × 4 matrices and the algebra
becomes complicated.
Fortunately one can apply the same rules of thumb with a high degree of confidence – the first energising winding
“bootstraps” the second and the two together bootstrap the ratio windings. Once a design is near complete, based
on these principles, it could then be worth the effort to simulate it with suitable software. One can then vary
parameters in order to optimise the design, especially if the device is to be manufactured in volume at the lowest
possible cost.
With loading, for example, the flux in the first energising winding is typically a minimum of 99% of that required
for the applied voltage. The missing flux is due to the voltage lost across the winding resistance and the small
current flowing in the secondary. The same applies to the second energising core (99% of the deficit) so that the
combined flux is 99.99%. The currents flowing in the ratio windings (primary and secondary) are correspondingly
much lower, supplying 99.9% of the deficit so that the total flux in all three cores is 99.99999% and a ratio error
of <100ppb is readily achieved.
Confirmation of the simulation results with tests on a prototype is also fairly simple. The effect of follower error
and noise, for example, can be measured by injecting a small signal with a transformer. Similarly, the effect of
loading can be observed by temporary removal.
The rules of thumb are repeated here for convenience: -
a). One must avoid loading the ratio secondary, especially with resistance. An inductive load is less of a
problem (small quadrature error) and it is possible to include an extra strand for the purposes of
equalising subsequent decade ropes with negligible error. The auxiliary core needs to be large enough and
with a sufficient number of turns to present a sufficiently high inductive load.
b). One can load the first and second energising cores with little effect on accuracy – e.g. for energising a
subsequent IVD or RT device for decades 3 and 4. See, for example, the monograph “An F18 type ratio
transformer bridge” [2].
c). The contribution to noise and error due to the followers, via the energising windings, can be made
negligible. The follower noise current, however, flows through the source resistance and the voltage
generated is added to the Johnson noise of the source. If the followers are used to drive only the energising
windings it is necessary, therefore, to set the noise resistance considerably higher than the source resistance
(lower noise current but higher noise voltage).
d). If the requirement is for a “one-off” transformer one may as well spend the cash on larger, high
permeability cores (in the required proportions). One can then use the thickest wire gauges (lowest
resistance) that will comfortably fit in neat, complete and uniform layers. The result will be overkill, in
terms of accuracy, and a little larger than necessary. Size 11b (SM100) for the energising cores and a 11c
(SM200) for the ratio core are recommended. See example calculation section 3.3.1 (later) and [2] for more
detail.

3
2. Active drive for all three primary windings
As with two-stage IVDs and transformers one could drive all three primary windings with no stability problems.
The accuracy, as well as noise, is then likely to be limited by the followers. The routing of currents to the
energising windings is very important. No energising current should flow in a section of wire between the inverting
input of the follower and the ratio winding. Depicted diagrammatically: -
V1 Ratio winding
V2
Energising windings
V3
Fig. 2.1 Connection order for high accuracy
Resistance bridges based on this approach are versatile and relatively simple to construct. See the monograph “An
F17 type ratio transformer bridge” by the same author [1]. If one wishes to achieve maximum performance,
especially in terms of noise, however, it is better to drive only the energising windings although this again raises
the issue of stability (see section 3).
2.1 Input currents and impedances
If the source impedance is very low, compared to the winding resistances, the analysis is fairly simple and reveals
the main advantages of the three-stage “bootstrap” principle. If one assumes that all three inputs are connected to
the same voltage source then: -
I1 
Y11  Y12  Y13  V 
R2 R3
VIN
IN
Z Z
I2 
Y21  Y22  Y23 V 
sL1R3  R1R3
VIN
IN
Z Z
I3 
Y31  Y32  Y33 V 
s 2 L1L2  sL2 R1  L1R2  L2 R2   R1R2
VIN
IN
Z Z
With the determinant: -
At high frequency, relative to the winding characteristic frequencies, to a good approximation: -
R R2 R3 R3 1
s   Z  s 3 L1L2 L3 I1  3
VIN I2  2
VIN and I 3  VIN
L s L1 L2 L3 s L2 L3 sL3
The resulting input impedances are: -
sL2 sL3 sL3

Z1  sL1   Z 2  sL2  and Z 3  sL3
R2 R3 R3
The impedance, Z3, of the first energising winding is, as expected, that of a simple inductor. The impedance of the
second energising winding is boosted by a large factor and real (a large negative resistance), exactly as in the case
of a two stage inductor. The ratio winding impedance is boosted even more and, usefully, is mainly imaginary. If
the source impedance is resistive then the loading effect is mainly a quadrature error.
4
Part 3: Monograph 4
The next most significant component is the real part. The full expression is: -
R1R2 R3  sL1  L2  L3 R2 R3  L2  L3 R1R3  L3 R1R2   s 2 L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2   s3 L1L2 L3
Z1 
R2 R3
At high frequency, to a good approximation, retaining both real and imaginary components: -
R s 3 L1L2 L3  s 2 L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2 

s   Z1 
L R2 R3
The largest term is negative imaginary and the next largest is negative real. The input impedance, apart from the
frequency dependence, looks like a small capacitor in series with a large negative resistor: -
Z1   R   j
1
C  
-R(ω) C(ω)
2.2 The transfer function

Ω11V1  Ω12V2  Ω13V3
The transformer output, assuming a 1:1 ratio of turns is: VOUT  U1 
Z
If all three inputs are connected to the same low resistance source: V1  V2  V3  VIN
The main output is then: -
Ω11  Ω12  Ω13
VOUT  U1  VIN
Z
One can keep the algebra to the minimum by noting that, in subscript notation: ij   X ikYkj
k
The first subscript numbers the row and the second the column so that: 
j
1j 
j
X k
Y
1k kj
It is possible to swap the order of addition:  1j   X 1k  Ykj   X 1k Yk1  Yk 2  Yk 3 

j k j k
VOUT X 11Y11  Y12  Y13   X 12 Y21  Y22  Y23   X 13 Y31  Y32  Y33 
 T s   
VIN Z
From above: -
Y11  Y12  Y13  R2 R3
Y21  Y22  Y23  sL1R3  R1R3
Y31  Y32  Y33  s 2 L1L2  L2 R1  L1R2  L2 R2 s  R1R2
X 11  sL1  sL2  sL3
X 12  sL2  sL3
X 13  sL3
T s  
L1  L2  L3 R2 R3  R1R3 L2  L3   L3 R1R2 s  L2 R3  L3 R3 L1  L2 R1  L1R2  L2 R2 L3 s 2  L1L2 L3s 3
Z
5
As if by magic the numerator replicates the determinant, apart from the first term. From above: -
Divide top and bottom by R1R2 R3 and multiply the coefficients by the natural frequency raised to the appropriate
power to give the transfer function in normalised form s  j N  : -
1
s  bs  as
3 2
 R R R 3
T s   3 with  N   1 2 3 
s  bs  as  1
2
 L1 L2 L3 
a
L1  L2  L3 R2 R3  L2  L3 R1R3  L3 R1R2  
N
R1 R2 R3
L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2 2

b N
R1 R2 R3
It is not surprising that the transfer function has the same form as a three-stage high-pass filter. Simulation shows
that acceptable values for a and b are between 2 and 10. As with three-stage filters the lower the value the greater is
the resonant peaking. Error analysis shows that, at high frequency, the in-phase error term is proportional to b. The
parameter a contributes very little to the imaginary error (fifth order): -
To analyse for high frequency errors divide top and bottom by s 3  bs 2  as : -
1
 
T s   1  3
1

 s  bs  as 
2
Take out a factor of s3 and apply an approximation, neglecting terms of order s-5 and higher [1]: -
1  b
s  1  T s   1 
1 b
3 
1  1 3  4
s  s s s
The in-phase error is now fourth order, in terms of frequency, compared to second order for a two-stage
transformer. In more convenient form with frequency in Hz: -
1
3 4
f  f   R1 R2 R3  3
T  f   1  j N   b N
1
f  f N   with fN   
 f   f  2  L1 L2 L3 
If the inductances and resistances are the same one obtains the values: a  6 and b  5 . With these values peaking
is minimal and the stability margin more than adequate. It is possible, in practice, to vary the resistances and
inductances to reduce these values with savings, in terms of smaller and lower permeability cores, fewer turns and
still retain accuracy at low operating frequency.
1 1 z
1. Method of approximation: z  1   1 z
1  z 1  z2
6
Part 3: Monograph 4
With the extra bootstrapping effect one should be able to reduce the number of turns and use thicker wire, making
it easier to construct. I shall use the same (medium) size cores as the example in the monograph “two-stage IVDs
and RTs” [1] but this time with 200 turns, instead of 400. This should be fairly simple to construct by employing
the BNNL winding technique [2].
All three cores type 7c mumetal (μR ≈ 50,000; see tables of data at the end of this monograph): -
The length of wire per turn on the first energising winding is approximately: 15 × 2 + 60 – 36 = 54mm
Inner circumference ≈ 36mm × π ≈ 113mm can accommodate 200 turns in two layers of 1mm OD wire.
Outer circumference ≈ 60mm × π ≈ 188mm can accommodate 200 turns of 0.94mm OD in a single layer.
The outer circumference is the limiting dimension: the largest wire diameter that is a comfortable fit is 20SWG
(enamelled) at 0.914mm diameter with a resistance of 26mΩm-1.
The first energising winding requires: 200  54mm  11m of wire.

Resistance R3 would be approx: R3  11m  26mm1  0.29
Permittance of all three cores: AL  51H turn2
Inductance of all three windings: L1  L2  L3  N 2 AL  200  200  51 106  2H
The second energising winding is similar but takes more wire. The first core is now slightly bigger due to the first
energising winding and so the length of wire per turn is approximately: 15 × 2 +17×2+ 62 – 34 = 92mm
With 200 turns the total length is 200  92mm  19m

Resistance R2 would be approx: R2  19m  26mm1  0.49 (i.e. very approximately twice R3.)
The ratio winding consists of a rope with typically 20 strands wound 20 times (also BNNL) of the same wire
(20SWG). Ten strands are connected in series for the ratio primary and the other ten for the secondary. With 20
strands the rope is approximately 5mm in diameter. The inner diameter is reduced slightly: -
Inner circumference ≈ 30mm × π ≈ 94mm can accommodate 20 turns in a single layer (4.7mm/turn).
Outer circumference ≈ 60mm × π ≈ 188mm can easily accommodate 20 turns also in a single layer.
As a ball park estimate the length of wire, for the ratio primary winding (200 turns), is roughly three times that of
the first energising winding, partly because it is wound around all three cores and partly because the strands are
twisted into a rope.
Resistance of 200 turns of ratio primary: R1  3R3  0.87
At 25Hz the bootstrapped input impedance of the ratio winding is: -
 2  25  2 
sL2 sL3 2 2
Z1  sL1     207 M
3
R2 R3 0.5 0.3
The source resistance (cable from the output of the followers: typically <0.1Ω) is, therefore, negligible.
N.B. This does not include the inter-winding capacitance which then becomes dominant.
It is interesting to compare the stability and accuracy with a two-stage actively driven transformer…
1. Part 3, monograph 3: “Two-stage IVDs and RTs”. See section 1.1.

2. Part 3, monograph 1: “IVDs and RTs – the basics”. For balanced no-net-loop (BNNL) see section 1.3.
7
The calculation need only be approximate: L1  L2  L3  2H R1  1 R2  0.5 and R3  0.3
The transfer function (from the previous section) is, in the normalised form s  j N  .
1 1
s 3  bs 2  as  1  R1R2 R3  3 1  1  0.5  0.3  3
T s   3 with fN  N        0.042 Hz
s  bs 2  as  1 2 2  L1L2 L3  2  2  2  2 
a
L1  L2  L3 R2 R3  L2  L3 R1R3  L3 R1R2  
N
R1R2 R3

6  0.5  0.3  4  1  0.3  2  1  0.5  2  0.042  5.5
1  0.5  0.3
L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2 2

b N
R1R2 R3
2  2  1  2  4  0.3  4  2  0.5
  2  0.042  4.9
2
1  0.5  0.3
Fig. 2.3.1 A slight peak close to the natural frequency [1]
Transformer ratio accuracy at 25Hz is: -

3 4
f  f 
f  f N  T  f   1  j N   b N   1  j 4.7  109  3.9  1011
 f   f 
Both in-phase and quadrature error terms are truly negligible. The limit, in practice, is follower errors and flux
leakage from the first energising core.
1. Spreadsheet: “Basic three-stage”.

8
Part 3: Monograph 4
3. Active drive for energising windings only
3.1 The importance of source resistance
Once again one can employ the filter circuit model. Note also the order of connections to the energising windings.
The larger current, I3, should not flow through any part of the connection to the second energising winding: -
V1 R1 I1
U1
RS
L1
VIN V2 R2 I2
U2
L2
Follower V3 R3 I3
U3
L3
0V
Fig. 3.1.1 Equivalent circuit for active drive for ratio windings only
The source resistance, RS, results in some positive feedback. The feedback network consists of the energising
windings, which has a high pass characteristic (two-stage), followed by the ratio winding, which has a low pass
characteristic. The result is a band pass characteristic whose peak magnitude can approach unity depending on the
relative cut-off frequencies. For adequate stability margin the high pass cut-off frequency needs to be higher than
the low pass cut-off. Apart from the interaction between the high pass and low pass sections the cut-off frequencies
are approximately: -
R2 R3 RS  R1 R2 R3 RS  R1
HP  LP  required: HP  LP  
L2 L3 L1 L2 L3 L1
Fig. 3.1.2 Low-pass, high-pass and combined band-pass characteristic
Clearly the source resistance and ratio winding inductance determine the lowest natural frequency and,
therefore, limit low frequency accuracy as the detailed analysis demonstrates.
9
For the circuit fig. 3.1.1, assuming an ideal voltage follower: -
Y11V1  Y12V2  Y13V3 R2 R3

V1  V2  V3 and I  Z 1V  I1   V1
Z Z
 R2 R3 RS  Z
But VIN  V1  I1 RS  V1 1   so that V1  V2  V3  VIN
 Z  Z  R R R
  2 3 S
As above: VOUT  U1 
Ω11V1  Ω12V2  13V3 
Z
 VOUT 
Ω11  Ω12  13   Z
VIN
Z Z  R2 R3 RS
VOUT 11  12  13

Resulting in: T s   
VIN Z  R2 R3 RS
The numerator is, from section 2.2: -
sL1  L2  L3 R2 R3  R1R3 L2  L3   L3 R1R2   s 2 L2 R3  L3 R3 L1  L2 R1  L1R2  L2 R2 L3   s 3 L1L2 L3
T s  
Z  R2 R3 RS
As above the determinant is: -
The whole transfer function is, therefore: -
sL1  L2  L3 R2 R3  R1R3 L2  L3   L3 R1R2   s 2 L2  L3 R3 L1  L2 R1  L1R2  L2 R2 L3   s 3 L1L2 L3
T s  
RS  R1 R2 R3  sL1  L2  L3 R2 R3  L2  L3 R1R3  L3 R1R2   s 2 L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2   s3 L1L2 L3
Divide top and bottom by RS  R1 R2 R3 and multiply the coefficients by the natural frequency raised to the
appropriate power to give the transfer function in normalised form s  j N  : -
1
as  bs 2  s 3  RS  R1 R2 R3  3
T s   with    
1  as  bs 2  s 3
N
 L1 L2 L3 
a
L1  L2  L3 R2 R3  L2  L3 R1R3  L3 R1R2 
RS  R1 R2 R3 N
L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2 2

b N
RS  R1 R2 R3
The result is very nearly the same as the previous case (see page 6) with two important differences. The resistance
R1 is replaced by R1 + RS in the formula for the natural frequency and in the denominator for parameters a and b. As
the source resistance increases, therefore, the natural frequency increases (lower accuracy) and the values of a and
b decrease (less stability margin).
The reduced stability margin can be understood in terms of the increased cut-off frequency of the low-pass part of
the feedback network causing increasing overlap with the high-pass characteristic of the energising windings.
10
Part 3: Monograph 4
This confirms the same trade-offs as with two-stage IVDs and transformers. It is useful here to recall and extend
the rules of thumb for the active drive of two-stage transformers as the same principles apply. See the monograph
“Two-stage IVDs and RTs” [1].
1. To improve stability add extra resistance in series with the energising winding(s) with a large capacitor in
parallel (active drive “compensator”). In practice it is usually sufficient to add a compensator to only the
first energising winding (RS < 100Ω). If the source resistance is higher it may be necessary to add a
compensator to both, though the analysis becomes more complicated.
2. To improve stability further employ a thicker (axially) and higher permeability top core and add extra
turns to the ratio winding (around the top core only). This increases L1 substantially.
3. The follower noise (via the energising windings) is much reduced. The follower current noise, however,
flows through the source resistance and the voltage generated appears across the ratio primary. Best noise
performance is achieved, therefore, when the noise resistance of the followers is significantly greater than
the source resistance. This is usually done by operating the follower front end BJTs at a low operating
current. See the monograph “Low noise BJT pre-amps” for more detail [2].
If one repeats the calculation of the previous example with the values:
L1  L2  L3  2H R1  1 R2  0.5 R3  0.3 and RS  100
1 1
 1  RS  R1 R2 R3  3 1  101  0.5  0.3  3
fN  N        0.2 Hz
2 2  L1L2 L3  2  2  2  2 
The natural frequency is increased by almost a factor of five (cube root of 101) compared to the previous example,
entirely due to the increased source resistance. This is not too bad, however, as the in-phase error, at the lowest
operating frequency of 25Hz, is of the order 4b ppb.
a
L1  L2  L3 R2 R3  L2  L3 R1R3  L3 R1R2  
RS  R1 R2 R3 N

6  0.5  0.3  4  1  0.3  2  1  0.5  2  0.195  0.26
101  0.5  0.3
L2 L3 R1  L1 L2  L3 R3  L1  L2 L3 R2 2

b N
R1R2 R3
2  2  1  2  4  0.3  4  2  0.5
  2  0.195  1.1
2
101  0.5  0.3
Computer modelling shows that these values are on the low side, resulting in a large resonant peak close to the
resonant frequency – stability is the main problem.
Fortunately there is a simple way to maintain a low natural frequency and improve stability margin: rule of thumb
1(above) with an active drive compensator [1].

2. Part 5, monograph 2: “Low noise BJT pre-amps”.
11
3.2 Active drive with compensator
The basic idea is that at low frequency (below the natural frequency) the compensator resistance dominates,
ensuring stability but, as frequency increases the impedance of the capacitor drops so that, at the operating
frequency, the bootstrapping effect and high accuracy is restored. As a ball park estimate (very approximately) the
impedance of the capacitor is of the same order as the compensator resistor at the natural frequency of the
transformer: -
1
For stability: R  RS and, at the natural frequency: XC  R
N C
V1 R1 I1
U1
RS
L1
VIN V2 R2 I2
U2
C L2
Follower R3 I3
U3
V3
R L3
Compensator
0V
Fig. 3.2.1 Active drive with compensator (first stage only)
At the operating frequency the reduced current in the first energising winding (as a result of the extra series
impedance) results in a slightly lower voltage induced in the second energising winding. The small error is thus
largely corrected by a slight increase in current in the second energising winding, as long as one keeps R2 small.
The high input impedance and accuracy of the ratio winding is hardly affected by the compensator R and C. The
transfer function can be derived by the substitution: -
R R  R3  sRR3C
R3  Z 3  R3  or, in more convenient form: R3  Z 3 
1  sRC 1  sRC
Fig. 3.2.2 Impedance magnitude of a typical compensator vs frequency (RS = 100Ω) [1]
1. Spreadsheet: “Compensator impedance”

12
Part 3: Monograph 4
The algebra is a bit messy and relegated to appendix 1. The main results are, in normalised form s  j N  : -
1
as  bs 2  cs 3  s 4  R  R1 R2 R  R3   4
T s   with N   S 
1  a   s  bs 2  cs 3  s 4  L1L2 L3 RC 
a
L1  L2  L3 R2  R1 L2  L3 R  R3   L3 R1R2 
RS  R1 R2 R  R3  N
b
L2  L3 R  R3 L1  L1  L2  L3 R2 RR3C  R1RR3C L2  L3   L2 R1  L1R2  L2 R2 L3  L3 R1R2 RC   2
RS  R1 R2 R  R3  N
c
L2  L3 RR3CL1  L1L2 L3  L2 R1  L1R2  L2 R2 L3 RC  3 
RR3C
N
RS  R1 R2 R  R3  N
R  R3
3.2.1 Error analysis

1
 1  s 
Divide top and bottom by as  bs  cs  s :
2 3 4
T s   1  4 
 as  bs  cs  s 
2 3
A very good approximation is [1]: -

 1  s 
s  1  T s   1  4 
 as  bs  cs  s 
2 3
Take out a factor of s 4 and repeat the approximation for the small error term: -
1  s  c b a 
T s   1  1    
s 4  s s 2 s3 
Terms of s 6 and smaller are negligible so that, to a very good approximation: -
1  s  c   1 c
c 1  T s   1  4 
1  1 3  4  5
s  s s s s
This is sufficient to retain both in-phase (real) and quadrature (imaginary) components. Note that the term cs 5 is
retained because it may be comparable to s 3 . In more convenient form, with frequency in Hz: -
1

  fN 
3
 fN  
5
  fN 
4
1  RS  R1 R2 R  R3   4
f  f N  T  f   1  j     c      with fN   
  f   2 
      
f f L1L2 L3 RC
In practice the compensator resistance is much greater than the winding resistance so that a convenient
approximation is: -
RR3C
R  R3    N  R3CN
R  R3
1 1 z
1. Method of approximation: z  1   1 z
1  z 1  z2
13
Adding extra turns to the top core can be represented according to the usual convention: windings horizontally
adjacent to cores are wound around those cores, at least in part. In this case NP turns of the ratio winding rope are
wound around the top core (only) and then NP turns around all three cores. The bootstrapping voltage induced in
the ratio winding is the same as before. Ratio accuracy is also maintained as the secondary winding is part of the
same rope as the primary and shares the same flux.
V1 I1 R1
NP
Ratio winding
VOUT
NP Φ1 Φ2 Φ3 NS
Secondary
I2 R2
V2 NP winding
Energising
windings
I3 R3
V3 NP
Fig. 3.3.1 Extra turns around the top (ratio) core
The overall effect is to increase the inductance L1 by a factor of four, as the following demonstrates: -
V1  I1R1  s2 N P1  N P2  N P3  V2  I 2 R2  sN P2  N P3  etc.
Note the extra factor of two is because of the extra turns around the top core. The expressions for V2 and V3 remain
unaltered. Similarly, for ideal magnetic circuits, the magneto-motive force in the top core is also doubled so that the
fluxes are: -
1  2 N P I1 AL1 2  N P I1  N P I 2 AL 2 3  N P I1  N P I 2  N P I3 AL 2
AL1  permittance of core 1. AL 2  permittance of core 2. AL 3  permittance of core 3.
From the above:    

V1  I1R1  s 4 N P2 I1 AL1  N P2 I1 AL 2  N P2 I 2 AL 2  N P2 I1 AL3  N P2 I 2 AL3  N P2 I3 AL3 
The winding inductances are: L1  N P2 AL1 and L2  N P2 AL 2 etc
Then: V1  I1 R1  4sL1  sL2  sL3   I 2 sL2  sL3   I3 sL3  etc
The rest of the analysis is exactly the same as before (sections 1, 2 and 3) but with the substitution: L1  4L1 .One
may as well retain the formulae for the transfer functions and input impedances and calculate the inductance L1
with twice the number of turns (i.e. the actual number of turns around the top core): L1  2 N P  AL1 .
2
14
Part 3: Monograph 4
The analysis and previous example (section 3.1) point the way to go – with a higher source resistance (up to 100Ω)
the only option is to significantly increase all inductances (especially L1) and apply at least one compensator. The
top (ratio) core is increased to a size 11c SM200 with both energising cores also size 11 but only thickness b
(SM100) and, to make winding practicable, one may as well stick to 200 turns. The larger cores also allow one to
use thicker wire (1.5mm is about the thickest that can be easily wound) and accommodate the extra turns around
the top core. When calculating total length of the energising windings one adds a bit extra (about 5%) because of its
thickness and bend radius. Using the thicker wire on the first energising winding is required, not to reduce the
resistance but to fill the larger core – creating, as near as possible, a uniform sheet of current around the surface of
the core.
First energising core type 11b (see appendix 2): -

The length of wire per turn on the first energising winding is approximately: 19 × 2 + 112 – 66 = 84mm
Inner circumference ≈ 66mm × π ≈ 207mm can accommodate 200 turns in two layers of 2mm OD wire.
The outer circumference is the limiting dimension: the largest wire diameter that is a comfortable fit is 1.5mm
(enamelled) with a resistance of 9.8mΩm-1 (extrapolated from 16SWG of 1.626mm at 8.3mΩm-1 because the
metric size is more readily available from stock).
The first energising winding requires (+5%): 200  88mm  18m of wire.
Resistance R3 would be approx: R3  18m  9.8mm1  180m
The second energising winding is around both 11b cores with a slightly reduced ID and increased OD
Inner circumference ≈ 60mm × π ≈ 188mm can accommodate 200 turns in two layers of 1.8mm OD wire.
One may as well use the same wire size (i.e. 1.5mm - any larger is tricky because of the radius of bends).
OD = 114mm ID = 60mm combined axial = 19 + 3 + 19 = 41mm.

The length of wire per turn on the second energising winding is approximately: 41 × 2 + 114 – 60 = 136mm
The second energising winding requires (+5%): 200  141mm  28m of wire.
Resistance R2 would be approx: R2  28.5m  9.8mm1  0.3
Permittance of both energising cores: AL  136H turn 2

Inductance of both energising windings: L2  L3  N 2 AL  200  200  136  106  5.4H
The ratio winding consists of a rope with typically 20 strands wound 20 times around the top core only and another
20 times around all three cores – a total of 40 turns around the top core (see section 4.3.3). Ten of the strands are
connected in series and used for the primary, the other 10 for the secondary. This would usually require thinner
wire (about 0.5mm diameter is comfortable). With 20 strands the rope is approximately 4mm in diameter. The
inner diameter is again reduced slightly: -
Inner circumference ≈ 57mm × π ≈ 179mm can accommodate 40 turns in a single layer (4.5mm/turn available).
The outer circumference is not a problem and can easily accommodate 40 turns.
Ratio core type 11c (see appendix 2): -

The length of wire per turn on the top core only is approximately: 23 × 2 + 112 – 66 = 92mm
The average inner and outer diameters remain about the same but the axial length increases: -
OD = 114mm ID = 60mm combined axial = 19 + 3 + 19 +3 +23= 67mm.
The length of rope per turn of the ratio winding around all three cores is approximately: -
67 × 2 + 114 – 60 = 188mm
15
The ratio primary winding (ten strands or 200 turns) requires: 200  188  92  56m
Resistance R1 is approximately: R1  56m  88mm1  5
Permittance of ratio core: AL  328H turn 2 (SM200 grade)
Inductance of ratio windings: L1  N 2 AL  400  400  328  106  52H
I shall assume the following values: -

a). Transformer characteristics: R1  5 R2  0.3 R3  0.18
b). The compensator resistance is set at the maximum expected source resistance: R  RS  100  R3 , R1
c). The two energising windings have the same inductance: L2  L3  5.4H
d).Boosted inductance of the ratio winding primary: L1  52H
e). The target natural frequency is approximately: N  1 rads-1.
f). The capacitor has (very approximately) the same impedance as R at the natural frequency.
1 1
The compensator capacitor is, therefore: XC  R  C  10mF
N C N R
These calculations are “ball park” (the inductances, in particular, are highly unpredictable). One can simplify the
manual calculation with approximations: -
L1  10L with L  5.4H and RS  R1  RS and R  R3  R
1 1
 R  R1 R2 R  R3   4  R R 4
N   S    N   S 3 2   1.17 rads-1
 L1L2 L3 RC   10 L C 
The natural frequency is near enough
RR3C
 N    R3CN  2.1 103 and small enough.
R  R3
a
L1  L2  L3 R2  R1 L2  L3 R  R3   L3 R1R2  
 12 L 2 LR1 LR1 
a     N  3
RS  R1 R2 R  R3  RS R2 RS R 
N
 RS
The full expression for b is: -
b
L2  L3 R  R3 L1  L1  L2  L3 R2 RR3C  R1RR3C L2  L3   L2 R1  L1R2  L2 R2 L3  L3 R1R2 RC   2
RS  R1 R2 R  R3  N
 20 L2  2
Only the first term is significant so that: b   N  191.17 2  26
 RS R2 
The full expression for c is: c

L2  L3 RR3CL1  L1L2 L3  L2 R1  L1R2  L2 R2 L3 RC  3
RS  R1 R2 R  R3  N
 20 L2 R3C 10 L3 L2 R1  11R2 C  3

 c     N  0.035  0.52  0.081.17 3  1
 RS R2 RS R2 R RS R2 
16
Part 3: Monograph 4
The result is a peak in the frequency response but well below the operating frequency. There is further scope for
increasing the compensator capacitor though practical considerations come into play. See the monograph “A
simulated large capacitor circuit” by the same author [1].
The precise values from a spreadsheet calculator are: -
L1  52H L2  L3  5.4H R  RS  100 R1  5 R2  0.3 R3  0.18
N  1.2  f N  0.19Hz  a  2.78 b  25.8 c  1.02 and   2.16 103
Fig. 3.3.1.1 Bode plot of the low frequency response
The error analysis, from the previous section, is:-

  fN 
3
 fN  
5
  fN 
4
N
f  f N  T  f   1  j     c      with fN   0.19 Hz
  f   2
     
f f
 7.6  10 3  T  f   1  j 0.8  109  2.7  109

fN
  R3CN  2.16  103 and, at 25Hz
f
Both quadrature and in-phase errors are very small. The contribution from the 5th order term is negligible.
17
Whereas most applications are best served by driving both energising windings from the primary side a potentially
useful variant employs a single low noise high accuracy voltage follower (HAVF) on the secondary side to provide
the energising current. The primary winding input is fully differential and the input impedance remains boosted but
the output is relative to local 0V. Loading on the secondary winding is negligible and the very low output resistance
of the HAVF could be useful.
The main advantage is the saving of a voltage follower and its floating power supply (lower cost and size). Despite
this there are no obvious (high accuracy) applications – the output relative to 0V is a problem.
One might expect that a possible application is for noise matching. This is not so – a two-stage approach provides a
sufficient boost to the input impedance. The main problem is the phase error and the lower magnitude error of a
three-stage transformer is of no benefit. For more detail see the monograph “Noise matching transformers” by the
same author [1].
High accuracy with a high source resistance could be one possibility. Previous analysis has shown that the best way
to ensure stability with moderately high source resistance (up to 100Ω) is to boost the top core inductance and add
a compensator in series with at least one of the first energising windings. With higher source resistance (> 100Ω),
however, it would make sense to add compensators to both energising windings. For example: -
NS
RS + R1 Output
NP
VIN
NP
Φ3 Φ2 Φ1 VOUT
NP
0V
Z2
NP
Z3
NP Compensators
Fig. 4.1 Outline schematic of an impedance matching transformer
The follower noise injected via the energising windings is negligible (see section 5) but the noise current is
reflected back to the primary and flows through the source resistance. Best performance is achieved, therefore,
when the noise resistance of the follower is significantly greater than the source resistance. With compensators in
series with both energising windings the DC performance of the follower becomes less important and a JFET input
stage becomes an attractive option, especially for the higher range of source resistance.
To the best of my knowledge there is nothing in the literature, based on this idea, and no commercial kit is
currently available. If you can think of an application, dear reader, please contact the author.
18
Part 3: Monograph 5
Noise matching transformers

1. Introduction
Best noise performance is achieved when the noise resistance of the pre-amplifier matches the signal source
resistance [1]. A reasonably good match is within a factor of three. A larger mismatch can be corrected with a
transformer. Optimal noise matching is when the transformer ratio is the square root of the resistance ratio: -
NS RN
For optimal noise matching: 
NP RS
Where: -
N P  Number of primary turns
N S  Number of secondary turns
RN  Noise resistance of pre-amp (voltage noise/current noise)
RS  Source resistance
Excellent matching from about 1kΩ to over 100kΩ is easily achieved by direct connection to a pre-amp with a
bipolar junction transistor (BJT) front end [2]. The noise resistance of BJTs can be controlled over a range 1kΩ to
over 100kΩ by selecting the required collector current. Lower source resistance can be accommodated by
connecting a number of BJTs in parallel, though the law of diminishing returns sets in rather quickly: the reduction
is proportional to the square root of the number of pairs [1]. Reducing the noise resistance by a factor of ten, for
example, would require 100 matched pairs at considerable expense. At the upper end of the range it may be
possible to connect directly to a large area (low noise resistance) type junction field effect transistor (JFET) pair
even if matching is not ideal – noise power spectral density (and noise temperature equivalent) is at least two orders
of magnitude lower for the best JFETs (typically 10-21W/Hz or 20K for a BJT versus 4×10-24W/Hz or 0.1K for a
JFET).
JFETs with noise resistance from 100kΩ to over 10MΩ are readily available. Matching can be adjusted, but only to
a very limited extent, by selecting the required drain-source current. JFETs also work well at very low temperature
though that would be expensive and beyond the scope of these monographs.
One application for a noise matching transformer is from low source resistance (e.g. platinum resistance
thermometers (typically 0.3 - 400Ω)) to a BJT pre-amp (noise resistance typically ≈ 1kΩ). This is readily achieved
with a basic (single-stage) transformer. There is no point in improving on this (e.g. matching to a JFET) as the main
source of noise is Johnson noise from the source (T > 20K).
The main problem with single-stage transformers is the phase shift due to source resistance and primary
inductance. The result is a design with a large, high permeability core with a large number of turns for the primary
(hundreds) requiring a very large number (thousands) of turns for the secondary. Whereas this is not particularly
difficult (technically) it is laborious and time consuming.
There may be other applications, however, where the source is very cold (< 20K) but the resistance is too low for a
direct match to JFETs. This raises the possibility of a two-stage approach [3]. To the best of my knowledge no
commercial kit is available and a comprehensive search of the literature has drawn a blank. Section 3 remains in the
realm of theory but if you are interested in making and testing a prototype please contact the author.
1. Part 5, monograph 1: “Null detectors – the basics”. See section 2.

1
2. A single stage transformer
Near ideal impedance matching (from 0.3Ω – 300Ω to a BJT matched pair) can be achieved with a single-stage
transformer. The main problem is the requirement for a large (typically >10c) high permeability (SM100) core and
the very large number of turns required for the secondary in order to achieve the necessary input impedance. The
following has three settings (nominally 1, 10 and 100Ω source resistance). The BJT amplifier has collector currents
set for a noise resistance of 1kΩ (typically 0.1mA) [1].
100Ω Size 10c SM100

core
700
10Ω
3000 VOUT
200
1Ω
VIN Output to
100
pre-amp: RN = 1kΩ
Fig. 2.1 A noise matching transformer for low source resistance
The input impedance at the lowest operating frequency (typically 25Hz) is: -
Z  2fL with L  N P2 AL and AL  153 H turn2
The resulting input impedances are: for the 1Ω winding (100 turns): L  1.53H , Z  240 ; 10Ω (300 turns):
L  13.8H , Z  2k and for the 100Ω winding (1000 turns): L  153H , Z  24k . The winding resistances
are negligible compared to the inductive impedances. According to basic transformer theory the transfer function
has a first order high pass characteristic [2]: -
s
T s  
L
with  
1  s RS
At the lowest operating frequency the effect on magnitude is small and not particularly important. The phase shift,
however, could affect the null detector operation. In polar form: -
 1 
T s   cos exp  j  with   arctan  
  
2
  1  cos   1 
1 RS
and   
2  L
The result is less than one degree phase shift for source resistance up to 300Ω. See fig. 2.4
1. Part 5, monograph 2: “Low noise BJT pre-amps”. See section 2.4.

2
Part 3: Monograph 5
Ideal amp
VS VN
RS NP NS IN
Fig. 2.2 Noise model with matching transformer
NS V
Define the transformer ratio and noise resistance:  and RN  N
NP IN
According to basic (single-stage) transformer theory the current and voltage reflected to the primary side are [1]: -
VN
I P  I N and VP 

The source noise, VS, noise current and pre-amp noise voltage are statistically independent and the total (RMS)
noise voltage, referred to the primary side is, therefore [2]: -
2
V 
VT2  VS2  I N RS    N 
2
 
This is a minimum when the gradient is zero with respect to the transformer ratio: -
VT2  2V 2
 2I N2 RS2  3N  0
 
VN2 RN
   2 2  
4
QED.
I N RS RS
If one assumes a noise-free source VS  0 the noise power referred to the primary side is: -
I2  R  
2 2
VT2 V 
PS     I N RS    N   N  RS    N  
2 2
RN   RN     
RN I N2
The minimum power is, therefore:   PMIN   2 RN RS
RS RN
Expressed as a ratio the power match efficiency is, therefore: -
PMIN 2 RN RS

PS   RS 2  RN  2

2. Part 5, monograph 1: “Null detectors – the basics”. See appendix 1.
3. Spreadsheet: “Noise matching transformer”.
3
For the ideal transformer (see fig. 2) with three settings 1Ω, 10Ω and 100Ω the degree of matching is satisfactory
from 0.3Ω to about 300Ω [1]: -
Fig. 2.3 Power matching efficiency for a single-stage transformer
The phase shift is sufficiently low for a null detector [1]: -
Fig. 2.4 Phase shift (25Hz and 75Hz)
(The lower frequency results in greater phase shift.)
1. Spreadsheet: “Noise matching transformer 1”.
4
Part 3: Monograph 5
3. A possible two-stage transformer
3.1 Outline design
A two-stage transformer could offer advantages compared to the single-stage approach: fewer turns and smaller
cores. The actively driven energising winding provides an enormous boost to the input impedance which, at the
operating frequency, becomes real (resistive). The result is a significant reduction in phase shift. It is then possible
to reduce the number of turns on the primary and secondary for a given source resistance.
A higher primary to secondary ratio is also practicable (e.g. to match a low to medium source resistance to the
much higher noise resistance of a JFET pre-amplifier). The proposed design, however, is aimed at matching the
output of a single-stage transformer (1kΩ) to the lowest noise JFET pre-amplifier: a step-up ratio of about 1:30.
Previous analysis [1] has shown that the best way to ensure stability with moderately high source resistance (up to
1kΩ) is to boost the top core inductance with extra windings and a higher permeability core plus a compensator (a
large capacitor and parallel resistor) in series with the energising winding. The approach chosen is active drive,
from the secondary side [1], with a (JFET input) compensator [2].
RS
NP
VIN
NP Φ2 Φ1 NP
0V
Output to Compensator, Z
NS NP
pre-amp
Fig. 3.1.1 Outline schematic of an impedance matching transformer
The lower accuracy requirement also means that the primary and secondary windings do not need to be on the same
rope which can be an advantage (low capacitive coupling between primary and secondary). Also, most of the flux,
corresponding to the input voltage, is in the energising core. The main secondary (output to the pre-amp) could be
wound around that core only, rather than both. This would save a great deal on wire though it may not be the most
practicable approach. It should be possible to employ a relatively simple compensator (no need for a high accuracy
voltage follower), albeit of composite type with a low noise JFET front end [3].
1. Part 3, monograph 3: “Two-stage IVDs and RTs”. See section 7 (active drive from the secondary).
5
It is shown elsewhere [1] that the equivalent circuit (assuming a ratio of 1:1) is a high pass filter with active drive
from the output. The follower and series impedance are hypothetical – the actual circuit is a simulated large
capacitor which performs the same function [2]: -
RS+R1 I1 U1
V1
VOUT
L1
Z I2
U2
V2
L2
0V
0V
Fig. 3.2.1 The equivalent circuit
With no compensator the impedance Z is simply the energising winding resistance R2. With a compensator make
the substitution R2  Z . This is the compensator in series with the winding resistance: -
R
Z  R2 
1  sRC
Also, the resistance R1 consists of both source and winding resistance. The transfer function (from [1]) becomes: -
sL1  L2 Z  s 2 L1L2
T s  
VOUT

V1 RS  R1 Z  sL1  L2 Z  s 2 L1L2
A useful parameter is the determinant: Z  RS  R1 Z  sL2 RS  R1   L1  L2 Z   s 2 L1L2
One can check this with the matrix method [3]. The output impedance matrix is: -
 U1   sL1  sL2 sL2  I1 

U  XI or      
U 2   sL2 sL2  I 2 
The input impedance matrix is: -
 V1   RS  R1  sL1  sL2 sL2  I1 

V  ZI or      
V2   sL2 Z  sL2  I 2 
 I  1  Z  sL2  sL2  V1 
I  Z 1V or  1     
RS  R1  sL1  sL2 V2 
The inverse is:
 I 2  Z   sL2
1. Part 3, monograph 3: “Two-stage IVDs and RTs”. See section 3.

3. Part 2, monograph 1: “Two-stage filters”. For an introduction to the matrix method see section 2.
6
Part 3: Monograph 5
From which the transfer function matrix equation is: -
Ω  U1  1  sL1  L2 Z  s 2 L1L2 sL2 RS  R1   V1 

U  V or      
Z U 2  Z  sL2 Z sL2 RS  R1   s 2 L1L2 V2 
In this case the energising drive is from the output side. If one assumes an ideal voltage follower/compensator: -
V1  VIN and V2  U1  VOUT
Ω11V1  Ω12V2 Ω11

 T1 s  
VOUT
VOUT  
Z VIN Z  Ω12
A little algebra produces the same transfer function as above and confirms the equivalent circuit method.
Ratio accuracy is not particularly important and it is worth checking if the voltage developed across the energising
core is sufficiently accurate.
Ω21V1  Ω22V2 U 2 Ω21  Ω22T1 s 

U2  and V2  VOUT  T1 s VIN  T2 s   
Z VIN Z
One could expand the transfer function to the usual polynomial form but that method reveals little. It is much
simpler to simulate the equations with a spreadsheet and bite-size calculations (first calculate the matrix elements,
determinant and transfer function T1 s  ). The results confirm that the phase error is sufficiently small.
In this case the main issue is stability – the inductance of the top core needs to be substantially greater than the
energising core. This can be achieved with extra turns around the top core only and the highest possible
permeability. Effective bootstrapping requires the energising winding to be uniformly distributed around the core to
minimise flux leakage. A number of windings can be connected in parallel and this also ensures low resistance. The
reduced number of turns for the primary and energising windings also allows the use of thicker wire and medium
sized cores. A useful starting point is the example based on 5c cores (mumetal and super mumetal: μR ≈ 50,000 and
200,000 respectively) [1]. The primary windings are 40 turns BNNL of 0.457mm enamelled copper wire (26SWG).
Both cores type 5c: -

Inner circumference  23    72mm mm can accommodate 160 turns (four windings of 40 turns each) in a single
layer of 0.45mm OD wire. It may be a bit of a squeeze but worth a try with 26SWG (enamelled) at 0.457mm
diameter as one is likely to have some in stock. A couple of extra turns of double layer at the centre of each BNNL
as the winding is finished off should leave plenty of room for the secondary winding. Otherwise 0.4mm diameter
wire would be a comfortable fit. The outer circumference is not critical.
Each energising winding requires: 40  48mm  200mm  2.1m of wire, including 100mm tails.
Resistance of each energising winding would be approx: R  2.1m  105mm1  0.22
Four windings connected in parallel produces a net resistance: R2  0.22 4  0.056
Permittance of energising core (mumetal): AL  51H turn2
Inductance of energising windings: L2  N 2 AL  40  40  51 106  0.082H
7
The secondary (output to the pre-amp) consists of 126 turns (BNNL) of a ten strand rope of fine wire. The winding
resistance is not important but the wire should be strong enough to be manageable (without breaking). Enamelled
copper of 0.2mm diameter should be satisfactory. The primary to secondary ratio is then up to 40:1260 (1:31.5 and
a maximum noise resistance match of approximately 1:1000).
The inner diameter is reduced by 1mm so that the inner circumference is reduced to 22    69mm
The rope is approximately 1mm in diameter requiring two layers on the inner circumference: -
First layer: possibly 22mm    1mm  69 (35 per side looks good). The internal diameter reduces to 20mm.
Second layer: possibly 20mm    1mm  63 turns (28 per side to make up the total required). The internal
diameter reduces to 18mm and more than sufficient for the ratio windings.
The primary winding consists of 40 turns around the top core only (BNNL) plus another 40 turns around both cores
(BNNL) occupying half the core. With twice as many turns and four times the permeability the inductance is
increased by a factor of 16: -
Permittance of top core (SM200): AL  204H turn 2

Inductance of energising windings: L2  N 2 AL  80  80  204  106  1.3H
The primary winding resistance is negligible compared to the source resistance (up to 1kΩ).
The ratio secondary also consists of 40 turns around the top core only plus 40 turns around both cores (BNNL) on
the other half of the core. This should keep interwinding capacitance sufficiently small without the need for
screening. Winding resistance is again negligible as the compensator has very high input impedance.
Simulation with a spreadsheet indicates that a suitable compensator is 10Ω in parallel with 0.1F. The resulting
phase shift is: -
Fig. 3.3.1 Phase shift for 1kΩ source resistance
There is also a slight peak in the magnitude response but too small to be of concern.
1. Spreadsheet “A two-stage noise matching transformer”
8
Part 3: Monograph 6
An F17 type ratio transformer bridge

1. Introduction
In the summer of 1978 I graduated and joined ASL as a Development Engineer, thanks to Peter Wolfendale,
based on my knowledge and experience of microprocessors. My first job was to design the printed circuit
board for the first of what became the “F series” of resistance thermometry bridges. JDY had come up with
some new ideas which, with the introduction of a microcontroller, made it possible to significantly reduce
size and cost, compared to the market leader – the ASL A7 double Kelvin automatic bridge. When I asked
John “what are we going to call it?” he replied “Fred”, short for “fairly random electronic design”. The
prefix “F” survived for quite a few years in the form of models F16, F17, F18, F25 and F26.
Fig. 1.1 The F17 (Picture courtesy ASL Ltd)
One of JDY’s main innovations was the high accuracy “inside-out” voltage follower (HAVF) [1]. With very
high input impedance and very low output impedance it resulted in a major simplification in the required
characteristics of the ratio transformer.
The resulting design was very simple to construct: a three stage transformer with mid–range sized toroids,
only 100 turns for the energising stages and sufficient room for an extra winding which allowed a range of: -
0.000000 to 3.999999
This range is well suited to resistance thermometry as the maximum value of resistance of a typical
commercially available SPRT [2] is just less than four times its resistance at the triple point of water.
The F17 operates at 1.5 × supply frequency (75 or 90Hz) for maximum rejection of supply harmonic
interference. This is low enough for most thermometers and standard resistors so that AC/DC differences are
negligible.
The only disadvantage is the noise generated by the followers, reducing resolution for a given bandwidth,
compared to what is possible theoretically. For many industrial customers and academics, however, this was
not a problem and the F17 sold like hot cakes.
1. Part 4, monographs 1 and 2: “High gain blocks” and “High accuracy voltage followers”
2. For example the Tinsley model 5187SA Standard Platinum Resistance Thermometer.
1
The followers drive both energising windings and ratio windings in parallel. Note the order of connections –
the current flowing through the first energising winding does not flow in any part of the connection to the
second energising winding or the ratio winding. Similarly, the (smaller) current flowing through the second
energising winding does not flow in any part of the connection to the ratio winding. The connections to the
ratio winding are thus closest to the inverting input which, by the action of negative feedback, is at the same
voltage as the non-inverting input to a very high degree of accuracy. This order of connections is essential
for accurate operation – and not a little disconcerting for the production department.
nVR
RS VS
RT VT
Null detector
Fig. 1.1.1 The F17 basic bridge configuration (simplified)
The ratio transformer is very easy to construct. The followers had sufficient accuracy (sub-ppm) and low
noise to achieve the target specification – accuracy to better than 1mK with a 25Ω SPRT.
The internal reference resistor is contained in a very simple temperature controlled oven, which most users
found perfectly adequately stable over time.
N.B. The alternative to high accuracy followers was to use two extra reference resistors, in series with RS, to
provide the voltages for the two energising windings. The main disadvantages of this approach are twofold: -
1. The reference resistors are fixed internal devices, requiring a temperature controlled environment. It is
preferable to have a single external reference resistor e.g. a Wilkins type.
2. The high source resistance requires the toroidal cores to be larger and/or of higher grade (higher
permeability) or with more turns.
Historical note: This approach was taken by ASL’s main competitor, Tinsley Instruments, resulting in the far
inferior model 5840 originally developed by R. B. D. Knight of NPL [1].
1. Knight R. B. D., “A precision bridge for resistance thermometry using a single inductive current
divider.” Euromeas. 77, IEE conference. Pub. 152.
2
Part 3: Monograph 6
1.2 Active guard circuit
Another innovative design feature of the F17 is the use of a high gain block (HGB, two-stage, type 1 [1]) to create a
“virtual earth” point for the bridge. The HGB, standard resistor and thermometer are configured as an inverting
amplifier. The action of feedback ensures that the inverting input of the HGB is maintained at 0V very accurately,
setting the bridge potentials relative to local earth. This is much more practicable than a “Wagner balance” [2].
The F17 employs coaxial cables for both external standard resistor and thermometer. The outer conductors (current
and voltage) provide adequate screening of the more sensitive (to interference) inner conductors. Any interference
coupled to the (high impedance) current source side outers flows through both resistors and has no affect on the
balance. The HGB side has very low impedance and any interference is absorbed by the HGB output.
coax VS VT coax
outers outers
RT
RS
Virtual earth
HGB
0V (earth)
Fig. 1.2.1 The F series active guard
2. The main ratio transformer [3]
1 1
100 0 - 300
4
1 2 3 4 0 - 90
5 5 0-9
0 – 90 6
10-2
×2
0-9 7 Output
0V
0-9 8
10-2
100 2 9
10-2 RS trim
100 3
Fig. 2.1 The F17 main ratio transformer
For more detail (theory) see: -

2. Part 3, monograph 9: “Coaxial AC chokes”
3
One of the main advantages of direct drive with followers is the possibility of employing a three-stage ratio
transformer with thinner wire (0.5mm) on medium sized cores (7a) and a much reduced number of turns. The
result: all seven decades can be incorporated in a single transformer unit which is easy to manufacture.
Winding 1: 5 strand rope with 100 turns around all three main cores (BNNL). One of the strands is used as the ratio
primary, three for a variable secondary (decade 1) and one for equalisation of the next decade. Being part of the
same rope the voltage induced in each strand is the same to a high degree of accuracy.
Windings 2 & 3: Energising windings - 100 turns (BNNL) in a single layer to fill the inner circumference.
Winding 4: 11 strand rope with 10 turns (BNNL) around all three main cores plus a few turns through small
auxiliary core 4. 10 of the strands are connected in series and provide a variable secondary (decade 2) which is
wired in parallel with the decade 1 equalisation strand. The extra strand is used for equalisation of the next decade.
Winding 5: 10 strand rope with 1 turn around all three main cores and a few turns through small auxiliary core 5.
The 10 strands are connected in series and provide a variable secondary (decade 3). It is also connected in parallel
with the decade 2 equalisation strand.
N.B. Decades 1, 2 and 3 ratio settings (“taps”) are selected by low resistance glass encapsulated reed relays.
Winding 6: 10 strand rope with10 turns around all three main cores. Two sets of 10 analogue switches are used to
select the required taps which are then connected to the bottom of windings 7 and 8.
Winding 7: 10 strand rope with 1 turn. The required output is again selected by analogue switch. When added to
one of the outputs selected from winding 6 the result is reduced by a factor of 100 and then connected to the bottom
of winding 5. Winding 6 selection 1 and winding 7 thereby furnish decades 4 and 5 respectively.
Winding 8: Same as winding 7 but the result is reduced by a factor of 10000 before being added to the bottom of
winding 5. Winding 6 selection 2 and winding 8 thereby furnish decades 6 and 7 respectively.
Windings 6, 7 and 8 voltages are combined using two small transformers, supplied by a pair of high pass
filters/voltage followers (see fig. 2.3). Both followers require very low DC offset adjustments due to the low
resistance of the primary windings: -
High-pass filter/followers To winding 5
Dec 4 & 5
To output
Dec 6 & 7
200:2 turns
0V
200:2+2 turns
Fig. 2.2 Decades 4 to 7 are furnished by small step-down transformers
For the last two decades (6 & 7) a single-stage transformer (ratio 100:1) is sufficiently accurate. The outputs of this
transformer (two windings of 2 turns each) are added to the inputs of a two-stage transformer (also 100:1). The
output resistance is very low, but not negligible, consisting mainly of the resistance of the interconnecting wires.
The energising current would cause a small voltage drop and so a separate output winding is used for the purpose.
The second output winding is then added to the ratio winding which has much higher (bootstrapped) input
impedance. The small error in the energising voltage has negligible effect on the two-stage transformer ratio
accuracy. Note the relative polarity of the windings for correct adding of the voltages.
4
Part 3: Monograph 6
The other end of the two-stage transformer primary windings are driven by the voltage follower for decades 4 & 5.
Note the order of connection to the energising winding – the energising current does not flow through any part of
the connection to the ratio winding. A two stage transformer is used to reduce the phase error to a negligible level
(required for the more critical decades 4 & 5). The combined output is then decades 4 to 7 isolated from 0V and
correctly scaled relative to the main ratio transformer. A twisted pair is used to convey this voltage to the bottom of
winding 5 where it is combined with the twisted pair output from decades 1, 2 & 3.
The reason for the two-stage high pass filters remains a mystery as there should be no DC from the analogue
switches. The filter has a very high input impedance and negligible gain and phase error at 75Hz [1].
C1 Voltage follower
VIN
I1 VOUT
R1
I2 C2
R2 R1=R2 = 100k
C1=C2 = 2μ2
0V
Fig. 2.3 Actively driven high pass filter (two-stage)
The null detector pre-amp [2] and high accuracy voltage followers [3] employ matched bipolar junction transistor
pairs (LM394) at the front end with collector current set at 1mA: noise matching to approximately 350Ω. The
contribution from current noise is, therefore, negligible (< 100Ω source resistance). The voltage noise contribution
from each is about 1nV (RMS) in 1Hz of bandwidth and is comparable to the Johnson noise generated in a 100Ω
resistor at room temperature.
After the low noise pre-amp is a band pass filter for the 75/90Hz carrier frequency and a notch filter for the first
supply harmonic (50/60Hz) followed by a switchable gain voltage amplifier. Both in-phase and quadrature
synchronous rectifiers employ analogue switches in a double-balanced mode [4] to produce a DC output. One of
three low-pass filter bandwidths (10, 1 and 0.1Hz) can be selected for the in-phase signal.
The bridge can be balanced manually (using the front panel lever switches and meter) or automatically with a
micro-controller and efficient algorithm.
The output of the quadrature synchronous rectifier is integrated and then multiplied by the in-phase reference sine
wave using a precision analogue multiplier (AD533). The accurate 90 degree phase shift is implemented with a low
phase error ferrite (gapped) pot core transformer [5]. The output of the pot core is added to the main bridge output
for a continuous quadrature null balance.
The active guard is a high gain block (two-stage, type 1). [3] See section 1.2.
For a bit more detail on the active guard, quad servo and null detector circuits see the monograph “An F18 type
ratio transformer bridge” [6].
1. Part 2, monograph 1: “Two-stage filters”. See, especially, section 5.

2. Part 5, monograph 2: “Low noise BJT pre-amps”.
3. Part 4, monographs 1 and 2: “High gain blocks” and “High accuracy voltage followers”.
5
Part 3: Monograph 7
An F18 type ratio transformer bridge

1. Introduction
In 1983 JDY designed and wound a prototype ratio transformer that took the three stage technique to new heights
of sophistication and ingenuity. The result formed the basis of the seven decade (< 0.1ppm accuracy) F18
resistance thermometry bridge which went on to become the de facto standard in all of the major temperature
calibration labs around the world. It was later superceded by the WIKA model F900 with an extra decade which is
now called the CTR9000 (< 20ppb accuracy) [1]. For some reason the ASL badge remains.
Fig. 1.1 The F18 (Picture courtesy WIKA/ASL Ltd)
Various standards institutions around the world were trying, at the time, to extend the range of platinum resistance
thermometry to (at least) the freezing point of silver (962ºC) [2]. At such high temperatures the slight leakage of
even the best insulating materials required a much lower resistance of the thermometer (2.5Ω or even 0.25Ω at
0ºC). This placed even more stringent requirements on the measurement system - in terms of noise performance
and the ability to detect frequency dependent effects. A major concern was for mutual inductance between the
current carrying pair and the voltage sensing pair – an effect which is more pronounced for low value resistors.
The challenge, then, was for an instrument that could be optimally matched for noise at low resistance and still
maintain sub 0.1ppm accuracy with conventional 25Ω and 100Ω platinum resistance thermometers (with the
relevant reference resistors), operating at the lowest possible frequency.
The resistance of a 2.5Ω SPRT increases to almost 1.3Ω at the gold point and so the range of the F18 was chosen to
be: -
0.0000000 to 1.2999999
This was based on the ready availability of high grade transfer standard resistors with nominal values of 0.1Ω, 1Ω,
10Ω, 25Ω and 100Ω.
The frequency of operation was chosen to be selectable: either half or 1.5 × supply frequency (25/30Hz and
75/90Hz) so that any AC effects could be detected and, possibly, accounted for.
1. www.wika.co.uk
2. Sostmann, H. E: “Fundamentals of thermometry part III. The Standard Platinum Resistance
Thermometer”. Easily found with a google search for ITS90.
1
2. The basic principle of operation
As with the basic three stage design [1] the two energising cores provide the great majority of the magnetic flux [2].
The current flowing in the ratio winding is substantially reduced and the accuracy is increased. The major advance
of the F18 design, compared to the F17, was to eliminate the noise contribution of the followers by connecting the
primary ratio winding directly across the reference resistor. This requires even higher input impedance as the
reference resistance could be up to 100Ω.
Negative capacitors
nVR
RS VR IL
D
I
compensator
RT VT
Fig. 2.1 The F18 basic bridge configuration (simplified)
This approach results in positive feedback and possible instability depending on the source resistance [2]. Stability
can be restored by adding extra resistance in series with the first energising winding. Unfortunately this would
reduce accuracy significantly (or increase the minimum operating frequency). JDY found an elegant and ingenious
solution – a large capacitor in parallel with the extra resistance [2, 3]. At low frequency (where the instability
occurs) the capacitor has little effect and the resistance dominates, maintaining stability. At the operating frequency
the impedance of the capacitor is much reduced and the bootstrapping effect is largely restored – restoring the high
input impedance of the primary and high accuracy.
Stability is also improved by significantly increasing the inductance of the ratio primary windings compared to the
energising windings. This was achieved with another innovation – extra turns around the top core only [2].
In some applications the source resistance could be as high as 100Ω and thus the target input impedance was >1010
Ω (the real part). The main limitation, it was found, was the inter-winding capacitances. It was found necessary to
use PTFE insulated wire and a pair of negative capacitors [4] to neutralise the inter-winding capacitance plus a final
manual adjustment - the “Wolfendale tweek”. This was “not elegant” according to JDY but we were in a hurry to
get it into production! He was also unhappy with the “ratio tweek” – a final 1:1 ratio adjustment. See section 6.
The follower current noise flows through the source resistance and the voltage generated appears across the ratio
primary. Best performance is achieved, therefore, when the noise resistance of the followers is significantly greater
than the source resistance. A noise resistance of 1kΩ was found to be a good compromise.

2. Part 3, monograph 4: “Three-stage ratio transformers”.
2
Part 3: Monograph 7
3. Active guard circuit
The F18 uses the same active guard as the F17 - a high gain block (HGB, two-stage, type 1 [1]) to create a “virtual
earth” point for the bridge. The HGB, standard resistor and thermometer are configured as an inverting amplifier.
The action of feedback ensures that the inverting input of the HGB is maintained at 0V very accurately, setting the
bridge potentials relative to local earth. This is an improvement over a simple direct connection to earth by making
the bridge immune to “leaky” cables and connectors, which can happen in some applications. In the following
diagram, for example, C1 to C3 represent leaky capacitances. If a direct earth connection is made to the same point
then any in-phase component of the impedance of C1 to ground would look like a large resistor in parallel with RS,
affecting the measurement. Similarly C3 acts in parallel with RT. No current flows in C2 as there is no potential
difference. With a virtual earth at the same point the leakage current through C3 is provided by the HGB and C1
simply appears in parallel with the current source – problem solved.
Virtual earth VT
VS
RT
RS
C1 C3
HGB
0V C2
Fig. 3.1 The F series active guard
4. The divider
Fig. 4.1.1 attempts to depict the structure of the main ratio transformer with the usual convention – A winding that
is horizontally adjacent to toroidal core has windings around that core. For clarity the number of turns is specified
alongside. In this case the tricky one is winding 7 – it is partly wound around the top core and then around all three.
Windings 1 and 3: Energising windings of 200 turns of 1.5mm OD wire. It is essential that these are highly uniform
balanced, no-net loop (BNNL) type windings [2].
Windings 2 and 4: Energising secondary windings - for energising decades 3 and 4.

2 turns also of 1.5mm OD wire.
Winding 6: Ratio winding - 24 strands of 0.6mm OD PTFE insulated wire twisted to form a rope and wound 20
times around the top core only and then 20 times again around all three main cores (also uniform BNNL). When
calculating the inductance of this winding it has, in effect, a total of 40 turns. Ten strands are connected in series for
the ratio primary winding and 12 are connected in series for the variable secondary. The two remaining strands are
connected in parallel to provide equalisation for decade 2. Two are used in this way to reduce the source resistance.
Being part of the same rope the ratio between the primary and secondary windings is very accurate.
Winding 7: 12 strands of 0.6mm OD PTFE insulated wire wound 2 turns around TC1 and TC2 plus 4 turns around
TC3 plus 30 turns around auxiliary TC4. In this way it accurately shares the same flux combination as the main ratio
rope [3]. Winding 7 is tapped to act as an inductive voltage divider (IVD) for decade 2 [2].

2. Part 3, monograph 1: “Inductive voltage dividers and ratio transformers – the basics”.
3. Part 3, monograph 2: “Single stage inductors and transformer”. See section 6 on “equalisation”.
3
W5: “Wolfendale tweek”. A small in-phase current/flux is added into the main
(top) core as the final (manual) adjustment to the input impedance.
5 4
200 20
6
Ratio primary 6 6 20
200
20 × (0 – 12)
Winding W6: - 20 Output: VOUT

24 strand; 20 turns around TC3 plus 20
VOUT  0  12  0  9 P
VP V
turns around TC1, TC2 and TC3.
10 100
W7: Decade 2
7 2 × (0 – 9)
TC1 and TC2: Size 11a (mumetal)
TC3: Size 11c (supermumetal; SM200)
TC4: Size 7a (supermumetal; SM100) TC3 7 W7: Equalisation for decades 3 & 4
TC4 2
200 3 TC2 4 2 W4
Energising for decades 3 & 4
Energising windings
200 1 TC1 2 2 W2
Winding W7: -
12 strand; 2 turns around TC1 and
TC2 plus 4 turns around TC3 plus
30 turns around TC4
Fig. 4.1.1 F18 ratio transformer decades 1 and 2 (outline design)
4
Part 3: Monograph 7
4 Output
Hi
Lo
Decade 1
200
10×20
Decade 3
W3
20 W3
10
10×10
I6
Decade 2 Decade 4
10×1
TC8
W4
TC3 TC4 2
TC7
I5
200 TC2 2 W4 W2 100

TC6
I4
200 TC1 2 W2 W1 100 TC5
TC5 – TC7: Size 7a (supermumetal; SM100)

TC8: Size 2b (mumetal)
Fig. 4.1.2 Decades 1 to 4 (outline design)
5
This is also a three-stage design with energising derived from ratio transformer 1. The ratio primary has such high
input impedance that it is easily driven from an equalised decade 2 extra secondary (2 turns). The primary also acts
as an IVD for decade 3. The equalised winding 4 secondary is also tapped as an IVD for decade 4.
Windings 1 and 2: 100 turns of 0.8mm enamelled copper wire (BNNL).
Winding 3: 10 turns of a 12 strand rope of 0.8mm enamelled copper wire. 10 strands are used for the
primary/decade 3 IVD and two are connected in parallel (half the resistance) and used to equalise winding 4.
Winding 4: 1 turn of a 10 strand rope of 0.8mm enamelled copper wire plus 3 extra turns through the 2b auxiliary
core.
For core sizes and other data see appendix 1.
4.3 The resistive multiplying R-2R DAC
Decades 5, 6 and 7, being less critical are implemented using a 12 bit binary multiplying digital to analogue
converter. The input is taken from the outputs of the followers via a two-stage transformer with active drive from
the output side [1]. The main windings consist of 200 turns (BNNL). An extra 2 turns provides the reference
voltage for the ratio tweek. See section 6.
2 To ratio tweek cct.

To MDAC
VIN
200
200
Input from Energising
Followers 200 winding
0V
Fig. 4.3.1 MDAC input stage
The output of the MDAC is then passed through a two-stage high-pass filter (JDY special [2]) to remove the DC
offset. It is then stepped down with two more two-stage transformers, each reducing the output by precisely 100:1.
100:1 100:1
From MDAC via

high-pass filter
Output added in
series with decades
1-4 divider output
Fig. 4.3.2 Step-down stage
The output is then suitably scaled and added in series with the output of the main divider (decades 1 – 4) output.
1. Part 3, monograph 3: “Two-stage IVDs and RTs”. See section 7.

2. Part 2, monograph 1: “Two-stage filters”. See section 2 and, especially, 2.5.1 (example calculation).
6
Part 3: Monograph 7
The first stage of the null detector is a single-stage impedance (noise) matching transformer with 1, 10 and 100Ω
settings providing better than 75% power transfer over the range 0.3 - 300Ω [1]. The low noise (bipolar junction
transistor) pre-amp [2] is followed by notch filters for power supply first and third harmonics plus band-pass filters
for half and three times local supply frequency and pair of analogue switch type synchronous detectors (in-phase
and quadrature) and second order low-pass filters [3]. The in-phase signal is brought to a null either manually
(using the front panel switches and meter) or automatically with a micro-controller. The quadrature null balance
operates continuously with a “quadrature servo” [4].
The quadrature servo consists of an analogue multiplier which takes its in-phase reference AC input from the main
carrier generator circuit. The other input is the integrated output of the quadrature synchronous rectifier. The output
of the multiplier is converted to quadrature and transformed to the required level by a low phase error ferrite pot
core transformer. The primary is the feedback element of an inverter circuit (input voltage converted to a current)
so that it acts as a mutual inductor. The resistor/capacitor series combination (“snubber”) in parallel with the
primary contributes negligible phase error at the operating frequency but limits the gain of the circuit at very high
frequency [5].
Quadrature
output
In-phase
AC input
Quadrature
input (DC)
Multiplier
0V
Fig. 5.1 Final stages of the quadrature servo
The output of the quad servo is then added in series with the output of the main divider (decades 1 – 4) output.
1. Part 3, monograph 5: “Noise matching transformers”. See section 2.

2. Part 5, monograph 2: “Low noise BJT pre-amplifiers”.
4. In the original A7 automatic bridge the mutual inductance of the ferrite pot core was varied by rotating
one element with a servo motor – hence the term: “quadrature servo”.
5. Part 4, monograph 3: “High accuracy amplifiers, integrators and differentiators”. See section 5
7
6. Manual “tweeks”
Two final (manual) adjustments were incorporated: A “ratio tweek” and an input impedance or “Wolfendale
tweek”. Both were justified by the fact that they were simple (low cost) and substantially contributed to the
achievement of the target specification (<100ppb).
6.1 The ratio tweek
The main limitation on accuracy is due to stray flux “leakage”, especially from the ends of the thin strip of high
permeability metallic glass that makes up the energising core. If a part of the first decade rope happens to coincide
with one or both ends the result can be a small non-linearity and a slope error.
Whereas it is possible to design the layout of an instrument [1] to minimise offsets (the instrument “zero”) it is less
practicable to avoid the non-linearity and slope errors. Fortunately both are stable and a simple (low cost) manual
trim is possible for the latter.
VREF/100
10k 10k
1Ω VOUT
22k
Figs. 6.1 The ratio tweek circuit
The ratio tweek takes its (isolated) input from a secondary of the two-stage transformer used to provide the
reference input to the MDAC (see fig. 4.3.1). It is accurately one hundredth (10-2) of the reference voltage (the
difference at the outputs of the followers). The output is added in series with the ratio winding primary with a
further attenuation in the range ±10-4. The total range of slope adjustment is, therefore, ±1ppm. The 1:1 ratio is set
to within ±0.01ppm.
6.2 The input impedance tweek
The three-stage bootstrap results in very high input impedance but not quite high enough for some applications.
VREF
1M 1M
(to “Wolfendale
tweek” winding)
10k
Fig.6.2 The impedance tweek circuit
The reference input is taken directly from the outputs of the voltage followers. The high source resistance presented
to the tweek winding results in a very small in-phase current (and flux), adjusting the real part of the input
impedance. The adjustment is made (1:1 ratio ±0.01ppm) with 100Ω in series with the transformer
primary/follower inputs.
1. A game we called “hunt the nanovolt”: Using the very sensitive null detector to locate and eliminate
transmitters and receivers of stray flux - with twisted pairs or coax connections, correct orientation of
components and routing of connections. The only component that required magnetic screening was the
main ratio transformer and the noise matching transformer.
8
Part 3: Monograph 7
Appendix: Core data
Minimum Effective Effective

Permittance Case Case Case
Core relative magnetic magnetic
AL OD ID axial
size permeability length area
(μH/turn2) (mm) (mm) (mm)
μR LE (mm) AE (mm2)
11a 50,000 279 241 54 112 66 16
11c 200,000 279 363 328 112 66 23
7b 100,000 150 91 76 60 36 12
2b 50,000 57 25 27 24 12 8
9
Part 3: Monograph 8
A 16 bit binary differential capacitance bridge

1. Introduction
The following design is based on an original, by JDY, as part of a high accuracy rotary servo-mechanism. The
basic idea is to drive the centre of a single-stage centre-tapped ratio transformer with a control signal, VC. The
output of the charge amplifier/synchronous rectifier, after suitable loop compensation and a power amplifier, drives
a torque motor/capacitive transducer to achieve a null balance. The resulting angular displacement is proportional
to the control signal. For more detail see the monograph “Rotary capacitive displacement transducers” by the same
author [1].
screen
C1 CF
V1
VC
V’P
C2 VOUT
NP
V2
NS
NS
VR  V1  V2  VP 0V
NP
Fig. 1.1 A differential capacitance bridge with centre-tap drive
The control voltage is derived from a reference voltage with a hybrid ratio transformer/inductive voltage divider
(RT/IVD) for the most significant 8 bits and a resistive (R-2R type) multiplying DAC for the lower 8 bits. The
input to the servo is then a simple 16 bit binary code which is accurately related (proportional) to the angular
displacement required.
Fig. 1.2 A Combined actuator/transducer and interface

(picture courtesy ASL Ltd)
1. Part 1, monograph 3: “Rotary capacitive displacement transducers”
1
2. Outline design
Even more ingenious is the use of a high gain block (HGB) in an “inside-out” voltage follower mode [1 and 2]. The
very high input resistance allows the use of miniature, low cost FET switches for selecting the required RT/IVD
taps. Both inputs of the HGB are maintained at local 0V ensuring high accuracy (no common mode) and avoiding
the need for a floating power supply [2].
The “inside-out” principle is to place the input signal in series with the feedback connection. The action of
feedback is to ensure the two inputs of the HGB are at the same voltage – in this case 0V. The output of the HGB
is, therefore, accurately the same as the control signal but with much lower source impedance. This is exactly the
same as a high accuracy follower apart from the power supply centre is now connected to local 0V and common
mode is not a problem – a direct result of the fact that the control is isolated from local 0V made possible with a
transformer/IVD.
VC
V’P V1
VC
0V
V2
High gain block
Fig. 2.1 The “inside-out” principle.
N3 (8 bits)
Single-stage RT1
V’P 3 8t MDAC
V1
16 × 32t
HGB
32t 1 0V
2 VC
4t 2 1 128t
V2 0V Single-stage RT3
16 × 16t
3
T2 T 1 V3 N1 (4 bits)
16 × 1t V4
2
N2 (4 bits)
128t 1 Two-stage RT/IVD2
Fig. 2.2 A differential capacitance bridge in more detail
According to Kirchhoff’s law the outputs of (centre tapped) transformer RT1 are (fig. 2.2): -
VR V
V1  VC  and V2  VC  R with VR  V1  V2
2 2

2. Part 4, monograph 2: “High accuracy voltage followers”. See section 2.2
2
Part 3: Monograph 8
At balance, assuming an ideal op-amp (fig. 1.1), the output of the charge amplifier is: -
V1C1  V2C2
VOUT   0V
CF
 V   V 
 VC  R C1  VC  R C2  0
 2  2
VC 1 C2  C1
  
VR 2 C2  C1
It is shown elsewhere [1] that the capacitance ratio of a rotary differential capacitive transducer is related to angle
(in degrees) by the formula: -
C2  C1
   
C2  C1 45
VC 
The voltage ratio is, therefore, proportional to angle: 
VR 90
Transformer RT1 has 32 turns for the primary and 32 for each strand of the main secondary winding. The outputs
(see fig 2.2) are, therefore: -
V1  VC  N0VP and V2  VC  N0VP
Where VP refers to the voltage across each strand of the secondary side. With a single-stage transformer VP is only
approximately the same as the primary drive voltage VP  VP  . It is, however, accurately related to the reference
voltage: -
VR
VR  V1  V2  2 N0VP  VP 
2N 0
The integer N 0 refers to the number of strands (32 turns each) either side of the centre tap (connected to VC ). A
practical design (fig. 2.2) employs a 16 strand rope so that the range of choice is: -
N0  1  8
The control voltage is accurately related to VP : -
 90
VC  VP    N 0 or   
90 N0
Where  is the voltage ratio VC VP  determined by the transformer/IVD (RT/IVD2) and MDAC settings.
The range of the servo is determined, therefore, by the range of  and the choice of N 0 .
1. Part 1, monograph 3: “Rotary capacitive displacement transducers”. See section 5.1
3
RT/IVD2 is a two-stage hybrid ratio transformer/inductive voltage divider. Winding 1 is the energising winding
providing most of the flux in toroidal core T1. Winding 3 is the ratio primary (wound around both cores) and is also
used as an inductive voltage divider. The voltage across winding 3 is “equalised” to the reference voltage by direct
connection to suitable taps on RT1. The very small current flowing through winding 3 results in extra flux in the
top core (T2). The resistance of each strand is approximately the same so that ratio accuracy is maintained – the
main principle of an IVD. Winding 2 is a ratio transformer secondary - it is also around both cores so that the
voltage induced is also accurately related to the reference voltage. For more details on IVDs and RTs see the
relevant monographs [1 and 2].
The voltage at the selected tap of IVD winding 3 is, with the ratio of turns shown explicitly (refer to fig. 2.2): -
16t 16t
V3  VC  VP  N1 VP  VC  VP  N1 VP  V3
128t 128t
The integer N1 represents the IVD setting: N1  0  15
Similarly, the voltage at the selected tap of winding 2 is: -
1t 1t
V4  V3  N 2 VP  V3  V4  N 2 VP
128t 128t
The integer N 2 represents the IVD setting: N 2  0  15
16 1
The control voltage is, therefore: VC  VP  N1 VP  V4  N 2
128 128
The output of RT3 depends on the MDAC setting and the ratio of turns. If one assumes an ideal HGB (inverting
input at precisely 0V): -
8t N 4t
V4  VP  3 
32t 256 128t
The integer N 3 represents the MDAC setting: N1  0  255
The polarity of RT3 is chosen so that the control voltage is: -
16 1 N 1
VC  VP  N1 VP  N 2 VP  3 VP
128 128 256 128
1  N 
The ratio  is, therefore:  1 16 N1  N 2  3 
128  256 
It is now clear that the control input is a simple binary code: -
State Code (Hex) Ratio

N1  N2  N3  0 0000  1
N1  8 and N 2  N3  0 8000  0
N1  N 2  15 and N3  255 FFFF   1 (actually:   0.99997 )
1.
1. Part 3, monograph
Monograph: “IVDs
“IVDs1:and RTs and
– theRTs – the basics”
basics”
2. Part 3, monograph 2: “Single-stage inductors and transformers”
2. Monograph: “Single-stage inductors and transformers”
3. Part 3, monograph 3: “Two-stage IVDs
3. Monograph: “Two-stage IVDs and RTs” and RTs”
4
Part 3: Monograph 8
3. Winding suggestions
The design of inductors and transformers for operation with capacitive transducers is much easier than for
resistance bridges. The frequency of operation (typically in the range 1 – 10kHz) is sufficiently high for winding
resistance to be negligible but not so high that interwinding capacitance becomes a problem. Much finer wire can
be used for the windings and, as a result, the toroidal cores can be quite small. The main thing to remember is that
the number of turns must be exact and energising windings should be uniformly distributed around the core
(balanced no-net-loop or BNNL) [1]. Uniform distribution helps to ensure that most of the flux is contained within
the toroid casing. Rope strands are connected in series, paying careful attention to polarity (start/finish).
The following are suggestions and not critical. All windings are with enamelled copper wire [2].
3.1 The single-stage ratio transformer (RT1)
Core size: 4a mumetal.
Winding 1 (energising primary): 32 turns balanced no-net loop (BNNL) of 0.5mm OD wire.
Winding 2 (main ratio winding): 32 turns of a 16 strand rope (BNNL) of 0.25mm OD wire.
Winding 3: 8 turns of 0.25mm OD wire.
The equalising taps (above and below the centre tap) are from one strand each (32 turns) so that the voltage
difference is precisely 2VP.
3.2 The two-stage inductive voltage divider (RT/IVD2) [3]
Both toroidal cores are size 3a mumetal. All windings are with 0.25mm OD enamelled copper wire.
Winding 1 (energising primary): 128 turns (BNNL) around the bottom core only.
Winding 2 (ratio secondary): 1 turn of a 16 strand rope around both cores.
Winding 3(ratio primary and IVD): 16 turns (BNNL) of a 16 strand rope around both cores.
The energising winding bootstraps winding 3 – the induced voltage is approximately 2VP (128:256 turns). The ratio
is “equalised” by direct connection to RT1 (precisely 2VP) with a low resistance twisted pair. The small voltage
difference results in a very small current flowing and a little extra flux in the second core. The current flowing
through the ratio winding does not introduce significant errors (<1ppm) because it is an IVD – the winding
resistances are very nearly the same.
The toroidal core is size 1a mumetal. Both windings are with 0.25mm OD enamelled copper wire.
Winding 1: 128 turns (BNNL).
Winding 2: 4 turns.
Accuracy could be improved to 20 bits by replacing the 8 bit MDAC with a 12 bit device and upgrading RT3 to a
two-stage transformer. It may also be necessary to use slightly larger cores and thicker wire.
1. Part 3, monograph 1: “IVDs and RTs – the basics”.

2. Data on toroidal cores and copper wire is appended to the monograph: “Two-stage IVDs and RTs”.
5
Part 4: Monograph 1
High gain blocks

1. Introduction
A high gain block (HGB) is a differential amplifier with dynamic characteristics designed to ensure stable
operation with negative feedback [1]. The important properties of an ideal HGB include very high gain (at low
frequency), low noise, very high input impedance, low output impedance and insensitivity to power supply
variations. A basic example is the ubiquitous integrated circuit (IC) operational amplifier [2] on which is based a
wide variety of circuit configurations. This monograph includes a few of them as they are also useful building
blocks for many high accuracy applications, including multi-stage HGBs. The multi-stage HGB can be thought of
as an extension of the op-amp concept. An op-amp can be thought of as a single-stage HGB.
Despite the high (open loop) gain of some op-amps the closed loop accuracy is not quite sufficient for some high
accuracy applications.
Stability can also be an issue. Some manufacturers, for example, push gain-bandwidth product to the limit, for
marketing reasons, at the expense of stability. The output resistance combines with any load capacitance (e.g. cable
capacitance) to produce extra phase shift in the feedback loop, reducing stability margin or, even worse, causing
sustained oscillation at high frequency.
Multi-stage HGBs combine two or more op-amp circuits, in series, to achieve much higher open loop gain and,
therefore, improved closed loop accuracy. There are three main types [3]: -
1. One or more “one-plus-integrators” (OPIs) followed by an integrator, each based on an op-amp IC with external
feedback components (resistors and capacitors) to tailor the frequency response. This type is robustly stable even
with significant capacitive load (>1nF).
2. Two or more op-amps (open loop) in series, with “feed-forward”.
3. A hybrid of the first two with the order reversed (integrator first). The first stage is an op-amp, with a fully
differential input, followed by an OPI with RC feedback.
Output
Inputs
Fig.1 Circuit symbols for a single-stage (op-amp) and a multi-stage HGB
One could consider a composite op-amp (e.g. a “long tail pair” with tailored frequency response followed by an op-
amp) as another type of two-stage HGB but the main application is for low noise pre-amplifiers where high
accuracy is not particularly important [4].
Applications of multi-stage HGBs include high accuracy voltage followers [5] inverting and non-inverting
amplifiers, integrators and differentiators [6].
1. Block as in “building block”. Multi-stage HGBs have a sufficiently well defined function and common
characteristics to justify a single concept and circuit symbol.
2. Thomas H. Lee: “IC Op-Amps Through the Ages” rev. Nov. 2002: “The operational amplifier concept
emerged from extensive development of electronic analogue computers in the 1940s.”
3. All three types were developed by JDY in the mid 1980s. Type 2 was published (“High precision
composite op-amps”, Electronics and Wireless world, 1987). It has also appeared in a Comlinear
Corporation data sheet (no author specified) dated April 1994, as a “five-decade integrator”.
4. Monographs: “Low noise BJT pre-amps” and “Low noise JFET pre-amps”.
5. Monograph: “High accuracy voltage followers”.
6. Monograph: “High accuracy amplifiers, integrators and differentiators”
1
The following block diagram embodies the principle of an ideal multi-stage HGB: -
VIN 1 V1 1 V2 1 VOUT
1
1 V IN dt 1
1  V dt
1
2  V dt
2
one-plus-integrators (OPIs) Integrator
Fig. 1.2 Model for a three-stage HGB (type 1)
In principle the order is not important. The integrator is usually the final stage (types 1 and 2) for practical reasons
– an integrator is better able to drive a capacitive load.
A very good mathematical model for an N-stage HGB, over a wide range of frequency (typically 1Hz to 1MHz), is
the transfer function in the usual complex representation s  j  : -
N 1
 1 
H N s   OUT  1 
V 1

VIN   1s   2s
At very low frequency the “DC gain” of the op-amps combine to provide enormous open loop gain. In the
following example (N = 4) this is a minimum of 1020 (100dB or 105 per op-amp). As the frequency of the test signal
increases the gain starts to fall at a rapid rate (Nth order) but then reverts to first order before it passes through 0dB.
This ensures closed loop stability with 100% negative feedback. At higher frequency (typically 5MHz) the op-amps
run out of steam and slope increases again.
Fig. 1.3 Bode plot of the open loop gain of a four-stage HGB
In practice there is not much advantage in going beyond a three-stage HGBs though this author has built
and tested a five-stage HGB (just for the fun of it) in (very carefully constructed) prototype form.
2
Part 4: Monograph 1
2. Feedback, stability and accuracy (general theory)
The most basic and frequently employed circuits employ negative feedback with two resistors or a resistor and
capacitor. These are analysed with the following assumptions: -
a). Infinite input impedance and zero output impedance.
b). Perfect common mode and power supply rejection.
c). Linear behaviour (e.g. no slew rate limiting).
The circuit is inverting or non-inverting depending on which input is connected to the source 0V (V2 = 0V for the
inverting mode and V1 = 0V for the non-inverting mode).
Whereas the input and output are usually thought of as single-ended (i.e. relative to local 0V) they are best thought
of as quasi-differential signals: the input and output are a pair of connections (twisted or co-axial) which are routed
to prevent magnetic interference and earth loops [1].
PSU
V2
0V
V1 VOUT
I Z1
VE
Z2 I
Fig. 2.1.1 An HGB with negative feedback
V1  VE VE  VOUT
According to Kirchhoff’s and Ohm’s laws: I 
Z1 Z2
H s  
VOUT
By definition the open loop transfer function is:
V2  VE
 Z  Z
From the first equation: VOUT  VE 1  2   V1 2
 Z1  Z1
VOUT
From the second: VE  V2 
H s 
 V  Z  Z
Combine the two to eliminate VE : VOUT  V2  OUT 1  2   V1 2
 H s   Z1  Z1
  Z  1   
From which: VOUT 1  1  2    V2 1  Z 2   V1 Z 2
 
  Z1  H s  

 Z1  Z1
1. Monograph: “High accuracy voltage followers”. For examples of signal routing see sections 3 and 6.
3
I shall define a parameter  s  which is the reciprocal of the feedback factor and may be a function of frequency.
This will simplify the algebra: -
  s  
F s   and  s     V2  s   V1 2
Z1 1 Z Z
1 2  VOUT 1 
Z1  Z 2 F s  Z1  H s   Z1
 Z  H s  
VOUT  V2  s   V1 2  
Z1  H s    s  
The output is, therefore:

Z  H s  
Inverting mode V2  0V  :
VOUT
  2  
V1 Z1  H s    s  
VOUT  Z 2  H s  
Non-inverting mode V1  0V  :  1   
V2  Z1  H s    s  
The term in the second bracket is of particular interest as it determines the closed loop stability and accuracy in
both cases.
VOUT  Z 2 
  2 Ds  and  1   Ds 
VOUT Z
V1 Z1 V2  Z1 
H s  Ls  H s 
The “D” factor is, therefore: Ds    where Ls   H s F s  
H s    s  Ls   1  s 
Ls  is the “loop gain” – the transfer function of the HGB and feedback network combined.
The “D” factor expresses the difference between the actual and the ideal closed loop transfer functions. If the
magnitude of the loop gain is infinite then Ds   1 and the ideal transfer functions are as expected: -
Ls    
VOUT Z VOUT Z
 2 and  1 2
V1 Z1 V2 Z1
One can extract the error component with a little algebra: -
 s 
Ds   1  or Ds   1 
1
H s    s  Ls   1
At low frequency the loop gain is very large and Ds   1 but at some high frequency one would expect the closed
loop transfer function to have a resonant peak, depending on the stability margin, before falling below 0dB.
Finally, note the requirement which must relate to stability: -
Ls 
Ds    what if Ls   1?
Ls   1
The accuracy and stability of each type of HGB are investigated in general in the relevant sections in this
monograph. Further detail can be found in other monographs [1 and 2]

2. Monograph: “High accuracy amplifiers, integrators and differentiators”.
4
Part 4: Monograph 1
2.2 The Bardayquist stability criterion.
The condition Ls   1 is the Barkhausen criterion for sustained oscillation (i.e. 100% positive feedback). The
general Nyquist criterion for stability, on the other hand, is quite complicated as is JDY’s preferred method: the
Routh-Hurwitz test. For our purposes the condition for adequate stability can be summarised in a short statement
(the “BarDayQuist” stability criterion) and illustrated with the aid of a new type of plot of frequency response in
the complex plane (the “BoDayQuist” plot).
The loop consisting part of the positive real axis and the locus representing the loop gain, Ls  , in the
complex plane, must not enclose, nor get too near to, the -1 point.
The new plot combines the best features of the Nyquist plot and the Bode plot. The magnitude is on a logarithmic
scale (radial distance) so that the huge gain remains visible. The phase shift is retained on the same plot so that the
phase margin can also be seen. The following is a rather extreme example chosen to illustrate its utility.
Imaginary axis
1024
1018
1012
106
-1 point
Real axis
unity gain circle
Fig. 2.2.1 The “BoDayQuist” plot illustrates how the stability criterion is satisfied (4-stage HGB)
H f 
The radial distance is: R  log10
H MIN
5
The example shown is based on the LF356 (GBWP = 5MHz with low frequency gain of 100dB) with an HGB OPI
frequency of 16kHz.
The gain, at very low frequency, is due to four op-amps in series (1020). As frequency increases (from DC) the
locus advances clockwise with phase (lag) increasing rapidly to very nearly 360 degrees (90 degrees per integrator
stage). The gain drops rapidly and, as it approaches the unity gain circle, the phase lag reduces to just over 90
degrees. The locus passes through the unity gain circle (0dB) with a phase margin of about 60 degrees. As the gain
continues to fall the phase starts to increase again, due to the limited GBWP of the op-amps and the locus spirals
into the centre. With the model employed each of the four op-amp stages contributes up to 90 degrees plus another
90 degrees from the integrator stage. The ultimate phase shift is 450 degrees (5 × 90). The locus eventually
approaches the centre point along the negative imaginary axis (not visible unless the range of frequency is extended
upward).
If any part of the HGB overloads the gain drops and the locus could collapse towards the centre and pass through
the -1 point. This can be avoided by making the locus to first unwind. This is achieved with back-back diodes
across the OPI capacitors in type 1 HGBs [1]. When the diodes conduct each OPI becomes a follower stage with a
gain of 1 and negligible phase shift. Type 3 HGBs (two-stage) also employ back-back zener diodes to avoid non-
linear oscillation or latch-up. See section 4.3.
Type 2 HGB circuits (two-stage) appear to be inherently stable, though very fast op-amps should be avoided.
Fig.2.2.2 A conventional Nyquist plot for comparison with fig. 2.2.1
Various plots in these monographs were easily produced with a spreadsheet using complex number arithmetic
(IMSUM, IMPRODUCT etc). One worksheet, including slider controls, is provided for entering various parameters
(e.g. coefficients of transfer functions, overall gain, start frequency and number of decades). A second worksheet
does all the calculations in stages. Further worksheets contain the various plots required (magnitude, phase,
Nyquist, BoDayQuist and closed loop magnitude and errors). For a copy please contact the author.
1. Monograph: “High accuracy voltage followers”. See section 6 and fig. 6.1.1.
6
Part 4: Monograph 1
2.3 Phase margin
The part of the BarDayQuist criterion “too near to the -1 point” is a little vague. A useful and quantitative measure
of stability is the phase margin. This is the difference between the actual phase shift, UG , as the magnitude of the
loop gain passes through 0dB (unity gain), and that required for sustained oscillation. The phase shift for sustained
oscillation is 360 degrees but 180 degrees is due to the feedback being applied to the inverting input. The definition
of loop gain does not include this hence the critical point in the complex plane is a magnitude of 1 and a phase shift
of 180 degrees (the -1 point). One is usually concerned with phase “lag” which, for historical reasons, is defined as
a numerically negative angle and clockwise rotation from the real axis. For convenience, however, it is usual to
express the phase margin as numerically positive and in degrees. The usual definition of phase margin is: -
 PM deg   180  UG deg 
In the Nyquist plot fig. 2.3.1, for example, the phase margin is the angle between the negative real axis and the line
joining the centre point to the point at which the locus passes through the unity gain circle (about 60 degrees).
A general rule of thumb is to aim for a minimum (worst case) phase margin of 45 degrees. The result is a
resonant peak but this is not a major problem in many applications. Most high accuracy applications employ a low
distortion sine wave signal which does not contain components at the frequency that would excite that resonance.
Unity gain circle
Phase margin
Total phase lag, θUG
Fig. 2.3.1 The definition of phase margin
Calculations can often be performed most conveniently (with a scientific calculator) using the polar form. For an
integrator with an “extra pole”, for example (see section 3.1.1): -
exp  j  2
Ls   cos E exp  j E  with tan E    E
1 1
 
 B s1   E s   B s1  j tan E   B
The integrator contributes -90 degrees and the pole an extra phase lag which is a function of frequency.
cos  E  tan E 
Ls   1  UG   E B
B cos  E 
Given  B and the extra phase,  E (e.g. 45 deg), it is possible to calculate the (max) time constant of the extra pole.
7
2.4 The size of the resonant peak
The ideal phase margin is 90 degrees – the ideal HGB is an integrator, at least as the loop gain passes through 0dB.
A lower phase margin results in a resonant peak in the closed loop response. Computer modelling allows one to
explore the trade-off between closed loop accuracy and stability with considerable precision. There is, however, a
simple calculation that provides an approximate value for the size of the peak.
I shall assume that as frequency increases the magnitude of L(s) decreases monotonically through 0dB. There
should be only one frequency UG at which the magnitude is 1. Denote the phase shift at that frequency as UG . In
polar form the loop gain, with a magnitude of 1 is, therefore: -
LUG   1  LUG   exp  jUG 
The “D” factor at this particular frequency is, therefore: -
LUG  exp  jUG 

DUG   
LUG   1 exp  jUG   1
From basic complex number theory: -
exp  jUG 
DUG  
1

cos UG  j sin UG  1 1  cos UG 2  sin 2 UG
DUG  
1
With a bit of algebra this simplifies:
2  2 cos UG
1
  
Now 1  cos 2  2 cos  2
with the remarkably simple result: DUG    2 cos UG  
  2 
Clearly as UG approaches   the magnitude becomes infinite. The cosine function is even so that it does not
matter if one defines the phase shift as positive or negative. In the case that the phase margin is 45 degrees the total
phase lag of the loop is 135 degrees: -
UG  135 degrees  DUG  
1
 1.31
2 cos67.5
The peak at this frequency is approximately 31% (+2.3dB).
Fig. 2.4.1 The resonant peak with a phase margin of 45 degrees [1]
1. Spreadsheet: “Second order low-pass”
8
Part 4: Monograph 1
3. Some operational amplifier circuits
3.1 Operational amplifiers
An integrated circuit op-amp typically consists of a number of amplifier stages which combine to provide an open
loop gain, at low frequency (typically < 100Hz), between 10 5 and 106 (100 – 120dB). For most types the input is
differential and the output is single-ended (relative to local 0V). The ideal device has zero noise, infinite input
impedance, zero output impedance and is immune to common mode and power supply variations.
Internally compensated op-amps incorporate a small capacitor which introduces a “dominant pole”
(typically: f P  10  100Hz ) resulting in a first order low-pass characteristic over a wide range of frequency. This
ensures stable operation with any amount of feedback. The approximate frequency at which the gain falls below
0dB is known as the “unity gain bandwidth” or “gain-bandwidth product” (GBWP) and is specified in Hz  f B  .
Low cost devices have a GBWP which is typically between 1MHz and 10MHz. At higher frequency  f E  an “extra
pole” is responsible for more phase shift resulting in (with 100% feedback) a phase margin less than 90 degrees. An
op-amp is thus, in effect, a high gain, second order, low-pass filter with very widely separated real poles. In the
complex representation s  j  : -
  E  H s  
G
with  P  G B and  P   B   E
1   P s 1   E s 
The open loop frequency response of a typical family of devices is illustrated in the following diagrams. The
LF356, for example, has a GBWP of 5MHz (at 20ºC) with a generous phase margin of 75 degrees. The LF357 is
basically the same device with reduced internal compensation (by a factor of four). As a consequence it has a
minimum closed loop gain of four unless external compensation is employed [1]. The advantage of reduced
internal compensation is a closed loop response that is, given the same feedback factor, four times faster and four
times more accurate. The generous phase margin, combined with a relatively low output resistance, also means that
the LF356 can easily drive a load capacitance of 1nF (typically 10m of cable) and remain stable, even with 100%
negative feedback.
Fig. 3.1 Open loop frequency response for a family of op-amps (gain (dB) and phase (degrees)) [2].
Higher performance op-amps (especially in terms of GBWP) are available but these tend to be quite expensive,
dissipate more power and require RF design techniques, skills and test equipment. Non-linear characteristics (e.g.
overload and slew rate limiting) also contribute to instability. These effects are difficult to predict or model. It is
recommended that prototypes are thoroughly tested: “the proof of the pudding is in the eating”.
1. Monograph: “High accuracy voltage followers”. See section 6.3. See also section 3.6 of this monograph.
2. Courtesy National Semiconductor (data sheet DS005646).
9
3.1.1 Op-amp models
A very good model of an op-amp, for a small sinusoidal signal (no slew rate limiting), from DC to the unity gain
frequency (and a little beyond) is a high gain, first order, low-pass filter followed by an extra low pass
characteristic. In the complex representation s  j  : -
0    B  H s   Ps  with  P 
G G
 G B
1   P s  B
Where G is the gain at very low frequency (i.e. the “DC gain”),  P is the time constant of the dominant pole
(internal compensation),  B is the gain-bandwidth product (GBWP) and Ps  represents the fact that the op-amp
transistors are “running out of steam”. The extra term, Ps  , depends on the type of op-amp and load capacitance.
Some manufacturers push the internal compensation to the limit, increasing the GBWP, for marketing reasons, at
the expense of closed loop stability. At low frequency the effect of Ps  is negligible and a good model is a high
gain first order low pass filter: -
  B  Ps   1  H s  
G
1   P s 
This model is useful for calculating closed loop errors, at low frequency, for circuits employing a single op-amp.
Over a wide range of frequency (typically four decades), above the dominant pole but below the GBWP, the op-
amp behaves like a fast integrator. The response is linear but the time constant varies significantly with temperature
(typically ≈ -0.5%/deg C): -

1   P s   B s  H s  
1
with  B  P
 Bs G
In practice the contribution to the magnitude, due to Ps  , is small and a sufficiently good model is a low-pass filter
or integrator with an “extra pole”: -
0    B  H s    H s  
G 1
and   B
1   P s 1   E s   B s1   E s 
The latter is useful for calculating the stability margin for single op-amp circuits. The polar form (magnitude and
phase) proves most convenient: -
exp  j  2 cos E 
with tan E    E
1 1 1
 and  
 Bs  B 1   E s 1  j tan E  exp  j E 
Also, with this model, the unity gain frequency is lower than the gain-bandwidth product.
cos E  cos E 
H s    UG   B cos E 
 B B
HGBs Type 2 and 3 rely on the full open loop characteristic of at least one op-amp and the extra pole model is
required.
With type 1 HGBs one need not include the extra pole in the model. The overall gain is designed to be well below
0dB at the GBWP. Type 1 HGBs are employed where robust stability is required, especially when driving cable
capacitance.
10
Part 4: Monograph 1
The LF356, for example, has a GBWP of 5MHz and phase margin of 75 degrees with negligible load capacitance.
The extra pole is responsible, therefore, for an extra 15 degrees of phase lag (the ideal integrator would provide a
phase margin of 90 degrees). From section 2.3: -
tan E 
Ls   1  E B
cos  E 
1 tan E 
B   3.2  108 s   E   B  8.9  10 9 s
2f B cos E 
This corresponds to an extra pole at around 18MHz. The LF356 is a “good” op-amp.
A large capacitive load results in another pole and an increase in phase shift. The output resistance, R and load
capacitance, C, combine to form another first order, low-pass filter and the high frequency model becomes: -
  B  H s  
1
with  L  RC
 B s1   E s 1   L s 
In practice the two poles combine as a single extra pole, as the second order term is usually negligible: -
 E s  1 and  L s  1   L E s 2  1 and 1   E s 1   L s   1   E   L s
The phase shifts from each mechanism simply add and the single “extra pole” model is usually sufficient. The polar
form, however, provides a convenient method of calculation without this approximation: -
exp  j  2
H s   cos E exp  j E cos L exp  j L 
 B
with tan E    E and tan L    L

The total phase shift is: T    E  L The phase margin (degrees) is, therefore:  PM  90   E   L 
2
Consider, for example, the unity gain frequency: -
H s   cos E cos L   UG  cos E cos  L 

1 1
 B B
The LF356 has an output resistance of 50Ω. What is the maximum load capacitance for a minimum phase margin
of 45 degrees (15 + 30) with a feedback factor of 100%?
0.966  0.866
H s   1  UG  cos E cos L  
1
 2.61  107
B 3.2  10 8
tan15 tan30
E   1.03  108 s and  L   2.21  108 s
UG UG
L 2.21  108
The maximum capacitance is, therefore: CMAX    442 pF
R 50
11
3.2 The integrator
With feedback an op-amp can be used to implement a practical integrator circuit which is an excellent building
block as part of a multi-stage HGB.
The main advantage is that the gain falls below 0dB well before the frequency at which the op-amp runs out of
steam (the extra pole) and the effect of load capacitance is much reduced. Compared to the op-amp itself the
integrator characteristic extends to a much lower frequency and the time constant is more stable over temperature.
As the final stage of an HGB overall stability is assured by design, even with a large capacitive load.
One other important characteristic is the effect of the virtual earth. The action of feedback is to maintain both inputs
at approximately the same voltage (i.e. 0V). The op-amp common mode input is very small and error due to the op-
amp common mode rejection ratio is negligible. The virtual earth can also act as a summing junction - it is possible
to add two or more inputs with extra input resistors.
Virtual earth CI
RI
VIN
VOUT
0V
0V
Time constant
τI = RICI
PSU
Fig.3.2.1 A simple integrator
With an integrator one expects the gain to continue increasing as frequency decreases limited only by the finite gain
of the op-amp. This sets a lower limit to the operating frequency. For a low frequency analysis I shall assume,
therefore, the high gain, first order, low-pass filter model for the op-amp (not including the extra pole): -
  B  H s  
G
with  P  G B
1   Ps
Where G is the “DC gain”  P is the time constant of the dominant pole and B  1  B is the GBWP in rads-1. From
section 2.1 the “D” factor is, therefore: -
H s 
Ds  
G

H s    s  G   s 1   P s 
The feedback elements are a capacitor and resistor with a time constant which is usually much larger than the op-
amp time constant: -
  s   1 
1 1
Z1  RI and Z 2  with  I  RI CI and  I   B
sCI Is
1
  
Ds   1  
1 1
The “D” factor is, therefore:   B s  B 
 G G I s I 
12
Part 4: Monograph 1
The effects of the real components are usually irrelevant as they do not contribute to the phase error. One could, for
 1 B 
example, define a parameter      1 . The transfer function becomes: -
 G I 
1
1 1  
T s   Ds  
1
1      B s 
Is Is  G I s 
1
1  
Extract a factor 1    : T s  
1
1    B s 
 I s  G I s 
Where: -
 I   I 1      I : indicating a slightly increased time constant of the integrator, compared to the ideal. This
could be easily mitigated with a corresponding reduction in the value of the resistor RI or increase in CI.
B
 B    B : indicating a slightly reduced op-amp time constant (a small increase in the GBWP).
1 
Multiply top and bottom by G I s and a factor of  I s cancels and, noting that G I   B : -
G G
T s   
1  G I s  G I B s 2
1  G I s 1   B s 
The result is, as expected, a finite gain at very low frequency (the same as the op-amp) with a second order low-
pass characteristic with two widely separated poles. The “D” factor has a broad, flat, band-pass characteristic with,
to a very good approximation: -
G I s
Ds  
1  G I s 1   B s 
As frequency increases (from about 1Hz to 1kHz) and well below the GBWP the term B s is negligible and the
circuit looks increasingly like an integrator followed by a first order high-pass filter characteristic with a positive
phase error: -
 1  G I s   1  1 
 B s  1  T s      1  
 I s  1  G I s   I s  G I s 
At some critical frequency the phase error is zero: -
1 1
  B s  0  C 
G I s G I B
Note that the effect of the correction factors 1    cancel.
Typical values for an integrator as part of an HGB are: -
G  105  I  105 s (16kHz) and  B  3.2  108 s (5MHz)
fI fB
The critical frequency is, in more convenient form: f C   900 Hz
G
13
1
At higher frequency the term become negligible and the transfer function becomes an integrator followed by
G I s
a first order low-pass characteristic with negative phase error: -
1  1  1
G I s  1  T s     1   B s 
 I s  1   B s   I s
In more convenient form, with frequency in Hz, the phase error is sufficiently small (<15 degrees is tolerable as
part of an HGB) over a wide range of frequency (typically < 1Hz to 1MHz): -
 1   f f 
 f  f B  T s  
fI
1 j  I   
G  I s   Gf f B  
Fig. 3.2.2 Phase error versus frequency (Hz)
One can conclude a rule of thumb: -
With a good op-amp and stable feedback components, a reasonably good model for this circuit (as part of an
HGB type 1) is an ideal integrator:-
I 1
   B  T s  
G Is
If, on the other hand, one requires an accurate integrator, with low phase error (e.g. as part of a high
accuracy oscillator or filter circuit) then one should employ a two-stage HGB (type 2) rather than a single
op-amp [1 and 2].
1. Monograph: “High accuracy amplifiers, integrators and differentiators”. See section 4.

2. Monograph: “A circuit for measuring tanδ”.
14
Part 4: Monograph 1
The best way to assess stability is an examination of the loop gain. At high frequency the best model of the op-amp
is an integrator with an extra pole (see section 3.1.1): -
1  1 
  B  H s    
 B s  1   E s 
The feedback factor is also a function of frequency: -
 s
 F s  
1 Z1
Z1  RI and Z 2   I with  I  RI CI and  I   B
sCI Z1  Z 2 1   I s
The loop gain is, therefore: -

1  1   I s 
Ls   H s F s     
 B s  1   E s  1   I s 
The phase shift of the feedback network is positive (phase advance) and the total phase shift around the loop is
reduced (e.g. compared to a voltage follower). One can employ the polar form for which no approximation is
necessary: -
1 1
Is  1   1 
  cos I exp  j I  with tan I  
1
 1    1  j
1Is  Is    I   I
The loop gain, in polar form, is, therefore: -
exp  j  2
Ls   cos E exp  j E cos I exp  j I 
 B
cos E cos I  cos E cos I 

The magnitude is: Ls    1  UG 
 B B

The total phase shift is: T     E   I The phase margin (degrees) is:  PM  90   E   I
2
In practice the phase shift due to the feedback network is small and the extra pole is the more significant (typically
a maximum of 45 degrees with a capacitive load) and the unity gain frequency is not much lower than the GBWP.
1
 I  0 and  E  45  UG   0.707B
2 B
The unity gain frequency is usually much higher than the integrator characteristic frequency so that the phase shift
due to the feedback network is small and the phase margin is about the same as a voltage follower: -
tan I  
1
 1   I  0   PM  90   E
 I UG
The result is a resonant peak at high frequency. The closed loop gain is well below 0dB at this frequency so that
any resonant peak is unlikely to cause a problem. This is not the case with a one-plus-integrator circuit as the next
section demonstrates.
It is recommended, therefore, that the integrator is the final stage of a multi-stage type 1 high gain block,
especially with a capacitive load.
15
3.3 The one-plus-integrator (OPI)
A one-plus-integrator is the same circuit as an integrator with the input connections reversed. The feedback factor
is exactly the same as for the integrator as is the low frequency phase error analysis.
Time constant, τI = RICI CI
RI
0V
VOUT
VIN
0V
PSU
Fig. 3.3.1 A one-plus integrator circuit (OPI)
From the general analysis, section 2.1, the closed loop transfer function is: -
VOUT  Z 2   1 
 1   Ds   1   Ds 
1
Z1  RI and Z 2  and  I  RI CI 
sC I VIN  Z1   Is 
The reciprocal feedback factor and “D” factor are the same as for the integrator (section 3.2) and so the transfer
function is, from DC to a frequency approaching the GBWP of the op-amp: -
1
 1   
 B s  1  T s   1 
1 1
1     B s  B 
  I s  G G I s I 
I shall again extract a real factor 1    resulting in a small overall drop in gain and a band-pass correction factor
with two widely separated poles: -
 1  1  G I s   1  1  G I s 
T s    1   
2  1   
1    I s  1  G I s  G I B s   1     I s  1  G I s 1   B s  
At low frequency the OPI looks like a first order low-pass filter with the same DC gain as the op-amp: -
 1  G 
 I s  1   B s  1  T s     
1   1  G I s 
As frequency increases the gain falls, first order, and the circuit behaves like an integrator: -
 1  1
  I s  1  T s   
1

G  1     I s
Over a wide range of frequency, the magnitude of the band-pass characteristic is very nearly one and the result is a
reasonably accurate one-plus-integrator (see fig. 3.2.2 for typical phase error): -
G I s  1  1 
 1  T s   
1
  I s   B s  1  
1  G I s  G I B s 1    I s 
2
G
16
Part 4: Monograph 1
At high frequency the feedback factor is very nearly 100% and the closed loop gain levels out to very nearly one.
To investigate the phase margin and any resonant peak, therefore, one needs the high frequency model of the op-
amp: an integrator with an extra pole: -
1  1 
  B  H s    
 B s  1   E s 
The analysis is exactly the same as for the integrator circuit.
exp  j  2
Ls   cos E exp  j E cos I exp  j I 
 B
with tan E    E and tan I  

1
 I
cos E cos I  cos E cos I 

The magnitude and unity gain frequency are: Ls    UG 
 B B

The total phase shift is: T     E   L The phase margin (degrees) is:  PM  90   E   L
2
The consequence is the possibility of a resonant peak above 0dB which could be a problem. It is
recommended, therefore, that an OPI circuit is not used to drive a capacitive load – the last stage of a multi-
stage HGB (type 1) should be the integrator.
Calculating the unity gain frequency and phase margin may take a few iterations: -
a). First estimate the unity gain frequency: UG  1  B
b). Calculate the phase shifts based on this estimate: tan E    E and tan I   1  I 
cos E cos I 
c). Recalculate the unity gain frequency and repeat: UG 
B
The solution should converge after two or three iterations.
Rule of thumb: -
One can conclude that, as part of an HGB, with a low capacitance load, a reasonably good model of the
circuit, over a wide range of frequency (typically < 1Hz to 1MHz) is a one-plus-integrator: -
I
   B  T s   1 
1
G Is
17
3.4 The non-inverting amplifier and voltage follower
Both feedback components are resistors which simplifies the analysis. A major source of error, however, is the
finite common mode rejection ratio of the op-amp. This circuit, therefore, has limited high accuracy applications.
For a voltage follower R2  0 or R1   (or both).
R2
R1
0V
VOUT
VIN
0V
PSU
Fig. 3.4.1 A non-inverting amplifier circuit
From the circuit analysis, section 2.1 the closed loop transfer function is: -
VOUT  R2 
 1   Ds  with   1  2
R
Z1  R1 and Z 2  R2 
VIN  R1  R1
I shall assume the high gain, low-pass filter model for the op-amp for low frequency (below the unity gain
frequency). The reciprocal feedback factor is now real and constant so that the “D” factor is: -
H s 
1
  
 H s    Ds  
G
  B  1    B s 
1   Ps H s     G 
1
 R   
The transfer function is, therefore: T s   1  2 1    B s 
 R1  G 
One can extract a factor 1    : -

  R  1   
 1  T s   1  2 
1
   with  B  B
G  R1  1    1   B s  1 
The result is a slightly reduced gain with a first order low-pass characteristic. The bandwidth is approximately
inversely proportional to gain (hence the gain-bandwidth product is approximately constant). At low frequency, to
a very good approximation: -
 B s  1  T s   1 
 R2  1

R1  1  


 1   B s   B s 
2

 
In more convenient form with frequency in Hz: -

 f  f  
2
 R  1
f  f B  T s   1  2   1  j   
 R1  1    f B  f B  

The phase error is first order with respect to frequency and too large for some amplifier/follower
applications. Also, this does not include errors due to the finite CMRR.
18
Part 4: Monograph 1
With a low gain (R2 < R1 and a feedback factor approaching 100%) the extra pole results in a low phase margin and
a resonant peak at high frequency. The high frequency model of the op-amp is required: an integrator with an extra
pole: -
1  1 
  B  H s    
 B s  1   E s 
From section 2.1 the closed loop response is: -
H s 
T s    Ds  with Ds  
R2 1 R
 and   1  2
R1 H s    1   B s1   E s  R1
Ds  
1
The result is a second order response:
1   B s   B E s 2
The transfer function is, in standard normalised form s  j N  : -

1  B
T s  
1 1
with natural frequency  N  and damping ratio  
1  2s  s 2  B E 2 E
To achieve the minimum phase margin of 45 degrees the unity gain frequency must be the same as the extra pole.
The total phase shift is 135 degrees (90 degrees from the integrator and 45 degrees from the extra pole). For a
typical bode plot, with 45 degrees phase margin, see fig. 2.4.1. With a loop gain magnitude of one the result is: -
H s  1  1    1  
 Ls  
1
UG      E    1  E  2
E   B s  1   E s  j B  1  j  B
1  B 1 1
    0.42
2 E 2 2
Worst case is the voltage follower (100% feedback:   1 ). If one assumes that the extra pole is entirely due to the
output resistance and capacitive load the capacitance to produce this peak can be estimated. The LF356, for
example, has output resistance of around 50Ω and a GBWP of 5MHz: -
1
  1 and  B   3.2  108 s   E  2 B  4.5  108 s
2f B
E 4.5  108
and  E  RC  CMAX    900 pF
R 50
In practice the op-amp internal extra pole contributes about 15 degrees of extra phase lag so that the maximum
contribution from the load capacitance is 30 degrees. The maximum capacitance is about half this estimate. See
section 3.1.1 for the more precise calculation. For improved accuracy and stability see section 3.6.
As a rule of thumb a voltage follower based on an internally compensated single op-amp does not have
sufficient accuracy or stability for many high accuracy applications. Fortunately a two or three-stage HGB
with 100% feedback and floating power supply provide a simple and cost-effective solution [1].
To eliminate CMRR errors employ the inverting mode (see section 3.5). To reduce phase error employ a
two-stage HGB [2].
1. Monograph: “High accuracy voltage followers”

19
3.5 The Inverting amplifier
With an inverting amplifier both op-amp inputs are maintained at local 0V and common mode is not an issue. With
two or more input resistors the circuit can also perform addition.
R2
R1
VIN
VOUT
0V
0V
PSU
Fig. 3.5.1 The inverting amplifier circuit
From the circuit analysis, section 2.1 the closed loop transfer function is: -
  2 Ds 
VOUT R
Z1  R1 and Z 2  R2 
VIN R1
The reciprocal feedback factor and “D” factor are the same as the non-inverting amplifier so that, at low frequency,
the transfer function is: -
1
R   
  B  H s    T s    2 1    B s 
G
1   Ps R1  G 
I shall again extract a factor 1    : -
 R2   
 1  T s     with R1  1   R1 and  B  B
1
 
G R1  1   B s  1 
The result is an inverting amplifier with a slightly reduced gain and a first order low-pass characteristic. At low
frequency, to a very good approximation: -
 B s  1  T s   
R2
R1
1   B s   B s 
2

 f  f  
2
R  1
f  f B  T s    2   1  j   
R1  1    f B  f B  

Once again the main problem is the phase error (quadrature). The in-phase error is likely to be negligible compared
to the resistor tolerance and drift. For lower phase error employ a two-stage HGB (usually type 2) [1 and 2].
The high frequency analysis (resonant peak due to the extra pole) is the same as for the non-inverting mode but
unlikely to be an issue. The minimum feedback factor is typically 0.5   2 for an inverter (gain = -1).

20
Part 4: Monograph 1
3.6 A voltage follower with external compensation
Voltage followers, based on a single (internally compensated) op-amp, do not usually provide sufficient accuracy
for many applications (see section 3.4). A de-compensated op-amp (reduced internal compensation) can, however,
with a suitable feedback network, boost the closed loop accuracy and stability. When combined with an advanced
OPI stage, for example, the result is a useful two-stage high accuracy voltage follower (HAVF) [1].
The basic idea is to employ the higher gain to boost accuracy at low frequency but reduce the feedback factor, at
high frequency, to maintain stability. This is often referred to as “external compensation”: -
R2 = 2k2
V1
C1 R1
LF357
VOUT
VIN
100nF 100Ω 0V
PSU
Fig. 3.6.1 A voltage follower with a de-compensated op-amp
R2
VOUT V1
R1
C1
VIN VIN
Fig. 3.6.2 The feedback network
The best way to analyse the circuit is to think of the feedback network as a simple RC filter (with VIN = 0) so that it
can be defined in the normal way: -
1  R1C1s 1   1s
 F s   with  1  R1C1 ,  2  R1  R2 C1 and  2   1
V1
VIN  0  
VOUT 1  R1  R2 C1s 1   2 s
More generally, therefore, based on voltage differences: V1  VIN  F s VOUT  VIN 
Combine the definitions of F(s) and H(s) to eliminate V1: -
VOUT  H s VIN  V1   VOUT  H s VIN  F s VOUT  VIN   VIN 
H s F s 
With a little algebra the closed loop transfer function is: T s  
VOUT

VIN H s F s   1
Ls 
The loop gain is, therefore (from section 2.1): T s    Ls   H s F s 
Ls   1
1. Monograph: “High accuracy voltage followers”. See section 6.3
21
A very good model of the op-amp, from DC to the unity gain frequency, is a high gain, low-pass filter with an extra
pole: -
G  1 
0    B  H s  
VOUT G
   with  P  G B 
VIN  V1 1   P s  1   E s  B
The closed loop transfer function is, therefore: -
G1   1s 
T s  
G1   1s   1   P s 1   2 s 1   E s 
This looks a little daunting but the time constants (and relevant frequencies) are usually widely separated: -
 P   2  1   B   E
With reduced internal compensation the maximum gain (minimum typically 105) and the frequency of the extra
pole remain the same but the time constant of the dominant pole is reduced. With the LF357, for example, the
GBWP is increased to 20MHz (compared to 5MHz for the LF356) which is also about the same as the extra pole
(see section 3.1.1). The relevant parameters are: -
G 1
G  105 and  E   B  8  109 s   P  G B   8  10 4 s and f P   200 Hz
B 2 P
For the recommended component values in fig. 3.6.1, for example, the external compensation kicks in at a
frequency determined by the time constant  2 .
 2  R1  R2 C1  2.3  104 s and

1
Typical values are: f2   700 Hz
2 R1  R2 C1
1
Similarly the time constant of the zero is 1  R1C1  105 s and f1   16kHz
2R1C1
Fig. 3.6.3 Loop gain with typical component values (see fig. 3.6.1)
22
Part 4: Monograph 1
The resulting loop gain is flat at low frequency (typically DC – 200Hz). As frequency increases the op-amp
dominant pole and the feedback pole cause the gain to drop with a second order slope. The zero at 16kHz causes
the slope to revert to first order (causing the phase lag to reduce to nearly 90 degrees) as the loop gain magnitude
falls below 0dB. This occurs well below the frequency of the extra pole resulting in a phase margin approaching 90
degrees. The unity gain frequency (of the loop gain) is sufficiently low that this circuit can easily drive substantial
load capacitance (≈ 1nF) with no stability problems.
1012
106
Unity gain circle
Fig. 3.6.4 The BoDayQuist plot of loop gain with typical component values
The detailed analysis is not as complicated as it looks. At low frequency the R1C1 series snubber circuit has high
impedance and the resistor R2 provides 100% feedback. In practice a moderately low value for R2 is required due to
the op-amp input capacitance. The closed loop response is the same as a voltage follower with the LF357 gain-
bandwidth product  f B  20MHz . Repeated from above, for convenience: -
1   1s G  1  H s F s 
F s   and H s     and T s  
1   2s 1   Ps 1   Es  H s F s   1
H s 
 E s  1s   2 s  1  F s   1 and T s  
G

H s   1 G  1   P s
The result is lower in-phase and quadrature error, by a factor of four, compared to the fully compensated
LF356  f B  5MHz : -
1
 
 E s  1s   2 s  1  T s   1    B s   1    B s
1 1
 G  G
f  f 2  T s   1 
1 f
j
G fB
23
With a minimum DC gain of 105 the in-phase error is less than 10ppm and, in many applications, the effect of
quadrature error is negligible with a reasonably good phase sensitive null detector.
Even if one takes into account the rapid fall in gain due to the second pole (≈700Hz) the next significant error term
is small. Repeated from above: -
G1   1s 
T s  
G1   1s   1   P s 1   2 s 1   E s 
 E s  1s  1  T s  
G
G  1   P s 1   2 s 
1    2   P 2 2 
1

 T s   1   P
1
s s   1    B s   B 2 s 2
 G G G  G
f2
f  f1  T s   1   j
1 f

G f B f B f2
The main application is designed to operate at a frequency of 400Hz [1]. The resulting extra in-phase error is
around +11ppm, though one should not rely on this to cancel, with any great accuracy, the -10ppm error due to the
finite open loop gain.
At high frequency (above f1 : the zero of the feedback network) and approaching the extra pole: -
G 1s
  B   P s   2 s  1s  1  T s  
G 1s   P s1   E s  2 s
  
T s  
1
With a little algebra: with  B  P 2   B 2   B
1   B s1   E s  G 1 1
This is precisely the same second order, low-pass response of the basic voltage follower (see section 3.4) with a
GBWP reduced by the factor  2  1  1. With the values recommended this is typically: -
 2 R1  R2
  23
1 R1
The LF357 GBWP of 20MHz is reduced to below 1MHz (≈ 870kHz) and well below the extra pole, even with
significant load capacitance. The stability margin is an almost perfect 90 degrees (see fig. 3.6.4).
The stability margin is best analysed in the polar form of the loop gain. The unity gain frequency is much higher
than the dominant pole and a sufficiently accurate model for the op-amp is an integrator with an extra pole. The
contribution to phase shift from the feedback may be significant, however, and the loop gain model is: -
1  1  1   1s 
 P s  1  Ls     
 B s  1   E s  1   2 s 
24
Part 4: Monograph 1
At high frequency the phase shift of the feedback network is expected to be almost 90 degrees phase lag due to the
pole and approaching 90 degree phase advance due to the zero. The network is best described, therefore, with
(small) corresponding angles   90    etc: -

 2 s  1s  1  1  1s  1  j tan1  with 1  etc.
2
In which case do the following: -
 1   1s   1s  1  1  1s   1  1  j tan1    1 cos2 
F s            exp  j 2  1 
 1   2 s   2 s  1  1  2 s   2  1  j tan2    2 cos1 

with tan1   and tan2  
1 1
and  2   1  2  1 and 1   1  0 etc.
 1  2 2
The net phase shift is always negative (phase lag). The loop gain is: -
1  1        cos E cos2 
Ls     F s   1 exp  j    E  2  1   with tan E    E
 Bs 1   E s   2 B   2  cos1 

The total phase shift is: T     E  2  1 The phase margin (degrees) is:  PM  90   E  1  2 
2
 1 cos E cos2 
Ls  
 2 B cos1 
All the angles are small so that a reasonably good estimate for the unity gain frequency is: -
1
Ls   1  UG   5.43  106 (about 865kHz and consistent with the previous estimate)
 2 B
From which a reasonably good estimate of the angles are, in degrees: -
 E  8  109 s   E  2.5  cos E   0.999
 2  2.3  104 s  2  0.0  cos2   1.000
1  105 s  1  1.0  cos E   1.000
The total phase margin is, therefore, a generous:  PM  90  3.5  86.5 degrees
This example confirms the assumption that the phase contribution due to the dominant pole (≈ 200Hz) is negligible.
Also, the 90 degree phase lag of the pole due to the feedback network (≈ 700Hz) is almost entirely cancelled by the
89 degree phase advance of the zero, at the unity gain frequency.
External compensation makes it possible to employ a de-compensated op-amp to boost accuracy, at low
frequency, and achieve much better stability margin with a capacitive load.
25
3.7 An advanced OPI2
A useful variant of the one-plus-integrator is a quasi-differential input, single-stage HGB based on an op-amp with
a two-stage RC network [1]. In this case the network is used to provide feedback with reduced phase error
compared to a single-stage RC filter. At low frequency the feedback signal passes through the network
V1  VF  and any errors in the subsystem (e.g. non-linearity, offset, noise) are thereby eliminated. At high
frequency the capacitors of the network provide 100% feedback with stability margin inherent to the op-amp (the
same as a voltage follower). A typical application is in combination with a voltage follower (boosted accuracy: see
section 3.6) with overall 100% feedback to implement a moderately high accuracy voltage follower [2] capable of
driving significant capacitance.
VIN VOUT
H(s) subsystem
2×R
V1
2×C
VF
Network F(s)
Fig. 3.7.1 An advanced OPI provides feedback to correct subsystem error
The output of the feedback network can be derived by the same method of the previous section: -
V1  VOUT  F s VF  VOUT 
 VOUT  H s VIN  V1   H s VIN  VOUT  F s VF  VOUT 
H s VIN  H s F s VF
With a little algebra: VOUT 
1  H s 1  F s 
The circuit is designed to provide feedback around a subsystem for which, at low frequency, the output is nearly
the same as the input with a small error represented by the parameter  . This may be a complex number, possibly a
function of frequency, or a random number to represent noise: -
and   F  VF  1   VOUT with   1

1
F 
RC
H 1   
T s  
VF
With a little algebra the overall transfer function is: 
VIN 1  H  HF
At low frequency the feedback network transfer function is nearly one with a small error represented by the
parameter  : -
  F  F s   1   with   1
H s 1    1 
 T s   
1  H s   H s   H s  1    1 H s   
1. Monograph: “Two-stage filters”. For a basic low phase error filter see section 2.2.
26
Part 4: Monograph 1
At low frequency the open loop gain of the op-amp is large and the term  is likely to be very small. Dividing top
and bottom by 1   has negligible effect on the size of the error terms. To a good approximation, therefore: -
  F  H s   1 and   1  T s   1 
1
 
H s 
The dominant error term is due to the finite open loop gain of the op-amp. Closed loop accuracy is limited,
therefore, by the advanced OPI2 (open loop gain and CMRR) and not the subsystem.
For a more detailed analysis for a typical application see the monograph “High accuracy voltage followers” [1].
A basic OPI could be used in the same way – as a quasi-differential input single-stage HGB in a feedback loop. It is
interesting, therefore, to compare the open loop characteristic of both circuits - with VF connected to 0V. From
above, repeated for convenience: -
H s VIN  H s F s VF
VOUT 
1  H s 1  F s 
H s 
VF  0  T s  
VOUT

VIN 1  H s 1  F s 
For a basic OPI, over a wide range of frequency (typically < 1Hz to 1MHz), one can simplify the algebra with the
basic integrator model of the op-amp (see section 3.3 for detail): -
Fs
H s   and F s    1  F s  
1 1
with  F  RC
 Bs 1Fs 1Fs
F
   B  T s   1 
1

G Fs
With a two-stage low-pass filter one obtains a significantly different result. From the monograph “High accuracy
filters” [2]: -
3 F s  1  F2 s 2
F s   with   RC  1  F s  
 F2 s 2  3 F s  1 F
 F2 s 2  3 F s  1
With the same model for the op-amp and a little algebra: -
1   P s   B s  H s  
1
 Bs
 F2 s 2  3 F s  1
 T s  
 B s F2 s 2  3 F s  1   F2 s 2
At a frequency well above the filter cut-off but below the op-amp GBWP the  F2 s 2 terms dominate: -
 F2 s 2
 F s  1 and  B s  1  T s  
1

 B s s    s
2 2
F
2 2
F  Bs  1

2. Monograph: “Two-stage filters”. For a basic low phase error filter see section 2.2.
27
Once again the result is a voltage follower with a bandwidth limited only by the op-amp. The gain is very nearly
one (the O in OPI2). More generally, for a frequency well below the GBWP the s3 term is negligible: -
 F2 s 2  3 F s  1
 B s  1   B s F2 s 2   F2 s 2  T s  
 B s3 F s  1   F2 s 2
Also, the filter cut-off frequency is much lower than the GBWP so the term 3 B F s 2 is also negligible: -
 F2 s 2  3 F s  1
 B   F  3 B F s 2   F2 s 2  T s  
 B s   F2 s 2
There is a transition frequency depending on the filter cut-off frequency relative to the GBWP. For a frequency
above this value: -
B  F2 s 2  3 F s  1
  2   B s   F s  T s  
3 1
2 2
1  2 2
F Fs
2 2
Fs Fs
The result resembles an OPI plus an extra double integrator. A more appropriate name could be an OPI+I2.
At lower frequency the double integrator term becomes small compared to the single integrator: -
B  F2 s 2  3 F s  1 3 F
 F s  1 and     s   2 2
s  T s    
1
F
2 B F
 Bs  B  Bs
At very low frequency the slope reduces to first order.
For an LF356 (GBWP = 5MHz), for example, with a filter cut-off frequency of 16kHz [1]: -
The op-amp and filter time constants are:  B  3.2  108 s and  F  105 s
The transition frequency from first order to second order roll-off is: -
1 B
fT   51Hz
2  F2
This is about the same as the dominant pole and above the lowest possible operating frequency. For this
circuit, unlike the basic OPI, one needs the low frequency model of the op-amp, including finite DC gain, if
one wishes to predict the low frequency response accurately: -
The resulting algebra is complicated and it is necessary to resort to a spreadsheet model. One may as well employ
the fullest model, from DC to the GBWP, with the extra pole, as this will also model the high frequency response,
including any resonant peak.
0    E  H s  
G
1   P s 1   E s 
T s  

G  F2 s 2  3 F s  1 
With a little algebra:
 
 F2 s 2  3 F s  1 1   B s 1   E s   G F2 s 2
28
Part 4: Monograph 1
Typical values are [1]: -
Op-amp DC gain: G  105
Gain-bandwidth product (5MHz):  B  3.2  108 s
Filter frequency (16kHz):  F  105 s
Extra pole (with some capacitive load also ≈ 5MHz):  E  3.2  108 s
The result is slightly under-damped second order low-pass characteristic which levels out to a gain of one at the
filter frequency. There are two resonant peaks: at the transition from flat to second order roll-off (at ≈ 50Hz) and at
high frequency, due to the extra pole (at ≈ 5MHz).
Fig. 3.7.3 Open loop characteristic of an advanced OPI+I2 [2]
106
Unity gain circle
Fig. 3.7.4 The BoDayQuist plot (phase margin ≈ 90 deg.)

2. Spreadsheet: “Advanced OPI”
29
4. Multi-stage HGBs – some practical circuits
4.1 Type 1 HGBs
A type 1 multi-stage HGB consists of one or more one-plus-integrators followed by an integrator, each based on an
op-amp with external feedback. The final stage is the integrator as it is better able to drive a capacitive load (see
section 3.2).
Almost any type of low cost internally compensated op-amp will work well though a moderately fast type is
recommended (e.g. the JFET input LF356 with a gain-bandwidth product of 5MHz and slew rate of 12V/μs). The
main applications are for high accuracy voltage followers [1] and active guard circuits [2].
one-plus-integrators (OPI) C2
τ1 = R1C1
VIN R2
VOUT
C1 C1
Integrator
R1 R1 τ2 = R2C2
0V 0V
Fig. 4.1.1 A three-stage HGB (type 1)
It is shown in section 3 that the OPIs and integrators can be described, over a wide range of frequency (with
reasonably good op-amps typically 1Hz to 1MHz), by relatively simple transfer functions. These do not need to
include the finite op-amp gain at low frequency or the extra pole at high frequency. The overall open loop
characteristic can be described, therefore, by the following transfer function in the usual complex
representation s  j  : -
N 1
1  1 
 H N s   1 
1
   B 
G   1s   2s
With two or more stages (N > 1) the algebra is simplified if one adopts the normalised form s  j 1  : -
H N s  
1  s N 1 with 
2
s N
1
The value of  determines the stability margin and, to a certain extent, low frequency errors. These are
investigated in detail in the relevant monographs [1 and 2].
The physical layout of the circuit is important – coupling from the output stage to the input stage must be kept to a
minimum (especially magnetic – use twisted pairs and triples). Fig. 4.1.2 illustrates an example [1].
A low noise front end is also important – for best performance use a composite amplifier based on a matched BJT
long tail pair to implement the first OPI (see fig. 4.1.3).

30
Part 4: Monograph 1
Low noise HGB module Two-stage HGB module
FPSU decoupling
FPSU triple
+VS
0V
Input
pair -VS
VOUT
R2 I
C1
Output
R1 C2 R3 C3
pair
Feedback twisted or coax pair
Fig. 4.1.2 A three-stage HGB configured as an inside-out voltage follower
In normalised form s  j 1  : H 3 s  

1  s 2 with 
2
s 3
1
R1  100 C1  100nF R2  10k C2  1nF R3  3.9k C3  1nF
f1  16kHz 1  105 s f 2  41kHz  2  3.9  106 s   0.39
31
2×100nF
2k2 +15V
0V
-15V
47k 47k
0V
470R VOUT
330pF
100nF
LM394
100R
6k8
All diodes 1N4148

BC109
36k 8k2
Fig. 4.1.3 A low noise OPI front-end
The BJTs are operating at 0.1mA each and generate less than 2 nV Hz (RMS).
The feedback capacitor is quite large as the resistor needs to have a low value (to keep Johnson noise low).
For more details see the monograph “Low noise BJT pre-amplifiers” by the same author [1].
1. Monograph: “Low noise BJT pre-amps”.
32
Part 4: Monograph 1
Type 2 HGBs employ the inherent integrator characteristic of typical op-amps to achieve a similar result to the type
1 HGB. Unlike the type 1 HGB, however, closed loop stability is not so predictable. A circuit that works well with
one type of op-amp may oscillate when another type is plugged in. The LF353 dual JFET op-amp is recommended
(GBWP of 4MHz and 13V/μs slew rate). The main applications are for inverting configurations: low phase error
amplifiers, integrators and differentiators [1] where the load capacitance is small (< 50pF).
VE Z2
VIN Z1
½LF353 VOUT
H1(s) V1 H1(s)
k
0V 4k7 ½LF353 0V
Fig 4.2.1 A two-stage (type 2) HGB in inverting mode
The combined gain of two op-amps, at low frequency (< 100Hz), is so high that the closed loop error is too small to
be measured unless the feedback factor is extremely low (very high closed loop gain). There is usually no point,
therefore, in employing the very low frequency model. For the low frequency analysis I shall assume the basic
integrator model for each op-amp: -
 B s  1  H1 s  
1
 Bs
V1  kH1 s VE  
k
For the first op-amp: VE
 Bs
VOUT  H1 s V1  VE   V  V 
1
For the second op-amp:
 Bs 1 E
Substitute the first equation into the second: -
1  k  1  k 
s  j B  VOUT    VE  VE    1  V
 Bs   Bs   B s   B s  E
One normally defines the open loop transfer function from the non-inverting input to the output: -
1  k 
H 2 s   
VOUT
 1  
VE  B s   B s 
For a direct comparison with type 1 HGBs normalise to the OPI time constant s  j  B k  : -
B 1 s
1  and  2   B  H 2 s  
k ks2
This is exactly the same as the type 1 two-stage HGB with: k 
High frequency analysis (extra pole) can be found for various circuits in the relevant sections [1].
33
With a type 3 HGB the order is reversed (integrator first) to take advantage of the differential input stage of the op-
amp. Latch-up is avoided and recovery from overload ensured with a limiter circuit based on a pair of zener diodes.
The main application is for a high gain differential amplifier [1] as part of a quadrature servo [2]. If a low gain is
required (×1 or ×10) the feedback factor must be reduced with a low value resistor across the inputs [1].
Differential
input ½LF353 ½LF353
VOUT
VIN H1(s)
1k 2n2 C
Integrator
OPI
2 × 7v5 10k R
0V
0V
Fig. 4.3.1 A two-stage HGB (type 3)
As with a type 2 HGB, even with a closed loop gain of 1000, the loop gain with two op-amps is so high that the
low frequency (<100Hz) error is too small to be measured. The low frequency characteristic can be modelled,
therefore, with an integrator followed by a one-plus integrator: -
1  1 
 B s  1  H 2 s   1   with 1  RC
 B s   1s 
Over most of the frequency range of interest (typically 100Hz to 1MHz), in normalised form s  j 1  : -
1 s 
2 B  H 2 s   with   B
s 2
1
This is the same as the type 1 two-stage HGB. The optimum value for  depends on the feedback factor [1]. The
OPI time component values in fig. 4.3.1 are for a maximum gain of 1000 [1].
A type 3 HGB should be used with a low feedback factor (typically < 0.01) - the extra pole of the first op-amp and
the resonant peak of the OPI could result in instability at high frequency. A low feedback factor ensures that the
loop gain is well below 0dB at the extra pole frequency and the effect of the extra poles is negligible.

2. Monograph: “Null detectors – the basics”. See section 6.
34
Part 4: Monograph 2
High accuracy voltage followers (HAVFs)

1. Introduction
High accuracy voltage followers (HAVFs) have numerous applications. Some resistance bridges, for example,
employs a pair of HAVFs to drive the primary windings of a ratio transformer.
High accuracy followers

+
Ratio transformer
RS nS
nP
+
D
Null
Virtual earth detector
RT
+ nS RT

nP RS
Fig. 1.1 Outline schematic of the ASL F16 and F17 series resistance bridges
Followers can also be used to eliminate the problem of loading of a ratio transformer secondary winding by
providing the necessary load current. The HAVF forces the transformer secondary voltage across the two-terminal-
pair reference resistor RS. With virtually no current passing through the transformer secondary much thinner wire
and semiconductor switches can be used.
High accuracy followers

Ratio transformer
nS 2 RT

nS 1 nS 1 RS
RS
0V
Null detector
nS 2
RT
Fig. 1.2 HAVF being used to accurately drive a load (ASL model F25)
It is also possible to implement very accurate active guarding, often necessary when working at the level of parts
per billion. The follower provides the drive current flowing through the stray capacitance from the active guard to
local 0V (“ground”). The active guard screens the sensitive connection.
Sensitive connection
+
Stray capacitance
Fig. 1.3 HAVF used as an active guard
1
2. Theory of operation
For more detailed analysis of feedback and stability see the monograph “High gain blocks” [1].
2.1 The limitations of a conventional voltage follower
The two main problems with a conventional voltage follower, employing a single op-amp, are the limited common
mode rejection ratio, open loop gain and stability margin.
H(s) VOUT
VIN
0V
PSU
Fig. 2.1.1 A conventional voltage follower based on a single op-amp
It is shown elsewhere [2] that the closed loop transfer function, at low frequency, based on the high gain low-pass
filter model of the op-amp is, to a very good approximation: -
1
 
  B  H s    T s   1    B s 
G 1
1   Ps  G 
Where G is the gain at very low frequency (i.e. the “DC gain”),  P is the time constant of the dominant pole
(internal compensation) and B  1  B is the gain-bandwidth product (GBWP) in radians/s.

1  f  f  
2

f  f B  T s   1   1  j  
 G  f B  f B  

The real (in-phase) error term is a minimum 1/G and, therefore, limited by the DC gain of the op-amp. The
imaginary (quadrature) error, increases in direct proportion to the frequency and is usually much less of a problem.
 
With an LF356 op-amp, for example, the DC gain can be as low as 100dB G  105 resulting in an in-phase error
of up to 10ppm and too large for many applications. The GBWP is 5MHz so that, at an operating frequency of
75Hz, the quadrature error is approximately 15ppm (15µrad).
The finite common mode rejection ratio, which could also be as low as 100dB, contributes similar errors. See the
next section.
The very wide bandwidth and low stability margin, especially when driving a capacitive load (e.g. long cables)
results in a resonant peak at high frequency (typically 5MHz) [2] and severe practical problems. The solution is to
employ a robustly stable (type 1) multi-stage high gain block (HGB).
1. Monograph: “High gain blocks”. See, especially, section 2.

2. Ibid: See section 3.4
2
Part 4: Monograph 2
2.2 Common mode rejection and the “inside-out” configuration
The main problem with the conventional follower is common mode due to mismatch in the differential input stage.
The inputs of the HGB vary with respect to the power supply, resulting in a significant error. Fortunately there is a
simple and elegant solution to this problem – the “inside-out” mode of operation. The basic principle is to place the
input signal in series with the feedback connection. The action of the feedback is the same – the output of the HGB
ramps up or down until its inputs are the same. Only then does the output stabilise. In the case of the inside-out
follower the power supply is “floating” and is driven to follow the input voltage, thus eliminating the common
mode completely.
Feedback Feedback
0V
VIN VOUT
VOUT
HGB HGB
VIN 0V
CG
Important!
PSU Floating PSU
Conventional Inside-out
Fig. 2.2.1 Conventional follower and the inside-out follower
The earth symbols indicate the part of the circuit which may be connected to local 0V while testing (e.g. the signal
generator and/or oscilloscope inputs) or are at or near local earth potential. In practice a high accuracy system
should have only one earth connection.
At first sight it appears very strange that the output pin of the op-amp (final stage of the HGB) is connected to
earth. Old habits die hard and this author admits to many head-scratching moments before realising that the ‘scope
test lead earth was clipped to the PSU 0V.
The capacitance from the centre of the PSU to ground is also marked as important. This is because it is usually
quite large, due mainly to the capacitance across the power supply mains transformer. The capacitive load can
combine with the op-amp output resistance resulting in extra phase shift and reduced stability margin. The open
loop frequency response of the HGB is designed to mitigate this problem. For more details on stability see the
monograph “High gain blocks” [1].
2.3 The floating power supply (FPSU)
Each follower requires its own floating power supply. This need not be expensive (the power required is usually
quite low) but the capacitance to ground is an important factor. The best type of commercially available PSU for
this task employs linear regulators with low noise and ripple and a mains transformer with low capacitance between
primary and secondary. The author has found that a power supply transformer with split sections is perfectly
adequate for all but the most demanding applications. For the ultimate in performance a special PSU can be
constructed using a small (high frequency) transformer, with separated or screened windings, operating from a
higher frequency AC power source. It is also possible to use rechargeable batteries with guarded screening to
minimise this problem but this is not very practicable.
1. Monograph: “High gain blocks”.
3
2.4 Closed loop transfer functions
N 1
 1 
H N s   1 
1
The open loop transfer function for an N-stage HGB is: 
  1s   2s
I.e. the HGB consists of N-1 “one-plus-integrators” (OPIs), followed by a final integrator. The algebra is simplified
if one employs the normalised form (normalised to the OPI time constant): -
s  j 1 with

  2 1  H N s  
1 s
N 1
1 s N
The closed loop transfer function for an N-stage voltage follower is, therefore: -
H s  1  s N 1
TN s    N
H s   1 s  1  s N 1
The parameter    2 1 has a significant effect on stability margin (N > 1). The values chosen are at the upper
limit of what is practical and must, therefore, be regarded as a maximum in each case: -
In normalised form s  j 1   for 60% or +4dB peaking
T1 s  
1
Single-stage: N=1 No limit
s  1
s 1
Two-stage: N=2 T2 s   1
s  s  1
2
s 2  2s  1
Three-stage: N=3 T3 s   0.4
s 3  s 2  2s  1
s 3  3s 2  3s  1
Four-stage: N=4 T4 s   0.2
s 4  s 3  3s 2  3s  1
s 4  4s 3  6s 2  4s  1
Five-stage: N=5 T5 s   0.15
s 5  s 4  4s 3  6s 2  4s  1
Fig. 2.4.1 Frequency response of N-stage voltage followers (N = 2 to 5 left to right).
4
Part 4: Monograph 2
2.5 Error analysis
As above the algebra is made easier if one normalises to the time constant of the OPIs s  j 1  .
s N
The transfer function for an N-stage follower is: TN s   1 
s N  1  s N 1
For a single op-amp (N = 1) the approximation is fairly simple. At low frequency: -
s
N  1 and s  1  T1 s   1   1  s  s 
2
s  1
This simplifies to a more convenient form, with frequency in Hz: -
2
f  f 
T1 s   1  j   
1
with f2  (the gain-bandwidth product of the op-amp)
f2  f2  2 2
For two-stage HGBs and higher the algebra is a little more subtle. The denominator of the error term is
approximately 1 so that for N > 1: -
s N s N
N  1 and  s  1  TN s   1 
N

1  N  1s

 1  s N 1  N  1s  O s 2 
1  s N 1
N  1 and s  1  TN s   1  s N   N  1s N 1
The first two error terms are sufficient for both the real (in-phase) and imaginary (quadrature) components: -
In more convenient form with frequency in Hz  f1  1 2 1  : -

N N 1
 f   f 
N  1 and f  f1  TN s   1    j    N  1 j 
 f1   f1 
I shall employ the maximum values for  .

2 3
 f   f 
Two-stage: N=2,   1  T1  f   1     j  
 f1   f1 
The largest term is real (in-phase). The imaginary term is third order and represents a much smaller phase error
than would be the case with a follower based on a single op-amp.
3 4
 f   f 
Three-stage: N=3,   0.4  T3  f   1  j 0.4   0.8 
 f1   f1 
It is unlikely that N > 3 designs offer any further advantage.
The reader may notice that the transfer functions and, therefore, the error analysis have the same form as
an N-stage low pass filter [1]. See part 2 [1].
1. Monographs: “Two-stage filters” and “Three-stage filters”.
5
3. Power supply and signal wiring.
The HGB is carefully constructed so that the input and output signal are twisted or co-axial pairs. The power supply
also enters the HGB as a twisted triple. The output pair and FPSU triple must be kept a safe distance (a few cm)
away from the input and feedback pair (certainly not bunched in the same loom). This ensures minimal problems
with stray magnetic flux. The following diagram illustrates the correct layout for power supply and signal wiring.
The arrows indicate the presence of go/return current which, being physically close, means a minimum of external
magnetic flux.
FPSU and triple
Output pair
Input pair
Feedback pair
Feedback pair
Fig. 3.1 HAVF with more detail of signal pair and PSU triple routing
4. Measuring the accuracy of an inside-out follower
For testing purposes it is possible to reverse the input signal connections so that the 0V (earth potential) is on the
HGB inverting input side and the final stage op-amp output is driven, relative to the power supply. The action of
the feedback is the same and there is no difference, as far as the internal circuitry of the follower is concerned. Both
inputs are now at, or close to, 0V (very low common mode) and a low noise, high gain, differential amplifier can be
used to boost the error signal so that it can be measured with an AC voltmeter or spectrum analyser. The amplifier
needs its own power supply. The HAVF floating power supply must still be allowed to float - one must not connect
FPSU 0V to earth.
VIN
VOUT
to AC voltmeter
×1000 low noise amp
Fig. 4.1 Error test configuration (signal generator connections reversed)
6
Part 4: Monograph 2
5. Stability considerations
HAVF stability is a complex topic when one considers non-linear effects such as slew rate limiting and recovery
from power-up and overload conditions. It has been found in practice, however, that a number of simple measures
can be taken so that stability is ensured even with complex and variable load impedance in a wide range of
applications.
The main trade-off is, not surprisingly, between frequency of operation and accuracy. One of the main (and most
demanding) applications of high accuracy voltage followers, for example, is platinum resistance thermometry,
operating at 25Hz or 75Hz for a 50Hz supply (30Hz or 90Hz for a 60Hz supply). At this low frequency it is
possible to achieve sub-ppm accuracy while maintaining stability, even while driving a ratio transformer energising
winding (with resonant leakage inductance and inter-winding capacitance).
Capacitance bridges usually operate at a frequency of 1-10 kHz. At the higher end it is still possible to achieve
sufficient accuracy for HAVFs to be useful (e.g. as drivers for active guards).
The general principle is to design for an HGB with the lowest possible unity gain frequency while still achieving
the necessary open loop gain at the frequency of operation. In many cases a two or three stage design is adequate
and the gain is well below 0dB at a frequency much lower than the range where capacitive and resonant loads
become an issue.
Recovery from overload is made possible by connecting a pair of back-back diodes in parallel with the feedback
capacitors (apart from the last stage). In normal operation the voltage across the diodes is very small and they
present high impedance. When overloaded, however, the diodes conduct and the one-plus integrators revert to a ×1
follower, allowing the circuit to recover. This can be understood with the aid of a BarDayQuist plot of the open
loop gain of an extreme example (4-stage HGB) [1]. As each OPI overloads the phase shift reduces by 90 degrees
and the locus collapses to the centre without passing through the critical -1 point.
Imaginary axis
1012
109
106
103
-1 point
Real axis
unity gain circle
Fig. 2.4.1 The “BoDayQuist” plot illustrates how the stability criterion is satisfied (4-stage HGB)
1. Monographs: “High gain blocks”. See section 2

7
6.1 A two-stage HAVF
A two-stage HAVF has sufficient accuracy for an active guard and providing a virtual earth (see section 1). The
circuit, fig. 6.1.1 is shown in normal test configuration (not error test) with a load resistor (see section 3).
Op-amps: 2 × LF356 or similar

Time constants R1  10k C1  1nF  1  105 s
2
R2  10k C2  330 pF  2  105 s  1
1
FPSU decoupling: 2×100nF ceramic per op-amp.
6.2 A three stage HAVF with low noise front end
This three-stage design employs a low noise front end (see fig. 6.2.1 and 6.2.2) with collector current set at 0.1mA.
It has sufficiently high accuracy, low noise current and low DC offset for driving the energising windings of an F18
type ratio transformer [1] (see also fig. 1.1). It is also shown in normal test configuration with a load resistor: -
Op-amps: 3 × LF356 or similar
Time constants R1  100 C1  100nF  2  105 s (reduced resistance for lower noise)
R2  10k C2  1nF  1  105 s
2
R3  10k C3  330 pF  2  3.3 106 s   0.33
1
FPSU decoupling: 2×100nF ceramic per op-amp.
With the current source (0.2mA) and collector resistances shown the noise resistance is approximately 1kΩ.
The same design can be used to drive the energising windings and ratio primary of a two or three-stage ratio
transformer [2]. Best noise performance is achieved when the front-end is matched to the source resistance. This
usually involves increased collector current with lower voltage noise and higher current noise (lower noise
resistance). Collector current should be no higher than 1 or 2mA (each), however, to ensure low self-heating and
maintain low DC offset [3].
1. Monograph: “An F18 type ratio transformer bridge”.

2. Monograph: “An F17 type ratio transformer bridge”.
8
Part 4: Monograph 2
Two-stage HGB module
FPSU decoupling
FPSU triple+V
S
0V
-VS
Input
pair I
Output
R1 C1 R2 C2 pair
Feedback pair
Fig. 6.1.1 A two-stage HGB with routing detail (normal operation)
9
Low noise HGB module Two-stage HGB module
FPSU decoupling
FPSU triple+V
S
0V
Input
pair -VS
VOUT
R2 I
C1
Output
R1 C2 R3 C3
pair
Feedback twisted or coax pair
Fig. 6.2.1 Three-stage HGB with low noise front end
10
Part 4: Monograph 2
2×100nF
2k2 +15V
0V
-15V
47k 47k
0V
470R VOUT
330pF
100nF
LM394
100R
6k8
BC109 All diodes 1N4148
36k 8k2
Fig. 6.2.2 A low noise OPI front-end
The BJTs are operating at 0.1mA each and generate less than 2 nV Hz (RMS).
For more details see the monograph “Low noise BJT pre-amplifiers” by the same author [1].
11
6.3 A low cost follower with moderately high accuracy
Whereas not as accurate as a multi-stage inside-out follower this circuit may be found useful with an accuracy
approaching 1ppm. The cost is reduced by operating from a normal power supply so that the main limitation is the
common mode rejection ratio (CMRR) of the first op-amp. The main application is for a low cost resistance bridge
(c.f. ASL model F25) depicted in fig. 1.2.
VIN LF356 100nF Follower T3(s)

V2
T1(s)
V1 100Ω LF357
2 × 10nF
2k2 RS
VF
Network T2(s) 2 × 1kΩ
I
Secondary
Fig. 6.3.1 A low cost voltage follower
The first stage is an op-amp with a two-stage feedback network employed as a single-stage HGB. I have chosen the
name “advanced OPI2” by analogy with the one-plus integrator [1] which is described in some detail elsewhere [2].
The signal being fed back is the voltage sensed across the reference resistor. At high frequency the network
provides 100% feedback with plenty of stability margin despite the second stage follower. At low frequency the
overall error (difference between VIN and VF) is very small due to the full open loop gain of the first op-amp (small
difference between VIN and V1), the low phase error of the two-stage network (small difference between V1 and VF)
and the moderately high accuracy of the second stage follower (small difference between V2 and VF).
The second stage follower employs an op-amp with reduced internal compensation so that the effective gain-
bandwidth product (at low frequency) is typically 20MHz (e.g. LF357). The external compensation ensures plenty
of stability margin even with a highly capacitive load (long cables to the reference resistor) [2]. The purpose of the
second stage follower is to use feedback to overcome the resistance of the current carrying wire to the reference
resistor. The very small difference between V2 and VF also ensures that the current flowing in the voltage sensing
wire is negligible. The external compensation requires a low source resistance for the non-inverting input.
The open loop transfer function of the first op-amp over most of the frequency range (up to the gain-bandwidth
product of typically 5MHz) can be accurately described as an integrator: -
T1 s  
1
with T1  1
 B1s
The feedback network is a two-stage low-pass filter and can be accurately described by [1]: -
3 N s  1
T2 s  
 s  3 N s  1
2 2
N
At a frequency significantly below the natural frequency:  N s  1  T2 s   1   N2 s 2  3 N3 s3
If one assumes that the lead resistance is small compared to the reference resistor the second stage follower is (see
T3 s  
1
section 2.1): so that T3  1
1   B2 s
1. Monograph: “Two-stage filters”. See section 2.2.

2. Monograph: “High gain blocks”. See sections 3.6 and 3.7
12
Part 4: Monograph 2
Referring to fig. 6.3.1: -
V2  T1 VIN  V1  and V1  V2  T2 VF  V2  and VF  T3V2
Use the second and third equation to eliminate V1 and V2: -
VF V  V 
  T1VIN  T1  F  T2 VF  F  
T3  T3  T3  
VF 1  T1  T1T2  T1T2T3   T1T3VIN
The overall transfer function is, therefore: -
T s  
VF T1T3

VIN 1  T1 1  T2   T1T2T3
1
1  1  1  T2 1 
 T s   
T1T2T3
  1   
T2  1  T1 1  T2   T1T2T3  T2  T2T3 T1T2T3 
The second and third terms in the brackets are small corrections and dividing by T2T3 makes a negligible difference
so that, to a very good approximation: -
1
1 1
T2  1 and T3  1  T s   1  1  T2  
T2  T1 
From above, at low frequency:  N s  1  T2 s   1   N2 s 2  3 N3 s3
 T s   1   N2 s 2  3 N3 s3  1   N2 s 2  3 N3 s3   B1s 
1 1
The lower order terms in  N s cancel and it is likely, therefore, that the accuracy is limited mainly by the finite gain-
bandwidth product of the first op-amp: -
 N s   B1s and  B1s  1  T s   1   B1s 1  1   B1s   B21s 2

4
In practice the second order term is negligible and the CMRR is the main source of in-phase error (typically 100dB
resulting in < 10ppm). The contribution due to the second stage follower appears to be negligible!
In the example above the first op-amp has a gain-bandwidth of 5MHz, the feedback network a natural frequency of
16kHz and the operating frequency is 400Hz. The relevant factors are: -
f f
 B1s   8  10 5 and  N s   2.5  10 2
f B1 fN
The main source of error is 80ppm quadrature which is easily rejected by a null detector with reasonable phase
accuracy and a synchronous rectifier [1].
1. Monograph: “Null detectors – the basics”.
13
Part 4: Monograph 3
High accuracy amplifiers, integrators and differentiators

1. Introduction
This monograph is concerned with feedback around a two-stage high gain block (HGB) in the inverting
configuration with a small capacitive load. The action of feedback is such that the inverting input is maintained at
very nearly local 0V (“virtual earth”) and the common mode voltage is negligible. Closed loop accuracy is limited
only by the feedback components and the gain of the HGB. There are four main applications: -
a). Inverting amplifiers and a differential amplifier - the latter as part of a quadrature servo.
b). Integrators: These are useful building blocks for active filters and two-phase oscillators.
c). Differentiator: For generating an accurate 90 degree phase shift as part of a quadrature servo.
d). Charge amplifiers: The feedback components are small capacitors and a very large resistor [3].
Z2
VE I
I Z1
VIN VOUT
H2(s)
Two-stage HGB
0V 0V
Fig. 1 The general inverting configuration with a high gain block (HGB).
Whereas a single high performance op-amp may offer sufficient in-phase accuracy for some applications they can
be quite expensive and phase error (quadrature) can be an issue. A more advanced two-stage HGB (types 1 or 2)
offers significantly lower phase error as well as lower cost. A differential amplifier can be implemented with a two-
stage type 3 HGB. For circuits employing a single op-amp see section 3 of “High gain blocks” [1].
It is unlikely that a three-stage HGB, or higher, offers any advantage. The improved in-phase accuracy is of no
benefit as this is limited by the feedback components.
For a high accuracy amplifier the resistors need to be high precision, low temperature coefficient types. Matched
pairs of resistors, usually fabricated on the same substrate, are a good choice. If a high value feedback resistor
(>10kΩ) is necessary then a small capacitor in parallel eliminates the extra phase shift (interaction with the input
capacitance) which could otherwise affect stability.
For a high accuracy integrator a low phase error (“low tanδ”) capacitor should be used (e.g. polypropylene) for the
feedback component. A good example is a circuit designed to measure tanδ [2]. Even better is to include a
compensator for the phase error based on its repeatability and stability.
For a high accuracy differentiator, as part of a quadrature servo, a low phase error transformer, based on a gapped
low loss ferrite pot core, is the preferred choice. The circuit converts the input (sinusoidal) voltage to a current,
through the transformer primary so that the output of the transformer is accurately in quadrature (precisely 90
degrees phase shift relative to the input). The transformer also provides an isolated output so that it can be added to
the output of a ratio transformer.
Charge amplifiers are mostly used as low noise null detectors and so accuracy is seldom an issue [3]. The option is
included here as the analysis is almost the same as for an inverting amplifier and high accuracy may prove useful in
some applications.

1
2. General analysis
For the more general discussion of feedback and stability for three-stage HGBs and higher see the monograph
“High gain blocks” [1]. There it is argued that a sufficiently good model of the open loop transfer function of a
two-stage HGB need not include the very low frequency (finite DC gain) model. The loop gain is usually so high
that it is not possible to measure the error at very low frequency. For the low frequency error analysis I shall
assume, therefore, an integrator and one-plus-integrator model: -
 1  1
H 2 s   1  
  1   2s
s
This model works well over a wide frequency range (typically 1Hz to 1MHz) for HGB type 1. It works less well, at
high frequency, for types 2 and 3, especially when driving a capacitive load [1] due to the “extra poles”. The
analysis is simplified if one normalises to the time constant of the one-plus integrator s  j 1  : -
H 2 s  
1  s  with  
2
s 2
1
The parameter  is chosen for the required stability margin and depends on the feedback factor.
At low frequency the HGB open loop gain can be enormous and the error voltage (at the inverting input) is very
small. The open loop transfer function is defined from the non-inverting input to the output so that s  j 1  : -
s  1  VOUT   H 2 s VE  
VE
 VE  s 2VOUT
s 2
This is included as it is readily measured with a low noise null detector [2]. In more convenient form, with
frequency in Hz: -
2
VE  f  1
f  f1      with f1 
VOUT  f1  2 1
The closed loop transfer function is, in normalised form s  j 1  [1]: -
Z2  H 2 s   Z  s 1 
T2 s     with  s   1  2
Z
    2 
Z1  H 2 s    s   Z1   s s  s  1 
2
Z1
The parameter  s  is the reciprocal of the feedback factor.
T2 s    D2 s 
Z2
The term in brackets is the “D” factor [1]:
Z1
At low frequency the “D” factor is very nearly one and closed loop accuracy is limited by the quality of the passive
component Z1 and Z2.
Z2   s s 2 
T2 s    1  
Z1   s s  s  1 
With a little algebra the error term can be extracted: 2

2
Part 4: Monograph 3
3. High accuracy amplifiers
For an inverting amplifier both feedback components are resistors. The reciprocal of the feedback factor does not
vary with frequency and the analysis is simplified. In normalised form s  j 1  : -
s 1 
 T2 s    D2 s  with D2 s  
R2 R2
 1 and   2
R1 R1 s  s  1
2
1
Stability depends on the value of the product  . A higher value results in lower phase margin (a higher resonant
peak at the OPI normalised frequency). In practice there can also be a lower limit due to the limited bandwidth of
the op-amps but the range is very wide for a type 1 HGB. A tolerable degree of peaking is about 60% (+4dB) and a
spreadsheet model can be used to estimate a suitable value. A typical maximum value is   1
Fig.3.1.1 Closed loop response for   1 [1]
For a type 2 HGB this model works well, at low frequency, but high frequency stability depends on the type of op-
amp and the capacitance of the load. With feedback factor approaching 100% there is usually a resonant peak in the
frequency response at around the unity gain frequency. If the resonance is a problem one can easily reduce the
feedback factor with a resistor across the HGB inputs or, with a type 2 HGB, setting the potentiometer a bit lower
(see fig. 3.3.1).
R2
R1
VIN VOUT
R3
0V 0V
Fig. 3.1.2 Reduced feedback factor with R3
1. Spreadsheet: “A two-stage HGB”
3
If one includes the very low and very high frequency characteristics of the op-amps the algebra gets a bit messy but
a spreadsheet model [1] reveals the open loop characteristic. For a typical two-stage HGB, based on LF356 op-
amps, the BoDayQuist plot illustrates how the stability criterion (avoiding the -1 point) is achieved: -
1012
106
-1 point
unity gain circle
Fig. 3.1.3 BoDayQuist plot for   1 [1]

3.2 Error analysis
For a two-stage (type 1) HGB, in normalised form s  j 1  the low frequency model is: -
R2  s 2  
T2 s    1   with   2
R1  s  s  1 
2
1
We need only the real (in-phase) and imaginary (quadrature) error components. At low frequency: -
s 2
 s  1  D2 s   1   1  s 2 1  s   1  s 2  s 3
2
1 s
In more convenient form with frequency in Hz  f1  1 2 1  : -
2 3
 f   f 
f  f1  D2 s   1      j  
 f1   f1 
The quadrature error is now third order with respect to frequency – compared to first order for a single op-
amp. The reader may notice that the error analysis has the same form as a two-stage low pass filter [2].
1. Spreadsheet: “Multi two-stage HGB”

2. Monograph: “Two-stage filters”
4
Part 4: Monograph 3
A circuit for measuring tanδ provides a useful example [1]. The HGB (type 2) is based on a dual op-amp (LF353)
with 4MHz gain-bandwidth product: -
VE R2
VIN R1
½LF353 VOUT
V1
k
0V 4k7 ½LF353 0V
Fig. 3.3.1 A simple inverting amplifier
The open loop transfer function of a two-stage HGB is: -
 1  1
H 2 s   1  
  1s   2 s
The gain of the first op-amp is reduced with a trimpot by a factor 0.25 so that the GBWP (and the OPI frequency) is
reduced to 1MHz. The optimum potentiometer setting was found with a step response (square wave input) on the
actual circuit.
1 
1   B k  1.6  107 s and  2   B   4  108 s and   2  k  0.25
2f B 1
R1  R2  4k 7   s   1 
R2
 2    0.5
R1
This is a factor of two lower than what one would predict for a reasonably stable circuit. The lower value, however,
improves high frequency stability by reducing the loop gain.
2 3
 f   f 
For a two-stage HGB: D2 s   1      j  
 f1   f1 
The frequency f1 corresponds to the time constant  1 (i.e. 1MHz).
At 1kHz the ratio f f1  103 so that the errors, both in-phase and quadrature, are negligible compared to the
capacitor tanδ being measured (≈10-4): -
f  1kHz and f1  1MHz  D2 s   1  5  107  j5  1010
5
4. High accuracy integrators
For an integrator the feedback components are a resistor and capacitor.
R
VIN VOUT
0V
0V
Fig. 4.1.1 Circuit diagram of a high accuracy integrator
and Z1  R   s   1 
1 1
Z2  with  I  RC
sC Is
1  H 2 s  
From above the closed loop transfer function is: T2 s     
 I s  H 2 s    s 
1
In normalised form s  j 1  :  s   1 
Is
The closed loop transfer function is, in normalised form s  j 1  : -
1  s 1  
T2 s      with   2
 I s   s s  s  1 
2
1
1  s 1  1
 T2 s     2  with     1
 I s  s  1   s  1  I
In practice the integrator time constant is much higher than the HGB time constant and the effect on the “D” factor
is negligible (in terms of peaking) compared to the inverting amplifier.
s 1
D2 s  
s  1   s  1
2
The result is a much reduced phase error compared to an integrator based on a single op-amp. The analysis is
repeated here for convenience [1]. The open loop transfer function, except at very high frequency, is: -
  B  H s  
G
1   Ps
1. Monograph: “High gain blocks”. See section 3.2
6
Part 4: Monograph 3
1
The gain-bandwidth product of the op-amp is: fB 
2 B
1  G I s 
With a little algebra the result is of the form: T s     
 I s  1  G I s 1   B s  
Where: -
  
 I   I 1  B  This indicates a slightly increased time constant of the integrator, compared to the ideal.
 I 
1
  
 B   B 1  B  This indicates a slightly reduced time constant compared to the gain-bandwidth product.
 I 
The first effect could be easily mitigated with a corresponding reduction in the value of the resistor.
 1   f f 
 f  f B  T s  
fI
1 j I   
G  I s   Gf f B  
The “D” factor has a second order band-pass characteristic [1] with a wide bandwidth: -
Fig. 4.1.2 Typical phase error of an integrator based on a single op-amp [1]
The result is a positive phase error at low frequency and a negative phase error at high frequency. The phase error
is zero only at a mid frequency, typically around 1kHz [2].
With a two-stage HGB the phase error is considerably reduced.
1. Spreadsheet: “Band-pass filter”

2. Monograph: “High gain blocks”. See section 3.2
7
4.2 Error analysis
For a two-stage HGB the “D” factor is, from section 2, in normalised form s  j 1  : -
 s s 2
D2 s   1 
 s s 2  s  1
1 s 2  s 
 s   1   D2 s   1  2 with    1
Is s  1   s  1 I
The integrator time constant is usually much greater than the OPI time constant so that:   
We need only retain the significant real (in-phase) and imaginary (quadrature) error components. The effect of the
s2 term in the denominator is negligible: -
s 2  s
s 2  s  D2 s   1   1  s 2  s 1  1   s 
1   s  1
    D2 s   1  s 2  s  s3
 f 
2

  f   f  
3

 D2  f   1      j        
 f1  
  1
f  f1  
As with the previous case a circuit for measuring tanδ provides a useful example [1]. The HGB time constants are
the same (LF353 op-amps): -
2
1  1.6  107 s and  2  4  108 s     0.25
1
1
The integrator time constant is (4k7 and 10nF):  I  RI CI  4.7  105 s      2.1  10 4
I
 f 
2

  f 
3
 f 
D2  f   1      j       
 f1  
  1
f  f1 

At 1kHz the ratios are: f f1  103 so that the errors, both in-phase and quadrature, are negligible compared to
the capacitor tanδ being measured (≈10-4).
f  1kHz and f1  1MHz  D2  f   1  2.5  107  j 2.5  1010  2.1 107 
1. Monograph: “A circuit for measuring tanδ”. See section 4.
8
Part 4: Monograph 3
5. A high accuracy differentiator
A convenient method of implementing a differentiator is to employ a low phase error transformer primary winding
as the feedback element in an inverting amplifier configuration. The action of feedback is to convert the input
voltage to a current through the primary. The output voltage is proportional to the rate of change of the flux/current
and the mutual inductance of the transformer (Faraday’s law). It is also, therefore, proportional to the rate of
change of the input voltage (i.e. differentiation). The resistance of the primary winding is relatively unimportant as
the current is accurately in-phase with the input voltage. The main application is as part of a quadrature servo with
a mutual inductance of typically 100μH [1].
I RP
VE
CS
R RS LP VOUT
VIN
I
V1
0V
Fig.5.1 A differentiator circuit
The output is isolated from local 0V and can be easily added to the output of a main ratio transformer, as required
in a typical quadrature servo.
The purpose of the series resistor/capacitor snubber in parallel with the transformer primary is to limit the gain at
high frequency. Even a small amount of distortion, noise or interference at the input could threaten to overload the
bridge null detector pre-amplifier. The snubber capacitor can resonate with the primary winding inductance but the
peak value is limited by the damping effect of RS. Typical component values are 1μF and 27Ω.
In practice the best available ferrite material (e.g. MMG type P12) has a phase error of the order 0.2mrad [2] and,
therefore, the phase error due to the HGB, at low frequency, is negligible. Fortunately this is sufficiently accurate
(and cost-effective) for most quadrature servo applications. The in-phase error is irrelevant as the servo
automatically adjusts the amount of quadrature injected for a null balance.
A quadrature servo based on a low phase error capacitor and resistor would be possible but it would also require a
low phase error isolating transformer (i.e. two-stage) and be less cost-effective.
The basic analysis (omitting RS and CS) is fairly simple. If one assumes an ideal HGB, with perfect virtual earth, the
current passing through the input resistor and transformer primary is: -
VIN
RS    I 
R
The flux in the transformer core is [3]:   N P IAL
Where: N P  Number of turns on the primary and AL  Permittance of the magnetic circuit (reciprocal of
reluctance).
1. Monograph: “Null detectors – the basics”. To explain 100μH see section 6.4.
2. Measured at low flux density (B < 1mT). Higher flux density results in increasing tanδ.
3. Monograph: “Single-stage IVDs and RTs”. See section 2.
9
The output of the transformer is, according to Faraday’s law: -
d N S N P AL dVIN
VOUT  N S 
dt R dt
In the complex representation s  j  d dt  the transfer function is: T s  
VOUT sLM

VIN R
Where: LM  N S N P AL  Mutual inductance of the transformer
In practice the inductance is not perfect but one can employ the complex model [1]: LM  LM 1  j tan  
The choice of input resistance is limited by the maximum current that can be delivered by the HGB. A maximum of
1mA is a reasonable compromise resulting in manageable power dissipation in the output stage and low flux
density in the core. With a maximum input voltage of 10V a suitable value is, therefore, 10kΩ.
5.2 Error analysis
From the general analysis (section 2) the open loop transfer function and “D” factor for a two-stage HGB is, in
normalised form s  j 1  : -
1  s  H 2 s  
H 2 s   and D2 s   with   2 and  s   1 
Z
s 2
H 2 s    s  1 R
Z is the complex impedance of the entire feedback network (transformer primary and parallel snubber). The
transfer function to the output of the HGB is, therefore (referring to fig. 5.1): -
V1  Z  V1
 D2 s  with “virtual earth” voltage VE 
VIN R H N s 
The total current through Z is: -

VE  V1  V1  1   VIN  1 
I  1    1   D2 s 
Z Z  H 2 s   R  H 2 s  
 VIN  1  H 2 s  
 I 1   
R  H 2 s   H 2 s    s  
 VIN  H 2 s   1 
 I  
R  H 2 s    s  
The complex representation for a mutual inductor is: VOUT  IsLM
The transfer function to the transformer output is, therefore s  j  : -
 H 2 s   1 
T s  
VOUT sLM
  
VIN R  H 2 s    s  
1. Monograph: “Low phase error capacitors and inductors”. See section 3.
10
Part 4: Monograph 3
At low frequency the HGB gain is very high and the term in brackets is very nearly 1. The feedback impedance is
very low (the transformer primary has very low impedance and the snubber has negligible effect).
 1  1  Z  R   s   1 and H N s   1
H 2 s   1  s    s   1   s 
1
 1   1 
  1  1    1  1    1 
H 2 s    s   H 2 s   H 2 s    H 2 s   H 2 s   H 2 s 
 Z 1 
To a very good approximation, therefore: 1   s     T s  
Z sLM
1  
R R  R H 2 s  
 1 
  RS RP  sLP 
Z  S 
sC
The impedance of the feedback network is:
 1 
  RS   RP  sLP 
 sCS 
Multiply top and bottom by sCS: Z

1  sCs RS RP  sLP 
1  sCS RS  RP   s 2CS LP
The resistance of the primary winding (easily < 0.1Ω) is much smaller than the snubber resistance so that, at a
frequency well below resonance, The feedback impedance is only the transformer primary winding (resistance plus
inductance). The impedance Z is also much lower than the input resistance: -
Z Z 1
s 2CS LP  1 and RS  RP  RS  Z  RP  sLP and  1   1
R R H 2 s 
In practice, therefore, the error due to the snubber and HGB is truly negligible compared to the phase error of the
ferrite transformer. One could easily justify employing a single (good quality) op-amp! An accurate model is: -
LM  LM 1  j tan    T s   1  j tan  
sLM
R
A typical transformer has a mutual inductance of 100μH with a winding resistance of <0.1Ω. With a snubber
capacitance of 1μF the natural frequency is: -
1
fN   16kHz
2 LPCS
A snubber resistance of 27Ω provides sufficient damping with a characteristic frequency of: -
1
fS   6kHz
2RS CS
At high frequency the snubber resistance becomes the dominant feedback component and the gain levels out: -
V1 27
2fLP  27   4  2.7  10 3
VIN 10
11
The maximum operating frequency is almost certainly less than 1.6kHz so that the maximum impedance of the
transformer primary is at most 0.1Ω, compared to an input resistance of 10kΩ. The open loop gain of even a basic
op-amp is at least 1000: -
Z Z 1
f  1.6kHz  Z  2fL  0.1   10 4   10 7
R R H1 s 
Frequency response with component values: LP  100H RP  0.1 RS  27 CS  1F
Fig. 5.3.1 Frequency response to the output of the HGB V1 VIN  [1]
It is necessary to check that the flux density is low enough for the assumption about tanδ. With 16 turns and a
maximum current of 1mA the flux is: -
  N P IAL  16  103  400  109  6.4  109Wb
The RM10 pot core has a magnetic circuit with an effective area of 83mm2 so that the flux density is: -
 6.4  109
B   77 T
AE 83  10 6
This is well below the recommended test condition for tanδ (<1mT) for this type of core.
1. Spreadsheet: “A differentiator”.
12
Part 4: Monograph 3
6. A high accuracy differential amplifier
One form of differential amplifier consists of a high gain block (HGB) and four resistors. Low phase error can be
achieved with a two-stage HGB. High common mode rejection ratio (CMRR), however, requires very accurately
matched resistor pairs.
R2A
I
V3
R1A
V1
V4 VOUT
V2
≈0V HGB
R1B
R2B
0V
Fig. 6.1 A differential amplifier
Frequently one of the inputs is at approximately 0V and the matching requirement can be much reduced. One
notable application is as part of a quadrature servo [1]. The voltage on one side of the standard resistor in a bridge
is often no more than a few mV (see fig. 6.2.1). It is then possible to employ a high accuracy differential amplifier
as long as the nominally 0V side is connected to the non-inverting input. The action of feedback is to drive the
inverting input to be the same as the non-inverting input and the CMRR requirement is much reduced.

R2 B
According to Ohm’s law and Kirchhoff’s laws, referring to fig. 6.1: V4  V2
R1B  R2 B
V1  V3 V3  VOUT
Similarly on the inverting side: I   VOUT 
R2 A
V3  V1   V3
R1 A R2 A R1 A
For an ideal HGB the action of feedback is to cause: V3  V4
R2 A  R2 B  R2 B
VOUT  V2  V1   V2
R1 A  R1B  R2 B  R1B  R2 B
R  R2 B  R
With a little algebra: VOUT   2 A  1 V2  2 A V1
 R1 A  R1B  R2 B  R1 A
 R  R2 A  R2 B  R
 VOUT   1 A  V2  2 A V1
 R1B  R2 B  R1 A  R1 A
 R  R2 A  R2 B  R2 A  R
 VOUT   1 A   V2  2 A V1
 R1B  R2 B  R2 A  R1 A  R1 A
13
R2 A   k A  1   R R1B
We can take out the gain factor: VOUT   V2  V1  with k A  1 A and k B 

R1 A   k B  1   R2 A R2 B

If the resistors are perfectly matched the result is, as expected: -
 k  1
  1 and VOUT  2 V2  V1 
R
k A  kB   A
 kB  1  R1
If one or the other inputs is 0V then one has either an inverting or non-inverting amplifier and it is clear that the
dynamic response is the same (see section 2). The low feedback factor ensures that the open loop gain is well
below 0dB at the extra pole frequency and the effect of the extra pole on closed loop stability is negligible.
For a two-stage HGB in normalised form s  j 1  : -
s 1
T s    2 D2 s  with D2 s  
VOUT R
V2  V1 R1 s 2  s  1
2 3
 f   f 
f  f1  D2  f   1      j  with
1
f1 
 f1   f1  2 1
6.2 Errors due to resistor tolerance
R2 A 1
One can take the gain on the inverting side as the precise definition for an ideal amplifier: G  
R1 A k A
The gain is typically a minimum of 10 and a reasonably good approximation is: -
 k  1
k A  0.1   A   1  k A 1  k B   1  k A  k B
 kB  1 
The formula simplifies to: -
VOUT  G1  k A  kB V2  V1 
The error, in terms of volts, can then be defined with: VOUT  GV2  V1   VOUT
 VOUT  Gk A  kB V2
The error is proportional to the (small) input voltage on the inverting side and the mismatch of resistance ratios.
 R 
Define: R1 A  R1  R1 etc  R1 A  R1 1  1   R1 1   A  etc.
 R1 
 A is the resistor tolerance in terms of ratio (e.g. 1%) on the inverting side. The effect on the resistance ratio is
then  2 A . Consider the worst case (R2 high and R1 low): -
R2 A R2 1   A  R2
 1   A 1   A   2 1  2 A 
R
 A  1  
R1 A R1 1   A  R1 R1
The effect on the error term k A  k B  is, therefore: -
k A  kB  k 1  2 A   k 1  2 B   2 Ak  2 B k
14
Part 4: Monograph 3
Each side contributes the same to the overall error so that one may as well specify the same tolerance.
 A  B    VOUT  4V2
The magnitude of the error, expressed as a ratio is, worst case: -
VOUT 4 V2

VOUT G V2  V1 
Moreover, in the quadrature servo application [1] the purpose of the amplifier is to boost the signal developed
across the reference resistor, RS. The voltage V2 is proportional to V1 and the result is a gain error and not important
as the following demonstrates: -
6.3 Example application and calculations
In a typical resistance bridge the voltage developed across the reference resistor, RS, is used by the quadrature
servo. The high accuracy voltage followers provide convenient low impedance sources for the inputs to the
differential amplifier.
+ V1
RS
+ + V2
I
RC D
0V
RT
+
Fig. 6.3.1 A typical resistance bridge configuration
One of the potential leads of the unknown resistor, RT, is held at local 0V by an active guard. The signal, V2, on the
lower potential lead of the reference resistor is determined, therefore, by the operating current and the lead
resistance RC.
According to Ohm’s and Kirchhoff’s laws: -
V1  V2
 V2  C V1  V2 
R
V2  IRC and I 
RS RS
 VOUT  4
RC
V1  V2 
RS
 R 
The result is a gain error:  VOUT   G  4 C V2  V1 
 RS 
For this application low cost resistors (1% tolerance) should suffice.
15
The two-stage HGB required is slightly unusual (a hybrid type 3 with reversed order) [1]. The first stage is an open
loop op-amp/integrator, required for its differential input. The second stage is a one-plus-integrator (OPI) with
external feedback components for an accurate and stable dynamic response. Latch-up due to overload of the first
stage is prevented by a limiter (a pair of zener diodes). The loop gain is reduced (and stability maintained) for the
lowest gain setting (×10) with resistor R3.
R2 Analogue switch (e.g. CD4052)

R1
½LF353 ½LF353
VOUT
VIN R3
1k 2n2
≈0V
R1
2 × 7v5 10k
R2
0V 0V
Fig. 6.3.2 A switched gain differential amplifier with two-stage HGB
The gain does not need to be accurate and 1% tolerance resistors are satisfactory: -
Gain 10 100 1000

R1 1kΩ 1kΩ 100Ω
R2 10k 100kΩ 100kΩ
R3 220Ω ∞ ∞
R2
For the high gain settings the reciprocal of the feedback factor is very simply:  1
R1
The result is 101 and 1001 (gain + 1). Calculating the reciprocal feedback factor for the lowest gain setting is a
little more complicated. Both inputs to the differential amplifier are connected to a low resistance source so that the
equivalent circuit is: -
ΔVOUT R2
R3 ΔVF
R1
R1 R2
0V
Fig. 6.3.2 The equivalent feedback network with R3
1. Monograph: “High gain blocks”. See section 2.
16
Part 4: Monograph 3
The resistors have substantially different values and the feedback factor is not particularly critical so that one can
rely on a very approximate calculation.
The first resistive divider R1 R2 is equivalent to a voltage source reduce by a factor of eleven in series with R1 in
parallel with R2 R1 || R2  . The overall circuit is, therefore, the reduced source voltage across the series combination
of R3 and two lots of parallel combinations R1 || R2  . The change in current through R3 is, therefore:
V
 I  OUT  R1 || R2  R3  R1 || R2 
R1 1

R1  R2 11 11
The parallel combinations are lower than R1 by roughly 10% so adding R3 (220Ω) brings the series combination
back up to nominally 2R1. The change in voltage across R3 is, therefore: -
VOUT V
I   2 R1  VF  OUT R3
11 22 R1
VOUT 22 R1
The reciprocal feedback factor is, therefore:    100
VF R3
s 1
The “D” factor for a two-stage HGB is [1]: D2 s  
s 2  s  1
The product  determines the stability margin. Spreadsheet modelling shows that a value between 0.2 and 2 is
satisfactory [1]. The higher value results in a larger resonant peak. With a maximum reciprocal feedback factor of
2 2
1001, therefore, the value of    is determined.
 1001
The integrator time constant for an LF353 with gain-bandwidth  f B  4MHz is:
1
B   4  108 s
2f B
B
The ratio of time constants for stability is:    2  10 3
1
The OPI time constant required for stable operation at the maximum gain is: 1  2  105 s .
Convenient standard values are 2n2 and 10k: -
1  RC  2.2nF  10k  2.2  105 s so that   0.18 or   1.8
At low frequency the error analysis is: -

2 3
 f   f 
D2 s   1      j   with
1
f  f1  f1   7.2kHz
 f1   f1  2 1
f
At the higher operating frequency of 75Hz the ratio of is  10 2 and the maximum quadrature error (gain =
f1
1000) is about 2ppm and negligible.
1. Monograph: “High gain blocks”. See section 2.
17
Part 4: Monograph 4
The Isotech microK “bridge”

1. Introduction
This monograph is included in part 4 because the microK “bridge” relies on a number of high accuracy active
circuits – a high stability DC current source, a differential amplifier and a very accurate analogue to digital
converter (ADC) [1]. The main application is resistance thermometry though the ADC can also measure the output
of a thermocouple. Isotech offers five versions with resistance ratio accuracy, over the full range (0 – 1.05), from
0.5ppm to 30ppb [2]. The main advantage, compared to conventional null-balance bridges, is a major reduction in
size and weight – no bulky ratio transformer. Project manager, Paul Bramley (PB), also claims higher reliability
based on an inherently “drift free” and robust design – no internal adjustments or “moving parts” (e.g. “trimpots”)
“requiring regular service visits”.
Fig.1.1 The MicroK “bridge” (picture courtesy Isothermal Technology Ltd [4])
The main disadvantage, theoretically, is the relatively poor noise performance for low source resistance (<10Ω)
though PB does not agree [3], especially when one takes into account settling time when switching between input
channels.
In later models (starting with the microK100 project) noise matching was improved with “a large array of (parallel)
amplifiers” [4] resulting in a noise resistance of “a few hundred Ohms” [3]. A good clue is the bandwidth settings:
0.5Hz, 0.1Hz and 0.02Hz with measuring times of 2, 10 and 50s respectively. In the brochure for the microK
“Gold” the stated resolution is 10nV (bandwidth not specified) [2].
Although described and marketed as a “bridge” the microK is basically a low frequency (5-10Hz) alternating DC
instrument. PB insists, however: “..it really is very like a Wheatstone bridge..”. You decide dear reader [5].
1. Bramley, P. and Pickering, J.: “Better Accuracy in Temperature Calibration and Measurement through a
New Type of Analog-to-Digital Converter”. The International Journal of Metrology (Cal. Lab. Magazine,
pages 30-35, Oct 2006). (Paul Bramley is of Metrosol Ltd and John Pickering is of Metron Designs Ltd).
2. Isotech brochure: “The new microK family of precision thermometry bridges” (Edition 2: 1516),
available at: www.isotech.co.uk
3. Isotech claim “low noise” but do not provide much information. See sections 6.1 and 6.14.
4. Bramley, P: “A few words from the microK100 design team” 2009, from www.metrosol-ltd.co.uk
5. See section 6.3.
1
2. The microK measurement system (overview)
2.1 Introduction
The measurement system is based on an ADC originally developed by (and licensed from) the National Physical
Laboratory (NPL) and Metron Designs Ltd. Pickering (of Metron) and Georgakopoulos et al [1] describe it as a
“delta-sigma” (Δ-Σ) converter but Bramley and Pickering [2] prefer “sigma-delta” (Σ-Δ). The “sigma” refers to
“sum” (Greek letter Σ) and delta refers to difference (Greek letter Δ). This is a remarkable bit of mixed signal
circuitry (analogue and digital) requiring average timing errors of less than 0.5ps (pico-second!), apparently [3].
The measuring range of the ADC is quoted as ±5V (not including the polarity reversal switch) [4]. The input
voltage range (thermocouple mode) is quoted as ±125mV [3], hence the need for a differential amplifier with
various gain settings.
2.2 Voltage (thermocouple) measuring mode
The connectors are gold plated tellurium copper alloy to keep thermal emfs to a minimum. Also, the polarity
reversing switch has very low thermal emfs (solid state - MOSFET) mounted immediately behind the connectors
[4]). Cold junction compensation (CJC) is external. Polarity reversal appears to be for thermocouple mode only –
for eliminating the DC offset of the amplifier. This suggests that the ADC is inherently bipolar (i.e. the input can be
positive or negative and the polarity switch is not used to achieve this [5].
Polarity reversal 5 bits

VIN
CJC VT 32 bits
G Σ-Δ ADC DSP
TeCu terminals 0V Diff. amp VR
Fig. 2.2.1 Outline schematic of the measurement system (Thermocouple measuring mode)
X represents the result of a single A-D conversion and Y the calculated result. VO is the amplifier offset. If one
assumes that the gain/ADC, thermocouple, reference and offset voltages are stable between measurement cycles: -
 V  VO    V  VO  X  X2 V
X 1  G T  X 2  G T   Y  1 G T
 VR   VR  2 VR
In thermocouple mode accuracy and noise performance are most likely limited by the reference voltage. Voltage
reference devices are notoriously noisy unless one employs a very low frequency low-pass filter (with large, low
leakage capacitors). A typical 5V reference (e.g. LT1021), for example, produces 3μVPK-PK in the range 0.1 – 10Hz
bandwidth. The microK employs “a very good buried zener reference” [6].
1. Pickering, J. R., Georgakopoulos, D., Williams, J.M. and Wright, P. S: “Effect of a PWM feedback DAC
on the Noise and Linearity of a Delta-Sigma ADC”, Int. Conf. on A to D and D to A Converters and Their
applications, 2005.
2. Bramley, P. et al: “Better Accuracy in Temperature Calibration….” Available via Isotech website.
3. Isotech brochure: “The new microK family of precision thermometry bridges”: “In order to achieve our
target of <0.05ppm, we needed to be able to produce pulses whose edges have relative timing errors of
0.5ps (about the time it takes light or electrical signals to travel 0.15mm).”
4. Bramley, P and Robinson, N.: “Cost Effective Techniques used to Validate the Performance of the
microK Resistance Thermometry Instrument with sub mK Uncertainty.” Available via Isotech website.
5. PB confirmed. See section 6.16.
2
Part 4: Monograph 4
It is also likely that one of the inputs of the differential amplifier is held at local 0V (rather than the thermocouple),
to avoid an error due to gain asymmetry (c.f. common mode rejection). This can be achieved with either a direct
connection or, more likely, with an active guard [1].
The microK brochure [2] quotes a DC voltage measuring accuracy of 0.25μV with a range setting of 20mV [3].
2.3 Resistance ratio measuring mode
In resistance measuring mode a DC current (0 – 10mA) is passed through the resistor and the voltage measured
(relative to an internal reference: VR). The current is then reversed and the measurement repeated. The difference is
calculated in order to eliminate thermal emfs and the amplifier input offset voltage. The current is proportional to
the internal reference voltage [4] so that each basic measurement is, in effect, a resistance ratio (relative to an
internal reference resistor in the current generating circuit). Other ratios are then calculated from “substitution
measurements” [5] (“switching at several times a second”). This requires the measuring current, differential
amplifier gain and ADC to be sufficiently stable for the short time between substitutions. The differential amplifier
and ADC also need to be very linear and stable between substitutions (typically <10ppb for the microK “gold”).
VIN
±I RT G
Current reversal Fixed
Fig. 2.3.1 The measuring current reversal scheme (resistance measuring mode)
It would seem (see next section) that exact current reversal is not practicable but this need not be a problem as long
as the selected current is sufficiently stable. If one assumes that all parameters are stable between measurements: -
 I R  VO  VTHERMAL
X 1  G 1 T
   I R  VO  VTHERMAL
 and X 2  G 2 T
 I  I R
  Y  X1  X 2  G 1 2 T
 VR   VR  VR
Once again the Xs represents the result of a single A-D conversion (probably 50 - 100ms per conversion) and Y the
calculated result.
Fluctuations of the reference, offset and thermal emfs set a lower limit to the reversal frequency and an upper limit
to each A-D conversion cycle (100ms for the original microK models [6]), equivalent to an operating frequency of
5Hz, though a more recent microK brochure quotes 6-10Hz [2]. This is a problem common to all so called “DC”
instruments (e.g. the “Kusters comparator”). It is stated in [7], for example, with unintended irony: “The reversing
cycle of the bridge should be as short as possible in order to be able to cope with changing thermal EMFs”.
The various microK models have three channels for measuring resistance – typically one for the thermometer being
calibrated and two for reference thermometers (SPRTs) or a single SPRT and an external “Wilkins” type transfer
standard resistor.

2. Isotech brochure: “The new microK family of precision thermometry bridges”: (Edition 2: 1516)
3. See also: Bramley, P. and Robinson, N.: “Cost Effective Techniques used to Validate the Performance of
the microK Resistance Thermometry Instrument with sub mK Uncertainty”. www.isotech.co.uk
5. Paul Bramley, P., Tavener, J. and Pickering, J.: “Using a Substitution Measurement Topology to
eliminate the Effect of Common Mode Errors in Resistance Measurements used in Temperature
Metrology” 2007 NCSL International Workshop and Symposium.
6. Bramley, P.: “A few words from the microK design team” 2006, from www.metrosol-ltd.co.uk
7. Kusters, N.L. and MacMartin, M. P.: “Direct-Current Comparator Bridge for Resistance thermometry”.
IEEE Trans. On Instrum. And Meas., vol. IM-19, No. 4, Nov 1970.
3
The measuring currents are proportional to a master internal reference voltage, VREF, probably via a 12-bit
multiplying digital to analogue converter (MDAC) [1], and inversely proportional to an internal reference resistor.
The reference supplied to the ADC is also derived from the same master reference [1]: -
VREF VREF  k  k2  RT
I1  k1 I 2  k2 and VR  k3VREF  Y  G 1 
R5 R5  k3  R5
The values k1 , k 2 and k3 must also be sufficiently stable between A-D conversions. This makes sense – matched
pairs of resistors and MDACs, with the required short term stability, are readily available and variations (low
frequency noise and drift) in the voltage reference have a much reduced effect. It is also cited as the main reason
for calling the microK a “bridge”, which is rather strange [2].
To measure the ratio of two external resistors a further two measurement cycles (a total of four) are required – by
the “substitution” method [2] (probably a total of 200 – 400ms per measurement): -
RT Y X 1  X 2
 
RT Y  X 1  X 2
This, again, requires sufficient stability between substitutions.
According to PB [3] the microK goes one better – taking three consecutive samples with the middle sample double
weighted in the calculation. If one assumes that the total offset drifts at a constant rate (parameter  ): -
VO  VTHERMAL  V0  t
The samples are taken at uniformly timed intervals ( T ) with t  0 for the first sample. Once again the Xs
represents the result of a single A-D conversion and Y the calculated result: -
 I R  V0    I R  V0  T   I R  V0  2T 
X 1  G 1 T  X 2  G 2 T  X 3  G 1 T 
 VR   VR   VR 
 Y  X1  2 X 2  X 3  2G
I1  I 2 RT
VR
Using the substitution method, therefore, the ratio of two external resistors is: -
RT Y X 1  2 X 2  X 3
 
RT Y  X 1  2 X 2  X 3
This requires a minimum of six A-D conversion cycles (300 – 600ms per measurement). The process is then
repeated a sufficient number of times and the average calculated, in order to achieve the required resolution and
accuracy.
Clearly, higher order correction for drifting offsets is possible with more data. A useful software facility would be
the ability to monitor and display a graph of the actual offsets.
1. PB confirmed. See sections 6.6 and 6.10.

2. Bramley, P. et al: “Using a Substitution Measurement Topology….” In section 4: “…the internal zener
reference is used by both the current source and the ADC means that it is in fact a bridge system”. See section
6.3 for more on this issue.
3. PB comment. See section 6.8.
4
Part 4: Monograph 4
3. The voltage controlled (ultra-constant) current source
This is an ingenious two-stage design, probably due to John Pickering of Metron Designs Ltd. It is described in
Bramley et al [1] though not in much detail. The first stage is an “improved Howland current pump” based on an
op-amp with positive and negative feedback [2]: -
R2
R1
V1 V3
VC
I1
V2
R3 R5
R4 RL
V4 VL
I2 I3
Fig. 3.1 The first stage current source
If one assumes an ideal op-amp then the action of feedback is to make both inputs the same voltage. According to
Ohm’s law and Kirchhoff’s laws: -
V R  V3 R1 V2 R4  V4 R3
V  V1  V3  V1   V  V2  V4  V2 
R1 R3
 1 2 
R1  R2 R3  R4 R1  R2 R3  R4
V3  V4 V4  V2 
Also, the output current is: I 3  I1  I 2  
R5 R3  R4
For a constant current source the output resistance is infinitely high (zero output conductance). One can assume,
therefore, with V1 and V2 constant: -
I 3 V3 1 1 1 V3 R5
   0  1
V4 V4 R5 R5 R3  R4 V4 R3  R4
V1R2  V3 R1 V2 R4  V4 R3 V3 R1 R3
From above one also finds:   
R1  R2 R3  R4 V4 R1  R2 R3  R4
V3 R5 R  R  R2  R3 R
Both conditions are satisfied if: 1  3  1    1
V4 R3  R4 R1  R3  R4  R4  R5 R2
The result has an elegant symmetry. A reasonable choice could be, for example: -
R1  R2  R3  R4  R5
V3  V1 V1  V3
From the inverting side: R1  R2  V  V1  
2 2
V1  V3
The action of feedback is to make the inputs of the ideal op-amp the same: V  V 
2
1. Bramley, P. et al: “Using a Substitution Measurement Topology…”
2. Sheingold D. H.: "Impedance & Admittance Transformations using Operational Amplifiers".
The Lightning Empiricist, Vol. 12, No. 1. (Jan 1964)
5
V1  V3 V  V3
V  V2  I 2 R3  and V  V3  I1R5  I 2 R4  1
2 2
Add the last two equations: V2  I 2 R3  V3  I1R5  I 2 R4  V1  V3
V2  V1 VC
From above and with a little algebra: R3  R4  R5  I 3  I1  I 2  
R5 R5
The first stage has a truly differential input – a good idea for any high accuracy circuit. It is probably the case that
V1 is connected to the control voltage source local 0V.
Clearly R5 is a critical component, though the circuit performance (output resistance) also relies on accurate
matching of the other resistors. Bramley et al estimate an output resistance of about 9MΩ [1], due to component
tolerance (not specified), which they deemed insufficient and, therefore, a second “cascode” stage was added: -
Fig.3.2 The two-stage current source (courtesy Bramley et al [1])
This is a strange choice of name. The term “cascode” [2] usually refers to a two-stage high frequency amplifier [3].
It can be described as a voltage follower with a P-channel JFET source follower output stage (i.e. inside the loop).
It is not clear what VZ represents; A reasonable guess is that it is connected to V2 (see fig. 3.3) so that the current
flowing through R3 and R4 is zero. The load resistance, as “seen” by the first stage current regulator, then becomes
the drain-source resistance of the JFET plus the actual load resistance in series.
According to the MicroK brochure [4] there are three range settings for measuring current: 0-100μA, 0.1-1mA and
1-10mA. A reasonable estimate for the range of the control voltage is 0 ± 5V. From the analysis above this can be
achieved by selecting R5 (50kΩ, 5kΩ and 500Ω, respectively). The switches do not need to be fast but “on”
resistance and “off” leakage current are critical. For more detail see [5].

2. PB comment: See section 6.12.
3. According to Wikipedia “cascode” is a conflation of cascade and pentode, originally coined for a dual
triode high frequency amplifier – grounded cathode followed by grounded grid, designed to eliminate the
“Miller” capacitance effect. The name applies to similar transistor circuits, including the widely used dual
gate MOSFET.
4. Brochure: “The new microK family of precision thermometry bridges” (Edition 2: 1516)
5. Part 4, monograph 6: “A high accuracy current source”.
6
Part 4: Monograph 4
The actual circuit is likely to be, therefore: -
R1 R2
0V V3
I1
VC
R3 R5
R4 I2 I3 RDS RL
0V
V4 = VC
Fig. 3.3 A two-stage current regulator (including the “cascode”)
The effect on the circuit is rather interesting: -
V4  VC  I 2  0  V  V  VC  V3  2VC  RDS  RL  R5
The drain-source resistance of the P-channel JFET automatically adjusts so that the total load resistance
RDS  RL  is precisely the same as the reference resistor R5. The actual load resistance, RL, may vary, within
limits, but the current remains “ultra-constant” [1].
The P-type JFET works only for positive control voltage. To reverse the current there is probably some means of
selecting an N-type JFET [2]. Also, one can think of the first stage current source as a very high voltage source,
VHI, with a very high source resistance, RHI. The equivalent circuits, drawn in a familiar form are: -
Positive VHI 0V
RHI RL
Negative VC
I VC D
S N-type
P-type S
D I
VC
Positive VC RL
RHI
0V Negative VHI
Fig. 3.4 The second stage is a voltage follower with a JFET source follower in the loop
There appears to be a problem at zero current – no loop gain. The circuit probably works down to 10% of each
range setting (i.e. minimum current ±10μA).
1. Bramley, P. et al: “Cost Effective Techniques …”. The Metron product (I-REF2) is quoted to have an
output resistance of >10GΩ.
2. PB confirmed: See section 6.11
7
The specification of the top-of-the-range (MicroK “Gold”) is 30ppb ratio accuracy over the whole measuring range
(ratio of 0 - 1.05) [1]. A reasonable target for the current source is a contribution of no more than 10ppb. The
timescale between substitutions is of the order of only 100ms but this is still a tall order. The noise level (well
within the range of 1/f noise of most semiconductors) is also a major factor and probably contributes to the
instrument’s overall noise performance [2].
To achieve this level of performance it would be necessary to employ a very good (low noise) reference voltage
source. The reference resistor, R5, is also critical – it is probably necessary to employ a two-terminal-pair technique,
especially for the lowest resistance value (500Ω). The voltage sensing connections (to resistors R2 and R4) need to
be as close as possible to the component R5 [3]. Each connection would need its own switch: a total of 12 for three
values of resistor R5.
According to Bramley et al “Although the above analysis shows that the inclusion of a cascode stage reduces the
errors caused by the current source to insignificant proportions, the measurement system in the microK is also
actively guarded to further improve performance” [4]. I presume this refers to a virtual earth: The resistor being
measured is the feedback element of an op-amp (or a high gain block?) [5]: -
Fig. 3.5 The substitution method (courtesy Bramley et al [4])
The load resistance of the first stage current regulator is now the JFET drain-source resistance plus the resistance of
the current carrying lead (plus the switch resistance) of the two-terminal-pair resistance, RX, being measured. The
latter is usually quite small RL  R5  so that RDS  R5 (approximately).
The guard amplifier ensures that the voltage sensing lead of RX is accurately 0V all along its length (negligible
current flows in the voltage sensing lead) hence eliminating common mode at the differential amplifier input.
1. Brochure: “The new microK family of precision thermometry bridges” (Edition 2: 1516)
2. I could find nothing in the published literature regarding the noise contribution due to the current source.
3. Part 1, monograph 1: “High accuracy resistors” See section 3.
4. Bramley, P. et al: “Using a Substitution Measurement Topology…”. See section 3.3.2.
5. Part 4 monograph 1: “High gain blocks”. Even better would be a two-stage high gain block (HGB type
1). See section 4.1.
8
Part 4: Monograph 4
The four switches for selecting RX (fig. 3.5) allow the substitution method: The MicroK has three sets of terminals
for external resistors (typically two resistance thermometers and a transfer standard resistor). Speed and “on”
resistance are not critical but thermal EMFs and leakage current must be low or stable between substitutions.
The JFET adjusts to compensate for any change in RL thus ensuring a very accurate constant current, at least in the
short term, regardless of which resistor is selected. Fig. 3.5 is reproduced in a more convenient form: -
R1 R2
0V V3
I1 Virtual earth
VC
VT
R3 R5
T
R4 RL RT
I2 I3 RDS
VC
0V
Fig. 3.6 Current regulator into a virtual earth (active guard)
The virtual earth is much better than a direct connection to earth [1].
If you are now scratching your head, dear reader, you are not the only one. The following is an alternative
approach. The reference resistor, R5, is more clearly a two-terminal-pair device: -
VT
RL RT
R5
VC
-VC
High accuracy Active guard
0V (two-stage HGB)
voltage follower
Fig. 3.7 An alternative current source
The lead resistance plus switch resistance, RL, is shown explicitly to emphasise the fact that one of the potential
leads of RT is no longer held accurately at 0V. PB points out, correctly, that this would introduce common mode at
the input of the differential amplifier [2]. Later, however, he confirms that the differential amplifier is “floating”
[3], at least for more accurate models, by which I presume he means the power supply is bootstrapped.
It would seem to be a key feature of the microK design that common mode must be avoided – hence the “ultra-
constant” current source. PB: “It's unavoidable as far as I can see” [2].
A bootstrapped power supply with high accuracy voltage follower offers an alternative….
1. Part 3, monograph 6: “An F17 type ratio transformer bridge”. See section 1.2.
2. PB feedback: See section 6.13.
3. PB comment: See sections 6.7 and 6.15.
9
4. The differential amplifier
Very little information could be found on the microK differential amplifier hence the following includes more
speculation. In later models better noise matching (lower noise voltage/ resistance) is achieved with “a large array”
of non-inverting amplifiers in parallel, apparently [1]: -
Fig. 4.1 Noise matching by amplifiers in parallel (Courtesy PB [1])
This is rather strange as both inputs need to present a very high input resistance. The basic idea is to reduce voltage
noise at the expense of increasing current noise (reduced noise resistance). The number and type of amplifiers and
noise resistance are not specified.
PB feedback confirms that the actual design is “considerately more complicated than disclosed” [2]. A likely
candidate is a fully differential instrumentation amplifier: -
V1
R4
R2
R3
VOUT
R1
R3
R2
R4
0V
V2
Fig. 4.2 A basic instrumentation amplifier configuration
Gain stability (short term) is critical and so the resistors would have to be very good ones (e.g. ultra precision bulk
metal film types in a matched network) [3]. Linearity is also critical so that the op-amps would have to be very high
performance or, more likely, composite op-amps or high gain blocks [4] [5] with a low noise front end [6].
The gain needs to be variable (switch selected feedback factors) which is also not trivial [5].
1. Bramley, P: “A few words from the microK100 design team” 2009. www.metrosol-ltd.co.uk
2. PB feedback: See section 6.14.
3. Part 1, monograph 1: “High accuracy resistors”.
5. Part 6, monograph 3: “High accuracy amplifiers, integrators and differentiators”. See, for example, a
variable gain differential amplifier, section 6.3.
6. Part 5, monograph 2: “Low noise BJT preamps”.
10
Part 4: Monograph 4
Common mode rejection is less critical as one of the inputs (probably V2 - on the non-inverting side) is held,
accurately, at local 0V by the active guard. See previous section fig. 3.6.
An alternative approach: -
Noise matching with a transformer is not possible and so a parallel input stage is the only practicable way of noise
matching to a low source resistance. This can be achieved with a number of low noise matched pair BJTs in
parallel, each with its own constant current source. These replace a single matched “long tail pair” in a composite
op-amp circuit. The second stage differential amplifier could be based on a two-stage HGB. For details on low
noise and high accuracy design see the relevant monographs [1 and 2].
……etc
Current
sources
Input
Fig. 4.3 Parallel connected pairs to reduce noise voltage
Common mode rejection depends on the output resistance of the current sources as well as the matching of the
transistor pairs [1].
Another alternative is to connect a number of instrumentation amplifiers in parallel using a technique employed by
Analog Devices [4]: -
Fig. 4.4 Instrumentation amplifiers in parallel

2. Part 4, monograph 3: “High accuracy amplifiers, integrators and differentiators”
3. Website: www.interfet.com
4. Gerstenhaber, M., Johnson, R. and Hunt, S.: Analog Dialogue 49-05, May 2015
11
A less likely option is a large area dual matched JFET. The IF3602 by Interfet Corporation [3], for example, boasts
a low noise voltage of 0.3nV Hz at 100Hz but I have not been able to obtain information on current noise or
low frequency performance.
As noted above common mode rejection is less critical as one input to the differential amplifier (probably V2) is
held, accurately, at local 0V: -
I RL
V2 ≈ 0V
Virtual VOUT
earth RT VT G
V1
0V
Fig. 4.4 The active guard circuit and differential amplifier
The main disadvantage with this method is that the (variable) resistance, RL, appears in series with the constant
current source, hence the need for an ultra-high output impedance (“dual stage”) design. The required common
mode rejection of the differential amplifier, on the other hand, becomes readily achievable.
Limited common mode rejection can be thought of as an asymmetry of the input. The gain from the non-inverting
input to the output is slightly different to that from the inverting input so that, for example (referring to fig. 4.4): -
VOUT  G  G V2  GV1  GV2  V1   GV2
The term GV2 represents the error at the output. The virtual earth voltage, V2, is determined by the open loop gain
of the guard amplifier (typically >105 for a single low cost op-amp). Common mode rejection ratio is defined as
G G and, in data sheets, is often quoted in dB (>80dB or 104 is readily achieved with standard components).
The error, expressed as a ratio (compared to the output signal) is, therefore: -
V2 G GV2
 105 and  104   109
V1 G G V2  V1 
12
Part 4: Monograph 4
In the previous section it was suggested that the two-stage constant current source could be replaced by a voltage
follower. The resistance, RL, consists of the current carrying lead and switch and sets up a common mode, V2, at the
input which is now independent of V1 and much more problematic: -
I RL
V2
R5 VOUT
RT
VC
-VC V1
0V
Fig. 4.5 An alternative approach
In an extreme example RL could be 10Ω with a measuring current of 10mA hence V2  100mV . A reasonable
requirement is that this should result in an error at the output of the differential amplifier equivalent to no more than
the noise limit  1nV  . If one assumes a zero differential signal RT  0 : -
V2 V1  0  VOUT  GV2
VOUT G G
Referred to the input:  V2  1nV   108 CMRR  140dB
G G G
This is a very tall order for a conventional design (virtually impossible). Fortunately there is a simple solution: a
“bootstrapped” floating power supply. The power supply to the differential amplifier and ADC is driven, very
accurately, to follow the common mode voltage. The differential amplifier/ADC stages “see” no common mode.
See fig. 4.6.
The problem is moved to the digital interface where the odd 100mV of common mode should not be a problem,
especially if optical or differential signalling is employed – a good idea anyway (for speed and rejection of
interference).
The microK employs an FPGA to perform all the high speed logic functions (ADC control and digital filtering) and
it should be possible to incorporate, if necessary, a (less speed critical) serial interface to the main processor with a
pair of opto-couplers.
13
The principle of the inside-out follower [1] is quite simple: the input signal is in series with the negative feedback
connection so that the 0V(B) of the bootstrapped supply “follows” V2. The supply to the high gain block (HGB) is
also bootstrapped so that it, also, does not “see” any common mode. The open loop gain, at low frequency, of the
HGB is so high that following accuracy can be better than 1ppm (two-stage HGB) [2].
0V V+(B)
V2
HGB 0V(B)
=V2
V-(B)
Floating PSU
Fig. 4.6 The inside-out follower and bootstrapped power supply
In a revealing comment Bramley et al conclude that the differential amplifier contributes significantly to a
quadratic non-linearity of the microK measurement system [3]: -
“A good example of this [quadratic error] is the power-coefficient of the resistors used to set the amplifier
gain. Typically, resistors have a linear temperature coefficient of resistance. However, since the power
dissipated in the resistor is proportional to the square of the voltage across it, this leads to a variation in
resistance that is quadratic with applied voltage.”
Fig. 4.7 The quadratic error due to the current source (courtesy Bramley et al [4])
Elsewhere the quadratic error is also attributed to the output resistance of the current source [4].

2. Part 4, monograph 1: “High Gain Blocks”.
3. Bramley, P. et al: “Cost Effective Techniques …”.
4. Bramley, P. et al: “Using a Substitution Measurement Topology…” See section 3.3.1
14
Part 4: Monograph 4
5. The sigma-delta ADC
5.1 Overview
The analog to digital converter is described, in outline, in Bramley et al [1]: -
Fig. 5.1.1 The sigma-delta ADC in outline (courtesy Bramley et al [1])
The following analysis is based on the above (Fig. 5.1.1) and a few other clues (i.e. more speculation): -
VR MCLK
VIN VE V4 32 bits
-H(s) ADC Latch DSP
HGB SCLK 5 bits

VF
PWM
VR MCLK
Fig. 5.1.2 A functional analysis
Unlike a conventional bridge the microK ADC is designed to oscillate between states either side of null balance.
The main elements are a summing junction, a high gain block (HGB with dynamic characteristic H(s)) a high speed
analogue to digital to converter (5 bit: probably a flash type ADC), a high speed latch and a very accurate pulse
width modulator (PWM). The output is a rapidly changing 5 bit code which is then passed through a low-pass
digital filter (digital signal processor: DSP). At its very simplest this could be a simple accumulator that adds
together a large number of samples. The microK DSP produces an output of up to 32 bits, apparently.
A summing junction was chosen, rather than a differential input stage, probably because the common mode
rejection required would otherwise be impractical (see the next section).
The high gain block (HGB) is, in effect, a very high gain amplifier (at low frequency) with a dynamic characteristic
designed to ensure closed loop stability (apart from the high frequency oscillation) and high accuracy. Bramley et
al describe this as “four integrators” [1]. This may be the case at low frequency but it would be better to use a
single integrator followed by three “one-plus-integrators” (see later) [2]. This author refers to such a circuit as a
“four-stage HGB”. Four stages does seem a bit excessive – it is shown in [3], for example, that three stages should
be sufficient for the level of accuracy required.
1. Bramley, P. et al: “Better Accuracy in Temperature Calibration…”

2. PB insists on “four integrators”. See section 6.16.
3. Part 4, monograph 1: “High gain blocks”. See section 3.2
15
The flash ADC sampling frequency and PWM cycle period is set by the sampling clock (SCLK). In the microK
literature this is variously specified as 5μs [1] and, more recently, 10μs. In the latest brochure, for example,
(section: Performance by Design): “In order to achieve our target of <0.05ppm, we needed to be able to produce
pulses whose edges have relative timing errors of <0.5ps” [2]. This is consistent with a PWM period of 10μs: -
0.5 ps
 5 108 (0.05ppm)
10s
For the MicroK Gold the timing accuracy is even greater (±0.1ps).
The accuracy of the pulse width modulator is paramount. The PWM is, in effect, a multiplying digital to
analogue converter (MDAC): the average value of the output, over a single cycle, is the reference voltage
multiplied by the 5-bit binary input code (see below). This is the key to the ADC’s astonishing performance: -
The low resolution of the flash ADC/PWM pair means that the loop is very unlikely to achieve an exact (stable)
null balance. The loop will usually oscillate, therefore, switching between states either side of null balance.
Apart from this instability one can think of the whole ADC as a linear feedback circuit, albeit with an A-D-A
conversion process inside the loop (flash A-D followed by PWM D-A). See fig. 5.1.3.
As long as the PWM conversion is accurate the average value of its output, VF , is proportional to the average
value of the 5-bit data stream and the master voltage reference. If one assumes that the A-D-A conversion process
has a gain of one and the input, VIN , is a low frequency sinewave then, in the complex representation s  j  , on
average, referring to fig. 5.1.2: -
 1   H s 
VF  1    V4  1   H s  VF  VIN  
VF

VIN 1  1   H s 
The symbol VF represents the average value of the PWM output (as seen with a low-pass filter) and  a small
error (systematic or random) due to the A-D-A process. With very high H s  to a very good approximation: -
VF
1     1 and H s   1  
1
1
VIN H s 
The circuit (fig. 5.1.2) behaves like a high accuracy inverting amplifier (gain = -1): VF  VIN
I.e. If one viewed the PWM output signal, VF, through a 1kHz low-pass filter, for example, it would appear to be an
inverted version of V4.
Since VF is accurately proportional to the average of the 5-bit data stream the latter is accurately
proportional to the input voltage.
The brochure also specifies a “measurement time (per channel) of < 2s (1s with computer interface)” representing
200,000 (100,000) 5-bit samples [2]. It is likely that many more samples are required for 10ppb resolution. If one
assumes 106 PWM cycles (10s average time) and the master clock jitter is purely random then the timing accuracy
reduces to 103 times that required for a single cycle (i.e. 0.1ns). For more see [3].
1. Bramley, P. et al: “Better Accuracy in Temperature Calibration…”

2. Brochure: “The new microK family of precision thermometry bridges”. Edition 2 (1516).
3. Part 4, monograph 7: “High accuracy DACs and ADCs.
16
Part 4: Monograph 4
It is clear that the feedback must be negative. A signal inversion could be implemented in the A-D-A circuitry but
it is probably simpler to incorporate it into the high gain block. In the analysis of op-amp circuits, for example,
feedback is applied to the inverting input (representing 180 degree phase shift) and the loop gain is usually
specified from the non-inverting input, hence the choice of sign convention (-H(s) rather than H(s) ).
The input is bipolar (range from -5V to +5V) [1]. This could be implemented in the PWM design but it is probably
much simpler to keep the PWM unipolar (0 or 10V) and add an offset into the summing junction. A reasonably
good low frequency model is, therefore, a high accuracy inverting/summing amplifier, based on a high gain block: -
R1 R2
-VR/2
VIN
VF
H(s)
R1
HGB
0V
0V
Fig. 5.1.3 A low frequency model of the sigma-delta ADC (unipolar VF )
For an input range of ±5V, therefore, the local reference voltage needs to be VR = 10V and the PWM
output range is VF = 0 or 10V. The average output of the PWM is accurately related to the input: -
R2  V 
VF   VIN  R 
R1  2
VF R  H s  
  2  
R1  1  H s  
The AC analysis of this circuit results in the transfer function:
VIN
The factor in brackets (the “D” factor) embodies the dynamic response. It also describes the difference between the
actual output and the ideal. At low frequency the gain is very high so that, to a very good approximation: -
VF R  1 
H s   1    2 1  
VIN R1  H s  
According to PB, however, the PWM output is bipolar [2] (probably -5V or 5V) and the offset is not required. The
analysis, however, remains the same: -
R2
VIN
VF
H(s)
R1
HGB
0V
0V
Fig. 5.1.4 A better low frequency model (bipolar VF )
It would be reasonable to assume that R1 and R2 are a pair of accurately matched resistors (ideally: R1 = R2).
1. Bramley et al: “Cost Effective Techniques…”

2. PB comment: “Our PWM is actually bipolar. The symmetry helps ensure linearity…” See section 6.16
17
5.2 The summing junction and high gain block
To avoid problems with common mode the summing junction is almost certainly a virtual earth – adding currents.
In the paper by Bramley et al, for example, a diagram shows resistors connected to the non-inverting input of an
op-amp with nothing but a capacitor providing the feedback to the inverting input [1]. This is clearly a mistake but
a sufficient clue as to the intention [2]: -
Fig. 5.2.1 Part of the diagram by Bramley et al [1]
Much more likely is the following circuit – combining a summing junction and integrator: -
R2 I C (low tanδ)
VF
F/B
VIN
VI
R1
0V
HGB
Fig. 5.2.2 The first stage (high accuracy) adder/integrator
Resistors R1 and R2 are critical components. Ideally R1 = R2 at least for the time between substitutions. Here is
another problem: R2 includes the output resistance of the PWM D-A converter. I shall, however, continue
with the analysis (more anon).
The result is a falling output, with a constant slope for the first part of the PWM cycle (VF = +5V) and an increasing
output for the second part (VF = -5V: see the appendix for detail). The output of the adder/integrator at the end of a
PWM cycle (≈10μs) is usually higher or lower than at the start: -
ΔV1
ΔVI(T)
VI(t=0)
t1 T
t=0
Fig. 5.2.3 Output of the integrator (single PWM cycle, zero noise)
1. Bramley, P. et al: “Using a Substitution Measurement Topology…” See section 3.3.2.

2. PB comment: “You’re absolutely right….” See section 6.16.
18
Part 4: Monograph 4
The integrator is also a critical component, hence the need for a low noise, high performance HGB and a
good quality feedback capacitor. The extra gain, at low frequency, can be provided with two or three (non-
critical) one-plus-integrator stages: -
VI
C1 C1
R1 R1
0V 1  R1C1 
Fig. 5.2.4 Two one-plus-integrator stages
The combined frequency response for a four-stage HGB is as follows: -

 At very low frequency the gain is huge, limited only by the DC gains of the op-amps. With a low cost op-
amp this is at least 1020 (105 per op-amp). This is much higher than required.
 As frequency increases the HGB behaves like four integrators in series with the gain falling at a rate of four
decades per decade of frequency.
 At a frequency, chosen by design (typically 16kHz), the gain of the one-plus-integrators level off to a gain
of one leaving a single integrator characteristic as the gain passes through 0dB (magnitude of one and
phase lag of approximately 135 degrees at about 100kHz). The resulting 45 deg phase margin provides
sufficient closed loop stability.
 At very high frequency (about 5MHz) the op-amps run out of steam (with “extra poles”) and the gain starts
to drop further, with increasing phase shift.
 The closed loop response has very high accuracy at low frequency but a slight resonant peak at high
frequency. See figs. 5.2.6, 5.2.7 and 5.2.8.
Fig. 5.2.5 Open loop frequency response of a four-stage HGB
19
A four-stage HGB seems excessive. In AC bridge designs three-stage HGBs provide more than sufficient open
loop gain for the target accuracy [1]. I shall assume, therefore, a three-stage HGB, including the flash A-D-A
process. The open loop transfer function is, in the usual complex representation s  j  : -
2
 1  1
H 3 s   1  
  1s   2 s
In a form normalised to the time constant of the one-plus-integrators s  j 1  : -
H 3 s  
1  s 2 with  
2
s 3
1
VF R  H 3 s  
   2 D3 s 
R
The low frequency model of the sigma-delta ADC is, therefore:   2 
VIN R1  1  H 3 s   R1
s 2  2s  1
The “D” factor for a three-stage HGB is, in normalised form s  j 1  [1]: D3 s  
s 3  s 2  2s  1
 is the reciprocal of the feedback factor. If both resistors (see fig. 5.1.4) have the same value then   2

  2 is the ratio of the time constants. The value of  determines the phase margin and the size of the resonant
1
peak and the real and imaginary errors at low frequency for a sinusoidal input. Analysis and modelling (and
experience) indicate that a good compromise is [2]: -
3 4
 f   f  1
  0.4  D3  f   1  j 0.4   0.8  with f1   16kHz
 f1   f1  2 1
The imaginary component represents a phase error (quadrature) and the real part the in-phase error. The
frequency f1  16kHz represents the highest that is practical for readily available (low cost) op-amps [1].
 
Typical component values are: resistors and capacitors for the one-plus-integrators 1  105 s are 10kΩ and 1nF
respectively. For the integrator: -
  0.4    0.2   2  2 106 s  10kΩ and 200pF  f2  80kHz

One could argue for a higher value for the resistors because of the output resistance of the PWM (appears in series)
with a correspondingly lower value for the feedback capacitor. This is probably unwise due to parallel (stray)
capacitance injecting “spikes” into the integrator capacitor. It would probably be a good idea to pass the resistor
through a grounded screen anyway, to minimise this problem. For more detailed discussion see [3].
The slight resonant peak (about +4dB) at high frequency also means that, with a step change at the input, the ADC
output overshoots (see fig. 5.2.6). The transient is quite large (≈ 30%) but converges rapidly to an accurate result
(see figs. 5.2.7 and 5.2.8). Such an event would happen at the start of each reversal cycle unless there is some form
of “preset” of the ADC state by the control logic.
1. Part 4, monograph 1: “High gain blocks”. See sections 2 and 4.1.

2. Part 4, monograph 2: “High accuracy voltage followers”. See section 2.4.
3. Part 4, monograph 7: “High accuracy DACs and ADCs”
20
Part 4: Monograph 4
The dynamic response (frequency domain) for the transfer function is as follows: -
Fig. 5.2.6 Frequency response [1]
s 2  2s  1
D3 s   with s  j 1  and   0.4
s 3  s 2  2s  1
1
The natural” frequency is: fN   16kHz
2 1
1. Excel spreadsheet: “MicroK freq response”
21
The step response (time domain) is as follows [1]: -
Fig. 5.2.7 Unit step response (units of τ1 time constants: 10μs)
Fig. 5.2.8 Error analysis (units of τ1 time constants)
I.e. error settles to <10ppb in 25 time constants (≈ 250μs)
N.B. Settling time could be significantly reduced if the ADC is preset to a suitable state. For more detail see [2].
1. Excel spreadsheet: “MicroK step response”

2. Part 4, monograph 7: “High accuracy DACs and ADCs”
22
Part 4: Monograph 4
5.3 The flash ADC and pulse width modulator
One of the most critical elements of the microK measurement system is the pulse width modulator (PWM).
Whereas the microK PWM has a resolution of only 5 bits it needs to be very accurate – for the microK gold to >25
bits (ratio error < 30ppb)! According to PB the PWM is bipolar [1] (probably switching between -5V and +5V): -
t1
VR
T -VR
VR
MCLK PWM
PWM
signal
integer, n -VR
Fig. 5.3.1 The principle of a bipolar PWM based MDAC
For the ideal PWM the average output voltage, over a single PWM cycle, is the reference voltage multiplied by the
ratio of two integers: -
t1  2n 
VAVE  2VR  VR  VR   1 n  0,1,2,.....N with N  31 (11111 binary)
T N 
I.e. There are 31 time slots and the PWM signal varies from 0 to 31 slots occupied by contiguous “ones”.
In a diagram by Bramley et al it is suggested that the input to the PWM is a (5 bit) binary code [2] (see fig. 5.1.1).
This is not entirely surprising as it is likely that a field programmable gate array (FPGA with 150,000 gates), on
which the microK logic is based, usually includes standard building blocks (including IP or “intellectual property”
blocks). One of these is likely to be a flash ADC with 5-bit binary decoder included. The PWM is also (probably)
constructed with standard building blocks: a synchronous counter (5-bit binary), comparator and parallel latch: -
MCLK Counter resets

Counter
on count 31
MSB A (max) = 30
A 5
(i.e. 31 states)
B≤A
Comparator
MCLK
B VR
5
DSP PWM
Latch signal
Latch VF
SCLK
-VR
V4 5
Inverter/driver
Flash ADC
Fig. 5.3.2 A conventional PWM design

Examples: -
ADC outputs all “zeros” (00000): B≤A is always valid and the comparator output remains one (PWM output = 0).
ADC outputs code 5 (00101): See fig. 5.3.3. (PWM output = 1 for five contiguous “slots”).
ADC outputs all “ones” (11111): The counter never reaches 31 and B≤A is never valid (PWM = 1 for 31 slots).
1. PB comment: See section 6.16.

2. Bramley, P. and Pickering, J.: “Better Accuracy in Temperature Calibration…”
23
It is not clear, in any of the published literature, how the astonishingly accurate timing is achieved. The figure
quoted (0.5ps) for 50ppb [1], however, is not an absolute figure – it is the voltage profile, within each PWM cycle,
that must be accurately related to each 5-bit code. Timing accuracy is only part of the picture. Nothing of the inner
workings of the logic is published and the following is, therefore, highly speculative: -
Some design considerations for the logic circuitry: -

a). The exact frequency of the master clock (MCLK) is not important – as long as it is sufficiently stable over each
PWM cycle. For a PWM cycle of 10μs the master clock is 3.1MHz.
b). Random fluctuation of the master clock frequency introduces noise into the measurement. The effect averages
out over a large number of cycles but may extend the time required to achieve the target resolution. A rather special
(very low noise) clock is probably used.
c). Systematic variations in frequency over each PWM cycle must be avoided. It is possible to imagine, for
example, some interference (an impulse) from the sampling clock (SCLK) getting into the master clock circuit
causing the frequency to jump at the start of each PWM cycle which then begins to settle down to the steady state
frequency. The result would be a non-linearity of the PWM output relative to n (PB confirmed [2]).
Counter 0 1 2 3 4 5 16 31
MCLK
MSB/SCLK
B≤A
PWM
Fig. 5.3.3 Timing diagram of a synchronous PWM circuit (B = 5)
d). The design needs to be synchronous and “glitch free”. Most high speed FPGAs have standard building blocks
that do this, plus methods of distributing a master clock to minimise clock “skew” (i.e. clock transitions reaching
different parts of the chip at different times). In addition to a master (power-up) reset for all flip-flops a master
timing/sequence generator is required. Also, high speed flash converters often employ a track/hold circuit to hold
the input constant during sampling, to minimise glitches (in this case known as “sparkles”).
The timing diagram (fig. 5.3.3) provides an example of a synchronous PWM circuit (see fig. 5.3.2): -
 Counting occurs on the rising edge of MCLK. On a count of N (31) the 5-bit counter self-resets. I.e. it
never gets to 31 (11110 changes to 00000). This is necessary for full bipolar operation (PWM output range
from –VR to +VR).
 The most significant bit (MSB) of the counter can be used as a sampling clock (SCLK). A falling edge
indicates the start of a PWM cycle and is used to latch the flash ADC output. The rising edge of SCLK
could be used to indicate that the code B is valid and can be “pushed” on a stack or into a FIFO memory.
 After a short delay both inputs to the comparator settle to valid states (A and B both valid).
 After a further delay (variable, depending on the inputs) the output of the comparator (B≤A) becomes
valid.
 As long as the total delay is less than half a MCLK cycle (≈160ns for a 10μs PWM cycle) the high speed
PWM latch reliably synchronises the PWM signal to the falling edge of the MCLK. The approximate
PWM signal (error caused by the variable comparator delay) becomes a very accurate PWM signal - the
on/off ratio is accurately related to the binary code B.
 The flash A-D-A process need not be accurate – the feedback loop finds a balance eventually. The data
stream to the DSP, however, must be the same as that which generates the PWM signal. It is best,
therefore, to take the data stream from after the ADC latch.
 With a PWM cycle of 10μs/sample it should be possible to employ a fast microcontroller and an interrupt
driven subroutine (fast “push” and “pop” stack operation) to acquire the data stream.
1. Brochure: “The new microK family of precision thermometry bridges”. Edition 2 (1516).
2. PB feedback: “Timing jitter needs to be good, but more importantly it can't have any significant
correlation with the conversion or measurement cycles.” See section 6.16.
24
Part 4: Monograph 4
e). The PWM output resistance is critical: -
 The “on” resistance of the MOSFETs appears in series with the high precision resistor (R2 see fig. 5.2.2)
and needs to be sufficiently small, symmetrical and stable over the time between substitutions.
 The summing resistors must be “lowish” or else contribute Johnson noise. If R2 ≈ 10kΩ then ΔR ≈ 0.1mΩ.
 A very low output resistance (≈ 20mΩ) is possible with large area MOSFET devices but the problem is
then large gate-source/drain capacitance and large charge injection.
f). It is not clear how the high level PWM signal (10Vpk-pk) is generated – all high speed logic families and
FPGAs operate on much lower power supplies. Perhaps there is a high level MCLK and a level shifting MOSFET
driver before the PWM signal is synchronised.
g). It should be possible to dispense with the binary encoder in the flash ADC. The result is a faster conversion: -
VR VIN
R/2
30×R 31 outputs
(n of N)
R/2 31 Comparators
-VR
Fig. 5.3.4 A basic flash ADC (bipolar without binary decoder [1])
The n of N code scheme is easily converted to a PWM signal with a pre-settable shift register: -
MCLK VR
SCLK
Shift register PWM
signal
DSP 31
-VR
V4 ADC
Fig. 5.3.5 A simplified high speed PWM
N.B. The n of N code is often referred to as a “thermometer” code, by analogy with the level of mercury in a simple
thermometer (example: 1111100000000….etc represents n = 5). One advantage is that it is less prone to large
errors due to “sparkles” (a fast changing ADC input and one relatively slow comparator can produce a false 0
(example: 1110100000….etc for n = 5). This would represent an error of 1/31 for the PWM cycle and would be
easily corrected by the feedback loop. A binary decoder, on the other hand, could introduce a very large error,
upsetting the loop equilibrium, requiring time to recover. A track/hold circuit would help.
h). However the performance is achieved it is clearly very ingenious!
1. It is usual for flash converter comparator thresholds to be set half way between binary states, hence the
two R/2 resistors.
25
6. Feedback and comment from Paul Bramley
“I don't really agree with this statement. If set to comparable settings i.e. ASL bridge bandwidth and number of
samples per reading set to give ~same response time, then the two are very similar. Users report that the microK
gives consistently same standard deviation and F18/F900s give more variable SD when making same measurement.
I concede that "on a good day" an F900 can give slightly lower SD as it should due to differences in the way it
works, but competent users prefer microK.”
6.2 Performance compared to conventional null balance bridges
“Other and very significant differences are: -

1. Drift free. ASL/MI bridges require regular service visits to maintain alignment and therefore performance.
2. Much higher reliability due to use of more modern manufacturing techniques, elimination of contacts
(connectors, potentiometers) and robust design (comprehensive input protection).”
6.3 Is it a bridge?
“Yes... I used to think of this as a reversing DC potentiometric instrument. However, when you look at the
measurement architecture it looks more like a Wheatstone bridge. One arm is formed by the DUT and the current
sense resistor on the current source (these carry the same current, of course). The other arm is formed by the current
steering resistors in the ΣΔ ADC. The null detector is the one in the ΣΔ ADC, which works by balancing its input
voltage against the delta modulated bit stream it generates. The measurement is, of course, dependent on the values
of these 3 resistors so we overcome this problem by using a substitution technique. Anyway, it really is very like a
Wheatstone bridge plus some active circuitry (which you would use in any modern Wheatstone bridge anyway).
More detail is in the paper attached *- see section 4) [1]. To be honest, I'm less concerned whether people think of
it as a bridge, it's only its performance that matters.”
*The section to which this refers includes the following diagram (and the mistake mentioned above – see section
5.2): -
Fig. 6.3.1 *From section 4 (courtesy Bramley et al [1])
CID: Does it look like a Wheatstone bridge? Can you see any mistakes?
26
Part 4: Monograph 4
6.4 Timing accuracy
“Yes, timing accuracy is critical, but only relative timing of edges as PWM is used as the feedback DAC in the ΣΔ
converter.”
6.5 Reversal frequency and 1/f noise
“The reversal also eliminates the 1/f noise from amplifiers provided reversal rate is above the corner frequency.
Input reversed "behind" connectors for DC voltage measurements. Current reversed for resistance measurements.”
6.6 Master reference voltage device
“We use a very good buried zener reference. As you say this is one of the ultimate limits for voltage measurement.
Not such a problem with current as the reference is shared between ADC & current source so it's inherently a ratio
measurement with ΣΔ ADC providing the balance mechanism.”
“The diff-amp is "floating" but we use active guarding to maintain one of the inputs at an internal 0V reference.
This eliminates the common-mode problem optimally by ensuring that lead resistances to the 4-terminal resistance
do not lead to a common-mode voltage.”
6.8 Elimination of amplifier offset and thermal emfs
“Actually, we make more than 2 measurements and weight them. For example, using 3 with the middle one
reversed but weighted by x2 eliminates any effect of offsets that are changing linearly with time... a useful tip I
picked up from my former brilliant colleague, John Yewen. But the principle of reversal is, of course, involved (but
only eliminates "static" offsets).”
6.9 The need for certain components to have very good short term stability
“The + & - currents are very well matched. However, the current reversal means that the stimulus is the difference
between the two current polarities and this difference is measured with the ADC. Both of these change linearly
with Vref so I don't think it is just the substitution that eliminate sensitivity to imbalance between the + & -
current.”
Also: “Yes, with the "fast" reversals the stability of gain etc. is not a problem, but you are right... this is a pre-
requisite.”
6.10 The measuring currents are proportional to a master internal reference voltage, VREF, probably via a
12-bit multiplying digital to analogue converter
“Yes, it is a 12-bit DAC. You can lose "probably" if you wish”.
6.11 The current regulator
PB feedback confirmed that section 3 analysis is not far from the truth “…the principle is correct” but later “…we
also don't wish to give away our IPR!”
“We actually buffer (voltage follower) V4 connecting back to R4 which changes your calculations (simplifies
them) but the principle is correct. We tend to publish only the principle and leave out non-essential detail.”
“We couldn't use one JFET for both directions (gate channel would become forward biased). We therefore use both
a P & N JFET where the "Unused" one is isolated by suitable biasing.
“Again, I think regarding the JFET as the active component in a servo system rather than a voltage controlled
resistance helps clarify operation. Of course we use JFETs so that there is no current injected into the current
source circuits.”
27
6.12 Is the current regulator second stage a “cascode” stage?
“I think of Cascode as a common base/gate stage following an output stage to provide isolation. This is commonly
used to reduce the miller effect to improve bandwidth but it is equally good at isolating the output from the load to
increase output impedance. I think the term is legitimate.”
Later, also: “Just reading this now after commenting above. Wikipedia does mention the increased output
impedance as well as the more usual benefit sought of higher bandwidth.”
Referring to fig. 3.3 (two stage design): -
|
|
|
Detailed feedback redacted to protect IPR.
|
|
|
Referring to estimated component values: -
“Values are wrong (wouldn't wish to disclose precise details obviously) but the principle is correct.”
6.13 Suggested alternative design (Fig. 3.7): -
“Not as good as above when you consider the effect of current flowing in lead (& track resistances). You either end
up with common mode voltage or sense current being affected by these resistances. It's unavoidable as far as I can
see.”
“As you seem to have deduced, the amplifier is considerably more complicated than disclosed but the principle is
correct. We use an array of op-amp based amplifier stages to amplify the signal. These are then added/averaged.
The signal sums linearly and the noise (uncorrelated) sums as the square root. You therefore get a root N (N =
number of amplifiers) improvement in voltage noise at the cost of current noise. It's exactly the same noise
impedance matching using a transformer in F18... but it’s harder with DC because you need a lot of amplifiers
rather than just optimising the turns ratio!
For commercial reasons we don't provide much more detail... it wasn't easy to get it working. But it does work,
giving true differential, low voltage noise (noise impedance is a few hundred ohms) highly linear (ppb) amplifier.
We did look at using matched transistor pairs such as the LM194 but chose to use a different approach using
multiple op-amps (in parallel) to lower the noise and in series (to increase gain & ensure adequate linearity). We
don't really need such a high CMMR to achieve our performance. By connecting the sense point of the guard
amplifier to the diff-amp input and using the cascode isolated current source there is virtually no effect of lead
resistance on the current source OR the CM of the diff-amp.”
6.15 Bootstrapped PSU
“Yes... a good technique and used only on the more accurate microK products.”
“Yes, one of the factors we had to consider in the design of the ultra-linear amplifier is the power coefficient of the
resistors used to set the gain. As you appreciate, these need to be lowish value (to avoid Johnson noise) but then
their non-linear resistance with voltage can create gain non-linearity.”
28
Part 4: Monograph 4
6.16 The ADC
“All correct though the appearance of PWM might be a little misleading for readers. It is a 5 bit PWM feedback
DAC that is fed with a sigma-delta modulated feedback code. Not sure it needs elaboration, but showing just a
PWM stage might lead people to think that this is a PWM DAC being used directly as an ADC.”
“A simple accumulator works, but it isn't optimal of course. We use various filters (including simple accumulation)
depending on the target specification.”
“The 2s (timescale) includes the reversals (several of them) and the substitution. The accuracy is 30ppb but a single
reading at 2s has a high uncertainty due to noise (even the Johnson noise is more than the 30ppb). To get the noise
low enough to be able to "use" the accuracy requires multiple samples per reading (using the settings) in the same
way that the F18/F900 need to reduce the bandwidth in order to exploit their underlying linearity.”
“More stages gives us more gain and lowers the noise, we do use 4 stages in microK as design simulations showed
this to be worthwhile. The details are fading from memory as this was all done in 2005!”
“Spot on, nice description of how it works. Our PWM is actually bipolar. The symmetry helps ensure linearity (I
think!)”
Error in outline diagram (fig. 5.2.1): -
“You're absolutely right! Can't recall why I used the poor representation for the integrator (may be a mistake or
may have just been trying to indicate the intention of the sub-circuit). Not quite as fig 5.2.2 as it really is fully
bipolar ΣΔ ADC, but the principal is spot on.”
“We find that 3 integrators is okay for a normal ΣΔ ADC and more only leads to instability as you indicate. Have a
5-bit feedback reduces the quantisation noise and simultaneously allows us to add another integrator. When
modelled the quantisation noise reduces not by a factor of 32 (5 bit) but by about 600. This makes the QN
negligible (the pre-amp noise then dominates the input referred noise.”
“Absolutely right though the ADC dead time is very small. The photoMOS relays have on/off times of a few ms so
these are more significant (though worth it for their solid state reliability). The lost time does reduce S/N ratio but
not by much.”
“Yes, the relative timing accuracy is critical as it carries the full accuracy burden of the measurement. We have
swapped an analogue accuracy (for a conventional 5-bit DAC) for a timing requirement. This is generally easier
thought it took us many months to develop the technology to achieve this and is part of the core IP (all hidden in
the FPGA and surrounding circuitry, of course).”
“Timing jitter needs to be good, but more importantly it can't have any significant correlation with the conversion
or measurement cycles. It wasn't too hard.”
“It's properly bipolar so this is not a problem.”
Critical components in the flash ADC?
“Yes, we don't need anything "special" and rely on the design being very tolerant rather than high stability
components.”
“The design of the ADC internal processing is such that it very rapidly converges after a step change. There is very
little latency. We lose only a few cycles and this is built into the FPGA logic.”
“Hi Chris, thanks for sharing a truly impressive overview (better than anyone else I have come across). I think you
have done a great job in understanding the guts of the microK. Some of the conclusions are not correct and I have
tried to share information where I can. Obviously a lot is rather valuable IP and regrettably I can't really go further.
I have learnt a few lessons from reading your work here and will put them to good use in future iterations of the
microK family.”
29
6.17 Further comments from PB
The main aspects of the microK design that were intended to be improvements over IVD instruments were:
1. All solid state design to improve reliability. There are no relays (the reed relays in F18 were a source of regular
failures).
2. Minimise connections and use gold finish were unavoidable (tin plated contacts in F18 often failed after a few
years, also many silver plated open trim potentiometers used in F18 used, the wipers of which would fail… no
potentiometers used in microK).
3. Inherent stability using substitution topology. The IVD solution argues that it is inherently stable because a
transformer cannot lose or gain turns (I used this feature whilst at ASL). However, not all the flux in the primary
links the secondary (even with the magnetisation windings working) and the shortfall is made up by using a tweak
winding to compensate for this. Unfortunately the circuit that performs this function can itself drift with time Also.
After digit 4 the ratio is realised using a MDAC, this is an old part with limited stability compared with more
modern equivalents.
4. Robustness: the microK has been design to survive 240V AC as well as full 5kV transient discharges directly
into the input terminals. I have tried this and it works although it did eventually fail due to a flash-over on the PCB
caused (I believe) by a large transient on the mains supply. We don’t advertise this design feature as we don’t want
customers trying it out! The F18 range were easily damaged as the front end goes straight into the matched
transistor pair & other electronics. Service repairs of F18 were common compared with precisely no field failures
for microK in 12 years and with a larger installed base.
5. EMC: the front end of microK has been developed to provide immunity to radiated and conducted emissions to
the EU standards required for CE marking. F18 used the get out clause in the standard that allows you to cap
sensitive inputs for EMC testing (i.e. the instrument isn’t really tested for EMC). Users report that microK gives
consistent noise levels (inherent to the bridge) where competitor (ASL, Guildline & MI) exhibit varying noise
levels depending on what other equipment is in use. In theory, the IVD technology should provide better signal to
noise (if input referred amplifier noise = detector noise) because it is constantly balancing rather than switching
between measurement of the DUT & reference. I have been thinking about this over the weekend and have come
up with a new topology that overcomes this problem. When we work on the next iteration of the microK range I’ll
see if this can be included in the design. Many thanks for prompting me to look again at this issue, it’s been a
useful exercise in trying to see microK versus IVD bridges from an outside perspective. Since it’s launch the
microK has steadily established itself as the instrument of choice for primary temperature metrology. Two recent
comments made to me at the last TEMPMEKO conference illustrate this:
1. Greg Strouse of (a long time advocate of ASL bridge technology and a good customer when I was with ASL)
chided me (tongue in cheek) because he had been telling people for many years that if they wanted the best
measurement instrument that had to buy and ASL F-bridge because AAC bridges were simply better than any DC
based instrument but now he was having to eat his words and recommend the DC based microK. Greg used to buy
only ASL AC bridges but NIST are now on a rolling programme to replace all their F-bridges with microK.
2. Wes Tew approached me to say that he had been telling people that DC bridges would never compete with AC
bridge because no one could make a DC current source that was stable enough or an ADC that was sufficiently
linear and low noise but he said “I was wrong”. I really appreciated his comments as (like you) he understood the
magnitude of the challenge in getting a reversing DC instrument to provide performance only previously obtainable
with an AC resistance bridge.
An independent assessment by NIST & NRC of a range of instruments from ASL, MI, Guildline & Isotech
(Metrosol) showed the microK to exceed specification with the two microK bridges tested come out best of the ~15
tested (outperforming even the F900). I can’t seem to find the report but below is a presentation that I think was
based on this work. You will see that the microK 100 came in at about half its specification limit whereas the F18
bridge was twice it’s limit. My experience is that F18/F900 can just about achieve their specification but require
annual realignment to maintain this. On the other hand, microK is entirely consistent and needs no maintenance
(there are no pots to adjust anyway). Whilst customers can send their microK back for checking (and as you
observe it is included in some packages) very few do, but when they do there are absolutely no changes in
performance (linearity checks are unchanged within the measurement uncertainty).
https://www.isotech.co.uk/assets/uploads/Technical%20Articles/performance-assesementbridges.
pdf
30
Part 4: Monograph 4
Appendix: More analysis of the microK sigma-delta ADC
The summing junction and an integrator are most likely combined in a single stage, reproduced for convenience: -
R2 I C (low tanδ)
VF
F/B
VIN
VI
R1
0V
HGB
Fig. 1 The summing junction and integrator
If one assumes an ideal HGB, equal resistors, Ohm’s law and the basic property of a capacitor, the current is: -
VIN VF VE dV
I    C I
R R R dt
The equivalent error voltage is VE (see overview block diagram, fig. 5.1.2). If one also assumes that the PWM is
bipolar (i.e. switches between -VR and VR): -
First part of the cycle: VF  VR  VE t   V1  VIN  VR for 0  t  t1
Second part of the cycle: VF  VR  VE t   V2  VIN  VR for t1  t  T
t1
V1
0V
V2
t=0 T
Fig 2. The error voltage as a function of time
T represents the period of a single PWM cycle (probably 10μs). Divide by C and integrate, retaining the negative
sign on the LHS for convenience: -
t
  VI t  
dV V 1
 I  E
dt RC  V d
0
E with   RC (The time constant of the integrator)
If one assumes that the input and reference voltages are constant.
t
 VI t   V d  V  V t  0
1 t

First part of the cycle: for 0  t  t1
0
 1 1 I
 VI t  
1
t
t  t1   V t1  V t  0 for

Second part of the cycle: V d  V t1  t  T
t1
2 2
 1
 I
31
VI t  0 is the initial output of the integrator (at the start of the PWM cycle). We are primarily interested in the
change in output: subtract VI t  0 : -
 VI t   V1
t
First part of the cycle: for 0  t  t1

Second part of the cycle:  VI t   V2

t  t1   V t1
for t1  t  T
 1

The result, assuming no noise, is a falling output, with a constant slope for the first part of the cycle and an
increasing output for the second part: -
V1
ΔVI(T)
VI(t=0)
t1 T
VI (minimum)
t=0
Fig. 3. A typical output of the integrator
The change at the end of the cycle is:  VI T   V2

T  t1   V t1  V T
 VR
2t1  T 
 1
 IN
 
It is highly unlikely that there is no change after just one cycle – the input voltage, including noise, must be exactly
equal to the average output of the PWM (one cycle). It is useful, however, to check this (special) condition: -
 2t 
VI T   0  VIN  VR 1  1 
 T 
The ratio of times is the ratio of the ADC output (n ) and the total count of the PWM (N). For this special case: -
t1 n  2n 
  VIN  VR 1  
T N  N
This is consistent with the aim: VIN  5V  5V for n = 0, 1, 2…N and VR  5V
It is also worth checking how the circuit would operate in practice. The minimum voltage at the output of the
integrator (value at time t1): -
- VI t1   V1  VIN  VR 
t1 T n
  N
If one assumes that n is close to the correct value for the given VIN (most of the time in normal operation): -
 2n   2n  T n  n2 n  T
VIN  VR 1     VI t1   VR 1   1  VI t1   2VR  2  
 N  N  N N N 
This is a function of the form: yx   x 2  x which has a minimum at x  0.5

n
I.e. When  0.5 corresponding, very approximately, to mid-range input (n = 15 or 16 and VIN ≈ 0V).
N
32
Part 4: Monograph 4
It is also reasonable to assume (see later) that the integrator time constant is about the same as the PWM cycle
period (at least within a factor of ten): -
 0.5 and VI t  0  0 and   T  VI min   

n VR T
 2.5V
N 2 
This seems reasonable though it is clear that  must not be much smaller than T . A larger value of  corresponds to
a lower open loop gain and reduced closed loop accuracy - a major trade-off (speed and accuracy versus overload).
The worst case happens, however, when the input changes from one extreme to the other (polarity reversal: say -5V
to +5V or vice versa) at the worst possible time (at the start of a PWM cycle). The output of the PWM is +VR (+5V)
for the whole cycle (to balance the previous -5V input) so that the equivalent error voltage is +10V. The slope is,
from above, (assuming:   T  10s ): -
dVI V
 E with VE  VIN  VR  10V
dt RC
dVI  10V  10V

The worst case slope is, therefore:   5  1V s
dt  10 s
This is well within the capabilities of a reasonably good op-amp. The worst case output after 10μs is  10V . This is
also within the capabilities of the first stage (with ±15V PSU) but it will almost certainly overload the second and
third stage (one-plus-integrators) and flash ADC. The loop must be designed to recover from such overload
conditions, in a controlled way, and the timing/control/data collection algorithm should allow for the extra delay:
possibly more than the response of the ideal (linear) loop response.
More generally the input voltage can be anywhere within the range. One can describe the difference between the
input and the PWM state with a parameter  k . At the start of a measurement cycle (initial state n0): -
 2n0   0  
VIN  VR 1  
 N 
If the input voltage remains constant then: n0   0  nk   k with k = 0, 1, 2, …
The index k represents the number of PWM cycles. After the first PWM cycle, from above: -
 2t  T  T  2n0   0  2t1 
 VI T   VIN    VI T   VR 1 
T
 VR  1   1
     N T 
0 T
VI T   2VR
t1 n0
This simplifies nicely:  
T N N 
The (fast) change in integrator output passes straight through the one-plus-integrators to the flash ADC input.
The change at the flash ADC input, in terms of the average voltage interval (one bit) for adjacent states, at the end
of the first PWM cycle is, therefore: -
n1  n1  n0  VI T  
2VR T
 0
N 
T
More generally: nk  nk  nk 1   k 1

33
a). The approximation is due to the fact that the intervals are unlikely to be exactly the same – it depends on the
accuracy of the flash ADC. An accuracy of 1% should be good enough and is easily achieved [1].
b). If  0 is numerically positive then the input voltage corresponds to a state above n0. The output of the integrator
increases taking the input to the ADC in the right direction (increasing n).
c). The size of the change depends on the integrator time constant, relative to the PWM cycle period. If one chooses
them to be about the same   T  the change at the ADC input corresponds to very nearly the same as the initial
error. The first PWM cycle should be sufficient, therefore, to reduce the error to less than one (least significant) bit
of the PWM  1  1  1 . The advantage would seem to be speed – rapid convergence to approximate null
balance. The main disadvantage is instability – once the error has reduced to less than one bit the loop oscillates
erratically, successively overshooting and/or undershooting state thresholds. This problem is worst at PWM
threshold boundaries, even for longer time constants.
d) If one chooses a longer time constant   T and a high resolution ADC/PWM pair the result is a quasi-
exponential convergence [2]. An exponential converges to within 10ppb in around 20 time constants.
e) Large transients (polarity reversals and substitutions) could be avoided with a smart controller – loading the
PWM at the start of each “X” (50ms) measurement period with the previously remembered value.
f) Once the error  reduces to less than one interval the loop oscillates to produce a lower frequency triangle wave
superimposed on the higher frequency triangle wave (at the integrator output). If the frequency of oscillation is
sufficiently high it passes through the one-plus-integrators largely unaffected and, at the output of a track/hold
circuit, the signal would more closely resemble a step-wise sawtooth (see fig. 5). The shape and frequency depend
on the input voltage relative to the PWM states.
g). With a sufficiently large number of PWM cycles the extremely high gain (at low frequency) before the flash
ADC ensures that the average output of the PWM is the same as the average input voltage over the same time
period. With a three stage high gain block (total gain of >1015 at <10Hz), for example, an error of 5V at the flash
input corresponds to 5 × 10-15V referred to the input! The loop in effect “counts” the total number of +VR and –VR
quanta.
h). Later models probably have a minimum ADC “X” measurement period of 50ms (i.e. 5,000 PWM cycles of
10μs). Settling time is probably of the order 10ms so that 4,000 samples are available for calculating the average.
The current is then reversed and the measurement repeated. The second resistor is then substituted and, with a
current reversal, the minimum ratio measurement time is 200ms. The process is then repeated ten times for the
minimum measurement time quoted of 2s “per channel” (five times for 1s with computer interface) [3]. For higher
resolution and accuracy the total measurement time is quoted as up to 50s (a total of 5 million samples of which 4
million (80%) are probably useable).

2. A quasi-linear system?
In the limit N   the variables n and  become continuous. The change after each PWM cycle is: -
T
n  n  n          

If one also considers a large number of PWM cycles with a relatively large integrator time constant (a
timescale long compared to the PWM cycle period) and approach the infinitesimal limit: -
d  t
  t    0exp   
dt
  T and T  dt    d  
   
We have, therefore, a reasonably accurate model of a quasi-continuous feedback system, driving the
output of the ADC, with each PWM cycle, to a null balance with an exponentially decaying error.
3. Isotech brochure: “The new microK family of precision thermometry bridges”. Edition 2 (1516).
34
Part 4: Monograph 4
The lower frequency triangle wave starts from below the n-state threshold until it reaches above the upper
threshold. The PWM state then changes to n+1, the error becomes 1   (i.e. negative) and the integrator ramps
down until it falls below the lower threshold and the state reverts to n. The cycle then repeats. If   0.5 (about
half way between PWM states) with a long integrator time constant (say   10T ) the sawtooth is roughly
symmetrical and there is little overshoot or undershoot (see fig. 4).
With   0.5 and   10T the input to the flash ADC would look something like the following. The dashed line
corresponds to the actual input voltage (half way between thresholds n and n + 1): -
n+1
k2 cycles down
k1 cycles up
VR

α N
n
k1T k2T
Fig. 4 Oscillation between states at the output of a track/hold circuit
If  is not too small it is possible to estimate the period and frequency of the oscillation: -
2VR
The number of PWM cycles required for each part of the sawtooth is: k  VI
N
Referring to fig. 5, therefore, the numbers of cycles for the up ramp and down ramp are, respectively: -
 
k1  and k2 
T 1   T
  
The period of oscillation is: k1T  k2T   
 1    1   
nk1T  n  1k2T k2
The average value from the data stream is, as expected: n  n
k1T  k2T k1  k2
k2
but:   n  n 
k1  k2
The average state is close to the correct value within each cycle of oscillation. This looks promising as a large
number of such cycles provide an even closer approximation to the required average value.
Unfortunately, with a long integrator time constant, the maximum frequency is below the maximum practicable
one-plus-integrator frequency (typically 16kHz [1]) and the integrator signal does not pass through but undergoes
two more integrations, reaching the upper and lower thresholds much more quickly. Fig. 5 is no longer valid and
the analysis is far more complicated [2]. For example: -
0.25
The maximum frequency is when   0.5 so that with   10T  100s : f MAX   2.5kHz
10 4 s
1. A higher frequency increases loop gain and improves closed loop speed/accuracy. See section 5.2.
2. PB insists “four integrators” relying on computer simulation, apparently. See section 6.16
35
With smaller and large values of  the frequency is even lower. This would suggest that a lower value of
integrator time constant is preferable. If  is small (the input is close to a PWM state), for example, it takes a
large number of PWM cycles to ramp up to the next state but only one or two to ramp back down again. The
resulting frequency is higher (except for values of  close to 0 or 1). The sawtooth is highly asymmetric and there
is a strong possibility that the down ramp overshoots (see spreadsheet simulation fig. 5). The frequency and shape
of the signal is more complicated and difficult to predict but, at least, the oscillation is mostly at high frequency and
the low frequency model of the loop is largely valid. In practice low frequency noise is also present (greatly
amplified) which the loop attempts to correct (equivalent to a varying input signal). Mid and high frequency noise
probably cause occurrences of PWM states far away from the states either side but the loop should be able to cope
with this – unless the ADC input exceeds its range (overload).
It is surprisingly easy to model the (noiseless) oscillation with a spreadsheet.
The first row contains initial conditions (state = 1 (up ramp), V = 0)
Column A: 0-100 iterations for horizontal axis
Column B records the current state (1 for ramp up or 0 for ramp down), which is copied from the row above
(previous state) column D.
Column C: Calculate new voltage: =IF(B6=1,C5+$G$4/$H$4,C5-(1-$G$4)/$H$4)
Column D: Calculate new state: =IF(B5=1,IF(C5>1,0,1),IF(C5<0,1,0))
Cells G4 and H4 hold values for  and  T taken from slider controls.
In the following example   0.1 and  T  1 . Note the large undershoot on the down ramp.
Fig. 5 A spreadsheet simulation
The calculated average value of alpha (100 PWM cycles) corresponds reasonably well with input alpha.
36
Part 5: Monograph 4
JFET Theory
1. Introduction
An N-type JFET is basically a thin conduction channel of N-type semiconductor material embedded in a P-type
substrate forming a high quality PN junction. At each end of the conduction channel connections are brought to the
surface with N-type material (drain and source). A single connection is made to the substrate (the gate). Whereas
some devices are precisely symmetrical with regard to drain and source others are designed to minimise on-chip
capacitance between the gate and drain. At low frequency the drain and source are usually interchangeable.
An insulating depletion region is formed at the PN junction. This acts like an insulating dielectric whose thickness
depends on the voltage difference between the channel and gate. When a current flows through the channel the
voltage difference varies (down the channel) and the shape of the depletion region varies accordingly. The drain-
source current is, therefore, a function of three voltages: drain, gate and source.
VD Drain
Source Gate Drain
IDS
Gate
VG
Source
VS
P-type substrate
Fig. 2.1.1 A basic model for the JFET (N-type)
In most applications the PN junction is reverse biased and the current flowing in or out of the gate is negligible (a
few pA at ambient temperature). The current flowing “down the drain” is almost exactly the same as that flowing
“from the source” (hence the silly names).
JFETs have two modes of operation: voltage controlled resistor (VCR) and “pinched-off” mode, depending on the
channel-gate voltage distribution. The latter is most frequently employed in amplifiers as voltage gain is
maximised. With a low channel-gate voltage the conduction channel behaves like a resistor. As the channel-gate
voltage increases, however, the conduction channel becomes very thin, the voltage-current relationship becomes
non-linear and, at sufficiently high voltage, the channel is pinched off and the JFET behaves like a (gate controlled)
constant current source. The channel connection labelled drain is invariably chosen to be the most positive and it is
the drain end of the channel that is pinched off. The current is deemed positive when flowing from drain to source.
Fig. 1.1 Drain-source current (mA) versus drain-source voltage (U430)
It is remarkable that such a complex system can be described, reasonably accurately, with a fairly simple theory,
based on a few plausible assumptions….
1
2. The theory
2.1 Basic theory of the PN junction
N-type silicon is pure crystalline silicon which is doped with a tiny proportion of impurity atoms which, in terms of
potential energy, have one electron too many. These electrons prefer to wander free between the silicon atoms –
able to conduct electricity. The impurity atoms become positively charged but the overall charge imbalance in each
small region is still zero (except at the junction). P-type material is the opposite – the impurity atoms are hungry for
an extra electron. Both types of doped silicon are fairly good electrical conductors.
At a PN junction electrons desert their N-type impurity atoms and stick to neighbouring P-type impurity atoms
creating a charge imbalance – just like in a charged capacitor. Energy equilibrium is reached when the electric field
created by the charge imbalance counteracts the effect by attracting electrons back to the N-type material. The
result is a thin layer either side of the junction where the electrons are strongly bonded and are no longer free to
conduct electrical current. If the P-type anode is made more negative than the N-type cathode the energy balance
shifts and the depletion region grows thicker. The charge increases and the junction behaves like a (voltage
dependent) capacitor [1]. If the anode is made more positive electrons are attracted away from the depletion region
but are quickly replaced by more electrons from the N-type side of the junction resulting in a current flowing.
Anode Depletion region
P-type
Junction
N-type
Cathode
Fig. 2.1.1 The PN junction and depleted region either side (not to scale)
If the drain and source are connected together (cathode) a JFET acts like a high quality diode with very low reverse
bias leakage and accurate conformity to the theoretical (thermodynamic) formula for a diode: -
IB  V  
VBE  VT ln or I B  I S exp  BE   1
IS   VT  
I S  A small current depending on the doping level of the silicon.

k  1.38  1023 J K is Boltzmann’s constant.
T  Absolute temperature (approximately 293K at 20 ºC )
e  1.6  1019 C is the quantum of electrical charge (e.g. on a proton)
kT
VT   25mV (at 20ºC) is a voltage corresponding to the thermal energy of the electrons.
e
1. JFET diodes perform well as voltage controlled capacitors (varactor) in certain applications.
2
Part 5: Monograph 4
2.2 The model
I shall assume that the N-type strip is uniformly rectangular and uniformly doped. In practice, for low noise JFETs
(low resistance), the strip is much longer than it is thick and much wider than it is long. In the following diagram
the vertical scale is much exaggerated: -
Gate Depletion region

VD ≈ VS = VG = 0V
IDS
Source h(x) Drain
dx
x Conduction channel
Fig.2.2.1 Simplified schematic of the conduction channel in low resistance mode
The boundary between the conducting channel and the depletion region is fuzzy. There is a gradual transition from
conductor to insulator and the dimensions of the conduction channel are not precisely defined. Similarly, the
connections at each end alter the effective length. Fortunately this fuzziness does not prevent one from assuming a
simple geometry, with effective dimensions, as the following analysis demonstrates: -
Define: -
W  Effective width of the channel (constant)
L  Length of the channel (constant)
hx   Effective thickness of the channel at position x (variable, depending on the channel-gate voltage)
With: W  L  hx 
x  Distance from the source end

  y, z   Free charge density
For N-type JFETs the free charges are electrons and the free charge density is numerically negative. The free
charge density is uniform throughout the channel except at the boundary with the depletion region where it
gradually drops to zero. It is also a function of temperature as the free electrons are a result of thermal equilibrium.
Any electrons added to the channel are quickly absorbed as equilibrium is restored (and vice versa). From
definitions and basic principles: -
The current density in the channel is: J   v   E (Ohm’s law)
Where:   Conductivity of the channel (numerically positive, by convention).


The conductivity and free charge density are related by the electron mobility:      

The electron mobility is, therefore, numerically negative.
Usually, the drain is more positive than the source and the free electrons flow from source to drain. The current, by
convention, is positive in the opposite direction.
3
I shall assume that the only non-zero components of the vectors are the x components. This seems reasonable from
the simple geometry. Similarly, the free charge density is independent of x. The current density is, therefore: -
dV x 
J x    y, z  with V(x) = potential in the channel and dV  V x  dx   V x 
dx
The current passing through any plane (perpendicular to the channel) must be the same (independent of x)
otherwise there would be a build up of charge in the channel. The Coulomb force is so strong that any charge
imbalance, apart from that maintained by the potential gradient in the channel, would be dispersed rapidly, at least
on the timescale of a low frequency model. The current density and, therefore, the potential gradient must vary
down the channel.
dV x 
In general, through the plane at position x: I DS   J x x, y, z dydz     y, z  dydz
dx
The channel potential gradient is a function of x but independent of y and z and so one can take it outside the
integral. The double integral yields the free charge per unit length, which is also a function of x: -
dV x  dV x  dQx 
I DS      y, z dydz  
dx dx dx
dQx 
L D
Multiply both sides by dx and integrate from source to drain: I
0
DS dx  I DS L   
S
dx
dV
The limits of the integration are from the lower to the higher voltage (usually source to drain) so that the current is
positive when flowing in the direction of drain to source.
Note also, by definition: dV  V x  dx   V x   dVCG  dV
Where dVCG is the channel-gate voltage, which is important for the following: -
The last integral is not simple as dQ dx depends on the potential in the channel. As the voltage in the channel
increases, relative to the gate, more electrons are taken from the depletion region leaving more positively charged
atoms. The electrons exit the channel via the (usually) more positive drain electrode. In general one can model the
junction as an infinite array of infinitesimal capacitors with a common connection to the gate and with the
same voltage profile as the channel. The channel becomes thinner but the free charge density remains the same
(thermal equilibrium) and the total charge available for conduction reduces (becomes less negative). Each
infinitesimal capacitance is also a function of the channel-gate voltage so that the change in free charge per unit
length for each capacitor is: -
dQ Q0 dC VCG 
  VCG
dx L dx
Where Q0 = total free charge when VCG  0V all along the channel (i.e. a constant for a given device at a given
temperature): -
 D dC 
 I DS 
L 2  Q
S
0  LV dV
dx 
The integral of the first term is simple but the second is less obvious. The dummy variable, V, refers to the channel-
gate voltage. The general expression for drain-source current is, therefore: -
 D
dC 
I DS  2  0 DS
L 
Q V  L 
S
V dV 
dx 
4
Part 5: Monograph 4
2.3 Drain-source on resistance
One of the most useful parameters is the drain-source on resistance, measured at very low current (typically 100μA
or 1mA with VDS < 100mV). This is easily and quickly measured and correlates closely with other parameters – it is
especially useful for selecting matching pairs from a number of single devices. The usual method for calculating
resistance is based on the length, cross-sectional area and conductivity of the conductor. The subscript 0 indicates
the effective value of the parameter under the test conditions: -
VDS L
In the limit: VD  VS  VG  0V R0  
I DS Wh0
Unfortunately  and h0 are not easy to calculate or analyse but, fortunately, one has the capacitor hypothesis. From
above, repeated for convenience: -
 D
dC 
I DS  2  0 DS
L 
Q V  L 
S
V dV 
dx 
In the limit VD  VS  VG  0V the integral is zero: -

Q0 VDS L2
VCG  0  I DS  VDS  R0  
L2 I DS Q0
In practice the resistance remains constant (the plot of current versus drain voltage is approximately linear) for a
drain-source voltage of up to 1V (see fig. 2.3.1 for the case VGS = 0V).
Fig. 2.3.1 Drain-source on resistance (top plot, Siliconix U430)
N.B. For an N-type JFET both Q0 and  are numerically negative so that the conductivity and resistance are always
numerically positive.
5
2.4 Voltage controlled resistor mode
If the voltage on the gate is reduced, with drain and source held at about 0V, the thickness of the channel reduces
but remains approximately uniform for the full length. The resistance increases and one has a voltage controlled
resistor (VCR): -
 RVSG  
L
VD  VS  0V and VG  0V
WhVSG 
Once again I shall employ the capacitance hypothesis. From above, repeated for convenience: -
 D
dC 
I DS  2  0 DS
L 
Q V  L 
S
V dV 
dx 
The channel-gate voltage is approximately constant down the channel and the capacitance, as well as charge, is
distributed uniformly. dC dx is constant and equal to the average capacitance per unit length CJ L  : -
D D
dC dC
 L V
dx S
VD  VS  0V and VG  0V dV  LVSG dV  VSGCJVDS
S
dx
CJ is the capacitance of the junction at the specified channel-gate operating voltage. Obviously one could replace
VSG with VDG as they are assumed to be the same. The current is, therefore: -

I DS  Q0  VSGCJ VDS
L2
As the channel-gate voltage increases all the free electrons are removed and the current falls to zero. This happens
at the “pinched-off” voltage, VP. A reasonable model is, therefore: -
Q0  VSG 
and CP  CJ VP 
Q
I DS  
2 
1  VDS with VP  0
L  VP  CP
VDS  VP  L2
The resistance is, therefore: RDS     R0 with R0 
I DS  VP  VSG  Q0
It is usual to specify the gate voltage relative to the source: -
 VP 
VSG  VGS  RDS    R0
 VP  VGS 
As VGS reduces to the (numerically negative) value of VP the resistance increases to infinity. In practice there is not
a sharp cut-off as the channel tends to leak current until the gate voltage is substantially lower than the “pinch-off”
voltage (e.g. when used as an analogue switch). The resistance remains reasonably constant for a drain-source
voltage in the range ±1V, depending on the type of JFET. See fig. 2.3.1 for various values of VGS.
The equation for RDS is only approximate as the value of VP varies slightly with VGS.
The lowest resistance is obtained with the gate-channel voltage slightly positive (i.e. the PN junction is slightly
forward biased). Obviously there is a limit as the diode begins to conduct and a maximum of 200mV is typical.
A more in-depth analysis shows that the range of drain and source voltage can be extended….
6
Part 5: Monograph 4
2.5 The general case
As the current and drain voltage increases the drain-gate voltage approaches pinch-off and the dynamic resistance
dVDS dI DS  increases. The plot of current versus voltage becomes non-linear (see fig. 1.1).
Gate
VD > VS; VG<0V VDG ≈ -VP
Source IDS Drain
Fig. 2.5.1 The drain-gate voltage approaches pinch-off
 dC 
D
Generally, repeated for convenience: I DS  2Q0VDS  L  V dV 
L  S
dx 
In the general case the integral requires careful examination. One can employ integration by parts: -
A basic rule of differentiation is: d FG   FdG  GdF  FG   dGF   dFG

  dFG  FG   dGF
V2 dC dC V 2 dC V 2  dC 
In this case F 
2
and G 
dx
so that: V dx
dV 
2 dx
  d
2  dx 

The first term is significant as the voltage varies down the channel. The second, on the other hand, is a small
correction. The charge distribution and the thickness of the depletion region may vary significantly down the
channel but I shall assume that the capacitance gradient does not.
dC dC  dC 
 constant  L  CJ and d  0
dx dx  dx 
 2
VDG  VSG
2

To a good approximation, therefore: I DS  Q0VDS  CJ 
L2  2 
1  2
VDG  VSG
2
 L2
Alternatively: I DS   DS
V   with R 
R0  2VP 
0
Q0
This equation is only valid for a range of voltages which do not pinch off the channel completely – once the current
drops to zero it remains zero as the gate-channel voltage becomes more negative. A little more algebra reveals the
symmetrical form (drain and source are interchangeable): -
1  2
I DS   VP  VDG   VP  VSG  
2
2VP R0  
7
A little more algebra reveals an extended voltage controlled resistor mode: -
 VDG  VSG VDG  VSG   I DS 

1  VDG  VSG VDG  VSG 
 VSG VDS 
2 2
VDG 
R0  2VP 
VDS  VDG  VSG 

Also: VDG  VSG  VDS  I DS  1  
R0  2VP 
The conductance is, therefore: -
1 I 1  V  VSG 
  DS  1  DG 
RDS VDS R0  2VP 
1 1  VD  VS  2VG 
Also: VDG  VD  VG and VSG  VS  VG   1  
RDS R0  2VP 
In the last section it was assumed that VD  VS  0V so that VG  VGS and the resulting formula is approximately
the same. This is usually the case as the source is connected to 0V and the drain signal is kept small. Also, the
dependence on drain voltage can be reduced by adding a proportion of it to the control signal. The most frequently
cited variable attenuator circuit is, for example [1]: -
VIN VOUT
R
RG
VC RG
0V
Fig. 2.5.2 VCR linearisation
The formula for conductance simplifies: -
VD  VC 1 1  VC 
VG  VC  and VS  0V   1  
2 RDS R0  2VP 
The circuit works best when the gate resistors are much larger than the output resistance of the attenuator. A factor
of ten (at least) is advised [1]: -
RG  R || RDS MAX 
The general case also reveals an alternative approach. If the circuit is arranged so that drain and source voltages are
equal and opposite, relative to some reference level (typically local 0V), then the linear range is significantly
extended (doubled – both drain and source ends of the channel can approach pinch-off). For example: -
1 1  VG 
VD  VS  0V   1  
RDS R0  VP 
1. Siliconix Inc: “Small –Signal FET Data Book”. January 1986.

See section 7-75 “FETs as Voltage-Controlled Resistors”
8
Part 5: Monograph 4
2.6 Pinched-off mode
In most amplifier applications the drain-gate voltage is higher than that required for pinch-off. Part of the channel,
at the drain end, becomes very narrow but the current is not completely shut off. If it were the voltage drop down
that part of the channel would bring the channel-gate voltage down and the channel would expand. A stable
equilibrium is achieved and the result is high transconductance and quite a high drain resistance (low drain
conductance). The current is controlled almost entirely by the gate-source voltage and is largely independent of the
drain-source voltage. The JFET becomes a voltage controlled current source.
Gate
VDG > -VP
IDS
Source Drain
Fig. 2.6.1 Operation in pinched-off mode
1  2
I DS   VP  VDG   VP  VSG  
2
From the previous section:
2VP R0  
In voltage controlled resistor mode the active region is when VDG and VSG are both positive and each of the
components in brackets are negative (VP is negative). In pinched-off mode the contribution to the equation from the
drain-gate effect falls to zero and remains so as VDG increases. Remarkably, the contribution from the source-gate
element remains the same.
1  2
In pinched-off mode: VP  VDG  0  I DS   VP  VSG  
2VP R0  
The pinch-off voltage is numerically negative and the drain-source current is, therefore, positive. The result is a
square law characteristic with k and VP approximately constant: -
VP  VSG  0  I DS  k VSG  VP  VP  VSG  0  I DS  0

2
and
Take the square root for a linear equation: I DS   k VSG  VP 
Plots of measured data of I DS versus VSG have a negative slope (see fig. 2.6.2) and one must, therefore, take the
negative square root. Equally valid, preferred by some, is a form of the equation with gate-source voltage as the
chosen variable: -
VGS  VP  I DS  k VGS  VP  VGS  VP  I DS  0

2
and
In this form both VGS and VP are numerically negative but VGS  VP is numerically positive in the operating range.
9
A batch of ten J112 devices provided seven with very low noise and a couple of reasonably well matched pairs: -
Matched pair
Fig. 2.6.2 Linearised plot for a batch of J112 JFETs (IDS in mA)
The theoretical model has its limitations: -
I DS   k VSG  VP 1    with   1
The factor 1    represents a small correction. A measure of the accuracy of the theory is a plot of difference
between measured data and the best fit straight line. The error is clearly systematic and less than ±2% over quite a
wide range of current: -
Fig.2.6.3 Deviation from best fit linear model I DS  VSG
10
Part 5: Monograph 4
2
 V 
Most text books and application notes prefer the form: I DS  I DSS 1  GS 
 VP 
Both VGS and VP are numerically negative with the ratio typically varying from 0 to 1. IDSS is the drain-source
saturation current, obtained when the gate-source voltage is zero. Manufacturers often specify minimum and
maximum values for IDSS and VP despite the fact that they are notoriously variable, even for devices of the same
type. This is not particularly helpful to the designer. It is easy to relate, with a little algebra, the relationship
between parameters, resulting in some design rules of thumb: -
1  kVP L L2 Q0
k I DSS  kVP2  with R0   and VP 
2VP R0 2R0 Wh0 Q0 CJ VP 
For devices of a particular type the parameter k is the most consistent (see fig. 2.6.2). Even though the pinch-off
voltage varies by 300mV (potential offset of a pair) spreadsheet analysis shows that the slope is consistent to within
±2.5%. If the outlier is excluded the consistency of k is better than 0.5%.
The designer is primarily interested in the gain. This can be predicted accurately, given the operating current and
drain resistance. For a single JFET with drain resistance RD and drain output resistance RDO, the effective load
resistance is the two in parallel: -
RD RDO
RDE 
RD  RDO
The gain of a simple (common source) amplifier depends on the forward transconductance and effective load
resistance: -
dVD I
G   g FS RDE with g FS  DS
dVGS VGS
I DS
I DS  k VSG  VP    2k VSG  VP 
2
From above:
VGS
I DS
Also: VSG  VP   g FS  2 kIDS
k
In a typical design the effective load resistance is not much lower than the actual drain resistance which drops
approximately 5V of DC (operating with a +15V power supply): -
5
RDE  RD 
I DS
As a ball park estimate, therefore, the gain is: -
5 k
G  g FS RD  2 kIDS   10
I DS I DS
This is an interesting result: Higher voltage gain is obtained, in practice, at lower operating current – the
opposite of what one might expect. The higher drain resistance more than compensates for the lower
transconductance.
For the J112 matched pair (see fig. 2.6.2) the average value for k  7.85 mA V 2 and so the expected gain at 1mA
is approximately 28 (5kΩ drain resistance) and the forward transconductance is g FS  5.6 mA V .
11
2.7 Deviation from the model
In practice the measured capacitance (VDS = 0) appears to consist of three components: channel-gate, end electrodes
and the package interconnections. As the gate voltage becomes more negative the channel-gate capacitance falls to
zero quite quickly until the channel is completely shut off. The capacitance of the end electrodes then continues to
fall more slowly, also due to a growing depletion region. The package and external strays contribute a fixed
capacitance.
Fig. 2.7.1 Gate capacitance (pF) versus gate-channel voltage (Siliconix U430).
Clearly the hypothesis that the capacitance is uniformly distributed can only be an approximation, especially in
pinched-off mode. In early work on JFETs Shockley [1] derived formulae, cited by many others, for the thickness
of the conduction channel of the form: -
 V x  
hx   h01  CG 
 VP 
This leads, by integration, directly to the result: -
I DS 
1 
 DS
V 
1.5
2 VDG 
 VSG
1.5

R0 
 3 VP 

The model for operation in pinched-off mode needs modifying accordingly: -

 V 
I DS  I DSS 1  GS 
 VP 
Where  is between 1.5 and 2 depending on the type of device. In the case of the J112 type the best fit is obtained
with a value of  ≈2.
1. Shockley, W. “A unipolar field-effect transistor”. Proc. IRE, vol 40, pp 1365 – 1376, 1952.
12
Part 5: Monograph 4
For the best matched pair the best fit values for  were 2.008 and 1.971 based on the following model: -
I DS  k VSG  VP 

 log10 I DS  log10 k   log10 VSG  VP
The pinch-off voltage was calculated by extrapolation using the simple square law. The results were VP = -2.053V
and -2.060V respectively).
Note that VSG  VP is numerically negative in the operating region and the magnitude function is necessary.
Fig 2.7.2 Logarithmic fit to calculate the average slope   2
2.8 Design rules of thumb
a). Buy a batch of 10 low cost single devices (e.g. J112) and test for low noise. If at least 50% are good buy a batch
of 100 – statistically this should provide a good number of low noise matched pairs.
b). Test for low noise with a prototype pre-amp circuit [1]. If you do not have access to a spectrum analyser use an
audio amp with headphones and learn to recognise “white” noise versus “popcorn” noise. Reject devices with the
latter.
c). Use the on resistance check to select matched pairs - with an ordinary DMM (±0.1% accuracy should suffice).
Connect the gate to the source and measure the drain-source resistance.
d). Design for a fairly low operating current (compared to a similar BJT design) – usually in the range 0.1 – 1mA.
JFETs may have higher noise voltage, compared to the best BJTs, but….
1. Part 5, monograph 3: “Low noise JFET preamps”
13
3. JFET noise
3.1 The basic model
The basic noise model is an ideal (noise free) amplifier with a noise voltage source in series with the input and a
noise current source in parallel with the source impedance (usually a source resistance). The source resistance also
generates noise, VS, depending on resistance and temperature (Johnson noise): -
VS VN
RS IN
Fig. 3.1 Basic noise model for an amplifier
The noise current flows through the source impedance creating a third noise voltage source in series with VN. The
three sources are statistically independent and conform to a normal (Gaussian) probability distribution and so
combine as follows: -
VT  VS2  I N RS   VN2
2
The total noise voltage referred to the input is:
Where VS, VN, and IN represent the standard deviation (root mean square -RMS) of the probability distributions. VN
and IN are normally specified, in data sheets, in terms of spectral density (volts and amps per square root of
bandwidth in Hertz) and as a (graph) function of frequency (see fig. 3.2). Johnson noise, on the other hand, can be
easily calculated and the spectral density does not vary with frequency.
The random voltage, as measured across the resistor terminals (open circuit), and the random current that would
flow through a short circuit can be characterised with normal distributions with RMS values: -
4kTB
VS  4kTRS B and I S  so that PR  VR I R  4kTB
RS
Where: -
k  1.38  1023 J K = Boltzmann’s constant.
T  is the absolute temperature ( T  293K at 20ºC).
B  Bandwidth of the measuring instrument, usually a spectrum analyser and often specified as 1Hz.
PR  4kTB is the “noise power”. It does not refer to any actual flow of power but it is a useful concept.
For an ideal JFET, at low frequency, the main source of (unavoidable) noise is the Johnson noise generated in the
conduction channel, just as if it were a resistor. The voltage noise in the channel affects the width of the channel
and, therefore, the drain-source current. For this reason JFET voltage noise is often modelled as a noise current
source in the output circuit. This, however, translates in a complicated way, to an equivalent noise source in series
with the gate, depending on the mode of operation. The most frequently used mode is the pinched-off mode and the
voltage gain is sufficiently high for the gate series model (above) to be the most convenient. The only way to
reduce this source of noise is to cool the device.
JFETs have other sources of noise due to the method of manufacture. The most problematic is “1/f” noise, so called
as the spectral density increases inversely proportional to frequency. In some devices the lowest noise is only
achieved at operating frequencies above 100Hz or even 1kHz. Similarly a mechanism known as “popcorn” noise
can be a problem. The only practical solution is to splash the cash on tested/guaranteed devices or find a
manufacturer who consistently produces excellent low cost (untested) JFETs. The author has found the latter policy
quite realistic – typically 6 or 7 out of a pack of 10 JFETs perform well and the issue of DC matching is relatively
easy to solve.
14
Part 5: Monograph 4
Fig. 3.2 Typical voltage noise (J112)
The other main source of noise is primarily due to the gate leakage current. It is remarkable that the quantisation of
charge is directly responsible for this observable phenomenon. With a leakage current, IL, the average number of
electrons flowing through the gate in time, T, is: -
I LT
N
e
Where e  1.60  1019 C is the quantum of electrical charge (i.e. on a proton).
These are thermally generated electrons and the rate at which they pass through the gate is highly random.
According to a fundamental theory of probability the number can vary (RMS or one standard deviation) by N .
e N eI L
The RMS current is, therefore: IN  
T T
This is an average over a time T and a well known theory (Fourier transforms) equates this process of averaging to
an equivalent ideal filter with bandwidth 2B Hertz.
1
 2 B  I N  2eI L B
T
In practice data sheets usually provide noise performance in 1Hz of bandwidth (B = 1).
The leakage current depends mainly on temperature (approximately doubling every 11ºC) and the drain-gate
voltage, increasing rapidly when VDS > 10V. With good ventilation and a heat sink the self heating can be held to
less than 10ºC above ambient and a leakage current of less than 10pA is possible. The noise current is, therefore: -
I N  2  1.6  1019  1011  2 fA Hz
A typical JFET will have a noise voltage of about VN  5nV Hz and the noise resistance is: -
VN
RN   2.5M
IN
Also of interest is the noise power: PN  VN I N  1023 W Hz
PN
Plus the equivalent noise temperature: T  0.2 K
4k
15
It is interesting to compare these results with the best BJT performance. From the datasheet of a SSM2210 with a
collector current of 1mA at 25Hz: -
VN  1nV Hz and I N  1 pA Hz  RN  1k
The noise resistance is much lower – more suited to resistance bridge applications.
The noise power and equivalent temperature, however, are much higher: -
PN  1021W Hz and T  18K
Historically it has not been practicable (or necessary) to produce a suitable noise matching transformer for low
source resistance (e.g. 1Ω) to a JFET pre-amp. BJT pre-amps have been the first choice for resistance bridge
applications. It may be possible, however, and the reader is invited to contact the author if interested [1].
16
Part 5: Monograph 1
Null detectors – the basics

1. Introduction
According to Wikipedia (and Stig Ekelof [1]) the Wheatstone “bridge” was invented by Samuel Hunter Christie in
1833 but improved upon and popularised by Sir Charles Wheatstone ten years later. A simple version was still used
in the “A” level syllabus as recently as the 1970s: a length of uniform resistance wire alongside a metre rule with
copper connections and brass screw terminals mounted on a nice plank of wood. The null detector was a very
simple (and delicate) moving coil galvanometer. With it we were able to establish the relationship between the
length, cross sectional area, conductivity and resistance of various types of wire with approaching 0.1% accuracy.
The term “bridge” presumably refers to the way the galvanometer null detector bridges across the ratio arms: -
Unknown
resistor
D
Known
resistor
Reference
wire and scale
Fig. 1.1 A Wheatstone bridge
We were instructed to be careful when bridging the circuit and touch the reference wire gently with the knife-edge
null detecting probe so as not to dent it.
The terms “bridge” and “null detector” have stuck – the principle is the same, though modern instruments have
much more accurate dividers and more sensitive null detectors.
Whereas a simple moving coil galvanometer can be remarkably sensitive (μA

DC) they are also rather fragile. With polarity reversal, amplification and
filtering (first with thermionic and now semiconductor devices) the sensitivity
improved substantially (sub μV DC). With low frequency AC energising of the
bridge, at a frequency chosen to avoid local power supply interference and a
noise resistance matching transformer sensitivity can be sub 1nV, with only a
few seconds averaging time, even at room temperature.
In principle the linearity and gain of the null detector are unimportant – the main
purpose is to indicate 0V (or zero current) in the presence of noise and
interference. In practice, however, the out-of-balance signal can be useful to
provide feedback for a control system (e.g. for a high performance servo-
mechanism, based on a ratio-metric capacitive transducer and transformer bridge
[2 and 3]).
1. Stig Ekelof: “The Genesis of the Wheatstone Bridge” "Engineering Science and Education Journal",
volume 10, no 1, February 2001, pages 37–40.
2. Part 3, monograph 8: “A 16 bit binary differential capacitance bridge”
1
2. Low noise pre-amps
2.1 A basic pre-amp noise model
The noise performance and sensitivity of a null detector is determined mainly by the first stage – a low noise pre-
amp. Principle characteristics (in data sheets) are noise voltage and noise current. These give rise to the concepts of
noise power and noise resistance. The former should be as low as possible and the latter should be the same as the
magnitude of the source impedance. The main aim is for the noise contribution from the pre-amp to be small
compared to the noise from the source.
Ideal amp
VS VN
ZS IN
Fig. 2.1.1 A simple noise model
The symbols VS , VN , and I N represent the statistical parameter (RMS) of the random voltages and current in 1Hz
of bandwidth. For a refresher on noise theory see the appendix.
VN
The noise power and noise resistance are, respectively: PN  VN I N and RN 
IN
Ideally the noise resistance should be the same (within a factor of 3) as the magnitude of the source impedance: -
RN  Z S
Another useful parameter is the noise temperature – the temperature of the resistor that would produce the same
noise voltage and noise current: -
PN
TN 
4k
Where: k  1.38  1023 JK 1 is Boltzmann’s constant.
As well as matching source and noise resistance the noise temperature of the pre-amp should be lower than the
source resistance (e.g. a cryogenic resistance thermometer).
One of the easiest ways to optimise noise resistance is to employ a matched pair of bipolar junction transistors as
the first stage of the pre-amp and vary the operating (collector) current. The noise resistance can vary from about
1kΩ (IC = 1mA) to about 400kΩ (IC = 1μA) [1]. Typical values from the data sheet for a SSM2210 (at 25Hz) are: -
Current (μA) VN nV Hz  IN pA Hz  PN (W) RN (kΩ) TN (K)

-21
1 25 0.06 1.5×10 417 27
-21
10 8 0.3 2.4×10 27 43
-21
1000 1 1 1×10 1.0 18
Fig. 2.1.2 Typical noise characteristics of a SSM2210 (Analog Devices Corp)
A higher operating current is not recommended as self heating can be a problem.
1. Part 5, monograph 3: “Low noise BJT pre-amps
2
Part 5: Monograph 1
2.2 Amplifiers in parallel
For a lower source resistance a number of identical amplifiers can be connected in parallel [1]. The output voltages
are added together and divided by the number of amplifiers, N. The noise currents combine in parallel also
according to the RMS calculation. The resulting noise voltage is lower but the noise current is higher so that the
resulting noise resistance is reduced by a factor N: -
VT 
1
N
V12  V22  V32  ... 
1
V1 and IT  I1
2

 I 22  I 32  ...  N I1  RN 
VT

1 V1
IT N I1
N
This can be achieved with a number of low noise matched pair BJTs (or dual JFETs) in parallel, each with its own
constant current source. These replace a single matched “long tail pair” in a composite op-amp circuit. For practical
circuits see the relevant monographs [1 and 2].
……etc
Current
sources
Input
Fig. 2.2.1 Matched BJTs in parallel
2.3 Noise matching transformers
Connecting a large number of low noise pre-amps in parallel is not always practical. Some high temperature
thermometers, for example, have a resistance as low as 1Ω. This would require 1000 dual BJTs in parallel. A better
solution is to employ a noise matching transformer [3].
100Ω Size 10c SM100

core
700
10Ω
3000 VOUT
200
1Ω
Output to
VIN 100
pre-amp: RN = 1kΩ
Fig. 2.3.1 A single-stage noise matching transformer
The main disadvantage is the large number of turns on the secondary – not difficult but very tedious.

3
2.4 Charge amplifiers
With high source impedance (e.g. a capacitance bridge: typically 1MΩ) it is better to employ a junction field effect
(JFET) input stage. Remarkable results can be achieved with a low cost JFET input op-amp (e.g. LF356) though
best performance is achieved with a dual matched JFET pair as part of a composite op-amp. A typical application is
the charge amplifier in a capacitance bridge. It is shown elsewhere [1] that the contribution due to the noise current
of the op-amp and feedback resistor is usually relatively small and a suitable model is: -
RF
CF
CR
VV
VOUT
VR
CT LF356
VN
CG
0V
Fig. 2.4.1 A charge amplifier (outline schematic)
The symbol CG represents ground capacitance due to (coax) connecting cables, capacitance in the transducer and
input capacitance of the op-amp and should be kept to a minimum.
The action of feedback is to maintain the inverting input at local 0V (“virtual earth”) and, therefore, no current
flows through capacitance CG. The circuit is an inverting amplifier so that, over a wide range of frequency: -
VV CR  VRCT
VOUT  
CF
In a typical bridge application the ratio of voltage is adjusted for a null balance so that the ratio of capacitance is: -
CT V
 V
CR VR
CT represents a transducer capacitance and C R a reference capacitor, often incorporated into the transducer
The noise gain is that of a non-inverting amplifier (consider both inputs connected to 0V): -
CR  CT  CG
GN  1 
CF
For more detail, including noise analyses see the relevant monographs [2, 3, 4 and 5].
1. Part 5, monograph 3: “Low noise JFET pre-amps”. See section 2.

2. Part 1, monograph 3: “Rotary capacitive displacement transducers.
3. Part 1, monograph 4: “Linear capacitive displacement transducers”
4. Part 1, monograph 5: “Variable gap capacitive displacement transducers”
5. Part 5, monograph 4: “JFET theory”
4
Part 5: Monograph 1
3. AC gain and filtering
In low frequency applications a significant problem is low frequency (AC power supply related) interference. The
low noise pre-amp, including matching transformer, usually has a fairly wide bandwidth - interference is amplified
as well as the signal. A variable gain/filter stage allows the signal thorough but attenuates noise and interference
sufficiently to allow a total AC amplification of up to 106-107 before the AC-DC conversion stage. A typical design
for an operating frequency of 25 or 75Hz (local supply 50Hz) is as follows: -
BPF
50
BPF HPF Variable Variable
25/75 ≈16 Gain Gain
BPF
100
Control Control Control
BPF
150
Fig. 3.1 Variable gain and filtering (outline schematic for 25Hz and 75Hz operation)
The first band-pass filter, at the selected operating frequency, reduces high frequency noise and interference
sufficiently to allow further amplification. After the variable gain stage is a multi-frequency notch filter consisting
of band-pass filters (single op-amp - inverting) and a summing junction. The summing function can be combined
with a second variable gain stage (inverting amplifier with virtual earth).
Supply first harmonic (50Hz) can be a problem due to stray magnetic fields (from mains powered equipment), earth
loops or lack of adequate screening. The second harmonic (100Hz) comes from stray magnetic fields from poorly
designed power supplies. The pulses of current that charge the (large) smoothing capacitors immediately following
the full-wave rectifier occurs every half cycle and the poorly routed wiring radiates magnetic flux. The lowest
frequency component from this mechanism is 100Hz though all the higher harmonics are present. The third
harmonic also comes from power supplies – this time from the mains transformer. With insufficient turns and/or
iron a power transformer runs close to magnetic saturation. The result can be a remarkable amount of 150Hz
magnetic flux spewing out of the transformer.
Stray magnetic flux passes easily through steel structures, along bench framework and, by virtue of sod’s law,
through your most sensitive bit of wiring. Good wiring practice helps (twisted pairs or coax cables and avoiding
earth loops) but low frequency magnetic interference can be annoyingly difficult to diagnose [1].
Users of hearing aids (switched to loop operation) are frequent victims of magnetic interference due to poor wiring
practice [2].
If local power supply is 60Hz the frequencies change accordingly.
1. Many audio engineers are familiar with these problems: mains “hum”and other buzzing sounds. In
audio applications 100, 150Hz and higher harmonics are the most problematic - more audible than 50Hz.
2. Some years ago I was asked to investigate a mysterious “buzzing” that was bothering a number of
hearing aid users in a Methodist chapel (hearing aids switched to loop), especially under a balcony. A small
(3cm diameter with 50 turns) search coil, portable amplifier and headphones soon found the problem. The
live cables were routed down one side of the building, via a bank of switches, but a single neutral returned
along the other side. The other clues were that the problem got worse when they replaced incandescent
bulbs (resistive) with more efficient fluorescent types (100Hz audible pulses) and the balcony was held up
by an RSJ. They were very close to buying a new loop amplifier.
5
The overall effect reduces low frequency interference by at least an order of magnitude, even as the supply
frequency varies (typically ±0.2% but up to ±1% with a sudden surge or drop in demand). For further reduction the
whole amplifier/filter unit can be repeated two or three times.
Fig. 3.2 The frequency response of the HPF and notch filter combination
The quality factors of the notch filters are chosen to ensure zero phase shift at 75Hz but this leaves a phase shift at
25Hz. The high-pass filter cut-off frequency is chosen to correct for this. The high-pass filter is most conveniently
placed before the first (non-inverting, high input impedance) variable gain stage. A two-stage design is
recommended as it has a very small phase shift at 75Hz [1], simplifying the design process.
Fig. 3.3 Phase shift of the HPF and notch filter combination
In practice it is necessary for each BPF to have a variable resistor for adjusting frequency. For maximum rejection
it is also advisable for the summing junction resistors to be adjustable (see appendix 2 for details).
1. Part 2, monograph 1: “Two-stage filters”
6
Part 5: Monograph 1
Typical values for centre frequency and quality factor are easily found with a spreadsheet simulator with sliders: -
For zero phase shift at 75Hz: Q50Hz  5 Q100Hz  10 Q150Hz  10
The phase shift at 25Hz, mainly due to the 50Hz notch, is compensated by the high-pass filter. A further slider
control allows one to adjust the cut-off frequency so that the phase shift is zero at 25Hz with minimal effect at
75Hz.
The interaction between the notch BPFs also means that the centre frequency of each is not set precisely to the
target value.
Spreadsheet settings: f50Hz  49.48Hz f100Hz  100.05Hz f150Hz  151.45Hz
In practice one adjusts the variable resistors with suitable test signals. There is a small amount of interaction
between the settings so that the adjustments need to be repeated. Twice or three times should be sufficient.
The band-pass filters at the operating frequency are best with a lower quality factor: Q  2 is a good compromise
between selectivity and phase error due to frequency and temperature variations (mainly affecting the capacitor
values – use low drift polyester types). Whereas the total phase error of the amplifier/filter sections is not critical a
lower value ( ± a few degrees is tolerable) means less interaction between the in-phase and quadrature null-balance
servos. Both components eventually reduce to zero.
Calculating practical component values can be made easier with a spreadsheet. Given the frequency and quality
factor try a variety of values for R2 in order to find a practical value for the capacitors. The resistance R1B needs to
be a fixed resistor plus a variable.
Freq (Hz) Q R2 (kΩ) R1A (kΩ) R1 (Ω) R1B (Ω) C1=C2 (nF)
25 2.083 39 20 2247 2540 680
50 5 200 100 2000 2041 159
75 2.022 39 20 2385 2717 220
100 10 200 100 500 503 159
150 10 200 100 500 503 106
Fig. 3.4 Practical component values
Fig. 3.5 Notch filters and band-pass filter (75Hz and Q = 2) combination
7
4. Synchronous rectifiers
4.1 The quad FET switch
After the amplifier/filter stages the AC signal is converted to DC. This can be achieved in a number of ways – the
simplest being a quad FET switch driven with logic signals derived from the AC reference voltage. The circuit is a
double-balanced bridge structure with a differential input and output – effectively multiplying the signal by ±1: -
Input (+)
notQ
Q
Output
notQ
Q
Input (-)
Fig. 4.1.1 The Quad FET switch synchronous rectifier (voltage mode)
If the input signal (and its inverse) is in-phase with the logic signals the result is a full-wave rectified signal (and its
inverse) at the output. If the input signal is in quadrature the average output is zero. This gives rise to the alternative
name: “phase sensitive detector” (PSD).
The double-balanced structure has the advantage that the charge injected from the logic signals through the FET
switch gate capacitances is the same on both sides. The effect is eliminated by the following differential
amplifier/low-pass filter stage. Switch (on) resistances are low and reasonably well matched so that the effect of
input resistance of the following stage can be made negligible. Some designers prefer the current mode – as part of
an inverting amplifier configuration. The main advantage is that the FET switches operate at 0V (both sides) and
the variation of resistance (with common mode voltage) is eliminated. It is also possible to use low cost CD4066
type quad FET switches with a separate ±7.5V power supply, produced locally with a pair of zener diodes: -
R
notQ R
Q
Output
notQ
Q 0V
R
Fig. 4.1.2 The Quad FET switch synchronous rectifier (current mode)
This type of synchronous rectifier works well up to an operating frequency of 100kHz. Higher frequency (e.g. for a
very high speed capacitance transducer interface) is possible with an RF type MOSFET “double balanced mixer” or
“Gilbert cell multiplier” approach (sinewave drive).
8
Part 5: Monograph 1
4.2 Rejection of Noise and Interference
A square wave, with amplitude ±1 and frequency, C , can be expressed as an infinite series of sine waves (a
Fourier series). Only the odd harmonics are present (hence the sum includes only cases of k = 1, 3, 5, 7 etc). The
amplitude of each harmonic reduces - inversely proportional to frequency.

sin kC t 
4
VSQUAREWAVE  
oddkk
If one assumes that the incoming signal has amplitude VS and is at a frequency, ω with a phase (at t = 0) of θ the
output of the quad FET switch is: -

VOUT  2VS sin t    sin kC t 
4
oddkk
The extra factor of two is due to the differential structure of the synchronous rectifier (voltage mode, see fig. 4.1.1).
One can multiply each item on the right of Σ by sin(ωt + θ) then do the summation: -

sin t   sin kC t 
4
VOUT  2VS 
oddkk
The result is sum and difference frequencies: -

VOUT 
4
VS 
1
coskC   t     coskC   t   
 oddk k
A low pass filter, after the synchronous rectifier, is used to reduce the AC components and pass the DC component,
corresponding to zero frequency: -
  kC   is an odd multiple of C
The synchronous rectifier only produces a DC output for odd harmonics of the carrier.
The effect of odd harmonics in the original carrier waveform is usually negligible, especially at “null balance”.
For a pure carrier signal (k = 1 is the only component) the average (DC) output of the synchronous rectifier is: -
  C  VOUT  VS cos  (voltage mode)

4

If the signal is in-phase with the reference square wave   0 the output is simply proportional to the input. If the
signal is in quadrature   90 deg  the average (DC) output is zero. Two synchronous rectifiers, operated at 90
degrees relative to each other, provide DC outputs proportional to the cosine and sine components (real and
imaginary) respectively. With a current mode synchronous rectifier (or similar) the average (DC) output is reduced
by a factor of two (factor 2  ).
4.3 Output ripple
The AC components at the output are often called “ripple”. The mid-higher frequency components are easily
reduced by a low-pass filter after the rectifier (see next section) but the lower frequency components can be a
problem. The most significant low frequency AC components are the second harmonic of the operating frequency
(full wave rectified signal) and the difference between the operating frequency and the interference components.
9
Ripple components: -
 25Hz operation rectified (2nd harmonic): C    50Hz
 25Hz operation with 50Hz interference: C    50Hz and 3C    25Hz
 75Hz operation rectified (2nd harmonic): C    150Hz (no problem for the low-pass filter)
 75Hz operation with 50Hz interference: C    25Hz
 75Hz operation with 100Hz interference: C    25Hz
 75Hz operation with 150Hz interference: C    75Hz (no problem for the low-pass filter)
Higher frequency components of interference are attenuated sufficiently by the band-pass filters before the
synchronous rectifier. Clearly the main problem is the 25Hz ripple component.
+1 -1 +1 -1 +1 -1 +1 -1 +1
75Hz
50Hz
100Hz
150Hz
Fig. 4.2.1 Output ripple for 50Hz, 100Hz and 150Hz supply interference
(75Hz operating frequency)
10
Part 5: Monograph 1
5. Low-pass filters
5.1 A combined low-pass/notch filter
When operating at low frequency (25Hz and 75Hz) the main problem is the 25Hz AC component. The solution is
quite simple – a combined low-pass and notch filter: A simple band-pass filter (inverting) provides a second input
to a conventional second order low-pass filter: -
R1B R3
V1B
BPF
V2 C2
V1A R1A R2
VIN
VOUT
C1
0V 0V
Fig. 5.1.1 A combined low-pass and notch filter.
It is shown in appendix 3 that the output of the filter is, in normalised form s  j N  : -
 R R  1 
VOUT  V1 A 3  V1B 3  
2 
 R1 A R1B  1  2s  s 
The natural frequency and damping ratio are: -
1 1 R2C2  R3 R R 
fN  and     3  3 
2 R3 R2C2C1 2 R3C1  R1 A R1B R2 
A typical bandwidth is 10Hz (critically damped) which provides sufficient smoothing for fast balance operation.
Lower bandwidths can then be implemented by sampling the output with a 12-bit ADC plus microcontroller and
employing digital filtering. A modest sampling rate of 50Hz is practicable and should be more than sufficient.
If an analogue (moving coil) meter balance indicator is required a suitable bandwidth is 0.2Hz (critically damped).
In both cases the band-pass filter (see below) has a maximum gain of 0.5 hence R1B  0.5R1 A
Practical values for the components are: -
R1A (kΩ) R1B (kΩ) R2 (kΩ) R3 (kΩ) C1 (nF) C2 (nF) Freq (Hz) DR
150 75 39 160 398 100 10 0.90

540 270 180 24200 4400 33 0.20 1.00
Fig. 5.1.3 Practical values for low pass filters.
11
A very basic band-pass filter is a practical option: -
VIN R
VOUT
C
0V 0V
Fig. 5.1.2 A basic band-pass filter
It is shown in appendix 3 that the transfer function is, in the complex representation s  j  : -
VOUT  sRC

VIN 1  2sRC  s 2 R 2C 2
The natural frequency and damping ratio are: -

1
fN  and   1
2RC
The maximum gain, at the natural frequency, is 0.5
Practical component values are C  470nF and R  13.5k (An 8k2 fixed resistor plus a 10k variable).
The combination provides a significant attenuation to the 25Hz difference component – at least -40dB even when
the power supply varies by ±1%.
Fig. 5.1.4 Frequency response of a 10Hz low-pass plus 25Hz notch filter
12
Part 5: Monograph 1
5.2 A bridge as part of a control system
It is often the case that a null-balance bridge or signal conditioner is used to interface a transducer as part of a
control system. Typical applications are high performance servo-mechanisms based on ratiometric variable
capacitance transducers. One example is a limited angle servo-mechanism used for the positioning of a mirror (e.g.
rapid scanning of a laser beam or microscope image) [1 and 2].
Fig. 5.2.1 A high accuracy servo system
The conventional approach is to employ a “signal conditioner”: a transducer interface that produces a DC output
proportional to position. The interface produces second harmonic ripple, even without interference. The low pass
filter reduces the ripple considerably but does not eliminate it completely.
Ripple attenuation versus phase shift, due to the filter, then becomes a major trade-off. Ripple can be reduced at the
expense of extra phase shift and vice versa. A small phase shift can be tolerated (e.g. 5 degrees maximum) as part
of an overall phase shift budget for the main control loop stability. AC ripple, on the other hand, is amplified by the
loop compensation, especially if it includes a derivative term (e.g. PID control with high frequency boost to
compensate for inertia), resulting in overload.
The temptation is to opt for a high operating frequency but this can compromise accuracy [3].
The solution is to employ the bridge as part of the control loop: The set-point (“demand”) signal sets the
bridge ratio and the actuator drives the transducer (mechanically) to achieve null balance. Zero output
voltage means zero ripple!
For advice or more detail please contact the author.

2. Part 3, monograph 8: “A 16 bit binary differential capacitance bridge
3. In one version (frame scanning for a thermal imager) the carrier frequency was 2MHz so that the low-
pass filter bandwidth could be as high as 10kHz.
13
6. The quadrature servo
6.1 In-phase and quadrature
The issue of quadrature usually arises when measuring the ratio of resistors with either parallel cable capacitance
or, in the case of very low resistance values, series inductance. For more detail see the monograph “High accuracy
resistors” [1]. Quadrature is much less of a problem with capacitance bridges (except with very long connecting
cables) [2].
In-phase and quadrature are defined relative to master phase references: usually the logic signals used to drive the
synchronous rectifiers. To generate 75Hz, for example, a phase-lock loop is used to track the (nominally) 50Hz
supply with a divider in feedback followed by three T-type flip-flops (e.g. based on JK flip-flops, type CD4027).
The Q and notQ output timings can be accurate to a few nano-seconds thanks to the accurate matching of gate
characteristics on the same chip: -
6 150Hz
2 In-phase
50Hz PLL 2 75Hz
2 Quadrature
300Hz
Fig. 6.1.1 The master phase reference (75Hz)
Phase locking the operating (“carrier”) frequency to a precise multiple of the supply frequency affords maximum
rejection of interference.
The in-phase logic signals can then be used to produce the (nominally) in-phase sinewave carrier with two second
order low-pass filters, each operated at the corner frequency with a total phase shift of approximately 180deg. The
higher harmonics are reduced sufficiently for the purpose and phase accuracy is not particularly important.
A typical application is a resistance bridge with a three-stage ratio transformer. A quadrature imbalance is caused
mainly by cable capacitance plus a very small phase error due to the ratio transformer [3]: -
CS VQ
RS VS
VD D
I
0V
RT VT
CT
Fig. 6.1.2 A typical resistance bridge structure
1. Part 1, monograph 1: “High accuracy resistors”. See section 3.

2. Part 3, monograph 2: “Single stage inductors and transformers”. See section 4.5 and example
calculation 4.5.1
3. Part 3, monograph 4: “Three-stage RTs”. See example calculation section 2.3.
14
Part 5: Monograph 1
The transformer ratio is adjusted and the quadrature servo adds a signal, VQ , to the output of the bridge so that a
null is achieved for both in-phase and quadrature components: -
VD  aVS  VT  VQ  0
NS
a is the transformer ratio setting. The phase error of a ratio transformer is usually much smaller than that due
NP
to the parallel capacitance and is simply added to it – equivalent to a small change in capacitance. The second order
term (in-phase error) is negligible. I shall assume, therefore, that a is a real number.
R
A resistor in parallel with capacitance has impedance: Z
1  jRC
Define parameters:  S  C RS CS and T  C RT CT . Both are small (typically <0.1mrad or 100ppm)
Note that for small angles, to a good approximation (in radians): tan   
IRT aIRS
The ideal quadrature servo needs to add a signal: VQ  VT  aVS  
1  jT 1  j S
One can separate this into its real and imaginary parts: -
IRT aIRS  aIRS IRT 

VQ    j    
2 T 
1  T 1   S
2 2
 1  S
2 S
1  T 
Both contributions to the imaginary component are small and the effect of the denominators is negligible.
T  IRTT etc.  ImVQ   j aIRS S  IRTT 

IRT
1  T2
Similarly, at or approaching null balance, the real part is also small so that: IRT  aIRS
One possibility is, therefore, for the quadrature servo to inject a signal: VQ  jaIRS  S  T 
This signal is, as expected, proportional to the magnitude of the current and the phase difference. It is also precisely
in quadrature relative to the current but that is not easy to do in practice.
A more practical option is to derive a signal from the reference voltage, VS: -
VQ  jbVS  VD  a  jb VS  VT
VT
At null balance (in-phase and quadrature): VD  0   a  jb
VS
IRT IRS R 1  j S
Now: VT  and VS   a  jb  T 
1  j T 1  j S RS 1  jT
With a little algebra: -
RT  1   ST  R   
 a   and b  T  S 2T 
 1  T RS  1  T
2
RS  
15
For the very highest accuracy it is possible to add capacitance or, better still, matching cable to one side or the other
so that the remaining quadrature imbalance is small. To a very good approximation, therefore: -
and b  T  S  T 
RT R
 S  T and  S  1 and T  1  a 
RS RS
b
The phase difference is:   S  T
a
Matching cable is the better choice because any loss factor (“tan(δ)”) of the cable dielectric, equivalent to a small
imaginary component for both  S and T , is the same for both numerator and denominator and cancels (in the
formula for the real component, a).
 S  T and  S   S 1  j  and T  T 1  j   a 
RT
RS
Similarly, if the signal injected has a small phase error, equivalent to a small imaginary component,  Q , of the
parameter b, the result is a very small in-phase error: -
a
b  b1  jQ   a  jb  a  bQ  jb   T   S Q
a
RS  25 with 1 metre of cable CS  200 pF  ; RT  100 at the end of 5 metres of cable CT  1nF  with an
operating frequency of 75Hz (   2f  471 radians per second).
RT
 S  471 25  2  1010  2.4  106 T  471 100  109  4.7  105 and a  4
RS
a 1   ST
The in-phase error is:   2.2  10 9 (2.2ppb and negligible)
a 1  T2
The quadrature imbalance is:  S  T  4.5  105 (45ppm)
The parameter b is: b

RT
 S  T   1.8  10 4 (180ppm)
RS
With an operating current of 1mA (RMS) the reference voltage is 25mV (RMS) and the magnitude of the injected
signal is: -
VQ  jbVS  4.5V (RMS)
If the injected signal has a phase error of Q  104 (0.1mrad) the in-phase error is: -
a
  S  T Q  4.5  109 (4.5ppb)
a
The method based on VQ  jbVS is sufficiently accurate.
16
Part 5: Monograph 1
6.2 A practical quadrature servo
One practical approach is based on an analogue multiplier and integrator in a negative feedback loop.
VD G1 Quad PSD Quad phase

Ref.
Integrator
Differentiator
LF
VS VREF V1 R
G2 Multiplier VQ
In-phase V2
(approx.) 0V
Fig. 6.2.1 A typical quadrature servo
The DC output of the integrator, together with the AC reference voltage (substantially in-phase), derived from the
bridge reference resistor, are put to an analogue multiplier (four quadrant e.g. Analog Devices AD534). The
reference voltage is amplified to a suitable level (maximum typically 20VPK-PK) with a high accuracy differential
amplifier (gain G2) [1: section 5]. A bridge with a pair of high accuracy voltage followers provides a convenient
low impedance source for the reference voltage VS [2].
The AC output (substantially in-phase) of the multiplier then undergoes a phase shift of precisely 90 degrees with a
high accuracy differentiator based on a low phase error ferrite pot core transformer [1: section 6]. The transformer
secondary is isolated so that the signal is easily added in series with the output of the ratio transformer (see fig.
6.1.2).
The synchronous rectifier/integrator functions are easily combined into a current mode circuit with a feedback
capacitor, rather than a resistor: -
R
notQ C
Q
Output
notQ
Q 0V
R
Fig. 6.2.2 A combined synchronous rectifier/integrator
Clearly it would be an advantage if the amplifier/filter stages (represented by G1) used for the in-phase null balance
could also be used by the quadrature servo. With a suitable integrator time constant, gain G2 and
transformer/mutual inductance this proves to be possible (see below).

2. Part 4, monograph 2: “High accuracy voltage followers”. See section 1.
17
The overall effect of the feedback is to drive the quadrature component to zero. The output of the differentiator
circuit is [1]: -
C LM
VQ  j V2
R
LM is the mutual inductance of the transformer, C is the operating frequency and V2 R is the current through the
transformer primary. VQ is limited by the maximum output of the multiplier (typically: V2 = ±10VPK), the maximum
current through the ferrite transformer primary (typically ±1mAPK with R = 10kΩ) and the mutual inductance. A
suitable transformer has 16 turns for both primary and secondary (see section 6.4) on an RM10 pot core so that the
mutual inductance is [1]: -
AL  400 nH turn2  LM  N S N P AL  100H

The maximum output at an operating frequency of 75Hz C  471rads1 is:- 
V2  10VPK and R  10k  VQ  47 VPK
MAX
LF
V V
The output of the multiplier is, typically: V2  REF 1 with VREF  G2VS
10V
The maximum is only achieved when the VREF input to the multiplier is ±10VPK and the gain of the differential
LF
amplifier, G2, is set accordingly. The symbol V1 represents the DC output of the integrator (maximum also ±10V).
The denominator factor 10V (ten Volts) is typical for a four quadrant analog multiplier. The symbol V (volts) is
retained as a reminder that the equations must be dimensionally correct. The actual range of the servo depends on
the gain of the differential amplifier and the differentiator as the following demonstrates: -
 aIRS 1  j S   IRT 1  jT 

aIRS IRT
The bridge output (see fig. 6.1.2) is: aVS  VT  
1  j S 1  jT
RT
When the in-phase (real) component is set to null: a
RS
The remaining imaginary component is, to a good approximation: ImaVS  VT   IRT T   S 
LF C LM C LM
With V1  10V the maximum output of the servo is: VQ  VREF  G2VS
MAX R R
This is equal to but opposite the maximum quadrature output of the bridge: VQ  IRT  S  T MAX
MAX
C LM
VS  IRS  VQ  G2 IRS  IRT  S  T MAX
MAX R
This corresponds to a maximum value for the parameter b: bMAX 

RT
 S  T MAX  C LM G2
RS R
18
Part 5: Monograph 1
6.3 The servo as a control loop
The quadrature servo can be thought of as a continuous negative feedback control system. The input is the bridge
output: -
VS G2
VREF
VIN = aVS - VT LF
VD G1 V1 V2 jLM/R
Is
VQ
Fig. 6.3.1 The quadrature servo feedback loop
The ferrite transformer secondary is added in series with the bridge output so that the signal presented to the
amplifier filter stages is: -
VD  VIN  VQ
The quadrature servo injects a voltage proportional to the reference signal VS (the voltage developed across the
reference resistor) and phase shifted by precisely 90 degrees: -
VIN  aVS  VT and VQ  jbVS  VD  a  jb VS  VT
The null balance state (parameters a and b), for both in-phase and quadrature, is independent of the reference
voltage and, therefore, the operating current. The balance remains stable as the operating current varies (randomly
or due to temperature variations).
The quadrature servo main gain block consists of an amplifier, filter, synchronous rectifier and integrator,
producing a slowly varying “DC” output proportional to the integral of the imaginary component. One can describe
this with the usual complex representation of an integrator s  jLF  : -
ImVIN  VQ 
LF
G1
V1 
Is
LF is the frequency of the slowly varying input signal VIN  aVS  VT  and G1 is the overall gain factor,
LF
including the synchronous rectifier. The symbol V1 represents the low frequency complex representation. The
symbols VQ etc remain the complex representation of the AC signals at the operating frequency C .
LF
G V V
The output of the multiplier is: V2  2 S 1
10V
C LM
The differentiator provides the accurate (90 deg) phase shift: VQ  j V2
R
19
The injected signal is now substantially quadrature: V2 has a small quadrature component and the transformer
introduces a very small phase error, equivalent to an imaginary component of LM. I shall represent the small error
with a factor (1   ) : -
C LM
ImVQ (1   )  V2 with   1 (  is a small and possibly complex number)
R
Combine the equations above to reveal in the (low frequency) complex representation s  jLF  : -
C LM G2VS G1
ImVQ 1     ImVIN   ImVQ 
R 10V  I s
The various gain factors and integrator characteristic represent a high gain block [1]: -
C LM G2VS G1
ImVQ 1      H s ImVIN   ImVQ  with H s   
R 10V  I s
The sign convention is chosen to be consistent with the usual definition of the open loop characteristic of a high
gain block (from the non-inverting input to the output) [1]. With a little algebra: -
 1  
ImVQ 1     ImVIN 
 H s  
At very low frequency the magnitude of the high gain block is very large and the term  H s  is truly negligible.
One can deduce the transfer function, to a very good approximation: -
 ImVQ   H s  1
 1  T s  
R 10V 1
  with  Q  
H s  ImVIN  1  H s  1   Q s C LM G2VS G1 I
The interpretation is simple: The response is that of an inverter (gain = -1) with a first order low pass characteristic.
At very low frequency, to a good approximation: -
 QLF  1  H s   1  ImVQ    ImVIN   ImVD   0
Given a step-change in quadrature the servo approaches balance with the usual exponential decay to zero (null
balance): -
 t 
ImVD   ImVD t  0exp   
  
 Q
 
Five time constants t  5 Q is usually regarded as sufficent settling time and, very approximately, a time constant
of 1second is a reasonable design target.
20
Part 5: Monograph 1
6.4 Interaction between the in-phase and quadrature balance
The in-phase balance algorithm is usually best implemented with a microcontroller or external computer. The most
appropriate algorithm depends on circumstances. Rapid balance from a large change (e.g. switching to a different
thermometer or resistor) usually involves initiating a sequence: set a low gain, measure the out-of-balance,
calculate and correct the transformer ratio accordingly and repeat with a progressively increasing gain until the
required resolution is achieved. Once null balance is achieved the algorithm can then switch to a tracking mode –
similar to a linear feedback system with a suitably fixed high gain setting and time constant.
If the main gain/filter stages are common to both in-phase and quadrature servo there is a high degree of
interaction. With a low gain setting, for example, the quadrature servo time constant is large and the servo is slow
to achieve balance. As the gain is increased the servo speeds up. Fortunately this is not a problem since an accurate
quadrature null balance is required only at the highest gain setting. With a suitable transformer, variable gain
differential amplifier stage (G2) and integrator time constant  I  a reasonably good compromise between servo
range and settling time can be achieved. The quadrature servo can be left to run continuously with only a small
effect on the in-phase null balance process. Similarly, small changes to the transformer ratio have negligible effect
on the quadrature null balance.
The time constant for the servo feedback loop is, from the previous section: -
R 10V 1
Q  
C LM G2VS G1 I
A reasonable target is of the order 1 second (5s settling time from a large change). The optimum design
considerations are as follows: -
1). The AC gain of the main amplifier/filter stages (G1) needs to be sufficiently large so that in-phase accuracy is
limited only by noise (typically  1nVRMS Hz referred to the input of the pre-amplifier). The DC error at the
input of the final stage synchronous rectifier/low-pass filter is typically <0.1mV hence the gain needs to be at least
105 (preferably 106) as long as the synchronous rectifier is not overloaded by interference. Two sets of variable
gain/filter stages are usually sufficient (see section 3) though it would be wise to monitor the residual signal level
and set the maximum gain accordingly. A reasonable assumption is, therefore, a maximum gain setting in tracking
mode: -
Maximum gain setting: G1  106
2). The gain of the differential amplifier, G2, needs to be variable to compensate for large variations in operating
current and reference resistor [1]. The gain is chosen so that the signal VREF  is optimum at the analogue
multiplier input (typically 2 -20VPK-PK). The choice of gain also affects the actual range of the quadrature servo
though that is not critical. A reasonable assumption is VREF  3VPK (give or take a factor of three up or down). It is
necessary, however, to measure the reference voltage VREF  , with a further synchronous rectifier/low-pass filter
and ADC channel, in order to determine the appropriate gain setting.
For practical values (approximately ×10, ×100 and ×1000) see section 6 [1]. It is debateable whether a fine gain
adjustment stage is necessary. Assume: -
VREF  G2VS  3VPK
3). Typical values for the differentiator are fC  25Hz or fC  75Hz [1: section 5]: -
C LM
C  157 or  471 LM  100H and R  10k   157  108 or  471 108
R
21
4). The optimum time constant of the integrator can now be calculated. From above: -
C LM G2VS
I  G1 Q  157  108  0.3  106  1s  0.47 s
R 10V
This is easily implemented with switched gain stages (typically ×1, ×10 or ×100) and a fine gain adjustment stage
based on a multiplying digital to analogue converter (12-bit should suffice).
Even though the gain of the shared amplifier/filter stages can vary over a wide range the quadrature servo
integrator time constant can be fixed.
The range of the quad servo can then be determined: -
bMAX 
RT
 S  T MAX  C LM G2
RS R
22
Part 5: Monograph 1
Appendix 1: Basic noise theory
A1.1. Johnson noise
In the early development of radio and thermionic devices Johnson [1] and Nyquist [2] (experimentally and
theoretically, respectively) realised that there is a fundamental relationship between the random voltage observed at
the terminals of a resistor, absolute temperature and bandwidth. The modern expression is: -
VN  4kTRB (Volts RMS)

Where: -
VN Is one standard deviation (the RMS value) of a very large number of instantaneous samples of voltage
measurement and is referred to as the “noise voltage”. The RMS value is also related to power.
k  1.38  1023 JK 1 is Boltzmann’s constant (relating random kinetic (thermal) energy and temperature).
T = Absolute temperature (Kelvin)
R = Resistance (Ohm’s)
B = Bandwidth (Hz) - of the (ideal) measuring instrument
Nyquist’s theory is based on classical concepts in statistical thermodynamics (i.e. not quantum) and transmission
line theory (see section 4 of this appendix). The “free” electrons in a conductor, with their highly random motion,
behave like a perfect monatomic gas in thermal equilibrium with their surroundings. This form of noise is called
“thermal” and is extremely random – conforming to the “normal” (Gaussian or “bell curve”) statistical distribution.
Fig. A1.1.1 The normal (Gaussian) probability distribution
Given a large number, N, of instantaneous samples, Vi , with an average of zero, the standard deviation, VN , is
defined by: -
1 N 2
VN  Vi
N i 1
For a normal distribution 68.3% of samples, on average, fall within the range 0  VN . Measuring instruments with
resolution limited by noise often quote two standard deviations (95.5%) or even three standard deviations (99.7%).
1. Johnson, J. B.: “Thermal Agitation of Electricity in Conductors”. Phys. Review 32 (1928). P97-109.
2. Nyquist, H: “Thermal Agitation of Electric Charge in Conductors”. Phys. Review 32 (1928). P110.
23
It is shown in many texts on probability and statistics that the RMS of a number of such random variables added
together is: -
VT  VN21  VN22  VN23  ...
Whereas the instantaneous measured values of voltage add arithmetically, according to one of Kirchhoff’s laws
(conservation of energy), the statistical parameters, RMS, add according to a form of Pythagoras’ theorem – if the
random variables are statistically independent they are, in a general sense, orthogonal (mutually perpendicular).
If, for example, one connected a number of resistors in series (at the same temperature) the total voltage developed
across them would have an RMS value corresponding to a single resistor with the same total resistance.
VT  4kTBR1  R2  R3  ...
It would seem (and it is no accident) that the quantity of interest has the units of (electrical) power. The “noise
power” depends only on temperature and bandwidth: -
VN2
PN   4kTB
R
The concepts of “noise power” and “noise temperature” turn out to be as useful, if not more so, compared to the
concept of “noise voltage”. If, for example, one connected a number of resistors in parallel the “noise power”
would be, as expected: -
1 1 1  VT2 VT2 VT2


PN  V  
T
2
  ...     ...
 1
R R2 R3  R1 R2 R3
It is as if each resistor is able to supply a certain amount of power (e.g. to a very cold load resistor) and these add
arithmetically to equal the total power, according to the law of conservation of energy. Unfortunately it is not that
simple – not all of the “noise power” is delivered to the load (see below).
If one short circuits the terminals of a resistor a random “noise current” would flow according to Ohm’s law, which
remains valid for RMS values: -
1 N 2 1 N Vi 2 VN 4kTB
IN   Ii 
N i 1

N i 1 R 2

R

R
(RMS)
The product of “noise voltage” and “noise current” is, not surprisingly, the “noise power” as defined above: -
VN I N  PN
In practice most applications fall somewhere between open circuit and short circuit. If one were to connect a warm
source resistor to a cold load resistor heat would flow down the connections, in the form of a random AC current.
The rate at which the heat energy flows can be interpreted as (random) electrical power: -
Heat
VN
RS IN RL
Fig. A1.1.2 A warm source and cold load
24
Part 5: Monograph 1
VN
Ohm’s law remains valid for the RMS values and, therefore: - IN 
RS  RL
VN2 RL
The power delivered to the load is: PL  I N2 RL 
RS  RL 2
The maximum power delivered to the load is found with simple calculus – the gradient is zero. Also, multiply top
and bottom by RS  RL  and divide by VN2 : -
3
PL VN2 VN2 RL

 2  0  RL  RS
RL RS  RL 2 RS  RL 3
RF engineers are familiar with this – maximum power transfer and best noise performance is when the source and
load resistance are equal. Matching also prevents reflections – a particular problem with high frequency (including
“digital”) circuits and transmission lines. If the load is matched to the source the actual power flow is one
quarter of the “noise power”: -
VN2 P
RL  RS  PL   N
4 RL 4
A1.2. Low noise pre-amps
The most basic model of a real amplifier is an ideal (noiseless) amplifier with a noise voltage source in series with
one of the inputs and a (statistically independent) noise current source in parallel. There may be two or more
statistically independent mechanisms that give rise to these but if one assumes that all practical measures have been
taken to minimise the combined effect one may as well treat each as a single source.
The noise current flows through the source impedance generating a second noise voltage in series. The source
impedance may also generate noise and so the complete model is as follows: -
Ideal amp
VS VN
RS IN
Fig. A1.2.1 A basic noise model (resistive source)
Once again one can interpret the symbols as the RMS value of the probability distributions over a specified range
of frequency. Low noise amplifiers and voltage references are often specified, for example, in the range 0.1 to
10Hz. The RMS value of the net signal at the input of the amplifier is calculated according to: -
VT2  VS2  VN2  I N2 RS2 (RMS values)
More generally noise is specified and measured/displayed in terms of spectral density – with units of either
V 2 Hz or V Hz , defined in the usual way: employing the symbol  to aid interpretation: -
 
d VT2

lim  VT2   (units: V 2 Hz ) and e n 
 
d VT2
(units: V Hz )
df f  0 f df
 
Where  VT2 is the small but finite noise voltage (squared) in the small but finite bandwidth f .
25
Noise spectral density often varies with frequency. The total noise, referred to the input of the amplifier in the
frequency range f1 to f 2 is, therefore: -
f2  d V
VT2    S
2
   f   d V   f   d I   f R
2
N
2
N 2 
df
S
f1
 df df df 
What if the source is partly inductive or capacitive? One can think of the current noise, in each infinitesimal
bandwidth, as a pure sinewave, albeit with random magnitude and phase. The phase distribution is uniform (the
same probability density from 0 to 360 degrees) and remains so regardless of the imaginary part of the source
impedance. The voltage developed does, however, depend on the magnitude of the source impedance and,
therefore, the frequency. The contribution from the noise current is, therefore: -
f2    f  Z  f  df
d I N2

2
RS  Z S  S
f1 df
In practice most datasheets specify noise in units of V Hz though often omitting the words “spectral density”.
Publications frequently include equations that appear to be dimensionally inconsistent. The symbol e n , for
example, would normally be associated with a voltage: -
en 
 
d VT2
df
Fig. A1.2.1 Noise voltage spectral density for a low noise dual JFET (U430)
Fortunately most applications are concerned with a narrow range of frequency over which the noise spectral density
can be regarded as constant so that calculations are quite simple: -
V 2d VN2   2
f  en f    VN  en f etc.
N
df
Typical values for a dual matched JFET (U430) are: -
Current (mA) VN nV Hz  IN  fA Hz  PN (W) RN (MΩ) TN (K)

1 4 ≈1 (@25ºC) 4×10 -24
4.0 0.07
26
Part 5: Monograph 1
A1.3 Optimum noise matching
The minimum value for VT coincides with the minimum value of VT2 so that, with a little algebra, one can find the
required condition, assuming the source noise and source resistance are constant: -
 
d VT2  0  2VN dVN  2RS2 I N dI N  0
It is also reasonable to assume that the noise power of the pre-amp is constant – one can trade off a reduced noise
voltage at the expense of increased noise current, pro-rata, so that: -
dI N dI N VN2 V
PN  VN I N (constant)  dVN   PN 2
 VN   dI N  RS2 I N dI N  0  N  RS
IN IN IN IN
VN
The ratio of noise voltage to noise current is the pre-amp “noise resistance”:  RN
IN
If the source is partly reactive: RN  Z S
Best noise performance is achieved, therefore, when the noise resistance of the pre-amp matches the
magnitude of the source impedance at the operating frequency.
A1.4. Some notes on Nyquist’s theory
With half a blank page left I could not resist some comments on Nyquist’s astonishing theory. During the 1920s
much progress was made in quantum theory (see, for example, [1]). Nyquist employed a similar concept in his
theory of noise: the quantisation of the electromagnetic field due to boundary conditions. His argument goes
something like the following: -
Consider an ideal transmission line (characteristic impedance R) with warm resistors (resistance R) at both ends.
Thermal equilibrium is reached and then the two ends are simultaneously short circuited, trapping the
electromagnetic energy (all power is reflected back from the short circuits). One can regard the length of line as
“vibrating at its natural frequencies”. Each mode of vibration is one degree of freedom with average energy kT.
Nyquist deduced the density of modes per Hz of bandwidth and bingo!
In the last few of lines of his paper Nyquist discussed the latest (then) thinking on statistical thermodynamics in the
light of the new quantum theory. He pointed out that the energy per degree of freedom (the principle of equal
energy partition or “peep”) consistent with Planck’s theory is: -
h
E
 h 
exp   1
 kT 
h  6.626  1034 Js is Planck’s constant and   frequency (Hz). The small value of Planck’s constant means that
for frequency range below optical (c.f. the “ultra-violet catastrophe”): -
h  h  h
 1  exp   1  E  kT
kT  kT  kT
1. Dirac P.A.M.: “The Quantum Theory of the Emission and Absorption of radiation”. Proc. Royal Soc.
(London) A114 pp. 243-265 (1927).
27
Appendix 2: Band-pass filter analysis
A2.1 The transfer function
A practical choice for the band-pass filter (inverting) is based on a single op-amp. Calculating practical component
values can be a bit tricky but, fortunately, this has been done for the frequencies of interest. The choice of
subscripts (1A and 1B) in the following circuit will become clear later (the parallel combination).
V1 C1
R2
R1A C2
VIN
VOUT
R1B
0V 0V
Fig. A2.1.1 A multiple feedback band-pass filter
If one assumes an ideal op-amp the inverting input is a virtual earth (0V) and, according to Ohm’s law and
Kirchhoff’s laws in the complex representation s  j  : -
VIN  V1
 VOUT  V1 sC1  V1sC2  1  0
V
VOUT  V1sR2C2 and
R1 A R1B
VIN V V
  1  VOUT sC1  V1sC1  V1sC2  1  0
R1 A R1 A R1B
Eliminate V1 : -
VOUT VIN 1 VOUT V V 1 VOUT

V1      VOUT sC1  OUT sC1  OUT sC2  0
sR2C2 R1 A R1 A sR2C2 sR2C2 sR2C2 R1B sR2C2
Multiply both sides by R1 A and sR2C2 : -
 R 
sR2C2VIN  VOUT 1  sC1R1 A sR2C2  R1 A sC1  R1 A sC2  1 A   0
 R1B 
The transfer function is, therefore: -
VOUT  sR2C2
 2
VIN s R1 A R2C1C2  sR1 A C1  C2   R1 A  R1B  R1B
Multiply top and bottom by R1B R1 A  R1B  to reveal the standard form: -
VOUT  2Gs N 
 2 2
VIN s N  2 s N   1
 N is the natural frequency,  the damping ratio Q  1 2  and G is the peak gain (at the natural frequency).
28
Part 5: Monograph 1
1 R1 A R1B R1 A R1B
Equating coefficients:  R2C1C2  R1R2C1C2 with R1 
 2
N R1 A  R1B R1 A  R1B
R1 is R1 A in parallel with R1B (hence the choice of subscripts).
2 2G
Also: 
R1 A R1B
C1  C2   R1 C1  C2  and 
R2 R1B R
C2  2 R1C2
N R1 A  R1B N R1 A  R1B R1 A
The natural frequency, damping ratio and peak gain are, therefore: -
1 1 R1 C1  C2  R C2
N   and G  2
R1R2C1C2 2 R1R2C1C2 R1 A C1  C2 
In practice it is possible for the capacitors to have the same value: -
1 R1 1 R2
C1  C2   N   and G 
R1R2 C R2 2 R1 A
1 1 R2
Some designers prefer the “Quality factor”: Q 
2 2 R1
Freq (Hz) Q R2 (kΩ) R1A (kΩ) R1 (Ω) R1B (Ω) C1=C2 (nF)
25 2.083 39 19.5 2247 2540 680
50 5 200 100 2000 2041 159
75 2.022 39 19.5 2385 2717 220
100 10 200 100 500 503 159
150 10 200 100 500 503 106
Fig. A2.1.2 Practical component values
A2.2 Bandwidth
The band-pass filter transfer function (with gain = 1) is, in normalised form s  j  N  jx  : -
2s 2jx
T s   
s  2s  1 1  x 2  2jx
2
Divide top and bottom by 2jx : -

1  x2  1 
T s   where tan  
1
 
1  j tan  2  x 
This form of the transfer function can be quite useful for calculating magnitude and phase. First is the phase from
an easily calculable form: -
 1
tan   Q x   where Q 
1
is the quality factor
 x 2
29
T s    cos 
1
Then the magnitude:
1  tan 2  
Note also: T s   cos exp  j 
1
It also provides a quick route to the bandwidth, best defined by the -3dB points, where the gain is :-
2
T s   1  tan 2    2  tan   1
1

2
This produces two quadratic equations each with two possible solutions – one needs to select the correct ones: -
1  x2  1 
tan      1  x 2  1  2x
2  x 
 b  b 2  4ac
The solution for the quadratic of the form ax 2  bx  c  0 is by using the usual formula x 
2a
Case 1: - Case 2: -
x 2  2x  1  0 x 2  2x  1  0
Providing solutions: -
x1     2  1 x2     2  1
The positive square roots must be the valid solutions in both cases. Assume, for example, the damping ratio is very
small (highly resonant with a narrow bandwidth). Taking the positive square root provides sensible values – just
above and below the natural frequency: -
  1  x1  1   and x2  1  
Taking the negative square root does not: x1  x2  1
The difference gets us to the bandwidth:  

x2  x1     2  1      2  1  2
The -3dB bandwidth is, therefore:   2 N
30
Part 5: Monograph 1
Appendix 3: Low-pass/notch filter analysis
A3.1 The basic low-pass filter
The basic idea is to employ a band-pass filter (inverting) and a conventional low-pass filter with two inputs: -
V1B R1B R3
BPF
V2 C2
V1A R1A R2
VIN
VOUT
C1
0V 0V
Fig. A3.1.1 A combined low-pass and notch filter.
If one assumes an ideal op-amp, Ohm’s law and Kirchhoff’s laws, in the complex representation s  j  : -
1 V  V2 V1B  V2 VOUT  V2 V2
VOUT   V2 and I  1 A     V2 sC1  0
sR2C2 R1 A R1B R3 R2
V1 A VOUT sR2C2 V1B VOUT sR2C2 VOUT VOUT sR2C2 VOUT sR2C2
        VOUT s 2 R2C2C1  0
R1 A R1 A R1B R1B R3 R3 R2
 sR C sR C 1 sR2C2 sR2C2  V V
 VOUT  2 2   2 2     s 2 R2C2C1    1 A  1B
 R1 A R1B R3 R3 R2  R1 A R1B
  R R R   R R
 VOUT 1  sR2C2  3  3  3   s 2 R3 R2C2C1   V1 A 3  V1B 3
  R1 A R1B R2   R1 A R1B
The result is a second order low pass filter (inverting) with two inputs. In normalised form s  j N  : -
 R R  1 
VOUT  V1 A 3  V1B 3  
2 
 R1 A R1B  1  2s  s 
The damping ratio and natural frequency are: -
 R R R  1
2  R2C2  3  3  3 N with  N 
 R1 A R1B R2  R3 R2C2C1
1 R2C2  R3 R R 
    3  3 
2 R3C1  R1 A R1B R2 
31
A3.2 A basic band-pass filter
The 25Hz notch filter is less critical than in the amplifier/filter units and a much lower quality factor is tolerable.
The most basic band-pass filter has a damping ratio of 1 (Q = 0.5): -
C
R
VIN
VOUT
C
0V 0V
Fig. A3.2.1 A basic band-pass filter
If one assumes an ideal op-amp, Ohm’s law and Kirchhoff’s laws, the transfer function is, in the complex
VOUT  1   1 
  R ||  R  
VIN  sC   sC 
VOUT  sRC
With a little algebra: 
VIN 1  2sRC  s 2 R 2C 2
The damping ratio and natural frequency are: -
1
2  2RCN with  N    1
RC
The maximum gain is 0.5
Practical component values (for 25Hz) are C  470nF and R  13.5k (An 8k2 fixed resistor plus a 10k
variable).
32
Part 5: Monograph 2
Low noise BJT pre-amplifiers

1. Introduction
The following circuits employ a differential “long tail pair” of matched low noise bipolar junction transistors
(BJTs). The differential structure and constant current source ensure a high level of rejection of common mode
voltage at the inputs and power supply variations. DC offset is low over a wide range of temperature.
Noise performance is excellent in applications where the source impedance is between 1kΩ and 100kΩ. If the
source impedance is lower than 1kΩ it is best to use an impedance matching transformer. If the source impedance
is significantly higher than 100kΩ (e.g. with a capacitance bridge) the contribution due to noise current becomes
dominant and it is better to use a pre-amplifier based on a matched pair of JFETs. For more details see the
monograph “A low noise JFET pre-amplifier” by the same author.
+15V
2×RC
IC IC VOUT
LM394
or similar
VIN ≈ 0V
IE IE
2×RE
V
2IE
Current regulator -15V
Fig. 1 Outline schematic of a long-tail pair.
As a rule of thumb the gain is, to a reasonably good approximation (see section 3 for details): -
dVOUT RC
G 
dVIN RE  REO
RC is the collector resistance and RE  REO is the emitter resistance (component) in series with the emitter output
resistance. The parameter REO is easily calculated from the operating current.
For a more accurate calculation replace the collector resistance with the effective collector resistance (the collector
resistance in parallel with the output resistance of the transistor).
The long tail pair can be used on its own, if accuracy and stability of the gain is not critical (e.g. as the pre-amp of a
null detector) or as the first stage, inside the loop, of a composite amplifier/integrator, employing an operational
amplifier with negative feedback for greater accuracy (e.g. as the first stage of a high accuracy voltage follower).
The choice of operating current depends mainly on the source resistance and the need for optimum impedance
matching (see section 3 for details).
1
2. A review of basic BJT theory (low frequency)
2.1 Current gain and output conductance
VC
IC
IB
VB
IE
VE
Fig. 2.1.1 A basic model for the BJT I E  I C  I B 
The collector current depends mainly on the base-emitter current but it is also a function of the collector-base
voltage due to “base width modulation”. The latter effect is small but not negligible. For a given VCB the collector
current is approximately proportional to the base current: -
IC  IC I B ,VCB   hDC I B
IC
with hDC  approximately constant
IB
Where hDC is usually referred to as the “DC current gain”. In order to analyse circuits, however, one needs to
model small signal (AC) characteristics, including the dependence on VCB: -
I C I
dI C  dI B  C dVCB
I B VCB
The first partial derivative defines the small signal current gain and the second defines the small signal output
conductance (in data sheets often referred to as hFE and hOE respectively): -
I C I C 1
Define the parameters: hFE  hOE  
I B VCB RCO
Fig. 2.1.2 Gain (hFE) and output conductance (hOE in μmhos) versus collector current (mA).
(LM394 datasheet, Dec. 1994. Courtesy National Semiconductor corp.)
The small signal current gain and output conductance increase with collector current and, for the LM394 type: -
1 I
hFE  105 log10 IC  1010 and hOE   C
RCO 100
2
Part 5: Monograph 2
For most types of matched BJT pairs the output conductance is accurately proportional to collector current (over
many decades), though the constant of proportionality may vary. The small signal current gain, on the other hand,
can vary substantially.
Fig. 2.1.3 Gain hFE  versus collector current (mA) for an SSM2210 (Courtesy Analogue Devices).
The DC current gain is, however, sufficiently large so that one can assume, for most practical purposes: -
hDC  1  I C  I B and I E  I C  I B  I E  I C and dI E  dI C
Less obvious is the relationship between the small signal current gain and the DC current gain. The latter is always
lower but not usually given in data sheets. It is easily measured but, fortunately, the difference is sufficiently small
for a design rule of thumb, as the following nice bit of analysis demonstrates: -
The collector current is approximately proportional to base current (the gradient increases slightly) and a
reasonably good fit is, therefore, the linear equation: -
I C  kIB with k a constant
The gradient hFE  is roughly proportional to the log of collector current and a reasonably good model is an
equation of the form: -
I C I C
hFE I C     ln I C     I B    ln kIB   
I B I B
Integrating results in: I C   ln kIB   1I B  I B
The constant of integration must be zero so that: I B  0  IC  0
  ln kIB   1     ln IC e  

IC
It is then clear that the DC current gain is: hDC 
IB
hFE  hDC 
The difference, at the same operating current, expressed as a ratio is: 
hFE hFE
105
For the LM394 at I C  1mA ; hFE  700 and    46 . The error is about 7% and one has, at least for the
ln 10
first iteration of the design process, the rule of thumb: hDC I C   hFE I C 
N.B. a better estimate is: hDC I C   hFE I C e (i.e. hFE at about one third the operating current.)
3
2.2 Base current
Commercially available matched pairs have properties closely matching the behaviour of an ideal BJT.
Specifically, to a very good approximation, the base-emitter junction behaves like an ideal PN junction: -
IB V 
VBE  VT ln or I B  I S exp  BE 
IS  VT 
I S  a small current depending on the doping level of the silicon.

k  1.38  1023 J K is Boltzman’s constant.
T  absolute temperature (nominally 293K at 20 ºC )
e  1.6  1019 C is the quantum of charge (e.g. on a proton)
kT
VT   25mV (at 20ºC) is a voltage corresponding to thermal energy of the electrons.
e
Note that VT is temperature sensitive and PN junctions are often employed as linear temperature sensors: -
dVT k
  86 V deg .
dT e
Note also that a measure of conformity is the linearity of VBE versus log(IC). Linearity is typically better than 0.1%,
over a very wide range of collector current (100pA to 1mA as VBE varies from about 200 to 600mV), and this
property is widely used for log/antilog and multiplier/divider circuit functions.
2.3 Emitter output resistance
The output resistance at the emitter is, from above, assuming a constant temperature: -
IS V  IB
dI B  exp  BE dVBE  dI B  dVBE
VT  VT  VT
IB dV
From section 2.1: dI C  hFE dVBE  CB
VT RCO
The small signal current gain hFE  is approximately the same as the DC current gain (see section 2.1) so that, in
many cases, it is sufficiently accurate to conclude: -
IC dV
hFE I B  I C  dI C  dVBE  CB
VT RCO
Hold the collector and base voltages constant and take a small bit of extra current from the emitter (by an amount
dIE). The emitter voltage must decrease so that VBE increases by dVBE. One can interpret this in terms of a voltage
source in series with a resistor - the emitter output resistance: -
dVBE VT 25mV
dVCB  0 and dI C  dI E  REO   
dI E IC IC
Rule of thumb: 25Ω at 1mA of current.
N.B. This low output resistance is often useful hence the frequently employed emitter follower circuit as an output
stage, especially when impedance matching to a 50Ω transmission line I C  0.5mA .
dVBE dVCB
A useful corollary is the reasonably accurate model: dI C  
REO RCO
4
Part 5: Monograph 2
2.4 BJT noise performance
The basic noise model is an ideal (noise free) amplifier with a noise voltage source in series with the input and a
noise current source in parallel with the source impedance (usually a source resistance). The source resistance also
generates noise, VS, depending on resistance and temperature (Johnson noise): -
VS VN
RS IN
Fig. 2.4.1 Basic noise model for the amplifier
The noise current flows through the source impedance creating a third noise voltage source in series with VN. The
three sources are statistically independent and conform to a normal (Gaussian) probability distribution and so
combine as follows: -
VT  VS2  I N RS   VN2 with VN  VN21  VN22
2
The total noise voltage at the input is:
Where VS, VN, etc. and IN represent the standard deviation (root mean square - RMS) of the probability distribution.
VN. and IN are normally specified, in data sheets, in terms of spectral density (volts and amps per square root of
bandwidth) and as a (graph) function of frequency (see fig. 2.4.2). Johnson noise, on the other hand, can be easily
calculated and the spectral density does not vary with frequency.
The random voltage, as measured across the terminals of a resistor (open circuit), and the random current that
would flow through a short circuit can be characterised as random variables with normal distributions with RMS
values: -
4kTB
VS  4kTRS B and I S  so that PJ  VS I S  4kTB
RS
Where: -
k  1.38  1023 J K = Boltzmann’s constant.
T  is the absolute temperature ( T  293K at 20ºC).
B  Bandwidth of the measuring instrument, usually a spectrum analyser and often specified as 1Hz.
PJ  4kTB is the “Johnson noise power”. It does not refer to any actual flow of power but it is a useful concept.
For an ideal BJT as the collector current increases the transistor input noise voltage reduces but the noise current
increases. The product (noise power) remains roughly constant. It can be shown that, for a useful range of (high)
frequency and (low) collector current for an ideal BJT: -
2B
VN 1  kT
eI C
Where: -
VN 1  Component 1 of the total noise voltage.
e  1.60  1019 C is the quantum of electrical charge (i.e. on a proton).
I C  Operating (collector) current.
See later for component 2.
5
The other main source of noise is primarily due to the base current. It is remarkable that the quantisation of charge
is directly responsible for this observable phenomenon. With a base current, IB, the average number of electrons
flowing through the base in time, T, is: -
I BT
N
e
Where e  1.60  1019 C is the quantum of electrical charge.
These are thermally generated electrons and the rate at which they pass through the base is highly random.
According to a fundamental theory of probability the number can vary (RMS or one standard deviation) by N .
e N eI B
The RMS current is, therefore: IN  
T T
This is an average over a time T and a well known theory (Fourier transforms) equates this process of averaging to
an equivalent ideal filter with bandwidth 2B Hertz.
1
 2 B  I N  2eI B B
T
In practice one can select the collector current which is related to the base current by the DC current gain: -
2eI C B
I C  hFE I B  I N 
hFE
hFE  DC current gain of the transistor (approximately equal to the small signal current gain)
1
The product of noise voltage and noise current is the noise power: PN  VN 1I N  2kTB
hFE
In practice data sheets usually provide noise performance in 1Hz of bandwidth (B = 1).
VN 1 kT PN
The noise resistance and noise temperature are: RN   hFE and T
I N eI C 4k
The formulae work reasonably well over a very wide range (decades) of frequency but only for low operating
current. In practice there is a significant (“base spreading”) resistance, RBB, in series with the base which, being at
ambient temperature, also generates noise. For the LM394 this is about 40Ω and for the SSM2210 it is typically
28Ω. Also, in datasheets, the small signal current gain is not specified accurately - noise calculations are very much
“ball park” and one ends up relying on measured performance as part of the design optimisation process.
The total voltage noise is, therefore, a combination of the ideal BJT and the Johnson noise of the extra resistance: -
VN  VN21  VN22 with VN 2  4kTRBB B
In addition, at very low frequency (typically <20Hz) the voltage noise spectral density increases, at a rate inversely
proportional to frequency (hence the name “1/f noise”), due to a further mechanism thought to be related to surface
contamination of the transistors. The noise current spectral density also increases at low frequency but, for the
LM394, the corner frequency increases with operating current, making the best choice of operating current a little
more complicated. In practice it is found that an operating frequency of 25Hz or above and a low operating current
(<1mA) avoids the problem of 1/f noise.
6
Part 5: Monograph 2
Fig. 2.4.2 Noise voltage nV  

Hz and current pA 
Hz versus frequency (kHz) for the LM394
Optimum noise performance is when the noise resistance of the transistor is the same as the source impedance
(noise matching). The equivalent noise resistance of the amplifier is, for low operating current and high frequency,
approximately: -
VN kT
RN   hFE
I N eI C
Given the source impedance one could use this to select the optimum operating current but, in many cases, this is
not sufficiently accurate. In practice it is necessary to use the datasheet information or, better still, the actual
measured performance, rather than the theoretical model. Also, the source impedance is often too low for a direct
match and it is better, therefore, to use an impedance matching transformer and a relatively high noise resistance
pre-amplifier. The transformer ratio can be made selectable to cater for a wide range of source impedance [1].
It is interesting to compare the equivalent noise resistance of an LM394 BJT at, say, 1mA operating current and
20ºC. According to the datasheet the small signal current gain is typically 700 but can be as low as 300. If one
employs the theoretical model and the typical value: -
kT
RN  hFE and 300  hFE  700  438  RN  690
eI C
If, on the other hand one relies on typical figures (fig. 2.4.2) from the data sheet.
From the datasheet at 25Hz and 1mA: VN  1.1nV Hz and I N  5 pA Hz  RN  220
The difference is considerable and measured performance is closer to the latter. The problem at low frequency is
1/f noise which is not predicted by the theory (a result of the manufacturing process). Fortunately this is still higher
than the source impedance typically encountered and so the (higher than expected) noise current is not a problem.
Also, noise performance only suffers when there is a major mismatch (typically >3:1). For lower noise current the
SSM2210, with lower 1/f corner frequency, is preferable.
From the SSM2210 datasheet at 25Hz and 1mA: -
VN  1nV Hz and I N  1 pA Hz  RN  1k
7
3. Analysis of the long tail pair
3.1 Voltage gain
For this analysis I shall assume, in addition to Kirchhoff’s laws and Ohm’s law: -
a) Perfectly matched transistors and resistors.
b) Ideal current source (the current is independent of the voltage, V).
c) Symmetrical inputs (0V ± dVIN ) and outputs (VC ± dVOUT ).
With a load resistance in the collector circuit the collector-base voltage is no longer constant – the collector voltage
decreases as the collector current increases.
+15V
RC
+dVOUT
dIC -dIC
-dVOUT
+dVIN LM394
N
or similar
-dVIN
+dIE -dIE
+dVE -dVE
RE
2IE
-15V
Fig. 3.1.1 Small signal analysis of the long-tail pair
dVBE dVCB
From section 2.3: dI C  
REO RCO
By definition, referring to fig. 3.1.1: -
dVBE  dVIN  dVE and dVCB  dVOUT  dVIN
Substitute these into the above: -

dVIN dVE dVOUT dVIN
dI C    
REO REO RCO RCO
dVOUT RE
also dI C   dVE  RE dI E and dI E  dI C  dVE   dVOUT
RC RC
8
Part 5: Monograph 2
 1 1 RE   1 1 
Re-arrange so that, to a good approximation:  dVOUT      dVIN   
 RC RCO REO RC   REO RCO 
 1 1 1 
Now     is the reciprocal of the effective collector resistance (conductance), hence the usual
 C
R RCO RCE 
(small signal) model of a current source in parallel with the output resistance and collector resistance.
1
dV R R 
Also: RCO  REO  G  OUT   EO  E 
dVIN  RCE RC 
Strictly speaking the gain of each side is negative but one normally refers only to the magnitude.
RCE
Maximum gain is achieved with zero emitter resistances: GMAX 
REO
A good choice of collector voltage is about 10V. This permits maximum dynamic range whilst keeping VCB > 5V.
One can conclude, in many cases (power supply of ±15V): -
I C RC  5V
From the second graph, fig. 2.1.2, the output conductance is proportional to the collector current according to: -
1 I
hOE   C  RCO  20 RC
RCO 100
RC
Hence the rule of thumb (for calculating gain within 5%): RCE  RC  G 
REO  RE
A frequently chosen operating current is 0.1mA so that the typical current gain is 600 and calculations based on
I E  I C should be in error by less than 0.2%. The collector output resistance is 1MΩ. Suitable collector resistors
are 47kΩ and the emitter output resistance is 250Ω.
RC RCO
The effective collector resistance is: RCE   44.9k
RC  RCO
R 44.9k
The maximum gain (zero emitter resistances): GMAX  CE   179
REO 250
For a gain of 100, employing the rule of thumb: REO  RE  470  RE  220 (an E24 value)
RC 47k
G   100
REO  RE 470
1
 250 220 
The more accurate formula is not much different: G    97.6
 44.9k 47k 
N.B. As RE increases the gain reduces. The emitter resistors provide a modicum of negative feedback and, as usual,
this helps to reduce sensitivity to variations in transistor characteristics and improves linearity.
9
3.2 Differential input resistance
If one holds one input at a constant voltage and increases the other by a small amount the base current also
increases. The ratio is the differential input resistance.
By definition: dVBE  dVIN  dVE  dVIN  dVBE  dVE
dVIN dVBE dVE

The input resistance is, therefore: RIN   
dI B dI B dI B
IB dVBE VT
The first part, from section 2.2: VBE  VT ln    hDC REO
IS dI B IB
dVE
The second part, by Ohm’s law:  hFE RE
dI B
The DC current gain is approximately the same as the small signal current gain and the input resistance is, with
sufficient accuracy in most cases: -
RIN  hFE REO  RE 
3.3 Common mode rejection (mismatched resistors)
Whereas data sheets often lack the necessary detail it is claimed that the matching of the transistors makes it
possible to achieve a common mode rejection ratio (CMRR) of 120dB (106) or more, by employing very low
tolerance/matched collector resistors (usually specified at 0.1%). This can be overkill in many applications and
maximum CMRR can be achieved with 1% or even 5% resistors if one employs a current source with sufficiently
high output resistance. Also, it is frequently necessary to deliberately unbalance the collector resistors in order to
null the input offset voltage (see section 3.5)
If one increases the voltage at both inputs by dV the voltage, V, at the current source (see figs. 1 and 3.1.1)
increases by approximately the same amount. Ideally the current does not change and the collector voltages remain
the same. In practice the current source has a finite output conductance, equivalent to a large resistor, ROS, in
parallel with an ideal current source. The current will change by a small amount: -
dV
dI 
ROS
If one assumes that the BJTs are perfectly matched the change in current is shared equally. If the collector
resistances are exactly the same the result is a change in the output common mode but not the difference. The
resistors have a tolerance RC  RC  , however, and, in the worst case (one resistor higher and the other lower than
nominal), the difference between the outputs would change by: -
dI dV
RC  RC  dVOUT  2RC  RC
2 ROS
RC
The differential gain is, approximately (section 3.1): G
REO  RE
The CMRR is usually defined as the differential gain divided by the common mode gain: -
dVOUT R ROS
G  C 
dV RC REO  RE
10
Part 5: Monograph 2
For maximum CMRR one can choose the maximum gain RE  0 . Also, for a current source with suitably chosen
BJT (high RCO), the output resistance is typically (see sections 4.1 and 2.3 respectively): -
3 104 25mV RC
ROS  and REO   CMRR  1.2  106 
IC IC RC
A CMRR of better than 106 (120dB) is thus easily achieved with 1% tolerance resistors.
3.4 Common mode rejection (mismatched transistors)
In practice the CMRR is limited by the matching of the BJTs. The effect of an infinitesimal change in collector
voltage is negligible (second order) so that, to a very good approximation: -
dVBE dVCB dVBE

dI C   
REO RCO REO
The change in current is the same but the balance is altered slightly by the mismatch.
dVE dV dVBE
dI   dI1  dI 2 with dI1  BE and dI 2 
ROS REO1 REO 2
The change in current is very nearly the same in each side and, therefore: -
dVE dVBE 2 REO

dI    dVBE  dVE
ROS 2 REO ROS
The change in base-emitter voltage is very much less than the change in base voltage (the emitters “follow” the
gate common mode). The change in the output is: -
 1 1 
dVOUT  RC (dI1  dI 2 )  RC   dVBE
 REO1 REO 2 
Which simplifies, with a little algebra: -
REO RC
dVOUT  2 dVE
REO ROS
dVOUT R R
The common mode gain is, therefore: dVE  dVB   2 EO C
dVG REO ROS
The CMMR is usually defined as the differential gain divided by the common mode gain: -
dVOUT RCE REO ROS

G 
dVG REO 2REO RC
The effective collector resistance is usually not much lower than the collector resistor (component): -
REO ROS
RCE  RC  CMRR 
2REO REO
11
Manufacturers do not specify the mismatch in the emitter output resistance characteristics but, fortunately, one can
relate this to a parameter that is specified – the current gain, based on the fundamental properties (see section 2.2).
V 
I B  I S exp  BE  and I C  hFE I B
 VT 
VT
From the analysis in section 2.3: REO 
IC
kT
The thermal voltage VT   25mV (at 20ºC) is a fundamental property and one can be fairly confident that it
e
matches accurately within a pair. The current gain, on the other hand, is known to vary considerably, depending on
the manufacturing process (level of doping). The emitter output resistance is related to the DC current gain by: -
VT
REO 
hFE I B
Once again one can be confident that the base current matches reasonably well if the base-emitter voltage is the
same and the tolerance is, therefore the simple relationship.
REO h
  FE
REO hFE
We are usually interested in the magnitude only and so the CMRR is: -
hFE ROS
CMRR 
2hFE REO
The data sheet for the low cost version of the LM394 has a typical mismatch of 1% and the SSM2210 data sheet
quotes 0.5%. Both quote a maximum of 5%.
Once again the high output resistance of the BJT current source reduces the effect of transistor mismatch and a
CMRR of 106 (120dB) is readily achieved.
12
Part 5: Monograph 2
3.5 Input offset voltage and temperature coefficient
The base-emitter voltage for an ideal PN junction is, according to theory: -
IB kT
VBE  VT ln with VT   25mV (at 20ºC)
IS e
I C1 IC 2
For each transistor in a slightly mismatched pair, therefore: VBE 1  VT ln and VBE 2  VT ln
hFE1I S1 hFE 2 I S 2
I C1hFE 2 I S1
The difference is: VBE  VT ln
I C 2 hFE1I S 2
d VBE  k I C1hFE 2 I S1 VBE

The temperature coefficient is:  ln 
dT e I C 2 hFE1I S 2 T
With both inputs connected to 0V and the emitters connected together the base-emitter voltages are identical. Any
mismatch in the transistors results in an imbalance in collector currents and, if the collector resistors are identical,
an offset at the output.
d VBE 
 0 and VOUT  I C1  I C 2 RC
I C1hFE 2 I S1
VBE  0   1 and
I C 2 hFE1I S 2 dT
The output offset can then be eliminated by either: -

a). Applying an offset to one of the inputs or
b). Adjusting the collector resistors: VOUT  I C1RC1  I C 2 RC 2  0V
The latter preserves the condition for minimum temperature coefficient and is recommended. The mismatch in
collector resistors reduces the common mode rejection ratio slightly but this is not usually a problem with a high
output resistance BJT current source. This theory is not perfect but sufficiently accurate for most purposes.
+15V
Trimpot
≈ 1% of RC
2×RC
IC1 IC2 ΔVOUT = 0V
ΔVIN = 0V
V
IC1+IC2
-15V
Fig. 3.5.1 Offset trim for retaining good temperature matching
Any residual temperature sensitivity, due either to the transistor mismatch or from the source, can be significantly
reduced by a combination of offset trim methods. See the LM394 application note AN-222 for details.
13
4.1 A basic current regulator
A very simple current regulator employs a low cost, high gain BJT with guaranteed minimum collector output
resistance (e.g. BC109). The base is held at a constant voltage including a pn junction for temperature
compensation for the transistor VBE though some claim that two diodes or even a (red?) LED provides a better
match. The 47nF capacitor provides low impedance at high frequency preventing any AC signal on VC from getting
through to the base via the collector-base capacitance (≈5pF).
An increase in VC tends to increase IC depending on the inherent collector output resistance of the transistor. The
result is an increase in VE and a reduction in the base current, counteracting the change. The (negative) feedback
thus increases the effective output resistance of the transistor.
VC 0V
10k 47nF
IC
VB ≈ 7.8V
VE ≈ 7.2V 1N4148
RCC 10k
-15V
Fig. 4.1.1 Circuit model for the current regulator
dVB dVE dVC dVB

From section 3.1: dI C    
REO REO RCO RCO
RCC dV
dVB  0 and dVE  RCC dI E  dI C   dI E  C
REO RCO
dVC  R 
To a good approximation: dI E  dI C  ROS   RCO 1  CC 
dI C  REO 
The effective output resistance is, therefore, boosted by a large factor.
The base is normally held at about half the negative power supply so that the voltage across RCC is about 7V. Also
to a good approximation (rule of thumb) the emitter output resistance is inversely proportional to current: -
7.2V 25mV  7.2V 

RCC  and REO   ROS  RCO 1    290 RCO
IE IE  25mV 
100k
The output resistance of a suitably chosen BJT (e.g. BC109A) is: RCO  so that, very approximately: -
I C mA
3 104
ROS 
IC
14
Part 5: Monograph 2
4.2 A fully differential pre-amp
A long tail pair, followed by a differential in/out amplifier, makes an excellent pre-amplifier for a resistance bridge
null detector. Gain accuracy and stability, linearity and DC offsets are relatively unimportant – the most important
thing is very low noise and a fully differential structure to avoid earth loop problems. The following was
constructed as a stripboard prototype with an LM394 matched pair and some 0.1% 10k and 100Ω resistors
scavenged from an old resistance box. A TL072 low cost dual op-amp is perfectly adequate for the differential
amplifier (P channel JFET input stage so that in input range is up to the positive supply voltage). The back to back
diodes protect the matched pair from excessive input signals. Local power supply decoupling of 100nF (ceramic) is
usually sufficient if a very good quality regulated PSU is employed (recommended).
100Ω +15V
100nF
2×10k TL072
VC ≈ 7.5V 10k
VIN 5k VOUT
2×1N4148
10k
2×100Ω
47nF
0V
1N4148 10k
100nF
4k7 10k
-15V
Fig 4.2.1 A basic long tail pair pre-amp and differential amplifier
The long tail pair has a gain of approximately 200 followed by the differential amplifier gain of 5 (overall ×1000).
In practice the next stage is usually a band-pass filter with differential input stage and single-ended output stage,
after which earth loops cease to be an issue. For test purposes a differential amplifier, based on a single op-amp
with a gain of ten, would facilitate connection to a spectrum analyser.
The inputs should be connected by a screened twisted pair and the layout of the front end should be to minimise the
area through which stray magnetic flux can flow (especially the loop consisting of VIN and across the transistor
bases and the loop consisting of the 100Ω resistors and emitters). It is probably not necessary to screen the whole
amplifier but, if one does, then the screen (also the twisted pair) should be connected to local power supply 0V.
An operating current of 0.75mA was chosen so that the collectors are at approximately 7.5V and well within the
input range of the op-amps, including the maximum AC signal. The outputs of the op-amps are also biased at 7.5V
which limits the maximum signal but this is not a major problem. The upper limit for the TL072 is +13V and so the
maximum output is 11V peak-peak (22V differential).
15
4.3 A pre-amp with feedback
If the gain needs to be accurate and stable it is recommended that feedback be applied to one side of the long tail
pair. One of the inputs is labelled 0V (signal) and must be connected to the 0V (usually a virtual earth) side of the
bridge output. To avoid an earth loop the following stage can employ a differential input (the difference between
VOUT and signal 0V). Better still is to avoid an earth loop completely by employing an impedance matching
transformer. The signal 0V can then be connected to the local power supply 0V. The recommended collector
resistors are chosen so that, at the operating current, the collectors are at approximately 10V and well within the
input range of the LF356 (also a P channel JFET input stage). The action of feedback maintains the AC signal on
the collectors zero (or very small) so that maximum signal handling is limited only by the range of the op-amp
output (typically ±13V and only a little more than the previous example because it is single-ended).
Trimpot +15V
≈ 1% of RC 100nF
2×RC
LF356
≈10V VOUT
10k
VIN
10Ω 0V
(signal)
0V
(signal) 2×1N4148
0V
10k 47nF (PSU)
1N4148
100nF
RCC 10k
-15V
Fig. 4.1 A low noise pre-amplifier (gain = 1000)
With a closed loop gain of 1000 there is no problem with stability, though the bandwidth is reduced, compared to
the unity gain frequency of the op-amp. The gain of the front end is, very approximately: -
5V 25mV R
RC  and REO   G  C  200
IC IC REO
This would tend to increase the bandwidth but the much lower feedback factor (10-3) results in an overall reduction
of the bandwidth to one fifth (0.2) of the op-amp (approx 1MHz with a LF356: GBWP = 5MHz). This is not a
problem for most applications. The 10Ω in the feedback divider contributes negligible noise.
A large DC offset at the output can be a nuisance and so a DC offset trim is included. With a 470k resistor up to
320μV of mismatch can be corrected. Lowest temperature coefficient of DC offset is achieved when the operating
currents of the two transistors (and collector voltages) are precisely the same. For the very best DC performance,
therefore, it may be worth including an offset trim on the LF356 as well – for adjusting the output offset.
16
Part 5: Monograph 2
4.4 A low noise stage for an HAVF
With a little modification the previous example can be converted to a one-plus-integrator suitable for the first stage
of a high accuracy voltage follower (e.g. for the active drive of a three-stage ratio transformer) [1 and 2].
The feedback resistor is replaced by a capacitor. The time constant required usually means quite a large capacitor
(≈1-2μF with a 10Ω resistor). The load impedance is then too low for the op-amp. A simple solution is to increase
the 10Ω resistor by a factor of 10 and reduce the capacitor accordingly. The Johnson noise of the 100Ω resistor is
then comparable to the transistors but not critical. The resulting circuit works well at low frequency (sine wave - no
high frequency signal present). The back to back diodes (2×1N4148) across the capacitor help restore stable
operation after transient overload conditions (e.g. power-up) [2].
With a capacitor in the feedback circuit the feedback factor, at high frequency, increases to 100%. The closed loop
gain falls to unity and so, for stability, the loop gain needs to be reduced with a snubber (470Ω in series with
330pF). See below for details.
1kΩ
100nF +15V
2×47k
LF356
470Ω 330pF ≈10V VOUT
100nF
VIN
100Ω 0V
(signal)
0V
(signal) 2×1N4148
0V
(PSU)
10k
1N4148 100nF
36k 10k
-15V
Fig. 4.4.1 The first (low noise) one-plus-integrator stage of a high accuracy voltage follower (F18 type).
With the F18 type ratio transformer the follower voltage noise contributes very little to the overall performance but
the noise current needs to be low. Also, the very low resistance of the second energising winding requires excellent
DC performance. Noise current and DC performance is improved with low operating current (lower self-heating)
and an operating current of 0.1mA proves to be a good compromise. With the F17 type transformer, however, the
follower noise is more important and DC less critical (higher winding resistances) and an operating current of 1mA
is recommended. In both cases the DC offset adjustment is essential.

2. Part 4, monograph 2: “High accuracy voltage followers”
17
4.4.1 Stability and the snubber
The best way to reduce the open loop gain is a snubber across the collectors. At very low frequency the impedance
of the snubber is very high and it has no effect. The gain of the long tail pair is approximately 180 (see section
3.1.). At a frequency corresponding to twice the collector resistance and the snubber capacitance the gain starts to
fall. At the frequency corresponding to the snubber resistance and capacitance the impedance reaches its minimum
and the gain levels out. To be on the safe side the snubber resistance is chosen to be 200 times smaller than the
combined collector resistances and the gain levels out to just below unity. As a result the overall open loop gain,
including the op-amp, falls below unity just below the frequency at which the op-amp gain is unity and the stability
margin is about the same as the op-amp.
1
Pole frequency, at which the LTP gain starts to fall: f1   5.13kHz
2 2 RC CS
1
Zero frequency, at which the LTP gain levels out: f2   1.03MHz
2RS CS
The overall open loop transfer function is, therefore, LTP gain with a pole and a zero followed by an integrator,
representing an ideal op-amp: -
1   2s 1
T s   G  
1   1s  3 s
1  2RCCS  3.1 105 s  2  RS CS  1.55  107 s
The time constant for the op-amp corresponds to the gain-bandwidth product (GBWP) also known as the unity gain
frequency (5MHz for an LF356): -
1
3   3.2  108 s
2fGBWP
Fig. 4.4.1.1 Open loop gain (frequency in Hz)
The overall open loop gain initially falls at first order (one decade per decade) with a phase shift of 90 degrees. The
pole at 5kHz increases the slope to second order until the zero frequency of 1MHz after which it reverts to first
order. The phase shift when the gain passes through unity (0dB), with an ideal op-amp, is approximately 100
degrees, providing 80 degrees phase margin. In practice most op-amps have internal frequency compensation so
that the phase margin is at least 45 degrees and so the overall phase margin is reduced by 10 degrees to at least 35
degrees. There is some peaking in the closed loop frequency response at the upper cut-off frequency but this should
not be a problem if no high frequency signals are present.
18
Part 5: Monograph 2
4.5 A useful variant
A useful compromise, for a null detector pre-amp, is to apply feedback to one of the emitters. The 10kΩ feedback
resistor and emitter output resistance determine the feedback factor and, therefore, the closed loop gain. The closed
loop gain is not as accurate or stable as example 4.3 (the emitter output resistance is temperature sensitive) but the
fully differential input stage avoids the problem of earth loops. The 10k resistor to 0V on the other emitter restores
symmetry and balance.
The operating current is set precisely with a zener voltage reference and an op-amp applying negative feedback.
The action of the feedback is to maintain the collector voltage of the first transistor at precisely 5.1V below the
+15V supply. The current through the 5k1 collector resistor is, therefore, maintained at a stable 1mA. The diode in
series with the emitter resistors avoids latch-up under transient conditions. The other op-amp also applies feedback
to maintain the other collector at precisely the same voltage. Both feedback loops require a snubber to reduce loop
gain at high frequency in order to ensure stability.
A low cost dual op-amp (TL072) is perfectly adequate for most applications.
+15V
2×5k1 5V1 100nF

36R 4n7
VOUT
36R 4n7
2×1N4148
VIN
1k8
10k
10k
2×10Ω
0V
100nF
-15V
Fig. 4.5.1 A useful variant with fully differential input.
The gain is easily calculated, at least approximately. For the case above (1mA operating current): -
RF 25mV 10k
G 1 with REO   G  400
REO IC 25
If a DC offset trim is required the same technique as above may be employed. A 100Ω collector trimpot will
usually suffice.
19
Part 5: Monograph 3
Low noise JFET pre-amplifiers

1. Introduction
Junction field effect transistors (JFETs) have a higher noise voltage, compared to bipolar junction transistors
(BJTs) [1] but much lower noise current. Their noise resistance is much higher and suited to applications where the
source impedance is greater than about 100kΩ.
Whereas excellent integrated circuits are available (e.g. the Analogue Devices AD 645 op-amp and the Burr-Brown
INA126 instrumentation amplifier) the absolute best noise performance is achieved with discrete transistors or
proprietary matched pairs.
The most frequently used pre-amplifier circuit is the differential in/out long tail pair. The long tail pair can be used
on its own, if accuracy and stability of the gain is not critical (e.g. as the pre-amp of a null detector) or as the first
stage, inside the loop, of a composite amplifier/integrator, employing an operational amplifier with negative
feedback for greater accuracy. In high accuracy applications JFETs are mostly employed at the front end of a
charge amplifier, as part of a capacitance bridge, typically operating at 1.6kHz.
The choice of operating current depends mainly on the type of JFET. Generally speaking a higher current results in
a lower noise voltage and higher noise current but not in simple inverse proportion as with BJTs. The best way to
match source resistance is by selecting the right type of JFET (larger area devices have lower noise resistance). The
best choice of operating current is at the upper end of the device capability as the gain is also higher and the noise
voltage (usually the main issue) is lowest. One must be aware, however, of self heating and heat dissipation (good
ventilation and a heat sink help) as noise current increases significantly with temperature.
DC performance is not particularly good, in terms of both initial matching and temperature stability. The best (and
most expensive) proprietary matched pairs have a mismatch of 10mV or more and often require an offset trim.
Other parameters, on the other hand, are quite well matched, especially when the DC is trimmed (precisely matched
operating current) and a common mode rejection ratio of over 100dB (105) is readily achieved.
An alternative to the long tail pair is a differential source follower. The main advantage is speed (no Miller
capacitance) and a bandwidth of many MHz The main disadvantage is low gain (approximately ×1) and the need
for a low noise amplifier stage to follow. There are, however, a number of applications where a source follower
pre-amplifier could be a useful extra. In a multi-purpose instrument, for example, a wide range of source
impedance can be catered for with a BJT front end and a source follower. The source follower is switched in for the
higher impedance ranges.
An N-type JFET is basically a thin conduction channel of N-type semiconductor material embedded in a P-type
substrate forming a high quality PN junction. At each end of the conduction channel connections are brought to the
surface with N-type material (drain and source). An insulating depletion region is formed at the PN junction [2].
VD Drain
Source Gate Drain
IDS
Gate
VG
Source
VS
P-type substrate
Fig. 1.1 A basic model for the JFET (N-type)
1. Part 5, monograph 2: “Low noise BJT pre-amplifiers.”

2. Part 5, monograph 4: “JFET Theory.”
1
A single connection is made to the substrate (the gate). The extent of charge carrier depletion and, therefore, the
shape and thickness of the conduction channel depend on the relative voltages of all three connections. Whereas
some devices are precisely symmetrical, with regard to drain and source, others are designed to minimise on-chip
capacitance between the gate and drain. At low frequency the drain and source are usually interchangeable.
In most applications the PN junction is reverse biased and the current flowing in or out of the gate is negligible (a
few pA at ambient temperature). The current flowing “down the drain” is almost exactly the same as that flowing
“out of the source” (hence the silly names). The most frequently used mode of operation is the “pinched-off” mode
where the drain-gate voltage is strongly reverse biased and the conduction channel at the drain end is extremely
thin (“pinched off”). In this mode the drain-source current, I DS , depends mainly on the gate-source voltage but it is
also a function of the drain-gate voltage. The latter effect is small but not negligible. According to a fairly basic
model, to a good approximation [1]: -
VGS  VP  I DS  I DS VGS ,VDG   k VGS  VP 

2
with k and VP approximately constant
and
VGS  VP  I DS  0
Where: VGS  VG  VS and VDG  VD  VG
Both VGS and VP are numerically negative. The small signal analysis is usually defined by: -
I DS I
dI DS  dVGS  DS dVDG
VGS VDG
The first partial derivative defines the small signal forward transconductance and the second defines the small
signal output conductance (in data sheets often referred to as gFS and gOS respectively): -
I DS I DS 1
Define parameters: g FS  gOS  
VGS VDG RDO
g FS and gOS are themselves functions of the drain-source current. RDO defines the drain output resistance and is
analogous to the collector output resistance as in the case of BJTs. The parameters k , VP , g FS and g OS depend on
the type of device and also vary from device to device of the same type. Fortunately there are some fundamental
relationships between them which allow some useful design rules of thumb. The main one is that characteristics
match very closely for devices of the same type when operated at precisely the same current [1]. One need not pay
top dollar to achieve excellent performance with either an integrated pair or with two single transistors glued
together.
An equally valid form of the equation, preferred by this author, employs the (numerically positive) variable source-
gate voltage (VSG).
VSG  VP  I DS  k VSG  VP  VSG  VP  I DS  0
2
and
Take the square root for the linear equation: I DS  k VSG  VP 
The other mode of operation is as a voltage controlled resistor (VCR). This has a potential benefit which is
explored in section 4.
2
Part 5: Monograph 3
2. The long tail pair
The most frequently used JFET pre-amplifier is the differential “long tail pair” of matched low noise transistors
operated in the pinched-off mode. The differential structure and constant current source ensure a high level of
rejection of common mode voltage at the inputs and power supply variations. DC offset is not particularly accurate
or stable, with respect to temperature, compared to a BJT matched pair or even a low cost op-amp. An input offset
of 10mV is considered a good one.
The JFET high input impedance is easily damaged by electrostatic discharge and low leakage back-back diodes are
recommended for protection. These are basically JFETs with drain and source connected together to form the
cathode.
+15V
2×RD
IDS IDS VOUT
U430
or similar
VIN ≈ 0V V
Current regulator 2IDS
-15V
Fig. 2.1 Outline schematic of a long-tail pair.
As a rule of thumb the gain is, to a good approximation (see appendix section A1): -
dVOUT R R 1
G  g FS RDE with RDE  D DO and RDO 
dVIN RD  RDO gOS
g FS is the forward transconductance of the JFET and RDE is the effective drain resistance (the component resistance
in parallel with the drain output resistance, RDO).
The choice of operating current depends mainly on the type of JFET. Generally speaking a higher current results in
lower noise voltage and higher noise current but not in simple inverse proportion as with BJTs. The best way to
match source resistance is by selecting the right type of JFET (larger area devices have lower noise resistance). The
best choice of operating current is usually a trade-off between voltage noise and stage gain. Whereas higher current
results in higher forward transconductance the gain is lower – the drain resistors can be higher. See the monograph
“JFET theory” for more detail [1].
Other parameters, on the other hand, are quite well matched, especially when the DC is trimmed (precisely matched
operating current) and a common mode rejection ratio of over 100dB (105) is readily achieved.
Typical values for a dual matched JFET (U430) are: -

1 4 ≈1 (@25ºC) 4×10 -24
4.0 0.07
1. Part 5, monograph 4: “JFET Theory”. See section 2.6.
3
3. A differential source follower
An alternative to the long tail pair is a differential source follower. The main advantage is speed (no Miller
capacitance) and a bandwidth of many MHz The main disadvantage is low gain (approximately ×1) and the need
for a low noise amplifier stage to follow. There are, however, a number of applications where a source follower
pre-amplifier could be a suitable add-on extra. In a multi-purpose instrument, for example, with a low noise BJT
front end, the source follower could be switched in for a high source impedance range.
+15V
VIN ≈ 0V
U430
or similar
VOUT
2×RS
-15V
Fig. 3.1 A differential source follower
The input impedance is extremely high and the output resistance is moderately low – suitable for input to a BJT
matched pair. According to Ohm’s law and JFET theory [1], for each transistor: -
dVS  RS dI DS and dI DS  g FS dVGS  gOS dVDG
The change in drain-gate voltage has a very small affect on the gain: gOS  0  dI DS  g FS dVGS
dVS g FS RS
With a little algebra, for each JFET: dVGS  dVG  dVS  G  
dVG 1  g FS RS
The output resistance is also easy to calculate. If one holds the input constant and then takes a small bit of extra
current from the source, the source voltage must fall according to: -
dI DS  g FS dVGS  g FS dVG  dVS    g FS dVS  RSO  

dVS 1

dI DS g FS
The result is typically between 100Ω and 1kΩ. With a following input capacitance of a few pF a bandwidth in
excess of 100MHz is easily achieved.
A differential follower can also be used on its own, if accuracy and stability of the gain is not critical (e.g. as the
pre-amp of a null detector). It can also be used as the first stage, inside the loop, of a composite op-amp, employing
a low noise (BJT input) operational amplifier with negative feedback. A source follower would be particularly
useful in the front end of a high speed charge amplifier, operating at a frequency of 160kHz or even higher, as part
of a high speed capacitive transducer signal conditioner. Whereas such measurement systems are only moderately
accurate (to 0.01% at best) they are often key subsystems in much higher accuracy measurement and control
systems (e.g. nano-positioners and high accuracy optical instruments).
With a gain of only ×1 the stability of a feedback system is readily achieved.
4
Part 5: Monograph 3
4. An ultra-low input current pre-amplifier
The input (leakage) current of a JFET, in pinch-off mode, is largely dependent on the drain-gate voltage as well as
temperature. Unfortunately there is very little information available on gate leakage in voltage controlled resistance
(VCR) mode. A typical datasheet contains the following: -
Fig. 4.1 Gate leakage current versus drain-gate voltage (J112 courtesy Siliconix)
It should be possible to operate a JFET pair in VCR mode with much reduced drain-gate and source-gate potential
differences, resulting in very much reduced leakage current and, therefore, much lower current noise. The J112, for
example, is a symmetrical device and, if the drain and source are maintained at equally positive and negative
potentials, relative to the gate, the net leakage current should be extremely small. A reasonably good model is an
ideal (zero leakage) JFET with two very large resistors (typically >1012Ω) with leakage currents of the order
<100fA (10-13A) through each. In practice this would require the transistor package to be extremely clean (degrease
with fresh cotton wool and methylated spirits) with complete screening/guarding and a very good insulator (PTFE
or sapphire) for the gate terminal post [1].
VD
VIN
VS
Fig. 4.2 A symmetrical JFET model
The resistors are temperature sensitive as well as non-linear, depending on the potential differences. It should be
possible, however, to employ negative feedback to adjust the drain and gate DC potentials on a relatively long
timescale, relative to the operating frequency, with guaranteed loop stability over a useful range of conditions.
It is also possible to arrange for the drain and source voltages to “follow”, almost exactly, the gate AC potential
thus “bootstrapping” the drain-gate and source-gate resistances and capacitances [2].
1. Yeager, John. & Hrusch-Tupta, Mary Anne et al: “Low Level Measurement”, 5th edition.
Keithley Instruments Inc. For more practical tips on very high resistance and very low current measurements
see sections 2 and 4.
5
A practical circuit could be a differential cascode stage with a matched (low noise) BJT pair. This is preferable to a
long-tail pair (operated in the VCR mode) as the gain is much greater (see appendix A3). The resistors (R1 and R2)
determine the drain-source operating voltage (typically 0.1V). The diode compensates for the base-emitter voltage
and its variation with temperature. If the BJTs are perfectly matched the voltage developed across R2 is then
imposed across both JFETs. The value of resistor, R3, is chosen so that the drain and source voltages are
approximately equal and opposite relative to 0V (VC = 0V). Fine adjustment is then provided by the control voltage.
The 100kΩ potentiometer allows for a slight mismatch between the JFETs (up to 15mV difference in pinch-off
voltage). The input JFET must have the lower “on” resistance when tested with a meter (VGS = 0V). The
potentiometer is then set for zero output when the input gate is connected to 0V.
The input capacitors represent the ground capacitance, including the input capacitance of the JFET and a transducer
capacitance/reference and/or the feedback capacitance if configured as a charge amplifier.
100nF +15V
RC R1 RC
VOUT
VC K
Diff amp
R2 100k
100k
VIN ≈ 0V
0V
100Ω 10μF
Total input VS VC
capacitance, C
R4
R3
100nF -15V
Fig. 4.3 A differential cascode input stage with gate leakage control
If the JFETs, BJTs and collector resistors are perfectly matched the output should not change, at least not
instantaneously, when the control voltage is adjusted. If, however, there is a net leakage current the potential at the
gate of the input JFET will gradually ramp up or down resulting in a slowly varying output. This “DC” component
can then be fed back, with a suitable dynamic response, to automatically adjust the leakage current and maintain the
gate voltage at 0V. The adjustment range of VS is small and depends on the ratio of R3 and R4 (typically a control
signal of ±10V is reduced to ±0.1V). A reasonably good model would be, in the (very low frequency) complex
RS C VE
VIN VOUT
G
R
VS H(s)
Fig. 4.4 The pre-amp feedback model
At the operating frequency the signal passes through the capacitor, is amplified, and appears at the output.
6
Part 5: Monograph 3
 1 
The most basic feedback network is an integrator, based on an op-amp  H s     . The differential amplifier
  I s 
must be connected the right way round to ensure that the feedback is negative.
The JFETs are, in effect, constant current sources (inputs constant) and the biasing resistors (R1 and R2) can be
relatively large – the JFET source node is a high resistance point. The attenuation of the control signal is
determined, therefore, almost entirely by resistors R3 and R4. The effective time constant of the integrator is
increased so that with integrator components RI and C I : -
R3  R4
R4  100R3   I  RI CI  101RI CI
R3
For the model (see fig. 4.4) with negligible source resistance RS  0 and   RC : -
G  1 
H s    VIN  VS  VIN 
1 G
 VS   VE   
Is Is Is  1  s 
 G  G  s 
 VS 1      V
  I s1  s    I s  1  s  IN
VS  Gs
The transfer function, from VIN to VS is, therefore: 
VIN G   I s   Is 2
Divide top and bottom by G and the result is a second order band-pass characteristic: -
VS  s 
 with  I  I
VIN 1   I s   Is 2
G
This time the effective time constant of the integrator is reduced - by the preceding gain. In standardised and
normalised form s  j N  : -
VS  ks

VIN 1  2s  s 2
1 1  I
The natural frequency is:  and damping ratio: 
 I 2 
The constant k is related to the peak gain:

VS
s  jN       k
VIN  I 2
Loop stability depends on the damping ratio. A reasonable compromise is slight underdamping   0.5 so that the
time constants need to be approximately the same.
For stable operation, therefore:  I  
A large source resistance will also affect stability, limiting the range of applications. There is little point in detailed
analysis as the leakage resistance is highly unpredictable. It will be necessary to experiment with a prototype.
7
The transfer function from VIN to the main signal output is: -
VOUT 1 VS  Is 2
 
VIN H s  VIN 1   I s   Is 2
As expected this is a second order high-pass filter with the same natural frequency and damping ratio as above.
From the monograph “JFET theory” the current in VCR mode is [1. See section 2.5]: -
VDS  VG  RC dVG
VD  VS  0  I DS  1    dVC  RC dI DS  VDS
R0  VP  R0 VP
VDS dVC R I
By definition, when VG  0V :  I DS    C DS
R0 dVG VP
The overall gain, including differential amplifier (gain = K) is, therefore: -
dVOUT R I
G  K C DS
dVG VP
The J112 has an “on” resistance of about 50Ω and a reasonable choice of operating current is 2mA each side. When
stabilised this would result in drain and source voltages of ±50mV relative to the gate (0V). With a drain-gate and
source gate resistances of the order 1012Ω the resulting leakage current is 50fA in each (at 20ºC). This is
comparable with the best MOSFETs with the advantage of lower noise voltage (MOSFETs tend to be noisy). Fine
adjustment, by the action of feedback, then reduces the net average current to near zero, limited only by the leakage
current of the input capacitors.
The input capacitor could be constructed with PTFE or, even better, sapphire insulators with leakage currents at the
limit of measurement (≈10-17A or 10 atto-amps). According to theory the random fluctuation in each of the leakage
currents (current noise) is predicted to be [1. See section 3]: -
 I N  2eI L B and I L  50 fA  I N  0.13 fA Hz
Where e  1.60  1019 C is the quantum of electrical charge (i.e. on a proton) and B is the bandwidth in Hz.
A typical application would have an input capacitance of 10pF. This could be a very low leakage component
capacitor or capacitance transducer. The input capacitance represents the total capacitance at the input, including
ground capacitance and any feedback capacitance, as in the case of a charge amplifier. The resulting time constant
 
is around 10s R  1012  and a natural frequency of 0.16Hz (high-pass cut-off). This should facilitate operation at
half the power supply frequency (25 or 30Hz) or even lower.
The BJTs should be able to operate correctly with a collector-base voltage as low as 5V, allowing a DC voltage
drop across the collector resistors of 10V and collector resistances of 5kΩ. With a pinch-off voltage of -2V the
JFET gain is approximately ×5: -
RC I DS
5
VP
1. Part 5, monograph 4: “JFET theory”.
8
Part 5: Monograph 3
The gain of the differential amplifier needs to be sufficient for the noise contribution of the following stage to be
negligible. A convenient value is K = 20 so that the overall gain, including JFET stage, is ×100 and compensates
for the effect of the attenuator on the feedback time constant. The actual integrator component values then
determine the time constant.
The voltage noise contribution from the collector resistors is negligible compared to that generated by the noise
current of the JFETs and the noise voltage added by the BJTs. According to theory the “Johnson” current noise and
voltage noise generated by a resistor are [1. See section 2.4]: -
4kTB
IS  and VS  4kTRS B
RS
Where k  1.38  1023 J K = Boltzmann’s constant, T  is the absolute temperature ( T  293K at 20ºC) and
B  Bandwidth in Hz. With a drain-source resistance of 50Ω the noise current is: -
I S  18 pA Hz This flows through 5kΩ  VN 1  91nV Hz at the collectors.
The noise generated by the collector resistor, on the other hand, is negligible: VN 2  9.1nV Hz
The noise of the BJT, referred to the input, at 2mA operating current, is of the order 1nV Hz (SSM2010). This
is then amplified, by approximately the ratio of the collector to the emitter resistance (×100), also resulting in a
noise component of around VN 3  100 nV Hz . The three noise sources are statistically independent and combine
as the root mean square (RMS) [2. See appendix A1]. Also, the same noise from the other side combines to
increase the overall noise by a factor of 2
VT  VN21  VN22  VN23  ...  2  VT  189 nV Hz
The equivalent voltage noise, referred to the input (divide by the voltage gain), is very approximately
VN  40 nV Hz and significantly more than one would expect in the pinched-off mode (typically 5 nV Hz ).
As a ball-park estimate the noise resistance of the pre-amp is the ratio of the noise voltage and noise current: -
VN 40 nV Hz
RN    308M
I N 0.13 fA Hz
Suitable values for R2 and R1 are 1kΩ and 150kΩ respectively, consuming a modest extra 0.1mA of supply current.
The noise voltage developed by R2 and R3 is common to both sides and is easily rejected by the differential
amplifier. Suitable values for R3 and R4 are: -
14.95V
R3   3.65k  R4  365k
4.1mA
A fixed and variable resistor, connected in series, is probably the best solution for R3.
Finally, given the unpredictability of the integrator time constant required, it could be argued that a more adaptive
control loop, consisting of a microcontroller (with ADC and DAC), would be preferable. The algorithm could
continuously analyse the response of the loop and self optimise accordingly. See, also, section 5.4 and [3].
1. Part 5, monograph 4: “Low noise BJT pre-amplifiers”.
9
5. Charge amplifiers
5.1 Op-amp based charge amplifiers
The main low noise JFET circuit of interest in high accuracy electronics is a charge amplifier, as part of a null
detector in a capacitance bridge or signal conditioner [1], [2] and [3]. Excellent performance is possible even with a
low cost JFET input op-amp. Numerous types are available with typical RMS input noise of 12nV Hz .
The circuit is very simple – basically an inverting amplifier [4] with input capacitors (typically a variable and
reference capacitor) and a feedback capacitor. The action of feedback is to maintain the inverting input at 0V
(“virtual earth”). The ground capacitance usually consists of coax cable (connecting the transducer to the charge
amplifier) plus stray and input capacitance of the op-amp and capacitance in the transducer. With zero signal
voltage across no current flows through and its existence does not affect the measurement, apart from contributing
to the noise gain. For best noise performance the feedback capacitor should be smaller than the total ground
capacitance, subject to the requirement for closed loop bandwidth and negligible contribution due to noise current.
A smaller feedback capacitor means higher gain but lower bandwidth and more phase error at the operating
frequency. The feedback resistor provides a route for the DC leakage current and needs to be very large to ensure
low phase error and negligible noise current (typically 1GΩ with 10pF or 100pF at 1.6kHz). The precise values of
the feedback resistor and capacitor are not critical and DC at the output is not usually a problem. Much more
important are the provision of an overall screen and the avoidance of earth loops [5].
+15V
RF 100nF
CF
VV CR LF356
VOUT
VR
CT
CG 100nF
0V
-15V
Fig. 5.1.1 An op-amp based charge amplifier
1. Part 1, monograph 3: “Rotary capacitive displacement transducer.”

2. Part 1, monograph 4: “Linear capacitive displacement transducers.”
3. Part 1, monograph 5: “Variable gap displacement transducers”.
4. Part 4, monograph 1: “High gain blocks”. See section 3.
5. Part1, monograph 2: “High accuracy single capacitors”. See section 2.
10
Part 5: Monograph 3
Stability and noise performance depend on the size of the ground capacitance, CG. The feedback factor, at the
operating frequency, is determined by the feedback capacitor and the ground capacitance in parallel with the total
input capacitance, CT + CR. The latter is usually negligible and the feedback factor is, to a good approximation: -
CF C
Feedback factor: F  F
CT  CR  CG CG
The closed loop upper frequency response is reduced, compared to the open loop bandwidth of the op-amp by the
feedback factor: -
1
Closed loop bandwidth: CL  FB 
 CL
Where  B is usually referred to as the unity gain frequency or gain-bandwidth product.
Typically the op-amp bandwidth is 5MHz (LF356). With a ground capacitance of 100pF (1m of coax cable) the
feedback capacitor can be as low as 10pF (F ≈ 0.1) in which case the closed loop bandwidth is 500kHz and the
phase shift is negligible at an operating frequency of 1.6kHz.
Similarly, the feedback resistor also limits the lower frequency bandwidth. The overall result is a band-pass
characteristic with widely separated poles. It is shown elsewhere [1], and in many elementary texts, that the band-
pass characteristic, with respect to the VR input, can be described with a transfer function of the form s  j  : -
 H s  
TR s  
VOUT Z
 2   
VR Z1  H s    s  
Where Z1 and Z 2 are the input and feedback impedances respectively. H s   1  B s is the open loop characteristic
of the op-amp (an integrator) and  s  is the reciprocal of the feedback factor.
CT  sRF CF   1 
 TR s        
CF  1  sRF CF   1   CL s 
1 
The net phase shift is approximately:  
RF CF CL
One can consider the op-amp noise voltage to be in series with either input. With zero input voltages the equivalent
circuit is a non-inverting amplifier: -
RF
CF
VOUT
LF356
VN
CT + CR + CG
CG + 0V
CG + Fig. 5.1.2 Voltage noise model
1. Part 4, monograph 1: “High gain blocks”. See section 2.
11
CT  CR  CG 1
The noise gain is, therefore: GN  1  
CF F
Note that the noise gain is independent of frequency.
For an LF356 the noise voltage is typically 12nV Hz (RMS) and, with a feedback factor of 0.1, the noise level
at the output would be 132nV Hz .
The current noise model consists of current sources due to the op-amp and the feedback resistor. The action of
feedback (virtual earth) ensures that the net noise current flows only through the feedback capacitor.
IN2
22
CF IN
VOUT
IN1 LF356
CT + CR + CG
CG + 0V
CG + Fig. 5.1.3 Current noise model
The current sources are statistically independent so that the RMS net current flowing through CF is: -
I N  I N2 1  I N2 2
IN
The noise at the output is, therefore: VOUT  (RMS due to noise current)
CF
Note that the noise at the output now depends on the magnitude of the capacitive impedance and, therefore,
frequency. Ideal noise matching occurs when the contributions from the noise voltage and noise current are the
same: -
 C  CR  CG  I VN 1
VN 1  T   N  
 CF  CF I N  CT  CR  CG  CF 
One could interpret this as noise resistance match to the magnitude of the total capacitive impedance connected to
the virtual earth node. In practice the noise current of the feedback resistor dominates and it is not practical to trade
off voltage noise against current noise.
For example: The noise current of a 1GΩ resistor at room temperature (300K) is 4 fA Hz and higher than a
suitable op-amp or matched pair (typically  1 fA Hz ). The impedance of 100pF capacitance at 1.6kHz is 1MΩ
and the contribution to noise at the output is only 40nV Hz . This is less than the contribution due to noise
voltage.
Rule of thumb: One may as well choose a low noise JFET op-amp with a noise resistance a little above the
ideal.
12
Part 5: Monograph 3
5.2 A charge amplifier with long tail pair front end
The best noise performance is achieved by adding a matched pair at the front end of a reasonably low noise op-amp
to make a composite op-amp. Typical values for a dual matched JFET (U430) are: -

1 4 ≈1 (@25ºC) 4×10 -24
4.0 0.07
The extra gain and phase shift of the long tail pair (LTP) can result in instability, depending on the feedback factor.
A snubber (series resistor and capacitor) across the drains may be necessary.
A DC offset trim is included which can correct for up to 15mV of offset. The 100Ω resistor may contribute a small
amount to the noise and a large capacitor (e.g. Tantalum) is added to reduce the AC impedance to 10Ω at 1.6kHz.
Unlike BJT offset trim it is better to keep the drain resistors accurately matched so that, with zero differential
output, the pair are operating at precisely the same current and their characteristics are, therefore, better matched.
Both inputs are maintained at close to 0V so common mode rejection is not an issue and a BJT constant current
source may be a bit of overkill. The balanced structure and current source do, however, also provide a high level of
power supply rejection. With a low noise power supply a JFET based current regulator or even a resistor would
suffice. Otherwise see the monograph “Low noise BJT pre-amplifiers” for more detail.
+15V
100nF
2×RD
CS
VOUT
RS 100k
100k
VIN ≈ 0V
100Ω 0V
2IDS 10μF
100nF
-15V
Fig. 5.2.1 A composite op-amp with a long tail pair
The author found, in a batch of ten, seven single JFETs (low cost, low resistance types J112) with excellent noise
characteristics (typically 5nV Hz ). Two of those had a closely matching pinch-off voltage (10mV difference)
and very closely matching gain characteristic. The models used in text books and application notes are: -
2
 V 
  k VGS  VP 2  k  DSS
I
I DS  I DSS 1  GS
 VP  VP2
The parameter k is the most useful but, unfortunately, it is not provided in data sheets. The values obtained by
linear regression were 7.89 × 10-3 and 7.83 × 10-3 respectively (dimensions: amps/volt2) – a match of about 1%.
Similarly the values of pinch-off voltage were calculated by extrapolation to zero drain-source current.
13
Fig. 5.2.1.1 A batch of J112 JFETs
I DS
The gate-source voltage is: VGS   VP
k
I DS
The forward transconductance is:  2k VGS  VP   2 kIDS
VGS
For low noise the recommended operating current is about 1mA (not critical). The average gate-source voltage
required is, therefore: -
1
VGS   2.056  1.70V
7.86
The gates are operating at about 0V so that the source voltage is +1.7V.
The average forward transconductance is: g FS  2 7.86  106  5.61mS
(This is consistent with the data sheet that states a typical value of 6mS)
To operate well within the pinched-off mode the drain-gate voltage needs to be at least twice the pinch-off voltage.
Five volts should suffice so one can use a pair of 10kΩ drain resistors (0.1% tolerance, scavenged from an old
decade box). The data sheet is not very helpful with drain output resistance (specified as 25μS at 1mA but a drain-
gate voltage of 20V). The effective drain resistance (component resistance in parallel with the drain output
resistance) is, therefore, 20% lower than the actual resistance: -
RDO RD 40k  10k

RDE    8k
RDO  RD 40k  10k
The gain is, therefore, approximately: G  g FS RDE  5.61mS  8k  45
14
Part 5: Monograph 3
A typical application requires, for example, a ground capacitance in the range 100 – 500pF (extra long cable) and,
to retain a reasonably high frequency response, the feedback capacitor is chosen to be 100pF (1% polystyrene,
scavenged from an old capacitive decade box). The feedback factor can be as high as 0.5 (100pF feedback into
100pF ground capacitance) and one needs to reduce the gain, at high frequency, inside the feedback loop by an
extra factor of 22.5 in order to retain stability (feedback factor times the extra gain). To be on the safe side I
reduced the gain by 25 and the snubber resistor needs to be a factor of 12.5 lower than the drain resistors (think of
two snubber resistors in series with the centre connected to +15V). The result is 640Ω and, to be on the safe side
again (it’s not critical), I used a 620Ω as I had plenty in stock.
The main aim of the snubber is to reduce the gain of the long tail pair (LTP) to unity well before the op-amp gain
passes through 0dB. The LF356 has lots of phase margin to spare and experiment (and analysis) shows that the
LTP gain must start to level out to unity at a frequency of one fourth the op-amp unity gain frequency (5MHz).
1
Zero frequency, at which the long tail pair (LTP) gain levels out: f2   1MHz
2RS CS
1
The snubber capacitance needs to be, therefore: CS   260 pF
2RS f 2
Once again this is not critical and a component value of 270pF should be satisfactory.
1
Pole frequency, at which the LTP gain starts to fall: f1   30kHz
2 2 RDCS
This is well above the most frequently used operating frequency (1.6kHz) and the extra open loop gain at low
frequency helps with accuracy and low phase error. The resulting charge amplifier is, in fact, usable up to 16kHz.
Clearly there is scope for experimentation if one uses a different op-amp (e.g. a much higher gain-bandwidth
product) and requires more or less stability margin. For more detail and another example on snubber design and
stability see the monograph “Low noise BJT pre-amplifiers” [1].
For higher frequency of operation (e.g. 1MHz) the op-amp can be replaced by an uncompensated RF amplifier (e.g.
the ubiquitous μA733). To ensure stability the snubber resistor is made much smaller or eliminated altogether so
that the LTP provides the dominant pole. Lower drain resistors and higher operating current ensure bandwidth up
to. Say, 50MHz. The size of the capacitor depends on the feedback factor and some experimentation with stability
margin and layout may be necessary. With modern superfast (internally compensated) op-amps, however, there is
another way…
1. Part 5, monograph 2: “Low noise BJT pre-amplifiers”. See section 4.4.1.
15
5.3 A charge amplifier with source followers.
For the ultimate high speed a charge amplifier can be implemented with a differential source follower and low
noise high speed op-amp. The source followers do not add extra gain inside the loop and loop stability is simply an
issue of feedback factor. The CLC426 (230MHz unity gain and 1.6nV Hz ), for example, has internal
compensation for stable operation with a feedback factor up to 1.
+15V
VIN ≈ 0V
CLC426
VOUT
2×RS
-15V
Fig. 5.3.1 A composite op-amp with source followers
Such a design is not for the faint heart and considerable RF knowledge and understanding is required (plus some
really good test kit, especially the oscilloscope). Also, this is off at a tangent and the reader, if really interested,
should contact the author for further advice.
5.4 An ultra-low leakage charge amplifier
With an adaptive (microcontroller controlled) ultra-low input current pre-amp (see section 4) it should be possible
to construct a very sensitive charge amplifier. The basic idea is to allow the leakage current control loop to
stabilise, with the input disconnected, before switching to measurement mode. In measurement mode the control
loop is disabled, holding the zero leakage condition, and the input is connected via ultra-low leakage (glass
encapsulated) reed relays. The reeds need to be well screened from the activating coils to prevent charge injection.
CF
VOUT
1
Pre-amp 1
s
VC μC
0V
Fig. 5.4.1 An ultra-low leakage charge amplifier
The differential amplifier in the pre-amp can be given a first order low-pass characteristic. Extra gain in the loop is
then provided by a one-plus integrator. This has the same time constant as the diff-amp so that the combined open
loop gain is that of an integrator, equivalent to an op-amp. A second one-plus-integrator may be added, equivalent
to a two-stage high gain block, for higher accuracy [1].
With such a charge amplifier it should be possible to measure average currents as low as a few atto-amps (< 100
electrons/s). If you are interested in building and testing a prototype please contact the author.

16
Part 5: Monograph 3
6. Transducers incorporating a charge amp or single JFET
For the ultimate noise performance the charge amp (or single JFET), feedback capacitor and resistor can be
incorporated within the transducer (or physically close) to minimise ground capacitance [1]. Noise current becomes
an issue and the feedback resistor needs to be very large (typically > 1GΩ). Care must be taken to keep the op-amp
or JFET cool as leakage current doubles for every 11 degrees. Current noise increases in proportion to I L .
A surface mount style op-amp takes up little space and presents no interfacing problems as the output impedance is
very low.
Virtual earth
+/-15V supply
sensor electrode
output
JFET op-amp
active guard
guard screen (0V)
Epoxy resin earthed screen/casing

Fig. 6.1 A variable gap transducer with built-in charge amplifier [1]
The drain output of a single JFET in pinched-off mode, on the other hand, presents much higher impedance and an
active guard (driven coax screen) is recommended.
The best solution is to operate the JFETs in voltage controlled resistor (VCR) mode with leakage current control.
This mode eliminates the need for a high value resistor. The on resistance is typically 50Ω and interference ceases
to be a problem. Such a design, however, would require a very low noise stage to follow and the cascode circuit is
recommended. See section 4.
Screen
VIN C
Pre-amp
VOUT
Fig.6.2 A single JFET in VCR mode in a special high-pass filter [2]
In a null-balance bridge system it is also possible to eliminate the feedback capacitor (i.e. not a charge amplifier).
The bridge can still be balanced to a null though the gain of the pre-amp stage is less well defined due to the stray
capacitance unless the screen is actively driven. Once again, the special high-pass filter circuit is recommended [2].
For further advice please contact the author.
1. Part 1, monograph 5: “Variable gap capacitive displacement transducers”. See, for example, section 2.1.
2. Part 2, monograph 3: “An ultra-high input impedance high-pass filter”.
17
Appendix: Long tail pair theory
A1. Voltage gain
The analysis is simplified if one takes advantage of the symmetry of the circuit. Consider equal and opposite
infinitesimal changes to the inputs. The increase in current down one side is matched by a decrease in the other and
the source voltages remain constant. The gain must be the same if one of the inputs is held constant (e.g. in a
charge amplifier one input is connected to 0V).
+15V
2×RD
±dVD
+dIDS -dIDS VOUT
+dVG
-dVG
VS
Current regulator 2IDS
-15V
Fig. A1.1 Model for gain calculation
By definition, in the pinched-off mode: -
dVDG
dI DS  g FS dVGS  with dVS  0  dVGS  dVG  dVS  dVG and dVDG  dVD  dVG
RDO
g FS  Forward transconductance and RDO  drain output resistance (reciprocal of output conductance)
dVD  dVG
 dI DS  g FS dVG 
RDO
RD dI DS  dVG
By Ohm’s law: dVD   RD dI DS  dI DS  g FS dVG 
RDO
With a little algebra: -
 R  dV g FS RDO dVG  dVG
 1  D dI DS  g FS dVG  G  dI DS 
 RDO  RDO RDO  RD
dVOUT dVD R dI g R R  RD RD
The voltage gain is:    D DS   FS DO D   g FS RDE 
dVIN dVG dVG RDO  RD RDO  RD
RDO RD
RDE   Effective drain resistance (RD in parallel with RDO)
RDO  RD
RD
Usually: g FS RDE  1 and  1  G  g FS RDE
RDO  RD
18
Part 5: Monograph 3
A2. Common mode rejection ratio
A2.1 Mismatched drain resistors
If one increases the voltage at both inputs dVG  and the total current remains constant then the voltage, VS, at the
current source increases by the same amount. In practice the current source has a finite output conductance,
equivalent to a large resistor, ROS, in parallel with an ideal current source. The current will change by a small
amount and there is a very small difference between dVG and dVS: -
dVS dVG
dI  and dVS  dVG  dI 
ROS ROS
If one assumes that the JFET pair are perfectly matched then the change in current is shared equally. If the
resistances are exactly the same the result is a change in the output common mode but not the difference. The
resistors have a tolerance RD  RD  , however, and, in the worst case (one resistor higher and the other lower than
nominal), the difference between the outputs would change by: -
dI dVG
RD  RD  dVOUT  2RD  RD
2 ROS
The differential gain is, approximately (see previous section): G  g FS RDE
The CMRR is usually defined as the differential gain divided by the common mode gain. To a good approximation,
therefore: -
dVOUT R
G  g FS RDE  OS
dVG RD
The effective drain resistance is usually not much lower than the drain resistor (component) and, therefore: -
RD
RDE  RD  CMRR  g FS ROS 
RD
At a relatively high operating current (1 – 10mA) the forward transconductance is at least 1 - 10 mmho (milli-
Siemens) and a typical output resistance of a BJT current source is at least 10 7Ω. The common mode rejection ratio
is, therefore, a minimum 106 (120dB) with 1% tolerance resistors.
A2.2 Mismatched JFETs
In practice the CMRR is limited by the matching of the JFETs. The effect of an infinitesimal change in drain
voltage is negligible (second order) and to a very good approximation, therefore: -
dVDG
dI DS  g FS dVGS   g FS dVGS
RDO
The change in current is the same but the balance is altered slightly by the mismatch in JFETs.
dVS
dI   dI1  dI 2 with dI1  g FS 1dVGS and dI 2  g FS 2dVGS
ROS
The changes in current are very nearly the same: -
dVS dVS
dI1  dI 2 and dI   dVGS 
ROS 2 g FS ROS
19
The change in gate-source voltage is very much less than the change in gate voltage (the source voltage “follows”
the gate common mode). The change in the output is: -
RD g FS
dVOUT  RD (dI1  dI 2 )  RD g FS dVGS  dVS
2 g FS ROS
dVOUT R g
The common mode gain is, therefore: dVS  dVG   D FS
dVG 2 g FS ROS
The CMMR is usually defined as the differential gain divided by the common mode gain: -
dVOUT 2g R
G  g FS RDE  FS OS
dVG g FS RD
The effective drain resistance is usually not much lower than the drain resistor (component): -
g FS
RDE  RD  CMRR  2 g FS ROS 
g FS
As before the product g FS ROS  104 and a mismatch of no more than 1 or 2% is possible so that a CMRR of 106
(120dB) is readily obtained.
With charge amplifiers both inputs are firmly anchored at local PSU 0V and a high CMRR is usually overkill – a
JFET current regulator or resistor to supply the current is usually sufficient.
The matched pair (U430) datasheet quotes the following, re: matching: -
20
Part 5: Monograph 3
A3. The long-tail pair in VCR mode
With suitable drain resistors and operating current it is possible to operate in the voltage controlled resistor mode.
One possible application is an ultra-low leakage current amplifier (see section 4), with drain and source voltages
equal and opposite, relative to the inputs (0V). The main difference, compared to the differential cascode
recommended there, is a much lower voltage gain, requiring the following stage to have a very low voltage noise
and low noise resistance (i.e. a noise matching transformer [1]).
Here again one can take advantage of the circuit symmetry. Consider equal and opposite changes at the inputs.
+15V
2×RD
+dIDS ±dVD -dIDS VOUT
+dVG
-dVG
VS
RD/2
2IDS
-15V
According to theory the drain source resistance is [2]: -
 VP  dVG RDS
VD  VS  0V  RDS  R0    dRDS  R0VP  dV
 VP  VG  VP  VG  VP  VG G
2
R0
At VG  0 , therefore:  dRDS  dVG (N.B. VP is numerically negative)
VP
The current remains approximately constant, being determined mainly by the power supply voltage and the drain
resistance.
V
RD  RDS and VD  VS  0V  I DS 
RD
The change in drain voltage is determined, therefore, almost entirely due to the change in drain-source resistance: -
dVD I DS dRDS I DS R0
G  
dVG dVG VP
With a typical RDS resistance of 50Ω and pinch-off voltage of -2V and an operating current of 2mA (c.f. example
calculation, section 4.1) the gain is: -
G  0.05

2. Part 5, monograph 4: “JFET theory”. See section 2.5
21
Part 6: monograph 3
A circuit for measuring tanδ

1. Introduction
The ideal capacitor has purely negative imaginary impedance. In practice, however, even high quality polymer
dielectric capacitors have impedance with a real part, which can be modelled as a small series resistance, which
varies with frequency [1]: -
C RS 1
Z  RS 
jC
Fig. 1.1 Equivalent circuit for a practical capacitor
The ratio of the real part to the imaginary part is known as the “tanδ”: the tangent of the acute angle to the negative
imaginary axis of the complex number which represents the impedance. The angle is very small so that, to a very
good approximation (in radians): -
tan   RS C  
Imaginary axis
R
RS
Real axis
j
Z
C
Fig. 1.2 The complex representation of a capacitor (real part exaggerated)
Fig. 1.3 Tanδ for polypropylene dielectric capacitors (courtesy EPCOS AG 2015 [2])
At low frequency the angle is constant and one can employ the concept of a complex capacitance [1]: -
 1  j C
constant   RS C  RS   Z  C
C jC 1  j 
1. Part 1, monograph 6: “Low phase error capacitors and inductors”.

2. Film Capacitors: General technical information, Sept 2015. See section 2.3.2.
1
1.1 The general complex representation
For this analysis I shall use the general complex representation of a sinusoid ( s    j ) where the real part
represents either an exponentially growing (  positive) or exponentially decaying (  negative) sinusoid: -
VOUT  VP e st with s    j
 VOUT  VP et e jt
The time constant  D of the decaying sine wave is related to  . This is easily seen if one expresses the decaying
sinusoid in the usual form, with a numerically positive time constant: -
 t 
VOUT  VP et e jt  VP exp    exp  jt 
 D 
1
  
D
Fig. 1.1.1 An exponentially decaying sine wave (i.e. the real part)
V  exp  10t sin100t 
 D  0.1s and   100 rads-1
2
Part 6: monograph 3
2. A practical circuit
With good quality polymer capacitors the tan(δ) is so small that it is difficult to measure with conventional circuits.
One solution is to construct a pair of integrators and an inverter with high gain blocks (HGBs) and provide positive
feedback so that it is borderline stable.
The open loop gain of each HGB is so high that the closed loop phase error is negligible, compared to the effect of
tan(δ) [1 and 2].
With capacitor C3 set to zero it is easy to get the circuit oscillating with a short impulse current into one of the
virtual earths. The oscillation dies away slowly. The time constant of the exponential decay is related to the average
tan(δ) of the integrator capacitors. Alternatively, the addition of a small adjustable capacitor, C3, adds a small phase
lag to the inverter. This is increased until the circuit just bursts into oscillation. This condition represents a total
phase shift around the loop of precisely 360 degrees and a gain (magnitude) of one at the frequency of oscillation
(the “Barkhausen criterion” for oscillators [3]). The average tan(δ) can then be calculated from the resonant
frequency, C3 and R4 as the following demonstrates.
C3
R4 C1 C2
R3 R1 R2
VOUT
HGB1 HGB2 HGB3

0V
Fig. 2.1 A borderline oscillator circuit (BOC) for measuring tanδ
2.1 Analysis of the borderline oscillator circuit (BOC)
I shall assume the following: -
a) The inverter has a small (DC) gain error (use ±1% or matched resistors): gain G   R4 R3
b) All resistors have negligible phase error. It is recommended that stray capacitance at the virtual earths is kept
small and low to medium value resistances are used (< 10kΩ).
c) The feedback capacitors can be described as complex capacitors.
The open loop gain consists of the inverter/low pass filter (HGB1) with phase shift  3  R4C3 and two integrators
(HGB2 and HGB3) with small phase errors 1 and  2 respectively [4]. The open loop transfer function is: -
 1  j1   1  j 2  G1  j1 1  j 2 

Ls  
G
   with  3  R4C3
1  sR4C3 sR1C1 sR1C2 1  j 3 s 2 R1C1R2C2

3. http://en.wikipedia.org/wiki/Barkhausen_stability_criterion
4. Part 1, monograph 6: “Low phase error capacitors and inductors”.
3
All three phase errors are very small so that, to a good approximation: -
G1  j1 1  j 2 1  j 3  G1  j 1   2   3 

Ls   
s 2 R1C1R2C1 s 2 R1C1R2C1
The output is connected to the input: -
Ls VOUT  VOUT  VOUT  0 or Ls   1
G
Clearly the latter represents the case from which one can deduce: s j  1  j 1   2   3 
R1C1R2C2
For sustained oscillation the real part of s must be zero and, therefore:  3  1   2
The average δ of the two capacitors is then easily calculated from the critical value of capacitance which just
sustains oscillation: -
1   2 R R4C3 G
 AVE   with R 
2 2 R1C1R2C2
If, on the other hand, the extra capacitance is removed the result, when triggered, is an exponentially decaying sine
wave, represented by a value of s with a (negative) real component. To a good approximation: -
C3  0  s  j
G     2  
 1  j 1 
R1C1R2C2  2 
One can separate out the real and imaginary parts to obtain: -
G
s    j   AVE R  jR with R 
R1C1R2C2
From the real part one can deduce δAVE: -

   AVE R   AVE  
R
The time constant  D of the decaying sine wave is related to  . This is easily seen if one expresses the decaying
sine wave in the usual form, with a numerically positive time constant: -
 t 
VOUT  VP et e jt  VP exp    exp  jt 
 D 
1 1
    AVE 
D  DR
A practical method is counting the number, n, of cycles taken for the amplitude to fall by a factor 1/e: -
1 2 2n
The period of each cycle is: T    D  nT 
f R R R
1
From which the solution is:  AVE 
2n
4
Part 6: monograph 3
2.2 Results (sustained oscillation method)
(See log book: test data from 24 March 2011).
R3 = R4 = 4k7 ±5% (G = -1 ± 10%) C3 = 140pF ±5% Measured frequency: 3330Hz
Check the frequency. Both R1 =R2 = RI = 4k7 ±5%; C1 = C2 = CI = 10nF ±10% (Polyester): -
1 1
fR    3386 Hz
2RI CI 2  4.7 103 108
From above:  AVE  f R R4C3  3.14  3330  4.7  103  140  1012  6.9  103  10%
Clearly it would be possible to reduce the uncertainty by measuring all component values with greater precision.
Fig. 2.2.1 Borderline oscillator with C3 = 0
2.3 Results (decaying sinusoid method)
From fig. 2.1.1 count from where the amplitude is 10V (peak) to 3.7V (peak): n = 25±1
1
From above:  AVE 
2n
1
The result is:  AVE   6.4  103  4%
50
5
3. Some nice maths
Whereas the method above is simple and valid for low values of tan(δ) an exact analysis is possible if one converts
the transfer functions into polar form. An alternative representation of the impedance of a real capacitor is, for
example: -
ZC 
1
 RS 
1
1  jRS CI   1  j tan 
jC jCI jCI
cos   j sin  
Now 1  j tan   exp  j   ZC  exp  j 
1 1

cos  cos  jCI cos 
The transfer function for each integrator in polar form is, therefore, of the form: -
1
TI     exp  j 
ZC

RI RI CI cos 
Similarly, the inverter/low pass filter has the following transfer function (by definition G is negative): -
TLP     G cos  F exp  j F 

G G

1  jR4C3 1  j tan  F
The loop gain is: -
G cos  F
L   TI 1  TI 2  TLP  exp  j1   2   F 
 R1R2C1C2 cos 1 cos  2
2
For borderline/sustained oscillation the net phase shift is zero (modulo 360 degrees) and, therefore: -
 F  1   2
The average phase error due to the integrator capacitors is, therefore: -
1   2
 arctan R R4C3 
1
 AVE 
2 2
For the circuit to oscillate the magnitude of L  must be one at the resonant frequency: -
G cos  F
L   1  R 
R1R2C1C2 cos 1 cos  2
If one assumes that the capacitors have the same phase error,  C , then  F  2 C and cos  F  cos 2 C
From a well known trigonometric identity cos 2 C  cos 2  C  sin 2  C and so the exact solution, based on the
assumptions, simplifies to: -
R 
G
R1R2C1C2

1  tan 2  C 
6
Part 6: monograph 3
4. A prototype
To variable C3
C2 = 10nF
HGB1
C1 = 10nF
HGB2
HGB3
Fig. 4.1 Strip-board prototype borderline oscillator circuit
7
A two-stage HGB (type 2) based on a LF353 dual op-amp is sufficient for this applications. Each was adjusted for
stability as an inverting amplifier (Gain = -1) with a high frequency square wave test signal. The trimpot was
adjusted for ≈10% overshoot (ample stability at about 25% (k = 0.25)).
½LF353 ½LF353
VE VOUT
V1
k
4k7 0V
0V
Fig. 4.2 A two-stage HGB (type 2)
I shall assume that the operational amplifiers are ideal integrators with a gain bandwidth product (GBWP) of
1
fB   4MHz for an LF353 [1].
2 B
For the circuit fig. 4.2: V1  

k
VE with k  0.25 and VOUT 
1
V1  VE 
 Bs  Bs
1  1
In a form normalised to the OPI time constant s  j B k  H s   
VOUT
  1  
VE ks  s 
This is a type 2 HGB with:  2   B  4  108 s and 1   B k  1.6  107 s
TN s    DN s 
Z2
The closed loop transfer function is [2]:
Z1
Where the “D” factor for the amplifier/filter is [3]: -  I  RI CI  4.7  105 s
2 3
 f   f  2
D2 s   1      j  
R
with    k  0.25 and   1  2  2
 f1   f1  1 R1
The frequency f1 corresponds to the time constant  1 (i.e. 1MHz). For the integrators it is very similar [4]: -
 f 
2

 f 
3
 f  
D2  f   1     j       with    1  1
 f1    f1  I
 1 
f

1
At 3kHz the ratios are: f f1  3  103 and     2.1  10 4 so that the errors are negligible [5]
I
1. Part 4, monograph 1: “High gain blocks”. See section 2.2

2. Part 4, monograph 3: High accuracy inverting amps, integrators and differentiators”. See section 2.
3. Ibid. See section 3.
4. Ibid. See section 4.
5. Ibid. See section 4.2
8
Part 6: monograph 3
5. A voltage controlled high Q filter/oscillator
The borderline oscillator circuit could form the basis of a very high Q band-pass filter or accurate two-phase
oscillator. Such a circuit could prove useful, for example, as part of a very sensitive null detector for the most
demanding bridge applications. The usual approach is to incorporate notch filters at 50Hz and 150Hz and a band-
pass filter at the bridge operating frequency (nominally 25Hz or 75Hz, also known as the “carrier” frequency). The
effectiveness of the filtering is limited by the fact that the supply frequency varies, albeit by a small amount,
limiting the quality factor of the notch filters. The carrier frequency is usually phase locked to the supply and also
varies, limiting the quality factor of the band pass filter. The following provides a different approach – a band pass
filter with adjustable frequency and quality factor, which can be operated at a much higher quality factor. The
bridge balancing algorithm is more complicated but higher levels of interference could be tolerated. The basic idea
is to use a pair of multipliers to adjust the feedback and control the resonant frequency and quality factor/gain in a
way that is largely independent. The multipliers could be analogue or R-2R type multiplying digital to analogue
converters. If you are interested in constructing/testing a prototype please contact the author.
R
VOUT
VO Rω
VC1
CQ
R I
VC2
VIN V1
Multipliers
CIN
e.g. AD534
HGB1
0V
Fig. 5.1 Modified inverter stage for voltage control of resonant frequency and quality factor
5.1 Analysis of the modified inverter
The basic principle of the circuit is to vary the gain and phase shift of the inverter by a small amount. An additional
input is also provided in the case of the band-pass filter. The result is a voltage controlled band pass filter, as the
following analysis shows: -
VC1  VOUT
The output of the analogue multiplier is typically: VO  etc.
10
According to Ohm’s law and Kirchhoff’s law in the complex representation s  j  : -
VOUT VC1 VOUT VC 2 V

I   VOUT sCQ  VIN sCIN   1
R 10 R 10 R
Multiply by R and collect terms: -
 V R VC 2 
VOUT 1  C1  sRCQ   V1  VIN sRCIN
 10V R 10V 
9
Assume two identical integrators so that: -
2 2
 1  sRS CI   sRI CI 
VOUT  V1     V1  VOUT   
 sRI CI   1  sRS CI 
With which one can eliminate V1: -
 V R VC 2 s 2 RI2CI2 
VOUT 1  C1  sRCQ    V sRC  0
 10 R 10 1  sRS CI 2  IN IN
Simplify the algebra by defining parameters: -
VC1 R VC 2 tan 
  RCQ  I  RI CI  IN  RC IN and    RS CI 
10 R 10 
  I2 s 2 
VOUT 1    s  2 
 VIN IN s  0
 1    s  
Multiply by 1    s  and rearrange for the transfer function: -

2
 IN s1    s  2
T s  
VOUT
 2 2
VIN  I s  1    s 1    s 2
For very low frequencies and around the resonant frequency this is very nearly the ideal transfer function for a
second order band pass filter, which one can see more clearly with the following approximations. I shall assume
   
small tanδ   s  1 and a small frequency adjustment range   1 but allow the possibility of low quality
 
factor  Q s  1 : -
  s 1  1    s 2  1  2  s
Qs  1 and  1  1    s 1  2  s   1      2  s  2 Q  s 2

The transfer function is more recognisable: -
  IN s1  2  s 
T s  
 
    s 2    2  s  1  
2
I
The factor 1 2  s  in the numerator represents a small phase shift which is negligible compared to the phase shift
of the filter itself. Divide top and bottom by 1    to obtain the standard form: -
 IN s

T s   2
1     2 2
 G N s
 I     s 2    2   s  1  N s  2 N s  1
1    1
N 
1

1   
The natural frequency is:
N  2
I    
10
Part 6: monograph 3
The natural frequency is largely adjusted by control parameter  : -
    I2   N 
1   
I
For small variations the control is linear so that, to a good approximation with frequency in Hz: -
1  
  1  fN  1  
2RI CI  2 
The deviation in natural frequency from the nominal is, therefore: -
VC1 R
f N  fN
20 R
The damping ratio can be deduced from: 2 N 

  2   N.B. The quality factor is: Q 
1
1 2
This time the main control parameter is  and the effect of  is small and so, at the resonant frequency, to a good
approximation: -
 2 
  2    VC 2  RCQ  2 tan  noting that

 N RS CI  tan 
N 10 RI CI N
If the control voltage VC 2 is set to zero the damping ratio is simply the tanδ of the integrator capacitors and one has
the borderline oscillator circuit. The control voltage can be negative and so the damping ratio can be controlled all
the way down to zero (infinite Q) and the circuit oscillates. The upper limit is determined by the component values.
At the resonant frequency the gain depends on the damping ratio (i.e. is controlled by VC2) with no upper limit: -
T  N   
G
2
The factor, G, can be deduced from the numerator: -
 IN  IN 1   RC IN RC IN
G N   G   
1     N 1    RI CI 1    RI CI 1  
Once again the effect of small  is small and so, to a good approximation: -
RC IN
G
RI CI
The analysis shows that one can control the resonant frequency and damping ratio (gain) largely independently but
there is a small degree of interaction possibly requiring a number of iterations. The (in-phase) test signal is applied
and the output of the in-phase and quadrature detectors monitored. The damping ratio (i.e. Q) is first set to the
required level of sensitivity and then the resonant frequency is adjusted so that the output of the quad detector is
zero.
For a dual phase oscillator it is recommended that a continuous amplitude control is applied to the damping ratio.
Consult the author for further advice.
11
6. Compensating for tanδ
It should be possible, in principle, to compensate for the phase error of a capacitor at least to the level of it being
reproducible and stable. This is another possible project – contact the author if you require further advice.
In this case it is more convenient to model the capacitor with a large parallel resistance.
RP  1 sCI 1  1  1  1  j RPCI 
The impedance of the parallel combination is: Z      
2 2 2 
RP  1 sCI sCI  1  1 sRPCI  sCI  1  1  RPCI 
1
From which the precise result is: tan  
RPCI
The phase error is constant over the low to medium frequency range so that the equivalent parallel resistance is
inversely proportional to frequency: -
1
RP 
CI tan 
One can, therefore, compensate for the equivalent resistance by injecting a current through a compensating resistor
with an inverting amplifier.
RC
R2
RP
CI V1
RI R1
VIN V2
0V
Fig. 6.1 Compensating for tanδ
The gain of the amplifier needs to be varied as the operating frequency is changed.
V1 V2 V2 V2 V1
I  0  RC   RP 
RP RC V1 CI tan 
Once a suitably large compensating resistor is chosen the gain of the inverting amplifier can be calculated: -
R2
G  RC CI tan 
R1
In practice one could adjust the compensation to achieve sustained oscillation in a borderline oscillator
configuration (see fig. 2.1 with C3 = 0) after which one can be confident that each integrator provides precisely 90
degrees phase shift at that frequency.
12
Part 6: Monograph 1
A simulated large capacitor circuit

1. Introduction
This ingenious circuit was developed by JDY in the 1980s, based, probably, on an original idea by Robert
Cutkosky of NBS [1]. JDY gave it this name because it behaves, at the operating frequency, like a very large
capacitor. A better model, over the frequency range of interest, is a large capacitor in parallel with a resistor.
The main application is to improve the stability of an actively driven multi-stage IVD or ratio transformer: -
VIN
Compensator
Fig. 1.1 A simulated capacitor application (An F18 type ratio transformer [2]).
V1 R2 I2
VIN I3
VOUT
I1
Load, ZL
I1
R1
V2 C
0V
Fig. 1.2 A simulated large capacitor circuit
At very low frequency the capacitor has high impedance, compared to R1, and the circuit is a voltage follower
with 100% feedback via R1 (V1 = VIN). Resistor, R2, is then in series with the output and the load impedance.
At high frequency the capacitor has low impedance, compared to R1, and provides 100% feedback from VOUT.
This time the follower action is to make VOUT = VIN.
Over the full range of frequency the circuit behaves like series impedance, ZE: the resistor, R2, in parallel with a
large capacitor, CE: -
ZE
R2
VIN VOUT
CE
Fig.1.3 The equivalent circuit
1. National Bureau of Standards (NBS) is now known as The National Institute for Science and
Technology (NIST). Ref. required.
2. Part3, monograph 7: “An F18 type ratio transformer bridge”.
1
It is argued elsewhere that, for stability, the resistance, R2, needs to be of the same order (very approximately) as
the maximum source resistance and the natural (cross-over) frequency of the compensator needs to be the same
as the natural frequency of the ratio transformer [1]. Typical values are, therefore: -
R2  100 f N  0.16Hz N  1rads1   R1  R2 C  1  R1  1M and C  1F
The equivalent capacitance is: CE  10mF
This is far too large for a component capacitor, hence the need for a simulated capacitor.
Fig. 2.1 Magnitude of a typical compensator vs frequency
2. Basic analysis
If one assumes an ideal op-amp the action of feedback is to make the inverting input the same as the non-
inverting input. Also, according to Ohm’s and Kirchhoff’s laws, referring to fig. 1.2, in the complex
V1  VIN V V
 sCVIN  VOUT  I 2  1 OUT
VOUT
V2  VIN  I1  and I1  I 2  I 3 
R1 R2 ZL
Combine the three and switch to admittances where possible to simplify the algebra (maximum double-decker
equations):-
ALVOUT  sCVIN  VOUT   A2 V1  VOUT  with AL 
1 1
and A2 
ZL R2
We can eliminate V 1 using the first equation with: A1V1  A1VIN  sCVIN  sCVOUT
 ALVOUT  sCVIN  sCVOUT  A2VIN  A2 R1sCVIN  A2 R1sCVOUT  A2VOUT
1. Part 3, monograph 4: “Three-stage RTs” See section 3.
2
Part 6: Monograph 1
Re-arrange to find: VOUT  AL  sC  A2 R1sC  A2   VIN sC  A2  A2 R1sC 
VIN  VOUT V  VOUT AL

We are expecting an equation of the form:  Z E or IN 
I3 VOUT AE
1
Where ZE is the equivalent impedance and AE  is the equivalent admittance of the circuit. With a little
ZE
algebra: -
VIN A AL
1  L 
VOUT AE sC  A2  A2 R1sC
From which it is easy to see that the equivalent admittance is: -
AE  A2  1 A2 R1 sC
 R 
This is the admittance of R2 in parallel with a capacitor, CE, with: CE  1  1 C QED.
 R2 
The reciprocal is: -
R2 1
ZE  with natural frequency fN 
1  R1  R2 sC 2 R1  R2 C
3. Errors due to limited gain-bandwidth product
The accuracy of the circuit depends on the gain-bandwidth product of the op-amp. The analysis is a bit
complicated and is relegated to appendix 1. The full expression for the equivalent impedance, referring to fig.
1.2 is, to a very good approximation: -

ZE 
1
1 
1
1  A2 Z L 1  sR1C 
1  A2 R1 sC  A2  H s  
H s  is the open loop characteristic of the op-amp (or high gain block).
For the main application the load impedance is an energising winding: inductance in series with a small resistor,
which is usually much smaller than R2. A good approximation is, therefore: -
RL R  sL L
 1  1  A2 Z L  1  L  1   L s with  L 
R2 R2 R2
1
Similarly, the time constant  N  R1C corresponds, very nearly, to the natural frequency: f N 
2 R1  R2 C
We are primarily interested in the low frequency characteristics, including the maximum “DC” gain of the op-
amp. The low frequency model (high gain low-pass filter) is appropriate [1]. The equation for the impedance
takes the elegant form: -
 
H s   1  1   L s 1   N s 1   P s 
G 1 1
 ZE 
1   Ps 1  A2 R1 sC  A2  G 
1. Part 4, monograph 1: “High gain blocks” See section 3.1
3
Typical values of the time constants (for a three-stage ratio transformer compensator) are: -
L 5.4 H
Load:  L    54ms Natural frequency:  N  R1C  1M  1F  1s
R2 100
The dominant pole of an op-amp corresponds to the frequency at which the gain starts to drop  f P  50Hz  : -
1
P   3.2ms with open loop “DC” gain: G  105
2f P
The magnitude error increases with frequency starting from the lowest level determined by the op-amp “DC”
gain.

Fig. 3.1 Magnitude error for typical values log10 Ds   1 
Fig. 3.2 Phase error for typical values arg Ds 
4
Part 6: Monograph 1
4. Practical considerations
At high frequency, with an inductive load, the feedback factor is 100% with the usual resonant peak at the unity
gain frequency [1] (See section 3.1.1). Even a small parallel load capacitance (e.g. 100pF of interwinding
capacitance) would interact with the series resistance, R2, to add extra phase shift and reduce stability margin.
Fortunately this is easily fixed with a snubber (R and C in series) in parallel with the load. Typical values are
100nF and 10Ω. As frequency increases (above 160kHz) the load presents a high impedance and the snubber
resistance dominates. The feedback factor drops to 10%.
V1 100Ω Snubber
VIN
100nF
Load, ZL
10Ω
1μF
0V
Fig. 4.1 High frequency model (typical values)
At lower frequency the snubber capacitance dominates and the load looks partly capacitive. The equivalent
capacitance, CE, is much larger than the load capacitance and the result is a slightly reduced energising voltage.
A small error in the energising voltage has a much reduced effect on the main ratio accuracy, especially with a
three-stage transformer [2].
ZE
R2
VIN
CE >> CS ZL
0V
Fig. 4.2 Low frequency model
At very low frequency the parallel resistance, R2, dominates but the load looks like a very small resistor. The
snubber capacitance then presents very high impedance and, again, the effect is negligible.
The complete circuit does not warrant detailed modelling as the frequencies of interest, and impedances, are so
widely separated. See appendix 2.
One may also ask if it is worth increasing the open loop gain with, for example, a two-stage high gain block
(e.g. a type 3 HGB would provide a high input impedance) [1] (see section 4.3). In practice any errors
(magnitude and phase or noise) introduced via energising windings are much reduced and have negligible effect
on the accuracy of the ratio windings [2]. If necessary one could employ a composite op-amp with, for example,
a matched BJT or JFET pair [3]. The extra stage not only boosts open loop gain at low frequency but also
improves noise performance.
In practice accuracy is limited by common mode rejection ratio and, for very high accuracy, it is necessary to
bootstrap the power supply.

2. Part 3, monograph 3: “Two-stage IVDs and RTs”. See section 4.2.4
3. Part 5, monographs 2 &3: “Low noise BJT preamps” and “Low noise JFET preamps”
5
Appendix 1: Error analysis (due to limited gain-bandwidth product)
V1 R2 I2
VIN I3
VOUT
I1
Load, ZL
I1
R1
V2 C
0V
Fig. 1.2 A simulated large capacitor circuit (repeated for convenience)
According to Ohm’s and Kirchhoff’s laws, in the complex representation s  j  : -
I1  A1 V1  V2   sCV2  VOUT  I 2  A2 V1  VOUT  and I1  I 2  I3  ALVOUT
 ALVOUT  sCV2  sCVOUT  A2V1  A2VOUT
The output of the op-amp is: V1  H s VIN  V2 
 ALVOUT  sCV2  sCVOUT  A2 H s VIN  A2 H s V2   A2VOUT
The changes are shown in curly brackets for easy checking.
We can eliminate V2 with: I1  A1H s VIN  A1H s V2   A1V2  sCV2  sCVOUT
 V2 sC  A1H s   A1   A1H s VIN  sCVOUT
1
Introduce impedance parameter Z to simplify the algebra: Z 
sC  A1H s   A1
 V2  A1H s ZVIN  sCZVOUT


ALVOUT  sCA1H s ZVIN  s 2C 2 ZVOUT 

 sCVOUT  A2 H s VIN  A2 A1H 2 s ZVIN  A2 H s sCZVOUT  A2VOUT 
Re-arrange to find: -
VOUT
VIN
 
AL  s 2C 2 Z  sC  A2 H s sCZ  A2  sCA1H s Z  A2 H s   A2 A1H 2 s Z
VIN A A  s 2C 2 Z  sC  A2 H s sCZ  A2  sCA1H s Z  A2 H s   A2 A1H 2 s Z

1  L  L
VOUT AE sCA1H s Z  A2 H s   A2 A1H 2 s Z
It is tempting here to employ the approximation A1H s Z  1but that could be a mistake. The difference
between the two largest elements is, for example: -
 
A2 H s   A2 A1H 2 s Z  A2 H s sC  A1H s   A1   A2 A1H 2 s  Z  A2 H s sC  A1 Z
6
Part 6: Monograph 1
Similarly, three other terms afford some simplification: -
 
 s 2C 2 Z  sC  sCA1H s Z   s 2C 2  sCsC  A1H s   A1   sCA1H s  Z  sCA1Z
With these substitutions things are looking better: -
AL AL  A2 H s sCZ  A2  sCA1Z  A2 H s sC  A1 Z


AE sCA1H s Z  A2 H s sC  A1 Z
Another pair of terms now cancel: A2 H s sCZ  A2 H s sC  A1 Z   A2 H s  A1 Z
AL AL  A2  sCA1 Z  A2 H s  A1 Z
 
Finally one has: -
A2  A2 H s  A1 Z  A2 sC  A1H s   A1   A2 H s  A1 Z  A2 sC  A1 Z
AL AL  A2 sC  A1 Z  sCA1 Z
 
AL AL   A2  A1 sCZ  A2 A1Z
 
AE  A2  A1 sCH s Z  A2 A1H s Z
All terms now add and one can safely assume the approximation. In the limit that H s  tends to infinity one
obtains the result in section 2 - a useful check on the algebra so far: -
H s    then Z  0 and A1H s Z  1 

AL AL

AE 1  A2 R1 sC  A2
Take out a factor AL from the numerator: -
 Z L  AL   A2  A1 sCZ  A2 A1Z  AL 1   A2  A1 sCZL Z  A2 A1Z L Z 

1
AL
For the denominator take out a factor A1H s Z : 1  A2 R1 sC  A2 A1H s Z
The impedance is, therefore: -
 
1   A2  A1 sCZ L Z  A2 A1Z L Z 
1 1 1
 ZE  
AE 1  A2 R1 sC  A2  A1H s Z 
The first item is the ideal expression for the impedance and the terms in brackets are correction factors, both
with magnitudes approximating 1 at low frequency. Introduce the deviation factor Ds  : -
Ds 
1
ZE 
1  A2 R1 sC  A2
with: Ds  
1  A  A1 sCZ L  A2 A1Z L
 2
A1H s Z A1H s 
7
 sC  A1H s   A1
1
From above one has:
Z
sC  A1   A2  A1 sCZ L  A2 A1Z L
 Ds   1 
A1H s 
In most cases one can assume a very good approximation: -
1  sR1C  Z L A2 sR1C  Z L A2
A2  A1  Ds   1 
H s 
The error term factorises to something simple: -
Ds   1  1  A2 Z L 1  sR1C 

1
H s 
The load impedance is usually inductance in series with a winding resistance, RL, which is much smaller than
R2. A good approximation is, therefore: -
RL R  sL L
 1  1  A2 Z L  1  L  1   L s with  L 
R2 R2 R2
1
Similarly the time constant  N  R1C corresponds, very nearly, to the natural frequency: f N 
2 R1  R2 C
We are primarily interested in the low frequency characteristics, including the “DC” gain of the op-amp. The
low frequency model (high gain low-pass filter) is appropriate. The equation for the impedance then takes the
elegant form: -
 
H s    Ds   1  1   L s 1   N s 1   P s 
G 1
1   Ps  G 
Appendix 2: Snubber example calculations

 10  0.3 j  and the snubber
1
Unity gain frequency (typically 5MHz): B  3.14  107  RS 
jBCS
1
resistance dominates. The impedance of the load capacitance (100pF) is much larger:  320
 BCL
At the lowest operating frequency (25Hz) the compensator capacitance (10mF) has low impedance compared to
1
the parallel resistance (100Ω): O  157   1.57
OCE
At very low frequency   10 the snubber capacitance has very high impedance
1
 1M and has
CS
negligible effect on the circuit.
1
At the highest operating frequency (160Hz): O  103  L  5k and  10k is comparable but
CS
1
 0.1 and the result is a small (10ppm in-phase) error in the energising voltage and negligible.
CE
8
Part 6: Monograph 2
A simulated negative capacitor circuit

1. Introduction
An actively driven three stage ratio transformer (e.g. of the F18 type) has, potentially, a very high input impedance,
capable of high accuracy even with a significant source resistance. In practice, however, the interwinding
capacitance sets an upper limit which, at the very least, results in a high quadrature imbalance, even at a low
operating frequency. Also, the capacitance between primary and secondary is a problem. Fortunately, for the very
highest accuracy applications, there is a simple and ingenious solution: a simulated negative capacitor circuit which
neutralises the interwinding capacitance over a wide range of frequency.
The basic principle is to employ positive feedback, through a matching capacitor, with a low-pass filter in the loop
to ensure stability at high frequency. The cut-off frequency of the filter is chosen to be well above the operating
frequency but sufficiently low to ensure adequate attenuation and stability margin at high frequency.
CF
VIN
RS
I1 VOUT
×G F(s) VF
CT
0V
Fig. 1.1 Outline schematic of a negative capacitor
VOUT  Voltage at the transformer primary. Ideally VOUT  VIN and I1  0

RS  Source resistance.
CT  Transformer interwinding capacitance.
CF  Matching feedback capacitance CF  CT  .
G  Gain of a wide-band amplifier (variable and approximately ×2).
F s   Transfer function of a low pass filter.
1.1 The scale of the problem
A typical scenario is a source resistance of up to RS = 100Ω and interwinding capacitance of up to CT = 1nF. To put
the latter into perspective it is equivalent to adding 10m of coax cable to the primary side of the bridge.
The operating frequency is 75Hz. Without the negative capacitor the transfer function would be a low-pass filter
circuit for which the transfer function is, in the complex representation s  j  : -
T s  
1
 1  sRS CT  s 2 RS CT  1  j 4.7  105  2  109
2 2
1  sRS CT
The in-phase error is small but the quadrature component of 47ppm could be a problem. Also, the capacitance
between primary and secondary produces a similar effect. In a typical bridge the transformer ratio is adjusted for
in-phase balance (a null) and the quadrature servo injects a signal to achieve a quadrature balance. The injected
signal has a phase accuracy of around 2mrad (0.2%) so that a quadrature imbalance of 50ppm would result in an in-
phase error of 0.1ppm. It is worth the cost of a bit of extra circuitry to neutralise this effect. It is hardly more
practicable to add extra cable (or a capacitor) to the other side of the bridge.
It should be noted that the transformer interwinding capacitance also has a phase error (the insulating material is
usually PTFE) and the type of feedback capacitance should be chosen to have similar dielectric properties
(polystyrene is the best match). It is for the same reason that matching cables should be used on the reference and
variable arms of the bridge, achieving near quadrature balance.
1
2. Basic circuit analysis
According to Kirchhoff’s law the currents into the node add up to zero and Ohm’s law provides, in the complex
I1  VF  VOUT sCF  0  VOUT sCT  0
With VF  GF s VOUT  I1  VOUT sCT  sCF  GF s sCF 
CT  CF
At low frequency F s   1 and the gain is adjusted so that G   I1  0 as required
CF
The circuit works best when: CF  CT  G2
We can simplify the algebra, without loss of generality, by assuming CF  CT and G2
VIN  VOUT VIN  VOUT

From Ohm’s law: I1    2sCTVOUT 1  F s 
RS RS
T s  
VOUT 1
 
VIN 1  2sRS CT 1  F s 
3. A circuit with a simple first order filter
A simple first order low pass filter has a maximum phase shift of 90 degrees at high frequency and the loop gain
can be made to fall below 0dB (×1) with a phase margin of close to 90 degrees.
The transfer function is of the form: -
F s  
1
1  s
N.B. The time constant is typically related to a resistance and capacitance of the form:   RC
s 1  s
Now 1  F s    T s  
1  s 1  s  2 RS CTs 2
1  as
1
with N  and a  N
1  as  s 2 2 RS CT
This is exactly the same as for a two-stage low pass filter and no accident as the positive feedback acts just like a
bootstrap stage. The error analysis is the same. At low frequency: -
s2
  N  T s   1   1  s 2  as 3
1  as  s 2
2 3
 f   f 
T  f   1     a 
1
 fN   fN  2 2 RS CT
The phase error is small but the in-phase error is only second order with respect to frequency and is a problem, as
the following demonstrates: -
2
Part 6: Monograph 2
 
A filter cut-off frequency of 16kHz   105 has been found to be a reasonable compromise for operation at
75Hz.
1
fN   113kHz and a   2f N  7.1
2 2 RS CT
The value of parameter a is quite high indicating plenty of stability margin (see the monograph “Two-stage filters”
by the same author). With the negative capacitor the significant error components are: -
2 3
 f   f 
f  f N  T  f   1     a   1  4  10 7  j 2  10 9
 fN   fN 
At 2ppb the quadrature error is now negligible but the in-phase error of 0.4ppm is too high for many applications.
The latter is due to the phase shift of the filter as the following demonstrates.
4. A circuit with a two-stage filter
The in-phase error of the previous example can be reduced to negligible levels by the use of a two-stage filter. This
could be done with an actively driven two-stage filter with its very low output impedance. In practice, however, it
is most easily achieved with a directly connected RLC filter. The output impedance is sufficiently low and
substantially inductive, obviating the need for an additional op-amp stage. See the monograph “Two-stage filters”,
section 6 by the same author.
L CT
VIN
C
0V
Fig. 4.1 An RLC filter connects directly to the feedback capacitor
If one neglects the loading effect of the feedback capacitor (see section 4.2) the transfer function for the filter is: -
1  sRF CF s 2CF LF
F s   so that: 1  F s  
1  sRF CF  s 2CF LF 1  sRF CF  s 2CF LF

From above the overall transfer function is, after multiplying top and bottom by 1  sRF CF  s 2CF LF : - 
1  sRF CF  s 2CF LF
T s  
1

1  2sRS CT 1  F s  1  sRF CF  s 2CF LF  s 3 2 RS CT CF LF
This is the same as a three-stage low-pass filter which, in normalised form, s  j  N  is: -
1  as  bs 2
T s  
1
with a  RF CFN b  CF LFN2 and N 
1  as  bs 2  s 3 3 2 RS CT CF LF
3
At low frequency, to a very good approximation: -
s3
  N  T s   1   1  s 3  as 4
1  as  bs 2  s 3
3 4
 f   f 
f  f N  T  f   1  j    a 
 fN   fN 
The in-phase error is now fourth order, with respect to frequency, and truly negligible.
As above typical values for an application are: Source resistance: RS  100 and capacitance: CT  1nF
The filter natural frequency is again 16kHz with: LF  1mH CF  100nF and RF  150
The overall transfer function has parameters: -
1
N   3.68  105 rads-1 (58.6kHz) a  RF CFN  5.5 b  CF LFN2  13.5
3 2 RS CT CF LF
The result is a low and broad peak around the natural frequency indicating plenty of stability margin: -
Fig. 4.1.1 Frequency response near the cut-off frequency (for dB ×20) [1]
(a = 5.5 b = 13.5)
1. Spreadsheet: “Negative cap analyser”.
4
Part 6: Monograph 2
4.2 A check on the output impedance
In section 4 it was assumed that the loading effect of the feedback capacitor was negligible. It is necessary to check
this. The output impedance of the filter is the RC series combination in parallel with the inductance.
 1 
R   sL
 
Z OUT s   sC 

1  sRC sL
2
1
R
sC
At low frequency, the output impedance is, therefore, substantially the inductance: -
f  f N  ZOUT s   sLF
At 75Hz the impedance of the inductor and feedback capacitor are, respectively: -
Z L s   j 2fLF  0.47 j ZC  f    j
1
and  2.1 jM
2fCT
The effect is to reduce the value of the capacitor by a negligible amount. Also, in order to keep the phase error due
to resistance in series with the inductor to less than, say 10-3 radians that resistance must be less than 2kΩ, which is
easily achieved.
4.3 A practical circuit
The most practicable circuit is a fully differential negative capacitor – neither side needs to be at earth potential. A
pair of low cost JFET input op-amps (e.g. a TL072 dual) are perfectly adequate for this circuit. The leakage
currents (a few pA) and their random fluctuations, flowing through the source resistance, have negligible effect.
The interwinding capacitance can vary greatly and so the feedback capacitors are “select on test” to the nearest
preferred value. The variable resistor allows one to adjust the differential gain for precise neutralisation.
CT
VIN 1mH
10k 100nF
150Ω
22k 0V
150Ω
10k 100nF
1mH
VIN
CT
Fig. 4.3.1 A differential negative capacitor circuit.

High Accuracy Electronics Christopher I Daykin

Uploaded by

Copyright:

Available Formats

High Accuracy Electronics Christopher I Daykin

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

High Accuracy Electronics Christopher I Daykin

Uploaded by

Copyright:

Available Formats

Part 0: Acknowledgements and preface

High Accuracy Electronics

(at room temperature)

Faraday’s toroidal transformer – the first on record (Picture courtesy of IET)

A collection of monographs on inductive voltage dividers, ratio transformers and

Version 1.0 (May 2020)

Other contributions came from: -

More feedback would be appreciated.

Monograph 2: High accuracy single capacitors

Monograph 3: Rotary capacitive displacement transducers

Monograph 4: Linear Capacitive Displacement Transducers

Monograph 6: Low phase error capacitors and inductors

Part 2: High Accuracy Filters

Monograph 2: Three-stage filters

Monograph 3: An ultra-high input impedance high pass filter

Part 3: Inductive Voltage Dividers and Ratio Transformers

Monograph 3: Two-stage IVDs and RTs

Monograph 4: Three-stage RTs

Monograph 5: Noise matching transformers

Monograph 6: An F17 type ratio transformer bridge

Monograph 7: An F18 type ratio transformer bridge

Monograph 8: A 16 bit binary differential capacitance bridge

Part 4: High accuracy active circuits

Monograph 2: High accuracy voltage followers (HAVFs)

Monograph 4: The Isotech microK “bridge”

Monograph 5: Multislope ADCs

Part 5: Null detector circuits

Monograph 2: Low noise BJT pre-amplifiers

4.5 A useful variant

Monograph 3: Low noise JFET pre-amplifiers

Part 6: Miscellaneous circuits

Monograph 2: A simulated negative capacitor circuit

Monograph 3: A circuit for measuring tanδ.

High accuracy resistors

The three types are: -

Current carrying terminals

Voltage sensing terminals

Fig. 1.1 The “Wilkins” type transfer standard 2TP resistor

1. Part 4, Monograph 3: “High accuracy amplifiers, integrators and differentiators”.

Fig. 2.5 Simplified equivalent circuit of a remote resistor

1. Part 4, monograph 3: “High accuracy amplifiers, integrators and differentiators”.

Fig. 2.1.2 Equivalent circuit of fig. 2.1.1 (courtesy Awan et al)

This author begs to differ!

A more satisfactory definition of a four-terminal-pair is offered in section 5.

Fig. 3.1 2TP connections

Fig. 3.2 A typical bridge configuration for 2TP resistors

1. Part 5, monograph 1: “Null detectors – the basics”.

Define parameters:  S  C RS CS and T  C RT CT . Both are small (typically <0.1mrad or 100ppm).

3.1.1 Example calculation: -

 S  471 25  2  1010  2.4  106 T  471 100  109  4.7  105

1. Part 5, monograph 1: “Null detectors – the basics”. See section 6.1.

1 and  2  1  VOUT  cos D   j sin D aR1 1  j1   R2 1  j 2 

The bridge ratio, a, is adjusted so that the real part is zero.

ReVOUT   0  aR1cos D   1 sin D  R2 cos D    2 sin D   0

R2  cos D    2 sin  D   R2  1   2 tan D  

To a useful degree of accuracy, assuming small phase errors: -

3.2.1 Example calculation

1  2.4rad  2  47rad and tan D   0.1

Fig. 3.3.1 Equivalent circuit

The impedance is: Z  R  jL