Stgap 2 Sicd

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STGAP2SiCD

Datasheet

Galvanically isolated 4 A dual gate driver

Features
• High voltage rail up to 1200 V
• Driver current capability: 4 A sink/source @ 25 °C
• dV/dt transient immunity ±100 V/ns
• Overall input-output propagation delay: 75 ns
• Separate sink and source option for easy gate driving configuration
• 4 A Miller CLAMP
• UVLO function
• Configurable interlocking function
• Dedicated SD and BRAKE pins
• Gate driving voltage up to 26 V
• 3.3 V, 5 V TTL/CMOS inputs with hysteresis
• Temperature shutdown protection
• Standby function
• 6 kV galvanic isolation
• Wide Body SO-36W
• UL 1577 recognized

Application
• Motor driver for industrial drives, factory automation, home appliances and fans
Product status link • 600/1200 V inverters
• Battery chargers
STGAP2SiCD
• Induction heating
Product label • Welding
• UPS
• Power supply units
• DC-DC converters
• Power Factor Correction

DS13714 - Rev 2 - September 2022 www.st.com


For further information contact your local STMicroelectronics sales office.
STGAP2SiCD

Description
The STGAP2SiCD is a dual gate driver for SiC MOSFETs which provides galvanic
isolation between each gate driving channel and the low voltage control and interface
circuitry. The gate driver is characterized by 4 A current capability and rail-to-rail
outputs, making it suitable for mid and high power applications such as power
conversion and industrial motor drivers inverters. The separated output pins allow to
independently optimize turn-on and turn-off by using dedicated gate resistors, while
the Miller CLAMP function allows avoiding gate spikes during fast commutations in
half-bridge topologies. The device integrates protection functions: dedicated SD and
BRAKE pins are available, UVLO and thermal shutdown are included to easily design
high reliability systems. In half-bridge topologies the interlocking function prevents
outputs from being high at the same time, avoiding shoot-through conditions in case
of wrong logic input commands. The interlocking function can be disabled by a
dedicated configuration pin, allowing independent and parallel operation of the two
channels. The input to output propagation delay results are contained within 75 ns,
providing high PWM control accuracy. A standby mode is available in order to reduce
idle power consumption.

DS13714 - Rev 2 page 2/24


STGAP2SiCD
Block diagram

1 Block diagram

Figure 1. Block diagram

VDD VH_A

UVLO
VH
INA Floating Level GON_A
Section Shifter
Control
Logic
GOFF_A
CLAMP_A
INB
I
S
GNDISO_A
Floating ground A +
Control O
SD VCLAMPth
Logic L
A
T VH_B
I
O
BRAKE
N
UVLO
VH
Floating Level GON_B
Section Shifter
VDD Control
GOFF_B
Logic
CLAMP_B
iLOCK
GND GNDISO_B
Floating ground B +

VCLAMPth

DS13714 - Rev 2 page 3/24


STGAP2SiCD
Pin description and connection diagram

2 Pin description and connection diagram

Figure 2. Pin connection (top view)

N.C. 1 36 N.C.
N.C. 2 35 GNDISO_A
N.C. 3 34 GNDISO_A
N.C. 4 33 CLAMP_A
N.C. 5 32 GOFF_A
VDD 6 31 GON_A
INA 7 30 VH_A
INB 8
SD 9
BRAKE 10

iLOCK 11
N.C. 12 25 CLAMP_B
GND 13 24 GNDISO_B
N.C. 14 23 GOFF_B
N.C. 15 22 GON_B
N.C. 16 21 N.C.
N.C. 17 20 VH_B
N.C. 18 19 N.C.

Table 1. Pin description

Pin number Pin name Type Function

6 VDD Power supply Control logic supply voltage


7 INA Logic input Control logic input for Channel A, active high
8 INB Logic input Control logic input for Channel B, active high
9 SD Logic input Shutdown input, active low
10 BRAKE Logic input Control logic input, active low
11 iLOCK Analog input Interlocking enable/disable
13 GND Power supply Control logic ground
20 VH_B Power supply Channel B gate driving positive supply
22 GON_B Analog output Channel B Source output
25 CLAMP_B Analog output Channel B Miller Clamp
23 GOFF_B Analog output Channel B Sink output
24 GNDISO_B Power supply Channel B gate driving isolated ground
30 VH_A Power supply Channel A gate driving positive supply
31 GON_A Analog output Channel A Source output
33 CLAMP_A Analog output Channel A Miller Clamp
32 GOFF_A Analog output Channel A Sink output

34, 35 GNDISO_A (1) Power supply Channel A gate driving isolated ground

1, 2, 3, 4, 5, 12, 14,
N.C. Not connected.
15, 16, 17, 18

1. Both GNDISO_A pins must be connected and shorted together.

DS13714 - Rev 2 page 4/24


STGAP2SiCD
Electrical data

3 Electrical data

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Test condition Min. Max. Unit

VDD Logic supply voltage vs. GND -0.3 6.5 V


VLOGIC Logic pins voltage vs. GND -0.3 6.5 V

iLOCK Interlocking Enable vs. GND -0.3 VDD + 0.3 V


Positive supply voltage
VH_x -0.3 28 V
(VH_x vs GNDISO_x)
Voltage on gate driver outputs
VOUT -0.3 VH_x + 0.3 V
(GON_x , GOFF_x , CLAMP_x vs GNDISO_x)
TJ Junction temperature -40 150 °C

TS Storage temperature -50 150 °C

ESD HBM (human body model) 2 kV

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter Package Value Unit

Rth(JA) Thermal resistance junction to ambient SO-36W 52 °C/W

DS13714 - Rev 2 page 5/24


STGAP2SiCD
Recommended operating conditions

3.3 Recommended operating conditions

Table 4. Recommended operating conditions

Symbol Parameter Test conditions Min. Max. Unit

VDD Logic supply voltage vs. GND 3.1 5.5 V


VLOGIC Logic pins voltage vs. GND 0 5.5 V
iLOCK Interlocking Enable vs. GND 0 VDD V
Positive supply voltage
VH_x 26 V
(VH_x vs. GNDISO_x)
Floating grounds differential voltage
GNDISOA-B(1) -1700 +1700 V
(GNDISO_A - GNDISO_B)
Primary to secondary ground
VIORM -1200 +1200 V
(GND - GNDISO_A); (GND - GNDISO_B)
FSW Maximum switching frequency(2) 1 MHz

tOUT Output pulse width 100 ns

TJ Operating junction temperature -40 125 °C

1. Characterization data, 1200 V max. tested in production.


2. Actual limit depends on power dissipation and TJ.

DS13714 - Rev 2 page 6/24


STGAP2SiCD
Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 18 V, VDD = 5 V unless otherwise specified)

Symbol Pin Parameter Test conditions Min. Typ. Max. Unit

Dynamic characteristics

INA, INB, SD, Input to output


tDon See Figure 8 50 75 90 ns
BRAKE propagation delay ON

INA, INB, SD, Input to output


tDoff See Figure 8 50 75 90 ns
BRAKE propagation delay OFF

tr Rise time CL = 4.7 nF, 30 ns

tf Fall time See Figure 8 30 ns

MT Matching time (1) 20 ns

INA, INB, SD,


tdeglitch Inputs deglitch filter 20 40 ns
BRAKE

Common-mode transient VCM = 1500 V,


CMTI(2) immunity, |dVISO/dt|
100 V/ns
see Figure 9

Supply voltage

VH_x UVLO turn-on


VHon 14.6 15.5 16.4 V
threshold

VH_x UVLO turn-off


VHoff 13.9 14.8 15.7 V
threshold

VHhyst VH_x UVLO hysteresis 600 750 950 mV

IQHU_A
VH undervoltage
VH = 7 V 1.3 1.8 mA
IQHU_B quiescent supply current

IQH_A
VH_x quiescent supply
1.3 1.8 mA
IQH_B current

IQHSBY_A
Standby VH_x quiescent
400 550 µA
IQHSBY_B supply current

IGOFF = 0.2 A;
SafeClp GOFF active clamp 2 2.3 V
VH floating

VDD quiescent supply


IQDD 1.8 2.4 mA
current

Standby VDD quiescent


IQDDSBY Standby mode 40 80 µA
supply current

Logic Inputs

INA, INB, SD, High level logic threshold


Vil 0.29·VDD 0.33·VDD 0.37·VDD V
BRAKE voltage

INA, INB, SD, Low level logic threshold


Vih 0.62·VDD 0.66·VDD 0.72·VDD V
BRAKE voltage

INA, INB, SD, Logic inputs high level


Ilogic_h Vlogic = 5 V 33 50 70 µA
BRAKE input bias current

INA, INB, SD, Logic inputs low level


Ilogic_l Vlogic = 0 V 1 µA
BRAKE input bias current

INA, INB, SD, Logic inputs pull-down


Rpd 70 100 150 kΩ
BRAKE resistor

Interlocking

Interlockng enable
iLOCKen iLOCK 0.7·VDD V
voltage

DS13714 - Rev 2 page 7/24


STGAP2SiCD
Electrical characteristics

Symbol Pin Parameter Test conditions Min. Typ. Max. Unit

iLOCK high level bias


iLOCK_h iLOCK iLOCK = VDD 1 µA
current

iLOCK low level bias


iLOCK_l iLOCK iLOCK = GND 35 55 75 µA
current

iLOCK_pu iLOCK iLOCK pull-up resistor 66 90 142 kΩ

Driver buffer section

TJ = 25°C 4
Source short-circuit
IGON A
current TJ = -40 / +125°C (2)
3 5

Source output high level


VGONH IGON = 100 mA VH-0.15 VH-0.12 V
voltage

RGON Source RDS_ON IGON = 100 mA 1.25 1.5 Ω

TJ = 25°C 4
IGOFF Sink short-circuit current A
TJ = -40 / +125°C (2)
3 5.5

Sink output low level


VGOFFL IGOFF = 100 mA 110 120 mV
voltage

RGOFF Sink RDS_ON IGOFF = 100 mA 1.1 1.2 Ω

Miller Clamp

CLAMP voltage
VCLAMPth VCLAMP vs. GNDISO 1.3 2 2.6 V
threshold

VCLAMP = 15 V
CLAMP short-circuit TJ = 25°C
ICLAMP 4 A
current
TJ = -40 ÷ +125°C (2)
2 5

CLAMP low level output


VCLAMP_L ICLAMP = 100 mA 96 115 mV
voltage

RCLAMP CLAMP RDS_ON ICLAMP = 100 mA 0.96 1.15 Ω

Overtemperature protection

TSD Shutdown temperature (2) 170 °C

Temperature hysteresis
Thys (2) 20 °C

Standby

tSTBY Standby time See Section 6.3 200 280 500 µs

tWUP Wake-up time See Section 6.3 10 20 35 µs

tawake Wake-up delay See Section 6.3 90 140 200 µs

tstbyfilt Standby filter See Section 6.3 200 280 800 ns

1. MT = max (|tDon(A) - tDon(B)|, |tDoff(A) - tDoff(B)|, |tDoff(A) - tDon(B)|, |tDoff(B) - tDon(A)|)


2. Characterization data, not tested in production.

DS13714 - Rev 2 page 8/24


STGAP2SiCD
Isolation

5 Isolation

Table 6. Isolation and safety-related specifications

Parameter Symbol Value Unit Conditions

Clearance Measured from input terminals to output terminals,


CLR 8 mm
(Minimum External Air Gap ) shortest distance through air

Creepage (*) Measured from input terminals to output terminals,


CPG 8 mm
(Minimum External Tracking) shortest distance path along body

Comparative Tracking Index


CTI ≥ 400 V DIN IEC 112/VDE 0303 Part 1
( Tracking Resistance)
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)

Table 7. Isolation characteristics

Parameter Symbol Test Conditions Characteristic Unit

Maximum Working Isolation


VIORM 1200 VPEAK
Voltage
Method a, Type test
VPR = VIORM × 1.6, tm = 10 s 1920 VPEAK

Input to Output test voltage Partial discharge < 5 pC


VPR
In accordance with VDE 0884-11 Method b1, 100 % Production test
VPR = VIORM × 1.875, tm = 1 s 2250 VPEAK

Partial discharge < 5 pC

Transient Overvoltage tini = 60 s


VIOTM 6000 VPEAK
(Highest Allowable Overvoltage) Type test

Maximum Surge Test Voltage VIOSM Type test 6000 VPEAK

Isolation Resistance RIO VIO = 500 V; Type test >109 Ω

Table 8. Isolation voltage as per UL 1577

Description Symbol Characteristic Unit

Isolation Withstand Voltage, 1min (Type test) VISO 3535/5000 Vrms/ PEAK

Isolation Test Voltage, 1sec (100% production) VISOtest 4242/6000 Vrms/ PEAK

Recognized under the UL 1577 Component Recognition Program - file number E362869

DS13714 - Rev 2 page 9/24


STGAP2SiCD
Functional description

6 Functional description

6.1 Gate driving power supply and UVLO


The STGAP2SiCD is a flexible and compact gate driver with 4 A output current and rail-to-rail outputs. The device
allows to implement either unipolar or bipolar gate driving.

Figure 3. Power supply configuration for unipolar and bipolar gate driving

Unipolar gate driving Bipolar gate driving

VH_A VH_A
VDD VDD

GON_A VH GON_A VH
GOFF_A GOFF_A
INA INA CLAMP_A
CLAMP_A

VL
I GNDISO_A I GNDISO_A
INB S INB S
O O
Control L
Control L

Logic A VH_B Logic A VH_B


T
BRAKE T BRAKE
I I
O VH
O
GON_B VH GON_B
N N
GOFF_B GOFF_B
SD SD
CLAMP_B CLAMP_B

iLOCK VL
iLOCK GNDISO_B GNDISO_B

GND GND

Undervoltage protection is available on VH_x supply pin. A fixed hysteresis sets the turn-off threshold, thus
avoiding intermittent operation.
When VH_x voltage goes below the VHoff threshold, the output buffer goes into “safe state”. When VH_x voltage
reaches the VHon threshold, the device returns to normal operation and sets the output according to actual input
pins status.
The VDD and VH_x supply pins must be properly filtered with local bypass capacitors. The use of capacitors with
different values in parallel provides both local storage for impulsive current supply and high-frequency filtering.
The best filtering is obtained by using low-ESR SMT ceramic capacitors, which are therefore recommended. A
100 nF ceramic capacitor must be placed as close as possible to each supply pin, and a second bypass capacitor
with value in the range between 1 μF and 10 μF should be placed close to it.

6.2 Power-up, power-down and ‘safe state’


The following conditions define the “safe state”:
• GOFF = ON state
• GON = high impedance
Such conditions are maintained at power-up of the isolated side (VH_x < VHon) and during whole device power-
down phase (VH < VHoff), regardless of the value of the input pins.
The device integrates a structure which clamps the driver output to a voltage not higher than SafeClp when VH
voltage is not high enough to actively turn the internal GOFF MOSFET on. If VH_x positive supply pin is floating
or not supplied the GOFF pin is therefore clamped to a voltage smaller than SafeClp.
If the supply voltage VDD of the control section of the device is not supplied, the output is put in safe state, and
remains in such condition until the VDD voltage returns within operative conditions.
After power-up of both isolated and low voltage side the device output state depends on the input pins' status.

DS13714 - Rev 2 page 10/24


STGAP2SiCD
Control Inputs

6.3 Control Inputs


The device is controlled through the following logic inputs:
• SD: active low shutdown input;
• BRAKE: active low brake input;
• INA, INB: active high logic inputs for channel A and channel B driver outputs;
• iLOCK: used to enable or disable the interlocking protection.
The operation of the driver IOs is described in Table 9.

Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state")

Input pins(1) Output pins

iLOCK SD BRAKE INA INB GOUT_A GOUT_B


X L X X X Low Low
X H L X X Low HIGH
X H H L L Low Low
X H H H L HIGH Low
X H H L H Low HIGH
Interlocking VDD H H H H Low Low
GND H H H H HIGH HIGH

1. X: Don’t care

A deglitch filter allows input signals with duration shorter than tdeglitch to be ignored, thereby preventing noise
spikes potentially present in the application from generating unwanted commutations.

6.4 Watchdog
The isolated HV side has a watchdog function in order to identify when it is not able to communicate with LV side,
for example because the VDD of the LV side is not supplied. In this case the output of the driver is forced into
“safe state” until communication link is properly established again.

6.5 Thermal shutdown protection


The device provides a thermal shutdown protection. When junction temperature reaches the TSD temperature
threshold, the device is forced into “safe state”. The device operation is restored as soon as the junction
temperature is lower than TSD - Thys.

6.6 Standby function


In order to reduce the power consumption of both control interface and gate driving sides the device can be put in
standby mode. In standby mode the quiescent current from VDD and VH_x supply pins is reduced to IQDDS and
IQHS_x respectively, and the output remains in ‘safe state’ (the output is actively forced low).
The way to enter standby is to keep the SD low while keeping the other input pins (INA, INB and BRAKE) high
(“standby” value) for a time longer than tSTBY. During standby the inputs can change from the “standby” value.
To exit standby, inputs must be put in any combination different from the “standby” value for a time longer than
tstbyfilt , and then in the “standby” value for a time t such that tWUP< t < tSTBY.
When the input configuration is changed from the “standby” value the output is enabled and set according to
inputs state after a time tawake.

DS13714 - Rev 2 page 11/24


STGAP2SiCD
Interlocking function

Figure 4. Standby state sequences

Sequence to enter stand-by mode


t < tSTBY t = tSTBY
“stand-by”: { INA = INB = BRAKE = HIGH
SD = LOW
duration too short
is any different combination
INA, INB, SD, BRAKE “stand-by” “stand-by”

Device status ACTIVE STAND-BY

Output ACTIVE SAFE-STATE

Sequence to exit stand-by mode


t = tSTBY t > tstbyfilt t < tWUP t > tSTBY tWUP < t < tSTBY t = tawake
duration duration too long
too short
INA, INB, SD, BRAKE “stand-by” “stand-by” “stand-by” “stand-by”

Device status ACTIVE STAND-BY ACTIVE

Output ACTIVE SAFE-STATE ACTIVE

6.7 Interlocking function


The interlocking function prevents outputs GOUT_A and GOUT_B from being high at the same time, regardless
of the status of the input pins INA and INB. In half-bridge topologies this protection avoids shoot-through in case
wrong input signals are generated by the controller device. If the status of INA and INB is such to require both
channels to be ON at the same time, the driver turns both channels off. In some topologies it is required to allow
both channels to be ON at the same time: this can be achieved by disabling the interlocking function trough the
iLOCK pin. The iLOCK pin is either connected to VDD, which enables the interlocking function, or to GND, which
disables the interlocking function and allows parallel operation of Channel_A and Channel_B. Refer to Control
Inputs for complete logic inputs truth table.

DS13714 - Rev 2 page 12/24


STGAP2SiCD
Typical application diagram

7 Typical application diagram

Figure 5. Typical application diagram – Half-bridge configuration

HV_BUS
VDD
VH_HS
VDD VH_A
1uF 100nF
100nF 1uF
VDD
UVLO GON_A
HIN INA VH
Floating Level
Rfilt Section Shifter
Cfilt
Control
GOFF_A
Logic
CLAMP_A
LIN INB
Rfilt
Cfilt GNDISO_A
MCU I
S Floating ground A
SD SD Control O
+
GND_HS
Load_ Phase
VCLAMPth
Rfilt
Cfilt
Logic L
VH_LS
A VH_B
T
BRAKE BRAKE
I 100nF 1uF
O
N
UVLO GON_B
VH
Floating Level
Section Shifter
GOFF_B
VDD Control
Logic
CLAMP_B
iLOCK
VDD or GND
GND GNDISO_B
Floating ground B +
GND_LS
VCLAMPth

GND_PWR

Figure 6. Typical application diagram – Half-bridge configuration with negative gate driving

HV_BUS
VDD
VH_HS
VDD VH_A
1uF 100nF

VDD
+
UVLO
VH
GON_A
HIN INA VH
Floating Level
Rfilt Section Shifter
Cfilt Control
GOFF_A
Logic
CLAMP_A
LIN INB
Rfilt
Cfilt GNDISO_A
MCU I
S Floating ground A
Control + GND_HS
SD SD O VL_HS + Load_ Phase
Rfilt Logic L VCLAMPth VL
Cfilt A VH_LS
VH_B
T
BRAKE BRAKE
I
+
O
N
UVLO
VH
VH
GON_B
Floating Level
Section Shifter
GOFF_B
VDD Control
Logic
CLAMP_B
iLOCK
VDD or GND
GND GNDISO_B
Floating ground B + GND_LS
VL_LS
VCLAMPth VL
+
GND_PWR

DS13714 - Rev 2 page 13/24


STGAP2SiCD
Layout

8 Layout

8.1 Layout guidelines and considerations


In order to optimize the PCB layout, the following considerations should be taken into account:
• SMD ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to
each supply rail pin. A 100 nF capacitor must be placed between VDD and GND and between VH_x and
GNDISO_x, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to
provide local storage for pulsed current a second capacitor with value in the range between 1 µF and 10 µF
should also be placed close to the supply pins.
– As a good practice it is suggested to add filtering capacitors close to logic inputs of the device (INA,
INB, BRAKE, SD), in particular for fast switching or noisy applications.

• The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop
area and inductance that might cause noise or ringing.

• To avoid degradation of the isolation between the primary and secondary side of the driver, there should be
no trace or conductive area below the driver.

• If the system has multiple layers, it is recommended to connect the VH_x and GNDISO_x pins to internal
ground or power planes through multiple vias of adequate size. These vias should be located close to the IC
pins to maximize thermal conductivity.

8.2 Layout example


An example of STGAP2SiCD suggested half-bridge with negative gate driving PCB layout is shown in Figure 7 ;
the main signals have been highlighted by different colors. It is recommended to follow this example for proper
positioning and connection of filtering capacitors. It is recommended to follow this example for proper positioning
and connection of filtering capacitors.

Figure 7. Suggested PCB layout for half-bridge configuration with negative driving voltage

TOP BOTTOM

GHS
DHS
Roff Ron

CG

SHS
CVDD
RIN CL
CVDD CVHL
CIN
RIN
CVH
CIN
RIN
CIN
RPU
CIN
RPU

RIN
CVHL
Roff
GLS

DLS
Ron

CG

CL

CVH
SLS

DS13714 - Rev 2 page 14/24


STGAP2SiCD
Testing and characterization information

9 Testing and characterization information

Figure 8. Timings definition

INA 50% 50%

INB 50% 50%

tr tf
90% 90%

GOUT_A 10% 10%

t Don t Doff

tr tf
90% 90%

GOUT_B 10% 10%

t Don t Doff

Figure 9. CMTI test circuit

DS13714 - Rev 2 page 15/24


STGAP2SiCD
Package information

10 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

10.1 SO-36W package information

Table 10. SO-36W package dimensions


Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs are not to exceed
0.15 mm per side.
mm
Dim. NOTES
Min. Typ. Max.

A 2.65
A1 0.1 0.3
b 0.25 0.35
c 0.20 0.33
D 15.20 15.60
E1 7.4 7.6
E 10.05 10.65
e 0.80
e1 4.00
L 0.61 0.91
h 0.25 0.75
θ 0° 8°
aaa 0.25
bbb 0.25
ccc 0.10

DS13714 - Rev 2 page 16/24


STGAP2SiCD
SO-36W package information

Figure 10. SO-36W package outline

D
DETAIL F
e1
e1/2

36 19

E1 E

1 18
DETAIL F

h x 45°

e/2
29x e

TOP VIEW

32x b A1

SIDE VIEW

DS13714 - Rev 2 page 17/24


STGAP2SiCD
Suggested land pattern

11 Suggested land pattern

Figure 11. SO-36W suggested land pattern

11.1

1.5

0.5

3.5

0.8

8.1

DS13714 - Rev 2 page 18/24


STGAP2SiCD
Ordering information

12 Ordering information

Table 11. Device summary

Order code Output configuration Package Package marking Packaging

Separated outputs
STGAP2SICD SO-36W GAP2ID Tube
and Miller CLAMP
Separated outputs
STGAP2SICDTR SO-36W GAP2ID Tape and Reel
and Miller CLAMP

DS13714 - Rev 2 page 19/24


STGAP2SiCD

Revision history

Table 12. Document revision history

Date Version Changes

18-Oct-2021 1 Initial release.


29-Sep-2022 2 Added UL file certification

DS13714 - Rev 2 page 20/24


STGAP2SiCD
Contents

Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.1 Gate driving power supply and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 Power-up, power-down and ‘safe state’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.3 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.5 Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.6 Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.7 Interlocking function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13


8 Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
8.1 Layout guidelines and considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.2 Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

9 Testing and characterization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15


10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
10.1 SO-36W package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18


12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

DS13714 - Rev 2 page 21/24


STGAP2SiCD
List of tables

List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 18 V, VDD = 5 V unless otherwise specified) . . . . . . . . . . . . . . . . . 7
Table 6. Isolation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Isolation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Isolation voltage as per UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. SO-36W package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DS13714 - Rev 2 page 22/24


STGAP2SiCD
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Power supply configuration for unipolar and bipolar gate driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Standby state sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Typical application diagram – Half-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Typical application diagram – Half-bridge configuration with negative gate driving . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Suggested PCB layout for half-bridge configuration with negative driving voltage . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Timings definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. CMTI test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. SO-36W package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. SO-36W suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DS13714 - Rev 2 page 23/24


STGAP2SiCD

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DS13714 - Rev 2 page 24/24

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