Stgap 2 Sicd
Stgap 2 Sicd
Stgap 2 Sicd
Datasheet
Features
• High voltage rail up to 1200 V
• Driver current capability: 4 A sink/source @ 25 °C
• dV/dt transient immunity ±100 V/ns
• Overall input-output propagation delay: 75 ns
• Separate sink and source option for easy gate driving configuration
• 4 A Miller CLAMP
• UVLO function
• Configurable interlocking function
• Dedicated SD and BRAKE pins
• Gate driving voltage up to 26 V
• 3.3 V, 5 V TTL/CMOS inputs with hysteresis
• Temperature shutdown protection
• Standby function
• 6 kV galvanic isolation
• Wide Body SO-36W
• UL 1577 recognized
Application
• Motor driver for industrial drives, factory automation, home appliances and fans
Product status link • 600/1200 V inverters
• Battery chargers
STGAP2SiCD
• Induction heating
Product label • Welding
• UPS
• Power supply units
• DC-DC converters
• Power Factor Correction
Description
The STGAP2SiCD is a dual gate driver for SiC MOSFETs which provides galvanic
isolation between each gate driving channel and the low voltage control and interface
circuitry. The gate driver is characterized by 4 A current capability and rail-to-rail
outputs, making it suitable for mid and high power applications such as power
conversion and industrial motor drivers inverters. The separated output pins allow to
independently optimize turn-on and turn-off by using dedicated gate resistors, while
the Miller CLAMP function allows avoiding gate spikes during fast commutations in
half-bridge topologies. The device integrates protection functions: dedicated SD and
BRAKE pins are available, UVLO and thermal shutdown are included to easily design
high reliability systems. In half-bridge topologies the interlocking function prevents
outputs from being high at the same time, avoiding shoot-through conditions in case
of wrong logic input commands. The interlocking function can be disabled by a
dedicated configuration pin, allowing independent and parallel operation of the two
channels. The input to output propagation delay results are contained within 75 ns,
providing high PWM control accuracy. A standby mode is available in order to reduce
idle power consumption.
1 Block diagram
VDD VH_A
UVLO
VH
INA Floating Level GON_A
Section Shifter
Control
Logic
GOFF_A
CLAMP_A
INB
I
S
GNDISO_A
Floating ground A +
Control O
SD VCLAMPth
Logic L
A
T VH_B
I
O
BRAKE
N
UVLO
VH
Floating Level GON_B
Section Shifter
VDD Control
GOFF_B
Logic
CLAMP_B
iLOCK
GND GNDISO_B
Floating ground B +
VCLAMPth
N.C. 1 36 N.C.
N.C. 2 35 GNDISO_A
N.C. 3 34 GNDISO_A
N.C. 4 33 CLAMP_A
N.C. 5 32 GOFF_A
VDD 6 31 GON_A
INA 7 30 VH_A
INB 8
SD 9
BRAKE 10
iLOCK 11
N.C. 12 25 CLAMP_B
GND 13 24 GNDISO_B
N.C. 14 23 GOFF_B
N.C. 15 22 GON_B
N.C. 16 21 N.C.
N.C. 17 20 VH_B
N.C. 18 19 N.C.
34, 35 GNDISO_A (1) Power supply Channel A gate driving isolated ground
1, 2, 3, 4, 5, 12, 14,
N.C. Not connected.
15, 16, 17, 18
3 Electrical data
4 Electrical characteristics
Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 18 V, VDD = 5 V unless otherwise specified)
Dynamic characteristics
Supply voltage
IQHU_A
VH undervoltage
VH = 7 V 1.3 1.8 mA
IQHU_B quiescent supply current
IQH_A
VH_x quiescent supply
1.3 1.8 mA
IQH_B current
IQHSBY_A
Standby VH_x quiescent
400 550 µA
IQHSBY_B supply current
IGOFF = 0.2 A;
SafeClp GOFF active clamp 2 2.3 V
VH floating
Logic Inputs
Interlocking
Interlockng enable
iLOCKen iLOCK 0.7·VDD V
voltage
TJ = 25°C 4
Source short-circuit
IGON A
current TJ = -40 / +125°C (2)
3 5
TJ = 25°C 4
IGOFF Sink short-circuit current A
TJ = -40 / +125°C (2)
3 5.5
Miller Clamp
CLAMP voltage
VCLAMPth VCLAMP vs. GNDISO 1.3 2 2.6 V
threshold
VCLAMP = 15 V
CLAMP short-circuit TJ = 25°C
ICLAMP 4 A
current
TJ = -40 ÷ +125°C (2)
2 5
Overtemperature protection
Temperature hysteresis
Thys (2) 20 °C
Standby
5 Isolation
Isolation Withstand Voltage, 1min (Type test) VISO 3535/5000 Vrms/ PEAK
Isolation Test Voltage, 1sec (100% production) VISOtest 4242/6000 Vrms/ PEAK
Recognized under the UL 1577 Component Recognition Program - file number E362869
6 Functional description
Figure 3. Power supply configuration for unipolar and bipolar gate driving
VH_A VH_A
VDD VDD
GON_A VH GON_A VH
GOFF_A GOFF_A
INA INA CLAMP_A
CLAMP_A
VL
I GNDISO_A I GNDISO_A
INB S INB S
O O
Control L
Control L
iLOCK VL
iLOCK GNDISO_B GNDISO_B
GND GND
Undervoltage protection is available on VH_x supply pin. A fixed hysteresis sets the turn-off threshold, thus
avoiding intermittent operation.
When VH_x voltage goes below the VHoff threshold, the output buffer goes into “safe state”. When VH_x voltage
reaches the VHon threshold, the device returns to normal operation and sets the output according to actual input
pins status.
The VDD and VH_x supply pins must be properly filtered with local bypass capacitors. The use of capacitors with
different values in parallel provides both local storage for impulsive current supply and high-frequency filtering.
The best filtering is obtained by using low-ESR SMT ceramic capacitors, which are therefore recommended. A
100 nF ceramic capacitor must be placed as close as possible to each supply pin, and a second bypass capacitor
with value in the range between 1 μF and 10 μF should be placed close to it.
Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state")
1. X: Don’t care
A deglitch filter allows input signals with duration shorter than tdeglitch to be ignored, thereby preventing noise
spikes potentially present in the application from generating unwanted commutations.
6.4 Watchdog
The isolated HV side has a watchdog function in order to identify when it is not able to communicate with LV side,
for example because the VDD of the LV side is not supplied. In this case the output of the driver is forced into
“safe state” until communication link is properly established again.
HV_BUS
VDD
VH_HS
VDD VH_A
1uF 100nF
100nF 1uF
VDD
UVLO GON_A
HIN INA VH
Floating Level
Rfilt Section Shifter
Cfilt
Control
GOFF_A
Logic
CLAMP_A
LIN INB
Rfilt
Cfilt GNDISO_A
MCU I
S Floating ground A
SD SD Control O
+
GND_HS
Load_ Phase
VCLAMPth
Rfilt
Cfilt
Logic L
VH_LS
A VH_B
T
BRAKE BRAKE
I 100nF 1uF
O
N
UVLO GON_B
VH
Floating Level
Section Shifter
GOFF_B
VDD Control
Logic
CLAMP_B
iLOCK
VDD or GND
GND GNDISO_B
Floating ground B +
GND_LS
VCLAMPth
GND_PWR
Figure 6. Typical application diagram – Half-bridge configuration with negative gate driving
HV_BUS
VDD
VH_HS
VDD VH_A
1uF 100nF
VDD
+
UVLO
VH
GON_A
HIN INA VH
Floating Level
Rfilt Section Shifter
Cfilt Control
GOFF_A
Logic
CLAMP_A
LIN INB
Rfilt
Cfilt GNDISO_A
MCU I
S Floating ground A
Control + GND_HS
SD SD O VL_HS + Load_ Phase
Rfilt Logic L VCLAMPth VL
Cfilt A VH_LS
VH_B
T
BRAKE BRAKE
I
+
O
N
UVLO
VH
VH
GON_B
Floating Level
Section Shifter
GOFF_B
VDD Control
Logic
CLAMP_B
iLOCK
VDD or GND
GND GNDISO_B
Floating ground B + GND_LS
VL_LS
VCLAMPth VL
+
GND_PWR
8 Layout
• The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop
area and inductance that might cause noise or ringing.
• To avoid degradation of the isolation between the primary and secondary side of the driver, there should be
no trace or conductive area below the driver.
• If the system has multiple layers, it is recommended to connect the VH_x and GNDISO_x pins to internal
ground or power planes through multiple vias of adequate size. These vias should be located close to the IC
pins to maximize thermal conductivity.
Figure 7. Suggested PCB layout for half-bridge configuration with negative driving voltage
TOP BOTTOM
GHS
DHS
Roff Ron
CG
SHS
CVDD
RIN CL
CVDD CVHL
CIN
RIN
CVH
CIN
RIN
CIN
RPU
CIN
RPU
RIN
CVHL
Roff
GLS
DLS
Ron
CG
CL
CVH
SLS
tr tf
90% 90%
t Don t Doff
tr tf
90% 90%
t Don t Doff
10 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
A 2.65
A1 0.1 0.3
b 0.25 0.35
c 0.20 0.33
D 15.20 15.60
E1 7.4 7.6
E 10.05 10.65
e 0.80
e1 4.00
L 0.61 0.91
h 0.25 0.75
θ 0° 8°
aaa 0.25
bbb 0.25
ccc 0.10
D
DETAIL F
e1
e1/2
36 19
E1 E
1 18
DETAIL F
h x 45°
e/2
29x e
TOP VIEW
32x b A1
SIDE VIEW
11.1
1.5
0.5
3.5
0.8
8.1
12 Ordering information
Separated outputs
STGAP2SICD SO-36W GAP2ID Tube
and Miller CLAMP
Separated outputs
STGAP2SICDTR SO-36W GAP2ID Tape and Reel
and Miller CLAMP
Revision history
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.1 Gate driving power supply and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 Power-up, power-down and ‘safe state’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.3 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.5 Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.6 Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.7 Interlocking function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 18 V, VDD = 5 V unless otherwise specified) . . . . . . . . . . . . . . . . . 7
Table 6. Isolation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Isolation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Isolation voltage as per UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. SO-36W package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Power supply configuration for unipolar and bipolar gate driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Standby state sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Typical application diagram – Half-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Typical application diagram – Half-bridge configuration with negative gate driving . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Suggested PCB layout for half-bridge configuration with negative driving voltage . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Timings definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. CMTI test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. SO-36W package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. SO-36W suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18