International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)

Volume VIII, Issue IV, April 2019 | ISSN 2278-2540

Review Paper on Design and Implementation of

Kogge-Stone Adder Using Cadence Virtuoso
Alfiya Kouser1, Harshitha D2, Karotiya Rishabh3, Lakshmi Narsimha4, Prof. Tanya Mendez5
1,2,3,4
UG Students, Department of Electronics and Communication Engineering, AIET, Mijar, Moodbidri, Karnataka, India
5
Department of Electronics and Communication Engineering, AIET, Mijar, Moodbidri, Karnataka, India

Abstract—In Very Large Scale Integration (VLSI) designs, to improving the efficiency of the design. Carry Look-ahead
Parallel Prefix Adder (PPA) have better delay performance. A Adder are based on the parallel prefix computation. After
parallel prefix adder involves the execution of the operation in many years of research, focus is on improving the delay
parallel which can be obtained by segmentation into smaller performance of the adder.
pieces. The binary addition is the basic arithmetic operation in
digital circuits and it is essential in most of the digital systems II. LITERATURE REVIEW
including Arithmetic and Logic Unit (ALU), Microprocessor and
Digital Signal Processors (DSP). At present, the research Penchalaiah and Kumar [1] did research on a new PPA
continues in increasing the adder’s delay performance. In this architecture called KSA which was proposed for 8, 16, 32 and
paper the investigation of Kogge Stone Adder (KSA) using Carry 64-bit addition. The proposed method was implemented and
Look-ahead Adder (CLA) is done. These adders are the results were validated by the comparison of KSA with
implemented using Cadence Virtuoso Platform in both the front- CSKA in terms of area, delay, speed and power consumption.
end and back-end design. The obtained results on the proposed KSA reported the
Keywords-PPA, ALU, KSA, CLA minimum energy consumption compared with the CSKA
along with area compaction and high speed. The proposed
I. INTRODUCTION method can be very useful in high speed applications.

B inary adders are one of the essential and broadly utilized

arithmetic operation in current Integrated Circuits (IC’s).
They tend to play a critical role in determining the
Hoe et al. [2] has proposed three types of carry-tree adders
(the Kogge-Stone, sparse Kogge-Stone, and spanning tree
adder) and compares them to the simple Ripple Carry Adder
performance of the design. Arithmetic operation is the normal (RCA) and Carry Skip Adder (CSA). These designs of varied
regular task in advanced incorporated circuits. The least bit-widths were implemented on a Xilinx Spartan 3E FPGA
complex circuit includes addition, subtraction and and delay measurements were made with a high-performance
multiplication or divisions. The computation should be fast logic analyzer. Due to the presence of a fast carry-chain, the
and the area consumed by the computation should be fast and RCA designs exhibit better delay performance up to 128 bits.
the power consumption should be less. These are the essential The carry-tree adders are expected to have a speed advantage
necessities for any adders. Parallel processing is a type of over the RCA as bit widths approach 256. Hence it is
calculation in which numerous figuring are done at the same concluded that the carry-tree adders eventually surpass the
time, working on the rule that substantial issues can regularly performance of the linear adder designs at high bit-widths,
be separated into simpler ones, which are then settled expected to be in the 128 to 256 bit range.
simultaneously in parallel. These are a few unique types of
parallel registering bit level, instruction level, data, and task Shilpa C. N et al. [3] worked on the design and
parallelism. Parallelism has been utilized power consumption performance of the Kogge Stone Parallel Prefix Adders and
and consequently heat generation by computers has become a implemented it using different design technique. CMOS
major concern in recent years, parallel computing has become (Complementary Metal Oxide Semiconductor) and GDI (Gate
the dominant paradigm in computer architecture, mainly in Diffusion Input) are the different design technique used. The
the form of multi-core processors. design and simulation of logic gates were performed on
CADENCE Design Suit 6.1.6 using virtuoso and ADE
Parallel computers can be roughly classified according to Environment at GPDK 180nm technology. The execution
the level at which the hardware supports parallelism, with measurement considered for the performance of the KSA is
core and multi-processor computers having multiple delay, number of gate count/Transistor Count (area) and
processing elements within a solitary machine. Area and time power. Simulation studies are done for 4-bit, 8-bit and 16-bit
devoured by the circuit are the essential critical prerequisites. input data. The results of the comparative analysis, showed
Numbers can be spoken to in advanced circuits in different how the performance can vary from 4 bit to 16 bit adder
ways. Thus, developing efficient adder architecture is crucial architecture.

www.ijltemas.in Page 34
 International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume VIII, Issue IV, April 2019 | ISSN 2278-2540

Gurkaynak et al. [4] had described the design of radix-3 between them. The 16-bit KSA (Kogge Stone Adder) design
and radix- 4 parallel prefix adders, the main building blocks of used 16-bit BC’s and 15 GC’s with less delay compare to SKA
the higher radix parallel prefix adders were identified and and STA. The 16-bit BKA (Brent Kung Adder) used 14 BC’s
higher radix structures of Kogge-Stone Adders were presented. and 11 GC’s which is less compared to KSA and hence has
Work showed that the logic depth could be reduced by 50% less architecture and occupies less space than KSA. The delay
and the cell count can be reduced as much as 47% for 64-bit measurement shows that SKA and BKA have almost same
adders. Simulation results indicated that radix-4 adders could delay whereas STA has better delay results. The efficiency has
be 30% more faster than radix-2 realizations. It was also noted increased for delay up to 5.77% for RCA and for KSA has
that the proposed architectures not only reduced the depth of improved by 19.28%.
the carry propagation network as much as 50%, but the number
Athira et al. [8] proposed a Kogge-Stone Adder (KSA)
of cells required also decreased by as much as 47% (for the
with low power consumption and delay. Usually, Ripple Carry
Radix-4 Kogge-Stone adder) when compared to the Radix-2
Adders (RCA) are preferred for addition of two N-bit numbers
realizations.
as these RCAs provide faster design time among all types of
Penumutchi et al. [5] worked on the GDI technique to conventional methods. However, RCA’s have limitation that
design the circuits for high speed and low power applications. every full adder block must wait till carry bits were generated
A 64 bit GDI logic based KSA schematic was designed using from previous blocks of the full adder. The implemented
MENTOR GRAPHICS EDA Tool in 130nm Technology. Kogge-Stone Adder was a parallel prefix form Carry Look
Performance parameters like delay and average power Ahead (CLA) adder. Parallel prefix adders (PPA) are tree
consumption (at various dimensions of MOS transistors and based structure which speed up the binary addition. Hence
over a range of supply voltages) were measured and the best prefix adders are used for fast addition algorithms. The
adder in terms of performance was observed as the one with a experimental result shows that the addition by using Kogge-
delay of 407.07ps designed in GDI Technique. When Stone Adder reduces power consumption and delay in
compared to the others, Kogge -Stone Adder was identified as comparison with other conventional logics. The performance
the fastest adder and also had a lower fan-out at the output analysis was based on the power consumption and the worst
which increased its performance but on the other hand, it case delay in performing the operation. The CMOS adders
occupied much area and created wiring congestion problems. were realized using TSMC 45 nm technologies. The results
Much more advanced tool support was required to design KSA showed that the proposed KSA greatly reduces the power
with the exact expected performance. consumption.
K. Swetha et al. [6] proposed the fastest adder and used in Daphni and Vijula Grace [9] clarified about the design and
many data processing applications to perform the fast analysis of various Parallel Prefix Adder (PPA) and compared
arithmetic functions. The speed of operation of the CSLA is the performance of these adder on the aspects of area, delay
limited by the time required to propagate a carry through the and power. From the investigation results it was clear that the
adder. The implementation of 16-bit Linear Carry Select Adder Kogge stone adder (KSA) was superior for the delay process,
(LCSLA) with Kogge Stone Adder (KSA) was prepared in so the speed of the addition was automatically increased. But it
terms of Binary to Excess-1 converter (BEC) and extra logic takes more power consumption and area. In addition to that it
gates. A high speed adder was designed by merging the CSLA is described the comparison of PPA with the performance on
and KSA algorithms instead of using ripple carry adder (RCA) the aspects of area, power and delay. From the reviewed
and due to that the delay is reduced, but it occupied more area. analysis results it was clear that the KSA was better for the
Synthesis and simulation result of CSLA with KSA was done delay process, so the speed of the addition was automatically
by using Xilinx ISE 13.3 and Cadence EDA tool and increased. But it takes more power consumption and area.
compared interms of ADP and PDP, which showed that 16-bit Newer implementation can focus on attaining better area-
adder with FCL for KSA with BEC based CSLA for Cin=0 power delay PPA for low power VLSI applications.
affords better performance in terms of ADP and PDP and it
Smith and Chew Lim [10] introduced two innovations in
had 2% efficiency in ADP and 7% efficiency in PDP than
the design of prefix adder carry trees which used high-valency
other methods.
prefix cells to achieve low logical depth and end-around carry
Yezerla and Rajendra [7] proposed their design and adders with reduced fan-out loading (compared with the carry
implemented using Xilinx vertex 5FPGA and the adder delays select and fagged prefix adders). An algorithm for generating
were estimated using Agilent 1692A logic analyzer. The 16-bit parallel prefix carry trees suitable for use in a VLSI synthesis
SKA (Sparse Kogge Stone Adder) computes the carries with tool was presented with variable parameters including caw tree
Black Cells (BC’s) and Grey Cells (GC’s) and terminates with width, prefix cell valency, and the spacing of repeated carry
a 4-bit RCA (Ripple Carry Adder). The 16-bit STA (Spanning trees. The area-delay design space was mapped for a 0.25pm
Tree Adder) used also terminates with RCA and uses BC’s and CMOS technology. An algorithm for generating parallel prefix
GC’s and full adders but has difference in the interconnection trees with variable parameters was introduced and the

www.ijltemas.in Page 35
 International Journal of Latest Technology in Engineering, Management & Applied Science (IJLTEMAS)
Volume VIII, Issue IV, April 2019 | ISSN 2278-2540

performance results derived from SPICE simulations using a Stone Adder using CMOS and GDI design:A VLSI Based
Approach”, IEEE 2016.
uniform sizing model have been presented.
[4]. FrankK. Gurkaynad, Yusuf Leblebicit, Laurent Chaouatt and
III. CONCLUSION Patrik J. McGuinnessz “Higher Radix Kogge-Stone Parallel Prefix
Adder Architectures”, IEEE 2000.
The primary purpose of the paper is to make a survey of all [5]. Bujjibabu Penumutchi, Satyanarayana vella, Harichndra prasad
satti, “Kogge Stone Adder with GDI Technique in 130nm
the details and parameters of the Parallel Prefix Adder, Ripple Technology for High performance DSP Applications”, IEEE 2017.
Carry Adder, Carry Skip Adder Carry, Look Ahead Adder [6]. Y. Yorozu, M. Hirano, K. Oka, and Y. Tagawa, “Electron
and Brent-Kung adder in order to identify the efficient adder spectroscopy studies on magneto-optical media and plastic
in terms of delay and power consumption. The survey results substrate interface,” IEEE Transl. J. Magn. Japan, vol. 2, pp. 740–
741, August 1987 [Digests 9th Annual Conf. Magnetics Japan, p.
concludes that Kogge-Stone Adder reported the minimum 301, 1982].
energy consumption when compared with other adders and [7]. Sudheer kumar yezerla,B Rajendra, “Design and estimation of
also showed the performance analysis of 4-bit and 16-bit delay,power and area for parallel prefix adders”, IEEE 2014.
adder architecture, and performance based on ADP and PDP. [8]. T. S. ATHIRA, R. DIVYA, M. KARTHIK, A. MANIKANDAN,
“DESIGN OF KOGGE-STONE FOR FAST ADDITION”,
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