Experiment No:1

Familiarization of Digital ICs

Aim
To familiarize with some basic logic gate IC packages and to verify the truth tables of the logic
gates.
Components and equipments required: ICs 7408, 7432, 7404, 7400, 7402, 7486
and IC trainer kit.
Theory
IC trainer kit The equipment is mainly used to test and set up digital circuits while doing
experiments. Integrated circuits can be fitted in sockets or breadboards provided in it. There are
built-in voltage source and clock signals in it. The frequency of clock can be selected by turning
the knob into different positions. In order to feed monopulses manually, a debouncer switch is
also provided. A number of select switches are provided to represent low and high states for
digital inputs. Green and Red LEDs are provided to represent low and high states respectively
to visualize the digital outputs.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The output is
high when both the inputs are high. The output is low level when any one of the inputs is low.
7408 is a digital IC in the TTL family and contains four AND gates.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are Low. 7432
is a quad two input OR gate.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The output is low
when the input is high. IC 7404 is a hex inverter.
NAND GATE:
A NOT gate following an AND gate is called NAND gate. Its output will be low if all the inputs
are in high state.The output is high when both inputs are low and any one of the input is low.
7400 IC is a quad two input NAND gate.
NOR GATE:
A NOT gate following an OR gate is called NOR gate. The output is high when both inputs are
low. The output is low when one or both inputs are high.7402 is a quad two input NOR gate.
XOR GATE:
The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high. 7486 is a quad two input XOR gate.
Procedure
1. Test the ICs using digital IC tester before conducting the experiment.
2. Verify the dual in line package (DIP) pin out of the IC before feeding the inputs.
3. Setup the circuit and observe the output.
Result
Familiarized with the logic gate IC packages and verified the truth table for the logic gates.
 Experiment No:2
Realization of SOP and POS expression using
universal gates
AIM
To realize sum of product (SOP) and product of sum (POS) expressions using universal
gates.
Two input SOP:- A.B + A’.B’
Two input POS: - (A+B)(A’+B’)
Components and equipments required: ICs 7400, 7402 and IC trainer kit.
Theory
SOP stands for Sum of Product. SOP form is a set of product(AND) terms that are
summed(OR) together. When an expression or term is represented in a sum of binary
terms known as minterms and sum of products. POS stands for product of sum. A
technique of explaining a Boolean expression through a set of max terms or sum terms,
is known as POS(product of sum).
Procedure
1. Test all components using digital IC tester.
2. Set up the circuits as shown in figures one by one. Observe the outputs
corresponding to input combinations.
Result
Implemented the circuits and verified the outputs.

Realization of SOP expression Y=AB+A’B’ using NAND gates only

using NOR gates only

Realization of POS expression Y=(A+B)(A’+B’) using NOR gates only

using NAND gates only

 Experiment No:3
HALF ADDER AND FULL ADDER
Aim
To design and set up a half adder and full adder using
a) Minimum number of gates
b) Basic gates
c) NAND gates only
Components and equipments required: ICs 7408, 7432, 7404, 7400, 7486 and IC
trainer kit.
Theory
The simplest binary adder is called a half adder. Half adder has two input bits and two output
bits. One output bit is the sum and the other is carry. They are represented by S and C
respectively in the logic symbol. A half adder has no provision to add a carry from the lower
order bits when binary numbers are added. When two input bits and a carry are to be added,
the number of input bits become three and the input combinations increase to eight. For this, a
Full adder is used. Like half adder, it also has a sum bit and a carry bit. The new carry
generated is represented by Cin and carry generated from the previous addition is represented
by Cout.
Procedure
1) Verify whether all the components and wires are in good condition.
2) Set up the half adder circuit and feed the input bit combinations.
3) Observe the output corresponding to input combinations.
4) Repeat the above steps for a full adder circuit.
Result
Implemented the circuits and verified the outputs.

HALF ADDER
CIRCUIT DIAGRAM
1) Using minimum number of gates

2) Using basic gates

3) Using NAND gates only

FULL ADDER
CIRCUIT DIAGRAM
1) Using minimum number of gates

2) Using basic gates

3) Using NAND gates only
 Experiment No:4
HALF SUBTRACTOR AND FULL SUBTRACTOR
Aim
To design and set up a half subtractor and full subtractor using
d) Minimum number of gates
e) Basic gates
f) NAND gates only
Components and equipment required: ICs 7408, 7432, 7404, 7400, 7486 and IC
trainer kit.
Theory
Half subtractor is a combination circuit with two inputs and two outputs which is
difference and borrow. It produces the difference between the two binary bits at the input and
also produces an output (Borrow) to indicate if a 1 has been borrowed.
A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, taking into account borrow of the previous adjacent lower
minuend bit. This circuit has three inputs and two outputs. The three inputs A, B and Bin, denote
the minuend, subtrahend, and previous borrow, respectively. The two outputs, D and Bout
represent the difference and output borrow, respectively.
Procedure
1) Verify whether all the components and wires are in good condition.
2) Set up the half subtractor circuit and feed the input bit combinations.
3) Observe the output corresponding to input combinations.
4) Repeat the above steps for a full subtractor circuit.
Result
Implemented the circuits and verified the outputs.

HALF SUBTRACTOR
CIRCUIT DIAGRAM
1) Using minimum number of gates

2) Using basic gates

3) Using NAND gates only

FULL SUBTRACTOR
CIRCUIT DIAGRAM
1) Using minimum number of gates

2) Using basic gates

3) Using NAND gates

 Experiment No:5
CODE CONVERTERS
Aim
To design and set up the following circuits.
1) A BCD to Excess3 code converter.
2) A 4-bit Binary to Gray code converter
Components and equipments required: ICs 7408, 7432, 7404,7486 and IC trainer
kit.
Theory
A BCD digit can be converted to its corresponding Excess-3 code by simply adding 3 to
it. Since we have only 10 digits(0 to 9) in decimal, we don’t care about the rest and marked
them with a cross( X ).
To convert a Binary number to corresponding Gray code, the following rules are applied.
1) The MSB in the Gray code is the same as the corresponding bit in a Binary number.
2) Going from left to right, add each adjacent pair of binary digits to get the next Gray code
digit. Disregard carries.
Procedure
1) Test all the components and IC packages.
2) Verify the truth tables of the circuit by feeding the input bit combinations.
Result
Implemented the circuits and verified the outputs.
Binary to Gray Code converter
 Experiment No:6
Multiplexers and Demultiplexers using gates
Aim
To study a 4:1 multiplexer and 1:4 demultiplexer using gates.
Components and equipments required: ICs 7408, 7432, 7404 and IC trainer kit.
Theory
Multiplexer (MUX) is a combinational circuit which selects one of the inputs and route it
to the output. A multiplexer has data input lines, data select lines and output.
Demultiplexer (Demux) does the reverse operation of multiplexer. The data on a line is
directed to any one of the output line according to the binary code on data select lines.
Procedure
1) Test all ICs and wires and set up the circuit.
2) Feed all four combinations at S1S0 one by one, and observe corresponding output.
Result
Implemented the circuits and verified the outputs.