+

COMPUTER ORGANIZATION & ARCHITECTURE

Van-Khoa Pham (PhD.)
+ Chapter 7
Input/Output
 Read Memory
Address Lines
Write
N Words
Address 0 Data System
Data Lines Bus
Data N–1

Control Lines

Read I/O Module Internal

Write Data

External
Address M Ports Data

Internal
I/O Module
Data Interrupt
Signals
External
Data

Links to
Instructions Address
peripheral
Control devices
Data CPU Signals

Interrupt Data
Signals

Figure 3.15 Computer Modules Figure 7.1 Generic Model of an I/O Module
CPU-Memory-I/O Architecture

Memory

I/O I/O
CPU
module device

“CPU bus”
or “Bus interface” “I/O bus”
“System bus”
why does not connect peripherals
directly to the system bus?
 There are a wide variety of peripherals with various methods of
operation. It would be impractical to incorporate the necessary logic
within the processor to control a range of devices.

 The data transfer rate of peripherals is often much slower than that of
the memory or processor. Thus, it is impractical to use the high-speed
system bus to communicate directly with a peripheral.

 The data transfer rate of some peripherals is faster than that of the
memory or processor. Again, the mismatch would lead to inefficiencies
if not managed properly.

 Peripherals often use different data formats and word lengths than the
computer to which they are attached.
Ethernet modem
(max speed)

Graphics display

Wi-Fi modem
(max speed)

Hard disk

Optical disc

Laser printer

Scanner

Mouse

Keyboard

101 102 103 104 105 106 107 108 109 1010 1011
Data Rate (bps)

Figure 2.1 Typical I/O Device Data Rates

+
External Devices

Three
 Provide a means of
exchanging data between the categories:
external environment and the
computer  Human readable
 Suitable for communicating with
the computer user
 Attach to the computer by a  Video display terminals (VDTs),
link to an I/O module printers
 The link is used to exchange
control, status, and data
 Machine readable
between the I/O module and  Suitable for communicating with
equipment
the external device
 Magnetic disk and tape systems,
sensors and actuators
 Peripheral device
 An external device connected  Communication
to an I/O module  Suitable for communicating with
remote devices such as a terminal,
a machine readable device, or
another computer
 Control Status Data bits
signals from signals to to and from
I/O module I/O module I/O module

Control Buffer
Logic
Transducer

Data (device-unique)
to and from
environment

Figure 7.2 Block Diagram of an External Device

+ Keyboard/Monitor
Most common means of
computer/user interaction
User provides input through the
keyboard
International Reference Alphabet
(IRA) The monitor displays data
provided by the computer
 Basic unit of exchange is the character
 Associated with each character is a code
 Each character in this code is
Keyboard Codes
represented by a unique 7-bit binary
code  When the user depresses a key it
 128 different characters can be generates an electronic signal that is
represented interpreted by the transducer in the
keyboard and translated into the bit
 Characters are of two types: pattern of the corresponding IRA code
 Printable
 Alphabetic, numeric, and special
 This bit pattern is transmitted to the I/O
characters that can be printed on module in the computer
paper or displayed on a screen
 Control  On output, IRA code characters are
 Have to do with controlling the
transmitted to an external device from the
printing or displaying of characters I/O module
 Example is carriage return
 The transducer interprets the code and
 Other control characters are
sends the required electronic signals to
concerned with communications
procedures the output device either to display the
indicated character or perform the
requested control function
 The major functions for an I/O
module fall into the following
categories:
Control and timing
• Coordinates the flow of traffic between internal resources and external devices

Processor communication
• Involves command decoding, data, status reporting, address recognition

Device communication
• Involves commands, status information, and data

Data buffering
• Performs the needed buffering operation to balance device and memory speeds

Error detection
• Detects and reports transmission errors
 Interface to Interface to
System Bus External Device

Data
Data Registers External
Device
Data Status
Interface
Lines
Logic
Status/Control Registers Control

Address
Lines Data
External
I/O Device
Logic Status
Interface
Control Logic
Lines Control

Figure 7.3 Block Diagram of an I/O Module

+ Programmed I/O
Three techniques are possible for I/O
operations:
 Programmed I/O
 Data are exchanged between the processor and the I/O module
 Processor executes a program that gives it direct control of the I/O
operation
 When the processor issues a command it must wait until the I/O
operation is complete
 If the processor is faster than the I/O module this is wasteful of
processor time
 Interrupt-driven I/O
 Processor issues an I/O command, continues to execute other
instructions, and is interrupted by the I/O module when the latter has
completed its work
 Direct memory access (DMA)
 The I/O module and main memory exchange data directly without
processor involvement
 Table 7.1
I/O Techniques

No Interrupts Use of Interrupts

I/O-to-memory transfer Programmed I/O Interrupt-driven I/O

through processor

Direct I/O-to-memory Direct memory access (DMA)

transfer
+
I/O Commands
 There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:

1) Control
- used to activate a peripheral and tell it what to do

2) Test
- used to test various status conditions associated with an I/O
module and its peripherals

3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer

4) Write
- causes the I/O module to take an item of data from the data bus
and subsequently transmit that data item to the peripheral
 Issue Read Issue Read CPU I/O Issue Read CPU DMA
command to CPU I/O command to Do something block command Do something
I/O module I/O module else to I/O module else

Read status Read status Interrupt Read status Interrupt

of I/O I/O CPU of I/O of DMA
I/O CPU
module module module DMA CPU
Not
ready Next instruction
Check Error Check Error
status condition status condition (c) Direct memory access
Ready Ready
Read word Read word
from I/O I/O CPU from I/O I/O CPU
Module Module

Write word Write word

CPU memory CPU memory
into memory into memory

No No
Done? Done?

Yes Yes
Next instruction Next instruction
(a) Programmed I/O (b) Interrupt-driven I/O
Figure 7.4 Three Techniques for Input of a Block of Data
I/O Instructions
With programmed I/O there is a close correspondence between the I/O-related
instructions that the processor fetches from memory and the I/O commands that
the processor issues to an I/O module to execute the instructions

Each I/O device connected through I/O modules is given a

unique identifier or address

The form of the

When the processor
issues an I/O Memory-mapped I/O
instruction depends command, the
on the way in which command contains the
external devices are address of the desired
addressed device

Thus each I/O module There is a single address space for A single read line and a single write
must interpret the memory locations and I/O devices line are needed on the bus
address lines to
determine if the
command is for itself
+
I/O Mapping Summary

 Memory mapped I/O

 Devices and memory share an address space
 I/O looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands available

 Isolated I/O
 Separate address spaces
 Need I/O or memory select lines
 Special commands for I/O
 Limited set
 7 6 5 4 3 2 1 0
516 Keyboard input data register

7 6 5 4 3 2 1 0
Keyboard input status
517
and control register

1 = ready Set to 1 to
0 = busy start read

ADDRESS INSTRUCTION OPERAND COMMENT

200 Load AC "1" Load accumulator
Store AC 517 Initiate keyboard read
202 Load AC 517 Get status byte
Branch if Sign = 0 202 Loop until ready
Load AC 516 Load data byte

(a) Memory-mapped I/O

ADDRESS INSTRUCTION OPERAND COMMENT

200 Load I/O 5 Initiate keyboard read
201 Test I/O 5 Check for completion
Branch Not Ready 201 Loop until complete
In 5 Load data byte

(b) Isolated I/O

Figure 7.5 Memory-Mapped and Isolated I/O

Interrupt-Driven I/O
The problem with programmed I/O is that the
processor has to wait a long time for the I/O module
to be ready for either reception or transmission of
data

An alternative is for the processor to issue an I/O

command to a module and then go on to do some
other useful work

The I/O module will then interrupt the processor to

request service when it is ready to exchange data
with the processor

The processor executes the data transfer and

resumes its former processing
 Hardware Software

Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction

Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt

Figure 7.6 Simple Interrupt Processing

 T–M T–M
Y N+1
Control Control
Stack Stack
T T
N+1 Y+L
Program Program
Counter Counter

Y Start Y Start
Interrupt General Interrupt General
Service Registers Service Registers
Y + L Return Routine T Y + L Return Routine T–M
Stack Stack
Pointer Pointer

Processor Processor

T–M T

N User's N User's
N+1 N+1
Program Program

Main Main
Memory Memory

(a) Interrupt occurs after instruction

(b) Return from interrupt
at location N

Figure 7.7 Changes in Memory and Registers for an Interrupt

Design Issues

• Because there will

be multiple I/O
modules how does
the processor
determine which
Two design device issued the
interrupt?
issues arise in
implementing • If multiple
interrupt I/O: interrupts have
occurred how
does the
processor decide
which one to
process?
+ Device Identification
Four general categories of techniques are in
common use:
 Multiple interrupt lines
 Between the processor and the I/O modules
 Most straightforward approach to the problem
 Consequently even if multiple lines are used, it is likely that each line will have multiple I/O modules
attached to it

 Software poll
 When processor detects an interrupt it branches to an interrupt-service routine whose job is to poll
each I/O module to determine which module caused the interrupt
 Time consuming

 Daisy chain (hardware poll, vectored)

 The interrupt acknowledge line is daisy chained through the modules
 Vector – address of the I/O module or some other unique identifier
 Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine,
avoiding the need to execute a general interrupt-service routine first

 Bus arbitration (vectored)

 An I/O module must first gain control of the bus before it can raise the interrupt request line
 When the processor detects the interrupt it responds on the interrupt acknowledge line
 Then the requesting module places its vector on the data lines
 Slave
82C59A
interrupt
controller
External device 00 IR0
External device 01 IR1 INT
IR2
IR3
IR4
IR5
IR6
External device 07 IR7

Slave Master
82C59A 82C59A
interrupt interrupt 80386
controller controller processor
External device 08 IR0 IR0
External device 09 IR1 INT IR1 INT INTR
IR2 IR2
IR3 IR3
IR4 IR4
IR5 IR5
IR6 IR6
External device 15 IR7 IR7

Slave
82C59A
interrupt
controller
External device 56 IR0
External device 57 IR1 INT
IR2
IR3
IR4
IR5
IR6
External device 63 IR7

Figure 7.8 Use of the 82C59A Interrupt Controller

 PA3 1 40 PA4
Power +5 V PA2 2 39 PA5
supplies Group Group A
GND Port A PA1 3 38 PA6
A I/O
control (8) PA7 - PA0 PA0 4 37 PA7
RD 5 36 WR
CS 6 35 Reset
Bi-directional Group A GND 7 34 D0
data bus Data Port C I/O A1 8 33 D1
bus upper (4) PC7 - PC4 A0 9 8255A 32 D2
D7 - D0 buffer PC7 10 31 D3
8-bit Group B PC6 11 30 D4
internal Port C I/O PC5 12 29 D5
data bus Lower(4) PC3 - PC0
PC4 13 28 D6
RD PC3 14 27 D7
Read/
WR PC2 15 26 V
write Group
A1 Group B
control B PC1 16 25 PB7
A0 Port B I/O
logic control PC0 17 24 PB6
(8) PB7 - PB0
Reset PB0 18 23 PB5
CS
PB1 19 22 PB4
PB2 20 21 PB3
(a) Block diagram (b) Pin layout

Figure 7.9 The Intel 8255A Programmable Peripheral Interface

Interrupt
request
C3 A0 R0
A1 R1
A2 R2
A3 R3
INPUT A4 R4 KEYBOARD
PORT A5 R5
A6 Shift
A7 Control

C4 Data ready
C5 Acknowledge

82C55A
B0 S0
B1 S1
B2 S2
B3 S3
OUTPUT DISPLAY
B4 S4
PORT
B5 S5
B6 Backspace
B7 Clear

C1 Data ready
C2 Acknowledge
C6 Blanking
C0 C7 Clear line
Interrupt
request

Figure 7.11 Keyboard/Display Interface to 82C55A

+ Summary
Input/Output
Chapter 7
 Interrupt-driven I/O
 External devices
 Interrupt processing
 Keyboard/monitor
 Design issues
 Disk drive
 Intel 82C59A interrupt controller
 I/O modules
 Intel 82C55A programmable
 Module function
peripheral interface
 I/O module structure
 Programmed I/O
 Overview of programmed I/O
 I/O commands/instructions
 Direct memory access
 Drawbacks of programmed and
interrupt-driven I/O
 DMA function
 Intel 8237A DMA controller
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