This document discusses the design of a 7T SRAM cell using STT-SOT MTJs for non-volatile memory. It describes the read, write and hold operations of the proposed 7T SRAM cell design. It also discusses integrating STT-SOT MTJs into the cell to enable non-volatility and compares the performance with a 6T SRAM cell.
This document discusses the design of a 7T SRAM cell using STT-SOT MTJs for non-volatile memory. It describes the read, write and hold operations of the proposed 7T SRAM cell design. It also discusses integrating STT-SOT MTJs into the cell to enable non-volatility and compares the performance with a 6T SRAM cell.
This document discusses the design of a 7T SRAM cell using STT-SOT MTJs for non-volatile memory. It describes the read, write and hold operations of the proposed 7T SRAM cell design. It also discusses integrating STT-SOT MTJs into the cell to enable non-volatility and compares the performance with a 6T SRAM cell.
This document discusses the design of a 7T SRAM cell using STT-SOT MTJs for non-volatile memory. It describes the read, write and hold operations of the proposed 7T SRAM cell design. It also discusses integrating STT-SOT MTJs into the cell to enable non-volatility and compares the performance with a 6T SRAM cell.
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Design of STT-SOT MTJ-Based NVSRAM for Energy-Efficient In-Memory
Computing
Department of Electronics and Communication Engineering
Indian Institute of Information Technology- Allahabad
Supervisors: Submitted By:
Guide: Shrikant Harankhede Dr. Prasanna Kumar Misra MMI2022013 Assistant Professor, IIIT Allahabad Email: Email: prasanna@iiita.ac.in mmi2022013@iiita.ac.in Co-guide: Dr. Sanjai Singh Associate Professor, IIIT Allahabad Email: ssingh@iiita.ac.in Abstract: This work explores a novel 7-transistor non-volatile static random access memory (NVSRAM) architecture using spin transfer torque and spin orbit torque (STT-SOT) magnetic tunnel junctions (MTJs) tailored for battery-operated applications demanding low voltage operation and power consumption. The proposed design leverages the advantages of STT-SOT MTJs, such as low switching energy and field-free operation, to significantly reduce the voltage requirements compared to conventional NVSRAMs. The 7T configuration minimizes transistor count, leading to further power reduction and smaller cell size. We are aiming to operate in the near Vt region and operating the NVSRAM cell at a lower voltage .
Introduction: In the ever-evolving landscape of modern computing, the demand for memory technologies that can cater to the requirements of both high-performance and energy-efficient applications is paramount. Among the various contenders, Magnetoresistive Random Access Memory (MRAM) has emerged as a promising candidate, offering distinct advantages over traditional Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) technologies. This introduction seeks to explore the comparative analysis of MRAM against DRAM and SRAM and delve into the utilization of 7T Non-Volatile Static Random Access Memory (NVSRAM) based on Spin-Orbit Torque Magnetic Tunnel Junctions (STT-SOT MTJ) for low-power applications and its non-volatile nature for in-memory computing applications. DRAM and SRAM, though stalwarts in the memory hierarchy, grapple with inherent limitations that hinder their adaptability to the contemporary demands of computing systems. DRAM, while providing high-density storage, is volatile, requiring frequent refresh cycles that consume substantial power and compromise performance. SRAM, on the other hand, boasts faster access times and lower power consumption but falls short in terms of density due to its latch-based structure. In contrast, MRAM leverages the unique properties of magnetic materials to store data, promising the best of both worlds – the non-volatile characteristics of Flash memory and the speed and endurance akin to SRAM. This inherent non-volatility allows for data retention even in the absence of power, eliminating the need for constant refreshing and significantly reducing energy consumption. Within the realm of non-volatile MRAM, the 7T NVSRAM configuration stands out as a noteworthy design, leveraging the Spin-Orbit Torque effect within Magnetic Tunnel Junctions. This innovative approach not only ensures low power consumption but also enhances the reliability and endurance of the memory cells. The utilization of STT-SOT MTJ in 7T NVSRAM holds promise for addressing the power constraints in battery-operated devices and finding applications in emerging paradigms such as in-memory computing. As we embark on this exploration of MRAM and its 7T NVSRAM variant, we aim to unravel the intricacies of their design, performance characteristics, and potential applications. The subsequent chapters of this thesis will delve into the technological nuances, experimental findings, and implications of these memory technologies, contributing to the evolving landscape of semiconductor memory for the next generation of computing systems. Literature Review: [1] present an innovative approach in the design of Spin-Orbit Torque Non-Volatile SRAMs (SOT- NVSRAMs) with a focus on achieving reduced area overhead. The study introduces both 9T and 7T SOT- NVSRAM designs, showcasing improved area × energy product compared to existing alternatives. This marks a significant advancement towards energy-efficient non-volatile memory systems. However, the design of the 7T NVSRAM, utilizing diode-based SOT, introduces a trade-off. While reducing the area requirement, there is a noticeable increase in restore energy consumption and a larger read voltage headroom. Addressing this trade-off becomes a potential avenue for future research and optimization. [2] introduce a novel approach by developing basic logic gates using CMOS Static Random Access Memories (SRAM), aiming to enable in-memory Boolean computations. This innovative application of SRAM technology contributes to advancing in-memory computing capabilities. Despite its potential, traditional SRAM is volatile and requires a continuous power supply. The storage is mostly off-chip, limiting its efficiency. The study proposes an alternative by designing logic gates with Non- Volatile SRAM (NVSRAM), incorporating Spin-Orbit Torque (SOT) based Magnetic Tunnel Junctions (MTJ) to enhance energy efficiency in in-memory computing. [3] conducts a comprehensive comparative study, evaluating various performance parameters for SRAM and STT based MRAM using the GEM 5 simulator. This study provides valuable insights into the comparative performance of these memory technologies. While the study contributes significantly to understanding the performance parameters of SRAM and MRAM using STT-SOT MTJ, there is room for further exploration. Future research could delve deeper into the intricacies of performance metrics to provide a more nuanced understanding of the strengths and weaknesses of each technology, potentially paving the way for optimized memory architectures.
Results and discussion
Here we have worked on a 7T SRAM which is based on a positive feedback. Schematic:
Figure 1: Schematic of positive feedback based 7T SRAM
Read Mode Operation:
During read operation, Fig. 2 illustrates the transistor conditions in the proposed design. With WL and BL connected to Vdd and gnd, and RBL is charged to Vdd initially, the process begins. While reading ‘0’, PM1 is OFF, PM2 is ON, NM1 is ON, NM2 is OFF, and NM4 is ON (gated by Qb). a conducting path is formed between RBL and ground, which causes RBL to discharge, completing the read '0' operation. For read '1', where Q stores logic '1' and Qb stores '0', NM4 turns OFF, maintaining RBL at its pre-charged value.
Write Mode Operation:
In Figure 3, Write mode starts with WL connected to Vdd, which activates access transistor NM3. The bitline is set to the desired data level for writing. A conducting path is formed between the input bitline and node Q via NM3. For writing '1' at Q (assuming logic '0' at Q and '1' at Qb), BL is driven to Vdd, strengthening NM3. WL activation causes internal positive feedback via feedback transistor PM3, flipping the data of the nodes. Writing '0' drives BL to gnd, using internal positive feedback to achieve the desired levels.
Hold Mode Operation:
Figure. 4 depicts transistor conditions during hold operation. WL ties to ground, turning OFF NM3. Assuming data '0' and '1' at Q and Qb, feedback transistor PM3 (VSG3 = Vdd - VQ) helps to retain the same voltage level at Q and Qb. When Q stores '1' and Qb stores '0', PM3 is in cutoff, NM1 is OFF, and PM1 is ON, maintaining Q at a voltage slightly lower than Vdd. This design minimizes power dissipation in hold mode by reducing subthreshold leakage current through variation in supply voltage. Figure 1: read operation Figure2: write operation Figure 3: hold operation Parameter comparison with 6T SRAM:
Figure 5: Write delay Calculation
Figure 6: Write SNM Calculation
AND operation using two bit Cell:
Figure 7: AND operation Fig 8: AND output
The figure 7 shows AND operation using two 7T bit cells. The RBL and BL and common to both the cell. The output is taken from RBL. We can see Q0 = 0, Q1 = 1 and RBL = 0
Proposed design:
Fig 9: Proposed design using MTJ
Here we are proposing a design in which we will be integrating STT-SOT based MTJ for storing Q and Q_bar. We will also provide a a store and restore mechanism to write the data in MTJ and to get the data back from MTJ. This will ensure the data is always available and non-volatile. References: • [1]SOT and STT-Based 4-Bit MRAM Cell for High-Density Memory Applications Authors: NISAR et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO. 9, SEPTEMBER 2021 • [2]Energy Efficient Reduced Area Overhead Spin-Orbit Torque Non-Volatile SRAMs Authors: Karim Ali et al, IEEE TRANSACTIONS ON MAGNETICS, VOL. 57, NO. 2, FEBRUARY 2021 • [3]A Low Power 7T SRAM cell using Supply Feedback Technique at 28nm CMOS Technology Authors: Jitendra kumar Mishra et al, 2020 7th International Conference on Signal Processing and Integrated Networks • [4](SPIN)X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories Authors: Amogh Agrawal et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 12,DECEMBER 2018 • [5]A Comparative Study of Cache Memories Based on MRAM and SRAM Technologies Authors: Ashish Kumar Arya, 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS) • [6]Schmitter trigger-based single-ended stable 7T SRAM cell Authors: Appikatla Phani et al, Analog Integrated Circuits and Signal Processing, Springer Nature, 23 sept 2018 • [7]Spinlib manual
