MP 18851

MP18851
Isolated, Dual-Input Control,

Independent Dual-Channel Gate Driver
DESCRIPTION FEATURES
The MP18851 is an isolated, dual-channel gate • Up to 5kVRMS Input to Output Isolation
driver solution with up to 4A of source and sink (SOIC-16 WB Package)
peak current capability. The gate driver is • 1500VDC Functional Isolation between Two
designed to drive power switching devices with Secondary-Side Drivers (SOIC-16 NB and
a short propagation delay and minimal pulse- SOIC-16 WB Packages)
width distortion. By utilizing MPS’s proprietary • 700VDC Functional Isolation between Two
capacitive-based isolation technology, the Secondary-Side Drivers (LGA-13 Package)
driver can provide up to 5kVRMS withstand • Common-Mode Transient Immunity (CMTI)
voltage (per UL 1577) (SOIC wide-body >100kV/µs
package option). It can also provide a common- • 2.8V to 5.5V Input VDDI Voltage (VDDI)
mode transient immunity (CMTI) rating above Range to Interface with TTL and CMOS-
100kV/µs between the input side and output Compatible Inputs
driver. These advanced features enable high • Up to 30V Output Drive Supply with Several
efficiency, high power density, and robustness Under-Voltage Lockout (UVLO) Options
in a wide variety of power applications. • 4A Source, 4A Sink Peak Current Output
The MP18851 integrates fully independent dual • 50ns Typical Propagation Delay
gate drivers in one package. Each output can • -40°C to +125°C Operating Temperature
be grounded to the separated grounds, or Range
connected to a positive or negative voltage • UL 1577 Certified:
reference. The secondary topology can be • SOIC-16 NB: 3kVRMS Isolation for 60s
configured as a half-bridge high-side (HS) and • SOIC-16 WB: 5kVRMS Isolation for 60s
low-side (LS) driver, or as dual drivers each • LGA-13: 2.5kVRMS Isolation for 60s
controlled by two independent input signals. • DIN EN IEC 60747-17 (VDE 0884-17): 2021-
A wide primary-side VDDI supply voltage (VDDI) 10 Certified:
range makes the driver suitable to be interfaced • SOIC-16 NB: 4242VPK Isolation
with 3.3V and 5V digital controllers. The • SOIC-16 WB: 6000VPK Isolation
secondary-side driver can accept up to a 30V • LGA-13: 3535VPK Isolation
supply. All of the supply voltage pins feature • CQC Certification per GB 4943.1-2011
multiple under-voltage lockout (UVLO) • Available in SOIC-16 NB, SOIC-16 WB, and
protection options. LGA-13 (5mmx5mm) Packages
The MP18851 is available in SOIC-16 NB APPLICATIONS
(narrow body), SOIC-16 WB (wide body), and
LGA-13 (5mmx5mm) packages. • Half/Full-Bridge Converters
• Isolated DC/DC Converters
• Offline Isolated AC/DC Converters
• DC/AC Inverters
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
MP18851 Rev. 1.0 MonolithicPower.com 1

7/26/2022 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2022 MPS. All Rights Reserved.
MP18851 – ISOLATED, DUAL-INPUT, DUAL-CHANNEL GATE DRIVER
TYPICAL APPLICATION
VDDI VDDO
VDDI VDDA
VDDI R1
C1 OUTA
GNDI C2
VSSA
MP18851
EN/DIS
VDDO
INA VDDB
R2
INB OUTB
C3
VSSB
SELECTION GUIDE
Peak
Output On/ Config.
Output Input Overlap
Part Number UVLO Off Configuration Dead Package
Current Logic Protection
(V) Logic Time
(A)
MP18851-4A 3
MP18851-4B 5 SOIC-16 NB,
INA/ SOIC-16 WB,
MP18851-4C 4 8 EN Dual drivers - -
INB LGA-13
MP18851-4D 10 (5mmx5mm)
MP18851-4E 12
MP18851-A4A 3
MP18851-A4B 5 SOIC-16 NB,
INA/ SOIC-16 WB,
MP18851-A4C 4 8 DIS Dual drivers - -
INB LGA-13
MP18851-A4D 10 (5mmx5mm)
MP18851-A4E 12

ORDERING INFORMATION (1)

Part Number* Package Top Marking MSL Rating
MP18851-4AGSE
MP18851-4BGSE
MP18851-4CGSE
MP18851-4DGSE
MP18851-4EGSE
SOIC-16 NB 2
MP18851-A4AGSE
MP18851-A4BGSE
MP18851-A4CGSE
MP18851-A4DGSE
MP18851-A4EGSE
MP18851-4AGY
MP18851-4BGY
MP18851-4CGY
MP18851-4DGY
MP18851-4EGY
SOIC-16 WB See Below 3
MP18851-A4AGY
MP18851-A4BGY
MP18851-A4CGY
MP18851-A4DGY
MP18851-A4EGY
MP18851-4AGLU
MP18851-4BGLU
MP18851-4CGLU
MP18851-4DGLU
MP18851-4EGLU
LGA-13 (5mmx5mm) 3
MP18851-A4AGLU
MP18851-A4BGLU
MP18851-A4CGLU
MP18851-A4DGLU
MP18851-A4EGLU
* For Tape & Reel, add suffix -Z (e.g. MP18851-4AGSE-Z, MP18851-4AGY-Z, or MP18851-4AGLU-Z).
Note:
1) Contact MPS sales or our distributors to check the latest availability status for the ordering part numbers.

TOP MARKING
MP18851-4X (SOIC-16 NB and SOIC-16 WB Packages)
MPS YYWW
M18851-4X
LLLLLLLLL
MPS: MPS prefix

YY: Year code
WW: Week code
M18851-4X: Part number
X: UVLO level code, where X = A, B, C, D, or E
LLLLLLLLL: Lot number
TOP MARKING
MP18851-A4X (SOIC-16 NB and SOIC-16 WB Packages)
MPS YYWW
18851-A4X
LLLLLLLLL
MPS: MPS prefix

YY: Year code
WW: Week code
18851-A4X: Part number
LLLLLLLLL: Lot number

TOP MARKING
MP18851-4X (LGA-13 5mmx5mm Package)
MPSYYWW
MP18851
LLLLLLL
4X
MPS: MPS prefix
YY: Year code
WW: Week code
MP18851: Part number
LLLLLLL: Lot number
4X: Remaining alphanumeric characters of part number
TOP MARKING
MP18851-A4X (LGA-13 5mmx5mm Package)
MPSYYWW
MP18851
LLLLLLL
A4X
MPS: MPS prefix
YY: Year code
WW: Week code
MP18851: Part number
LLLLLLL: Lot number
A4X: Remaining alphanumeric characters of part number

PACKAGE REFERENCE
INA
INB
EN/DIS
SOIC-16 NB, SOIC-16 WB
TOP VIEW
GNDI 1 13 VDDA
INA 2 12 OUTA
INB 3 11 VSSA
VDDI 4
EN/DIS 5 10 VDDB
NC 6 9 OUTB
VDDI 7 8 VSSB
LGA-13 (5mmx5mm)

PIN FUNCTIONS
Pin #
SOIC-16 NB, Name Description
LGA-13
SOIC-16 WB
Non-inverting logic control signal input for driver A. The INA pin can
1 2 INA accept a TTL/CMOS level compatible input logic. This pin is internally pulled
down to GNDI. It is recommended to tie this pin to GNDI if not used.
Non-inverting logic control signal input for driver B. The INB pin can
2 3 INB accept a TTL/CMOS level compatible input logic. This pin is internally pulled
down to GNDI. It is recommended to tie this pin to GNDI if not used.
Input-side power supply input. VDDI supplies power to the primary-side
control circuitry. These pins are internally shorted, and are locally decoupled to
3, 8 4, 7 VDDI
GNDI using a low-ESR/ESL bypass capacitor. The capacitor should be placed
as close to the chip as possible.
Input-side ground. Reference ground for all input-side signals and internal
4 1 GNDI
control blocks.
Enable control input. The EN pin can be driven by an external TTL/CMOS
level compatible input logic signal to enable/disable the chip. This pin is pulled
5 5 EN
high internally. Pull this pin high or leave it open to enable the chip; pull it low to
shut down the driver output and disable the chip.
Disable control input. The DIS pin can be driven by an external TTL/CMOS
level compatible input logic signal to enable/disable the chip. This pin is pulled
5 5 DIS
low internally. Pull this pin low or leave it open to enable the chip; pull it high to
shut down the driver output and disable the chip.
6, 7, 12, 13 6 NC Not connected.
9 8 VSSB Output-side ground for driver B. Reference ground for output driver B.
Gate drive output for driver B. Connect this pin to the channel B power
10 9 OUTB
device gate.
Output-side driver power supply input for driver B. This pin supplies power
to the secondary-side driver B circuitry. It is locally decoupled to VSSB using a
11 10 VDDB
low-ESR/ESL bypass capacitor. The capacitor should be placed as close to the
chip as possible.
14 11 VSSA Output-side ground for driver A. Reference ground for output driver A.
Gate drive output for driver A. Connect this pin to the channel A power
15 12 OUTA
device gate.
Output-side driver power supply input for driver A. This pin supplies power
to the secondary-side driver A circuitry. It is locally decoupled to VSSA using a
16 13 VDDA
low-ESR/ESL bypass capacitor. The capacitor should be placed as close to the
chip as possible.

ABSOLUTE MAXIMUM RATINGS (2) Thermal Resistance (5) θJA θJC

VDDI - VGNDI ...................................-0.3V to +6.5V SOIC-16 WB ........................... 56 ...... 30... °C/W
VINA, VINB, VEN/DIS SOIC-16 NB ............................ 59 ...... 35... °C/W
............................. (VGNDI - 0.3V) to (VDDI + 0.3V) LGA-13 (5mmx5mm) ............. 106 ..... 50... °C/W
VINA, VINB, VEN/DIS transient for 50ns
................................ (VGNDI - 5V) to (VDDI + 0.3V) Notes:
2) Exceeding these ratings may damage the device.
VDDA - VSSA, VDDB - VSSB .................-0.3V to +35V 3) The maximum allowable power dissipation is a function of the
VOUTA .....................(VSSA - 0.3V) to (VDDA + 0.3V) maximum junction temperature TJ (MAX), the junction-to-
VOUTA transient for 200ns ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
.................................(VSSA - 2V) to (VDDA + 0.3V) any ambient temperature is calculated by PD (MAX) = (TJ
VOUTB .....................(VSSB - 0.3V) to (VDDB + 0.3V) (MAX) - TA) / θJA. Exceeding the maximum allowable power
VOUTB transient for 200ns dissipation can produce an excessive die temperature, which
may cause the regulator to go into thermal shutdown. Internal
.................................(VSSB - 2V) to (VDDB + 0.3V) thermal shutdown circuitry protects the device from
VSSA - VSSB permanent damage.
4) The device is not guaranteed to function outside of its
SOIC-16 NB, SOIC-16 WB ....-1500V to +1500V operating conditions.
LGA-13 (5mmx5mm) .................-700V to +700V 5) Measured on the MP18851 evaluation board, 2-layer PCB.
Continuous power dissipation (TA = 25°C) (3)
SOIC-16 WB ........................................ 2215mW
SOIC-16 NB ......................................... 2115mW
LGA-13 (5mmx5mm) ........................... 1175mW
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +150°C
ESD Ratings
Human body model (HBM) ...................... 4000V
Charged device model (CDM) ................. 2000V
Recommended Operating Conditions (4)
VDDI - VGNDI ...................................... 2.8V to 5.5V
VINA, VINB, VEN/DIS ............................. VGNDI to VDDI
VDDA - VSSA, VDDB - VSSB
........................... 4.2V to 30V (3V UVLO option)
.......................... 12V to 30V (10V UVLO option)
....................... 14.5V to 30V (12V UVLO option)
Operating junction temp (TJ) .... -40°C to +125°C

ELECTRICAL CHARACTERISTICS
2.8V ≤ VDDI - VGNDI ≤ 5.5V, VDDA - VSSA = VDDB - VSSB = 5V/12V/15V (6), TJ = -40°C to +125°C, typical
value is tested at TJ = 25°C, all voltages with respect to the corresponding ground(s), unless
otherwise noted.
Parameters Symbol Conditions Min Typ Max Units
Input-Side Supply Voltage
VDDI under-voltage lockout
VDDI_UVLO (VDDI - VGNDI) falling 2.42 2.6 2.78 V
(UVLO) threshold
VDDI UVLO hysteresis VDDI_UVLO_HYS 100 120 140 mV
Input-Side Supply Current
VDDI shutdown current IVDDI_SD VEN = VGNDI or VDIS = VDDI 1 1.3 mA
VEN = VDDI or VDIS = VGNDI,
VDDI quiescent current IVDDI_Q 1 1.3 mA
VINA/INB = VGNDI
f = 500kHz, 50% duty,
VDDI operating current IVDDI 2 2.8 mA
CLOAD = 100pF
Logic Input (INA, INB, EN/DIS)
Logic input high threshold VLI_H (VLI - VGNDI) rising 1.6 1.8 V
Logic input low threshold VLI_L (VLI - VGNDI) falling 1 1.2 V
Logic input hysteresis voltage VLI_HYS 360 400 440 mV
Internal pull-up resistance RLI_PU EN 200 kΩ
Internal pull-down resistance RLI_PD INA/INB, DIS 200 kΩ
Output-Side Supply Voltage
-A, 3V threshold 2.7 3.2 3.7 V
VDDA, VDDB UVLO threshold -B, 5V threshold 5 5.5 6 V
VDDA_UVLO,
when (VDDA - VSSA) or (VDDB - -C, 8V threshold 7.5 8 8.5 V
VDDB_UVLO
VSSB) is falling -D, 10V threshold 9.3 10 10.7 V
-E, 12V threshold 11 12 13 V
-A/-B, 3V/5V threshold,
200 300 400 mV
respectively
VDDA_UVLO_HYS,
VDDA, VDDB UVLO hysteresis -C, 8V threshold 420 520 620 mV
VDDB_UVLO_HYS
-D/-E, 10V/12V threshold,
0.8 1 1.2 V
respectively
Output-Side Supply Current
IVDDA_SD,
VDDA, VDDB shutdown current VEN = VGNDI or VDIS = VDDI 1 1.3 mA
IVDDB_SD
VDDA, VDDB quiescent current IVDDA_Q, VEN = VDDI or VDIS = VGNDI,
1 1.3 mA
(current per channel) IVDDB_Q VINA/INB = VGNDI
f = 500kHz, CLOAD = 100pF,
2.5 3 mA
VDDA, VDDB operating current IVDDA, VDDA/VDDB = 12V
(current per channel) IVDDB f = 500kHz, CLOAD = 100pF,
3 4.6 mA
VDDA/VDDB = 15V

ELECTRICAL CHARACTERISTICS (continued)

otherwise noted.
Gate Driver
VDDA/ VDDA/
VOUTA_H,
Logic high output voltage IOUTA/OUTB = -10mA VDDB VDDB V
VOUTB_H
- 0.03 - 0.01
VSSA/ VSSA/
VOUTA_L,
Logic low output voltage IOUTA/OUTB = 10mA VSSB VSSB V
VOUTB_L
+ 0.01 + 0.03
VDDA - VSSA = VDDB - VSSB =
IOUTA_SRC, 15V, VOUTA/OUTB - VSSA/SSB =
Peak output source current (7) -4 A
IOUTB_SRC 5V (5V Miller plateau),
f = 1kHz
VDDA - VSSA = VDDB - VSSB =
IOUTA_SNK, 15V, VOUTA/OUTB - VSSA/SSB =
Peak output sink current (7) 4 A
IOUTB_SNK 5V (5V Miller plateau),
f = 1kHz
ROUTA_H,
Output source resistance IOUTA/OUTB = -10mA 1.3 2.5 Ω
ROUTB_H
ROUTA_L,
Output sink resistance IOUTA/OUTB = 10mA 1 2 Ω
ROUTB_L
Switching (8)
(VOUTA/OUTB - VSSA/SSB) rising,
Output rise time tR 10 20 ns
CLOAD = 1.8nF
(VOUTA/OUTB - VSSA/SSB) falling,
Output fall time tF 10 20 ns
CLOAD = 1.8nF
Output pulse off if
Minimum pulse width tPW_MIN shorter than tPW_MIN, 23 35 ns
CLOAD = 0pF
Propagation delay from INA/INB to VEN = VDDI or VDIS = VGNDI,
tPDLH 35 50 65 ns
the OUTA/OUTB rising edge CLOAD = 0pF
Propagation delay from INA/INB to VEN = VDDI or VDIS = VGNDI,
tPDHL 35 50 65 ns
the OUTA/OUTB falling edge CLOAD = 0pF
Propagation delay from enable true
tPDEN VINA/INB = VDDI, CLOAD = 0pF 35 50 65 ns
to the OUTA/OUTB rising edge
Propagation delay from disable true
tPDDIS VINA/INB = VDDI, CLOAD = 0pF 35 50 65 ns
to the OUTA/OUTB falling edge
Pulse-width distortion |tPDLH - tPDHL| tPWD CLOAD = 0pF 1 6 ns
Propagation delay matching
tPDM CLOAD = 0pF 1 6 ns
(channel-to-channel)

ELECTRICAL CHARACTERISTICS (continued)

otherwise noted.
Switching (8)
Start-up delay from the input
supply exiting UVLO to the tSTU_VDDI 15 25 35 μs
VINA/INB = VDDI, CLOAD = 0pF
output rising edge
Shutdown delay from the input
supply entering UVLO to the tSHD_VDDI 500 ns
VINA/INB = VDDI, CLOAD = 0pF
output falling edge (7)
Start-up delay from the output
tSTU_VDDA, VEN = VDDI or VDIS = VGNDI,
supply exiting UVLO to the 10 20 30 μs
tSTU_VDDB VINA/INB = VDDI, CLOAD = 0pF
output rising edge
Shutdown delay from output
tSHD_VDDA, VEN = VDDI or VDIS = VGNDI,
supply entering UVLO to the 500 ns
tSHD_VDDB VINA/INB = VDDI, CLOAD = 0pF
output falling edge (7)
Static common-mode transient VINA/INB = VGNDI or VDDI,
CMTISTC 100 kV/μs
immunity (CMTI) (7) slew rate of VGNDI vs. VSSA/SSB,
VCM = 1500V
f = 100kHz pulse at INA/INB,
Dynamic CMTI (7) CMTIDYN 100 kV/μs
slew rate of VGNDI vs. VSSA/SSB,
VCM = 1500V
Notes:
6) For the test conditions, VDDA - VSSA = VDDB - VSSB = 5V is used for 3V UVLO devices; VDDA - VSSA = VDDB - VSSB = 12V is used for 5V and 8V
UVLO devices; and VDDA - VSSA = VDDB - VSSB = 15V is used for 10V and 12V UVLO devices.
7) Guaranteed by characterization; not production tested.
8) See Figure 1, Figure 2, and Figure 3 on page 19 as well as Figure 4 on page 20 for details.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

SOIC-16 SOIC-16
Parameters Symbol Condition LGA-13 Units
WB NB
Shortest pin-to-pin distance
External air gap
CLR through the air between the >8 >4 3.5 mm
(clearance) (9)
primary and secondary sides
Shortest pin-to-pin distance across
External tracking
CPG the package surface between the >8 >4 3.5 mm
(creepage) (9)
primary and secondary sides
Distance through
DTI Internal clearance >20 >20 >20 μm
insulation
Comparative tracking
CTI According to IEC60112 >600 >600 >600 V
index
Material group According to IEC 60664-1 I I I
Rated mains voltages ≤ 150VRMS I-IV I-IV I-IV
Overvoltage category per
Rated mains voltages ≤ 300VRMS I-IV I-III I-III
IEC 60664-1
Rated mains voltages ≤ 600VRMS I-III I-II -
UL 1577, 5th Edition
Recognized under UL 1577 Component Recognition Program, Single Protection. File number: E322138
VTEST = VISO for t = 60s
Dielectric withstanding (qualification),
VISO 5000 3000 2500 VRMS
insulation voltage VTEST = 1.2 x VISO for t = 1s (100%
production)
DIN EN IEC 60747-17 (VDE 0884-17): 2021-10 (10)
Certified according to DIN EN IEC 60747-17 (VDE 0884-17): 2021-10; EN IEC 60747-17:2020+AC: 2021.
Certification number: 40055265
Maximum repetitive peak
VIORM AC voltage (bipolar) 891 560 560 VPK
isolation voltage
Maximum working AC voltage (sine wave) 630 400 400 VRMS
VIOWM
isolation voltage DC voltage 891 560 560 VDC
VTEST = VIOTM for t = 60s
Maximum transient (qualification),
VIOTM 6000 4242 3535 VPK
isolation voltage VTEST = 1.2 x VIOTM for t = 1s (100%
production)
Method b1, at routine test (100%
Apparent charge (11) production), Vpd(ini) = 1.2 x VIOTM,
Vpd(m) 1697 1061 1061 VPK
measuring voltage tini = 1s, Vpd(m) = 1.875 x VIORM,
tm = 1s, partial discharge < 5pC
Tested per IEC 62368-1 with
Maximum surge isolation
VIOSM 1.2/50µs pulse, 4000 4000 3500 VPK
voltage (12)
VTEST = 1.3 x VIOSM (qualification)
Barrier capacitance (13) CIO f = 1MHz ~1 ~1 ~1 pF
VIO = 500V, TA = 25°C >10 12
Ω
Insulation resistance (13) RIO VIO = 500V, 100°C ≤ TA ≤ 125°C >1011 Ω
VIO = 500V, TA = TS = 150°C >109 Ω
Pollution degree Per DIN VDE 0110 Table 1 2
Climatic category 40/125/21

INSULATION AND SAFETY-RELATED SPECIFICATIONS (continued)

GB 4943.1-2011
Certified according to CQC GB 4943.1-2011.
File number: CQC22001348725, CQC22001348722, and CQC22001348723.
SOIC-16 WB:
Reinforced insulation, altitude ≤ 5000m, 125°C thermal cycling test passed, 700VP maximum working voltage
SOIC-16 NB:
Basic insulation, altitude ≤ 5000m, 125°C thermal cycling test passed, 660VP maximum working voltage
LGA-13:
Basic insulation, altitude ≤ 5000m, 125°C thermal cycling test passed, 480VP maximum working voltage
Notes:
9) See the Package Information section on page 30 for detailed dimensions. As an isolated solution, the recommended land pattern is helpful
to ensure adequate safety creepage and clearance distances on a PCB.
10) This coupler is suitable for “basic electrical insulation” only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
11) Electrical discharge caused by a partial discharge in the coupler.
12) The surge test is carried out in oil.
13) The barrier’s primary-side and secondary-side terminals are connected, forming a two-terminal device. CIO and RIO are measured between
the two terminals of the coupler.
SAFETY LIMITING VALUES (14)

SOIC-16 SOIC-16
Parameters Symbol Condition LGA-13 Units
WB NB
Maximum safety
TS 150 150 150 °C
temperature (15)
VDDA - VSSA = VDDB - VSSB = 12V (16),
Maximum output 91 87 48 mA
TJ = 150°C, TA = 25°C
safety current IS_O
(current per channel) VDDA - VSSA = VDDB - VSSB = 30V,
36 35 19 mA
TJ = 150°C, TA = 25°C
Input side 15 15 15 mW
Safety power Output side, channel A 1100 1050 580 mW
PS
dissipation (17) Output side, channel B 1100 1050 580 mW
Total 2215 2115 1175 mW
Notes:
14) Maximum value allowed in the event of a failure.
15) The maximum safety temperature (TS) has the same value as the maximum junction temperature, TJ (MAX), specified in the Absolute
Maximum Ratings section on page 8.
16) Tested for 5V and 8V UVLO devices.
17) Test conditions: VDDI - VGNDI = 5.5V, VDDA - VSSA = VDDB - VSSB = 30V, TJ = 150°C, TA = 25°C. The safety power dissipation is a function of
the maximum junction temperature TJ (MAX), the junction-to-ambient thermal resistance θJA, and the ambient temperature TA. This function
can be calculated using the following equations:
TS = TJ (MAX) = TA + (θJA x PS)
P S = IS x V I
Where VI is the input voltage.

THERMAL DERATING CURVES FOR SAFETY LIMITING VALUES

Thermal Derating Curve for Safety Thermal Derating Curve for Safety
Limiting Current Limiting Power
SOIC-16 WB package SOIC-16 WB package
100 2400
90 VDDA/VDDB=12V
SAFETY LIMITING CURRENT
80 VDDA/VDDB=30V 2000
PER CHANNEL (mA)
SAFETY LIMITING POWER

70 1600
60
50 1200
40
(mW)
800
30
20 400
10
0 0
0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
SOIC-16 NB package SOIC-16 NB package
100 2400
90 VDDA/VDDB=12V
2000
80 VDDA/VDDB=30V
PER CHANNEL (mA)
70 1600
60
50 1200
(mW)
40
800
30
20 400
10
0 0
0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200
LGA-13 package LGA-13 package
60 1400
VDDA/VDDB=12V
50 1200
VDDA/VDDB=30V
PER CHANNEL (mA)
1000
40
800
(mW)
30
600
20
400
10 200
0 0
0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200

TYPICAL CHARACTERISTICS
VDDI - VGNDI = 5V, VDDA - VSSA = VDDB - VSSB = 12V, CLOAD = 0pF, TJ = 25°C, all voltages with respect
to the corresponding ground(s), unless otherwise noted.
VDDI Quiescent Current vs. TJ VDDI Operating Current vs. TJ
No switching f = 500kHz, duty cycle = 50%
0.95 2.15
0.90 2.10
IVDDI_Q (mA)
IVDDI (mA)
0.85 2.05
0.80 2.00
VDDI=3.3V VDDI=3.3V
VDDI=5.0V VDDI=5.0V
0.75 1.95
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C)
VDDI Operating Current vs. fSW VDDA/VDDB Quiescent Current vs. TJ

Duty cycle = 50% Per channel, no switching
2.05 1.05
2.04 1.00
IVDDA_Q, IVDDB_Q (mA)
0.95
IVDDI (mA)
2.03
2.02 0.90
2.01 VDDI=3.3V 0.85

VDDI=5.0V
2.00 0.80
0 100 200 300 400 500 600 700 800 9001000 -40 -20 0 20 40 60 80 100 120 140
SWITCHING FREQUENCY (kHz) JUNCTION TEMPERATURE (°C)
VDDA, VDDB Operating Current vs. TJ

Per channel, f = 500kHz, duty cycle = 50%,
VDDA, VDDB Operating Current vs. fSW
CLOAD = 100pF Per channel, duty cycle = 50%
3.5 3.5
IVDDA, IVDDB (mA)
3.0
3.0
IVDDA, IVDDB (mA)
2.5
2.5
2.0
2.0
1.5
1.5 VDDA/VDDB=12V VDDA/VDDB=12V

1.0
VDDA/VDDB=15V VDDA/VDDB=15V
1.0 0.5
-40 -20 0 20 40 60 80 100 120 140 0 100 200 300 400 500 600 700 800 9001000
JUNCTION TEMPERATURE (°C) SWITCHING FREQUENCY (kHz)

TYPICAL CHARACTERISTICS (continued)

Logic Input High/Low Threshold vs.
TJ Output Source/Sink Resistance vs. TJ
1.8 2.2
LOGIC INPUT HIGH/LOW
OUTPUT SOURCE/SINK
1.6 1.8
RESISTANCE (Ω)
THRESHOLD (V)
1.4 1.4
1.2 1.0
1.0 VLI_H 0.6 ROUTA/OUTB_H

VLI_L
ROUTA/OUTB_L
0.8 0.2
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Output Peak Source/Sink Current vs.

VDDA/VDDB Supply Voltage Output Rise/Fall Time vs. TJ
5V UVLO version at 5V Miller plateau CLOAD = 1.8nF
6 14
OUTPUT PEAK SOURCE/SINK
OUTPUT RISE/FALL TIME (ns)
5 12
4
CURRENT (A)
10
3
8
2
Source 6 tR
1
Sink tF
0 4
5 10 15 20 25 30 -40 -20 0 20 40 60 80 100 120 140
VDDA, VDDB (V) JUNCTION TEMPERATURE (°C)
Propagation Delay vs. TJ Minimum Pulse Width vs. TJ

50 26
PROPAGATION DELAY (ns)
MINIMUM PULSE WIDTH (ns)
48 24
46 22
44 20
tPDLH
42 tPDHL 18
tPDEN
tPDDIS
40 16
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140

TYPICAL CHARACTERISTICS (continued)

Pulse-Width Distortion vs. TJ Propagation Delay Matching vs. TJ

tPDLH - tPDHL tPDA - tPDB
3 3
PULSE-WIDTH DISTORTION
PROPAGATION DELAY
2 2
MATCHING (ns)
1 1
(ns)
0 0
-1 -1
tPDM_R
tPDM_F
-2 -2
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140

TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested on the evaluation board, VDDI - VGNDI = 5V, VDDA - VSSA = VDDB -
VSSB = 12V, CLOAD = 0pF, TA = 25°C, all voltages with respect to the corresponding ground(s),
unless otherwise noted.
Typical Switching Waveform
CH1: VINA
CH2: VINB
CH3: VOUTA
CH4: VOUTB

DYNAMIC PARAMETERS DEFINITIONS

tR tF
90% 90%
OUTA/OUTB
10% 10%
Figure 1: Output Rising and Falling Time
INA/INB
0
DIS
50% 50%
EN
90%
tPDEN
tPDDIS
OUTA/OUTB
10%
Figure 2: Enable/Disable Response Time
50% 50%
INA/INB
tPDLHA
90%
OUTA tPDHLA
10% tPWDA = |tPDLHA - tPDHLA|
tPDM_F
tPDM_R
90%
tPDLHB tPDHLB
OUTB
tPWDB = |tPDLHB - tPDHLB|
10%
tPDM_R = |tPDLHA - tPDLHB| tPDM_F = |tPDHLA - tPDHLB|

Figure 3: Propagation Delay Matching and Pulse-Width Distortion

DYNAMIC PARAMETER DEFINITIONS (continued)

VDDI_UVLO_HYS
VDDI
VDDI_UVLO VDDA_UVLO_HYS ,
VDDB_UVLO_HYS
VDDA, VDDB VDDA_UVLO,

VDDB_UVLO
INA/INB
0
EN
0
tSHD_VDDA tSTU_VDDA
tSTU_VDDI tSHD_VDDB tSTU_VDDB
tSTU_VDDI 90%
OUTA/OUTB
10% tSHD_VDDI 10% 10%
Figure 4: VDDI and VDDA, VDDB Under-Voltage Lockout (UVLO)

DEVICE FUNCTIONAL MODES

Table 1: Logic Truth Table (18) (19)
Inputs Power Supply Outputs
Notes
INA INB EN DIS VDDI VDDA VDDB OUTA OUTB
L or O L or O H or O L or O P P P L L
L or O H H or O L or O P P P L H Output transition occurs
H L or O H or O L or O P P P H L immediately
H H H or O L or O P P P H H
X X L H P X X L L The chip is disabled
X X X X UP X X L L VDDI is unpowered
X L or O H or O L or O P UP P L L
VDDA is unpowered
X H H or O L or O P UP P L H
L or O X H or O L or O P P UP L L
VDDB is unpowered
H X H or O L or O P P UP H L
Notes:
18) L: Logic low; H: Logic high; O: Open; X: Not applicable; P: Powered; UP: Unpowered, UVLO condition.
19) If VDDI is powered, the output can operate as long as this channel is powered normally.

FUNCTIONAL BLOCK DIAGRAMS
INA VDDO
VDDA
Isolation
OUTA
Barrier
UVLO
VDDI VDDI
VDDI VSSA
UVLO
GNDI
VDDI
EN VDDO
VDDB
Isolation
OUTB
Barrier
UVLO
INB
VSSB
Figure 5: Functional Block Diagram (MP18851-4x, Enable Control Logic)
INA VDDO
VDDA
Isolation
OUTA
Barrier
UVLO
VDDI VDDI
VDDI VSSA
UVLO
GNDI
DIS VDDO
VDDB
Isolation
OUTB
Barrier
UVLO
INB
VSSB
Figure 6: Functional Block Diagram (MP18851-A4x, Disable Control Logic)

OPERATION
The MP18851 is an isolated, dual-input control, If the INA/INB inputs are left open, they are
independent dual-channel gate driver solution forced logic low via the internal pull-down
with 4A peak output current capability. This IC resistors. This configuration ensures that the
is designed to drive power switching devices corresponding output remains low if the control
with a short propagation delay and minimal input is not connected. If either logic input pin
pulse-width distortion. These advanced features (INA or INB) is not being used, it is
enable high efficiency, high power density, and recommended to externally connect it to ground
robustness in a wide variety of power for better noise immunity and stable operation.
applications.
Similarly, for on/off control, the EN pin is tied to
See Table 1 on page 21 for device functional VDDI via the internal pull-up resistor, while the
modes. DIS pin is connected to GNDI via the internal
pull-down resistor. Although leaving the EN/DIS
Under-Voltage Lockout (UVLO)
pins floating does allow the chip to operate
Under-voltage lockout (UVLO) is implemented normally after start-up, it is recommended to
to avoid the chip or certain blocks from provide a stable external signal input for on/off
operating at insufficient supply voltage. The control in actual applications.
MP18851 incorporates internal UVLO
comparators for all of the input and output Output Stage
supply circuit blocks to monitor the VDDI, The MP18851’s output stage is comprised of an
VDDA, and VDDB voltages (VDDI, VDDA and upper P-channel MOSFET and a lower N-
VDDB, respectively). Figure 4 on page 20 shows channel MOSFET (see Figure 7). The effective
the input and output supply UVLO time output pull-up source resistance
sequence diagram. (ROUTA_H/ROUTB_H) is the on resistance of the
upper P-channel MOSFET, which delivers the
If the input bias voltage (VDDI) is unpowered or
large peak source current during the external
under the UVLO threshold, the chip is not
power switch turn-on transition. The pull-down
enabled and the output stages do not receive
structure is an N-channel MOSFET, for which
control signals from the input stage. The UVLO
the on resistance (ROUTA_L/ROUTB_L) is the output
mechanism holds the output forced low,
effective pull-down impedance when the device
regardless of the present logic levels of the
is driven low.
input signals (including EN/DIS and INA/INB).
If either output stage of the driver is unpowered VDDA/
VDDB
or below its UVLO threshold, the corresponding RPP_H ROUTA_H
channel’s output is also pulled low. As long as /ROUTB_H
either channel is powered normally, the
corresponding channel can accept the related Drive
Output OUTA/
Signal
control signal. Driver OUTB
UVLO Control RPP_L
Input Stage and On/Off Control
ROUTA_L
All of the control input pins (EN/DIS and /ROUTB_L
INA/INB) can accept a TTL/CMOS compatible VSSA/
VSSB
logic input that is reliably isolated from each
output. These control pins can easily be driven Figure 7: Output Stage
with common logic-level signals from a digital
controller. However, any input signal applied to The output stage is optimized to provide strong
these control pins must never exceed the input driving capacity to a power device during the
stage supply VDDI. Therefore, it is recommended Miller plateau interval of the on/off switching
to tie VDDI to the same power supply as the procedure.
control signal sources. The control logic for EN,
INA, and INB are active high, while the control
logic for DIS is active low.

The MP18851 is capable of delivering 4A peak

source/sink current pulses. The rail-to-rail VPWM
output ensures that the voltage switches
between VDDA/VDDB and VSSA/VSSB, respectively.
Common-Mode Transient Immunity (CMTI)
VGS
Common-mode transient immunity (CMTI) is
one of the key characteristics that determines
an isolator’s robustness, and is especially VSW
important in high-voltage applications that
utilize devices with fast transient response (e.g. Figure 9: Abnormal Pulse Caused by Coupled
SiC/GaN FET). When a power device is Noise if dv/dt > CMTI
switching, the high slew rate dv/dt or di/dt
CMTI is defined as the maximum tolerable rate-
transient noise can corrupt the signal
of-rise (or fall) of a common-mode voltage
transmission across the isolation barrier (see
applied between two isolated circuits, given in
Figure 8 and Figure 9).
volts per second (V/ns or kV/µs). Below the
Isolation VBUS
maximum slew rate of a common-mode
VDDI Barrier VDDO voltage, the isolator’s output remains at the
specified logic level and timing.
VGS
VPWM Figure 10 shows the CMTI test set-up to
VSW
measure the CMTI of a coupler in both static
and dynamic operation, under the specified
common-mode pulse magnitude (VCM), the
specified slew rate for the common-mode pulse
(dVCM/dt), and other specified test or ambient
Figure 8: High Slew Rate Transient Noise conditions. The isolator’s output should remain
Coupling Path
in the correct state as long as the pulse
magnitude and the slew rate meet the relevant
CMTI specifications.
Powered by
Tie to a stable level Battery B
VDDO
to keep the chip
operating normally EN/DIS VDDA
Static: INA OUTA

Tie to VDDI or GNDI C2
Dynamic:
INB VSSA Oscilloscope
High-frequency PWM
Powered by VDDO
Battery A VDDI
VDDB
VDDI
VDDI OUTB
C1
C3
GNDI VSSB
+ VCM -
HV High dv/dt
Generator
Figure 10: CMTI Test Set-Up

APPLICATION INFORMATION
Selecting the VDDI Capacitor Channel B is powered by a separate supply.
The VDDI capacitor reduces the surge current Because the VDDB capacitor (CVDDB) must
drawn from the input supply, and supports support CVDDA’s charging current via the
current consumption for the primary logic bootstrap circuit, a bypass capacitor with
interface and transmitter block. Since the input greater capacitance can be chosen (e.g. a 10µF
side’s operating current is only a few mA, a ceramic capacitor). It is recommended to place
100nF ceramic capacitor with X5R or X7R a secondary, high-frequency, 100nF bypass
dielectrics is strongly recommended due to its capacitor in parallel.
low ESR and small temperature coefficients. Selecting the Bootstrap Diode and Series
For most applications, if the real supply power Resistor
is far away from the VDDI pin then it is
A bootstrap configuration is often applied to
recommended to add a >1µF bypass capacitor
power the HS driver in a half-bridge converter.
in parallel with this 100nF ceramic capacitor.
The bootstrap capacitor (CBST) is charged
Selecting the VDDA/VDDB Capacitor through the bootstrap diode and series resistor
The VDDA/VDDB capacitor is the bypass during the low-side (LS) turn-on interval. The
capacitor for the output gate driver. It supports diode loads the high reverse voltage (greater
current consumption for the driving control than bus voltage) during the LS turn-on interval.
block, maintains a stable driving voltage, and To reduce the conduction losses and reverse
supports up to 4A of transient source current. recovery losses, a high-voltage, fast recovery
diode or Schottky diode is recommended.
Given that the allowable VDDA/VDDB voltage
ripple is ΔVDDA/VDDB, and guarantees that the A bootstrap series resistor (RBST) is also
driver supply voltage cannot drop close to the recommended used to limit the inrush charging
UVLO level, the minimum VDDA/VDDB current, which can generate a spike on the
capacitance (CVDDA/VDDB) can be calculated with VDDA pin. It is recommended that RBST not
Equation (1): exceed 10Ω. The estimated peak charging
current can then be calculated with Equation (2):
1
IVDDA / VDDB  + QG VDDA / VDDB − VD _BST
CVDDA / VDDB =
fSW
(1) IBST = (2)
VDDA / VDDB RBST
Where IVDDA/VDDB is the VDDA/VDDB operating Where VD_BST is the forward voltage drop of the
current, fSW is the switching frequency, and QG bootstrap diode, and RBST is the bootstrap
is the power device’s gate charge. series resistor.
Keep in mind that the loop resistance, voltage Selecting the Input Filter for INA/INB
drop, and DC bias voltage ripple impact the The INA/INB input filter is not necessary in
supply voltage. Especially for channel A, which theory because the low-pass filter slows the
usually operates as the high-side (HS) driver in PWM signal’s rising/falling edge and affects the
a half-bridge converter and is powered by a propagation delay. However, if there is
bootstrap circuit, too high of a VDDA significant high-frequency ringing introduced by
capacitance (CVDDA) is not recommended as it the PCB traces, it is recommended to add a
may lead to issues, such as not charging simple RC filter at the input close to the
quickly enough at system power-up or during INA/INB pins.
the bootstrap cycle, or VDDA remaining stay To avoid increasing the input resistance, a
below its UVLO threshold and failing to power resistor below 100Ω is typically recommended.
the HS driver. A 1µF capacitor is typically When selecting the filter capacitor, ensure that
recommended for channel A. If channel A is the filter’s cutoff frequency is at least ten times
powered by a special supply, a higher CVDDA greater than fSW, a capacitance of dozens of pF
can be selected. is typically sufficient.

Selecting the External Driving Resistor is the smaller value between the estimated
The external driving resistor can be applied to IOUTA_SRC/OUTB_SRC or IOUTA_SNK/OUTB_SNK and 4A.
limit the ringing noise on the driving signal and Estimated Gate Driver Power Loss
adjust the switching speed to improve EMI
The total gate driver power loss is used to
performance. However, a greater driving
estimate the thermal performance. The
resistance increases switching losses, reduces
MP18851 must operate under the safety limiting
system efficiency, and can introduce thermal
values (see the Safety Limiting Values section
issues. In actual applications, the turn-on and
on page 13 for more details).
turn-off speeds can be adjusted the respective
driving resistors. Place the sink resistor in To estimate the gate driver power loss, first
series with an anti-parallel diode, and keep it calculate the chip’s operation power
separate from the source resistor. The total consumption (POP) using Equation (7):
driving resistance when pulling the power
POP = VDDI  IVDDI + VDDA  IVDDA + VDDB  IVDDB (7)
device low is sum of the sink resistor placed in
parallel with the source resistor. The gate driver’s self-power consumption is
The peak driving current can be used to related to fSW and the supply voltage. For the
evaluate the effect of the driving resistors. relationship reference between the input and
Without a driving resistor, the MP18851 can output channels’ current consumption vs. the
drive up to 4A of peak source and sink currents. operating frequency, see the Typical
Characteristics section on page 15.
Considering the driving resistor, the peak
source driving current for outputs A and B can Next, consider the gate driver power loss during
be calculated with Equation (3) and Equation switching operation. As a conventional totem-
(4), respectively: pole (TP) gate driver, each channel of the
MP18851 charges and discharges the power
VDDA device’s gate capacitance once during every
IOUTA _ SRC = (3)
ROUTA _H + RG _ SRC + RG(INT) switching cycle.
VDDB During the charging and the discharging period,

IOUTB _ SRC = (4) the total energy is supplied by VDDA/VDDB. If
ROUTB _H + RG _ SRC + RG(INT) there is no external gate driver resistor, the
power dissipation (PSW) can be calculated with
The peak sink driving current for outputs A and
Equation (8):
B can be calculated with Equation (5) and
Equation (6), respectively:  tON tON

PSW =  VDDA   iGA (t)dt + VDDB   iGB (t)dt   fSW
VGSA _ ON  
 
IOUTA _ SNK =
0 0
(5)
ROUTA _L + RG _ SRC || RG _ SNK + RG(INT)
= ( VDDA + VDDB )  QG  fSW (8)
VGSB _ ON Where tON is the turn-on time, and IGA/GB(t) is the
IOUTB _ SNK = (6)
ROUTB _L + RG _ SRC || RG _ SNK + RG(INT) driving current.
Where RG_SRC is the external source resistor, The behavior of the external source/sink
RG_SNK is the external sink resistor, RG(INT) is the resistors adds complexity to the dynamic power
power device’s internal gate resistance, and dissipation estimation.
VGSA_ON/VGSB_ON is the power device’s stable If the driving current is not saturated to 4A
gate-source voltage during the turn-on interval. within one switching cycle with external gate
VGSA_ON/VGSB_ON should typically be close to resistors, then PSW is shared between the gate
VDDA/VDDB. driver’s internal source and sink resistances
and the external gate driver resistors, based on
Since the driving current cannot exceed 4A, set the ratio of these series resistances. In this
the actual peak driving current to be whichever circumstance, PSW can be calculated with
Equation (9) on page 27:

VDDA  QG  fSW  ROUTA _ H ROUTA _ L 

PSW =  + 

2  ROUTA _ H + RG _ SRC + RG(INT ) ROUTA _ L + RG _ SRC || RG _ SNK + RG(INT ) 
(9)
V  QG  fSW  ROUTB _ H ROUTB _ L 
+ DDB  + 
R
2  OUTB _ H + RG _ SRC + RG(INT ) ROUTB _ L + RG _ SRC || RG _ SNK + RG(INT ) 
Where tON_SAT/OFF_SAT is the turn-on/off time with In some conditions, the MP18851 outputs the
a saturated 4A current output, and VGSA/GSB(t) is saturated 4A current at the beginning of the
the power device’s gate voltage during this turn-on/off interval. During this saturation time,
saturation time. the power loss (PSW_SAT) can be calculated with
Equation (10):
t ON _ SAT t OFF _ SAT
PSW _ SAT = 4A   (V
0
DDA − VGSA (t) ) dt + 4A   (V
0
GSA (t) ) dt
t ON _ SAT t OFF _ SAT

(10)
+ 4A   (V
0
DDB − VGSB (t) ) dt + 4A   (V
0
GSB (t) ) dt
The actual power loss is the sum of Equation (9) Multiply PLOSS by the junction-to-ambient
and Equation (10). Therefore, the total power thermal resistance (θJA) to determine the
loss dissipated in the MP18851 (PLOSS) can be junction temperature rise above the ambient
calculated with Equation (11): temperature (TA). Ensure that the junction
temperature (TJ) is below the maximum safety
PLOSS = POP +PSW (11)
temperature (TS).

PCB Layout Guidelines effective but can lead to the board being
Efficient PCB layout is critical for stable easily twisted.
operation. For the best results, refer to Figure 8. If the driver chip is used in a half-bridge
11 and follow the guidelines below: configuration, keep enough space and
1. Place the bypass/decoupling capacitors as maximize the creepage distance between
close as possible to the VDDI/VDDA/VDDB the dual channels.
supply pins and the corresponding grounds.
For each supply pin, it is recommended to
add a low-ESR/ESL, high-frequency, 100nF
bypass capacitor.
2. If an input RC filter is used, it is
recommended to place this filter close to the
corresponding control pin.
3. Place the high-current paths (e.g. the supply
path, drive path, and the connection
between the external power device source
and the VSSA/VSSB pins) very close to the
driver chip with short, direct, and wide
traces to minimize parasitic inductance and
avoid large transients and ringing noise.
4. It is strongly recommended to place large
power and ground planes or use multiple Top Layer
ground layers to help dissipate heat from
the gate driver chip to the PCB and improve
the thermal performance. Be careful when
splitting the traces or coppers to allow
sufficient insulation distance between the
low-/high-voltage planes.
5. Keep the driving loop from OUTA/OUTB to
the power device’s gate-to-source to
VSSA/VSSB short and with a minimal area.
Avoid placing the driving trace across
different PCB layers through vias, as it can
introduce parasitic inductance. Place the
driver IC as close as possible to the power
device.
6. Use the recommended land pattern design
for each package type to ensure adequate
insulation space between the primary and Bottom Layer
secondary sides. Avoid placing any Figure 11: Recommended PCB Layout (20)
components, tracks, or copper below the Note:
chip’s body in any PCB layer. 20) This example uses a 2-layer PCB layout with the SOIC-16
WB package.
7. A board cutout under the chip is not always
necessary, but is recommended for the
SOIC-16 package options to extend the
creepage distance on the PCB surface. The
LGA package’s bottom side is pressed on
the PCB surface, so the PCB cutout is not

TYPICAL APPLICATION CIRCUIT

R1
D1 NS
2 1
SMA 0805
TP1 TP2
INA
VDDA J2 VDDB J3
INA VDDA VDDB
2
TP3
INA C1
VDDA C2
VDDB
JP1 VDDI OUTA_G OUTB_G
R2 OUTA OUTB
1
0Ω 0.1µF 0.1µF
GNDI GNDI 1
INA
2
3 C5
C3
10µF/50V
VSSA C4
10µF/50V
VSSB
Jumper NC 1206 VSSA 1206 VSSB
GNDI
GNDI GNDI
JP2 VDDI R3 D2
0Ω GNDI
1 U1 TP4
2
INB R4 NS SOD-123 OUTA_G
VDDA 2 1
INB
3 C6 TP5 1 16
TP6
INB Jumper NC INB INA VDDA OUTA 0805
GNDI OUTA_G
R5 0Ω
TP7 2 15
L1 INB OUTA
J7 VDDI GNDI
2
BLM18BB050SN1D VDDI 0805 Q2 Q1
TP8 C7 Q5
VDDI 1 2 VDDI 3 14
2
VDDI VSSA VSSA NS TO-220 D2-PACK TO-247

C8 C9
1
C10 0805
10µF/10V MP18851
GNDI 1µF/10V 0.1µF 4 13 VSSA
1
0805 GNDI NC
VSSA
TP9
GNDI R6 EN/DIS5
GNDI 12 D3
JP3 EN/DIS NC TP10
VDDI
0Ω R7 NS SOD-123 OUTB_G
EN/DIS VDDB 2 1
EN/DIS 1
EN/DIS 6 11
TP12
2 NC VDDB OUTB 0805
3 OUTB_G
R8 0Ω
Jumper 7
NC OUTB
10
GNDI
2
GNDI GNDI
VDDI
8 9
TP13
0805
C12 Q4 Q3 Q6
VDDI VSSB VSSB NS TO-220 D2-PACK TO-247
1
0805
GNDI GNDI
VSSB
VSSB
GNDI GNDI
Figure 12: Typical Application Circuit

PACKAGE INFORMATION
SOIC-16 WB (HV ISOLATION)

PACKAGE INFORMATION (continued)

SOIC-16 NB (HV ISOLATION)

PACKAGE INFORMATION (continued)

LGA-13 (5mmx5mm)

CARRIER INFORMATION
SOIC-16 NB AND SOIC-16 WB
Pin1 1 1 1 1
ABCD
ABCD
ABCD
ABCD
Feed Direction
Package Quantity/ Quantity/ Reel Carrier Carrier

Part Number
Description Reel Tube Diameter Tape Width Tape Pitch
MP18851-4AGSE-Z
MP18851-4BGSE-Z
MP18851-4CGSE-Z
MP18851-4DGSE-Z
MP18851-4EGSE-Z
SOIC-16 NB 2500 50 13in 16mm 8mm
MP18851-A4AGSE-Z
MP18851-A4BGSE-Z
MP18851-A4CGSE-Z
MP18851-A4DGSE-Z
MP18851-A4EGSE-Z
MP18851-4AGY-Z
MP18851-4BGY-Z
MP18851-4CGY-Z
MP18851-4DGY-Z
MP18851-4EGY-Z
SOIC-16 WB 1000 47 13in 24mm 12mm
MP18851-A4AGY-Z
MP18851-A4BGY-Z
MP18851-A4CGY-Z
MP18851-A4DGY-Z
MP18851-A4EGY-Z

CARRIER INFORMATION (continued)

LGA-13 (5mmx5mm)
Pin1 1 1 1 1
ABCD ABCD ABCD ABCD
Feed Direction
Package Quantity/ Quantity/ Reel Carrier Carrier

Part Number
Description Reel Tube Diameter Tape Width Tape Pitch
MP18851-4AGLU-Z
MP18851-4BGLU-Z
MP18851-4CGLU-Z
MP18851-4DGLU-Z
MP18851-4EGLU-Z LGA-13
5000 N/A 13in 12mm 8mm
MP18851-A4AGLU-Z (5mmx5mm)
MP18851-A4BGLU-Z
MP18851-A4CGLU-Z
MP18851-A4DGLU-Z
MP18851-A4EGLU-Z

REVISION HISTORY
Revision # Revision Date Description Pages Updated
1.0 7/26/2022 Initial Release -
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.


MP 18851

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MP18851

Isolated, Dual-Input Control,

MP18851 Rev. 1.0 MonolithicPower.com 1

MP18851 Rev. 1.0 MonolithicPower.com 2

ORDERING INFORMATION (1)

MP18851 Rev. 1.0 MonolithicPower.com 3

MPS: MPS prefix

MPS: MPS prefix

MP18851 Rev. 1.0 MonolithicPower.com 4

MP18851 Rev. 1.0 MonolithicPower.com 5

SOIC-16 NB, SOIC-16 WB

MP18851 Rev. 1.0 MonolithicPower.com 6

MP18851 Rev. 1.0 MonolithicPower.com 7

ABSOLUTE MAXIMUM RATINGS (2) Thermal Resistance (5) θJA θJC

MP18851 Rev. 1.0 MonolithicPower.com 8

MP18851 Rev. 1.0 MonolithicPower.com 9

ELECTRICAL CHARACTERISTICS (continued)

MP18851 Rev. 1.0 MonolithicPower.com 10

ELECTRICAL CHARACTERISTICS (continued)

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INSULATION AND SAFETY-RELATED SPECIFICATIONS

MP18851 Rev. 1.0 MonolithicPower.com 12

INSULATION AND SAFETY-RELATED SPECIFICATIONS (continued)

SAFETY LIMITING VALUES (14)

MP18851 Rev. 1.0 MonolithicPower.com 13

THERMAL DERATING CURVES FOR SAFETY LIMITING VALUES

SAFETY LIMITING POWER

SAFETY LIMITING POWER

MP18851 Rev. 1.0 MonolithicPower.com 14

VDDI Operating Current vs. fSW VDDA/VDDB Quiescent Current vs. TJ

2.01 VDDI=3.3V 0.85

VDDA, VDDB Operating Current vs. TJ

1.5 VDDA/VDDB=12V VDDA/VDDB=12V

MP18851 Rev. 1.0 MonolithicPower.com 15

TYPICAL CHARACTERISTICS (continued)

1.0 VLI_H 0.6 ROUTA/OUTB_H

Output Peak Source/Sink Current vs.

OUTPUT RISE/FALL TIME (ns)

Propagation Delay vs. TJ Minimum Pulse Width vs. TJ

MINIMUM PULSE WIDTH (ns)

MP18851 Rev. 1.0 MonolithicPower.com 16

TYPICAL CHARACTERISTICS (continued)

Pulse-Width Distortion vs. TJ Propagation Delay Matching vs. TJ

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TYPICAL PERFORMANCE CHARACTERISTICS

Typical Switching Waveform

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DYNAMIC PARAMETERS DEFINITIONS

Figure 1: Output Rising and Falling Time

Figure 2: Enable/Disable Response Time

tPDM_R = |tPDLHA - tPDLHB| tPDM_F = |tPDHLA - tPDHLB|

MP18851 Rev. 1.0 MonolithicPower.com 19

DYNAMIC PARAMETER DEFINITIONS (continued)

VDDA, VDDB VDDA_UVLO,

10% tSHD_VDDI 10% 10%

Figure 4: VDDI and VDDA, VDDB Under-Voltage Lockout (UVLO)

MP18851 Rev. 1.0 MonolithicPower.com 20

DEVICE FUNCTIONAL MODES

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