Digital Logic, Positive Logic, Negative logic

Digital Logic
Electronic circuits are divided into two categories, digital and analog. An analog quantity varies
continuously and digital quantities only have discrete values. Digital systems can process,
store, and transmit data more efficiently. But it can only assign discrete values. Many systems
use a mix of analog and digital signals. For example, a CD player accepts digital data from the
CD drive and converts it to an analog signal.
Positive Logic and Negative logic
In the binary system, the digits 1 and 0 are called binary digits. To represent these two bits, we
use two different voltage levels. These voltages are called logic levels.
Generally higher voltage HIGH represents 1 and low voltage LOW represents 0. This is called
positive logic.
Another system that represents 1 with LOW and 0 with HIGH is called negative logic.
In a practical digital circuit, however HIGH and LOW can be any voltage between a specified
minimum and maximum voltages.
Further Reading
10.4 Positive Logic, Negative logic
POSITIVE AND NEGATIVE LOGIC: TPUB

Basic Logic Gates (NOT, AND, OR, XOR and X-

NOR)
Logic tells you a certain proposition is true if several conditions are true. Logic is applied in a
digital circuit to implement logic functions. Circuits that performs logic operations specified are
called logic gates.
There are three basic logic operations
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NOT
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AND
OR
These are indicated by following shape symbols

The lines connected to the left side of each symbol are inputs and line on the right is output. In
logic operations, the conditions mentioned earlier are represented by HIGH and LOW. Each of
the logic operations produces a unique result for a given set of conditions.
NOT
The NOT operation inverts the logic level. When the input is HIGH the output will be LOW.
When the input is LOW the output will be HIGH. Logic circuit inverter is used to implement NOT
operation.

In Boolean algebra complement of a variable is represented by a bar over a digit. The two
possible input-output combinations of an inverter(not gate) are,

This operation of an inverter(not gate) is summarized in the following table which shows the
output for each possible inputs. This is called a truth table.
INPUT A OUTPUT (Ā)
LOW 0 HIGH 1
HIGH 1 LOW 0

AND
 An AND gate is composed of a single output and multiple inputs. The AND operation produces
HIGH output only when all of its inputs are HIGH. When any or all inputs are LOW, then the
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output is LOW. The basic purpose of AND gate is to determine whether all conditions are
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simultaneously true.

In Boolean expression AND operation is represented either by placing a dot ( . ) between the
variables or by writing the variables together. The four possible input-output combinations of a
two-input AND gate are,

Operation of an AND gate is described in the truth table.

INPUT A INPUT B OUTPUT A.B
LOW 0 LOW 0 LOW 0
LOW 0 HIGH 1 LOW 0
HIGH 1 LOW 0 LOW 0
HIGH 1 HIGH 1 HIGH 1

OR
An OR gate is composed of a single output and multiple inputs. The OR operation produces
HIGH output when any of its inputs are HIGH. The output is LOW only if both of the inputs are
LOW.

The logical OR function is represented by placing a plus (+) in between the variables. The four
possible input-output combinations of a two-input OR gate are,
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The truth table of an OR gate is given below.
INPUT A INPUT B OUTPUT A B
LOW 0 LOW 0 LOW 0
LOW 0 HIGH 1 HIGH 1
HIGH 1 LOW 0 HIGH 1
HIGH 1 HIGH 1 HIGH 1

XOR and X-NOR Gates

Exclusive-OR (XOR)
The XOR gate has only two inputs. The output of an XOR gate is only HIGH when the two inputs
are at different logic levels. That is, if X is the output then X is HIGH when input A is HIGH and B
is LOW or when input A is LOW and B is HIGH.

XOR operation is represented by a + symbol with a circle around it. The four possible input-
output combinations of XOR gate is,

This operation can be summarized in the truth table.

INPUT A INPUT B OUTPUT A XOR B
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INPUT A INPUT B OUTPUT A XOR B
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LOW 0 LOW 0 LOW 0
LOW 0 HIGH 1 HIGH 1
HIGH 1 LOW 0 HIGH 1
HIGH 1 HIGH 1 LOW 0
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Exclusive-NOR
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Like XOR gate the XNOR gate also has only two inputs. The bubble on the right side of the
XNOR symbol indicates that the output is opposite of XOR gate.

The output of an XNOR gate is only HIGH when the two inputs are at same logic levels. That is,
if X is the output then X is HIGH when both A and B is HIGH or both A and B is LOW.

The operation is summarized in the truth table.

INPUT A INPUT B OUTPUT A XNOR B
LOW 0 LOW 0 HIGH 1
LOW 0 HIGH 1 LOW 0
HIGH 1 LOW 0 LOW 0
HIGH 1 HIGH 1 HIGH 1

Further Reading
Basic Logic Gates – Types, Functions | Byjus
Basic Logic Gates with Truth Table | Elprocus
 Universal gates (NAND and NOR gate)
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The NAND and NOR gates are called universal gates. That is universal gates can be used in
combination to perform the AND, OR and inverter operations.
NAND
The term NAND implies the function of an AND gate with an inverted output. The logic symbol
of NAND gate is equivalent to an AND gate followed by an inverter. NAND operation is
represented by a bar over the AND expression.

The NAND gate produces a LOW output only when all of its inputs are HIGH. That is for a two-
input NAND gate OUTPUT, X is LOW when both inputs A and B are HIGH. X is HIGH if either A
or B is LOW, or when both are LOW.

This operation is described in the truth table.

INPUT A INPUT B OUTPUT X
LOW LOW HIGH
LOW HIGH HIGH
HIGH LOW HIGH
HIGH HIGH LOW

Implementation of Logic Operations Using NAND Gate only

All logic gates can be implemented using NAND gate only.
NOT using NAND gate only
OR using NAND gate only

AND using NAND gate only

NOR using NAND gate only

NOR
The term NOR implies the function of an OR gate with an inverted output. The logic symbol of
NOR gate is equivalent to an OR gate followed by an inverter. NOR operation is represented by
a bar over the OR expression.

The NOR gate produces a LOW output when any of its inputs are HIGH. That is for a two-input
NAND gate OUTPUT, X is LOW when either input A or B is HIGH or when both A and B is HIGH.
X is HIGH only when both A and B is LOW
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The operation is summarized in the following truth table.
INPUT A INPUT B OUTPUT X
LOW LOW HIGH
LOW HIGH LOW
HIGH LOW LOW
HIGH HIGH LOW

Implementation of Logic Operations Using NOR Gate only

Since NOR gate is a universal gate, its combination can be used to implement any other logic
operation.
NOT using NOR gate only

OR using NOR gate only

AND using NOR gate only

NAND using NOR gate only

Further Reading
Universal Gates: NAND and NOR | UOP
Universal Gates | Gate Vidyalay

Half Adder
Recall laws of binary addition,
0+0=0
0+1=1
1+0=1
1 + 1 = 10
Half adder is a logical circuit that is used to perform this operation. It accepts two binary digits
as input and produces two binary digits, a sum and a carry, in its output. The logic symbol of a
half adder is given below.

The truth table of a half adder is given below.

A B ∑ COUT
0 0 0 0
0 1 1 0
1 0 1 0
 A B ∑ COUT
1 1 0 1
The expressions for Sum and Carry can be generated from the following K Maps.
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Observe that the value of Cout is 1 only when both inputs A and B are 1. Therefore Cout can be
implemented as AND of two variables.
Cout = AB
Now notice that the value of Sum (∑) is 1 only when inputs A and B are not equal. Therefore the
Sum can be expressed as XOR of two variables.
∑ = A⊕B

From these equations, we can implement the logic circuit required for a half adder. The Sum is
generated with an XOR gate with two inputs A and B, and the Carry is generated with an AND
gate.

Further Reading
Half Adder in Digital Logic | Geeks for Geeks
Hald Adder theory and circuit | Circuits Today

Half Subtractor
Half subtractor is a combinational circuit that performs subtraction of two bits. It accepts two
binary digits as input and produces two binary digits, a difference and a borrow, in its output.
The logic symbol of half subtractor is given below.

Expressions for Difference and Borrow can be derived from the following truth table and K-
Map.
A B D BOUT
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Observe that the value of D is 1 when inputs A and B are at different logic levels. This can be
expressed as XOR of two variables.

Now the value of Bout is 1 only when input A is 0 and input B is 1. That is Bout can be
expressed as

From these equations, we can implement the logic circuit required as follows.
D is generated with an XOR gate with two inputs A and B, and the Bout is generated with an
inverter and an AND gate.
Further Reading
Half Subtractor in Digital Logic | Geeks for Geeks
Half Subtractor Circuit Design | Elprocus

Full Adder
A full adder accepts two input bits and an input carry and generates a sum and a carry, in its
output. The logic symbol of a full adder is,

Truth table of a full adder is given below,

A B CIN ∑ COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
 A B CIN ∑ COUT
1 1 1 1 1
Expression for Sum and Carry can be derived using the following K Map.
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A full adder should add Cout with other input bits A and B. We have used XOR operation to
perform addition of two bits A and B. To add input carry, Cin, with the input bits, it must be
XOR-ed with A⊕B. Logic expression for sum and carry can be derived from the truth table.

The expression for Cout can be simplified into

This means two XOR gates are used to implement full adder sum function. The first will
generate A⊕B and the second will add this output with an input carry Cin. The complete logic
circuit of a full adder will be,

Implementation of Full Adder using Half Adders

A full adder can also be implemented using two half adder as follows.
Further Reading
Full Adder in Digital Logic | Geeks for Geeks
Full Adder | All About Circuits

Full Subtractor
A full subtractor is a combinational circuit that performs subtraction of three bits. This circuit
has three inputs the minuend A, subtrahend B, and borrow in Bin. Bin is the borrow of the
previous adjacent lower minuend bit. This Bin is also subtracted from A-B. A full subtractor has
two outputs, D and Bout, represents Difference and Borrow Out respectively.

Truth table of a full subtractor is,

A B BIN D BOUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
 A B BIN D BOUT
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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The logic expression for full subtractor can be derived from the truth table using the K Map
technique.

Expression for Bout can be again simplified as follows

These expressions can be implemented using two XOR gates, two AND gates and one OR gate
as follows

Further Reading
Full Subtractor in Digital Logic | Geeks for Geeks
Full Subtractor Circuit Design | Elprocus
4 bit Ripple Carry Adder
A full adder can be used to perform addition of two bits with an input carry. To add an N-bit
number, multiple full adder circuits can be cascaded parallelly. Such an arrangement of full
adders is called a parallel adder. N full adders are required to add n bits.
A ripple-carry adder is a parallel adder created by connecting carry output of each full-adder
with the carry input of the next higher-order full-adder. The input carry should occur first to
produce the sum and output carry of any stage (a stage is one full adder); this causes a time
delay in the addition process.
4 bit Ripple Carry Adder
A 4-bit binary ripple-carry adder is shown in the figure.

Full-adder 1 (FA1) cannot produce a potential carry until an input carry is applied. Full-adder
2(FA2) cannot produce a potential output carry until FA1 produces an output carry, Full-adder
3(FA3) cannot produce a potential output carry until FA2 produces an output carry and so on.
That is the input carry has to ripple through all the adders before a final sum is produced. This
causes a time delay in the addition process and is called propagation delay or ripple carry
delay.
Further Reading
Ripple Carry Adder | Circuits Today
4-bit ripple carry adder | Gate Vidyalay

Carry Look Ahead Adders

In a ripple carry adder, the carry from the previous stage should occur first to produce the sum
and output carry of any stage. This causes a time delay in the addition process and is called
propagation delay or ripple carry delay. The look-ahead carry addition is a method used to
speed up the addition process by eliminating the propagation delay. The look-ahead carry
adder anticipates the output carry of each stage.
We define two variables Carry generate, Cg, and Carry propagate, Cp.
Cg occurs when an output carry is generated internally by the full adder. A carry is generated
only when both inputs are 1s. It is expressed as the AND function of the two inputs.
Carry propagation function specifies when a carry-in would be propagated. Cp may be
propagated by the full-adder when either or both of the inputs are 1s. It is hence expressed as
the OR function of the two input bits. We write

The Output carry of a stage can be expressed in terms of Cg and Cp as

That is we get an output carry of 1 if it is generated by the full adder or if the adder propagates
the input carry.
Circuit diagram for a full adder that produces Cg and Cp function is shown below

4 bit Carry Look Ahead Adder

Carry generation and carry propagation in terms of the input bits to a 4-bit adder is shown in
the figure.
We can now write expressions for the output carry Cout of each full adder for the 4-bit example.
Full Adder 1

Full Adder 2

Full Adder 3

Full Adder 4
Observe that the output-carry for each stage is dependent only on the initial input carry Cin1,
the Cg and Cp functions of that stage. Since Cg and Cp can be expressed in terms of A and B
inputs to the full adder, all the output carries are available immediately. So we don’t have to
wait for a carry to ripple through all the stages and there will be no propagation delay.
Further Reading
Carry Look Ahead Adder | Geeks For Geeks
Carry Look Ahead Adder | Wikipedia

Decoders
Decoders are the combinational circuits that detect the presence of some code on its input and
indicate the presence of that code by a specified output. Generally, a decoder has n input lines
and 2n output lines.

Basic binary decoder

Suppose we need to detect the occurrence of binary number 1100 on the input of the circuit.
AND can be used as a decoding element because of AND gate produces HIGH output only
when all of its inputs are HIGH. Now we have to make sure that all inputs to the AND gate are
HIGH when the number 1100 occurs. This can be achieved by inverting last 2 bits. The
corresponding circuit design and logic equations are shown in the figure.
2-bit decoder
A 2-bit decoder (2 to 4-bit decoder) has 2 input lines and 4 output lines. That is, 4 decoding
gates are required to decode all possible combinations of two bits. For any given code on its
input, one of the four output becomes HIGH.

Binary codes corresponding outputs and decoding functions are described in the table.
BINARY OUTPUT
DECIMAL DIGIT DECODING FUNCTION
A0 A1 0 1 2 3
0 0 0 1 0 0 0
1 0 1 0 1 0 0
2 1 0 0 0 1 0
3 1 1 0 0 0 1
logical diagram of 2 to 4 bit decoder is shown in the figure.
3-bit decoder
A 3-bit decoder has 3 input lines and 8 output lines. That is, 8 decoding gates are required to
decode all possible combinations of three bits. For any given code on its input, one of the eight
output becomes HIGH.

Binary codes corresponding outputs and decoding functions are described in the table.
BINARY OUTPUT
DECIMAL DIGIT DECODING FUNCTION
A0 A1 A2 0 1 2 3 4 5 6 7
0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
2 0 1 0 0 0 1 0 0 0 0 0
3 0 1 1 0 0 0 1 0 0 0 0
4 1 0 0 0 0 0 0 1 0 0 0
5 1 0 1 0 0 0 0 0 1 0 0
6 1 1 0 0 0 0 0 0 0 1 0
 BINARY OUTPUT
DECIMAL DIGIT DECODING FUNCTION
A0 A1 A2 0 1 2 3 4 5 6 7
7 1 1 1 0 0 0 0 0 0 0 1
Circuit of a 3 bit decoder is given below,

4-bit decoder
A 4-bit decoder has 4 input lines and 16 output lines. That is 16 decoding gates are required to
decode all possible combinations of four bits. For any given code on its input, one of the
sixteen output becomes HIGH.

Binary codes corresponding outputs and decoding functions are described in the table.
BINARY OUTPUT
DECIMAL DIGIT DECODING FUNCTION
A0 A1 A2 A3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 1 000 0 00000 0 0 0 0 0 0
1 0 0 0 1 0 1 00 0 00000 0 0 0 0 0 0
2 0 0 1 0 0 0 1 0 0 00000 0 0 0 0 0 0
(
BINARY OUTPUT
DECIMAL DIGIT DECODING FUNCTION
A0 A1 A2 A3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
3 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
4 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
5 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
6 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
7 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
8 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
9 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
10 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
11 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
12 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
13 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
14 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
15 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Further Reading
Binary Decoder | Geeks For Geeks
Decoder | Electronics Tutorials

BCD to 7 segment decoder

In BCD Binary Coded Decimal), a binary pattern is used to represent a decimal number. A 7
segment display is used to display hexadecimal numeral by seven LEDs arranged in a definite
pattern as shown in figure (a).
A BCD to 7 segment decoder accepts the BCD code on its input and provide output to drive a 7
segment display.
For example, if the BCD code in the input is 0011 then we have to display decimal 3 on the 7
segment display. From the figure(b) it is clear that to display a 3 on a seven-segment display
we have to enable LEDs a,b,c,d and g. So the output lines should be a=,b=1,g=1,c=1 and d=1.

The truth table for a seven segment decoder is given below,

INPUT OUTPUT
DECIMAL DIGIT DECODING FUNCTION
A0 A1 A2 A3 A B C D E F G
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
 INPUT OUTPUT
DECIMAL DIGIT DECODING FUNCTION
A0 A1 A2 A3 A B C D E F G
9 1 0 0 1 1 1 1 1 0 1 1

Further Reading
BCD to 7 Segment Decoder | Geeks For Geeks
BCD Display | Electronics Tutorials

Encoders
An encoder is a combinational circuit that performs reverse function of a decoder. It accepts 2n
input and produces output in n output lines. This process of generating codes based on the
values of input lines is called encoding.

4 to 2 Line Encoder
A 4 to 2 line encoder consists of 4 input lines and 2 output lines. When any of the input lines
becomes 1, we get corresponding binary at the output lines.

Truth table of 4 to 2 line encoder is,

INPUT OUTPUT
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
 INPUT OUTPUT
0 1 0 0 1 0
1 0 0 0 1 1
From the truth table, we can find logic expressions for A0 and A1 as following,

The circuit diagram for a 4 to 2 line encoder is shown below,

Octal to Binary Encoder

An 8 to 3 line encoder or octal to binary encoder consists of 8 input lines and 3 output lines.
When any of the input lines becomes 1, we get corresponding binary at the output lines.

Truth table of 8 to 3 line encoder is,

INPUTS OUTPUT
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
 INPUTS OUTPUT
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
From the truth table, we can find logic expressions for A0, A1 and A2 as following,

The circuit diagram for a 8 to 3 line encoder is shown below,

Further Reading
Encoder | Tutorials Point
Encoder | Geeks for Geeks

Multiplexers
Multiplexer(MUX) is a device that allows digital signals from several sources to be routed onto a
single line of output. It has several input lines and a single output line. It has also data selector
lines which specifies which input signal has to be switched to the output line. n data selector
lines are required for routing 2n input lines.
4-input Multiplexer
A 4-input multiplexer has two data-selector lines a combination of which are used to select any
of the four data-input lines.
Logic symbol of a 4-input MUX is shown in figure.

If a binary 0 is applied to the data-selector lines, the data on input D0 appear on the data-
output line. If a binary 1 is applied to the data-selector lines, the data on input D1 appear on the
data-output line. If a binary 2 is applied to the data-selector lines, the data on input D2 appear
on the data-output line. If a binary 3 is applied to the data-selector lines, the data on input D0
appear on the data-output line.
This operation is given in the table.
DATA SELECTOR OUTPUT
S1 S0 Y
0 0
0 1
1 0
1 1
From the table it is clear that
is only if and :
is only if and :
is only if and :
is only if and :
The total expression for the data output is
This can be implemented using four 3-input AND gates, a 4-input OR gate, and two inverters
as shown in the figure.

8-input Multiplexer
An 8-input multiplexer has three data-selector lines a combination of which is used to select
any of the eight data-input lines.
Logic symbol of a 8-input MUX is shown in figure.

The operation of 8:1 MUX is described in the truth table.

DATA SELECTOR OUTPUT
S2 S1 S0 Y
0 0 0
0 0 1
0 1 0
 DATA SELECTOR OUTPUT
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The expression for the data output can be derived from the truth table

This can be implemented using eight 4-input AND gates, an 8-input OR gate, and three
inverters.
Higher-Order MUX Using Lower Order MUX
Multiplexers can also be implemented using a set of lower order multiplexers. Construction of
an 8×1 multiplexer using 4×1 and 2×1 multiplexers is shown in the figure.

Further Reading
Multiplexers | Geeks For Geeks
Multiplexers and Multiplexing | Tutorials Point
 Demultiplexers
A demultiplexer(DEMUX performs the reverse operation of a multiplexer. It takes input from
one line and distributes it to a given number of output lines. It is also known as a data
distributor. A demultiplexer with 2n output lines should have n data-selector lines.
1:4 Demultiplexer
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A 1:4 demultiplexer takes input from one line and distributes it to 4 output lines. It has 2 data
selector lines.

The operation of a 1:4 demultiplexer is described in the truth table.

DATA SELECTOR OUTPUTS
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 1 0
1 0 0 I 0 0
1 1 I 0 0 0
The logical expression can be derived from the truth table.

It can be implemented using the following circuit.

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