Pedagogical and Technological University of Colombia

Electronics Engineering School

Digital Electronics 1 Course
Laboratory Exercises
Laboratory Exercise 2
Basic Logic Gates
The purpose of this exercise is to describe the operation, use and sketch the external connections to integrated-circuit
chips AND, OR, NOT and XOR to implement logic circuits.

Introduction
Logic gates are the basic building blocks for forming digital electronic circuitry. A logic gate has one output
terminal and one or more input terminals. Its output will be HIGH (1) or LOW (0) depending on the digital level(s)
at the input terminal(s). Through the use of logic gates, we can design digital systems that will evaluate digital input
levels and produce a specific output response based on that particular logic circuit design. The five basic logic gates
are the AND, OR, NAND, NOR, and inverter.

The NOT Gate

The inverter (NOT circuit) performs the operation called investment or complementation. The inverter changes a
logical level to the opposite level. In terms of bits, change a 1 to a 0, and a 0 to 1.

1
Input Output Input Output

1
Input Output Input Output

(a) Distinctive symbols (b) Rectangular symbols

with denial indicators with polarity indicators
Fig. 1 Standard logic symbols of the inverter door (ANSI / IEEE Standard 91-1984)

When a HIGH level is applied to an inverter's input, a LOW level is presented at its output. When a LOW level is
applied to the input, a HIGH level is displayed on its output. Table below summarizes this operation. This table
shows the output for each possible input in terms of corresponding levels and bits.

TABLE I
INVESTOR TRUTH TABLE
Input Output
Low (0) High (1)
High (1) Low (0)

The figure below shows a circuit that generates the complement to 1 of an 8-bit binary number. The bits of the
binary number are applied to the inputs of the inverter and the complement to 1 is obtained at the outputs.

Binary number
1 1 0 1 0 1 0 0

0 0 1 0 1 0 1 1
Complement to 1
Fig. 2 Example of a circuit that generates the complement to 1 using inverters
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
The AND Gate
The AND gate is one of the basic doors with which all logical functions are constructed. An AND gate can have two
or more inputs and performs the operation known as logical multiplication.

A A &
X X
B B

(a) Distinctive symbol (b) Rectangular symbol, identified

by the AND (&) character
Fig. 3 Standard logic symbols of the AND gate with two inputs (ANSI / IEEE 91−1984 standard)

In an AND gate with two inputs, the output X is a HIGH level if A and B are at HIGH level; and X is a LOW level
if A is a LOW level, or if B is a LOW level, or if A and B are at the LOW level. The figure below illustrates a 2-
input AND gate that indicates the four possible input combinations and the corresponding result for each of them.

Low (0) Low (0)

Low (0) Low (0)
Low (0) High (1)

High (1) High (1)

Low (0) High (1)
Low (0) High (1)
Fig. 4 All possible logical levels for a two-input AND gate

The logical operation of a gate can be expressed by a truth table, in which all the input combinations with the
corresponding outputs are listed, as shown in the Table below for a two-input AND gate. The truth table can be
extended for any number of entries, for any AND gate, regardless of the number of entries, the output is a HIGH
level only when all the inputs are at HIGH level.

The total number of possible combinations of binary inputs to a gate is determined by the following expression:

𝑁 = 2𝑛

Where N is the number of possible input combinations and n is the number of input variables.

TABLE II
TRUTH TABLE OF A TWO-INPUT AND GATE
Inputs Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1

A common application of the AND gate is to enable or allow the passage of a signal (pulse train) from one point to
another at certain times, and inhibit or prevent the passage at other times. The purpose of this circuit is to measure
the frequency of the signal A. The enable pulse has a width of exactly 1 s. When the enable input is at the HIGH
level, signal A passes through the gate to the counter, and when the enable input is at the LOW level, the signal
passing through the gate is prevented.
1s

A
Register decoder
Counter
and frequency display
Enable
1s Zero reset
between enable pulses

Fig. 5 An AND gate that performs the enable / disable function for a frequency counter
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
The OR Gate
The OR gate is another of the basic doors with which all logical functions are built. An OR gate can have two or
more inputs and performs the operation known as logical addition.

A A ≥1
X X
B B
(a) Distinctive symbol (b) Rectangular symbol, identified
by the OR (≥1) character
Fig. 6 Standard logic symbols of the OR gate with two inputs (ANSI / IEEE Standard 91-1984)

In an OR gate, the X output is a HIGH level if either of the inputs, A or B, or both, are at HIGH level; X is a LOW
level if both inputs, A and B, are at the LOW level. The figure below illustrates the logical operation for a two-input
OR gate, indicating the four possible input combinations.

Low (0) Low (0)

Low (0) High (1)
Low (0) High (1)

High (1) High (1)

High (1) High (1)
Low (0) High (1)
Fig. 7 All possible logical levels for an OR gate with 2 inputs

The table below describes the logical operation of an OR gate with two inputs. This truth table can be extended to
any number of entries and, regardless of the number of entries, the output is a HIGH level when one or more entries
are HIGH.

TABLE III
TRUTH TABLE OF A TWO-INPUT OR GATE
Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 1

The figure below shows part of a simplified intruder detection and alarm system. This system could be used in a
room in a house: a room with two windows and a door. The sensors are magnetic switches that produce a HIGH
output level when the door (or windows) is opened and a LOW output level when it is closed. While the windows
and the door are secured, the switches are closed and the three OR door entrances are LOW. When one of the
windows or the door is opened, a HIGH level is generated at the corresponding entrance of the OR door and the
logic door output is set to HIGH. Then the alarm circuit is activated to warn of the intrusion.

A HIGH level
activates the alarm

Door / window HIGH = Open Alarm

open sensors LOW = Closed circuit

Fig. 8 A simplified intrusion detection system that uses an OR gate

Consult description, logical symbol and truth table for XOR, NAND and NOR gates.
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
Using IC Logic gates
AND and OR gates are available as ICs. The IC pin layout, logic gate type, and technical specifications are all
contained in the logic data manual supplied by the manufacturer of the IC. For example, referring to a TTL or a
CMOS logic data manual, we can see that there are several AND and OR gate ICs. To list just a few:

1. The 7408 (74LS08, 74HC08) is a quad two-input AND gate.

2. The 7411 (74LS11, 74HC11) is a triple three-input AND gate.
3. The 7421 (74LS21, 74HC21) is a dual four-input AND gate.
4. The 7432 (74LS32, 74HC32) is a quad two-input OR gate.

In each case, the letters LS stand for the Low-Power Schottky TTL family and the letters HC stand for the High-
Speed CMOS family. For example, the basic part number 7408 refers to an AND gate IC with four (quad) internal
AND gates each having two inputs. The most common TTL version is the 74LS08, and the most common CMOS
version is the 74HC08. They both have exactly the same pin layout and function. Besides the family designation
(LS, HC, etc.), most ICs will have a prefix that specifies the manufacturer. Two examples of this are SN for Texas
Instruments— SN7400 and DM for Fairchild—DM7400. Also, a suffix is added to the end of the part number to
specify the package style. Two examples of this are N for Plastic Dual-In- Line Package (P-DIP)—SN7400N and M
for Small-Outline Integrated Circuit (SOIC)—DM7400M.

Let’s look in more detail at one of these ICs, the 7408 in figure below. The 7408 is a 14-pin DIP IC. The power
supply connections are made to pins 7 and 14. This supplies the operating voltage for all four AND gates on the IC.
Pin 1 is identified by a small indented circle next to it or by a notch cut out between pin 1 and 14.

1 14 Vcc

2 13

3 12

4 11

5 10

6 9

GND 7 8

Fig. 9 The 7408 quad two-input AND gate IC pin configuration

The pin configurations for some other logic gates are shown in figure below.

1 14 Vcc 1 14 Vcc 1 14 Vcc

2 13 2 13 2 13

3 12 3 12 3 12

4 11 4 11 4 11

5 10 5 10 5 10

6 9 6 9 6 9

GND 7 8 GND 7 8 GND 7 8

(a) (b) (c)

Fig. 10 Pin configurations for other popular TTL and CMOS AND and OR gate IC; a) 7411; b) 7421; c) 7432 (74HC32)

Consult the pin configuration for the ICs: 7404, 7432 and 7486.
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
Part I
1. Determine the logical function that describes the operation of the digital circuit shown in figure below.
2. Obtain the truth table from the evaluation of the logical function obtained in 1.
3. Implement the logic circuit shown in figure below, using logic gates.
4. Obtain the truth table from the evaluation of the digital circuit implemented in 3.
5. Compare the results obtained in 2 and 4

A
B
X

Fig. 11 Digital circuit

Part II
A 16-segment display consists of sixteen segments, numbered 0 to 15 or a to u which can be used to display a
character, if you want to display the ‘A,B,C,D’ characters with the first four inputs “000,001,010,011” the bit
patterns that you need to put on the display to show this characters is shown below (note that to turn ON a segment
you need to put logic 0).

A B

M
K N
H C
Input Character A B C D E F G H K M N P R S T U
000 A 0 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0
001 B 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 1
U P 010 C 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1
011 D 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1
… … …
G D
T R
S

F E
(a) (b)
Fig. 12 a) 16-segment display; b) Truth table of a decoder for the characters “A, B, C, D”

Design and implement a circuit to display in the 16-segment each letter of your last name, if the letters no complete
the eight combinations of the input complete this with others characters. Use IC logic gates like as 74LS08, 74LS32
and others as necessary to make the circuit.

Perform the following steps:

1. Obtain the truth table of each character from the input signal.
2. Determine the logical function for each output (A, B, C, D, E, F, G, H, K, M, N, P, R, S, T, U).
3. Simplify the logical functions to get the lowest Boolean expression.
4. Simulate the circuit you designed in Proteus software or any other virtual simulator of digital circuits.to
verify its operation.
5. Implement the digital circuit designed.
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises

Part III

You want to perform a circuit to activate the fire alarm (𝑨) for the evacuation of a building. To do this you have a gas
sensor (𝑮), a smoke sensor (H), and two signals from a thermometer that indicate whether the temperature is higher
than 45°C (𝑻𝟒𝟓) and whether the temperature is greater than 60°C (𝑻𝟔𝟎).

Since sensors sometimes detect smoke and gases that do not always come from fires (e.g. from cigarettes or kitchens),
to avoid false alarms, the A signal will be activated when the following conditions are met conditions:

1) If the temperature is higher than 60ºC, the alarm will always be activated
2) If the temperature is between 45ºC and 60ºC the alarm will be activated only if they have detected gases or fumes
(or both).
3) If the temperature is lower than 45ºC, the alarm will be activated only if gases and fumes are detected

Summary……

𝑮: is equivalent to '0' if GAS resulting from combustion is detected.

𝑯: is considered '0' if SMOKE is detected.
𝑻𝟒𝟓: is equivalent ‘0' if the temperature is higher than 45 º C
𝑻𝟔𝟎: is equivalent ‘0' if the temperature is above 60ºC
Output signal A (alarm) will be activated at low level

Perform the following steps:

1. Obtain the truth table of the alarm signal (A)

2. Determine the logical function of the system.
3. Draw the digital circuit using symbols of the logic gates (logical circuit synthesis).
4. Implement the digital circuit using Proteus software or any other virtual simulator of digital circuits.

Evaluating Part:

In their working groups, you must make a video of a maximum of 10 minutes, supporting the design proposed for the
exercise shown in part III. The procedure should be explained in detail. All exercises must be clearly justified.
Answers without justification, or invalid procedures - will not be considered, or qualified. It is important to attach the
backup simulation