The document discusses various topics related to low power VLSI circuits and systems including run time leakage, methods to minimize body effect, stack effect, factors affecting speed of MTCMOS circuits, adiabatic charging, issues in power gated circuits design, fine and coarse granularity power gating, power gating topologies, battery gap, adiabatic circuits, actual battery capacity, memory effect in batteries, battery-aware task scheduling and battery-efficient traffic shaping and routing.
The document discusses various topics related to low power VLSI circuits and systems including run time leakage, methods to minimize body effect, stack effect, factors affecting speed of MTCMOS circuits, adiabatic charging, issues in power gated circuits design, fine and coarse granularity power gating, power gating topologies, battery gap, adiabatic circuits, actual battery capacity, memory effect in batteries, battery-aware task scheduling and battery-efficient traffic shaping and routing.
The document discusses various topics related to low power VLSI circuits and systems including run time leakage, methods to minimize body effect, stack effect, factors affecting speed of MTCMOS circuits, adiabatic charging, issues in power gated circuits design, fine and coarse granularity power gating, power gating topologies, battery gap, adiabatic circuits, actual battery capacity, memory effect in batteries, battery-aware task scheduling and battery-efficient traffic shaping and routing.
The document discusses various topics related to low power VLSI circuits and systems including run time leakage, methods to minimize body effect, stack effect, factors affecting speed of MTCMOS circuits, adiabatic charging, issues in power gated circuits design, fine and coarse granularity power gating, power gating topologies, battery gap, adiabatic circuits, actual battery capacity, memory effect in batteries, battery-aware task scheduling and battery-efficient traffic shaping and routing.
) DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING Low power VLSI Circuits and System
Unit V
1. What is run time leakage?
A leakage power dissipation continues to take place even when the circuit is not in use. It consumes the power as long as power rail supply is on. Run-time leakage power reduction based on multi-threshold-voltage CMOS (MTCMOS). A leakage power reduction techniques is applied at the time of run time.
2. What are methods adopted to minimize the body effect?
Triple-well technologies Silicon-on-insulator (SoI) technology 3. What is stack effect? When more than one transistor is in series in a CMOS circuit, the leakage current has a strong dependence on the number of turned off transistors. This is known as the stack effect
4. What are the factors that affect the speed performance of an MTCMOS circuit? The width of the sleep control transistors and the capacitances of the virtual power. The sleep transistors should have their widths large enough so that the ON resistances are small. The area penalty is relatively small because this is shared by all the logic gates on a chip
5. What is adiabatic? The term ‘adiabatic’ refers to the thermodynamic processes that exchange no heat with the environment. The electric charge transfer between various circuit nodes can be considered as the process. 6. Draw the adiabatic charging capacitor model
Page 1|5 A capacitor C is charged through a resistor R using a constant current I( t) instead of a fixed voltage Vdd . Here also it is assumed that initially at time t = 0, there is no charge in the capacitor. The voltage across the capacitor Vc ( t) is a function of time
7. Draw the adiabatic charging of NAND and AND gate.
It may be noted that the number of transistors required for the realization of the adiabatic circuit is larger than that of the static CMOS realization of the same function.
8. What is Terminal Voltage-Based Battery Scheduling?
The scheduling algorithm makes use of the state of charge of the battery for battery scheduling model. 9. What is active mode and sleep mode in power gating? An active mode, which is the normal operating mode of the circuit, and a low-power mode when the circuit is not in use. The low-power mode is commonly termed as sleep
Page 2|5 mode. At an appropriate time, the circuit switches from one mode to the other in an appropriate manner such that the energy drawn from the power source is maximized with minimum or no impact on the performance. 10. What are the task scheduling constraint? Task scheduling can be combined with voltage scaling to maximize the amount of charge that a battery can supply subject to the following constraints: Dependency constraint: task dependencies are preserved; Delay constraint: the profile length is within the delay budget; and Endurance constraint: the battery survives all the tasks. 11. List the various issues involved in the design of power-gated circuits Power-gating granularity Power-gating topologies Switching fabric design Isolation strategy Retention strategy Power-gating controller design
12. What is fine granularity and coarse granularity in power gating?
Fine-grained power gating, the power-gating switch is placed locally as part of the standard cell. The switch must be designed to supply the worst case current requirement of the cell so that there is no impact on the performance. A separate sleep control signals are used to control different building blocks such as instruction decoder, execution unit, and memory controller A coarse-grained power gating, a relatively larger block, say a processor or a block of gates is power switched by a block of switch cells. a single sleep control signal is used to power down the entire chip
13. List the power gating topologies
Global power gating
Local power gating
Page 3|5 Switch in cell gating 14. What is meant by battery gab? The advancement of VLSI technology has led to an increase in the number of transistor per die, as the feature size of the transistors has reduced and chip area has increased over the years. As a consequence, the power consumption has also increased. Unfortunately, the battery technology has not been able to maintain the same rate of growth in energy density, It is leading to a widening “battery gap”. i.e The power consumption the circuit based and battery storage in the technology
15. What is adiabatic circuits?
In adiabatic CMOS circuits, the energy consumption is minimized by slowing down the charge transport between the drain and source terminals of the metal–oxide– semiconductor field-effect transistor (MOSFET) switch and recovering the energy without dissipating as heat. A time-varying voltage source ensures the slow charge transport, keeping small potential across the on-resistance encountered by the MOSFET switches. As a
Page 4|5 consequence, adiabatic logic circuits lead to a reduction in power dissipation at the cost of slower speed of operation
16. What is actual capacity in battery driven system?
The actual capacity of a battery is the amount of energy that the battery delivers under a given load, and is usually used (along with battery life) as a metric to judge the battery efficiency of the load system. 17. What is memory effect in battery driven system? Memory effect, also known as battery effect, lazy battery effect, or battery memory, is an effect observed in NiCd and NiMH rechargeable batteries that causes them to hold less charge. It describes one very specific situation in which certain NiCd and NiMH batteries gradually lose their maximum energy capacity if they are repeatedly recharged after being only partially discharge
18. What is Battery-Aware Task Scheduling?
A Study the effect of different load profiles on the actual capacity of the battery. For the first ten experiments, the battery discharge current was kept constant in each 19. What is Battery-Efficient Traffic Shaping and Routing? Network protocols and communication traffic patterns play important roles in determining battery Efficiency and lifetime.
