BUF634A

BUF634A
SBOS948F – FEBRUARY 2019 – REVISED MAY 2021
BUF634A 36-V, 210-MHz, 250-mA Output, High-Speed Buffer

The BUF634A device can be used as a standalone
1 Features open-loop driver, or used inside the feedback loop of
• Pin-Selected Bandwidth: 35 MHz to 210 MHz a precision op amp to provide both high-precision and
• High Output Current: 250 mA large output current drive with improved capacitive
• Slew Rate: 3750 V/µs load drive.
• Low Quiescent Current: 1.5 mA (35-MHz BW)
For low-power applications, the BUF634A device
• Wide Supply Range: ±2.25 V to ±18 V
operates on a 1.5-mA quiescent current with a
• Internal Output Current Limit
250-mA output, 3750-V/µs slew rate, and 35-MHz
• Thermal Shutdown Protection
bandwidth. The device consumes 8.5-mA quiescent
• Available in Packages with Thermal Pad
current in wide-bandwidth mode with a 210-MHz
• Extended Temperature Operation:
bandwidth. The BUF634A is fully protected by an
–40°C to +125°C
internal current limit in its output stage and by thermal
2 Applications shutdown, making the device rugged and easy to use.
• Memory, Semiconductor Testers The BUF634A device is rated to function over the
• Test Equipment extended industrial temperature range of –40°C to
• Headphone Drivers +125°C. The BUF634A comes in three packages: D
• Flight Control Systems (SOIC), DRB (VSON), and DDA (HSOIC). The DRB
• Capacitive Load Drivers (VSON) and DDA (HSOIC) packages have excellent
• Valve Drivers, Solenoid Drivers thermal performance resulting from the thermal pad
• Line Drivers on the bottom side. The DRB package comes in a
very small form factor of 3.0 mm × 3.0 mm, making
3 Description the device a very suitable option for portable and size-
The BUF634A device is a high-performance, high- constrained applications.
fidelity, open-loop buffer that is capable of driving 250
Device Information(1)
mA of output current. The BUF634A is a 36-V device
PART NUMBER PACKAGE BODY SIZE (NOM)
with an adjustable bandwidth of 35 MHz to 210 MHz,
which is accomplished by varying the value of an SOIC (8) 4.90 mm × 3.90 mm
external resistor between the V– and BW pins. BUF634A VSON (8) 3.00 mm × 3.00 mm
HSOIC (8) 4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
100
TJA (°C/W) 4 Layer Board
V+ <JB (°C/W) 4 Layer Board
1 kQ 1 kQ 80 TJA (°C/W) 2 Layer Board
<JB (°C/W) 2 Layer Board
± 60
qC/W
VO
40
VIN
20
Vt 0
0 5 10 15 20 25 30 35
Top layer Cu Area (cm2) D037
Boost the Output Current of Any Operational Thermal Performance vs Cu Area for the DDA
Amplifier Package
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BUF634A
SBOS948F – FEBRUARY 2019 – REVISED MAY 2021 www.ti.com
Table of Contents
1 Features............................................................................1 8.4 Device Functional Modes..........................................15
2 Applications..................................................................... 1 9 Application and Implementation.................................. 16
3 Description.......................................................................1 9.1 Application Information............................................. 16
4 Revision History.............................................................. 2 9.2 Typical Application.................................................... 18
5 Device Comparison Table...............................................3 10 Power Supply Recommendations..............................20
6 Pin Configuration and Functions...................................3 10.1 Power Dissipation and Thermal Considerations..... 20
7 Specifications.................................................................. 4 11 Layout........................................................................... 21
7.1 Absolute Maximum Ratings ....................................... 4 11.1 Layout Guidelines................................................... 21
7.2 ESD Ratings .............................................................. 4 11.2 Layout Example...................................................... 23
7.3 Recommended Operating Conditions ........................4 12 Device and Documentation Support..........................24
7.4 Thermal Information ...................................................4 12.1 Device Support....................................................... 24
7.5 Electrical Characteristics: Wide-Bandwidth Mode ..... 5 12.2 Documentation Support.......................................... 24
7.6 Electrical Characteristics: Low-Quiescent 12.3 Receiving Notification of Documentation Updates..24
Current Mode ............................................................... 6 12.4 Support Resources................................................. 24
7.7 Typical Characteristics................................................ 7 12.5 Trademarks............................................................. 25
8 Detailed Description......................................................13 12.6 Electrostatic Discharge Caution..............................25
8.1 Overview................................................................... 13 12.7 Glossary..................................................................25
8.2 Functional Block Diagram......................................... 13 13 Mechanical, Packaging, and Orderable
8.3 Feature Description...................................................14 Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2020) to Revision F (May 2021) Page
• Replaced the THD+N vs Frequency Using the BUF634A with the OPA2810 (VO = 10 VPP, 90-kHz
Measurement Bandwidth) figure with the Thermal Performance vs Cu Area for the DDA Package figure........ 1
Changes from Revision D (September 2020) to Revision E (December 2020) Page

• Deleted preview statement for BUF634A VSON package..................................................................................1
• Deleted preview statement for the DRB package...............................................................................................3
Changes from Revision C (June 2020) to Revision D (September 2020) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added DRB package outline to Mechanical, Packaging, and Orderable Information section.......................... 25
Changes from Revision B (January 2020) to Revision C (June 2020) Page

• Deleted preview statement for BUF634A HSOIC package................................................................................ 1
• Deleted preview statement for the D and DDA packages.................................................................................. 3
Changes from Revision A (May 2019) to Revision B (January 2020) Page

• Added DRB (VSON) and DDA (HSOIC) packages to document........................................................................1
• Changed Applications section............................................................................................................................ 1
• Changed last paragraph of Description section .................................................................................................1
• Added discussion of VIN pin to ESD Protection section....................................................................................14
• Added Power Dissipation and Thermal Considerations section....................................................................... 20
• Added HSOIC Layout Guidelines (DDA Package With a Thermal Pad) section.............................................. 22
• Changed title of BUF634A Layout Example image.......................................................................................... 23
Changes from Revision * (February 2019) to Revision A (May 2019) Page

• Changed document status from Advance Information to Production Data ........................................................1
2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: BUF634A

BUF634A
www.ti.com SBOS948F – FEBRUARY 2019 – REVISED MAY 2021
5 Device Comparison Table

IQ / CHANNEL SLEW RATE
DEVICE VS ± (V) BW (MHz) VOLTAGE NOISE (nV/√ Hz) AMPLIFIER DESCRIPTION
(mA) (V/µs)
BUF634A ±18 1.5 – 8.5 35 – 210 3750 3.4 Unity-gain, open-loop buffer
BUF634 ±18 1.5 – 15 30 – 180 2000 4 Unity-gain, open-loop buffer
Unity-gain, open-loop buffer
LMH6321 ±18 11 110 1800 2.8
with adjustable current limit
6 Pin Configuration and Functions
BW 1 8 NC BW 1 8 NC
Exposed
NC 2 7 V+ NC 2 Thermal 7 V+
Die Pad
VIN 3 G=1 6 VO VIN 3 on 6 VO
Underside(1)
V– 4 5 NC 9¤ 4 5 NC
Figure 6-1. D and DDA Packages 8-Pin SOIC, 8-Pin Figure 6-2. DRB Package 8-Pin VSON with Thermal
HSOIC with Thermal Pad Top View Pad Top View
Table 6-1. Pin Functions

PIN
I/O(2) DESCRIPTION
NAME DDA(1) DRB(1) D
Bandwidth adjust pin. Connect the BW pin to the V– pin for wide-
BW 1 1 1 I BW mode and leave the BW pin floating for low-IQ mode. See the
Adjustable Bandwidth section.
NC 2, 5, 8 2, 5, 8 2, 5, 8 — No internal connection
V– 4 4 4 P Negative power supply
V+ 7 7 7 P Positive power supply
VIN 3 3 3 I Input
VO 6 6 6 O Output
Thermal Pad — — Thermal pad. Must be electrically shorted to V–.
(1) The DRB and DDA packages include a thermal pad on the backside of the device. The thermal pad must be connected to the same
potential as V–. Connect the thermal pad and V– to a heat-spreading plane to achieve low thermal impedance. The thermal pad can
also be unused (not connected to any heat-spreading plane or voltage), thus giving an overall higher thermal impedance.
(2) I = input, O = output, P = power.
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

BUF634A
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS = (V+) – (V–) Supply voltage 40 (±20) V
VIN Input voltage Vs ± 0.5 V
Output short-circuit (to ground) Continuous
TA Operating ambient temperature –40 125 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS = (V+) – (V–) Supply voltage ±2.25 ±15 ±18 V
TA Ambient temperature –40 25 125(1) °C
(1) Limited by RΘJA and TJ,Max for safe operation. See the Output Current section.
7.4 Thermal Information

BUF634A
THERMAL METRIC(1) D (SOIC) DRB (VSON) DDA (HSOIC) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 122.9 51 41.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 55.2 58 57.1 °C/W
RθJB Junction-to-board thermal resistance 68.4 23.8 17.0 °C/W
ΨJT Junction-to-top characterization parameter 12.1 1.7 4.6 °C/W
ΨJB Junction-to-board characterization parameter 67.2 23.8 17.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance NA 9.0 5.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

BUF634A
7.5 Electrical Characteristics: Wide-Bandwidth Mode

at TA = 25°C, VS = ±15 V, BW pin connected to V–, and RL = 100 Ω connected to mid-supply (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
RL = 1 kΩ 210
BW Bandwidth, –3 dB MHz
RL = 100 Ω 200
Bandwidth for 0.1-dB flatness VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω 50 MHz
SR Slew rate VO = 20-V step, VIN-SR = 4000 V/µs 3750 V/µs
Rise and fall time VO = 200-mV step 1.3 ns
Settling time to 0.1% VO = 20-V step, VIN-SR = 2500 V/µs 90 ns
Settling time to 1% VO = 20-V step, VIN-SR = 2500 V/µs 20 ns
en Voltage noise f = 1 kHz 3.4 nV/√Hz
in Current noise f = 100 kHz 0.85 pA/√Hz
VO = 2 VPP, f = 20 kHz –77
HD2 2nd-harmonic distortion dBc
VO = 10 VPP, f = 20 kHz –69
VO = 2 VPP, f = 20 kHz –77
HD3 3rd-harmonic distortion dBc
VO = 10 VPP, f = 20 kHz –56
DC PERFORMANCE
VOS Input offset voltage TA = 25℃ 36 65 mV
Input offset voltage drift(1) TA = –40℃ to 125℃ 175 µV/℃
IB Input bias current VIN = 0 V 0.25 2 µA
VO = ±10 V, RL = 1 kΩ 0.95 0.99
G Gain VO = ±10 V, RL = 100 Ω 0.93 0.95 V/V
VO = ±10 V, RL = 67 Ω 0.91 0.93
INPUT
Linear input voltage range RL = 1 kΩ, IB < 10 µA –13 13 V
ZIN Input impedance RL = 100 Ω 180 || 5 MΩ || pF
OUTPUT
IO = ±10 mA 1.6 1.8
Output headroom to supplies IO = ±100 mA 2.0 2.2 V
IO = ±150 mA 2.2 2.5
IO Current output, continuous ±250 mA
ISC Short-circuit current ±375 ±550 mA
ZO Output impedance DC, IO = 10 mA 5 Ω
POWER SUPPLY
VS Operating voltage range ±2.25 ±18 V
IQ Quiescent current IO = 0 mA 8.5 12 mA
PSRR Power-supply rejection ratio VS = ±2.25 V to ±18 V 64 75 dB
THERMAL SHUTDOWN
Thermal shutdown
180 ℃
temperature
(1) Based on electrical characterization over temperature of 35 devices.

BUF634A
7.6 Electrical Characteristics: Low-Quiescent Current Mode

at TA = 25°C, VS = ±15 V, BW pin left open, and RL = 100 Ω connected to mid-supply (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
RL = 1 kΩ 35
BW Bandwidth, –3 dB MHz
RL = 100 Ω 31
Bandwidth for 0.1-dB flatness VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω 2.3 MHz
SR Slew rate VO = 20-V step, VIN-SR = 4000 V/µs 3750 V/µs
Rise and fall time VO = 200-mV step 4 ns
Settling time to 0.1% VO = 20-V step, VIN-SR = 2500 V/µs 400 ns
Settling time to 1% VO = 20-V step, VIN-SR = 2500 V/µs 90 ns
en Voltage noise f = 1 kHz 8.1 nV/√Hz
in Current noise f = 10 kHz 0.3 pA/√Hz
VO = 2 VPP, f = 20 kHz –54
HD2 2nd-harmonic distortion dBc
VO = 10 VPP, f = 20 kHz –65
VO = 2 VPP, f = 20 kHz –40
HD3 3rd-harmonic distortion dBc
VO = 10 VPP, f = 20 kHz –44
DC PERFORMANCE
VOS Input offset voltage TA = 25℃ 36 65 mV
Input offset voltage drift(1) TA = –40℃ to 125℃ 175 µV/℃
IB Input bias current VIN = 0 V 0.03 0.25 µA
VO = ±10 V, RL = 1 kΩ 0.95 0.99
G Gain VO = ±10 V, RL = 100 Ω 0.93 0.95 V/V
VO = ±10 V, RL = 67 Ω 0.91 0.93
INPUT
Linear input voltage range RL = 1 kΩ, IB < 10 µA –13 13 V
ZIN Input impedance RL = 100 Ω 1400 || 5 MΩ || pF
OUTPUT
IO = ±10 mA 1.6 1.8
Output headroom to supplies IO = ±100 mA 2.0 2.2 V
IO = ±150 mA 2.2 2.5
IO Current output, continuous ±250 mA
ISC Short-circuit current ±350 ±550 mA
ZO Output impedance DC, IO = 10 mA 7 Ω
POWER SUPPLY
VS Operating voltage range ±2.25 ±18 V
IQ Quiescent current IO = 0 1.5 2.3 mA
PSRR Power-supply rejection ratio VS = ±2.25 V to ±18 V 64 80 dB
THERMAL SHUTDOWN
Thermal shutdown
180 ℃
temperature
(1) Based on electrical characterization over temperature of 35 devices.

BUF634A
7.7 Typical Characteristics

At TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted).
10 10
5 5
0 0
Normalized Gain (dB)

-5 -5
-10 -10
Phase (o)
Phase (o)
0 -15 0 -15
-10 -10
-20 8.6 mA -20
6.6 mA
-30 4.9 mA -30 -40oC
-40 2.7 mA -40 25oC
1.5 mA 125oC
-50 -50
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) D001
Frequency (Hz) D002
. Solid lines indicate wide-BW mode, dashed lines indicate low-

Figure 7-1. Gain and Phase vs Frequency and Quiescent IQ mode
Current Figure 7-2. Gain and Phase vs Frequency and Temperature
10 10
5 5
0 0

-5 -5
-10 -10
Phase (o)
Phase (o)
0 -15 0 -15
-10 -10
-20 -20
-30 RS = 0 : -30 RL = 1 k:
-40 RS = 50 : -40 RL = 100 :
RS = 100 : RL = 50 :
-50 -50
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) D003
Frequency (Hz) D004
Solid lines indicate wide-BW mode, dashed lines indicate low- Solid lines indicate wide-BW mode, dashed lines indicate low-
IQ mode IQ mode
Figure 7-3. Gain and Phase vs Frequency and Source Figure 7-4. Gain and Phase vs Frequency and Load Resistance
Resistance
10 10
5 5
0 0

-5 -5
-10 -10
Phase (o)
Phase (o)
0 -15 0 -15
-10 -10
-20 -20
CL = 0 pF CL = 0 pF
-30 CL = 47 pF -30 CL = 47 pF
-40 CL = 220 pF -40 CL = 220 pF
CL = 1 nF CL = 1 nF
-50 -50
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) D005
Frequency (Hz) D006
Low-IQ mode Wide-BW mode

Figure 7-5. Gain and Phase vs Frequency and Load Figure 7-6. Gain and Phase vs Frequency and Load
Capacitance Capacitance

BUF634A
7.7 Typical Characteristics (continued)

10 100
5 90
Power Supply Rejection Ratio (dB)

0 80

-5 70
-10 60
Phase (o)
0 -15 50
-10 40
-20 30
VS = ±2.25 V
-30 VS = ±5 V 20
-40 VS = ±12 V 10 PSRR+
VS = ±18 V PSRR
-50 0
100k 1M 10M 100M 1G 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D007
Frequency (Hz) D008
Solid lines indicate wide-BW mode, dashed lines indicate low- Solid lines indicate wide-BW mode, dashed lines indicate low-
IQ mode IQ mode
Figure 7-7. Gain and Phase vs Frequency and Power-Supply Figure 7-8. PSRR vs Frequency
Voltage
100
Low-IQ Low-IQ
Wide-BW Wide-BW
10
Voltage Noise (nV/—Hz)
Current Noise (pA/—Hz)
10
1 0.1
10 100 1k 10k 100k 0.1 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D011 Frequency (Hz) D017
. .
Figure 7-9. Voltage Noise Density vs Frequency Figure 7-10. Current Noise Density vs Frequency
-40 -40
-50
Harmonic Distortion (dBc)
-60 -50
-70
-80 -60
-90
-100 -70
-110 HD2 HD2

HD3 HD3
-120 -80
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Frequency (Hz) D012
Frequency (Hz) D013
Wide-BW mode, VIN = 10 VPP, RL = 1 kΩ Wide-BW mode, VIN = 10 VPP, RL = 100 Ω

Figure 7-11. Harmonic Distortion vs Frequency Figure 7-12. Harmonic Distortion vs Frequency

BUF634A

-30 -30
-40

-40
-50
-60
-50
-70
-80
-60
-90 HD2 HD2

HD3 HD3
-100 -70
100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M
Frequency (Hz) D014
Frequency (Hz) D015
Low-IQ mode, VIN = 10 VPP, RL = 1 kΩ Low-IQ mode, VIN = 10 VPP, RL = 100 Ω

Figure 7-13. Harmonic Distortion vs Frequency Figure 7-14. Harmonic Distortion vs Frequency
240 425
RL = 1 k: Low-IQ
210 RL = 100 : Wide-BW
400
-3 dB Bandwidth (MHz)
180 Limit Current (mA)

375
150
350
120
325
90
60 300
30 275
10 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125 150
Resistance (:) D001
Junction Temperature (oC) D016
. .
Figure 7-15. Small-Signal Bandwidth vs Bandwidth Adjustment Figure 7-16. Short-Circuit Current vs Temperature
Resistance
14.1 -11.6 14.1 -11.6
TA = 25oC
Output Voltage Swing - Sourcing (V)
Output Voltage Swing - Sourcing (V)
TA = -40oC
Output Voltage Swing - Sinking (V)
Output Voltage Swing - Sinking (V)

13.8 -12 13.8 -12
TA = 125oC
13.5 -12.4
13.5 -12.4
13.2 -12.8
13.2 -12.8
12.9 -13.2
12.9 -13.2
12.6 -13.6
TA = -40oC
12.6 -13.6 12.3 TA = 25oC -14
TA = 125oC
12.3 -14 12 -14.4
0 50 100 150 200 250 0 50 100 150 200 250
|Output Current| (mA) D035
|Output Current| (mA) D034
Wide-BW mode (solid lines indicate sourcing current, dashed Low-IQ mode (solid lines indicate sourcing current, dashed
lines indicate sinking current) lines indicate sinking current)
Figure 7-17. Output Voltage Swing vs Output Current Figure 7-18. Output Voltage Swing vs Output Current

BUF634A

12 0.2
10 VIN VIN
VO-Low-IQ 0.15 VO-Low-IQ
8 VO-Wide-BW VO-Wide-BW
Input and Output Voltage (V)

Input and Output Voltage (V)
6
0.1
4
2 0.05
0
-2 0
-4
-0.05
-6
-8 -0.1
-10
-12 -0.15
Time (50 ns/div) Time (20 ns/div)
D010 D009
. .
Figure 7-19. Large-Signal Transient Response Figure 7-20. Small-Signal Transient Response
100 10
Low-IQ Low-IQ: Sinking
Wide-BW Low-IQ: Sourcing
8 Wide-BW: Sinking
Wide-BW: Sourcing
Output Impedance (:)
Output Impedance (:)
6
10
4
1 0
0 50 100 150 200 250 10 100 1k 10k 100k 1M 10M 100M
Output Current (mA) D030
Frequency (Hz) D036
f = 100 kHz IO = 100 mA

Figure 7-21. Output Impedance vs Output Current Figure 7-22. Output Impedance vs Frequency
60 6000
50 5000
No. of Units in Each Bin
Offset Voltage (mV)
40 4000
30 3000
20 2000
TA = 40oC
10 TA = 25oC 1000
TA = 85oC
TA = 125oC
0 0
26
28
30
32
34
36
38
40
42
44
46
48
4 8 12 16 20 24 28 32 36
Supply Voltage (V) D020 Offset Voltage (mV) D032
. 14000 devices, µ = 35.7 mV, σ = 2.15 mV

Figure 7-23. Offset Voltage vs Supply Voltage Figure 7-24. Offset Voltage Distribution Histogram

BUF634A

55 14
50 12
No. of Units in Each Bin

45 10
Offset Voltage (mV)
40 8
35 6
30 4
25 2
20 0
110
115
120
125
130
135
140
145
150
155
-50 -25 0 25 50 75 100 125 150
Ambient Temperature (oC) D021 D031
Input Offset Drift (PV/oC)
35 devices
TA = –40°C to +125°C, 35 devices, µ = 134 μV/°C, σ = 7.4
Figure 7-25. Offset Voltage vs Temperature
μV/°C
Figure 7-26. Offset Voltage Drift Distribution Histogram
0.2 1
0.15 0.8
0.6
0.1
Input Bias Current (PA)
Input Bias Current (PA)
0.4
0.05 0.2
0 0
-0.05 -0.2
-0.4
-0.1
-0.6
-0.15 -0.8
-0.2 -1
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
Supply Voltage (V) D022
Low-IQ mode, 35 devices Wide-BW mode, 35 devices

Figure 7-27. Input Bias Current vs Supply Voltage Figure 7-28. Input Bias Current vs Supply Voltage
1.6 9
Quiescent Current (mA)
1.5 8.5
1.4 8
1.3 7.5
1.2 7
4 8 12 16 20 24 28 32 36 4 8 12 16 20 24 28 32 36

Figure 7-29. Quiescent Current vs Supply Voltage Figure 7-30. Quiescent Current vs Supply Voltage

BUF634A

1.8 9.5
9.1

1.7
8.7
1.6
8.3
1.5
7.9
1.4 7.5
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (oC) D028

Figure 7-31. Quiescent Current vs Temperature Figure 7-32. Quiescent Current vs Temperature
0.96 0.97
0.955 0.965
0.95 0.96
Gain (V/V)
Gain (V/V)
0.945 0.955
0.94 0.95
0.935 0.945
0.93 0.94
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Figure 7-33. Buffer Gain vs Temperature Figure 7-34. Buffer Gain vs Temperature
2
1.5
Power Dissipation (W)
0.5
0
-50 -25 0 25 50 75 100 125 150
.
Figure 7-35. Maximum Power Dissipation vs Temperature

BUF634A
8 Detailed Description
8.1 Overview
The BUF634A device is a high-speed, unity-gain, open-loop buffer that can be used in a wide range of
applications requiring large output current drive or large slew rates. The BUF634A can operate on power
supplies ranging from 4.5 V to 36 V and includes an internal output current limiting feature and thermal
shutdown, thereby making the device rugged and easy to use.
The bandwidth of the BUF634A can be adjusted by connecting a resistor between the V– and BW pins. Its
power scaling with bandwidth makes the device suitable for use in portable battery-powered applications. See
the Section 8.4.1 for a description of the relationship between bandwidth adjustment resistance and the device
–3-dB bandwidth.
The BUF634A can be used in a composite loop (inside the feedback loop of op amps) to increase output current,
eliminate thermal feedback, and improve capacitive load drive. See Figure 9-7 for this circuit. Decoupling the
high-power output current stage from the precision amplifier gives high precision performance by eliminating
thermal effects on input offset of the composite circuit. With a large slew rate of 3750 V/µs, the BUF634A can
quickly reproduce its input signal at its output without adding considerable delay when used in a composite loop.
When used in a composite loop, the outer amplifier controls the circuit precision and distortion performance and
the buffer augments the circuit output current drive capability.
See the Section 8.2 for a simplified circuit diagram of the open-loop complementary follower design of the
BUF634A.
8.2 Functional Block Diagram
V+
Thermal
Shutdown
I1(1)
50
VO
VIN
1.2 k
8k
BW V±
Stage currents are set by I1.

BUF634A
8.3 Feature Description

8.3.1 Output Current
The BUF634A can deliver up to ±250-mA continuous output current. Internal circuitry limits the output current
to approximately ±350 mA. Care must be taken to limit the output voltage swing for a given load resistance to
avoid limiting the output current and degrading linearity; see Figure 9-8. For many applications, however, the
continuous output current is limited by thermal effects. The output voltage swing capability varies with junction
temperature and output current; see Figure 7-17 and Figure 7-18. Care must be taken to operate the device
below the maximum-recommended junction temperature in applications using this buffer in wide-bandwidth
mode with a wide supply voltage and large output current to avoid permanent damage to the device.
8.3.2 Thermal Shutdown
Power dissipated in the BUF634A causes the junction temperature to rise. A thermal protection circuit in the
BUF634A disables the output when the junction temperature reaches approximately 180°C. When the thermal
protection is activated, the output stage is disabled and the output current is limited, allowing the device to cool.
Quiescent current is approximately 12 mA during thermal shutdown. When the junction temperature cools to
approximately 160°C, the output circuitry is again enabled. This process can cause the protection circuit to cycle
on and off with a period ranging from a fraction of a second to several minutes or more, depending on package
type, signal, load, and thermal environment.
The thermal protection circuit is designed to prevent damage during abnormal conditions. Any tendency to
activate the thermal protection circuit during normal operation is a sign of an inadequate heat sink or excessive
power dissipation for the package type.
8.3.3 ESD Protection
As shown in Figure 8-1, all device pins are protected with internal ESD protection diodes to the power supplies.
These diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes
can typically support 10-mA continuous currents. Current limiting series resistors must be added at the inputs
if common-mode voltages higher than the supply voltages are possible. Keep these resistor values as low as
possible because using high values degrades noise performance and frequency response. VIN is a non fail-safe
pin. Ensure V+ and V– are powered up before applying a signal to the VIN pin. Failure to do so results in current
flowing through the ESD diode. Restrict any current flowing through the ESD diodes to less than 10 mA.
V+
Power Supply
ESD Cell
RIN
VIN
VO
BW
V±
Figure 8-1. Internal ESD Protection

BUF634A
8.4 Device Functional Modes

8.4.1 Adjustable Bandwidth
The BUF634A –3-dB bandwidth can be adjusted from 35 MHz to 210 MHz for a 1-kΩ load resistance, as shown
in Figure 8-2, by connecting a resistor between the V– and BW pins. The bandwidth is set to 210 MHz with the
BW pin connected to V– and to 35 MHz with the BW pin left floating. The –3-dB bandwidth also changes with the
value of the load resistance for a given bandwidth adjustment resistance. The device quiescent current varies
from 1.5 mA (typical) to 8.5 mA (typical) with variation in bandwidth from 35 MHz to 210 MHz, respectively.
240
RL = 1 k:
210 RL = 100 :
-3 dB Bandwidth (MHz)
180
150
120
90
60
30
10 100 1k 10k 100k 1M
Resistance (:) D001
Figure 8-2. Small-Signal Bandwidth versus Bandwidth Adjustment Resistance

BUF634A
9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information

Figure 9-1 shows the BUF634A connected as an open-loop buffer. The source impedance and optional input
resistor, RS, influence the frequency response; see Figure 7-3. Bypass the power supplies with capacitors
connected close to the device pins. Capacitor values as low as 0.1 µF assure stable operation in most
applications, but high output current and fast output slewing can demand large current transients from the power
supplies, requiring the use of solid tantalum 10-µF capacitors. High-frequency, open-loop applications benefit
from special bypassing and layout considerations. See the Section 9.1.1 for more information. If the BUF634A
input is left floating, the device output can swing to either of the supplies based on the input bias current polarity.
Optiona l conn ection

for wide ba ndwidth ±
See Adju stable Ba ndwidth
section
Figure 9-1. Buffer Connections
9.1.1 High-Frequency Applications

The excellent bandwidth and fast slew rate of the BUF634A are useful in a variety of high-frequency, open-loop
applications. When operated in an open-loop application, printed circuit board (PCB) layout and bypassing
techniques can affect dynamic performance. Figure 9-2 through Figure 9-6 illustrate various application circuit
examples for the BUF634A.
For best results, use a ground-plane-type circuit board layout and bypass the power supplies with 0.1-µF
ceramic chip capacitors at the device pins in parallel with solid tantalum 10-µF capacitors. Source resistance
affects high-frequency peaking, step-response overshoot, and ringing. Best response is usually achieved with a
series input resistor of 25 Ω to 200 Ω, depending on the signal source. Response with some loads (especially
capacitive) can be improved with a resistor of 10 Ω to 150 Ω in series with the output. When driving multiple
device under test (DUT) inputs in automatic test equipment (ATE) testers (large capacitive load), as illustrated in
Figure 9-3, place an isolation resistor at the output of the BUF634A for adequate phase margin and stability.

BUF634A
G = +2
1 kŸ 1 kŸ
±
Drives hea dphon es
1 µF OPA165 6 BUF634A or sma ll spea kers.
+
100 kŸ
Figure 9-2. High-Performance Headphone Driver
V+
RF
CF
±
RISO
OPA281 0 BUF634A VO
VIN + BW
CL
V-
Figure 9-3. ATE and Test Pin Driver

+24 V
+
C(1)
10 k 12 V
+ ±
Psuedo
BUF634A ground
10 F +
C(1) 12 V
10 k
±
NOTE: (1) System bypass capacitors.
Figure 9-4. Pseudo-Ground Driver
IO = ±200 mA
VIN
+
±2 V
OPA2810 BUF634A
±
Valve
10
Figure 9-5. Current-Output Valve Driver

BUF634A
10 k
1k 9k 10 k
± ½ ±
½
OPA281 0 BUF634A Motor BUF634A OPA281 0
VIN
±1 V + +
±20 V
At 250mA
Figure 9-6. Bridge-Connected Motor Driver
9.2 Typical Application

The BUF634A device can be connected inside the feedback loop, as shown in Figure 9-7, of most op amps to
increase output current. When connected inside the feedback loop, the offset voltage of the BUF634A and other
errors are corrected by the open-loop gain and feedback of the op amp.
1 kŸ 1 kŸ
+
RL
C1 is not required for most common op amps. Use C1 with unity-gain stable, high-speed op amps.
Figure 9-7. Boosting Op Amp Output Current
9.2.1 Design Requirements

• Boost the output current of an OPA2810
• Operate from ±12-V power supplies
• Operate from –40°C to +125°C
• Gain = 2 V/V
• Output current = ±250 mA
• Bandwidth greater than 100 kHz

BUF634A
9.2.2 Detailed Design Procedure

To assure that the composite amplifier remains stable, the phase shift of the BUF634A must remain small
throughout the loop gain of the circuit. For a G = +1 op-amp circuit, the BUF634A must contribute little additional
phase shift (approximately 20° or less) at the unity-gain frequency of the op amp. Phase shift is affected by
various operating conditions that can affect the stability of the op amp.
For the circuit in Figure 9-7, most general-purpose or precision op amps remain unity-gain stable with the
BUF634A connected inside the feedback loop. Large capacitive loads may require the BUF634A to be
connected for wide bandwidth for stable operation. High-speed or fast-settling op amps generally require wide-
bandwidth mode to remain stable and to assure good dynamic performance. Check for oscillations or excessive
ringing on signal pulses with the intended load and worst-case conditions that affect phase response of the
buffer to determine stability with an op amp. Connect the circuit as shown in Figure 9-7. Choose resistors to
provide a voltage gain of 2 V/V. Select the feedback resistor to be 1 kΩ. Choose the input resistor to be 1 kΩ and
C1 to be 10 pF. Figure 9-8 and Figure 9-9 illustrate the THD+N plots for the BUF634A used with the OPA2810 in
a gain of
2-V/V composite loop. The THD+N performance is superior in a composite loop when compared with a
standalone BUF634A because of the negative feedback and open-loop gain of the OPA2810. In Figure 9-8,
the signal distortion degrades for large output voltages with 16-Ω and 32-Ω loads because of the device internal
short-circuit protection.
9.2.3 Application Curves
0 -80
RL = 16 : RL = 16 :
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (dB)
RL = 32 : RL = 32 :
-20 RL = 250 : RL = 250 :
-90
-40
-60 -100
-80
-110
-100
-120 -120
1 10 20 10 100 1k 10k
Output Voltage (VPP) D002
Frequency (Hz) D003
f = 20 kHz, 90-kHz measurement bandwidth VO = 10 VPP, 90-kHz measurement bandwidth
Figure 9-8. THD+N vs Output Voltage Using the Figure 9-9. THD+N vs Frequency Using the
BUF634A with the OPA2810 BUF634A with the OPA2810

BUF634A
10 Power Supply Recommendations

The BUF634A is intended for operation on supplies ranging from 4.5 V to 36 V (±2.25 V to ±18 V). At low
power-supply conditions, such as ±2.25 V, the output swing may be limited. See the output voltage range
specifications in the Electrical Characteristics tables for additional information. The BUF634A can be operated
on single-sided supplies, split, and balanced bipolar supplies or unbalanced bipolar supplies. Operating from
a single supply can have numerous advantages. With the negative supply at ground, the DC errors resulting
from the –PSRR term can be minimized. Minimize the distance (< 0.1 in.) from the power-supply pins to high-
frequency, 0.1-µF decoupling capacitors. A larger capacitor (10 µF typical) is used along with a high-frequency,
0.1-µF supply-decoupling capacitor at the device supply pins. For single-supply operation, only the positive
supply has these capacitors. When a split-supply is used, use these capacitors from each supply to ground. If
necessary, place the larger capacitors further from the device and share these capacitors among several devices
in the same area of the PCB.
10.1 Power Dissipation and Thermal Considerations
The BUF634A includes automatic thermal shutoff protection. This protection circuitry shuts down the amplifier
if the junction temperature exceeds approximately 180°C. When the junction temperature decreases to
approximately 160°C, the buffer turns on again. The package and the PCB dictate the thermal characteristics of
the device. Maximum power dissipation for a particular package is calculated using the following formula.
Tmax TA
PDmax
TJA (1)
where
• PDmax is the maximum power dissipation in the amplifier (W).
• Tmax is the absolute maximum junction temperature (°C).
• TA is the ambient temperature (°C).
• θJA = θJC + θCA
• θJC is the thermal coefficient from the silicon junctions to the case (°C/W).
• θCA is the thermal coefficient from the case to ambient air (°C/W).
The thermal coefficient for the thermal pad integrated circuit packages are substantially improved over the
traditional SOIC package. The data for the thermal pad packages assume a board layout that follows the thermal
pad package layout guidelines referenced above and detailed in the PowerPAD™ Thermally Enhanced Package
application report. If the thermal package integrated circuit package is not soldered to the PCB, the thermal
impedance increases substantially and may cause serious heat and performance issues.
When determining whether or not the device satisfies the maximum power dissipation requirement, make sure
to consider not only quiescent power dissipation, but dynamic power dissipation. Often times, this dissipation
is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation
provides visibility into a possible problem.

BUF634A
11 Layout
11.1 Layout Guidelines
11.1.1 SOIC Layout Guidelines (D Package Without a Thermal Pad)
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit. Bypass capacitors are used to
reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make
sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible, as illustrated in Figure 11-2.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
The SOIC-8 surface-mount package is excellent for applications requiring high output current with low average
power dissipation. To achieve the best possible thermal performance with the SOIC-8 package, solder the device
directly to a circuit board. Sockets degrade thermal performance because much of the heat is dissipated by
conduction through the package pins. Use wide circuit board traces on all device pins, including pins that are not
connected. For more information on designing the circuit board, see the BUF634AD Evaluation module user's
guide.

BUF634A
11.1.2 HSOIC Layout Guidelines (DDA Package With a Thermal Pad)

Figure 11-1 shows the DDA package top-side etch and via pattern.
0.300
(7,62)
0.100
(2,54) 0.026
0.035 0.010 (0,66)
(0,89) (0,254)
0.030
0.060 (0,732) 0.176
(1,52) (4,47)
0.140 0.050
(3,56) (1,27)
0.060
(1,52)
0.035
0.080
0.010 (0,89)
(2,03)
(0.254)
vias
All Units in inches (millimeters)
Figure 11-1. DDA Thermal Pad Integrated Circuit Package PCB Etch and Via Pattern
1. Use an etch for the leads and the thermal pad.

2. Place 13 vias in the thermal pad area. These vias must be 0.01 inch (0.254 mm) in diameter. Keep the vias
small so that solder wicking through the vias is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area, and help
dissipate the heat generated by the BUF634A. These additional vias may be larger than the 0.01-inch (0.254
mm) diameter vias directly under the thermal pad because they are not in the area that requires soldering.
As a result, wicking is not a problem.
4. The thermal pad is internally connected with V–. Therefore, always short the thermal pad to the same
potential as V– externally as well.
5. Connect all vias used under the thermal pad to remove heat to the V– plane.
6. When connecting these vias to the V– plane, do not use the typical web or spoke connection methodology.
Web and spoke connections have a high thermal resistance that slows the heat transfer during soldering.
The vias under the BUF634A thermal pad must connect to the internal thermal plane or thermal pour with a
complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask must leave the pins of the package and the thermal pad area with the 13 vias
exposed.
8. Apply solder paste to the exposed thermal pad area and all of the device pins.
9. With these preparatory steps in place, the device is placed in position and run through the solder reflow
operation as any standard surface-mount component.

BUF634A
11.2 Layout Example
BUF634A SOIC
Package
±
close to power pins
±
close to power pins
Figure 11-2. BUF634A Layout Example (SOIC)

BUF634A
12 Device and Documentation Support

12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, and is preloaded with a library of macromodels in addition to
a range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
12.1.2.2 TI Precision Designs

The BUF634A is featured in several TI Precision Designs, available online at
www.ti.com. TI Precision Designs are analog solutions created by TI’s precision analog applications experts
and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of
materials, and measured performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2810 Dual-channel, 27-V, Rail-to-Rail Input/Output FET-Input Operational Amplifier
data sheet
• Texas Instruments, BUF634AD Evaluation Module user's guide
• Texas Instruments, Combining An Amplifier with the BUF634 application note
• Texas Instruments, Add Current Limit to the BUF634 application note
• Texas Instruments, Power Amplifier Stress and Power Handling Limitations application note
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

BUF634A
12.5 Trademarks
TINA-TI™, TINA™, and TI E2E™ are trademarks of Texas Instruments.
DesignSoft™ is a trademark of DesignSoft, Inc.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

BUF634A
PACKAGE OUTLINE
DRB0008B SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
PIN 1 INDEX AREA

3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
EXPOSED 1.65 0.05 (0.2) TYP

THERMAL PAD
4 5
2X
1.95 2.4 0.05
8
1
6X 0.65 0.35
8X
0.25
PIN 1 ID 0.5 0.1 C A B
(OPTIONAL) 8X
0.3 0.05 C
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com

BUF634A
EXAMPLE BOARD LAYOUT

DRB0008B VSON - 1 mm max height
(1.65)
8X (0.6) SYMM
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
( 0.2) VIA
TYP (2.8)
LAND PATTERN EXAMPLE

SCALE:20X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com

BUF634A
EXAMPLE STENCIL DESIGN

SYMM METAL
8X (0.6)
TYP
1
8X (0.3) 8
(0.63)
SYMM
6X (0.65) (1.06)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com

PACKAGE OPTION ADDENDUM
www.ti.com 8-Apr-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
BUF634AIDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 BF634A Samples
BUF634AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BF634A Samples
BUF634AIDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 B634A Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 8-Apr-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BUF634AIDDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD
BUF634AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
BUF634AIDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BUF634AIDDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0
BUF634AIDR SOIC D 8 2500 356.0 356.0 35.0
BUF634AIDRBR SON DRB 8 3000 367.0 367.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008B SCALE 4.000
VSON - 1 mm max height
3.1 B
A
2.9
PIN 1 INDEX AREA

3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
EXPOSED 1.65 0.05 (0.2) TYP

THERMAL PAD
4 5
2X
1.95 2.4 0.05
8
1
6X 0.65 0.35
8X
0.25
PIN 1 ID 0.5 0.1 C A B
(OPTIONAL) 8X
0.3 0.05 C
4218876/A 12/2017
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
(1.65)
8X (0.6) SYMM
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
( 0.2) VIA
TYP (2.8)

SCALE:20X
0.07 MAX 0.07 MIN

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
SYMM METAL
8X (0.6)
TYP
1
8X (0.3) 8
(0.63)
SYMM
6X (0.65) (1.06)
5
4
(R0.05) TYP
(1.47)
(2.8)

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
www.ti.com
GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
PACKAGE OUTLINE
DDA0008J SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
C
6.2
TYP SEATING PLANE
5.8
A PIN 1 ID
AREA 0.1 C
6X 1.27
8
1
5.0 2X
4.8 3.81
NOTE 3
4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.1 C A B
NOTE 4
0.25
TYP
0.10
SEE DETAIL A
4 5
EXPOSED
THERMAL PAD
3.1 0.25
2.5 GAGE PLANE
0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.6 TYPICAL
2.0
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
www.ti.com
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
(2.95)
NOTE 9
SOLDER MASK
(2.6) DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS
1
8
8X (0.6)
(3.1)
SYMM SOLDER MASK
(1.3) OPENING
TYP (4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA SYMM METAL COVERED
BY SOLDER MASK
(1.3) TYP
(5.4)

SCALE:10X
0.07 MAX 0.07 MIN

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
DDA0008J PowerPAD TM SOIC - 1.7 mm max height
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
SYMM
BASED ON
0.127 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED SEE TABLE FOR

SYMM DIFFERENT OPENINGS
BY SOLDER MASK
FOR OTHER STENCIL
THICKNESSES
(5.4)

EXPOSED PAD
SCALE:10X
STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.91 X 3.47
0.125 2.6 X 3.1 (SHOWN)
0.150 2.37 X 2.83
0.175 2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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BUF634A

SBOS948F – FEBRUARY 2019 – REVISED MAY 2021

BUF634A 36-V, 210-MHz, 250-mA Output, High-Speed Buffer

(1) For all available packages, see the orderable addendum at

Changes from Revision D (September 2020) to Revision E (December 2020) Page

Changes from Revision C (June 2020) to Revision D (September 2020) Page

Changes from Revision B (January 2020) to Revision C (June 2020) Page

Changes from Revision A (May 2019) to Revision B (January 2020) Page

Changes from Revision * (February 2019) to Revision A (May 2019) Page

2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: BUF634A

5 Device Comparison Table

6 Pin Configuration and Functions

Table 6-1. Pin Functions

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

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Product Folder Links: BUF634A

7.5 Electrical Characteristics: Wide-Bandwidth Mode

(1) Based on electrical characterization over temperature of 35 devices.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5

7.6 Electrical Characteristics: Low-Quiescent Current Mode

(1) Based on electrical characterization over temperature of 35 devices.

6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: BUF634A

7.7 Typical Characteristics

Normalized Gain (dB)

Normalized Gain (dB)

. Solid lines indicate wide-BW mode, dashed lines indicate low-

Normalized Gain (dB)

Normalized Gain (dB)

Low-IQ mode Wide-BW mode

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7

7.7 Typical Characteristics (continued)

Power Supply Rejection Ratio (dB)

Normalized Gain (dB)

Current Noise (pA/—Hz)

Harmonic Distortion (dBc)

-110 HD2 HD2

Wide-BW mode, VIN = 10 VPP, RL = 1 kΩ Wide-BW mode, VIN = 10 VPP, RL = 100 Ω

8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

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7.7 Typical Characteristics (continued)

Harmonic Distortion (dBc)

-90 HD2 HD2

Low-IQ mode, VIN = 10 VPP, RL = 1 kΩ Low-IQ mode, VIN = 10 VPP, RL = 100 Ω

180 Limit Current (mA)

Output Voltage Swing - Sourcing (V)

Output Voltage Swing - Sinking (V)

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9

7.7 Typical Characteristics (continued)

Input and Output Voltage (V)

Output Impedance (:)

f = 100 kHz IO = 100 mA

. 14000 devices, µ = 35.7 mV, σ = 2.15 mV

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7.7 Typical Characteristics (continued)