1 FM25Q04B Ds Eng

FM25Q04B
4M-BIT SERIAL FLASH MEMORY
Datasheet
Jan. 2021
Datasheet
FM25Q04B 4M-BIT SERIAL FLASH MEMORY Ver.1.1 1
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Datasheet
 High Reliability
1. Description – Endurance: 100,000 program/erase cycles
– Data retention: 20 years
The FM25Q04B is a 4M-bit (512K-byte) Serial Flash  Green Package
memory, with advanced write protection mechanisms.
– 8-pin SOP (150mil)
The FM25Q04B supports the standard Serial
– 8-pin USON (0.55mm)
Peripheral Interface (SPI), Dual/Quad I/O as well as
– All Packages are RoHS Compliant and Halogen-
2-clock instruction cycle Quad Peripheral
free
Interface(QPI). They are ideal for code shadowing to
RAM, executing code directly from Dual/Quad SPI
(XIP) and storing voice, text and data.
The FM25Q04B can be programmed 1 to 256 bytes 3. Packaging Type
at a time, using the Page Program instruction. It is
designed to allow either single Sector/Block at a
time or full chip erase operation. The FM25Q04B SOP 8 (150mil)
can be configured to protect part of the memory as
CS# 1 8 VCC
the software protected mode. The device can
sustain a minimum of 100K program/erase cycles on DO(DQ1) 2 7 HOLD#(DQ3)
each sector or block. WP#(DQ2) 3 6 CLK
VSS 4 5 DI(DQ0)
2. Features
 4Mbit of Flash memory USON8 (0.55mm)
– 128 uniform sectors with 4K-byte each CS# 1 8 VCC
– 8uniform blocks with 64K-byte each or DO(DQ1) 2 7 HOLD#(DQ3)
– 16uniform blocks with 32K-byte each WP#(DQ2) 3 6 CLK
– 256 bytes per programmable page VSS 4 5 DI(DQ0)
 WideOperationRange
– 2.3V~3.6Vsingle voltage supply
– Industrial temperature range
 Serial Interface 4. Pin Configurations
– Standard SPI: CLK, CS#, DI, DO, WP#
– Dual SPI: CLK, CS#, DQ0, DQ1, WP#
PIN PIN
– Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3 I/O FUNCTION
NO. NAME
– QPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
1 CS# I Chip Select Input
– Continuous READ mode support
DO Data Output (Data Input Output
– Allow true XIP(execute in place) operation 2 I/O (1)
(DQ1) 1)
 High Performance WP# Write Protect Input (Data Input
3 I/O
– Max FAST_READ clock frequency: 100MHz (DQ2) Output 2)(2)
– Max READ clock frequency: 50MHz 4 VSS Ground
– Typical page program time: 0.6ms DI Data Input (Data Input Output
5 I/O (1)
– Typical sector erase time: 80ms (DQ0) 0)
– Typical block erase time: 250/400ms 6 CLK I Serial Clock Input
HOLD# Hold Input (Data Input Output
– Typical chip erase time: 3s 7 I/O (2)
(DQ3) 3)
 Low Power Consumption 8 VCC Power Supply
– Typical Deep Power Down current: <1μA Note:
 Security 1 DQ0 and DQ1 are used for Dual SPI instructions.
– Software and hardware write protection 2 DQ0 – DQ3 are used for Quad SPI and QPI instructions.
– Lockable4X256-Byte OTP security Pages
– 64-Bit Unique ID for each device
– Discoverable parameters(SFDP) register
Datasheet
5. Block Diagram
r
e
d
o
c
e
D
Address r X HV Generator
e
Generator d Memory c
o i
c Array g
e o
l
D t
u
Y p
t HOLD(DQ3)
u
c
i O
g Y-Gating l
o a
ir
L e
t WP(DQ2)
u S
p
In
WP l
a
ri
CS e DO(DQ1)
S
CLK
DI Sense DI(DQ0)
SRAM
Amplifier
DO
HOLD
Clock
Generator
State Machine
Figure 1 FM25Q04B Serial Flash Memory Block Diagram
Datasheet
6. Pin Descriptions
Serial Clock (CLK): The SPI Serial Clock Input (CLK) pin provides the timing for serial input and
output operations.
Serial Data Input, Output and I/Os (DI, DO and DQ0, DQ1, DQ2, DQ3): The FM25Q04B
supports standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on
the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO
(output) to read data or status from the device on the falling edge of CLK.
Dual/Quad SPI and QPI instructions use the bidirectional DQ pins to serially write instructions,
addresses or data to the device on the rising edge of CLK and read data or status from the
device on the falling edge of CLK. Quad SPI and QPI instructions require the non-volatile Quad
Enable bit (QE) in Status Register-2 to be set.When QE=1, the WP# pin becomes DQ2 and
HOLD# pin becomes DQ3.
Chip Select (CS#): The SPI Chip Select (CS#) pin enables and disables device operation.
When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2,
DQ3) pins are at high impedance. When deselected, the devices power consumption will be at
standby levels unless an internal erase, program or write status register cycle is in progress.
When CS# is brought low, the device will be selected, power consumption will increase to active
levels and instructions can be written to and data read from the device. After power-up, CS#
must transition from high to low before a new instruction will be accepted. The CS# input must
track the VCC supply level at power-up (see “9Write Protection” and Figure 62). If needed a pull-
up resister on CS# can be used to accomplish this.
HOLD (HOLD#): The HOLD# pin allows the device to be paused while it is actively selected.
When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device
operation can resume. The HOLD# function can be useful when multiple devices are sharing the
same SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for
Quad I/O, the HOLD# pin function is not available since this pin is used for DQ3.
Write Protect (WP#): The Write Protect (WP#) pin can be used to prevent the Status Registers
from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB,
BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB
sector or the entire memory array can be hardware protected. The WP# pin is active low.
However, when the QE bit of Status Register-2 is set for Quad I/O, the WP# pin function is not
available since this pin is used for DQ2.
Datasheet
7. Memory Organization
The FM25Q04B array is organized into 2,048programmable pages of256-
byteseach.Upto256bytes can be programmed (bits are programmed from 1 to
0)atatime.Pagescanbeerasedingroupsof16(4KBsectorerase),groupsof128 (32KB block erase),
groups of256 (64KB block erase)ortheentirechip(chiperase).TheFM25Q04B has 128erasable
sectors, 16erasable 32-k byte blocks and 8 erasable 64-k byte blocks respectively. The small
4KB sectorsallowforgreater flexibility in applications that requiredata and parameter storage.
Table 1Memory Organization

Block Block Sector
AddressRange
(64KB) (32KB) (4KB)
15 127 07F000h 07FFFFh
7 | … … …
14 112 070000h 070FFFh
13 111 06F000h 06FFFFh
6 | … … …
12 96 060000h 060FFFh
11 95 05F000h 05FFFFh
5 | … … …
10 80 050000h 050FFFh
.
.
.
5 47 02F000h 02FFFFh
2 | … … …
4 32 020000h 020FFFh
3 31 01F000h 01FFFFh
1 | … … …
2 16 010000h 010FFFh
15 00F000h 00FFFFh
1 … … …
0 | 2 002000h 002FFFh
0 1 001000h 001FFFh
0 000000h 000FFFh
Datasheet
8. Device Operations
Power On
Reset (66h + 99h) Reset (66h + 99h)
Device
Initialization
Standard SPI Enable QPI (38h)

Dual SPI QPI
Quad SPI Disable QPI (FFh) operations
operations
Figure 2 FM25Q04B Serial Flash Memory Operation Diagram
8.1. Standard SPI

The FM25Q04B is accessed through an SPI compatible bus consisting of four signals: Serial
Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write instructions, addresses or data to the device
on the rising edge of CLK. The DO output pin is used to read data or status from the device on
the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between
Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in
standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is
normally low on the falling and rising edges of CS#. For Mode 3, the CLK signal is normally high
on the falling and rising edges of CS#.
CS#
MODE3 MODE3
CLK MODE0 MODE0
DI Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DONT CARE
MSB
HIGH IMPEDANCE
DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Figure 3 The difference between Mode 0 and Mode 3
8.2. Dual SPI

The FM25Q04B supports Dual SPI operation when using instructions such as “Fast Read Dual
Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to
or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI
Read instructions are ideal for quickly downloading code to RAM upon power-up (code-
shadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using
Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: DQ0 and DQ1.
Datasheet
8.3. Quad SPI
The FM25Q04B supports Quad SPI operation when using instructions such as “Fast Read Quad
Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read
Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six
times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in
continuous and random access transfer rates allowing fast code-shadowing to RAM or execution
directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become
bidirectional DQ0 and DQ1 and the WP # and HOLD# pins become DQ2 and DQ3 respectively. Quad
SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
8.4. QPI
The FM25Q04B supports Quad Peripheral Interface (QPI) operations only when the device is
switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction.
The typical SPI protocol requires that the byte-long instruction code being shifted into the device only
via DI pin in eight serial clocks. The QPI mode utilizes all four DQ pins to input the instruction code,
thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead
and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI
mode are exclusive. Only one mode can be active at any given time. “Enable QPI (38h)” and
“Disable QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or
after a software reset using “Reset (99h)” instruction, the default state of the device is
Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in
Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become
bidirectional DQ0 and DQ1, and the WP# and HOLD# pins become DQ2 and DQ3 respectively. See
Figure 2 for the device operation modes.
8.5. Hold
For Standard SPI and Dual SPI operations, the HOLD# signal allows the FM25Q04B operation
to be paused while it is actively selected (when CS# is low). The HOLD# function may be useful
in cases where the SPI data and clock signals are shared with other devices. For example,
consider if the page buffer was only partially written when a priority interrupt requires use of the
SPI bus. In this case the HOLD# function can save the state of the instruction and the data in the
buffer so programming can resume where it left off once the bus is available again. The HOLD#
function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition
will activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is
not already low theHOLD# condition will activate after the next falling edge of CLK. The HOLD#
condition will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If
the CLK is not already low the HOLD# condition will terminate after the next falling edge of CLK.
During a HOLD# condition, the Serial Data Output (DO) is high impedance, and Serial Data
Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept
active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic state
of the device.
Active Hold Active Hold Active
Figure 4 HoldCondition Waveform
Datasheet
9. Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise
and other adverse system conditions that may compromise data integrity. To address this
concern, the FM25Q04B provides several means to protect the data from inadvertent writes.
Write Protect Features

 Device resets when VCC is below threshold
 Time delay write disable after Power-up
 Write enable/disable instructions and automatic write disable after erase or program
 Software and Hardware (WP# pin) write protection using Status Register
 Write Protection using Power-down instruction
 Lock Down write protection for Status Register until the next power-up
 One Time Program (OTP) write protection for array and Security Sectors using Status
Register.
Upon power-up or at power-down, the FM25Q04B will maintain a reset condition while VCC is
below the threshold value of VWI, (See “12.3Power-up Timing” and Figure 62). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC
voltage exceeds VWI, all program and erase related instructions are further disabled for a time
delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip
Erase and the Write Status Register instructions. Note that the chip select pin (CS#) must track
the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If
needed a pull-up resister on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status
Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will
be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL)
is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and
setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP2, BP1
and BP0) bits. These settings allow a portion as small as a 4KB sector or the entire memory
array to be configured as read only. Used in conjunction with the Write Protect (WP#) pin,
changes to the Status Register can be enabled or disabled under hardware control. See Status
Register section for further information. Additionally, the Power-down instruction offers an extra
level of write protection as all instructions are ignored except for the Release Power-down
instruction.
Datasheet
10. Status Register
The Read Status Register instructions can be used to provide status on the availability of the
Flash memory array, if the device is write enabled or disabled, the state of write protection, Quad
SPI setting, Security Sector lock status. The Write Status Register instruction can be used to
configure the device write protection features, Quad SPI setting and Security Sector OTP lock.
Write access to the Status Register is controlled by the state of the non-volatile Status Register
Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI
operations, the WP# pin.
Factory default for all Status Register bits are 0.
S7 S6 S5 S4 S3 S2 S1 S0
SRP0 SEC TB BP2 BP1 BP0 WEL WIP
STATUS REGISTER PROTECT 0

(non-volatile)
SECTOR PROTECT
(non-volatile)
TOP/BOTTOM PROTECT
(non-volatile)
BLOCK PROTECT BITS
(non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
Figure 5Status Register1
S15 S14 S13 S12 S11 S10 S9 S8
RFU CMP ERR DRV DRV LB QE SRP1

1 0
Reserved
COMPLEMENT PROTECT
(non-volatile)
Error Status
(volatile, Read only)
Output Driver Strength
(Volatile/Non-Volatile Writable)
SECURITY REGISTER LOCK BIT

(non-Volatile)
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1

(non-volatile)
Figure 6Status Register 2
Datasheet
10.1. WIP Bit
WIP is a read only bit in the status register (S0) that is set to a 1 state when the device is
executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write
Status Register or Erase/Program Security Sector instruction. During this time the device will
ignore further instructions except for the Read Status Register instruction (see tW, tPP, tSE, tBE,
and tCE in “12.6AC Electrical Characteristics”). When the program, erase or write status
register(or securitysector) instruction has completed, the WIP bit will be cleared to a 0 state
indicating the device is ready for further instructions.
10.2. Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after
executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write
disabled. A write disablestateoccursuponpower-uporafteranyofthe following instructions: Write
Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write
Status Register, Erase Security Sectorand Program Security Sector.
10.3. Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2-0) are non-volatile read/write bits in the status register (S4-2) that
provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in “12.6AC Electrical Characteristics”). All, none or a portion of the
memory array can be protected from Program and Erase instructions (see Table 4Status
Register Memory Protection). The factory default setting for the Block Protection Bits is 0, none
of the array protected.
10.4. Top/Bottom Block Protect (TB)

The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2-0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in Table 4Status Register Memory
Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status
Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.
10.5. Sector/Block Protect (SEC)

The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2-0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of
the array as shown in Table 4Status Register Memory Protection table. The default setting is
SEC=0.
10.6. Complement Protect (CMP)

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It
is used in conjunction with SEC, TB, BP2-0 bits to provide more flexibility for the array protection.
Once CMP is set to 1, previous array protection set by SEC, TB and BP2-0 will be reversed. For
instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not;
when CMP=1, the top 4KB sector will become unprotected while the rest of the array become
read-only. Please refer to Table 4Status Register Memory Protection table for details. The
default setting is CMP=0.
Datasheet
10.7. Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status
register (S8andS7).TheSRPbitscontrolthemethodofwriteprotection:softwareprotection,hardware
protection, power supply lock-down or one time programmable (OTP) protection.
Table 2Status Register Protect bits

Status
SRP1 SRP0 WP# Description
Register
WP# pin has no control. The Status register can be
Software
0 0 X written to after a Write Enable instruction, WEL=1.
Protection
(Factory Default)
Hardware When WP# pin is low the Status Register locked and can
0 1 0
Protected not be written to.
Hardware When WP# pin is high the Status register is unlocked and
0 1 1
Unprotected can be written to after a Write Enable instruction, WEL=1.
Power Supply Status Register is protected and can not be written to
1 0 X
Lock-Down again until the next power-down, power-up cycle.(1)
One Time Status Register is permanently protected and can not be
1 1 X
Program written to.
Note:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0)
state.
10.8. Output driver strength (DRV1, DRV0)

The DRV1 & DRV0 bits are used to determine the output driver strength.
Table 3Driver Strength bits
DRV1, DRV0 Driver Strength
0,0 100%
0,1 75%
1,0 50%
1,1 25%
10.9. Error Bit (ERR)

The Error bit is a status flag, which shows the status of last Program/Erase operation. It will be
set to "1", if the Program/Erase operation fails.If theProgram/Erase region is protected, Error bit
will not be set to “1”. It will be clear to “0” after power-up, or software Reset/Write Enable
instruction.
10.10. Security SectorLock Bit (LB)

The Security Register Lock Bit (LB) is non-volatile One Time Program (OTP) bit in Status
Register (S10) that provides the write protect control and status to the Security Registers. The
default state of LB is 0, Security Registersare unlocked. LBcan be set to 1using the Write Status
Register instruction. LB bitis One Time Programmable (OTP), once it’s set to 1, the Security
Registers will become read-only permanently.
Datasheet
10.11. Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows
Quad SPI and QPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin
and HOLD# are enabled. When the QE bit is set to a 1, the Quad DQ2 and DQ3 pins are enabled,
and WP# and HOLD# functions are disabled.
QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI; otherwise the command will be ignored. When the device is in
QPI mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot
change QE bit from a “1” to a “0”.
WARNING: If the WP# or HOLD# pins are tied directly to the power supply or ground
during standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
10.12. Status Register Memory Protection

Table 4Status Register Memory Protection
STATUS REGISTER FM25Q04B (4M-BIT) MEMORY PROTECTION

PROTECTED PROTECTED PROTECTED PROTECTED
CMP SEC TB BP2 BP1 BP0
BLOCK(S) ADDRESSES DENSITY PORTION
0 X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 0 1 7 070000h – 07FFFFh 64KB Upper 1/8
0 0 0 0 1 0 6 and 7 060000h – 07FFFFh 128KB Upper 1/4
0 0 0 0 1 1 4 thru 7 040000h –07FFFFh 256KB Upper 1/2
0 0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/8
0 0 1 0 1 0 0 and 1 000000h – 01FFFFh 128KB Lower 1/4
0 0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/2
0 0 X 1 X X 0 thru 7 000000h – 07FFFFh 512KB ALL
0 1 0 0 0 1 7 07F000h – 07FFFFh 4KB U - 1/128

0 1 0 0 1 0 7 07E000h – 07FFFFh 8KB U - 1/64
0 1 0 0 1 1 7 07C000h – 07FFFFh 16KB U - 1/32
0 1 0 1 0 X 7 078000h – 07FFFFh 32KB U - 1/16
0 1 0 1 1 0 7 078000h – 07FFFFh 32KB U - 1/16
0 1 1 0 0 1 0 000000h – 000FFFh 4KB L - 1/128

0 1 1 0 1 0 0 000000h – 001FFFh 8KB L - 1/64
0 1 1 0 1 1 0 000000h – 003FFFh 16KB L - 1/32
0 1 1 1 0 x 0 000000h – 007FFFh 32KB L - 1/16
0 1 1 1 1 0 0 000000h – 007FFFh 32KB L - 1/16
0 1 X 1 1 1 0 thru 7 000000h – 07FFFFh 512KB ALL
1 X X 0 0 0 0 thru 7 000000h – 07FFFFh 512KB ALL
Datasheet
STATUS REGISTER FM25Q04B (4M-BIT) MEMORY PROTECTION
PROTECTED PROTECTED PROTECTED PROTECTED
CMP SEC TB BP2 BP1 BP0
BLOCK(S) ADDRESSES DENSITY PORTION
1 0 0 0 1 0 0 and 5 000000h – 05FFFFh 384KB Lower 3/4
1 0 1 0 0 1 1 thru 7 010000h – 07FFFFh 448KB Upper 7/8
1 0 1 0 1 0 2 thru7 020000h – 07FFFFh 384KB Upper 3/4
1 0 1 0 1 1 4 thru 7 040000h – 07FFFFh 256KB Upper 1/2
1 0 X 1 X X NOE NONE NONE NONE
1 1 0 0 0 1 0 thru 7 000000h – 07EFFFh 508KB L - 127/128
1 1 0 0 1 0 0 thru 7 000000h – 07DFFFh 504KB L - 63/64
1 1 0 0 1 1 0 thru 7 000000h – 07BFFFh 496KB L - 31/32
1 1 0 1 0 X 0 thru 7 000000h – 077FFFh 480KB L - 15/16
1 1 0 1 1 0 0 thru 7 000000h – 077FFFh 480KB L - 15/16
1 1 1 0 0 1 0 thru 7 001000h –07FFFFh 508KB U - 127/128
1 1 1 0 1 0 0 thru 7 002000h – 07FFFFh 504KB U - 63/64
1 1 1 0 1 1 0 thru 7 004000h – 07FFFFh 496KB U - 31/32
1 1 1 1 0 X 0 thru 7 008000h – 07FFFFh 480KB U - 15/16
1 1 1 1 1 0 0 thru 7 008000h – 07FFFFh 480KB U - 15/16
1 X X 1 1 1 NONE NONE NONE NONE
Notes:
1. X= don’t care
2. If and Erase or Program command specifies a memory region that contains protected data
portion, this command will be ignored.
Datasheet
11. Instructions
The Standard/Dual/Quad SPI instruction set of the FM25Q04B consists of 34 basic instructions
that are fully controlled through the SPI bus (see Table 6 ~ Table 8). Instructions are initiated with
the falling edge of Chip Select (CS#). The first byte of data clocked into the DI input provides the
instruction code. Data on the DI input is sampled on the rising edge of clock with most significant
bit (MSB) first.
The QPI instruction set of the FM25Q04B consists of 23 basic instructions that are fully
controlled through the SPI bus (seeTable 9 QPI Instructions Set9 Instruction Set). Instructions are
initiated with the falling edge of Chip Select (CS#). The first byte of data clocked through DQ[3:0]
pins provides the instruction code. Data on all four DQ pins are sampled on the rising edge of
clock with most significant bit (MSB) first. All QPI instructions, addresses, data and dummy bytes
are using all four DQ pins to transfer every byte of data with every two serial clocks (CLK).
Instructions vary in length from a single byte to several bytes and may be followed by address
bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are
completed with the rising edge of edge CS#. Clock relative timing diagrams for each instruction
are included in Figure 7 through Figure 66. All read instructions can be completed after any
clocked bit. However, all instructions that Write, Program or Erase must complete on a byte
boundary (CS# driven high after a full 8-bits have been clocked) otherwise the instruction will be
ignored. This feature further protects the device from inadvertent writes. Additionally, while the
memory is being programmed or erased, or when the Status Register is being written, all
instructions except for Read Status Register will be ignored until the program or erase cycle has
completed.
11.1. Manufacturer and Device Identification

Table 5Manufacturer and Device Identification
OP Code MF7-MF0 ID15-ID0 ID7-ID0
ABh 12h
90h,92h,94h A1h 12h
9Fh A1h 4013h
Datasheet
11.2. Standard SPI Instructions Set
Table 6Standard SPI Instructions Set (1)
INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
CLOCK NUMBER (0-7) (8-15) (16-23) (24-31) (32-39) (40-47)
Write Enable 06h
Volatile SR Write Enable 50h
Write Disable 04h
Read Status Register-1 05h (S7-S0)(2)
Write Status Register-1 01h S7-S0
Write Status Register-2 31h S15-S8
Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3)
Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0
Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0
Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0
Chip Erase C7h/60h
Power-down B9h
Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0)
Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Release Powerdown / ID(4) ABh dummy dummy dummy (ID7-ID0) (2)
Manufacturer/Device ID(4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0)

(ID15-ID8)
(MF7-MF0) (ID7-ID0)
JEDEC ID(4) 9Fh Memory
Manufacture Capacity
Type
Read SFDP Register 5Ah 00h 00h A7-A0 dummy (D7-D0)
(UID63-
Read Unique ID(5) 4Bh dummy dummy dummy dummy
UID0)
EraseSecurity Sectors(6) 44h A23-A16 A15-A8 A7-A0
ProgramSecurity Sectors(6) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3)
ReadSecurity Sectors(6) 48h A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Enable QPI 38h
Enable Reset 66h
Reset 99h
Datasheet
11.3. Dual SPI Instructions Set
Table 7Dual SPI Instructions Set
INSTRUCTION
BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
NAME
CLOCK NUMBER (0-7) (8-15) (16-23) (24-31) (32-39) (40-47)
Fast Read Dual
3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(8)
Output
A7-A0, M7- (D7-
Fast Read Dual I/O BBh A23-A8(7)
M0 (7) D0, …)(8)
Manufacturer/Device
A7-A0, M7- (MF7-MF0,
ID by 92h A23-A8(7)
M0(7) ID7-ID0)
Dual I/O(4)
11.4. Quad SPI Instructions Set

Table 8Quad SPI Instructions Set
INSTRUCTION
BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
NAME
CLOCK NUMBER (0-7) (8-15) (16-23) (24-31) (32-39) (40-47)
D7-
Quad Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, …(3)
D0, …(10)
Fast Read Quad
6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(10)
Output
A23-A0, (xxxx, D7- (D7-
Fast Read Quad I/O EBh
M7-M0(9) D0)(11) D0, …)(10)
Word Read Quad A23-A0, (xx, D7- (D7-
E7h
I/O(13) M7-M0(9) D0)(12) D0, …)(10)
Octal Word Read A23-A0, (D7-
E3h
Quad I/O(14) M7-M0(9) D0, …)(10)
xxxxxx,
Set Burst with Wrap 77h
W6-W4(9)
Manufacture/Device xxxx, (MF7-
A23-A0, (MF7-MF0,
ID by 94h MF0, ID7-
M7-M0(9) ID7-ID0, …)
Quad I/O(4) ID0)
11.5. QPI Instructions Set

Table 9QPI Instructions Set (15)
CLOCK NUMBER (0,1) (2,3) (4,5) (6,7) (8,9) (10,11)
Write Enable 06h
Write Disable 04h
Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0(10) D7-D0(3)
Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0
Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0
Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0
Chip Erase C7h/60h
Datasheet
Power-down B9h
Set Read Parameters C0h P7-P0
Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy(16) (D7-D0)
Burst Read with
0Ch A23-A16 A15-A8 A7-A0 dummy(16) (D7-D0)
Wrap(17)
(16)
Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0 (D7-D0)
Release Powerdown / (2)
ABh dummy dummy dummy (ID7-ID0)
ID(4)
Manufacturer/Device (ID7-
90h dummy dummy 00h (MF7-MF0)
ID(4) ID0)
(ID15-ID8)
(MF7-MF0) (ID7-ID0)
JEDEC ID(4) 9Fh Memory
Manufacturer Capacity
Type
Disable QPI FFh
Enable Reset 66h
Reset 99h
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )”
indicate data output from the device on either1 or2 or 4 DQ pins.
2. The Status Register contents and Device ID will repeat continuously until CS# terminates the
instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and
Program Security Sectors, up to 256 bytes of data input. If more than 256 bytes of data are
sent to the device, the addressing will wrap to the beginning of the page and overwrite
previously sent data.
4. See Table 5Manufacturer and Device Identification table for device ID information.
5. Please contact Shanghai Fudan Microelectronics Group Co., Ltd for details.
6. Security Sector Address:
Security Sector: A23-A10 = 000h; A9-A8=00~11; A7-A0 = byte address
7. Dual SPI address input format:
DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
8. Dual SPI data output format:
DQ0 = (D6, D4, D2, D0)
DQ1 = (D7, D5, D3, D1)
9. Quad SPI address input format: Set Burst with Wrap input format:
DQ0 = A20, A16, A12, A8, A4, A0, M4, M0 DQ0 = x, x, x, x, x, x, W4, x
DQ3 = A23, A19, A15, A11, A7, A3, M7, M3 DQ3 = x, x, x, x, x, x, x, x
10. Quad SPI data input/output format:
DQ0 = (D4, D0…)
DQ1 = (D5, D1…)
DQ2 = (D6, D2…)
DQ3 = (D7, D3…)
11. Fast Read Quad I/O data output format:
DQ0 = (x, x, x, x, D4, D0, D4, D0)
DQ1 = (x, x, x, x, D5, D1, D5, D1)
DQ2 = (x, x, x, x, D6, D2, D6, D2)
DQ3 = (x, x, x, x, D7, D3, D7, D3)
12. Word Read Quad I/O data output format:
DQ0 = (x, x, D4, D0, D4, D0, D4, D0)
DQ1 = (x, x, D5, D1, D5, D1, D5, D1)
DQ2 = (x, x, D6, D2, D6, D2, D6, D2)
Datasheet
DQ3 = (x, x, D7, D3, D7, D3, D7, D3)
13. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0)
14. For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0)
15. QPI Command Address, Data input/output format:
CLK# 0 1 2 3 4 5 6 7 8 9 10 11
DQ0 C4 C0 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0
DQ1 C5 C1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1
DQ2 C6 C2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2
DQ3 C7 C3 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3
16. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst
Read with Wrap is controlled by read parameter P7 ~ P4.
17. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 ~
P0.
Datasheet
11.6. Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit in the
Status Register to a1. The WEL bit must be set prior to every Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program
Security Sectors instruction. The Write Enable (WREN) instruction is entered by driving CS# low,
shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then
driving CS# high.
CS#
CS# Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Mode 3 0 1 2 3 4 5 6 7 Mode 3 Instruction
CLK Mode 0 Mode 0 (06h)
DQ0
Instruction (06h)
DI DQ1
(DQ0)
DQ2
D0 High Impedance
(DQ1)
DQ3
Figure 7 Write Enable Instruction for SPI Mode (left) or QPI Mode (right)
11.7. Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 10.1 can also be written to as volatile
bits. This gives more flexibility to change the system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the
endurance of the Status Register non-volatile bits. To write the volatile values into the Status
Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior
to a Write Status Register (01h/31h) instruction. Write Enable for Volatile Status Register
instruction (Figure 8) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write
Status Register instruction to change the volatile Status Register bit values.
CS#
CLK Mode 0 Mode 0
Mode 3 0 1 2 3 4 5 6 7 Mode 3 Instruction(
CLK Mode 0 Mode 0 50h)
DQ0
Instruction (50h)
DI DQ1
(DQ0)
DQ2
D0 High Impedance
(DQ1)
DQ3
Figure 8 Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI
Mode (right)
Datasheet
11.8. Write Disable(WRDI) (04h)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit in the
Status Register to a 0. The Write Disable(WRDI) instruction is entered by driving CS# low,
shifting the instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL
bit is automatically reset after Power-up and upon completion of the Write Status Register,
Erase/Program Security Sectors, Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase and Reset instructions.
CS#
CLK Mode 0 Mode 0
Mode 3 0 1 2 3 4 5 6 7 Mode 3
Instruction
CLK Mode 0 (04h)
Mode 0
DQ0
Instruction (04h)
DI DQ1
(DQ0)
DQ2
D0 High Impedance
(DQ1)
DQ3
Figure 9 Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
11.9. Read Status Register-1(RDSR1) (05h) , Status Register-2

(RDSR2)(35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction
is entered by driving CS# low and shifting the instruction code “05h”for Status Register-1 or “35h”
for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown
inFigure 10 and Figure 11. The Status Register bits are shown in Figure 5andFigure 6.
The Read Status Register instruction may be used at any time, even while a Program, Erase or
Write Status Register cycle is in progress. This allows the WIP status bit to be checked to
determine when the cycle is complete and if the device can accept another instruction. The
Status Register can be read continuously, as shown in Figure 10 andFigure 11 The instruction is
completed by driving CS# high.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
Instruction (05h/35h)
DI
(DQ0)
Status Register 1/2 out Status Register 1/2 out
D0 High Impedance
(DQ1) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
=MSB  
Figure 10 Read Status Register Instruction (SPI Mode)
Datasheet
CS#
Mode 3 0 1 2 3 4 5
CLK Mode 0
Instruction
05h/35h
DQ0 4 0 4 0 4
DQ1 5 1 5 1 5
DQ2 6 2 6 2 6
DQ3 7 3 7 3 7
SR1/2 out SR1/2 out
Figure 11 Read Status Register Instruction (QPI Mode)
11.10. Write Status Register-1(WRSR)(01h), Status Register-2 (31h)

The Write Status Register (WRSR) instruction allows the Status Register to be written. Only non-
volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) ,
CMP, DRV0, DRV1, LB, QE, SRP1 (bits 14 and bit 12 thru 8 of Status Register-2) , can be
written to. All other Status Register bit locations are read-only and will not be affected by the
Write Status Register (WRSR) instruction. LB is non-volatile OTP bit, once it is set to 1, it cannot
be cleared to 0. The Status Register bits are shown in shown in Figure 5 and Figure 6 and
described in 10Status Register
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must
previously have been executed for the device to accept the Write Status Register (WRSR)
instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered
by driving CS# low, sending the instruction code “01h”, and then writing the status register data
byte as illustrated in Figure 12 Write Status Register Instruction (SPI Mode)and Figure 133.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction
must have been executed prior to the Write Status Register (WRSR) instruction (Status Register
bit WEL remains 0). However, SRP1 and LB, cannot be changed from “1” to “0” because of the
OTP protection for these bits. Upon power off or the execution of a “Reset (99h)” instruction, the
volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will
be restored.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See
“12.6AC Electrical Characteristics”). While the Write Status Register cycle is in progress, the
Read Status Register instruction may still be accessed to check the status of the WIP bit. The
WIP bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and
ready to accept other instructions again. After the Write Status Register cycle has finished, the
Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after CS# is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See
“12.6AC Electrical Characteristics”). WIP bit will remain 0 during the Status Register bit refresh
period.
Datasheet
The Write Status Register (WRSR) instruction can be used in both SPI mode and QPI mode.
However, the QE bit cannot be written to 0 when the device is in the QPI mode, because QE=1
is required for the device to enter and operate in the QPI mode.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
CLK Mode 0 Mode 0
Instruction (01h/31h) Status Register 1/2 in
DI
7 6 5 4 3 2 1 0
(DQ0)

D0 High Impedance
(DQ1)
=MSB
Figure 12 Write Status Register Instruction (SPI Mode)
CS#
Mode 3 0 1 2 3 Mode 3
CLK Mode 0 Mode 0
Instruction SR 1/2
01h/31h in
DQ0 4 0 4 0
DQ1 5 1 5 1
DQ2 6 2 6 2
7 3 7 3
DQ3
Figure 13 Write Status Register Instruction (QPI Mode)
11.11. Read Data (03h)

The Read Data instruction allows one or more data bytes to be sequentially read from the
memory. The instruction is initiated by driving the CS# pin low and then shifting the instruction
code “03h” followed by a24-bit address A23-A0 into the DI pin. The code and address bits are
latched on the rising edge of the CLK pin. After the address is received, the data byte of the
addressed memory location will be shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first. The address is automatically incremented to the next higher
address after each byte of data is shifted out allowing for a continuous stream of data. This
means that the entire memory can be accessed with a single instruction as long as the clock
continues. The instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in Figure 146. If a Read Data instruction is
issued while an Erase, Program or Write cycle is in process (WIP =1) the instruction is ignored
and will not have any effect on the current cycle. The Read Data instruction allows clock rates
Datasheet
from D.C. to a maximum of fR (see “12.6AC Electrical Characteristics”).
The Read Data (03h) instruction is only supported in Standard SPI mode.
CS#
Mode3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CLK Mode0
Instruction (03h) 24-Bit Addess

DI
23 22 21 3 2 1 0
(DQ0) ▲ Data Out1 Data Out2
DO HIGH IMPEDANCE
7 6 5 4 3 2 1 0 7
(DQ1)
▲
▲ = MSB
Figure 14 Read Data Instruction (SPI Mode only)
11.12. Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR(see “12.6AC Electrical Characteristics”). This is accomplished
by adding eight “dummy” clocks after the 24-bit address as shown in Figure 15. The dummy
clocks allow the devices internal circuits additional time for setting up the initial address. During
the dummy clocks the data value on the DI pin is a “don’t care”.
CS#
Mode
3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode
0
Instruction (0Bh) 24-Bit Address
DI
23 22 21 3 2 1 0
(DQ0)

D0 High Impedance
(DQ1)
=MSB
CS#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Clocks
DI
0
(DQ0)
Data Out 1 Data Out 2

D0 High Impedance
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
(DQ1)
 
Figure 15 Fast Read Instruction (SPI Mode)
Fast Read (0Bh) in QPI Mode
The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the
number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to
accommodate wide range applications with different needs for either maximum Fast Read
Datasheet
frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of
dummy clocks upon power up or after a Reset instruction is 2.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13
CLK Mode 0
Instruction IOs switch from
0Bh A23-16 A15-8 A7-0 Dummy Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2
* "Set Read Parameters" instruction (C0h) can

set the number of dummy clocks.
Figure 16 Fast Read Instruction (QPI Mode)
11.13. Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh)
instruction except that data is output on two pins; DQ0 and DQ1. This allows data to be
transferred from the FM25Q04B at twice the rate of standard SPI devices. The Fast Read Dual
Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for
applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the
highest possible frequency of FR(see “12.6AC Electrical Characteristics”). This is accomplished
by adding eight “dummy” clocks after the 24-bit address as shown in Figure 17. The dummy
clocks allow the device's internal circuits additional time for setting up the initial address. The
input data during the dummy clocks is “don’t care”. However, the DQ0 pin should be high-
impedance prior to the falling edge of the first data out clock.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
DI
23 22 21 3 2 1 0
(DQ0)

D0 High Impedance
(DQ1)
=MSB
CS#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Clocks IO0 switches from

Input to Output
DI 0 6
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
(DQ0)

D0 High Impedance
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
(DQ1)
   
Data Out 1 Data Out 2 Data Out 3 Data Out 4
Figure 17 Fast Read Dual Output Instruction (SPI Mode only)
11.14. Fast Read Quad Output (6Bh)

The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh)
instruction except that data is output on four pins, DQ0, DQ1, DQ2, and DQ3. A Quad enable of
Status Register-2 must be executed before the device will accept the Fast Read Quad Output
Instruction (Status Register bit QE
mustequal1).TheFastReadQuadOutputInstructionallowsdatatobetransferredfromthe FM25Q04B
at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see
“12.6AC Electrical Characteristics”). This is accomplished by adding eight “dummy” clocks after
the 24-bit address as shown in Figure 18. The dummy clocks allow the device's internal circuits
additional time for setting up the initial address. The input data during the dummy clocks is “don’t
care”. However, the DQ pins should be high-impedance prior to the falling edge of the first data
out clock.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
DQ0 23 22 21 3 2 1 0

High Impedance
DQ1
High Impedance
DQ2
High Impedance
DQ3
=MSB
CS#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
CLK
Dummy Clocks IO0 switches from

Input to Output
DQ0 0 4 0 4 0 4 0 4 0 4
High Impedance
DQ1 5 1 5 1 5 1 5 1 5
High Impedance
DQ2 6 2 6 2 6 2 6 2 6
High Impedance
DQ3 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
Figure 18 Fast Read Quad Output Instruction (SPI Mode only)
11.15. Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining
two I/O pins, DQ0 and DQ1. It is similar to the Fast Read Dual Output (3Bh) instruction but with
the capability to input the Address bits A23-A0 two bits per clock. This reduced instruction
overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”

TheFastReadDualI/Oinstructioncanfurtherreduceinstructionoverheadthroughsettingthe“Continuou
s Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 19. The upper
nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0)are
“don’t care (“x”)”. However, the DQ pins should be high-impedance prior to the falling edge of the
first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction
(after CS# is raised and then lowered) does not require the BBh instruction code, as shown in
Figure 20. This reduces the instruction sequence by eight clocks and allows the Read address to
Datasheet
be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do
not equal to (10), the next instruction (after CS# is raised and then lowered) requires the first byte
instruction code, thus returning to normal operation. It is recommended to input FFFFh on DQ0 for
the next (8 clocks), to ensure M4 = 1 and return the device to normal operation.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
Instruction (BBh) A23-16 A15-8 A7-0 M7-0
DI
22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
(DQ0)
D0
(DQ1) 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
=MSB  
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
CLK
IOs switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(DQ0)
D0
1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
(DQ1)
   
Byte 1 Byte 2 Byte 3 Byte 4
Figure 19 Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI
Mode only)
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK Mode 0
A23-16 A15-8 A7-0 M7-0
DI 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0
(DQ0)
D0
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
(DQ1)
 
=MSB
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLK
IOs switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(DQ0)
D0
1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
(DQ1)
   
Byte 1 Byte 2 Byte 3 Byte 4
Figure 20 Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode
only)
11.16. Fast Read Quad I/O (EBh)

The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction
except that address and data bits are input and output through four pins DQ0, DQ1, DQ2 and DQ3
and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O
dramatically reduces instruction overhead allowing faster random access for code execution (XIP)
directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable
the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”

TheFastReadQuadI/Oinstructioncanfurtherreduceinstructionoverheadthroughsettingthe“Continuo
us Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 21. The upper
nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction
(after CS# is raised and then lowered) does not require the EBh instruction code, as shown in
not equal to (1,0), the next instruction (after CS# is raised and then lowered) requires the first
byte instruction code, thus returning to normal operation. It is recommended to input FFh on DQ0
for the next instruction (8 clocks), to ensure M4= 1 and return the device to normal operation.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
Instruction (EBh) A23-16 A15-8 A7-0 M7-0 Dummy Dummy IOs switch from
Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6
Dq3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3
Figure 21 Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, SPI
Mode)
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK Mode 0
A23-16 A15-8 A7-0 M7-0 Dummy Dummy IOs switch from

Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3
Figure 22 Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page
by issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h)
command can either enable or disable the “Wrap Around” feature for the following EBh
commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8,
16, 32 or 64-byte section of a256-byte page. The output data starts at the initial address specified
in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output
will wrap around to the beginning boundary automatically until CS# is pulled high to terminate the
command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing
multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used
to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the
wrap around section within a page. See “11.19Set Burst with Wrap (77h)” for detail descriptions.
Datasheet
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 23. When
QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters
(C0h)” instruction to accommodate a wide range application with different needs for either
maximum Fast Read frequency or minimum data access latency. Depending on the Read
Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or
8. The default number of dummy clocks upon power up or after a Reset instruction is 2. In QPI
mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the
default setting, the data output will follow the Continuous Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O
instruction. Please refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To
perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst
Read with Wrap” (0Ch) instruction must be used. Please refer to “11.38Burst Read with Wrap
(0Ch)” for details.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK Mode 0
EBh A23-16 A15-8 A7-0 M7-0 Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3
* "Set Read Parameters" instruction (C0h) can

Figure 23 Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, QPI
Mode)
11.17. Word Read Quad I/O (E7h)

The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required
prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of
Status Register-2 must be set to enable the Word Read Quad I/O Instruction.
Word Read Quad I/O with “Continuous Read Mode”

TheWordReadQuadI/Oinstructioncanfurtherreduceinstructionoverheadthroughsettingthe“Continuo
us Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 24. The upper
Datasheet
nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are
(after CS# is raised and then lowered) does not require the E7h instruction code, as shown in
for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
CLK Mode 0
Instruction (E7h) A23-16 A15-8 A7-0 M7-0 Dummy IOs switch from
Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3
Figure 24 Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI
Mode only)
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13
CLK Mode 0
A23-16 A15-8 A7-0 M7-0 Dummy IOs switch from

Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3
Figure 25 Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode
only)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Word Read Quad I/O instruction can also be used to access a specific portion within a page
by issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h)
Datasheet
command can either enable or disable the “Wrap Around” feature for the following E7h
commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8,
16, 32 or 64-byte section of a256-byte page. The output data starts at the initial address specified
in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output
will wrap around to the beginning boundary automatically until CS# is pulled high to terminate the
command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing
multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used
to enable or disable the “Wrap Around” operation while W6-5 bits are used to specify the length of
the wrap around section within a page. See “11.19Set Burst with Wrap (77h)” for detail
descriptions.
11.18. Octal Word Read Quad I/O (E3h)

The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh)
instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the
dummy clocks are not required, which further reduces the instruction overhead allowing even
faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register-2
must be set to enable the Octal Word Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”

The Octal Word Read Quad I/O instruction can further reduce instruction overhead through
setting the “Continuous Read Mode” bits M7-M0 after the input Address bits A23-A0, as shown in
Figure 26. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad
I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower
nibble bits of the (M3-0) are “don’t care (“x”)”. However, the DQ pins should be high-impedance
prior to the falling edge of the first data out clock.
(after CS# is raised and then lowered) does not require the E3h instruction code, as shown in
for the next instruction (8 clocks), to ensure M4= 1 and return the device to normal operation.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
CLK Mode 0
Instruction (E3h) A23-16 A15-8 A7-0 M7-0 IOs switch from

Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7
Figure 26 Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10,
Datasheet
SPI Mode only)
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13
CLK Mode 0
IOs switch from
A23-16 A15-8 A7-0 M7-0
Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7
Figure 27 Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI
Mode only)
11.19. Set Burst with Wrap (77h)

In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast
Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-
byte section within a 256-byte page. Certain applications can benefit from this feature and
improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the
CS# pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap
Bits”, W7-0. The instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble
W3-0 are not used.
W4 = 0 W4 =1 (default)
W6, W5
Wrap Around Wrap Length Wrap Around Wrap Length
00 Yes 8-byte No N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and
“Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte
section within any page. To exit the “Wrap Around” function and return to normal read operation,
another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4
upon power on is 1. In the case of a system Reset while W4 = 0, it is recommended that the
controller issues a Set Burst with Wrap instruction to reset W4 = 1 prior to any normal Read
instructions since FM25Q04B does not have a hardware Reset Pin.
In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read
Datasheet
operation with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still
valid in QPI mode and can also be re-configured by “Set Read Parameters (C0h)” instruction.
Refer to “11.37Set Read Parameters (C0h)” and“11.38Burst Read with Wrap (0Ch)” for details.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3
CLK Mode 0 Mode 0
don’t don’t don’t Wrap
Instruction (77h)
care care care Bit
DQ0 X X X X X X W4 X
DQ3 X X X X X X X X
Figure 28 Set Burst with Wrap Instruction (SPI Mode only)
11.20. Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be
programmed at previously erased(FFh) memory locations. A Write Enable instruction must be
executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1).
The instruction is initiated by driving the CS# pin low then shifting the instruction code “02h”
followed by a 24-bit address A23-A0 and at least one data byte, into the DI pin. The CS# pin must
be held low for the entire length of the instruction while data is being sent to the device. The Page
Program instruction sequence is shown in Figure 29 and Figure 30.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant
address bits) should be set to 0. If the last address byte is not zero, and the number of clocks
exceeds the remaining page length, the addressing will wrap to the beginning of the page. In
some cases, less than 256 bytes (a partial page) can be programmed without having any effect
on other bytes within the same page. One condition to perform a partial page program is that the
number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to
the device the addressing will wrap to the beginning of the page and overwrite previously sent
data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the
last byte has been latched. If this is not done the Page Program instruction will not be executed.
After CS# is driven high, the self-timed Page Program instruction will commence for time duration
of tPP (See “12.6AC Electrical Characteristics”). While the Page Program cycle is in progress, the
Read Status Register instruction may still be accessed for checking the status of the WIP bit. The
WIP bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Page Program cycle has finished the
Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction
will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2-0) bits.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CLK Mode 0
Instruction (02h) 24-Bit Address Data Byte 1
DI
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
(DQ0)
 
=MSB
CS#
2072
2073
2074
2075
2076
2077
2078
2079
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3
CLK Mode 0
Data Byte 2 Data Byte 3 Data Byte 256

DI
(DQ0) 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
  
Figure 29 Page Program Instruction (SPI Mode)
CS#
516
517
518
519
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Mode 3
CLK Mode 0 Mode 0
Instruction
A23-16 A15-8 A7-0 Byte1 Byte2 Byte3 Byte 255 Byte 256
02h
DQ0 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0
DQ1 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1
DQ2 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2
DQ3 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3
Figure 30 Page Program Instruction (QPI Mode)
11.21. Quad Input Page Program (32h)

The Quad Page Program instruction allows up to 256 bytes of data to be programmed at
previously erased (FFh) memory locations using four pins: DQ0, DQ1, DQ2, and DQ3.The Quad
Page Program can improve performance for PROM Programmer and applications that have slow
clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad
Page Program instruction since the inherent page program time is much greater than the time it
take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write
Enable instruction must be executed before the device will accept the Quad Page Program
instruction (Status Register-1, WEL=1). The instruction is initiated by driving the CS# pin low then
shifting the instruction code “32h” followed by a 24-bit address A23-A0 and at least one data byte,
into the DQ pins. The CS# pin must be held low for the entire length of the instruction while data
is being sent to the device. All other functions of Quad Page Program are identical to standard
Page Program. The QuadPage Program instruction sequence is shown in Figure 31.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
Instruction (32h) 24-Bit Address
DQ0 23 22 21 3 2 1 0

DQ1
DQ2
DQ3
=MSB
CS#
536
537
538
539
540
541
542
543
31 32 33 34 35 36 37 Mode 3
CLK
Mode 0
Byte1 Byte2 Byte3 Byte 253 Byte 254 Byte 255 Byte256
DQ0 0 4 0 4 0 4 0 4 0
4 0 4 0 4 0
DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
DQ2 6 2 6 2 6 2 6 2
6 2 6 2 6 2
DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
      
Figure 31 Quad Input Page Program Instruction (SPI Mode only)
11.22. Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased
state of all1s (FFh). A Write Enable instruction must be executed before the device will accept the
Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by
driving the CS# pin low and shifting the instruction code “20h” followed a 24-bit sector address
A23-A0 (see Figure 1). The Sector Erase instruction sequence is shown in Figure 32&Figure 33.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After CS# is driven high, the self-timed
Sector Erase instruction will commence for a time duration of tSE (See “12.6AC Electrical
Characteristics”). While the Sector Erase cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during
the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to
accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed
if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits
(see Table 4Status Register Memory Protection table).
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0

DI
23 22 2 1 0
(DQ0)

DI High Impedance
(DQ1)
=MSB
Figure 32 Sector Erase Instruction (SPI Mode)
CS#
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction
A23-16 A15-8 A7-0
20h
DQ0 20 16 12 8 4 0
DQ1 21 17 13 9 5 1
DQ2 22 18 14 10 6 2
DQ3 23 19 15 11 7 3
Figure 33 Sector Erase Instruction (QPI Mode)
11.23. 32KB Block Erase (BE32) (52h)

The 32KB Block Erase instruction sets all memory within a specified block (32K-bytes) to the
erased state of all1s (FFh). A Write Enable instruction must be executed before the device will
accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is
initiated by driving the CS# pin low and shiftingthe instructioncode“52h”followeda24-bit block
address A23-A0. The Block Erase instruction sequence is shown in Figure 34&Figure 35.
done the Block Erase instruction will not be executed. After CS# is driven high, the self-timed
Block Erase instruction will commence for time duration of tBE1 (See “12.6AC Electrical
Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction
may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Block
Datasheet
Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Block Erase instruction will not be executed if the
addressed page is protected by the Block Protect (CMP, SEC, TB and BP2-0) bits (see Table
4Status Register Memory Protection table).
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0

DI
23 22 2 1 0
(DQ0)

DI High Impedance
(DQ1)
=MSB
Figure 34 32KB Block Erase Instruction (SPI Mode)
CS#
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction
A23-16 A15-8 A7-0
52h
DQ0 20 16 12 8 4 0
DQ1 21 17 13 9 5 1
DQ2 22 18 14 10 6 2
DQ3 23 19 15 11 7 3
Figure 35 32KB Block Erase Instruction (QPI Mode)
11.24. 64KB Block Erase (BE) (D8h)

The 64KB Block Erase instruction sets all memory within a specified block (64K-bytes) to the
erased state of all1s (FFh). A Write Enable instruction must be executed before the device will
accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is
initiated by driving the CS# pin low and shifting the instruction code “D8h” followed a 24-bit block
address A23-A0. The Block Erase instruction sequence is shown in Figure 36&Figure 37.
done the Block Erase instruction will not be executed. After CS# is driven high, the self-timed
Datasheet
Block Erase instruction will commence for a time duration of tBE (See 12.6AC Electrical
Characteristics”). While the Block Erase cycle is in progress, the Read Status Register instruction
may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Block
Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Block Erase instruction will not be executed if the
addressed page is protected by the Block Protect (CMP, SEC, TB and BP2-0) bits (see Table
4Status Register Memory Protectiontable).
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0
Instruction (D8h) 24-Bit Address

DI
23 22 2 1 0
(DQ0)

DI High Impedance
(DQ1)
=MSB
Figure 36 64KB Block Erase Instruction (SPI Mode)
CS#
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction
A23-16 A15-8 A7-0
D8h
DQ0 20 16 12 8 4 0
DQ1 21 17 13 9 5 1
DQ2 22 18 14 10 6 2
DQ3 23 19 15 11 7 3
Figure 37 64KB Block Erase Instruction (QPI Mode)
Datasheet
11.25. Chip Erase (CE) (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS#
pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is
shown in Figure 38.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instructionwill not be executed. After CS# is driven high, the self-timed Chip Erase
instruction will commence for time duration of tCE (See “12.6AC Electrical Characteristics”). While
the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to
check the status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0
when finished and the device is ready to accept other instructions again. After the Chip Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Chip Erase instruction will not be executed if any page is protected by the Block Protect (CMP,
SEC, TB and BP2-0) bits.
CS#
CLK Mode 0 Mode 0
Mode 3 0 1 2 3 4 5 6 7 Mode 3 Instruction
CLK Mode 0 Mode 0 C7h/60h
DQ0
Instruction (C7h/60h)
DI DQ1
(DQ0)
DQ2
D0 High Impedance
(DQ1)
DQ3
Figure 38 Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)
11.26. Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can be
further reduced with the Power-down instruction. The lower power consumption makes the
Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2
in“12.4DC Electrical Characteristics”). The instruction is initiated by driving the CS# pin low and
shifting the instruction code “B9h” as shown in Figure 39&Figure 40.
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the
Power-down instruction will not be executed. After CS# is driven high, the power-down state will
enter within the time duration of tDP (See “12.6AC Electrical Characteristics”). While in the power-
down state only the Release from Power- down / Device ID instruction, which restores the device
to normal operation, will be recognized. All other instructions are ignored. This includes the Read
Status Register instruction, which is always available during normal operation. Ignoring all but
one instruction makes the Power Down state a useful condition for securing maximum write
protection. The device always powers-up in the normal operation with the standby current of ICC1.
Datasheet
CS#
tDP
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (B9h)
DI
(DQ0)
Stand-by current Power-down current
Figure 39 Deep Power-down Instruction (SPI Mode)
CS#
tDP
Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Instruction
B9h
DQ0
DQ1
DQ2
DQ3
Stand-by current Power-down current
Figure 40 Deep Power-down Instruction (QPI Mode)
11.27. Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be
used to release the device from the power-down state, or obtain the devices electronic
identification (ID) number.
To release the device from the power-down state, the instruction is issued by driving the CS# pin
low, shifting the instruction code “ABh” and driving CS# high as shown in Figure 41&Figure 42.
Release from power-down will take the time duration of tRES1 (See “12.6AC Electrical
Characteristics”) before the device will resume normal operation and other instructions are
accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is
initiated by driving the CS# pin low and shifting the instruction code “ABh” followed by 3-dummy
bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit
Datasheet
(MSB) first as shown in Figure 41&Figure 42. The Device ID value for the FM25Q04B is listed in
Table 5Manufacturer and Device Identification table. The Device ID can be read continuously.
The instruction is completed by driving CS# high.
When used to release the device from the power-down state and obtain the Device ID, the
instruction is the same as previously described, and shown in Figure 43&Figure 44, except that
after CS# is driven high it must remain high for a time duration of tRES2 (See “12.6AC Electrical
Characteristics”). After this time duration the device will resume normal operation and other
instructions will be accepted. If the Release from Power-down / Device ID instruction is issued
while an Erase, Program or Write cycle is in process (when WIP equals1) the instruction is
ignored and will not have any effect on the current cycle.
CS#
tRES1
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (ABh)
DI
(DQ0)
Power-down current Stand-by current
Figure 41 Release Power-down Instruction (SPI Mode)
CS#
tRES1
Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Instruction
ABh
DQ0
DQ1
DQ2
DQ3
Figure 42 Release Power-down Instruction (QPI Mode)
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 Mode 3
CLK Mode 0 Mode 0
Instruction (ABh) 3 Dummy Bytes tRES2
DI 23 22 2 1 0
(DQ0)

Device ID
D0 High Impedance
7 6 5 4 3 2 1 0
(DQ1)

=MSB Power-down current Stand-by current
Figure 43 Release Power-down / Device ID Instruction (SPI Mode)
CS#
tRES2
Mode 3 0 1 2 3 4 5 6 7 8 Mode 3
CLK Mode 0 Mode 0
3 Dummy Bytes
ABh Input to Output
DQ0 X X X X X X 4 0
DQ1 X X X X X X 5 1
DQ2 X X X X X X 6 2
DQ3 X X X X X X 7 3
Device ID
Figure 44 Release Power-down / Device ID Instruction (QPI Mode)
11.28. Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
DeviceID instruction that provides both the JEDEC assigned manufacturer ID and the specific
device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down /
Device ID instruction. The instruction is initiated by driving the CS# pin low and shifting the
instruction code “90h” followed by a 24-bit address A23-A0 of 000000h. After which, the
Manufacturer ID for Shanghai Fudan Microelectronics Group Co., Ltd (A1h) and the Device ID
are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure
45&Figure 46. The Device ID value for the FM25Q04B is listed in Table 5Manufacturer and
Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be
read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be
read continuously, alternating from one to the other. The instruction is completed by driving CS#
high.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
Instruction (90h) Address (000000h)

DI
23 22 21 3 2 1 0
(DQ0)

DI High Impedance
(DQ1)
=MSB
CS#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Mode 3
CLK Mode 0
DI 0
(DQ0)
D0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
(DQ1)

Manufacturer ID Device ID
Figure 45 Read Manufacturer / Device ID Instruction (SPI Mode)
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 Mode 3
CLK Mode 0 Mode 0
Instruction A7-0 IOs switch from
A23-16 A15-8
90h (00h) Input to Output
DQ0 20 16 12 8 4 0 4 0 4 0
DQ1 21 17 13 9 5 1 5 1 5 1
DQ2 22 18 14 10 6 2 6 2 6 2
DQ3 23 19 15 11 7 3 7 3 7 3
MFR ID Device ID
Figure 46 Read Manufacturer / Device ID Instruction (QPI Mode)
Datasheet
11.29. Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read
Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and
the specific device ID at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O
instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“92h” followed by a24-bit address A23-A0 of 000000h, 8-bit Continuous Read Mode Bits, with the
capability to input the Address bits two bits per clock. After which, the Manufacturer ID for
Shanghai Fudan Microelectronics Group Co., Ltd (A1h) and the Device ID are shifted out 2 bits
per clock on the falling edge of CLK with most significant bits (MSB) first as shown in Figure 47.
The Device ID value for the FM25Q04B is listed in Table 5Manufacturer and Device Identification
table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then
followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously,
alternating from one to the other. The instruction is completed by driving CS# high.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
Instruction (92h) A23-16 A15-8 A7-0 (00h) M7-0
DI 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
(DQ0)
D0 High Impedance
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
(DQ1)
=MSB    
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Mode 3
CLK Mode 0
IOs switch from

Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
(DQ0)
D0
1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
(DQ1)
   MFR ID  Device ID
MFR ID Device ID
(repeat) (repeat)
Figure 47 Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only)
Note:
The “Continuous Read Mode” bits M7-M0 must be set to Fxh to be compatible with Fast Read
Dual I/O instruction.
11.30. Read Manufacturer / Device ID Quad I/O (94h)

The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read
Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and
the specific device ID at 4x speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O
instruction. The instruction is initiated by driving the CS# pin low and shifting the instruction code
“94h” followed by a 24-bit address A23-A0 of 000000h, 8-bit Continuous Read Mode Bits and
then four clock dummy cycles, with the capability to input the Address bits four bits per clock.
After which, the Manufacturer ID for Shanghai Fudan Microelectronics Group Co., Ltd (A1h) and
the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit
Datasheet
(MSB) first as shown in Figure 48. The Device ID value for the FM25Q04B is listed in
Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the
Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and
Device IDs can be read continuously, alternating from one to the other. The instruction is
completed by driving CS# high.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
Instruction (94h) A23-16 A15-8 A7-0 M7-0 Dummy Dummy IOs switch from
(00h) Input to Output
DQ0 4 0 4 0 4 0 4 0 4 0 4 0
High Impedance
DQ1 5 1 5 1 5 1 5 1 5 1 5 1
High Impedance
DQ2 6 2 6 2 6 2 6 2 6 2 6 2
High Impedance
DQ3 7 3 7 3 7 3 7 3 7 3 7 3
MFR ID Device ID
CS#
23 24 25 26 27 28 29 30 Mode 3
CLK Mode 0
DQ0 0 4 0 4 0 4 0 4 0
DQ1 1 5 1 5 1 5 1 5 1
DQ2 2 6 2 6 2 6 2 6 2
DQ3 3 7 3 7 3 7 3 7 3
MFR ID Device ID MFR ID Device ID

(repeat) (repeat) (repeat) (repeat)
Figure 48 Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only)
Note:
The “Continuous Read Mode” bits M7-M0 must be set to Fxh to be compatible with Fast Read
Quad I/O instruction.
11.31. Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is
unique to each FM25Q04B device. The ID number can be used in conjunction with user software
methods to help prevent copying or cloning of a system. The Read Unique ID instruction is
initiated by driving the CS# pin low and shifting the instruction code “4Bh” followed by a four bytes
of dummy clocks. After which, the 64- bit ID is shifted out on the falling edge of CLK as shown in
Figure 49.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
Instruction (4Bh) Dummy Byte 1 Dummy Byte 2

DI
(DQ0)
D0 High Impedance
(DQ1)
CS#
100
101
102
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Mode 3
CLK Mode 0
Dummy Byte 3 Dummy Byte 4

DI
(DQ0)
High Impedance
D0 63 62 61 2 1 0
(DQ1)
=MSB 
64-bit Unique Serial Number
Figure 49 Read Unique ID Number Instruction (SPI Mode only)
11.32. Read JEDEC ID (9Fh)

For compatibility reasons, the FM25Q04B provides several instructions to electronically
determine the identity of the device. The Read JEDEC ID instruction is compatible with the
JEDEC standard for SPI compatible serial memories. The instruction is initiated by driving the
CS# pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte
for Shanghai Fudan Microelectronics Group Co., Ltd (A1h) and two Device ID bytes, Memory
Type (ID15-ID8) and Capacity ID7-ID0 are then shifted out on the falling edge of CLK with most
significant bit (MSB) first as shown in Figure 50&Figure 51. For memory type and capacity values
refer to Table 5Manufacturer and Device Identification table.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK Mode 0
Instruction (9Fh)
DI
(DQ0)
Manufacturer ID
D0 High Impedance
(DQ1)
=MSB
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3
CLK
Mode 0
DI
(DQ0)
Memory Type ID 15-8 Capacity ID 7-0

D0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
(DQ1)
 
Figure 50 Read JEDEC ID Instruction (SPI Mode)
CS#
Mode 3 0 1 2 3 4 5 6 Mode 3
CLK Mode 0 Mode 0
9Fh Input to Output
DQ0 12 8 4 0
DQ1 13 9 5 1
DQ2 14 10 6 2
DQ3 15 11 7 3
MFR ID ID 15-8 ID 7-0
Figure 51 Read JEDEC ID Instruction (QPI Mode)
Datasheet
11.33. Read SFDP Register(5Ah)
The FM25Q04B features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that
contains information about device configurations, available instructions and other features. The
SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only
one PID table is specified. The Read SFDP Register instruction is compatible with the SFDP
standard initially established in 2010 for PC and other applications, as well as the JEDEC
standard 1.0 that is published in 2011.
The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction
code “5Ah” followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight “dummy” clocks are
also required before the SFDP register contents are shifted out on the falling edge of the 40th
CLK with most significant bit (MSB) first as shown in Figure 52. For SFDP register values and
descriptions, refer to the following SFDP Definition table.
Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP
Register.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
Instruction (5Ah) 24-Bit Address

DI
(DQ0) 23 22 21 3 2 1 0

D0 High Impedance
(DQ1)
CS#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Byte
DI
(DQ0) 0 7 6 5 4 3 2 1 0
D0 High Impedance
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
(DQ1)
=MSB  
Figure 52 Read SFDP Register Instruction
Serial Flash Discoverable Parameter (JEDEC Revision 1.0) Definition Table

BYTE
DATA DESCRIPTION COMMENT
ADDRESS
00h 53h SFDP Signature
01h 46h SFDP Signature SFDP Signature
02h 44h SFDP Signature = 50444653h
03h 50h SFDP Signature
04h 00h SFDP Minor Revision Number
JEDEC Revision 1.0
05h 01h SFDP Major Revision Number
06h 00h Number of Parameter Headers (NPH) 1 Parameter Header
07h FFh Reserved
08h 00h PID(3)(0): ID Number 00h = JEDEC specified
09h 00h PID(0): Parameter Table Minor Revision Number JEDEC Revision 1.0
Datasheet
BYTE
ADDRESS
0Ah 01h PID(0): Parameter Table Major Revision Number
0Bh 09h PID(0): Parameter Table Length 9 Dwords(2)
0Ch 80h PID(0): Parameter Table Pointer (PTP) (A7-A0)
PID(0) Pointer =
0Dh 00h PID(0): Parameter Table Pointer (PTP) (A15-A8)
000080h
0Eh 00h PID(0): Parameter Table Pointer (PTP) (A23-A16)
0Fh FFh Reserved
10h FFh Reserved
...(1) FFh Reserved
7Fh FFh Reserved
Bit[7:5]=111 Reserved
Bit[4:3]=00 Non-volatile Status Register
80h E5h
Bit[2]=1 Page Programmable
Bit[1:0]=01 Supports 4KB Erase
81h 20h 4K-Byte Erase Op code
Bit[7] =1 Reserved
Bit[6] =1 Supports (1-1-4) Fast Read
82h F1h Bit[3] =0 Not support Dual Transfer
Rate
Bit[2:1]=00 3-Byte/24-Bit Only
Addressing
83h FFh Reserved
84h FFh Flash Size in Bits
85h FFh Flash Size in Bits 4 Mega Bits =
86h 3Fh Flash Size in Bits 003FFFFFh
87h 00h Flash Size in Bits
Bit[7:5]=010 8 Mode Bits are needed
88h 44h Fast Read Quad I/O
Bit[4:0]=00100 16 Dummy Bits are needed
Setting
89h EBh Quad Input Quad Output Fast Read Op code
Bit[7:5]=000 No Mode Bits are needed
8Ah 08h Fast Read Quad
Output Setting
8Bh 6Bh Single Input Quad Output Fast Read Op code
Bit[7:5]=000 No Mode Bits are needed
8Ch 08h Fast Read Dual Output
Setting
8Dh 3Bh Single Input Dual Output Fast Read Op code
Bit[7:5]=100 8 Mode bits are needed
8Eh 80h Fast Read Dual I/O
Bit[4:0]=00000 No Dummy bits are needed
Setting
8Fh BBh Dual Input Dual Output Fast Read Op code
Bit[4]=1 support (4-4-4) Fast Read
90h FEh
Bit[0]=0 Not support (2-2-2) Fast Read
91h FFh Reserved
92h FFh Reserved
93h FFh Reserved
94h FFh Reserved
95h FFh Reserved
No Mode Bits or Dummy Bits for (2-2-2) Fast
96h 00h
Read
Datasheet
BYTE
ADDRESS
97h 00h Not support (2-2-2) Fast Read
98h FFh Reserved
99h FFh Reserved
Bit[7:5]=000 No Mode bits are needed
9Ah 08h
Bit[4:0]=01000 8 Dummy bits are needed
9Bh EBh QPI Fast Read Op code
9Ch 0Ch Sector Type 1 Size (4KB)
9Dh 20h Sector Type 1 Op code Sector Erase
9Eh 0Fh Sector Type 2 Size (32KB) Type &Op code
9Fh 52h Sector Type 2 Op code
A0h 10h Sector Type 3 Size (64KB)
A1h D8h Sector Type 3 Op code Sector Erase
A2h 00h Sector Type 4 Size (256KB) – Not supported Type &Op code
A3h 00h Sector Type 4 Op code – Not supported
...(1) FFh Reserved
FFh FFh Reserved
Notes:
1. Data stored in Byte Address 10h to 7Fh& A4h toFFh arereserved, thevalue isFFh.
2. 1Dword=4 Bytes
3. PID(x)= Parameter IdentificationTable (x)
11.34. Erase Security Sector(44h)

The FM25Q04B offers one 1024-byte Security Sector. TheSecurity Sector may be used by the
system manufacturers to store security and other important information separately from the main
memory array.
TheEraseSecurity SectorinstructionissimilartotheSectorEraseinstruction.AWriteEnable instruction

must be executed before the device will accept the Erase Security Sector Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting
the instruction code “44h” followed by a 24-bit address A23-A0 to erase Security Sectors.
A23-16 A15-10 A9-0

00h 000000 Don’t Care
The Erase Security Sector instruction sequence is shown in Figure 53. The CS# pin must be
driven high after the eighth bit of the last byte has been latched. If this is not done the instruction
will not be executed. After CS# is driven high, the self-timed Erase Security Sector operation will
commence for a time duration of tSE (See “12.6AC Electrical Characteristics”). While the Erase
Security Sector cycle is in progress, the Read Status Register instruction may still be accessed
for checking the status of the WIP bit. The WIP bit is a 1 during the erase cycle and becomes a 0
when the cycle is finished and the device is ready to accept other instructions again. After the
Erase Security Sector cycle has finished the Write Enable Latch (WEL) bit in the Status Register
is cleared to 0. The Security Sector Lock Bit (LB) in the Status Register-
2canbeusedtoOTPprotecttheSecurity Sectors.Oncethe LB bit is set to 1,the Security Sector will
be permanently locked, Erase Security Sector instruction will be ignored.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0

DI
23 22 2 1 0
(DQ0)

DI High Impedance
(DQ1)
=MSB
Figure 53 Erase Security Sector Instruction (SPI Mode only)
11.35. Program Security Sector (42h)

The Program Security Sector instruction is similar to the Page Program instruction. It allows from
one byte to256bytes of Security Sectordatato be programmed at previously erased(FFh) memory
locations. A Write Enable instruction must be executed before the device will accept the Program
Security Sector Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the
CS# pin low then shifting the instruction code “42h” followed by a 24-bit address A23-A0 and at
least one data byte, into the DI pin. The CS# pin must be held low for the entire length of the
instruction while data is being sent to the device.
A23-16 A15-10 A9-8 A7-0

00
01
00h 0000 Byte Address
10
11
The Program Security Sector instruction sequence is shown in Figure 54. The Security Sector
Lock Bit (LB) in the Status Register-2 can be used to OTP protect the Security Sectors. Once a
lock bit is set to 1, the Security Sector will be permanently lockedand Program Security Sector
instruction will be ignored.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CLK Mode 0
Instruction (42h) 24-Bit Address Data Byte1
DI 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
(DQ0)
 
=MSB
CS#
2072
2073
2074
2075
2076
2077
2078
2079
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3
CLK Mode 0
Data Byte 2 Data Byte 3 Data Byte 256

DI
(DQ0) 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
  
Figure 54 Program Security Sectors Instruction (SPI Mode only)
Datasheet
11.36. Read Security Sector (48h)
The Read Security Sector instruction is similar to the Fast Read instruction and allows one or
more data bytes to be sequentially read from the Security Sector. The instruction is initiated by
driving the CS# pin low and then shifting the instruction code “48h”followed by a 24-bit address
A23-A0 and eight “dummy” clocks into the DI pin. The code and address bits are latched on the
rising edge of the CLK pin. After the address is received, the data byte of the addressed memory
location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB)
first. The byte address is automatically incremented to the next byte address after each byte of
data is shifted out. Once the byte address reaches 3FFh (the last byte of the register), it will be
reset to 00h(the first byte of the register) and continue to increment. The instruction is completed
by driving CS# high. The Read Security Sector instruction sequence is shown in Figure 55. If a
Read Security Sector instruction is issued while an Erase, Program or Write cycle is in process
(WIP =1) the instruction is ignored and will not have any effect on the current cycle. The Read
Security Sector instruction allows clock rates from D.C. to a maximum of FR (see “12.6AC
Electrical Characteristics”).
A23-16 A15-10 A9-8 A7-0

00
01
00h 0000 Byte Address
10
11
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
DI
23 22 21 3 2 1 0
(DQ0)

DI High Impedance
(DQ1)
=MSB
CS#
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Byte
DI
(DQ0) 0 7 6 5 4 3 2 1 0

DI High Impendance
(DQ1) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
 
Figure 55 Read Security Sectors Instruction (SPI Mode only)
Datasheet
11.37. Set Read Parameters (C0h)
In QPI mode, to accommodate a wide range of applications with different needs for either
maximum read frequency or minimum data access latency, “Set Read Parameters (C0h)”
instruction can be used to configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast
Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions, and to configure the number
of bytes of “Wrap Length” for the “Burst Read with Wrap (0Ch)” instruction.
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy
clocks for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer
to Table 9 QPI Instructions Setthe Instruction set for details. The “Wrap Length” is set by W5-4 bit
in the “Set Burst with Wrap (77h)” instruction. This setting will remain unchanged when the device
is switched from Standard SPI mode to QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number
of dummy clocks is 2.
DUMMY MAXIMUM READ P1 – P0 WRAP LENGTH
P5 – P4
CLOCKS FREQ. 00 8-byte
00 2 50MHz 01 16-byte
01 4 80MHz 10 32-byte
10 6 100MHz 11 64-byte
11 8 100MHz
CS#
Mode 3 0 1 2 3 Mode 3
CLK Mode 0 Mode 0
Instruction Read
C0h Parameters
DQ0 P4 P0
DQ1 P5 P1
DQ2 P6 P2
DQ3 P7 P3
Figure 56 Set Read Parameters Instruction (QPI Mode only)
Datasheet
11.38. Burst Read with Wrap (0Ch)
The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read
operation with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)”
instruction in QPI mode, except the addressing of the read operation will “Wrap Around” to the
beginning boundary of the “Wrap Length” once the ending boundary is reached.
The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read
ParametersC0h)” instruction.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
CLK Mode 0
A23-16 A15-8 A7-0 Dummy Input to Output
0Ch
DQ0 20 16 12 8 4 0 4 0 4 0 4
DQ1 21 17 13 9 5 1 5 1 5 1 5
DQ2 22 18 14 10 6 2 6 2 6 2 6
DQ3 23 19 15 11 7 3 7 3 7 3 7
Byte1 Byte2 Byte3
“Set Read Parameters” instruction (C0h) can

Figure 57 Burst Read with Wrap Instruction (QPI Mode only)
11.39. Enable QPI (38h)

TheFM25Q04BsupportbothStandard/Dual/QuadSerialPeripheralInterface(SPI)andQuad
Peripheral Interface (QPI). However, SPI mode and QPI mode can not be used at the same time.
“Enable QPI (38h)” instruction is the only way to switch the device from SPI mode to QPI mode.
Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. See Table
9 QPI Instructions Set (15)for all supported SPI commands. In order to switch the device to QPI
mode, the Quad Enable (QE) bit in Status Register 2 must be set to 1 first, and an “Enable QPI
(38h)” instruction must be issued. If the Quad Enable (QE) bit is 0, the “Enable QPI (38h)”
instruction will be ignored and the device will remain in SPI mode.
See Table 9 QPI Instructions SetInstruction Set for all the commands supported in QPI mode.
When the device is switched from SPI mode to QPI mode, the existing Write Enable and the
Wrap Length setting will remain unchanged.
Datasheet
CS#
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (38h)
DI
(DQ0)
D0 High Impedance
(DQ1)
Figure 58 Enable QPI Instruction (SPI Mode only)
11.40. Disable QPI (FFh)

In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, a “Disable QPI
(FFh)” instruction must be issued.
When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL)
andthe Wrap Length setting will remain unchanged.
CS#
Mode 3 0 1 Mode 3
CLK Mode 0 Mode 0
Instruction
FFh
DQ0
DQ1
DQ2
DQ3
Figure 59 Disable QPI Instruction (QPI Mode only)
Datasheet
11.41. Enable Reset (66h) and Reset (99h)
Because of the small package and the limitation on the number of pins, the FM25Q04B provide a
software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is
accepted, any on-going internal operations will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register
bits, Write Enable Latch (WEL) status, Read parameter setting P7-P0, Continuous Read Mode bit
setting M7-M0 and Wrap Bit setting W6-W4.
“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI
mode. To avoid accidental reset, both instructions must be issued in sequence. Any other
commands other than “Reset (99h)” after the “Enable Reset (66h)” command will disable the
“Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to
reset the device. Once the Reset command is accepted by the device, the device will take
approximately tRST=30μs to reset. During this period, no command will be accepted.
Data corruptionmay happen if there is an on-going internal Erase or Program operation when
Reset command sequence isaccepted by the device. It is recommended to check the WIP bit in
Status Register before issuing theReset command sequence.
CS#
Mode 3 0 1 2 3 4 5 6 7 Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0 Mode 0
Instruction (66h) Instruction (99h)

DI
(DQ0)
D0 High Impedance
(DQ1)
Figure 60 Enable Reset and Reset Instruction Sequence (SPI Mode)
CS#
Mode 3 0 1 Mode 3 0 1 Mode 3
CLK
Mode 0 Mode 0 Mode 0
Instruction Instruction
66h 99h
DQ0
DQ1
DQ2
DQ3
Figure 61 Enable Reset and Reset Instruction Sequence (QPI Mode)
Datasheet
12. Electrical Characteristics
12.1. Absolute Maximum Ratings
Operating Temperature -40°C to +85°C
Storage Temperature -65°C to +150°C
Voltage on I/O Pinwith Respect to Ground -0.5V to VCC+0.4V
VCC -0.5V to 4.0V
*NOTICE: Stresses beyond those listed under“Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
12.2. Pin Capacitance

PARAMETER SYMBOL CONDITIONS Max Units
Input Capacitance CIN(1) VIN = 0V, f = 5 MHz 6 pF
Output Capacitance COUT(1) VOUT = 0V, f = 5 MHz 8 pF
Note: 1. this parameter is characterized and not 100% tested.
12.3. Power-up Timing

Applicable over recommended operating range from: TA= -40°C to 85°C, VCC = 2.3V to 3.6V,(unless
otherwise noted).
SPEC
SYMBOL PARAMETER UNIT
MIN MAX
tVSL VCC (min) to CS# Low 10 µs
tPUW Time Delay Before Write Instruction 1 10 ms
VWI Write Inhibit Threshold Voltage 1 2.0 V
VCC
VCC (max)
CS# Must Track VCC
VCC (min)
tVSL Device is Fully

Reset
State
Accessible
Vwl
tPUW
Figure 62 Power-up Timing& Power Up/Down and Voltage Drop
Datasheet
12.4. DC Electrical Characteristics
Table 10DC Characteristics
otherwise noted).
SPEC
SYMBOL PARAMETER CONDITIONS UNIT
MIN TYP MAX
Vcc Supply Voltage 2.3 3.6 V
ILI Input Leakage Current ±2 µA
ILO Output Leakage Current ±2 µA
CS# = VCC,
ICC1 Standby Current 3 10 µA
VIN = Vss or VCC
Deep Power-down CS# = VCC,
ICC2 1 5 µA
Current VIN = Vss or VCC
CLK=0.1VCC/0.9VCC at
15 mA
33MHz, DQ open
ICC3(1) Read Current
CLK=0.1VCC/0.9VCC, at
25 mA
100MHz, DQ open
Operating Current
ICC4 CS#=VCC 10 20 mA
(WRSR)
ICC5 Operating Current (PP) CS#=VCC 10 20 mA
ICC6 Operating Current (SE) CS#=VCC 10 20 mA
ICC7 Operating Current (BE) CS#=VCC 10 20 mA
VIL Input Low Voltage -0.5 0.2VCC V
VIH Input High Voltage 0.8VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6mA 0.4 V
VOH Output High Voltage IOH = -100 µA VCC-0.2 V
Notes:
1. Checker Board Pattern.
12.5. AC Measurement Conditions

Table 11AC Measurement Conditions
SPEC
MIN MAX
CL Load capacitance(including jig capacitance) 20 pF
TR, TF Input Rise and Fall Times 5 ns
VIN Input Pulse Voltages 0.2 VCC to 0.8 VCC V
IN Input Timing Reference Voltages 0.3 VCC to 0.7 VCC V
OUT Output Timing Reference Voltages 0.5VCC V
Input Levels Input Timing Reference Level Output Timing Reference Level
0.8 Vcc
0.7 Vcc AC
Measurement 0.5 Vcc
0.3 Vcc Level
0.2 Vcc
Figure 63 AC Measurement I/O Waveform
Datasheet
12.6. AC Electrical Characteristics
Table 12AC Characteristics
otherwise noted).
SPEC
MIN TYP MAX
Serial Clock Frequency for:
FR FAST_READ, PP, SE, BE, DP, RES, WREN, 100 MHz
WRDI, WRSR
fR Serial Clock Frequency for READ, RDSR, RDID 50 MHz
tCH1(1) Serial Clock High Time 4.5 ns
tCL1(1) Serial Clock Low Time 4.5 ns
tCLCH(2) Serial Clock Rise Time (Slew Rate) 0.1 V/ns
tCHCL(2) Serial Clock Fall Time (Slew Rate) 0.1 V/ns
tSLCH(2) CS# Active Setup Time 5 ns
tCHSH(2) CS# Active Hold Time 5 ns
tSHCH(2) CS# Not Active Setup Time 5 ns
tCHSL(2) CS# Not Active Hold Time 5 ns
tSHSL(2) CS# High Time 7 ns
tSHQZ(2) Output Disable Time 7 ns
tCLQX(2) Output Hold Time 0 ns
tDVCH(2) Data In Setup Time 1.5 ns
tCHDX(2) Data In Hold Time 4 ns
tHLCH(2) HOLD# Low Setup Time ( relative to CLK ) 5 ns
tHHCH(2) HOLD# High Setup Time ( relative to CLK ) 5 ns
tCHHH(2) HOLD# Low Hold Time ( relative to CLK ) 5 ns
tCHHL(2) HOLD# High Hold Time ( relative to CLK ) 5 ns
tHLQZ(2) HOLD# Low to High-Z Output 12 ns
tHHQX(2) HOLD# High to Low-Z Output 7 ns
tCLQV(2) Output Valid from CLK 8 ns
tWHSL(2) Write Protect Setup Time before CS# Low 20 ns
tSHWL(2) Write Protect Hold Time after CS# High 100 ns
tDP(2) CS# High to Deep Power-down Mode 3 µs
CS# High to Standby Mode without Electronic
tRES1(2) 3 µs
Signature Read
CS# High to Standby Mode with Electronic
tRES2(2) 1.8 µs
Signature Read
tRST(2) CS# High to next Instruction after Reset 1 ms
tW Write Status Register Cycle Time 10 15 ms
tBP Byte Program Time 30 50 µs
tPP Page Program Time 0.6 3 ms
tSE Sector Erase Time 80 300 ms
tBE Block Erase Time (32KB) 250 1500 ms
tBE Block Erase Time (64KB) 400 2000 ms
tCE Chip Erase Time 3 15 s
Datasheet
Notes:
1. tCH+tCL>= 1 / FR or 1/fR ;
2. This parameter is characterized and is not 100% tested.
CS#
tCH
CLK
tCLQV tCLQV tCL tSHQZ
tCLQX tCLQX
I/O
OUTPUT LSB OUT
tQLQH
tQHQL
Figure 64 Serial Output Timing
tSHSL
CS#
tCHSL tCHSH tSHCH
tSLCH
CLK
tDVCH
tCHDX tCLCH tCHCL
I/O
INPUT MSB IN LSB IN
I/O (High Impedance)

OUTPUT
Figure 65 Serial Input Timing
Datasheet
CS#
tHLCH
tCHHL tHHCH
CLK
tCHHH
tHLQZ
tHHQX
I/O
OUTPUT
I/O
INPUT
HOLD#
Figure 66 Hold Timing
CS#
tWHSL tSHWL
WP#
CLK
I/O
INPUT
Write Status Register is allowed Write Status Register is not allowed
Figure 67 WP# Timing
Datasheet
13. Ordering Information
FM 25Q 04 B -XXX -C -H
Company Prefix
FM = Fudan Microelectronics Group Co.,ltd
Product Family
25Q = 2.3~3.6V Serial Flash with 4KB Uniform-Sector,
Dual/Quad SPI & QPI
Product Density
04= 4M-bit
Product Version
Package Type (1)

SO = 8-pin SOP（150mil）
US = 8-pin USON（0.55mm）
Product Carrier
U = Tube
T = Tape and Reel
HSF ID Code
G = RoHS Compliant, Halogen-free, Antimony-free
Note:
1. For SO package, MSL1 package are available, for detail please contact local sales office.
Datasheet
14. Part Marking Scheme
14.1. SOP8 (150mil)
FM25Q04B
YYWWALHM
Moisture Sensitivity Level
1 = MSL1
Blank=MSL3
HSF ID Code
Lot Number（just with 0~9、A~Z）
Assembly’s Code
Work week during which the product was molded (eg..week 12)
The last two digits of the year In which the product was sealed / molded.
14.2. USON8(0.55mm)
5 Q 2
Product Density Code
Y M
The month (hexadecimal digit) in which the product was molded.
A L H The last one digit of the year In which the product was sealed / molded.
HSF ID Code
M
Moisture Sensitivity Level
1 = MSL1
Blank=MSL3
Lot Number（just with 0~9、A~Z）
Assembly's Code
Datasheet
15. Packaging Information
SOP 8 (150mil)
Symbol MIN MAX

A 1.350 1.750
A1 0.050 0.250
b 0.330 0.510
c 0.150 0.260
D 4.700 5.150
E1 3.700 4.100
E 5.800 6.200
e 1.270(BSC)
L 0.400 1.270
θ 0° 8°
NOTE:
1. Dimensions are in Millimeters.
Datasheet
USON8 (0.55mm)
Symbol MIN MAX

A 0.500 0.600
A1 0.000 0.050
D 2.900 3.100
E 1.900 2.100
D1 0.100 0.300
E1 1.500 1.700
b 0.180 0.300
e 0.500(BSC)
L 0.300 0.400
NOTE:
1. Dimensions are in Millimeters.
Datasheet
16. Revision History
VERSION DATE PAGE Revise Description
preliminary Aug.2019 69 Initial Document Release.
1.0 Nov.2019 69 Updated Table 6
1.1 Jan.2021 69 Corrected the typo.
Datasheet
Sales and Service
Shanghai Fudan Microelectronics Group Co., Ltd.
Address: Bldg No. 4, 127 Guotai Rd, Shanghai City China.
Postcode: 200433
Tel: (86-021) 6565 5050 Fax: (86-021) 6565 9115
Shanghai Fudan Microelectronics (HK) Co., Ltd.

Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road,
Tsimshatsui East, Kowloon, Hong Kong
Tel: (852) 2116 3288 2116 3338
Fax: (852) 2116 0882
Beijing Office
Address: Room 423, Bldg B, Gehua Building, 1 QingLong Hutong,
Dongzhimen Alley north Street, Dongcheng District, Beijing City,
China.
Postcode: 100007
Tel: (86-010) 8418 6608
Fax: (86-010) 8418 6211
Shenzhen Office
Address: Room.2306-2308, Building A7, Chuangzhi Cloud City,
Liuxian Avenue, Xili Street, Nanshan District, Shenzhen, China.
Postcode: 518000
Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611
Fax: (86-0755) 8335 9011
Shanghai Fudan Microelectronics (HK) Ltd Taiwan

Representative Office
Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist.,
Taipei City 114, Taiwan
Tel : (886-2) 7721 1889
Fax: (886-2) 7722 3888
Shanghai Fudan Microelectronics (HK) Ltd Singapore

Representative Office
Address : 47 Kallang Pudding Road, #08-06,The Crescent @
Kallang ,Singapore 349318
Tel : (65) 6443 0860
Fax: (65) 6443 1215
Fudan Microelectronics（USA）Inc.
Address : 97 E Brokaw Road, Suite 320,San Jose,CA 95112
Tel : (+1)408-335-6936
Web Site: http://www.fmsh.com/
Datasheet

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FM25Q04B

4M-BIT SERIAL FLASH MEMORY

Figure 1 FM25Q04B Serial Flash Memory Block Diagram

Table 1Memory Organization

Reset (66h + 99h) Reset (66h + 99h)

Standard SPI Enable QPI (38h)

Figure 2 FM25Q04B Serial Flash Memory Operation Diagram

8.1. Standard SPI

Figure 3 The difference between Mode 0 and Mode 3

8.2. Dual SPI

Active Hold Active Hold Active

Figure 4 HoldCondition Waveform

Write Protect Features

Factory default for all Status Register bits are 0.

SRP0 SEC TB BP2 BP1 BP0 WEL WIP

STATUS REGISTER PROTECT 0

WRITE ENABLE LATCH

Figure 5Status Register1

S15 S14 S13 S12 S11 S10 S9 S8

RFU CMP ERR DRV DRV LB QE SRP1

SECURITY REGISTER LOCK BIT

STATUS REGISTER PROTECT 1

10.2. Write Enable Latch (WEL)

10.3. Block Protect Bits (BP2, BP1, BP0)

10.4. Top/Bottom Block Protect (TB)

10.5. Sector/Block Protect (SEC)

10.6. Complement Protect (CMP)

Table 2Status Register Protect bits

10.8. Output driver strength (DRV1, DRV0)

10.9. Error Bit (ERR)

10.10. Security SectorLock Bit (LB)

10.12. Status Register Memory Protection

STATUS REGISTER FM25Q04B (4M-BIT) MEMORY PROTECTION

0 1 0 0 0 1 7 07F000h – 07FFFFh 4KB U - 1/128

0 1 1 0 0 1 0 000000h – 000FFFh 4KB L - 1/128

11.1. Manufacturer and Device Identification

Manufacturer/Device ID(4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0)

11.4. Quad SPI Instructions Set

11.5. QPI Instructions Set

11.7. Write Enable for Volatile Status Register (50h)

11.9. Read Status Register-1(RDSR1) (05h) , Status Register-2

Figure 10 Read Status Register Instruction (SPI Mode)

SR1/2 out SR1/2 out

Figure 11 Read Status Register Instruction (QPI Mode)

11.10. Write Status Register-1(WRSR)(01h), Status Register-2 (31h)

CLK Mode 0 Mode 0

Instruction (01h/31h) Status Register 1/2 in

Figure 12 Write Status Register Instruction (SPI Mode)

Figure 13 Write Status Register Instruction (QPI Mode)

11.11. Read Data (03h)

Instruction (03h) 24-Bit Addess

Figure 14 Read Data Instruction (SPI Mode only)

11.12. Fast Read (0Bh)

Data Out 1 Data Out 2

Figure 15 Fast Read Instruction (SPI Mode)

Fast Read (0Bh) in QPI Mode

* "Set Read Parameters" instruction (C0h) can

Figure 16 Fast Read Instruction (QPI Mode)

11.13. Fast Read Dual Output (3Bh)

Instruction (3Bh) 24-Bit Address