a Internally Trimmed

Precision IC Multiplier
AD632
FEATURES PIN CONFIGURATIONS
Pretrimmed to ±0.5% Max 4-Quadrant Error H-Package TO-100
All Inputs (X, Y and Z) Differential, High Impedance for
[(X1–X2)(Y1–Y2)/10] + Z2 Transfer Function
Scale-Factor Adjustable to Provide up to X10 Gain
Low Noise Design: 90 mV rms, 10 Hz–10 kHz
Low Cost, Monolithic Construction
Excellent Long-Term Stability
APPLICATIONS
High Quality Analog Signal Processing
Differential Ratio and Percentage Computations
Algebraic and Trigonometric Function Synthesis
Accurate Voltage Controlled Oscillators and Filters
D-Package TO-116

PRODUCT DESCRIPTION
The AD632 is an internally-trimmed monolithic four-quadrant
multiplier/divider. The AD632B has a maximum multiplying
error of ± 0.5% without external trims.
Excellent supply rejection, low temperature coefficients and
long term stability of the on-chip thin film resistors and buried
zener reference preserve accuracy even under adverse condi- PRODUCT HIGHLIGHTS
tions. The simplicity and flexibility of use provide an attractive Guaranteed Performance Over Temperature
alternative approach to the solution of complex control func- The AD632A and AD632B are specified for maximum multi-
tions. plying errors of ± 1.0% and ± 0.5% of full scale, respectively at
The AD632 is pin-for-pin compatible with the industry standard +25°C and are rated for operation from –25°C to +85°C.
AD532 with improved specifications and a fully differential high Maximum multiplying errors of ± 2.0% (AD632S) and ± 1.0%
impedance Z-input. The AD632 is capable of providing gains of (AD632T) are guaranteed over the extended temperature range
up to X10, frequently eliminating the need for separate instru- of –55°C to +125°C.
mentation amplifiers to precondition the inputs. The AD632 High Reliability
can be effectively employed as a variable gain differential input The AD632S and AD632T series are also available with
amplifier with high common-mode rejection. The effectiveness MIL-STD-883 Level B screening and all devices are available in
of the variable gain capability is enhanced by the inherent low either the hermetically-sealed TO-100 metal can or TO-116
noise of the AD632: 90 µV rms. ceramic DIP package.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1997
AD632–SPECIFICATIONS (@ +258C, VS = ±15 V, R ≥ 2 kV unless otherwise noted)

AD632A AD632B AD632S AD632T

Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

MULTIPLIER PERFORMANCE
( X1 − X 2 )(Y1 − Y 2 ) ( X1 − X 2 )(Y1 − Y 2 ) ( X1 − X 2 )(Y1 − Y 2 ) ( X1 − X 2 )(Y1 − Y 2 )
Transfer Function + Z2 + Z2 + Z2 + Z2
10V 10V 10V 10V
Total Error1 (–10 V ≤ X, Y ≤ +10 V) 61.0 60.5 61.0 60.5 %
TA = Min to Max 61.5 61.0 62.0 61.0 %
Total Error vs. Temperature ± 0.022 ± 0.015 60.02 60.01 %/°C
Scale Factor Error
(SF = 10.000 V Nominal)2 ± 0.25 ± 0.1 ± 0.25 ± 0.1 %
Temperature-Coefficient of
Scaling-Voltage ± 0.02 60.01 ± 0.2 60.005 %/°C
Supply Rejection (± 15 V ± 1 V) ± 0.01 ± 0.01 ± 0.01 ± 0.01 %
Nonlinearity, X (X = 20 V p-p, Y = 10 V) ± 0.4 ± 0.2 ± 0.3 ± 0.4 ± 0.2 ± 0.3 %
Nonlinearity, Y (Y = 20 V p-p, X = 10 V) ± 0.2 ± 0.1 ± 0.1 ± 0.2 ± 0.1 ± 0.1 %
Feedthrough3, X (Y Nulled,
X = 20 V p-p 50 Hz) ± 0.3 ± 0.15 ± 0.3 ± 0.3 ± 0.15 ± 0.3 %
Feedthrough3, Y (X Nulled,
Y = 20 V p-p 50 Hz) ± 0.01 ± 0.01 ± 0.1 ± 0.01 ± 0.01 ± 0.1 %
Output Offset Voltage ±5 630 ±2 ± 15 ±5 630 ±2 ± 15 mV
Output Offset Voltage Drift 200 100 500 300 µV/°C
DYNAMICS
Small Signal BW, (VOUT = 0.1 rms) 1 1 1 1 MHz
1% Amplitude Error (CLOAD = 1000 pF) 50 50 50 50 kHz
Slew Rate (VOUT 20 p-p) 20 20 20 20 V/µs
Settling Time (to 1%, ∆VOUT = 20 V) 2 2 2 2 µs
NOISE
Noise Spectral-Density SF = 10 V 0.8 0.8 0.8 0.8 µV/√Hz
SF = 3 V4 0.4 0.4 0.4 0.4 µV/√Hz
Wideband Noise A = 10 Hz to 5 MHz 1.0 1 .0 1.0 1.0 mV rms
P = 10 Hz to 10 kHz 90 90 90 90 µV/rms
OUTPUT
Output Voltage Swing 611 611 611 611 V
Output Impedance (f ≤ 1 kHz) 0.1 0.1 0.1 0.1 Ω
Output Short Circuit Current
(RL = 0, TA = Min to Max) 30 30 30 30 mA
Amplifier Open Loop Gain (f = 50 Hz) 70 70 70 70 dB
INPUT AMPLIFIERS (X, Y and Z)5
Signal Voltage Range (Diff. or CM ± 10 ± 10 ± 10 ± 10 V
Operating Diff.) ± 12 ± 12 ± 12 ± 12 V
Offset Voltage X, Y ±5 620 ±2 610 ±5 620 ±2 610 mV
Offset Voltage Drift X, Y 100 50 100 150 µV/°C
Offset Voltage Z ±5 630 ±2 615 ±5 630 ±2 615 mV
Offset Voltage Drift Z 200 100 500 300 µV/°C
CMRR 60 80 70 90 60 80 70 90 dB
Bias Current 0.8 2.0 0.8 2.0 0.8 2.0 0.8 2.0 µA
Offset Current 0.1 0. I 0.1 0.1 µA
Differential Resistance 10 10 10 10 MΩ
DIVIDER PERFORMANCE
( Z 2 − Z1 ) ( Z 2 − Z1 ) ( Z 2 − Z1 ) ( Z 2 − Z1 )
Transfer Function (X1 > X2) 10V + Y1 10V + Y1 10V + Y1 10V + Y1
( X1 − X 2 ) ( X1 − X 2 ) ( X1 − X 2 ) ( X1 − X 2 )
Total Error1
(X = 10 V, –10 V ≤ Z ≤ +10 V) ± 0.75 ± 0.35 ± 0.75 ± 0.35 %
(X = 1 V, –1 V ≤ Z ≤ +1 V) ± 2.0 ± 1.0 ± 2.0 ± 1.0 %
(0.1 V ≤ X ≤ 10 V, –10 V ≤ Z ≤ 10 V) ± 2.5 ± 1.0 ± 2.5 ± 1.0 %
SQUARER PERFORMANCE
( X1 − X 2 )2 ( X1 − X 2 )2 ( X1 − X 2 )2 ( X1 − X 2 )2
Transfer Function + Z2 + Z2 + Z2 + Z2
10V 10V 10V 10V
Total Error (–10 V ≤ X ≤ 10 V) ± 0.6 ± 0.3 ± 0.6 ± 0.3 %
SQUARE-ROOTER PERFORMANCE
Transfer Function, (Z1 ≤ Z2) 10V ( Z 2 − Z1 ) + X 2 10V ( Z 2 − Z1 ) + X 2 10V ( Z 2 − Z1 ) + X 2 10V ( Z 2 − Z1 ) + X 2
Total Error1 (1 V ≤ Z ≤ 10 V) ± 1.0 ± 0.5 ± 1.0 ± 0.5 %

–2– REV. A
 AD632
AD632A AD632B AD632S AD632T
Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

POWER SUPPLY SPECIFICATIONS

Supply Voltage
Rated Performance ± 15 ± 15 ± 15 ± 15 V
Operating ±8 618 ±8 618 ±8 622 ±8 622 V
Supply Current
Quiescent 4 6 4 6 4 6 4 6 mA
NOTES
1
Figures given are percent of full-scale, ± l0 V (i.e., 0.01% = 1 mV).
2
May be reduced to 3 V using external resistor between –V S and SF.
3
Irreducible component due to nonlinearity: excludes effect of offsets.
4
Using external resistor adjusted to give SF = 3 V.
5
See functional block diagram for definition of sections.
All min and max specifications are guaranteed.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*
AD632AD –25°C to +85°C Side Brazed Ceramic DIP D-14
AD632BD –25°C to +85°C Side Brazed Ceramic DIP D-14
AD632AH –25°C to +85°C Header H-10A
AD632BH –25°C to +85°C Header H-10A
AD632SD –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632SD/833B –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632TD –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632TD/883B –55°C to +125°C Side Brazed Ceramic DIP D-14
AD632SH –55°C to +125°C Header H-10A
AD632SH/883B –55°C to +125°C Header H-10A
AD632TH –55°C to +125°C Header H-10A
AD632TH/883B –55°C to +125°C Header H-10A

*For outline information see Package Information section.

CHIP DIMENSIONS AND PAD LAYOUT Thermal Characteristics

Dimensions shown in inches and (mm).
(Contact factory for latest dimensions.) Thermal Resistance θJC = 25°C/W for H-10A
θJA = 150°C/W for H-10A
θJC = 25°C/W for D-14
θJA = 95°C/W for D-14

For further information, consult factory.

REV. A –3–
AD632
Typical Performance Curves
(typical @ +258C with 6VS = 15 V)

Figure 4. AD632 Functional Block Diagram

OPERATION AS A MULTIPLIER
Figure 5 shows the basic connection for multiplication. Note
that the circuit will meet all specifications without trimming.

Figure 1. AC Feedthrough vs. Frequency

Figure 5. Basic Multiplier Connection

In some cases the user may wish to reduce ac feedthrough to a
minimum (as in a suppressed carrier modulator) by applying an
external trim voltage (± 30 mV range required) to the X or Y
input. Curve 1 shows the typical ac feedthrough with this ad-
justment mode. Note that the feedthrough of the Y input is a
Figure 2. Frequency Response as a Multiplier factor of 10 lower than that of the X input and should be used
in applications where null suppression is critical.
The Z2 terminal of the AD632 may be used to sum an addi-
tional signal into the output. In this mode the output amplifier
behaves as a voltage follower with a 1 MHz small signal band-
width and a 20 V/µs slew rate. This terminal should always be
referenced to the ground point of the driven system, particularly
if this is remote. Likewise the differential inputs should be refer-
enced to their respective signal common potentials to realize the
full accuracy of the AD632.
A much lower scaling voltage can be achieved without any re-
duction of input signal range using a feedback attenuator as
shown in Figure 6. In this example, the scale is such that
VOUT = XY, so that the circuit can exhibit a maximum gain of
10. This connection results in a reduction of bandwidth to
about 80 kHz without the peaking capacitor CF. In addition, the
output offset voltage is increased by a factor of 10 making exter-
nal adjustments necessary in some applications.
Figure 3. Frequency Response vs. Divider Denominator
Input Voltage

–4– REV. A
 AD632
Feedback attenuation also retains the capability for adding a Without additional trimming, the accuracy of the AD632B is
signal to the output. Signals may be applied to the Z terminal, sufficient to maintain a 1% error over a 10 V to 1 V denomina-
where they are amplified by –10, or to the common ground tor range (The AD535 is functionally equivalent to the AD632
connection where they are amplified by –1. Input signals may and has guaranteed performance in the divider and square-rooter
also be applied to the lower end of the 2.7 kΩ resistor, giving a configurations and is recommended for such applications).
gain of +9. This range may be extended to 100:1 by simply reducing the X
offset with an externally generated trim voltage (range required
is ± 3.5 mV max) applied to the unused X input. To trim, apply
a ramp of +100 mV to +V at 100 Hz to both X1 and Z1 (if X2 is
used for offset adjustment, otherwise reverse the signal polarity)
and adjust the trim voltage to minimize the variation in the
output.*
Since the output will be near +10 V, it should be ac-coupled for
this adjustment. The increase in noise level and reduction in
bandwidth preclude operation much beyond a ratio of 100 to 1.

*See the AD535 data sheet for more details.

Figure 6. Connections for Scale-Factor of Unity

OPERATION AS A DIVIDER
Figure 7 shows the connection required for division. Unlike
earlier products, the AD632 provides differential operation on
both numerator and denominator, allowing the ratio of two
floating variables to be generated. Further flexibility results from
access to a high impedance summing input to Y1. As with all
dividers based on the use of a multiplier in a feedback loop, the
bandwidth is proportional to the denominator magnitude, as
shown in Figure 3.

Figure 7. Basic Divider Connection

REV. A –5–
AD632
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

H-Package TO-100

C526a–1–6/97
D-Package TO-116

PRINTED IN U.S.A.

–6– REV. A