Cu184 Main

QUESTION ONE
a) Draw a diagram which shows how a pietzo electric crystal is connected to the MC6809 Microprocessor
and state the relationship between the frequency of the crystal and the free running clocks E and Q. Draw
a diagram which clearly shows the phase relationship between E and Q and on that diagram clearly mark
bus cycles. When during the marked bus cycles do the actual data transfers take place. [10]
b) Draw a diagram of a simple circuit which can be used to generate a power on reset as well as a push
button reset to RESET the MC6809 microprocessor. What appears on the address bus of a powered
MC6809 microprocessor while the reset line is pulled down active low? [5]
c) Describe the terms: access time, data retention time and endurance when used to describe EPROMs and
EEPROMs. Give typical values of these three parameters. [6]
d) Compare and contrast memory mapped I/O and dedicated or separate I/O and state which microprocessor
manufacturer uses which scheme between Motorola and Intel. [4]
QUESTION TWO
a) Draw to scale the memory map of an MC6809 microprocessor based Microcomputer where the first half
is read write memory and the last quarter is read only memory. The remaining one quarter is to be shared
equally by four I/O devices in the following order. First two are Motorola MC6821 PIAs and the last two
Rockwell R6551 ACIAs. Construct the memory address decoding table and write down the size of each
range and the range of addresses for each memory component and I/O device. [12]
b) Write down the selected device for each of the following addresses:
i) $D957 ii) $10FF iii) $897A iv) $B398 [3]
c) Implement the memory address decoding logic using discrete logic gates: NOT, AND, OR, NAND and
NOR. [10]
d) Draw the logic circuit diagram of an FPGA (field programmable gate array) which can implement the
address decoding much more compactly. [5]
QUESTION THREE
a) Draw the diagram of a current loop RS232 interface and explain its operation. What are the advantages
and limitations of the current loop interface when compared with the traditional RS232 interface which
uses line drivers and line receivers? [6]
b) With the use of appropriate diagrams, describe software handshaking and hardware handshaking when a
slow receiver receives data at a fast pace from a fast data sender. [6]
c) Describe the three errors associated with the RS232 interface: Parity Error, Framing Error and Character
Overrun. What can be done to minimise the occurrence of all the errors. [6]
d) Table Q.3 provides the information required to configure the Rockwell R6551 Asynchronous
Communications Interface Adapter (ACIA) chip. A 3.6864 MHz crystal is connected to the ACIA.
Determine the control byte and the command byte which must be written during initialisation to the
control register and command register respectively for the following configuration:
19 200 bits per second, Odd Parity, 1 Stop bit, 8 bits per character, receiver interrupts and all the
outgoing handshake signals active and normal ACIA operation. [7]
QUESTION FOUR
a) Describe the operation of the stack on the MC6809 Microprocessor. How is the stack initialised? Explain
clearly why interrupts are disabled by default after a hardware reset and why it is not allowed to call
subroutines before the system stack pointer register is initialised. [6]
b) Write down the sequence of five steps which is continuously repeated while a von Neuman processor is
fetching and executing instructions. At which point are pending enabled interrupts honoured? [6]
1
c) Explain clearly, with the use of an appropriate diagram, why an edge sensitive interrupt like NMI (non
maskable interrupt) on the MC6809 cannot be connected to several I/O devices which then share the one
interrupt request input. [4]
d) Explain clearly, in great detail, what happens from the time a falling edge occurs on the interrupt input
line NMI until control is transferred to its interrupt service routine. [6]
e) What is an open drain (O/D) output? Explain why clearly why input and output device interrupt request
outputs are open drain. [3]
QUESTION FIVE
Listing Q.5 is an MC68HC11 assembly language program. Assemble the program by hand into machine
code using the normal listing file format used by most assemblers. Convert the machine code into Intel
hex format records and Motorola S format records. In each case write down the end of file record. [25]
BAUD EQU $102B

SCDR EQU $102F
SCSR EQU $102E
TDRE EQU $80
RDRF EQU $20
UPPER_MASK EQU $DF
ORG $F800
START LDAA #30
STAA BAUD
ECHO_LOOP LDAA SCSR
BITA #RDRF
BEQ ECHO_LOOP
CMPA #$61
BLT DO_ECHO
CMPA #$7A
BGT DO_ECHO
ANDA #UPPER_MASK
DO_ECHO PSHA
TX_LOOP LDAA SCSR
BITA #TDRE
BEQ TX_LOOP
PULA
STAA SCDR
BRA ECHO_LOOP
Listing Q.5
QUESTION SIX
a) An MC68HC11 microcontroller is driven by a 1.8432 MHz crystal. The configuration bits RTR1:RTR2
are set to “11” to give a real time interrupt once every 2 16 enable cycles. Determine the exact interval
between real time interrupts and calculate the real time rate. Hence determine the values of the two
variables, time_out and adjust required to maintain a real time clock in the machine code
developed in lectures.
[8]
b) Describe input capture and output comparison on PORTA pins on the Motorola MC68HC11
microcontroller. [5]
2
c) Show how output comparison can be used to produce a variable speed control system for a DC motor
with the use of pulse width modulation (PWM) when variable mark space ratios are to be arranged for.
Draw the diagram of the circuit that interfaces the control signal to the DC motor whose speed is being
controlled. [12]
TABLE Q.3
CONTROL REGISTER BIT ALLOCATIONS COMMAND REGISTER BIT ALLOCATIONS
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
WL BAUD RATE SELECT PMC TIC

SBN RCS PME REM IRD DTR
WL1 WL0 BRS3 BRS2 BRS1 BRS0 PMC1 PMC0 TIC1 TIC2
SBN PARITY MODE CONTROL

0 1 STOP BIT Bank of DIP Switches PMC1 PMC0
1 2 STOP BITS 0 0 ODD Parity Transmitted / Received
1 1.5 STOP BITS FOR WL = 5 and NO PARITY 0 1 EVEN Parity Transmitted / Received
1 1 STOP BIT for WL = 8 and PARITY 1 0 MARK Parity Transmitted / Received
1 1 SPACE Parity Transmitted / Received
WL (Word Length)
WL1 WLO
0 0 8 Bits per character PARITY MODE ENABLE (PME)
0 1 7 Bits per character 0 Disabled
1 0 6 Bits per character 1 Enabled
1 1 5 Bits per character RECEIVER ECHO MODE
RCS (Receiver Clock Source) 0 Receiver normal mode
0 External Receiver Clock 1 Receiver ECHO Mode (TIC1:TIC0 = 00)
1 Internally Generated Baud Rate Clock
SELECTED BAUD RATE (For 1.8432 MHz)
BR3 BR2 BR1 BR0 Baud Rate
0 0 0 0 External Clock / 16 TRANSMITTER INTERRUPT CONTROL
0 0 0 1 50 bps TIC1 TIC0
0 0 1 0 75 bps 0 0 RTS=HIGH, Transmitter Disabled
0 0 1 1 102.92 bps 0 1 RTS=LOW, Transmitter INT enabled
0 1 0 0 134.58 bps 1 0 RTS=LOW, Transmitter INT disabled
0 1 0 1 150 bps 1 1 RTS=LOW, Transmitter INT disabled
0 1 1 0 300 bps Transmit break character on TxD
0 1 1 1 600 bps
1 0 0 0 1 200 bps
1 0 0 1 1 800 bps RECEIVER INTERRUPT REQUEST DISABLED (IRD)
1 0 1 0 2 400 bps 0 IRQ enabled for the receiver
1 0 1 1 3 600 bps 1 IRQ disabled for the receiver
1 1 0 0 4 800 bps DATA TERMINAL READY (DTR)
1 1 0 1 7 200 bps 0 Data Terminal NOT Ready (DTR = HIGH)
1 1 1 0 9 600 bps 1 Data Terminal Ready (DTR = LOW)
1 1 1 1 19 200 bps

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QUESTION ONE

BAUD EQU $102B

WL BAUD RATE SELECT PMC TIC

SBN PARITY MODE CONTROL

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