DS28H10RevB-max32555 Datasheet

MAXIM INTEGRATED CONFIDENTIAL/DISTRIBUTE ONLY UNDER NDA
EVALUATION KIT AVAILABLE
MAX32555 DeepCover Secure Cortex-M3

Flash Microcontroller
General Description Benefits and Features

DeepCover® embedded security solutions cloak sensitive ●● ARM® Cortex® M3 Processor Core Allows for Easy
data under multiple layers of advanced physical security Integration into Applications
to provide the most secure key storage possible. • 60MHz Core Operating Frequency Through PLL
The DeepCover Secure microcontroller (MAX32555) pro- • 512KB Dual-Bank Flash Memory with Cache
• 96KB System SRAM
vides an interoperable, secure, and cost-effective solution
• 1KB AES Self-Encrypted NVSRAM
to build new generations of trusted devices such as mobile
8
chip and pin pads. The MAX32555 is based on a Cortex ●● Security Features Facilitate System-Level Protection
• Secure Boot Loader with Public Key Authentication
72
M3 processor with 512KB of embedded flash, 96KB of
system RAM, 1KB of battery-backed AES self-encrypted • AES, DES and SHA Hardware Accelerators
NVSRAM. It includes all the essential functions of mobile • Modulo Arithmetic Hardware Accelerator (MAA)
11
POS terminal including a cryptographic engine, a true ran- Supporting RSA, DSA, and ECDSA
dom number generator, battery-backed RTC, environmen- • 8-Line Secure Keypad Controller
• Hardware True Random-Number Generator
tal and tamper detection circuitry, a magnetic stripe reader,
57
• Die Shield with Dynamic Fault Detection
a smart card controller with embedded transceiver to • 4 External Tamper Sensors with Independent
directly support 1.8V, 3.3V, and 5V cards, and an integrated Random Dynamic Patterns
secure keypad controller. It also includes a vast array of
/6 • 256-Bit Flip-Flop-Based Battery-Backup AES Key
peripherals, SPIs, UARTs, DMA, ADC, and DAC that add Storage
flexibility to control and differentiate the system design. • Temperature and Voltage Tamper Monitor
10
• Real-Time Clock
Applications
●● Integrated Peripherals Reduce External Component Count
●● PCI Mobile Payment Terminals (mPOS)
• Triple-Track Magnetic Stripe Head Interface
H
●● ATM Keyboards
• One ISO 7816 Smart Card Interface with Integrated
●● EMV Card Reader
Transceiver (1.8V, 3V, and 5V)
28
• USB 2.0 Device with Internal Transceiver and

Dedicated PLL
Functional Diagram • 3 SPI Ports, 3 UART Ports, and 1 I2C Controller
DS
• 8 Timers, All with PWM Capability

MAX32555
APB PERIPHERALS
• Up to 70 General-Purpose I/O Pins
ARM
CORTEX M3
NVIC • 6-Channel, 10-Bit ADC and 1-Channel, 8-Bit DAC
E/
SECURITY RTC* • Monochrome LCD Controller

MPU MONITOR*
• 4-Channel DMA Controller
I I D I S
AHB I AHB I
APB BRIDGE
APB
WATCHDOG OSC/PLL (2) ●● Power Management Optimizes Battery Life and
CODE SPACE AHB PERIPHERALS OTP GPIO
Reduces Active Power Consumption
FLASH SRAM NVSRAM
• Single 3.3V Supply Operation*
512kB 96K 1kB* TIMERS (8) KEYPAD
• Integrated Battery-Backup Switch
UART (3) SPI (3) • Clock Gating Function
DMA CRYPTO
ROM
64kB
• Low-Current Battery-Backup Operation
I2C ADC
USB DEVICE TRNG
SMART CARD MONO LCD

MSR DAC Ordering Information appears at end of data sheet.
* BATTERY-BACKED BLOCKS
*5V smart card support requires external 5.0V supply.

DeepCover is a registered trademark of Maxim Integrated Products, Inc.
ARM and Cortex are registered trademarks and ARM is a service mark of ARM Limited.
19-7145; Rev 0; 6/15


Absolute Maximum Ratings

(All voltages with respect to GND.) Operating Temperature Range............................ -40°C to +85°C
VDD, VDDA............................................................-0.5V to +3.6V Storage Temperature Range............................. -65°C to +150°C
SC_VDDA..............................................................-0.5V to +5.5V Continuous Power Dissipation (TA = +85°C).................1231mW
Any Lead......................................................-0.5V to VDD + 0.5V Soldering Temperature.................. See IPC/JEDEC J-STD-020A
Package Thermal Characteristics (Note 1)

CSBGA
Junction-to-Ambient Thermal Resistance (θJA)........32.5°C/W Junction-to-Case Thermal Resistance (θJC)...............8.8°C/W
8
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
72
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
11
(Limits are 100% tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and relevant supply voltage range
are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
57
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
/6
VDD, VDDA 3.0 3.3 3.6 V
Supply Voltage 1.8/3V cards 3.3 V
10
VSC_VDDA
1.8/3/5V cards 5.25 V
Battery Supply Voltage VBAT 2.3 3.6 V
H
Main Battery Supply Voltage VMAIN 0 3.6 V

28
Main Battery Supply Switching VMAIN_

2.2 2.4 2.6 V
Threshold SWITCH
Power-Fail Reset Voltage VRST 2.8 3.0 V
DS
VRST
Power-Fail Warning Voltage VPFW 2.2 2.6 V
+ 0.05
fSYS = 60MHz,
E/
Supply Current (Note 2) IDD1 60 80 mA

TA = +25°C
TA = +25°C 5.1 mA
Idle Mode Current (Note 3) IIDLE
TA = +85°C 5.6 mA
Standby Mode Current TA = +25°C 500 µA
ISTBY
(Note 4) TA = +85°C 700 µA
Battery Back Mode Current TA = +25°C 2.9 µA
IBAT
(Note 5) TA = +85°C 4.4 µA
Main Battery Back Mode
IMAIN TA = +25°C 6.1 µA
Current (Note 6)
Battery Leakage Current
IBAT2 TA = +25°C 100 nA
(Note 7)
EXTERNAL CRYSTAL OSCILLATOR
External Oscillator/Crystal
fHFXIN 12 MHz
Frequency (Note 8)
Crystal Oscillator Startup Time tHFSU 16,384 cycles
INTERNAL OSCILLATOR
Oscillator Frequency fOSC 48 54 62 MHz
www.maximintegrated.com Maxim Integrated │ 2


Electrical Characteristics (continued)


NANOPOWER RING
Nanopower Ring Frequency fNANO 3.8 14 kHz
DIGITAL I/O (Note 9)
8
Input High Voltage (All Pins 0.7 x
72
VIH VDD V
Except External Sensors) VDD
Input Hysteresis (All Pins
VIHYS 0.4 V
11
Except External Sensors)
Input Low Voltage (All Pins 0.3 x
VIL1 GND V
Except External Sensors) VDD
57
Output Low Voltage
VOL2 IOL = 2mA 0.4 V
(Standard Port Pins)
/6
Output High Voltage VDD
VOH2 IOH = -2mA V
(Standard Port Pins) -0.4
10
Output Low Voltage
VOL4 IOL = 4mA 0.4 V
(High-Drive Port Pins)
Output High Voltage VDD
H
VOH4 IOH = -4mA V

(High-Drive Port Pins) -0.4
28
Input Leakage Current IL Internal pullup disabled -1.0 +1.0 µA

Input Capacitance (HFXIN) CHFXIN 8 pF
Input Capacitance (32KIN) C32KIN 6 pF
DS
Input Capacitance
CIN 5 pF
(All Port Pins)
Input Pullup Resistance
E/
RPU 60 110 150 kΩ

(All Port Pins and RSTIN)
Input Pulldown Resistance
RPD 60 110 150 kΩ
(All Port Pins)
USB
USB Supply Voltage VUSB VDD V
Input High Voltage D+, D- VIH_USB (Note 10) 2.0 V
Input Low Voltage D+, D- VIL_USB (Note 10) 0.8 V
RL = 1.5 kΩ from DP to VUSB
Output Low Voltage D+, D- VOL_USB GND 0.3 V
and IOL = 4mA (Note 10)
RL = 15 kΩ from DP and DM to
Output High Voltage D+, D- VOH_USB 2.7 VDD V
GND and IOH = 4mA (Note 10)
Transition Time (Rise/Fall) D+,
tRF CL = 50pF (Note 10) 4 20 nS
D- (Note 11)
D+, D- Pin Capacitance CIN_USB Pin to GND 8 pF
Differential Input Sensitivity for
VDI FSD+ to FSD- (Note 10) 0.2 V
D+, D-
Common-Mode Voltage Range VCM Includes VDI range (Note 10) 0.8 2.5 V




Single-Ended Receiver
VSE (Note 10) 0.8 2.0 V
Threshold
Single-Ended Receiver
8
VSEH 200 mV
Hysteresis
72
Differential Output Signal
VCRS GBD 1.3 2.0 V
Cross-Point Voltage
11
Idle (Note 10) 0.9 1.7 kΩ
Internal Pullup Resistor RPU_USB
Receiving (Note 10) 1.425 3.090 kΩ
Driver Output Resistance RDRV 28 44 Ω
57
ENVIRONMENTAL SENSORS
VDD Overvoltage Threshold VDD_OV 3.6 3.8 V
/6
VBAT Undervoltage Threshold VBAT_UV 2.1 2.3 V
VBAT Over Voltage Threshold VBAT_OV 3.6 3.8 V
10
THTR 125.0
High-Temperature Threshold °C
THTRerr (Note 12) ±5
H
TLTR1 (Note 13) -60.0

THTR1err (Note 12) ±3.5
28
Low-Temperature Threshold °C
TLTR2 -37.0
TLTR2err (Note 12) ±2.5
DS
10-BIT ADC
Resolution 10 Bits
ADC Clock Frequency fACLK 0.1 6 MHz
E/
AN0–AN1 Input Voltage Range VAN GND VDDA V

Analog Input Capacitance CAIN 1 pF
Integral Nonlinearity INL (Note 14) ±2 LSB
Differential Nonlinearity DNL (Note 14) ±1 LSB
Offset Error VOS (Note 14) ±5 LSB
ADC Setup Time tADC_SU 30 µs
ADC Output Latency tADC 1025 TACLK
Due to channel or reference 48 FACLK
ADC Settling Time tADC_SETTLE
change 8 µs
ADC Throughput FADC 6 ksps
10-BIT ADC REFERENCE
Internal Reference Voltage VIREF 1.22 ±5% V
External Reference Voltage VEXTREF VDDA V
Internal Reference Setup Time tIREF_SU µs




8-BIT DAC
Resolution DACR Guaranteed monotonic 8 Bits
Differential Nonlinearity DNL Code 07 to F9h (Note 10) ±0.2 LSB
8
Integral Nonlinearity INL Code 07 to F9h (Note 10) ±0.4 LSB
72
Offset Error EO (Note 10) ±2 LSB
Gain Error EG (Note 10) ±2 LSB
11
Power-Up Time TPU 200 µs
Full-Scale Voltage VDACOUT 2.0 V
57
SMART CARD
Regulator on, SC_VDDA =
Active SC_VDDA Current 5V ILOAD + ILOAD +
IDD_SC5
/6
5.25V, fSC_CLK = 5MHz mA
Cards 2.5mA 3.5mA
(Note 10)
10
Active SC_VDDA Current 3V ILOAD + ILOAD +
IDD_SC33 3.3V, fSC_CLK = 5MHz mA
Cards 1.5mA 2.5mA
(Note 10)
H

Active SC_VDDA Current 1.8V ILOAD + ILOAD +
IDD_SC18 3.3V, fSC_CLK = 5MHz mA
28
Cards 1mA 1.5mA

(Note 10)
Inactive Mode Current IDD_SCIDLE Card inactive, regulator off 0.10 µA
DS
SMART CARD—SC_VCC
Output Low Voltage—
VSC_VCC1 ISC_VCC = 1mA (Note 10) 0 0.3 V
Card-Inactive Mode
E/
Output Current—
ISC_VCC1 SC_VCC = 0V (Note 10) 0 -1 mA
Card-Inactive Mode
Slew Rate—Card-Active Mode |VSC_VCCR| Up/down, C < 300nF 0.10 V/µs
5V supply selected,
4.60 5 5.25
ISC_VCC < -60mA (Note 10)
Output Low Voltage— 3V supply selected,
VSC_VCC2 2.78 3 3.22 V
Card Active Mode ISC_VCC < -55mA (Note 10)
1.8V supply selected,
1.66 1.8 1.94
ISC_VCC < -40mA (Note 10)
5V supply selected,
-60
VSC_VCC = 0V–5.25V (Note 10)
Output Current— 3V supply selected,
ISC_VCC2 -55 mA
Card Active Mode VSC_VCC = 0V–3.3V (Note 10)
1.8V supply selected,
-40
VSC_VCC = 0V–1.8V (Note 10)
Shutdown Current Threshold ISC_VCC_SD 170 mA




SMART CARD—SC_DETECT
0.3 x
Input Low Voltage VILSC_DETECT (Note 10) V
VDD
8
0.7 x
Input High Voltage VIHSC_DETECT (Note 10) V
72
VDD
Input Low Current IILSC_DETECT VSC_DETECT = 0V (Note 10) -5 -3 0 µA
11
Input High Current IIHSC_DETECT VSC_DETECT = VDD (Note 10) -1 +1 µA
SMART CARD—SC_CLK
57
VOLSC_CLK IOLSC_CLK = 1mA (Note 10) 0 0.3 V
Card Inactive Mode
Output Current—
IOLSC_CLK
/6
VOL_SCCLK = 0V (Note 10) ±15 µA
Card-Inactive Mode
Output Low Voltage— 0.2 x
VOL1SC_CLK IOLSC_CLK = 200μA (Note 10) 0 V
10
Card-Active Mode VSC_VCC
Output High Voltage— 0.7 x
VOHSC_CLK IOLSC_CLK = -200μA (Note 10) VSC_VCC V
H
CL = 30pF, fSC_CLK = 5MHz 8% of

Rise Time—Card-Active Mode tRSC_CLK ns
28
10%–90%, GBD fSC_CLK

CL = 30pF, fSC_CLK = 5MHz 8% of
Fall Time—Card-Active Mode tFSC_CLK ns
10%–90%, GBD fSC_CLK
DS
Current Limitation—
ISC_CLK_LIM (Note 10) -80 +80 mA
Card-Active Mode
Clock Frequency—
E/
fSC_CLK Operational (Note 10) 1 4.8 MHz

Card Active Mode
SMART CARD—SC_RST
VOLSC_RST IOLSC_RST = 1mA (Note 10) 0 0.3 V
Card Inactive Mode
Output Current—
IOLSC_RST VOLSC_RST = 0V (Note 10) ±15 µA
Card-Inactive Mode
VOL1SC_RST IOLSC_RST = 150μA (Note 10) 0 V
VOHSC_RST IOHRST = -200µA (Note 10) VSC_VCC V
Fall Time—Card-Active Mode TFSC_RST CL = 30pF, 90% to 10%, GBD 0.1 µs
Rise Time—Card-Active Mode TRCS_RST CL = 30 pF, 10% to 90%, GBD 0.1 µs
ISC_RST(LIMIT) (Note 10) -12 +12 mA
Card-Active Mode




SMART CARD—SC_C4, SC_C8
VOLSC_C48 IOLSC_C48 = 1mA (Note 10) 0 0.3 V
Card Inactive Mode
8
Output Current—
IOLSC_C48 VOLSC_C48 = 0V (Note 10) ±15 µA
72
Card-Inactive Mode
Internal Pullup Resistor— Between C4 or C8 and SC_
RPUPSC_C48 12.5 kΩ
Card Inactive Mode VCC (Note 10)
11
VOL1SC_C48 IOLSC_C48 = 1mA (Note 10) 0 0.3 V
Card-Active Mode
57
0.8 x
IOHSC_C48 ≤ -20μA (Note 10) VSC_VCC
Output High Voltage— VSC_VCC
VOHSC_C48 V
Card-Active Mode
/6
IOHSC_C48 ≤ -40μA (3V/5V) 0.75 x
VSC_VCC
(Note 10) VSC_VCC
10
ISC_C48(LIMIT) (Note 10) -15 +15 mA
Card-Active Mode
Output Rise/Fall Time— CL = 30 pF
tRFSC_C48 0.8 μs
H
Card-Active Mode fMAX_C48 = 1MHz, GBD

Input Low Voltage— 0.15 x
28
VILSC_C48 (Note 10) -0.3 V

Input Low Current—
IILSC_C48 VILSC_C48 = 0V (Note 10) -850 μA
DS
Card Active Mode

Input High Current— VIHSC_C48 = VSC_VCC
IIHSC_C48 20 μA
Card Active Mode (Note 10)
E/
Input High Voltage— 0.7

VIHSC_C48 (Note 10) VSC_VCC V
Card Active Mode VSC_VCC
SMART CARD—SC_IO
VOLSC_IO IOLSC_IO = 1mA (Note 10) 0 V
Card Inactive Mode VSCVCC
Output Current—
IOLSC_IO VOLSC_IO = 0V (Note 10) ±15 μA
Card-Inactive Mode
Internal Pullup Resistor—
RPUPSC_IO To SC_VCC (Note 10) 11.5 kΩ
Card Inactive Mode
VOL1SC_IO IOLSC_IO = 1mA (Note 10) 0 V
Card-Active Mode VSCVCC
VOHSC_IO IOHSC_IO ≤ -20μA (Note 10) VSCVCC V
Output High Voltage— IOHSC_IO ≤ -40μA (3V/5V) 0.75 x
VOHSC_IO VSCVCC V
Card Active Mode (Note 10) VSCVCC
ISC_IO(LIMIT) (Note 10) -15 +15 mA
Card-Active Mode




Output Rise/Fall Time—
TRFSC_IO CL = 30 pF, GBD 0.8 μs
Card-Active Mode
Input Low Voltage— 0.15 x
8
VILSC_IO (Note 10) -0.3 V
72
Input Low Current—
IILSC_IO VILSC_IO = 0V (Note 10) -850 µA
Card Active Mode
11
Input High Current— VIHSC_IO = VSC_VCC
IIHSC_IO 20 µA
Card Active Mode (Note 10)
Input High Voltage— 0.7 x
57
VIHSC_IO (Note 10) VSCVCC V
Card Active Mode VSCVCC
SMART CARD TIMING
/6
Activation Time tACT 160 μs
Deactivation Time tDEACT 80 μs
10
SC_DETECT Debounce Time tDBSC_DETECT 8 ms
FLASH MEMORY
Mass erase 35
H
Flash Erase Time ms

Page erase 4.5
28
Flash Programming Timer per

55 µs
Word
DS
Write/Erase Cycles 20,000 Cycles

Data Retention TA = +85°C 20 Years
Note 2: Measured on the VDD pin and the part not in reset. All inputs are connected to GND or VDD. Outputs do not source/sink any
E/
current. Part is executing code from internal RAM.

current.
current.
Note 5: Measured on the VBAT pin. VMAIN = 0V, VBAT = 3.3V, and VDD = 0V. All inputs connected to GND. Outputs do not source/
sink any current. RTC, die shield, temperature sensors, voltage sensors, and external sensors are enabled. External sensor
pairs are tied together with 0Ω resistors. The external sensor clock is 2kHz.
Note 6: Measured on the VMAIN pin. VMAIN = 3.3V, VBAT = 3.3V and VDD = 0V. All inputs connected to GND. Outputs do not
source/sink any current. RTC, die shield, temperature sensors, voltage sensors, and external sensors are enabled. External
sensor pairs are tied together with 0Ω resistors. The external sensor clock is 2kHz.
Note 7: Measured on the VBAT pin. VMAIN = 2.8V, VBAT = 3.6V and VDD = 0V. All inputs connected to GND. Outputs do not source/
sink any current.
Note 8: External oscillator duty cycle should be between 45% and 55%.
Note 9: The maximum total current, IOH (max) and IOL (max), for all listed outputs combined should not exceed 100mA to satisfy the
maximum specified voltage drop.
Note 10: Production tested at TA = +85°C.
Note 11: As per USB 2.0 specification, rise and fall time transitions must also be matched to within ±10%.
Note 12: 3-sigma limits based on characterized part.
Note 13: NMI response is not guaranteed under this operating condition. The AES key wipe operation, however, is guaranteed.
Note 14: Production tested at TA = +25°C.


Pin Configuration
TOP VIEW MAX32555

1 2 3 4 5 6 7 8 9 10 11
8
USB_ USB_
A P0.15 P0.20 P0.17 P0.16 P0.19 P0.23 P0.24 P0.26 P0.28 A
DM DP
72
B 32KIN 32KOUT P0.11 P0.9 VDD REG P0.18 P0.25 P0.27 P0.30 P2.0 B
11
57
C P0.14 P0.13 P0.12 P0.10 HFXOUT HFXIN P0.22 P0.31 P0.29 P2.2 P2.4 C
/6
EXTS2 EXTS0_ EXTS3 EXTS2
D VMAIN ADC5 VDD VSS P2.1 P1.3 P1.1 D
_IN OUT _IN _OUT
10
E VBAT P0.8 VSS P0.0 P0.1 P0.2 P0.3 ADC2 P2.3 P1.0 P1.5 E
H
28
ADC_ EXTS1 EXTS1

F ADC0 ADC3 P0.21 SC_IO P0.4 P2.5 P1.2 P1.7 F
VREF _IN _OUT
DS
EXTS3 EXTS0
G ADC1 DAC0 VDDA P0.7 P0.6 P0.5 P1.4 P1.6 P1.8 G
_OUT _IN
E/
MCR MCR SC_ SC_ RST RST_

H GNDA ADC4 VDD P1.9 P1.10 H
_3P _2P VDDA GND _IN OUT
J MCR_ MCR SC_ SC J

P1.30 P1.28 P1.23 P1.17 P1.12 P1.14 P1.11
3N _2N RST _C8
MCR_ SC_ SC_

K P1.29 P1.26 VSS REG P1.19 P1.20 P1.15 P1.13 K
1P VCC C4
MCR_ SC_ SC_

L P1.31 P1.27 P1.25 P1.24 P1.21 P1.22 P1.18 P1.16 L
1N CLK DETECT
1 2 3 4 5 6 7 8 9 10 11


Pin Description
GPIO PORT PRIMARY SECONDARY
BALL FUNCTION
NUMBER FUNCTION FUNCTION
E4 P0.0 KBD0 — Keyboard I/O
8
F7 P0.4 KBD4 — Keyboard I/O
72
G7 P0.5 KBD5 — Keyboard I/O
11
E2 P0.8 RXD0 — UART0 Data Input
57
B4 P0.9 TXD0 — UART0 Data Output
C4 P0.10 RTS0 SC_C4_BYP UART0 Request to Send/Smart Card C4 Bypass
/6
B3 P0.11 CTS0 SC_C8_BYP UART0 Clear to Send/Smart Card C8 Bypass
C3 P0.12 RXD1 — UART1 Data Input
10
C2 P0.13 TXD1 — UART1 Data Output
C1 P0.14 RTS1 — UART1 Request to Send
A1 P0.15 CTS1 SQW UART1 Clear to Send/RTC Square-Wave Out
H
A6 P0.16 MISO0 — SPI0 Master In, Slave Out

28
A3 P0.17 MOSI0 — SPI0 Master Out, Slave In

B7 P0.18 SCLK0 — SPI0 Clock
DS
A7 P0.19 SSEL0_0 — SPI0 Slave Select 0

F5 P0.21 SSEL0_2 SC_IO_BYP SPI0 Slave Select 2/Smart Card I/O Bypass
E/
C7 P0.22 SSEL0_3 SC_RST_BYP SPI0 Slave Select 3/Smart Card Reset Bypass
A8 P0.23 SDA — I2C Data
A9 P0.24 SCL — I2C Clock
B8 P0.25 MISO1 — SPI1 Master In, Slave Out
A10 P0.26 MOSI1 — SPI1 Master Out, Slave In
B9 P0.27 SCLK1 — SPI1 Clock
C9 P0.29 SSEL1_1 — SPI1 Slave Select 1
B10 P0.30 SSEL1_2 TCLK2 SPI1 Slave Select 2/Timer 2 CLK I/O
C8 P0.31 SSEL1_3 TCLK3 SPI1 Slave Select 3/Timer 3 CLK I/O
E10 P1.0 TCLK0 SC_DETECT_BYP Timer 0 CLK I/O/Smart Card Detect Bypass
D11 P1.1 TCLK1 SC_CLK_BYP Timer 1 CLK I/O/Smart Card CLK Bypass


Pin Description (continued)

BALL FUNCTION
F10 P1.2 LCD_DATA0 — Mono LCD Data 0
D10 P1.3 LCD_DATA1 — Mono LCD Data 1
G9 P1.4 LCD_DATA2 — Mono LCD Data 2
E11 P1.5 LCD_DATA3 — Mono LCD Data 3
8
72
F11 P1.7 LCD_DATA5 — Mono LCD Data 5
11
H10 P1.9 LCD_DATA7 — Mono LCD Data 7
H11 P1.10 LCD_EN — Mono LCD Enable
57
J11 P1.11 LCD_RS — Mono LCD Command/Data Select
J9 P1.12 LCD_RW — Mono LCD RW
K11 P1.13 MISO2 —
/6 SPI2 Master In, Slave Out
J10 P1.14 RXD2 — UART2 Data Input
K10 P1.15 TXD2 — UART2 Data Output
10
L11 P1.16 RTS2 — UART2 Request to Send

J8 P1.17 CTS2 — UART2 Clear to Send
H
L10 P1.18 TCLK4 — Timer 4 CLK I/O

28
K8 P1.19 SSEL2_2 — SPI2 Slave Select 2

K9 P1.20 SSEL2_0 — SPI2 Slave Select 0
DS
L8 P1.21 MOSI2 — SPI2 Master Out, Slave In

J7 P1.23 — —
E/
L7 P1.24 — —
L6 P1.25 — —
K5 P1.26 — —
L5 P1.27 SSEL2_3 — SPI2 Slave Select 3
J6 P1.28 SSEL2_1 — SPI2 Slave Select 1
K4 P1.29 SCLK2 — SPI2 Clock
J5 P1.30 TCLK6 — Timer 6 CLK I/O
G8 — EXTS0_IN — External Sensor 0 Input
D5 — EXTS0_OUT — External Sensor 0 Output
F3 — EXTS1_IN — External Sensor 1 Input
F8 — EXTS1_OUT — External Sensor 1 Output
D4 — EXTS2_IN — External Sensor 2 Input
D7 — EXTS2_OUT — External Sensor 2 Output



BALL FUNCTION
D6 — EXTS3_IN — External Sensor 3 Input
G3 — EXTS3_OUT — External Sensor 3 Output
E8 — ADC2 — ADC Channel 2
F4 — ADC3 — ADC Channel 3
8
H5 — ADC4 — ADC Channel 4
72
D2 — ADC5 — ADC Channel 5
A4 — USB_DM — USB D-
11
A5 — USB_DP — USB D+
B11 P2.0 VBUS_DET — USB VBUS Detect
57
H8 — RSTIN — System Reset Input
H9 — RSTOUT — System Reset Output
/6
C6 — HFXIN — High-Frequency Crystal Clock Input
C5 — HFXOUT — High-Frequency Crystal Clock Output
10
B1 — 32KIN — 32K RTC Crystal Input
B2 — 32KOUT — 32K RTC Crystal Output
D9 P2.1 TDI — JTAG Test Data Input
H
C10 P2.2 TDO — JTAG Test Data Output

28
E9 P2.3 TMS — JTAG Test Mode Select

C11 P2.4 TCK — JTAG Test Clock
DS
F9 P2.5 JTRST — JTAG Reset

B5, D3, H6 — VDD — Digital Supply Voltage
B6,K7 — REG — Regulator Capacitor
E/
E1 — VBAT — Battery Backup Power Supply

D1 — VMAIN — Main Battery Supply for Battery Backup mode
D8, E3, K6 — VSS — Core and I/O Power Supply Ground
H4 — GNDA — Analog Ground
G4 — VDDA — Analog 3.3V Power Supply
H3 — SC_VDDA — Smart Card PHY Power Supply
L3 — SC_DETECT — Smart Card Detect
K2 — SC_VCC — VCC (1.8V/3V/5V) Output to Smart Card
H7 — SC_GND — VSS Output to Smart Card
F6 — SC_IO — Smart Card I/O
J3 — SC_RST — Smart Card Reset
K3 — SC_C4 — Smart Card C4



BALL FUNCTION
J4 — SC_C8 — Smart Card C8
L2 — SC_CLK — Smart Card CLK
K1 — MCR_1P — Magnetic Stripe Reader Track 1, Positive Input
L1 — MCR_1N — Magnetic Stripe Reader Track 1, Negative Input
8
H2 — MCR_2P — Magnetic Stripe Reader Track 2, Positive Input
72
J2 — MCR_2N — Magnetic Stripe Reader Track 2, Negative Input
H1 — MCR_3P — Magnetic Stripe Reader Track 3, Positive Input
11
J1 — MCR_3N — Magnetic Stripe Reader Track 3, Negative Input
F1 — ADC0 — ADC Channel 0
57
G1 — ADC1 — ADC Channel 1
F2 — ADC_VREF — ADC Voltage Reference
/6
G2 — DAC0 — DAC Output Pin
H 10
28
DS
E/


Detailed Description The device also includes 1KB of battery-backed non-

The MAX32555 is built around the ARM Cortex-M3 core, volatile SRAM. This memory is provided for both secure
an enhanced 32-bit RISC CPU with memory protection unit data storage where data is automatically AES encrypted/
(MPU). It also provides separate instruction and data AMBA decrypted upon access and plain data such as transac-
AHB, interfaces connected to a multilayer AHB Matrix. The tion logs where security is not a primary concern, but data
Cortex-M3 processor implements the ARMv7-M architec- endurance is. The amount of space reserved for secure
ture instruction set. The ARMv7-M instruction set supports and plain data is user configurable.
Thumb and Thumb-2 instructions sets as well as 1-cycle Data stored in the secure partition is automatically
8
32-bit hardware multiply operations. encrypted by a dedicated hardware AES-256 engine and
using a random key that has been generated upon user
72
Refer to the Cortex-M3 Technical Reference Manual for
more details on operation of these features. This data sheet request. This random key is stored in a dedicated 256-bit
is an introduction to the primary features of the MAX32555. flip-flop-based secure nonvolatile key register that is auto-
11
Detailed descriptions of the device’s features can be found matically wiped upon triggering by one of the intrusions
in the user guides and errata sheets for this product. and environmental sensors, both internal and external.
The key itself can only be read by the dedicated AES-
57
Memory Map 256 engine and is not mapped on the AHB/APB buses,
The MAX32555 memory map is contiguous from 0000 making it unreadable from any other system peripherals
0000h to FFFF FFFFh with regions defined for different including CPU and JTAG. The block also provides a way
/6
memory types. Each memory/peripheral type is entirely to override the self-generated AES key with a user sup-
contained within its defined region. plied AES-256 key.
10
The MAX32555 internal memory region contains the pro- Internal ROM and Bootloader
gram and data memories for the CPU. Upon assertion and deassertion of system reset, the
H
Internal Flash Cortex-M3 is reset and begins program execution of

internal ROM code at address 0x00000000. A secure
The MAX32555 embeds 512MB of flash memory that is
28
bootloader is implemented to provide trusted boot, secure

split in two banks of 256KB. Each bank can be reconfig-
flash upload, flash integrity verification upon reboot, and
ured to be used upon reset through a secure selection
flash bank selection.
DS
mechanism. Furthermore the device simplifies remote

firmware upgrades by ensuring that only a valid firmware A built-in public key authentication scheme allows secure
is used upon boot. firmware updates from both UART and USB interfaces.
The flash also features a dedicated flash acceleration The secure bootloader is configured to use parameters
E/
engine to avoid latencies when executing code at the stored in OTP and/or NVSRAM.
maximum operating frequencies.
Internal OTP
Internal SRAM and NVSRAM The internal OTP memory resides on the APB bus. A spe-
The internal system SRAM is 96KB of zero wait-state cial controller is designed to read and write the bits in the
memory that is split into two banks of 48KB. Each of them OTP. The OTP offers 1KB of user storage.
is a dedicated AHB slave on the matrix, thus maximizing
the on-chip bandwidth and allowing parallel data transfers.


AMBA AHB Bus ●● Support for nesting and preemption by higher priority
The MAX32555 implements a four-layer 32-bit AHB bus interrupts
matrix. Arbitration between these peripherals is managed ●● Support for NMI (nonmaskable interrupts)
by a fixed burst arbitration scheme, wherein each master
has a fixed priority. Mono LCD Controller
The LCD interface allows an external LCD to be accessed
Interrupt Controller directly over the APB. This interface has the following
The MAX32555 includes the ARM nested vector inter- features:
8
rupt controller(NVIC), providing high speed, determin- ●● Directly compatible with popular monochrome LCDs,
istic response, interrupt masking, and multiple interrupt text, and graphic modes
72
sources.
●● Supports interfaces of 4-/8-bit data and 3 control
Features of the interrupt controller include:
●● Read and writes to external LCD-module-supported
11
●● IRQ generation for each interrupt source (program- register operations
mable)
●● Programmable read and write cycle times
57
●● Unique vectors for each interrupt channel
●● Programmable priority for each channel (8 priority
levels)
/6
10
AHB MASTER
H
USB DMA ARM S Crypto

28
1 2 3 4
DS
E/
INTERCONNECT MATRIX
1 2 3 4 5 6 7 8
APB USB NVSRAM DAC

TRNG SRAM0 SRAM1 MSR
Bridge CFG
AHB SLAVE
Figure 1. Bus Priority


USB Triple-Track Magnetic Stripe Head Interface

The MAX32555 provides one USB full-speed device inter- The magnetic stripe decoders embed a complete high-
face with a dedicated transceiver. performance solution for reading and decoding 3-track
The USB device ports allows seamless connection to magnetic stripe cards. It includes three parallel ADCs to
external USB hosts and provides a flexible endpoint process track data as well as filtering and decoding logic.
management for addressing most USB classes including SPI
composite devices.
The Serial Peripheral Interface (SPI) is a synchro-
●● Complies with USB specification rev. 2.0
8
nous interface allowing several SPI-compatible devices
●● Supports 12Mbps and 1.5Mbps data transmission to be interconnected. SPI-compatible devices include
72
EEPROMs, printer controllers, and contactless smart card
●● Integrated USB transceiver
controllers. The MAX32555 implements three indepen-
●● Programmable USB RAM for flexible endpoint con- dent SPI controllers for maximum flexibility. Each of the
11
figuration SPI controllers supports the follow features:
●● Dedicated DMA channel ●● Full-duplex, synchronous communication of 8-/6-bit
57
DMA Controller characters
The DMA controller allows automatic one-way data trans- ●● 4-wire interface plus 3 additional slave selects
/6
fer between two entities. These entities can be either ●● Data transfers rates up to one-fourth the PCLK fre-
memories or peripherals. The transfers are done without quency
using CPU resources. The following transfer modes are
10
●● Master mode of operation
supported:
●● Dedicated baud rate generator
●● 4-channel
●● 8 x 16 transmit and receive FIFOs
H
●● Peripheral-to-memory
●● Transmit and receive DMA support
●● Memory-to-peripheral
28
●● Maximum baud rate: 15Mbps

●● Memory-to-memory
All DMA transactions consist of an AHB burst read into the I2C
DS
DMA FIFO followed immediately by an AHB burst write The I2C host port is compliant with the Philips I2C stan-
from the FIFO. dard. The I2C port is a half duplex serial port that uses
two lines (data and clock) for data transmission. The
Cryptographic Accelerator
E/
MAX32555 chip provides two dedicated open-drain I/Os

The hardware cryptographic accelerator block is used to for the I2C bus. The I2C port can be set up as a master
assist the computationally intensive operations of several only. Standard 100kHz and fast 400kHz transmit modes
common algorithms. Supported algorithms include: are supported.
●● AES-128, 192, and 256 (FIPS 197) ●● I2C bus specification version 2.1 compliant (100kHz
●● DES and 3DES (NIST SP800-67) and 400kHz)
●● SHA-1, 224, 256, 384, and 512 (FIPS 180-3) ●● Programmable for both normal (100kHz) and fast bus
data rates (400kHz)
●● Modulo arithmetic hardware accelerator (MAA) with
support up to 2048-bit DSA and ECDSA, 4096-bit ●● Programmable for using normal addressing
(CRT) RSA ●● Clock synchronization and bus arbitration
The cryptographic accelerator is configured through an ●● Supports arbitration in a multimaster environment
APB register interface. Some of its features include: ●● Fully programmable slave response address
●● Integrated DMA with read ahead and write buffers for ●● 2 FIFOs (Rx and Tx)
high throughput
●● Supports I2C bus hold for slow host service
●● Support for NIST approved block modes (SP800-38A)
●● Transfer status interrupts and flags
●● Parallel calculation of block cipher and hash functions


Smart Card Interface allows it to optionally keep running even when the main
The MAX32555 smart card controller embeds both the digital supply (VCORE) for the device is powered down.
digital core and analog transceiver of the Smart Card The RTC’s time base is the external 32.768kHz crystal.
interface. The built-in transceiver is responsible of voltage The MAX32555 includes a battery backup switch to
translation according to the EMV or ISO7816-1 standard automatically and safely switch between different power
and can support 1.8V and 3V cards with internal power sources while maintaining nonvolatile SRAM content.
supply and 5V cards with external 5V power supply. A Many mobile pin pad implementations cut the main power
bypass mode is available to use an external transceiver. supply from the secure microcontroller when in stop
8
The dedicated card detection input can be used to wake- mode. The internal battery backup switch has two dedi-
up the device when in standby mode. cated input pins, VBAT that connects to a traditional non-
72
The ISO-7816 UART supports the following features: rechargeable lithium battery, and another called VMAIN
that connects to the main rechargeable battery through
●● ISO/IEC 7816 standards supported
11
an external low drop voltage regulator. Tamper detec-
●● Supports both synchronous and asynchronous cards tion applies to whatever input pin is currently selected by
●● 11-bit elementary time unit (ETU) counter the internal battery switch. The switch gives the priority
57
over to the VMAIN so the system drains as much current
●● 9-bit guard time counter
as possible from the main rechargeable battery before
●● 32-bit general-purpose waiting time counter switching to the hard-to-replace lithium battery. It allows
/6
●● Auto character repetition on error signal detection in the end devices to be stored on shelves for long periods
transmit mode of time and without the fear of losing NVSRAM content
10
●● Auto error signal generation on parity error detection because of exhausted lithium battery.
in receive mode It is also possible to connect VMAIN to VDD to switch to
the lithium battery as soon as the power is removed from
H
●● Manual mode to directly drive the card IOs

the MAX32555.
●● 8-level FIFO
28
The 32-bit second counter can count up to approximately

Random Number Generator 136 years and be translated to calendar format by appli-
Random numbers are the cornerstone of many security cation software. A time-of-day alarm and independent
DS
systems providing values that cannot be predicted by sub-second alarm can cause an interrupt or wake the
attackers. They prevent from replay attacks or key search device from standby mode. The independent subsecond
approaches. The best quality random numbers come alarm runs from the same RTC and allows the application
to support interrupts with a minimum interval of approxi-
E/
from true random number generators (TRNG) that base

their source of randomness on a physical unpredictable mately 3.9ms. This creates an additional timer that can
phenomenon. be used to measure long periods of time without perfor-
mance degradation.
The TRNG embedded in the MAX32555 chip is designed
to efficiently generate a 128-bit true random number in Traditionally, long time periods have been measured
128 system clock cycles. For example, only four consecu- using multiple interrupts from shorter interrupt intervals.
tive read accesses (32-bit access) are needed to obtain a Each timer interrupt required servicing, with each accom-
128-bit AES random key ready for encryption. The TRNG panying interruption slowing system operation. By using
passes NIST 800-22 and DIEHARD test suites. the RTC subsecond timer as a long-period timer, only one
interrupt is needed, eliminating the performance hit asso-
Real-Time Clock (RTC) ciated with using a shorter timer. The device also includes
The device includes a binary real-time clock (RTC) that a trimming feature with 1ppm resolution and can correct
keeps the time of day in absolute seconds with 1/256s up to ±127ppm.
resolution. The RTC operates from the VBAT supply that


Timers/Counters/PWM External Tamper Sensors

There are eight 32-bit reloadable timers with four asso- The device provides four external dynamic tamper sen-
ciated output pins that can be used for timing, event sors. Each external tamper sensor uses two pins (EXTS_
counting, or generation of pulse-width modulated (PWM) IN, EXTS_OUT) that provide a random, changing pattern
signals. The timers’ features include: generated by an internal, true random entropy source.
●● 32-bit reload counter The two pins of an external tamper sensor can be con-
nected to a mesh or user-defined, normally-closed tamper
●● Programmable prescaler with prescale values from 1 switch. Any mismatch on the EXTS_IN pin of a sensor
to 4096
8
pair triggers a destructive NMI after a user-configurable
●● Hi-drive (8mA) PWM output generation (timer 0–7 number of mismatches has been detected. Each pair
72
only) of sensor pins generates a unique signal and can be
●● Capture, compare and capture/compare capability independently enabled. One of the dynamic sensors has
11
a removal detection function for EPP application. When
●● External input pin for timer input, clock gating, or cap-
the EPP is legally removed from an ATM machine, the
ture signal (timer 0–7 only)
register SDBE is set instead of triggering a destructive
57
●● Timer output pin (timer 0–7 only) NMI. If the removal detection function is not enabled, the
●● Timer interrupt dynamic sensor triggers a destructive NMI upon tamper.
/6
UART Destructive NMI (DNMI)
A UART or universal asynchronous receiver-transmitter A DNMI is caused by triggering a tamper response or
is a piece of computer hardware that translates between environmental out of range condition. This causes the
10
part to instantly wipe the NVSRAM AES master key as

parallel bits of data and serial bits. The MAX32555
well as other sensitive registers. In the meantime, the
embeds three UARTs. The UARTs contain a shift register
device triggers a nonmaskable interrupt (NMI) to allow
H
that is used to convert data from a serial to a parallel form

a flexible and early answer to attack once the sensitive
and supports the following functions:
28
data is cleared (i.e., data logging). The NMI handler is

●● 8-byte FIFO user defined and stored in flash (default), but can also be
●● Programmable baud rate generator up to 6Mbps re-located in SRAM. Maxim provides hardware hooks and
DS
code examples for easily erasing the flash, SRAM, and

●● 5, 6, 7, or 8 data bits
NVSRAM content by the destructive NMI routine.
●● 1, 1.5, or 2 stop bits
Secure Keypad
E/
●● Odd, even, or no parity

The MAX32555 includes 8 I/Os that can be used by the
●● Interrupt generation secure keyboard controller. They are connected to a key
●● Supports Rx, Tx, CTS, and RTS signals matrix without the need for additional external components.
Security Monitor The keyboard controller supports the following features:
The behavior of the system is constantly monitored by a ●● 4 x 4 or 3 x 5 matrix
range of internal and external sensors. ●● Management of up to 16 keys
Internal Sensors ●● Randomized spread-spectrum key scanning
The internal sensors include environmental sensors such ●● Debouncing feature
as die shield sensor, programmable temperature sensor,
●● Four key registers
and battery-backed voltage sensor. Furthermore, there are
core sensors monitoring internal core voltages on all rails. ●● Push-and-release key detection features
Depending of the triggering source, the device might only ●● One-time readable key registers
reset or the encryption keys might be instantly wiped fol- ●● Secure scanning features
lowed by a destructive NMI. ●● GPIO mode
●● Integrated pullup and pulldown
Additional GPIO pins are available for nonsecure key
scanning.


Power Management System Reset

The Power Management Unit (PMU) controls system The MAX32555 provides following types of Reset operations:
clocking and power management. The configuration of ●● Hard reset
the PMU is performed through the PMU registers.
●● System reset
Upon a hard reset, the PMU drives the main oscillator
clock onto the system clock. All digital clock domains are ●● Peripheral reset
enabled and most analog circuits are powered down. Hard reset: A hard reset is caused by the reset input pin,
Various power-down modes are available for optimum an internal power-on reset, watchdog timeout, or a tamper
8
system performance configuration: reset from the security module. A hard reset resets all
72
●● Active digital modules of the device. The hard reset is asserted
asynchronously by any of its sources. The hard reset is
●● Idle with wake-up from GPIO, USB, and RTC released synchronously to the CLKXI oscillator input after
11
●● Standby all reset sources have been inactive for 16 clock cycles.
●● Battery backup with RTC alarm wakeup to power System reset: A system reset is caused by a hard reset
manager chip or a soft reset. A system reset resets all modules except
57
Additionally, the power management unit can help reduce the power management unit (PMU) and watchdog timer. A
power consumption even further by offering the following system reset is driven out onto the RSTOUT pin.
/6
features: Peripheral reset: A peripheral reset is caused by a sys-
●● Integrated oscillator with configurable PLL and flex- tem reset or an individual peripheral reset. These signals
reset APB peripherals, with the exception of the CPU,
10
ible prescaler options
PMU, watchdog timer, GPIO, and secure access.
●● Configurable dynamic CPU clock switching for fre-
quency stepping upon system load 10-Bit ADC
H
●● Independent CPU and peripherals clock domains for The ADC is a 10-bit analog-to-digital-converter. The fol-
28
slowing down CPU when performance is less required lowing features are supported:
●● Individual clock gating where each peripheral’s clock ●● Six channels
can be enabled and disabled on demand ●● Single-shot mode
DS
●● On-chip, low-frequency RC oscillator for running the ●● Conversion rate 6K samples/s

CPU at ultra-low speed while maintaining some back-
●● Power-down mode performing minimal power dissi-
ground activity
E/
pation
GPIO ●● Programmable threshold interrupts—each channel
A total of up to 70 GPIO pins are available on the device. has a high and low reading register. If any ADC read-
The GPIO module enables direct I/O control of the GPIO ing on that channel falls outside those thresholds, and
pins. Most pins are shared with a peripheral function interrupt is triggered if enabled.
and can be used as GPIO when the function is unused. The ADC can operate from an external or internal voltage
Though this multiplexing between peripheral and GPIO reference. The accuracy of conversions depends greatly
functions is usually static, it can also be done dynamically. on the quality of the VREF voltage supplied. VREF can be
The primary features of the GPIO module are: tied to the Analog VDD for the ADC. Care should be taken
●● Up to 70 GPIO pins to filter noise to achieve the best performance.
●● Configured as input, output, or I/O 8-Bit DAC
●● Generate interrupt The DAC is an 8-bit single-channel digital-to-analog con-
●● Interrupt generated on level or edges verter. The following features are supported:
●● Up to four independent interrupts ●● Output sample rate control
●● Wake the power management unit on rising/falling ●● Data flow control interrupts- FIFO almost empty, FIFO
edge underflow, data pattern done
●● Interpolation filter to enhance dynamic performance,
supporting 1:2, 1:4, and 1:8 interpolation


Watchdog Timer Additional Documentation

A watchdog timer is used to trigger a system reset if the Designers must have the following documents to fully use
application fails due to a hang and does not reload the all the features of this device. This data sheet contains
counter at regular intervals. The purpose of the watchdog pin descriptions, feature overviews, and electrical specifi-
is to bring the system back from a nonoperational state to cations. Errata sheets contain deviations from published
normal operation. The watchdog timer can also be used specifications. User guides contain detailed descriptions
as followed: of device features and peripherals from a programming
●● Internal system reset on timer overflow perspective.
8
●● Interrupt generation (IRQ) in timeout ●● This MAX32555 data sheet, which contains electrical/
72
timing specifications, package information, and pin
Input clock watched by the MAX32555 security mecha- descriptions.
nisms. The watchdog supports 16 programmable time
delay periods with prescale values from 216 to 231. For ●● The MAX32555 revision-specific errata sheet.
11
system clock running at 60MHz, a maximum timeout ●● The MAX32555 User Guide, which contains detailed
delay of 35s is supported. information and programming guidelines for core fea-
57
tures and peripherals.
JTAG Port
The JTAG interface is used for code loading, ICE debug Development and Technical Support
/6
activities and for control of Boundary Scan activities. Technical support is available at https://support.maxi-
The ordering information section contains unique part mintegrated.com/micro.
numbers for devices with the JTAG interface enabled or
10
disabled. Devices with the JTAG interface enabled are

used during application development and debugging.
H
Devices with the JTAG interface disabled prevent access

to the debugging interface and should be used in mass
28
production. For more Information, refer to the Secure

ROM User Guide.
DS
Ordering Information Package Information

For the latest package outline information and land patterns
E/
PART PIN-PACKAGE ICE (footprints), go to www.maximintegrated.com/packages. Note

121 CSBGA that a “+”, “#”, or “-” in the package code indicates RoHS status
MAX32555-LNS+ No only. Package drawings may show a different suffix character, but
(8mm x 8mm, 0.65mm pitch)
the drawing pertains to the package regardless of RoHS status.
MAX32555-LNJ+ 121 CSBGA Yes
(8mm x 8mm, 0.65mm pitch) PACKAGE PACKAGE LAND
OUTLINE NO.
TYPE CODE PATTERN NO.
+Denotes a lead(Pb)-free/RoHS-compliant package.
121 CSBGA X12188+3C 21-0680 90-0451


Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 6/15 Initial release —
8
72
11
57
/6
H 10
28
DS
E/
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │ 21

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MAXIM INTEGRATED CONFIDENTIAL/DISTRIBUTE ONLY UNDER NDA

EVALUATION KIT AVAILABLE

MAX32555 DeepCover Secure Cortex-M3

General Description Benefits and Features

• USB 2.0 Device with Internal Transceiver and

• 8 Timers, All with PWM Capability

SECURITY RTC* • Monochrome LCD Controller

SMART CARD MONO LCD

*5V smart card support requires external 5.0V supply.

19-7145; Rev 0; 6/15

MAX32555 DeepCover Secure Cortex-M3

Absolute Maximum Ratings

Package Thermal Characteristics (Note 1)

Main Battery Supply Voltage VMAIN 0 3.6 V

Main Battery Supply Switching VMAIN_

Supply Current (Note 2) IDD1 60 80 mA

www.maximintegrated.com Maxim Integrated │ 2

MAX32555 DeepCover Secure Cortex-M3

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VOH4 IOH = -4mA V

Input Leakage Current IL Internal pullup disabled -1.0 +1.0 µA

RPU 60 110 150 kΩ

www.maximintegrated.com Maxim Integrated │ 3

MAX32555 DeepCover Secure Cortex-M3

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TLTR1 (Note 13) -60.0

AN0–AN1 Input Voltage Range VAN GND VDDA V

www.maximintegrated.com Maxim Integrated │ 4

MAX32555 DeepCover Secure Cortex-M3

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Regulator on, SC_VDDA =

Cards 1mA 1.5mA

www.maximintegrated.com Maxim Integrated │ 5

MAX32555 DeepCover Secure Cortex-M3

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CL = 30pF, fSC_CLK = 5MHz 8% of

10%–90%, GBD fSC_CLK

fSC_CLK Operational (Note 10) 1 4.8 MHz

www.maximintegrated.com Maxim Integrated │ 6

MAX32555 DeepCover Secure Cortex-M3

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Card-Active Mode fMAX_C48 = 1MHz, GBD

VILSC_C48 (Note 10) -0.3 V

Card Active Mode

Input High Voltage— 0.7

www.maximintegrated.com Maxim Integrated │ 7

MAX32555 DeepCover Secure Cortex-M3

Electrical Characteristics (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Flash Erase Time ms

Flash Programming Timer per

Write/Erase Cycles 20,000 Cycles

current. Part is executing code from internal RAM.

www.maximintegrated.com Maxim Integrated │ 8