Am29F800B: Data Sheet

Am29F800B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 21504 Revision E Amendment 2 Issue Date June 1, 2004

THIS PAGE LEFT INTENTIONALLY BLANK.
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation ■ Embedded Algorithms
— 5.0 Volt-only operation for read, erase, and — Embedded Erase algorithm automatically
program operations preprograms and erases the entire chip or any
— Minimizes system level requirements combination of designated sectors
— Embedded Program algorithm automatically
■ Manufactured on 0.32 µm process technology
writes and verifies data at specified addresses
— Compatible with 0.5 µm Am29F800 device
■ Minimum 1,000,000 program/erase cycles per
■ High performance sector guaranteed
— Access times as fast as 55 ns ■ 20-year data retention at 125°C
■ Low power consumption (typical values at — Reliable operation for the life of the system
5 MHz) ■ Package option
— 1 µA standby mode current — 48-pin TSOP
— 20 mA read current (byte mode) — 44-pin SO
— 28 mA read current (word mode) — 48-ball FBGA
— 30 mA program/erase current — Known Good Die (KGD)
■ Flexible sector architecture (see publication number 21631)
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and ■ Compatibility with JEDEC standards
fifteen 64 Kbyte sectors (byte mode) — Pinout and software compatible with single-
— One 8 Kword, two 4 Kword, one 16 Kword, and power-supply Flash
fifteen 32 Kword sectors (word mode) — Superior inadvertent write protection
— Supports full chip erase
■ Data# Polling and toggle bits
— Sector Protection features:
— Provides a software method of detecting
A hardware method of locking a sector to program or erase operation completion
prevent any program or erase operations within
that sector ■ Ready/Busy# pin (RY/BY#)
— Sectors can be locked via programming — Provides a hardware method of detecting
equipment program or erase cycle completion
Temporary Sector Unprotect feature allows code ■ Erase Suspend/Erase Resume
changes in previously locked sectors — Suspends an erase operation to read data from,
■ Top or bottom boot block configurations or program data to, a sector that is not being
available erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Publication# 21504 Rev: E Amendment/+2
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Issue Date: June 4, 2004
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash Device erasure occurs by executing the erase com-
memory organized as 1,048,576 bytes or 524,288 mand sequence. This initiates the Embedded Erase
words. The device is offered in 44-pin SO, 48-pin algorithm—an internal algorithm that automatically
TSOP, and 48-ball FBGA packages. The device is also preprograms the array (if it is not already programmed)
available in Known Good Die (KGD) form. For more before executing the erase operation. During erase, the
information, refer to publication number 21631. The device automatically times the erase pulse widths and
word-wide data (x16) appears on DQ15–DQ0; the verifies proper cell margin.
byte-wide (x8) data appears on DQ7–DQ0. This device
The host system can detect whether a program or
is designed to be programmed in-system with the stan-
erase operation is complete by observing the RY/BY#
dard system 5.0 volt VCC supply. A 12.0 V VPP is not
pin, or by reading the DQ7 (Data# Polling) and DQ6
required for write or erase operations. The device can
(toggle) status bits. After a program or erase cycle has
also be programmed in standard EPROM program-
been completed, the device is ready to read array data
mers.
or accept another command.
This device is manufactured using AMD’s 0.32 µm
The sector erase architecture allows memory sectors
process technology, and offers all the features and ben-
to be erased and reprogrammed without affecting the
efits of the Am29F800, which was manufactured using
data contents of other sectors. The device is fully
0.5 µm process technology.
erased when shipped from the factory.
The standard device offers access times of 55, 70, 90,
Hardware data protection measures include a low
120, and 150 ns, allowing high speed microprocessors
VCC detector that automatically inhibits write opera-
to operate without wait states. To eliminate bus conten-
tions during power transitions. The hardware sector
tion the device has separate chip enable (CE#), write
protection feature disables both program and erase
enable (WE#) and output enable (OE#) controls.
operations in any combination of the sectors of mem-
The device requires only a single 5.0 volt power sup- ory. This can be achieved via programming equipment.
ply for both read and write functions. Internally gener-
The Erase Suspend feature enables the user to put
ated and regulated voltages are provided for the
program and erase operations. erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
The device is entirely command set compatible with the erasure. True background erase can thus be achieved.
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan- The hardware RESET# pin terminates any operation
dard microprocessor write timings. Register contents in progress and resets the internal state machine to
serve as input to an internal state-machine that con- reading array data. The RESET# pin may be tied to the
trols the erase and programming circuitry. Write cycles system reset circuitry. A system reset would thus also
also internally latch addresses and data needed for the reset the device, enabling the system microprocessor
programming and erase operations. Reading data out to read the boot-up firmware from the Flash memory.
of the device is similar to reading from other Flash or The system can place the device into the standby
EPROM devices. mode. Power consumption is greatly reduced in
Device programming occurs by executing the program this mode.
command sequence. This initiates the Embedded AMD’s Flash technology combines years of Flash
Program algorithm—an internal algorithm that auto- memory manufacturing experience to produce the
matically times the program pulse widths and verifies highest levels of quality, reliability and cost effective-
proper cell margin. ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
4 Am29F800B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7 TTL/NMOS Compatible .......................................................... 26
Special Handling Instructions for FBGA Package .................... 8 CMOS Compatible .................................................................. 27
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Test Setup....................................................................... 28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Test Specifications ........................................................... 28
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11 Key to Switching Waveforms. . . . . . . . . . . . . . . . 28
Table 1. Am29F800B Device Bus Operations ................................11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Word/Byte Configuration ........................................................ 11 Read Operations .................................................................... 29
Requirements for Reading Array Data ................................... 11 Figure 9. Read Operations Timings ............................................... 29
Writing Commands/Command Sequences ............................ 11 Hardware Reset (RESET#) .................................................... 30
Program and Erase Operation Status .................................... 12 Figure 10. RESET# Timings .......................................................... 30
Standby Mode ........................................................................ 12 Word/Byte Configuration (BYTE#) ........................................ 31
RESET#: Hardware Reset Pin ............................................... 12 Figure 11. BYTE# Timings for Read Operations............................ 31
Figure 12. BYTE# Timings for Write Operations............................ 31
Output Disable Mode .............................................................. 12
Table 2. Am29F800BT Top Boot Block Sector Address Table .......13
Erase/Program Operations ..................................................... 32
Table 3. Am29F800BB Bottom Boot Block Sector Address Table ..14 Figure 13. Program Operation Timings.......................................... 33
Figure 14. Chip/Sector Erase Operation Timings .......................... 34
Autoselect Mode ..................................................................... 14
Figure 15. Data# Polling Timings (During Embedded Algorithms). 35
Table 4. Am29F800B Autoselect Codes (High Voltage Method) ....15
Figure 16. Toggle Bit Timings (During Embedded Algorithms)...... 35
Sector Protection/Unprotection ............................................... 15
Figure 17. DQ2 vs. DQ6................................................................. 36
Temporary Sector Unprotect .................................................. 15 Temporary Sector Unprotect .................................................. 36
Figure 1. Temporary Sector Unprotect Operation........................... 15
Figure 18. Temporary Sector Unprotect Timing Diagram .............. 36
Hardware Data Protection ...................................................... 16 Figure 19. Alternate CE# Controlled Write Operation Timings ...... 38
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 16 Erase and Programming Performance . . . . . . . 39
Reading Array Data ................................................................ 16 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39
Reset Command ..................................................................... 16 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39
Autoselect Command Sequence ............................................ 17 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Word/Byte Program Command Sequence ............................. 17 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
Figure 2. Program Operation .......................................................... 17
SO 044—44-Pin Small Outline Package ................................ 40
Chip Erase Command Sequence ........................................... 17 TS 048—48-Pin Standard Pinout Thin Small
Sector Erase Command Sequence ........................................ 18 Outline Package (TSOP) ........................................................ 41
Erase Suspend/Erase Resume Commands ........................... 18 TSR048—48-Pin Reverse Pinout Thin Small
Figure 3. Erase Operation............................................................... 19
Outline Package (TSOP) ........................................................ 42
Command Definitions ............................................................. 20
FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm
Table 5. Am29F800B Command Definitions ...................................20
package .................................................................................. 43
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 21
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
DQ7: Data# Polling ................................................................. 21
Figure 4. Data# Polling Algorithm ................................................... 21 Revision A (August 1997) ....................................................... 44
RY/BY#: Ready/Busy# ........................................................... 22 Revision B (October 1997) ..................................................... 44
DQ6: Toggle Bit I .................................................................... 22 Revision C (January 1998) ..................................................... 44
DQ2: Toggle Bit II ................................................................... 22 Revision C+1 (April 1998) ....................................................... 44
Reading Toggle Bits DQ6/DQ2 .............................................. 22 Revision C+2 (April 1998) ....................................................... 44
DQ5: Exceeded Timing Limits ................................................ 23 Revision D (January 1999) ..................................................... 45
DQ3: Sector Erase Timer ....................................................... 23 Revision D+1 (March 23, 1999) .............................................. 45
Figure 5. Toggle Bit Algorithm......................................................... 23 Revision D+2 (July 2, 1999) ................................................... 45
Table 6. Write Operation Status ......................................................24 Revision E (November 16, 1999) ............................................ 45
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 25 Revision E+1 (August 4, 2000) ............................................... 45
Figure 6. Maximum Negative Overshoot Waveform ....................... 25 Revision E+2 (May 26, 2004) ................................................. 45
Figure 7. Maximum Positive Overshoot Waveform......................... 25
Am29F800B 5
PRODUCT SELECTOR GUIDE
Family Part Number Am29F800B
Speed Option VCC = 5.0 V ± 10% -55 -70 -90 -120 -150
Max access time, ns (tACC) 55 70 90 120 150
Max CE# access time, ns (tCE) 55 70 90 120 150
Max OE# access time, ns (tOE) 30 30 35 50 55
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY# DQ0–DQ15 (A-1)
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers
WE# State
Control
BYTE#
Command
Register
PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
Logic
OE#
Y-Decoder Y-Gating
STB
Address Latch
VCC Detector Timer
X-Decoder Cell Matrix
A0–A18
6 Am29F800B
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for
more information.
A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
NC 9 40 DQ5
NC 10 39 DQ12
WE# 11 38 DQ4
RESET# 12 48-Pin TSOP—Standard Pinout 37 VCC
NC 13 36 DQ11
NC 14 35 DQ3
RY/BY# 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0
A16 1 48 A15
BYTE# 2 47 A14
VSS 3 46 A13
DQ15/A-1 4 45 A12
DQ7 5 44 A11
DQ14 6 43 A10
DQ6 7 42 A9
DQ13 8 41 A8
DQ5 9 40 NC
DQ12 10 39 NC
DQ4 11 38 WE#
VCC 12 48-Pin TSOP—Reverse Pinout 37 RESET#
DQ11 13 36 NC
DQ3 14 35 NC
DQ10 15 34 RY/BY#
DQ2 16 33 A18
DQ9 17 32 A17
DQ1 18 31 A7
DQ8 19 30 A6
DQ0 20 29 A5
OE# 21 28 A4
VSS 22 27 A3
CE# 23 26 A2
A0 24 25 A1
Am29F800B 7
CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for
more information.
RY/BY# 1 44 RESET#
A18 2 43 WE#
A17 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 SO 34 A16
CE# 12 33 BYTE#
VSS 13 32 VSS
OE# 14 31 DQ15/A-1
DQ0 15 30 DQ7
DQ8 16 29 DQ14
DQ1 17 28 DQ6
DQ9 18 27 DQ13
DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC
FBGA
Top View, Balls Facing Down
A6 B6 C6 D6 E6 F6 G6 H6
A13 A12 A14 A15 A16 BYTE# DQ15/A-1 VSS
A5 B5 C5 D5 E5 F5 G5 H5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
A4 B4 C4 D4 E4 F4 G4 H4
WE# RESET# NC NC DQ5 DQ12 VCC DQ4
A3 B3 C3 D3 E3 F3 G3 H3
RY/BY# NC A18 NC DQ2 DQ10 DQ11 DQ3
A2 B2 C2 D2 E2 F2 G2 H2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A1 B1 C1 D1 E1 F1 G1 H1
A3 A4 A2 A1 A0 CE# OE# VSS
Special Handling Instructions for FBGA Flash memory devices in FBGA packages may be
Package damaged if exposed to ultrasonic cleaning methods.
T he package an d/or data integr ity may be
Special handling is required for Flash Memory products compromised if the package body is exposed to
in FBGA packages. temperatures above 150°C for prolonged periods of
time.
8 Am29F800B
PIN CONFIGURATION LOGIC SYMBOL
A0–A18 = 19 addresses
DQ0–DQ14 = 15 data inputs/outputs 19
A0–A18 16 or 8
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode) DQ0–DQ15
(A-1)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable CE#
OE# = Output enable OE#
WE# = Write enable WE#
RESET# = Hardware reset pin, active low RESET#
RY/BY# = Ready/Busy# output BYTE# RY/BY#
VCC = +5.0 V single power supply

(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS = Device ground
NC = Pin not connected internally
Am29F800B 9
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F800B T -70 E C
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
D = Commercial (0°C to +70°C) with Pb-Free Package
I = Industrial (–40°C to +85°C)
F = Industrial (–40°C to +85°C) with Pb-Free Package
E = Extended (–55°C to +125°C)
K = Extended (–55°C to +125°C) with Pb-Free Package
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
WB = 48-Ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 9 mm package (FBB048)
This device is also available in Known Good Die (KGD) form. See publication number
21536 for more information.
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE

T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F800B
8 Megabit (1 M x 8-Bit/512K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program and Erase
Valid Combinations Valid Combinations for FBGA Packages
AM29F800BT-55, Order Number Package Marking

AM29F800BB-55
AM29F800BT-55, F800BT55V,
AM29F800BT-70, AM29F800BB-55 F800BB55V
AM29F800BB-70
AM29F800BT-70, F800BT70V,
EC, EI, EE, ED, EF, EK WBC,
AM29F800BT-90, AM29F800BB-70 F800BB70V
FC, FI, FE, WBI,
AM29F800BB-90
SC, SI, SE, SD, SF, SK AM29F800BT-90, WBE, F800BT90V, C, I, E,
AM29F800BT-120, AM29F800BB-90 WBD, F800BB90V D, F, K
AM29F800BB-120 WBF,
AM29F800BT-120, WBK F800BT12V,
AM29F800BT-150, AM29F800BB-120 F800BB12V
AM29F800BB-150
AM29F800BT-150, F800BT15V,
AM29F800BB-150 F800BB15V
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
10 Am29F800B
DEVICE BUS OPERATIONS
This section describes the requirements and use of the the register serve as inputs to the internal state ma-
device bus operations, which are initiated through the chine. The state machine outputs dictate the function of
internal command register. The command register it- the device. The appropriate device bus operations
self does not occupy any addressable memory loca- table lists the inputs and control levels required, and the
tion. The register is composed of latches that store the resulting output. The following subsections describe
commands, along with the address and data informa- each of these operations in further detail.
tion needed to execute the command. The contents of
Table 1. Am29F800B Device Bus Operations

DQ8–DQ15
BYTE# BYTE#
Operation CE# OE# WE# RESET# A0–A18 DQ0–DQ7 = VIH = VIL
Read L L H H AIN DOUT DOUT High-Z
Write L H L H AIN DIN DIN High-Z
CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect

X X X VID AIN DIN DIN X
(See Note)
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-
The BYTE# pin controls whether the device data I/O
sert valid addresses on the device address inputs
pins DQ15–DQ0 operate in the byte or word configura-
produce valid data on the device data outputs. The
tion. If the BYTE# pin is set at logic ‘1’, the device is in
device remains enabled for read access until the
word configuration, DQ15–DQ0 are active and con-
command register contents are altered.
trolled by CE# and OE#.
See “Reading Array Data” for more information. Refer
If the BYTE# pin is set at logic ‘0’, the device is in byte
to the AC Read Operations table for timing specifica-
configuration, and only data I/O pins DQ0–DQ7 are ac-
tions and to the Read Operations Timings diagram for
tive and controlled by CE# and OE#. The data I/O pins the timing waveforms. ICC1 in the DC Characteristics
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
table represents the active current specification for
an input for the LSB (A-1) address function.
reading array data.
Requirements for Reading Array Data Writing Commands/Command Sequences
To read array data from the outputs, the system must To write a command or command sequence (which in-
drive the CE# and OE# pins to VIL. CE# is the power cludes programming data to the device and erasing
control and selects the device. OE# is the output control sectors of memory), the system must drive WE# and
and gates array data to the output pins. WE# should re- CE# to VIL, and OE# to VIH.
main at VIH.
An erase operation can erase one sector, multiple sec-
The internal state machine is set for reading array tors, or the entire device. The Sector Address Tables in-
data upon device power-up, or after a hardware reset. dicate the address space that each sector occupies. A
This ensures that no spurious alteration of the mem- “sector address” consists of the address bits required
ory content occurs during the power transition. No to uniquely select a sector. See the “Command Defini-
Am29F800B 11
tions” section for details on erasing a sector or the en- In the DC Characteristics tables, ICC3 represents the
tire chip, or suspending/resuming the erase operation. standby current specification.
After the system writes the autoselect command se-
RESET#: Hardware Reset Pin
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter- The RESET# pin provides a hardware method of reset-
nal register (which is separate from the memory array) ting the device to reading array data. When the system
on DQ7–DQ0. Standard read cycle timings apply in this drives the RESET# pin low for at least a period of tRP,
mode. Refer to the “Autoselect Mode” and “Autoselect the device immediately terminates any operation in
Command Sequence” sections for more information. progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
ICC2 in the DC Characteristics table represents the ac- pulse. The device also resets the internal state ma-
tive current specification for the write mode. The “AC chine to reading array data. The operation that was in-
Characteristics” section contains timing specification terrupted should be reinitiated once the device is ready
tables and timing diagrams for write operations. to accept another command sequence, to ensure data
integrity.
Program and Erase Operation Status
Current is reduced for the duration of the RESET#
During an erase or program operation, the system may
pulse. When RESET# is held at VIL, the device enters
check the status of the operation by reading the status
the TTL standby mode; if RESET# is held at VSS ±
bits on DQ7–DQ0. Standard read cycle timings and ICC
0.5 V, the device enters the CMOS standby mode.
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac- The RESET# pin may be tied to the system reset cir-
teristics section for timing diagrams. cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
Standby Mode ware from the Flash memory.
When the system is not reading or writing to the device, If RESET# is asserted during a program or erase oper-
it can place the device in the standby mode. In this ation, the RY/BY# pin remains a “0” (busy) until the in-
mode, current consumption is greatly reduced, and the ternal reset operation is complete, which requires a
outputs are placed in the high impedance state, inde- time of tREADY (during Embedded Algorithms). The
pendent of the OE# input. system can thus monitor RY/BY# to determine whether
The device enters the CMOS standby mode when CE# the reset operation is complete. If RESET# is asserted
and RESET# pins are both held at VCC ± 0.5 V. (Note when a program or erase operation is not executing
that this is a more restricted voltage range than VIH.) (RY/BY# pin is “1”), the reset operation is completed
The device enters the TTL standby mode when CE# within a time of tREADY (not during Embedded Algo-
and RESET# pins are both held at VIH. The device re- rithms). The system can read data tRH after the RE-
quires standard access time (tCE) for read access when SET# pin returns to VIH.
the device is in either of these standby modes, before it Refer to the AC Characteristics tables for RESET# pa-
is ready to read data. rameters and timing diagram.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, “RE- Output Disable Mode
SET#: Hardware Reset Pin”. When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
If the device is deselected during erasure or program-
ance state.
ming, the device draws active current until the
operation is completed.
12 Am29F800B
Table 2. Am29F800BT Top Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/ (x16) (x8)
Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range
SA0 0 0 0 0 X X X 64/32 00000h–07FFFh 00000h–0FFFFh
SA1 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh
SA10 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh
SA11 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh
SA12 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh
SA13 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh
SA14 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh
SA15 1 1 1 1 0 X X 32/16 78000h–7BFFFh F0000h–F7FFFh
SA16 1 1 1 1 1 0 0 8/4 7C000h–7CFFFh F8000h–F9FFFh
SA17 1 1 1 1 1 0 1 8/4 7D000h–7DFFFh FA000h–FBFFFh
SA18 1 1 1 1 1 1 X 16/8 7E000h–7FFFFh FC000h–FFFFFh
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See the “Word/Byte Configuration” section for more
information.
Am29F800B 13
Table 3. Am29F800BB Bottom Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/ (x16) (x8)
Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range
SA0 0 0 0 0 0 0 X 16/8 00000h–01FFFh 00000h–03FFFh
SA1 0 0 0 0 0 1 0 8/4 02000h–02FFFh 04000h–05FFFh
SA2 0 0 0 0 0 1 1 8/4 03000h–03FFFh 06000h–07FFFh
SA3 0 0 0 0 1 X X 32/16 04000h–07FFFh 08000h–0FFFFh
SA13 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh
SA14 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh
SA15 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh
SA16 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh
SA17 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh
SA18 1 1 1 1 X X X 64/32 78000h–7FFFFh F0000h–FFFFFh
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See the “Word/Byte Configuration” sectionfor more
information.
Autoselect Mode
The autoselect mode provides manufacturer and de- dress must appear on the appropriate highest order
vice identification, and sector protection verification, address bits. Refer to the corresponding Sector Ad-
through identifier codes output on DQ7–DQ0. This dress Tables. The Command Definitions table shows
mode is primarily intended for programming equipment the remaining address bits that are don’t care. When all
to automatically match a device to be programmed with necessary bits have been set as required, the program-
its corresponding programming algorithm. However, ming equipment may then read the corresponding
the autoselect codes can also be accessed in-system identifier code on DQ7–DQ0.
through the command register.
To access the autoselect codes in-system, the host
When using programming equipment, the autoselect system can issue the autoselect command via the
mode requires VID (11.5 V to 12.5 V) on address pin command register, as shown in the Command Defini-
A9. Address pins A6, A1, and A0 must be as shown in tions table. This method does not require V ID. See
Autoselect Codes (High Voltage Method) table. In addi- “Command Definitions” for details on using the autose-
tion, when verifying sector protection, the sector ad- lect mode.
14 Am29F800B
Table 4. Am29F800B Autoselect Codes (High Voltage Method)
A18 A11 A8 A5 DQ8 DQ7
to to to to to to
Description Mode CE# OE# WE# A12 A10 A9 A7 A6 A2 A1 A0 DQ15 DQ0
Manufacturer ID: AMD L L H X X VID X L X L L X 01h
Device ID: Word L L H 22h D6h

Am29F800B X X VID X L X L H
(Top Boot Block) Byte L L H X D6h
Device ID: Word L L H 22h 58h

Am29F800B X X VID X L X L H
(Bottom Boot Block) Byte L L H X 58h
01h
X
(protected)
Sector Protection Verification L L H SA X VID X L X H L
00h
X
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
The hardware sector protection feature disables both
shows the timing waveforms, for this feature.
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro-
tected sectors. START
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
RESET# = VID
quires a high voltage (VID) on address pin A9 and the
(Note 1)
control pins. Details on this method are provided in a
supplement, publication number 20374. Contact an
AMD representative to obtain a copy of the appropriate Perform Erase or
Program Operations
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting RESET# = VIH
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details. Temporary Sector
It is possible to determine whether a sector is protected Unprotect
Completed (Note 2)
or unprotected. See “Autoselect Mode” for details.

This feature allows temporary unprotection of previ-
Notes:
ously protected sectors to change data in-system. 1. All protected sectors unprotected.
The Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly pro- 2. All previously protected sectors are protected once
again.
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once VID is removed
Figure 1. Temporary Sector Unprotect Operation
from the RESET# pin, all the previously protected
Am29F800B 15
Hardware Data Protection proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection Write Pulse “Glitch” Protection
against inadvertent writes (refer to the Command Defi- Noise pulses of less than 5 ns (typical) on OE#, CE# or
nitions table). In addition, the following hardware data WE# do not initiate a write cycle.
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri- Logical Inhibit
ous system level signals during V CC power-up and Write cycles are inhibited by holding any one of OE# =
power-down transitions, or from system noise. VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
Low VCC Write Inhibit CE# and WE# must be a logical zero while OE# is a
logical one.
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC Power-Up Write Inhibit
power-up and power-down. The command register and If WE# = CE# = VIL and OE# = VIH during power up, the
all internal program/erase circuits are disabled, and the device does not accept commands on the rising edge
device resets. Subsequent writes are ignored until VCC of WE#. The internal state machine is automatically
is greater than V LKO. The system must provide the reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se- See also “Requirements for Reading Array Data” in the
quences into the command register initiates device op- “Device Bus Operations” section for more information.
erations. The Command Definitions table defines the The Read Operations table provides the read parame-
valid register command sequences. Writing incorrect ters, and Read Operation Timings diagram shows the
address and data values or writing them in the im- timing diagram.
proper sequence resets the device to reading array
data. Reset Command
All addresses are latched on the falling edge of WE# or Writing the reset command to the device resets the de-
CE#, whichever happens later. All data is latched on vice to reading array data. Address bits are don’t care
the rising edge of WE# or CE#, whichever happens for this command.
first. Refer to the appropriate timing diagrams in the The reset command may be written between the se-
“AC Characteristics” section. quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
Reading Array Data data. Once erasure begins, however, the device ig-
The device is automatically set to reading array data nores reset commands until the operation is complete.
after device power-up. No commands are required to
The reset command may be written between the se-
retrieve data. The device is also ready to read array
quence cycles in a program command sequence be-
data after completing an Embedded Program or Em-
fore programming begins. This resets the device to
bedded Erase algorithm.
reading array data (also applies to programming in
After the device accepts an Erase Suspend command, Erase Suspend mode). Once programming begins,
the device enters the Erase Suspend mode. The sys- however, the device ignores reset commands until the
tem can read array data using the standard read tim- operation is complete.
ings, except that if it reads at an address within erase-
The reset command may be written between the se-
suspended sectors, the device outputs status data.
quence cycles in an autoselect command sequence.
After completing a programming operation in the Erase
Once in the autoselect mode, the reset command must
Suspend mode, the system may once again read array
be written to return to reading array data (also applies
data with the same exception. See “Erase Sus-
to autoselect during Erase Suspend).
pend/Erase Resume Commands” for more information
on this mode. If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
The system must issue the reset command to re-en-
ing array data (also applies during Erase Suspend).
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
16 Am29F800B
Autoselect Command Sequence from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
The autoselect command sequence allows the host
Polling algorithm to indicate the operation was suc-
system to access the manufacturer and devices codes,
cessful. However, a succeeding read will show that the
and determine whether or not a sector is protected.
data is still “0”. Only erase operations can convert a “0”
The Command Definitions table shows the address
to a “1”.
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9. START
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any Write Program
Command Sequence
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manu-
Data Poll
facturer code. A read cycle at address XX01h in word from System
mode (or 02h in byte mode) returns the device code. Embedded
A read cycle containing a sector address (SA) and the Program
algorithm
address 02h in word mode (or 04h in byte mode) re-
in progress
turns 01h if that sector is protected, or 00h if it is un-
protected. Refer to the Sector Address tables for valid Verify Data?
No
sector addresses.
The system must write the reset command to exit the Yes
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence No

Increment Address Last Address?
The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Program-
Yes
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
Programming
cycles, followed by the program set-up command. The Completed
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim- Note: See the appropriate Command Definitions table for
ings. The device automatically provides internally gen- program command sequence.
erated program pulses and verify the programmed cell
margin. The Command Definitions take shows the ad- Figure 2. Program Operation
dress and data requirements for the byte program com-
mand sequence.
When the Embedded Program algorithm is complete, Chip Erase Command Sequence
the device then returns to reading array data and ad- Chip erase is a six-bus-cycle operation. The chip erase
dresses are no longer latched. The system can deter- command sequence is initiated by writing two unlock
mine the status of the program operation by using DQ7, cycles, followed by a set-up command. Two additional
DQ6, or RY/BY#. See “Write Operation Status” for in- unlock write cycles are then followed by the chip erase
formation on these status bits. command, which in turn invokes the Embedded Erase
Any commands written to the device during the Em- algorithm. The device does not require the system to
bedded Program Algorithm are ignored. Note that a preprogram prior to erase. The Embedded Erase algo-
hardware reset immediately terminates the program- rithm automatically preprograms and verifies the entire
ming operation. The program command sequence memory for an all zero data pattern prior to electrical
should be reinitiated once the device has reset to read- erase. The system is not required to provide any con-
ing array data, to ensure data integrity. trols or timings during these operations. The Command
Definitions table shows the address and data require-
Programming is allowed in any sequence and across ments for the chip erase command sequence.
sector boundaries. A bit cannot be programmed
Am29F800B 17
Any commands written to the chip during the Embed- Once the sector erase operation has begun, only the
ded Erase algorithm are ignored. Note that a hardware Erase Suspend command is valid. All other commands
reset during the chip erase operation immediately ter- are ignored. Note that a hardware reset during the
minates the operation. The Chip Erase command se- sector erase operation immediately terminates the op-
quence should be reinitiated once the device has eration. The Sector Erase command sequence should
returned to reading array data, to ensure data integrity. be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See When the Embedded Erase algorithm is complete, the
“Write Operation Status” for information on these device returns to reading array data and addresses are
status bits. When the Embedded Erase algorithm is no longer latched. The system can determine the sta-
complete, the device returns to reading array data tus of the erase operation by using DQ7, DQ6, DQ2, or
and addresses are no longer latched. RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC Figure 3 illustrates the algorithm for the erase opera-
Characteristics” for parameters, and to the Chip/Sector tion. Refer to the Erase/Program Operations tables in
Erase Operation Timings for timing waveforms. the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
Sector Erase Command Sequence waveforms.
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un- Erase Suspend/Erase Resume Commands
lock cycles, followed by a set-up command. Two addi- The Erase Suspend command allows the system to in-
tional unlock write cycles are then followed by the terrupt a sector erase operation and then read data
address of the sector to be erased, and the sector from, or program data to, any sector not selected for
erase command. The Command Definitions table erasure. This command is valid only during the sector
shows the address and data requirements for the sec- erase operation, including the 50 µs time-out period
tor erase command sequence. during the sector erase command sequence. The
Erase Suspend command is ignored if written during
The device does not require the system to preprogram
the chip erase operation or Embedded Program algo-
the memory prior to erase. The Embedded Erase algo-
rithm. Writing the Erase Suspend command during the
rithm automatically programs and verifies the sector for
Sector Erase time-out immediately terminates the
an all zero data pattern prior to electrical erase. The
time-out period and suspends the erase operation. Ad-
system is not required to provide any controls or tim-
dresses are “don’t-cares” when writing the Erase Sus-
ings during these operations.
pend command.
After the command sequence is written, a sector erase
When the Erase Suspend command is written during a
time-out of 50 µs begins. During the time-out period,
sector erase operation, the device requires a maximum
additional sector addresses and sector erase com-
of 20 µs to suspend the erase operation. However,
mands may be written. Loading the sector erase buffer
when the Erase Suspend command is written during
may be done in any sequence, and the number of sec-
the sector erase time-out, the device immediately ter-
tors may be from one sector to all sectors. The time be-
minates the time-out period and suspends the erase
tween these additional cycles must be less than 50 µs,
operation.
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended After the erase operation has been suspended, the
that processor interrupts be disabled during this time to system can read array data from or program data to
ensure all commands are accepted. The interrupts can any sector not selected for erasure. (The device “erase
be re-enabled after the last Sector Erase command is suspends” all sectors selected for erasure.) Normal
written. If the time between additional sector erase read and write timings and command definitions apply.
commands can be assumed to be less than 50 µs, the Reading at any address within erase-suspended sec-
system need not monitor DQ3. Any command other tors produces status data on DQ7–DQ0. The system
than Sector Erase or Erase Suspend during the can use DQ7, or DQ6 and DQ2 together, to determine
time-out period resets the device to reading array if a sector is actively erasing or is erase-suspended.
data. The system must rewrite the command sequence See “Write Operation Status” for information on these
and any additional sector addresses and commands. status bits.
The system can monitor DQ3 to determine if the sector After an erase-suspended program operation is com-
erase timer has timed out. (See the “DQ3: Sector Erase plete, the system can once again read array data within
Timer” section.) The time-out begins from the rising non-suspended sectors. The system can determine
edge of the final WE# pulse in the command sequence. the status of the program operation using the DQ7 or
18 Am29F800B
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion. START
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the Write Erase
Command Sequence
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence” Data Poll
for more information. from System
Embedded
The system must write the Erase Resume command Erase
(address bits are “don’t care”) to exit the erase suspend algorithm
mode and continue the sector erase operation. Further in progress
writes of the Resume command are ignored. Another No
Data = FFh?
Erase Suspend command can be written after the de-
vice has resumed erasing.
Yes
Erasure Completed
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
Am29F800B 19
Command Definitions
Table 5. Am29F800B Command Definitions
Bus Cycles (Notes 2–5)
Cycle
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Word 555 2AA 555
Manufacturer ID 4 AA 55 90 X00 01
Byte AAA 555 AAA
Autoselect (Note 8)
Device ID, Word 555 2AA 555 X01 22D6

4 AA 55 90
Top Boot Block Byte AAA 555 AAA X02 D6
Device ID, Word 555 2AA 555 X01 2258
4 AA 55 90
Bottom Boot Block Byte AAA 555 AAA X02 58
(SA) XX00
Word 555 2AA 555
Sector Protect Verify X02 XX01
4 AA 55 90
(Note 9) (SA) 00
Byte AAA 555 AAA
X04 01
Word 555 2AA 555
Program 4 AA 55 A0 PA PD
Byte AAA 555 AAA
Word 555 2AA 555 555 2AA 555
Chip Erase 6 AA 55 80 AA 55 10
Byte AAA 555 AAA AAA 555 AAA
Word 555 2AA 555 555 2AA
Sector Erase 6 AA 55 80 AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 10) 1 XXX B0
Erase Resume (Note 11) 1 XXX 30
Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A12 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations. 8. The fourth cycle of the autoselect command sequence is a
2. All values are in hexadecimal. read cycle.
3. Except when reading array or autoselect data, all bus cycles 9. The data is 00h for an unprotected sector and 01h for a
are write operations. protected sector. See “Autoselect Command Sequence” See
“Autoselect Command Sequence” for more information.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles. 10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
5. Address bits A18–A11 are don’t cares for unlock and mode. The Erase Suspend command is valid only during a
command cycles, unless SA or PA required. sector erase operation.
6. No unlock or command cycles required when reading array data. 11. The Erase Resume command is valid only during the Erase
7. The Reset command is required to return to reading array Suspend mode.
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
20 Am29F800B
WRITE OPERATION STATUS
The device provides several bits to determine the sta- Table 6 shows the outputs for Data# Polling on DQ7.
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, Figure 4 shows the Data# Polling algorithm.
and RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress. START
These three bits are discussed first.
DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host Read DQ7–DQ0
sys tem whether an Embedded Algor ithm is in Addr = VA
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence. Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro- No
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system No DQ5 = 1?
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap- Yes
proximately 2 µs, then the device returns to reading
array data.
Read DQ7–DQ0
During the Embedded Erase algorithm, Data# Polling Addr = VA
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the Yes
DQ7 = Data?
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of No
the sectors selected for erasure to read valid status in-
formation on DQ7. PASS
FAIL
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
Notes:
on DQ7 is active for approximately 100 µs, then the de-
1. VA = Valid address for programming. During a sector
vice returns to reading array data. If not all selected erase operation, a valid address is an address within any
sectors are protected, the Embedded Erase algorithm sector selected for erasure. During chip erase, a valid
erases the unprotected sectors, and ignores the se- address is any non-protected sector address.
lected sectors that are protected.
2. DQ7 should be rechecked even if DQ5 = “1” because
When the system detects DQ7 has changed from the DQ7 may change simultaneously with DQ5.
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7 Figure 4. Data# Polling Algorithm
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Am29F800B 21
RY/BY#: Ready/Busy# The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
The RY/BY# is a dedicated, open-drain output pin that
algorithm, and to the Toggle Bit Timings figure in the
indicates whether an Embedded Algorithm is in
“AC Characteristics” section for the timing diagram.
progress or complete. The RY/BY# status is valid after
The DQ2 vs. DQ6 figure shows the differences be-
the rising edge of the final WE# pulse in the command
tween DQ2 and DQ6 in graphical form. See also the
sequence. Since RY/BY# is an open-drain output, sev-
subsection on “DQ2: Toggle Bit II”.
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing The “Toggle Bit II” on DQ2, when used with DQ6, indi-
or programming. (This includes programming in the cates whether a particular sector is actively erasing
Erase Suspend mode.) If the output is high (Ready), (that is, the Embedded Erase algorithm is in progress),
the device is ready to read array data (including during or whether that sector is erase-suspended. Toggle Bit
the Erase Suspend mode), or is in the standby mode. II is valid after the rising edge of the final WE# pulse in
Table 6 shows the outputs for RY/BY#. The timing dia- the command sequence.
grams for read, reset, program, and erase shows the DQ2 toggles when the system reads at addresses
relationship of RY/BY# to other signals. within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
DQ6: Toggle Bit I trol the read cycles.) But DQ2 cannot distinguish
Toggle Bit I on DQ6 indicates whether an Embedded whether the sector is actively erasing or is erase-sus-
Program or Erase algorithm is in progress or complete, pended. DQ6, by comparison, indicates whether the
or whether the device has entered the Erase Suspend device is actively erasing, or is in Erase Suspend, but
mode. Toggle Bit I may be read at any address, and is cannot distinguish which sectors are selected for era-
valid after the rising edge of the final WE# pulse in the sure. Thus, both status bits are required for sector and
command sequence (prior to the program or erase op- mode information. Refer to Table 6 to compare outputs
eration), and during the sector erase time-out. for DQ2 and DQ6.
During an Embedded Program or Erase algorithm op- Figure 5 shows the toggle bit algorithm in flowchart
eration, successive read cycles to any address cause form, and the section “DQ2: Toggle Bit II” explains the
DQ6 to toggle. (The system may use either OE# or algorithm. See also the “DQ6: Toggle Bit I” subsection.
CE# to control the read cycles.) When the operation is Refer to the Toggle Bit Timings figure for the toggle bit
complete, DQ6 stops toggling. timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
Reading Toggle Bits DQ6/DQ2
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, Refer to Figure 5 for the following discussion. When-
the Embedded Erase algorithm erases the unpro- ever the system initially begins reading toggle bit sta-
tected sectors, and ignores the selected sectors that tus, it must read DQ7–DQ0 at least twice in a row to
are protected. determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
The system can use DQ6 and DQ2 together to deter- after the first read. After the second read, the system
mine whether a sector is actively erasing or is erase- would compare the new value of the toggle bit with the
suspended. When the device is actively erasing (that is, first. If the toggle bit is not toggling, the device has
the Embedded Erase algorithm is in progress), DQ6 completed the program or erase operation. The sys-
toggles. When the device enters the Erase Suspend tem can read array data on DQ7–DQ0 on the following
mode, DQ6 stops toggling. However, the system must read cycle.
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use However, if after the initial two read cycles, the system
DQ7 (see the subsection on “DQ7: Data# Polling”). determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
If a program address falls within a protected sector, high (see the section on DQ5). If it is, the system
DQ6 toggles for approximately 2 µs after the program should then determine again whether the toggle bit is
command sequence is written, then returns to reading toggling, since the toggle bit may have stopped tog-
array data. gling just as DQ5 went high. If the toggle bit is no longer
DQ6 also toggles during the erase-suspend-program toggling, the device has successfully completed the
mode, and stops toggling once the Embedded Pro- program or erase operation. If it is still toggling, the
gram algorithm is complete. device did not complete the operation successfully, and
22 Am29F800B
the system must write the reset command to return to erase command. If DQ3 is high on the second status
reading array data. check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other START
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
Read DQ7–DQ0
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
Read DQ7–DQ0 (Note 1)
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system Toggle Bit No
tries to program a “1” to a location that is previously pro- = Toggle?
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device Yes
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the No DQ5 = 1?
reset command to return the device to reading array
data.
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the Read DQ7–DQ0 (Notes
system may read DQ3 to determine whether or not an Twice 1, 2)
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase Toggle Bit No
command. When the time-out is complete, DQ3 = Toggle?
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad- Yes
ditional sector erase commands will always be less
Program/Erase
than 50 µs. See also the “Sector Erase Command Se-
Operation Not Program/Erase
quence” section.
Complete, Write Operation Complete
After the sector erase command sequence is written, Reset Command
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac- Notes:
1. Read toggle bit twice to determine whether or not it is
cepted the command sequence, and then read DQ3. If
toggling. See text.
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend) 2. Recheck toggle bit because it may stop toggling as DQ5
are ignored until the erase operation is complete. If changes to “1”. See text.
DQ3 is “0”, the device will accept additional sector Figure 5. Toggle Bit Algorithm
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
Am29F800B 23
Table 6. Write Operation Status
DQ7 DQ5 DQ2
Operation (Note 1) DQ6 (Note 2) DQ3 (Note 1) RY/BY#
Standard Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase
1 No toggle 0 N/A Toggle 1
Erase Suspended Sector
Suspend Reading within Non-Erase
Data Data Data Data Data 1
Mode Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
24 Am29F800B
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature 20 ns 20 ns
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground +0.8 V
VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V –0.5 V

A9, OE#, and
–2.0 V
RESET# (Note 2). . . . . . . . . . . . –2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . . –0.5 V to +7.0 V 20 ns
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Figure 6. Maximum Negative
Notes: Overshoot Waveform
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot 20 ns
to VCC +2.0 V for periods up to 20 ns. See Figure 7.
VCC
2. Minimum DC input voltage on pins A9, OE#, and RESET# +2.0 V
is –0.5 V. During voltage transitions, A9, OE#, and VCC
RESET# may undershoot VSS to –2.0 V for periods of up +0.5 V
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods 2.0 V
up to 20 ns.
20 ns 20 ns
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
Figure 7. Maximum Positive
than one second.
Overshoot Waveform
Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . .+4.5 V to +5.5 V
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
Am29F800B 25
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
VCC = VCC max;

ILIT A9, OE#, RESET Input Load Current 35 µA
A9 = OE# = RESET# = 12.5 V
ILO Output Leakage Current VOUT = VSS to VCC ±1.0 µA
CE# = VIL, OE# = VIH,

19 40 mA
f = 5 MHz, Byte Mode
VCC Active Read Current
ICC1
(Notes 1, 2) CE# = VIL, OE# = VIH,
19 50 mA
f = 5 MHz, Word Mode
VCC Active Write Current
ICC2 CE# = VIL, OE# = VIH 36 60 mA
(Notes 2, 3 and 4)
ICC3 VCC Standby Current (Notes 2, 5) CE#, OE#, and RESET# = VIH, 0.4 1 mA
VIL Input Low Voltage –0.5 0.8 V
VCC
VIH Input High Voltage 2.0 V
+ 0.5
Voltage for Autoselect and Temporary

VID VCC = 5.0 V 11.5 12.5 V
Sector Unprotect
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V
VLKO Low VCC Lock-Out Voltage (Note 4) 3.2 4.2 V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifcations are tested with VCC = VCCmax
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. ICC3 = 20 µA max at extended temperature (>+85°C)
26 Am29F800B
DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
VIN = VSS to VCC,

ILI Input Load Current ±1.0 µA
VCC = VCC max
A9, OE#, RESET Input Load VCC = VCC max,

ILIT 35 µA
Current A9 = OE# = RESET = 12.5 V
VOUT = VSS to VCC,

ILO Output Leakage Current ±1.0 µA
VCC = VCC max
CE# = VIL, OE# = VIH,

f = 5 MHz 20 40 mA
VCC Active Read Current Byte Mode
ICC1
(Note 2) CE# = VIL, OE# = VIH,
f = 5 MHz 28 50 mA
Word Mode
VCC Active Write Current

ICC2 CE# = VIL, OE# = VIH 30 50 mA
(Notes 1, 2, 3)
CE# and RESET# = VCC±0.5 V,

ICC3 VCC Standby Current (Note 2) 0.3 5 µA
OE# = VIH
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
Voltage for Autoselect and

VID VCC = 5.0 V 11.5 12.5 V
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
VOH1 IOH = –2.5 mA, VCC = VCC min 0.85 VCC V

Output High Voltage
VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 V
Low VCC Lock-Out Voltage

VLKO 3.2 4.2 V
(Note 3)
Notes:
1. ICC active while Embedded Erase or Embedded Program is in progress.
2. Maximum ICC specifcations are tested with VCC = VCCmax
3. Not 100% tested.
Am29F800B 27
TEST CONDITIONS
Table 7. Test Specifications
5.0 V
All
Test Condition -55 others Unit
2.7 kΩ
Device Output Load 1 TTL gate
Under
Test Output Load Capacitance, CL
30 100 pF
(including jig capacitance)
CL 6.2 kΩ
Input Rise and Fall Times 5 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement

1.5 0.8, 2.0 V
reference levels
Note:
Diodes are IN3064 or equivalents. Output timing measurement
1.5 0.8, 2.0 V
reference levels
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
28 Am29F800B
AC CHARACTERISTICS
Read Operations
Parameter Speed Options
JEDEC Std Description Test Setup -55 -70 -90 -120 -150 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 150 ns
CE# = VIL
tAVQV tACC Address to Output Delay Max 55 70 90 120 150 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 ns
tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 55 ns
Chip Enable to Output High Z (Note

tEHQZ tDF Max 20 20 20 30 35 ns
1)
Output Enable to Output High Z

tGHQZ tDF Max 20 20 20 30 35 ns
(Note 1)
Output Enable Read Min 0 ns

tOEH Hold Time Toggle and
(Note 1) Min 10 ns
Data# Polling
Output Hold Time From Addresses,

tAXQX tOH CE# or OE#, Whichever Occurs Min 0 ns
First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
tRC
Addresses Addresses Stable

tACC
CE#
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
RY/BY#
0V
Figure 9. Read Operations Timings
Am29F800B 29
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC Std Description Test Setup All Speed Options Unit
RESET# Pin Low (During Embedded

tREADY Max 20 µs
Algorithms) to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded

tREADY Max 500 ns
Algorithms) to Read or Write (See Note)
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRB RY/BY# Recovery Time Min 0 ns
Note:
Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 10. RESET# Timings
30 Am29F800B
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
JEDEC Std Description -55 -70 -90 -120 -150 Unit
tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns
tFLQZ BYTE# Switching Low to Output HIGH Z Max 20 20 20 30 35 ns
tFHQV BYTE# Switching High to Output Active Min 55 70 90 120 150 ns
CE#
OE#
BYTE#
tELFL
BYTE# DQ0–DQ14 Data Output Data Output
Switching (DQ0–DQ14) (DQ0–DQ7)
from word
to byte
mode DQ15/A-1 DQ15 Address
Output Input
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte DQ0–DQ14 Data Output Data Output
to word (DQ0–DQ7) (DQ0–DQ14)
mode
DQ15/A-1 Address DQ15
Input Output
tFHQV
Figure 11. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal

WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 12. BYTE# Timings for Write Operations
Am29F800B 31
AC CHARACTERISTICS
Erase/Program Operations
tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 45 50 50 ns
tDVWH tDS Data Setup Time Min 25 30 45 50 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHWL tGHWL Min 0 ns
(OE# High to WE# Low)
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 30 35 45 50 50 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
Byte Typ 7
tWHWH1 tWHWH1 Programming Operation (Note 2) µs
Word Typ 12
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Min 30 30 35 50 55 ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
32 Am29F800B
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
Data A0h PD Status DOUT
tBUSY tRB
RY/BY#
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 13. Program Operation Timings
Am29F800B 33
AC CHARACTERISTICS
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
10 for Chip Erase
tBUSY tRB
RY/BY#
tVCS
VCC
Note: SA = Sector Address. VA = Valid Address for reading status data.

Figure 14. Chip/Sector Erase Operation Timings
34 Am29F800B
AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0–DQ6 Status Data Status Data True Valid Data
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 15. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 16. Toggle Bit Timings (During Embedded Algorithms)
Am29F800B 35
AC CHARACTERISTICS
Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
WE# Erase Erase Suspend Erase Erase Suspend Erase Erase
Read Suspend Read Complete
Program
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.
Figure 17. DQ2 vs. DQ6

Parameter
JEDEC Std Description All Speed Options Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
RESET# Setup Time for Temporary Sector

tRSP Min 4 µs
Unprotect
Note: Not 100% tested.
12 V
RESET#
0 or 5 V 0 or 5 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 18. Temporary Sector Unprotect Timing Diagram
36 Am29F800B
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 45 50 50 ns
tDVEH tDS Data Setup Time Min 25 30 45 50 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHEL tGHEL Min 0 ns
(OE# High to WE# Low)
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 30 35 45 50 50 ns
tEHEL tCPH CE# Pulse Width High Min 20 ns
Programming Operation Byte Typ 7

tWHWH1 tWHWH1 µs
(Note 2) Word Typ 12
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29F800B 37
AC CHARACTERISTICS
555 for program PA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
Figure 19. Alternate CE# Controlled Write Operation Timings
38 Am29F800B
ERASE AND PROGRAMMING PERFORMANCE
Parameter Typ (Note 1) Max (Note 3) Unit Comments
Sector Erase Time 1.0 8 s Excludes 00h programming

Chip Erase Time (Note 2) 19 s prior to erasure (Note 4)
Byte Programming Time 7 300 µs
Word Programming Time 12 500 µs Excludes system level

Byte Mode 7.2 21.6 s overhead (Note 5)
Chip Programming Time
(Note 2) Word Mode 6.3 18.6 s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE

Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
Am29F800B 39
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
40 Am29F800B
PHYSICAL DIMENSIONS (continued)
TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
Am29F800B 41
TSR048—48-Pin Reverse Pinout Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
42 Am29F800B
FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm package
Dwg rev AF; 10/99
Am29F800B 43
REVISION SUMMARY
Revision A (August 1997) Revision C+1 (April 1998)

Initial release. Distinctive Characteristics
Changed typical program/erase current to 30 mA to
Revision B (October 1997) match the CMOS DC Characteristics table.
Global
Changed minimum endurance to 1 million write cycles
Added -55 speed option. Changed data sheet designa- per sector guaranteed.
tion from Advance Information to Preliminary.
AC Characteristics
Sector Protection/Unprotection
Erase/Program Operations: Corrected the notes refer-
Corrected text to indicate that these functions can only ence for tWHWH1 and tWHWH2. These parameters are
be implemented using programming equipment. 100% tested. Changed tDS and tCP specifications for 55
Table 1, Device Bus Operations ns device. Changed tWHWH1 word mode specification
to 12 µs.
Revised to indicate inputs for both CE# and RESET#
are required for standby mode. Alternate CE# Controlled Erase/Program Operations:
Corrected the notes reference for tWHWH1 and tWHWH2.
Program Command Sequence These parameters are 100% tested. Changed tDS and
Changed to indicate Data# Polling is active for 2 µs tCP specifications for 55 ns device. Changed tWHWH1
after a program command sequence if the sector spec- word mode specification to 12 µs.
ified is protected.
Temporary Sector Unprotect Table
Sector Erase Command Sequence and DQ3: Sector Added note reference for tVIDR. This parameter is not
Erase Timer 100% tested.
Corrected sector erase timeout to 50 µs.
Erase and Programming Performance
Erase Suspend Command In Notes 1 and 6, changed the endurance specification
Changed to indicate that the device suspends the to 1 million cycles.
erase operation a maximum of 20 µs after the rising
edge of WE#. Revision C+2 (April 1998)
DC Characteristics Product Selector Guide
Changed to indicate VID min and max values are 11.5 Deleted the -55 speed option for VCC = 5.0 V ± 5%.
to 12.5 V, with a VCC test condition of 5.0 V. Added Added the -55 speed option for VCC = 5.0 V ± 10%.
typical values to TTL table. Revised CMOS typical Ordering Information
standby current (ICC3).
Va l i d C o m b i n a t i o n s fo r A m 2 9 F 8 0 0 B T- 5 5 a n d
Figure 14: Chip/Sector Erase Operation Timings; Am29F800BB-55: Added the extended temperature
Figure 19: Alternate CE# Controlled Write range for all package types.
Operation TImings
Operating Ranges
Corrected hexadecimal values in address and data
waveforms. In Figure 19, corrected data values for chip VCC Supply Voltages: Deleted “VCC for ± 5% devices .
and sector erase. . . . +4.75 V to +5.25 V”. Changed “V CC for ±10%
devices . . . . +4.5 V to +5.5 V” to “VCC for all devices .
Erase and Programming Performance . . . +4.5 V to +5.5 V”.
Corrected word and chip programming times. Erase and Programming Performance
Revision C (January 1998) Note 2: Deleted “(4.75 V for -55)”.
Global
Formatted for consistency with other 5.0 volt-only
data sheets.
44 Am29F800B
REVISION SUMMARY (Continued)
Revision D (January 1999) Revision D+2 (July 2, 1999)

Distinctive Characteristics Global
Added the 20-year data retention subbullet. Added references to availability of device in Known
Good Die (KGD) form.
Ordering Information
Optional Processing: Deleted “B = Burn-in”. Revision E (November 16, 1999)
DC Characteristics—TTL/NMOS Compatible AC Characteristics—Figure 13. Program
ILIT: Added OE# and RESET to the Description column. Operations Timing and Figure 14. Chip/Sector
Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5 Erase Operations
V” in the Test Conditions column. Deleted tGHWL and changed OE# waveform to start at
high.
I L O, I C C 1 , I C C 2 : D e l e t e d “ V C C = V C C m a x ” i n
Test Conditions. Physical Dimensions
ICC3: Added Note 4, “ICC3 = 20 µA max at extended Replaced figures with more detailed illustrations.
temperatures (>+85°C)”.
Revision E+1 (August 4, 2000)
DC Characteristics—CMOS Compatible
Global
ILIT: Added OE# and RESET to the Description column.
Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5 Added FBGA package.
V” in the Test Conditions column.
Revision E+2 (June 4, 2004)
I CC1, I CC2 , I CC3 : Deleted “V CC = V CC max”; added
Ordering Information
Note 2 “Maximum I CC specifications are tested with
VCC = VCCmax”. Added Pb-Free OPNs.
Revision D+1 (March 23, 1999)

Command Definitions table
Corrected SA definition in legend; range should be
A18–A12. In Note 4, A17 should be A18.
Trademarks
Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F800B 45

Am29F800B: Data Sheet

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Am29F800B

Continuity of Ordering Part Numbers

For More Information

Publication Number 21504 Revision E Amendment 2 Issue Date June 1, 2004

Max access time, ns (tACC) 55 70 90 120 150

Max CE# access time, ns (tCE) 55 70 90 120 150

Max OE# access time, ns (tOE) 30 30 35 50 55

Note: See “AC Characteristics” for full specifications.

VCC Detector Timer

X-Decoder Cell Matrix

OE# = Output enable OE#

WE# = Write enable WE#

RESET# = Hardware reset pin, active low RESET#

RY/BY# = Ready/Busy# output BYTE# RY/BY#

VCC = +5.0 V single power supply

BOOT CODE SECTOR ARCHITECTURE

Valid Combinations Valid Combinations for FBGA Packages

AM29F800BT-55, Order Number Package Marking

Table 1. Am29F800B Device Bus Operations

Read L L H H AIN DOUT DOUT High-Z

Write L H L H AIN DIN DIN High-Z

CMOS Standby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z

TTL Standby H X X H X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z

Hardware Reset X X X L X High-Z High-Z High-Z

Temporary Sector Unprotect

Word/Byte Configuration command is necessary in this mode to obtain array

SA0 0 0 0 0 X X X 64/32 00000h–07FFFh 00000h–0FFFFh

SA1 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh

SA2 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh

SA3 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh

SA4 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh

SA5 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh

SA6 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh

SA7 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh

SA8 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh

SA9 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh

SA10 1 0 1 0 X X X 64/32 50000h–57FFFh A0000h–AFFFFh

SA11 1 0 1 1 X X X 64/32 58000h–5FFFFh B0000h–BFFFFh

SA12 1 1 0 0 X X X 64/32 60000h–67FFFh C0000h–CFFFFh

SA13 1 1 0 1 X X X 64/32 68000h–6FFFFh D0000h–DFFFFh

SA14 1 1 1 0 X X X 64/32 70000h–77FFFh E0000h–EFFFFh

SA15 1 1 1 1 0 X X 32/16 78000h–7BFFFh F0000h–F7FFFh

SA16 1 1 1 1 1 0 0 8/4 7C000h–7CFFFh F8000h–F9FFFh

SA17 1 1 1 1 1 0 1 8/4 7D000h–7DFFFh FA000h–FBFFFh

SA18 1 1 1 1 1 1 X 16/8 7E000h–7FFFFh FC000h–FFFFFh

SA0 0 0 0 0 0 0 X 16/8 00000h–01FFFh 00000h–03FFFh

SA1 0 0 0 0 0 1 0 8/4 02000h–02FFFh 04000h–05FFFh

SA2 0 0 0 0 0 1 1 8/4 03000h–03FFFh 06000h–07FFFh

SA3 0 0 0 0 1 X X 32/16 04000h–07FFFh 08000h–0FFFFh

SA4 0 0 0 1 X X X 64/32 08000h–0FFFFh 10000h–1FFFFh

SA5 0 0 1 0 X X X 64/32 10000h–17FFFh 20000h–2FFFFh

SA6 0 0 1 1 X X X 64/32 18000h–1FFFFh 30000h–3FFFFh

SA7 0 1 0 0 X X X 64/32 20000h–27FFFh 40000h–4FFFFh

SA8 0 1 0 1 X X X 64/32 28000h–2FFFFh 50000h–5FFFFh

SA9 0 1 1 0 X X X 64/32 30000h–37FFFh 60000h–6FFFFh

SA10 0 1 1 1 X X X 64/32 38000h–3FFFFh 70000h–7FFFFh

SA11 1 0 0 0 X X X 64/32 40000h–47FFFh 80000h–8FFFFh

SA12 1 0 0 1 X X X 64/32 48000h–4FFFFh 90000h–9FFFFh