Program : B.

Tech
Subject Name: Microprocessor & its Application
Subject Code: EC-501
Semester: 5th
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UNIT I: Salient features of advanced microprocessors. RISC & CISC processors. Review and evolution of
advanced microprocessors:8086,8088, 80186/286/386/486/Pentium, introduction to 8086 processor: Register
organization of 8086, Architecture, signal description of 8086, minimum mode 8086 systems and timings and
maximum mode 8086 systems and timings
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RISC & CISC processors:

Sl. No. RISC Architecture CISC Architecture

i RISC stands for Reduced Instruction Set CISC stands for Complex Instruction Set
Computer. Computer.
ii RISC processors have simple instructions CSIC processor has complex instructions that
taking about one clock cycle. take up multiple clocks for execution.
iii Performance is optimized with more focus on Performance is optimized with more focus on
software hardware.
iv It has no memory unit and uses a separate It has a memory unit to implement complex
hardware to implement instructions. instructions.
v It has a hard-wired unit of programming. It has a microprogramming unit.

Architecture of 8086 Microprocessor: The microprocessor 8086 architecture is divided into two parts, bus
interface unit (BIU) and execution unit (EU). The basic principle in this architecture is instruction pipelining and
memory segmentation which increases the processing capability.

Bus Interface Unit (BIU) : This unit establish the communication between the external devices and the processor.
The BIU consists of address conversion block which converts 16-bit offset and 16-bit segment address in to 20-
bit physical address. It includes the 6-bytes instruction queue for storing the instruction to be executed. The
segment registers hold the address of the respective segments and instruction pointer register holds the
address of the next instruction to be executed.

Execution Unit (EU) : The execution unit (EU) of the 8086 tells the BIU where to fetch instructions or data from,
decodes instructions and executes instruction. The EU contains control circuitry which directs internal
operations. A decoder in the EU translates instructions fetched from memory into a series of actions which the
EU carries out. The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment, decrement,
complement or shift binary numbers. The EU is decoding an instruction or executing an instruction which does
not require use of the buses.

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Address / Status Address / Data

A16/S3 - A19/S6 AD0 - AD15
Memory address &
data bus interface

Internal Data Bus

BUS
I Address Conversion Instruction Byte
N Mechanism (Adder) Queue (6 Bytes)
T
E
R CS
F DS
A SS
C ES
E
IP
UNIT

Internal Data Bus

Decoding
E
Circuit
X AH AL
E BH BL
C CH CL
U
DH DL
T
I SP
O BP
N SI Flags (16)
Timing &
DI
Control Circuit
UNIT
Register Bank

Clock & Control

Fig.1.1 : Internal Architecture of 8086 Microprocessor Signals

Register Organisation:
General Purpose Registers:
The registers AX,BX,CX and DX are the four general purpose 16-bit registers. These registers can also be used as
8-bit register of higher (H) and lower order(L). The general purpose registers have some special functions as
mentioned below.
AX - used as 16-bit accumulator, with the lower 8-bits designated as AL and higher 8-bits as AH.
BX - used as an offset storage for forming physical addresses in case of certain addressing modes.
CX – used as a default counter in case of string and loop instruction.
DX – used as implicit operand or destination in case of a few instruction.

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Segment Registers:
There are four 16-bit segment registers CS,DS,ES and SS used to point to the memory segments. Instead of
using 20-bit register for a physical address, the processor just maintain the two 16-bit register of segment
address and offset address.
CS – Code segment register used to hold the address of the code segment of the memory space.
DS – Data segment register used to hold the address of the current data segment of the memory space.
ES – Extra segment register which also pointing to the data segment
SS – Stack segment register is pointing to the top of the stack space in the memory.

Pointers and index registers.

The pointers contain within the particular segments. The pointers IP, BP, SP usually contain offsets within the
code, data and stack segments respectively
SP -- Stack Pointer is a 16-bit register pointing to program stack in stack segment.
BP -- Base Pointer is a 16-bit register pointing to data in stack segment. BP register is usually used for based,
based indexed or register indirect addressing.
SI -- Source Index is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as
well as a source data addresses in string manipulation instructions.
DI -- Destination Index is a 16-bit register. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation instructions.

Flag Register:
The 8086 flag register as shown in the fig 1.6. 8086 has 9 active flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X O D I T S Z X AC X P X CY

O-Overflow Flag D- Direction Flag

I- Interrupt Flag T- Trap Flag
S-Sign Flag Z-Zero Flag
AC-Auxiliary Carry Flag P –Parity Flag
CY-Carry Flag X- Not Used

Conditional Flags : Conditional flags are as follows:

Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in
multiple-precision arithmetic.
Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 –
D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains
even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation
is negative, sign flag is set.

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Control Flags: Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows
Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a program at a
time for debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled
and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by
executing CLI instruction.
Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory
address to lower memory address. When it is reset, the string bytes are accessed from lower memory
address to higher memory address.

Signal Description of 8086:

AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains on the lines
during T1 state, while the data is available on the data bus during T2, T3, TW and T4. Here T1, T2, T3, T4 and TW are
the clock states of a machine cycle. TW is a wait state. These lines are active high and float to a tristate during
interrupt acknowledge and local bus hold acknowledge cycles.
A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines. During T1, these are the
most significant address lines or memory operations. During I/O operations, these lines are low. During
memory or I/O operations, status information is available on those lines for T 2, T3, TW and T4 .The status of the
interrupt enable flag bit(displayed on S5) is updated at the beginning of each clock cycle. The S4 and S3

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combinedly indicate which segment register is presently being used for memory accesses as shown in Table.
These lines float to tri-state off (tristated) during the local bus hold acknowledge. The status line S6 is always
low(logical). The address bits are separated from the status bits using latches controlled by the ALE signal.

BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the transfer of data over the
higher order (D15-D8) data bus as shown in Table 1.2. It goes low for the data transfers over D 15-D8 and is used
to derive chip selects of odd address memory bank or peripherals. BHE is low during T 1 for read, write and
interrupt acknowledge cycles, when- ever a byte is to be transferred on the higher byte of the data
bus. The status information is available during T2, T3 and T4. The signal is active low and is tristated during 'hold'.
It is low during T1 for the first pulse of the interrupt acknowledge cycle.

RD-Read: Read signal, when low, indicates the peripherals that the processor is performing a memory or I/O
read operation. RD is active low and shows the state for T2, T3, TW of any read cycle. The signal remains
tristated during the 'hold acknowledge'.
READY: This is the acknowledgement from the slow devices or memory that they have completed the data
transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide
ready input to the 8086. The signal is active high.
INTR-lnterrupt Request: This is a level triggered input. This is sampled during the last clock cycle of each
instruction to determine the availability of the request. If any interrupt request is pending, the processor enters
the interrupt acknowledge cycle. This can be internally masked by resetting the interrupt enable flag. This signal
is active high and internally synchronized.
TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low, execution will continue, else,
the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading
edge of clock.
NMI-Non-maskable Interrupt: This is an edge-triggered input which causes a Type2 interrrupt. The NMI is not
maskable internally by software. A transition from low to high initiates the interrupt response at the end of the
current instruction. This input is internally synchronized.
RESET: This input causes the processor to terminate the current activity and start execution from FFFF0H. The
signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET
returns low. RESET is also internally synchronized.
CLK-Clock Input: The clock input provides the basic timing for processor operation and bus control activity. Its
an asymmetric square wave with 33% duty cycle. The range of frequency for different 8086 versions is from
5MHz to 10MHz.
VCC : +5V power supply for the operation of the internal circuit. GND ground for the internal circuit.

MN/MX :The logic level at this pin decides whether the processor is to operate in either minimum (single
processor) or maximum (multiprocessor) mode.

The following pin functions are for the minimum mode operation of 8086.
M/IO -Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates
the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation.
This line becomes active in the previous T4 and remains active till final T4 of the current cycle. It is tristated
during local bus "hold acknowledge".
INTA -Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. In other
words, when it goes low, it means that the processor has accepted the interrupt. It is active low during T 2, T3
and TW of each interrupt acknowledge cycle.

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ALE-Address latch Enable: This output signal indicates the availability of the valid address on the address/data
lines, and is connected to latch enable input of latches. This signal is active high and is never tristated.
DT /R -Data Transmit/Receive: This output is used to decide the direction of data flow through the
transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the
processor is receiving data, this signal is low. Logically, this is equivalent to S1 in maximum mode. Its timing is
the same as M/I/O. This is tristated during 'hold acknowledge'.
DEN-Data Enable This signal indicates the availability of valid data over the address/data lines. It is used to
enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal.
It is active from the middle of T2 until the middle of T4 DEN is tristated during 'hold acknowledge' cycle.
HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it indicates to the processor that
another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold
acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus
(instruction) cycle. At the same time, the processor floats the local bus and control lines. When the processor
detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and it should be externally
synchronized.

The following pin functions are for the maximum mode operation of 8086.
QS1 and QS0 – Queue status: These status signals indicate the code pre-fetch queue. These are active during
the CLK cycle after the queue operation is performed. The 6-bytes instruction queue which store the instruction
called as pre-fetch queue provides the pipelined processing feature in 8086. The queue status indicates as
mentioned
QS1 QS0 Indication
0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty queue
1 1 Subsequent byte from the queue

S2, S1, S0 – Status Lines:

S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
LOCK : This output pin indicates the use of system bus by the other master when this signal is low.
RQ / GT0 , RQ / GT1: These pins are used by other local bus master, in maximum mode operation . The local bus
are release at the end of the processor’s current bus cycle. Each of these pins are bidirectional with RQ/GT0
having highest priority than RQ/GT1

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Memory Organisation:

BHE = 0 A0 = 0
Odd Address Even Address
Bank Bank
8-Bit Memory 8-Bit Memory
8086 D0 – D7 D0 – D7
Microprocessor

D8 – D15 Higher Byte Lower Byte

D0 – D7

Fig.1.2: Physical Memory Organisation

The physical memory in 8086 is organised as odd and even bank. The total 1Mbytes of memory is divided into
two 512Mbytes memory bank each. The arrangements of these memory bank is as shown in Fig.2.b. The lower
byte data lines are connected with even memory bank and higher byte data lines are connected with odd
memory bank. A0 is used to select the even memory bank and the BHE line is used to select the odd memory
bank. The read and write cycle will operate to activate both the banks or only one bank based on the length of
the data. Since the 8086 is capable of operating on 16-bit data, with this type of configuration it is possible to
operate on 16-bit at a time.

Clock Generator 8284: The 8284A is an 18-pin IC designed for use with the 8086 microprocessors. The following
is a list of each pin and its function. The pin details are as shown in Fig. .

Fig. 1.3 Pin Diagram of Clock Generator

AEN1 and AEN2: The address enable pins are provided to qualify the ready signals. RDY1 and RDY2,
respectively. Which are used to cause wait states, along with the RDY1 and RDY2 inputs. Wait states are
generated by the READY pin of the 8086microprocessor. This is controlled by these two inputs.
RDY1 and RDY2: The bus ready inputs are provided in conjunction with the AEN1 and AEN2 pins to cause wait
states in an 8086 microprocessor based system.

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ASYNC: The ready synchronization selection input selects either one or two stages of synchronization for the
RDY1 and RDY2 inputs.
READY: Ready is an output pin that connects to the 8086 microprocessor READY input. This signal is
synchronized with the RDY1 and RDY2 inputs.
X1 and X2: The Crystal Oscillator pins connect to an external crystal used as the timing source for the clock
generator and all its functions.
F/C*: The Frequency/Crystal select input results the clocking source for the 8284A. If this pin is held high, an
external clock is provided to the EFI input pin, and if it is held low, the internal crystal oscillator provides the
timing signal.
EFI: The External Frequency input is used when the F/C is pulled high. EFI supplies the timing whenever the
F/C* pin is high.
CLK: The clock output pin provides CLK input signal to the 8086 microprocessors and other components in the
system. The CLK pin has an output signal that is one-third of the crystal or EFI input frequency and has a 33%
duty cycle, which is required by the 8086 microprocessors.
PCLK: The Peripheral Clock signal is one-sixth the crystal or EFI input frequency and has a 50 percent duty
cycle. The PCLK output provides a clock signal to the peripheral equipment in the system.
OSC: The Oscillator output is a TTL level signal that is at the same frequency as the crystal or EFI input.
RES*: The reset input is an active-low input to the 8284A. The RES* pin is often connected an RC network that
provides power-on resetting.
RESET: The Reset output is connected to the 8086/8088 microprocessors RESET input pin.
CSYNC: The clock synchronization pin is used whenever the EFI input provides synchronization in systems
with multiple processors. When the internal crystal oscillator is used, this pin must be grounded.
GND: The ground pin is connects to ground.
Vcc: This power supply pin connects to + 5.0V with a tolerance of ± 10 percent

Minimum Mode:

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its
MN/MX* pin to logic1. In this mode, all the control signals are given out by the microprocessor chip itself. There
is a single microprocessor in the minimum mode system. The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for
selecting memory or I/O devices, depending upon the address map of the system. The latches are generally
buffered output D-type flip-flops, like, 74LS373 or 8282. They are used for separating the valid address from
the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transreceivers
are the bidirectional buffers and sometimes they are called as data amplifiers. They are required to separate
the valid data from the time multiplexed address/data signal. They are controlled by two signals, namely, DEN*
and DT/R*. The DEN* signal indicates that the valid data is available on the data bus, while DT/R indicates the
direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program
storage.

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Fig.1.4: Minimum Mode Configuration

CLK
T1 T2 T3 Tw T4

ALE

Address/Status BHE, A19 – A16 S 7 – S3

Bus Reserved
Address/DATA A15 – A0 D15 – D0
For data in

RD

DEN

DT/R

Fig.1.5 : Read cycle timing diagram for Minimum mode

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• The read cycle begins with T1 state by assertion of ALE signal. The address is latched during this state.
• At T2 the address is removed from the local bus and the lines are reserved fro data. the RD signal is activated
to read during this state.
• The data is made available by the enable device on the line and a valid data is available once the RD signal
goes low and
• The process after finding the data on the lines make the RD signal high and tristate the data lines. Thus the
process needs T1 to T4 state to complete one machine cycle.

Maximum Mode:

In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this mode, the
processor derives the status signals S2*, S1* and S0*. Another chip called bus controller derives the control
signals using this status information. In the maximum mode, there may be more than one microprocessor in
the system configuration. The other components in the system are the same as in the minimum mode system.
The general system organization is as shown in the Fig1.6 The basic functions of the bus controller chip IC8288,
is to derive control signals like RD* and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the
information made available by the processor on the status lines. The bus controller chip has input lines S2*,
S1* and S0* and CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE, DEN*, DT/R*,
MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN*, IOB and CEN pins are specially useful for
multiprocessor systems. AEN* and IOB are generally grounded. CEN pin is usually tied to +5V.

Fig.1.6: Maximum Mode Configuration

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