THGBMBG5D1KBAIL Toshiba
THGBMBG5D1KBAIL Toshiba
THGBMBG5D1KBAIL Toshiba
FEATURES
THGBMBG5D1KBAIL Interface
THGBMBG5D1KBAIL has the JEDEC/MMCA Version 5.0 interface with 1-I/O, 4-I/O and 8-I/O mode.
Pin Connection
P-WFBGA153-1113-0.50-001 (11.5mm x 13mm, H0.8mm max. package)
14 NC NC NC NC NC NC NC NC NC NC NC NC NC NC
13 NC NC NC NC NC NC NC NC NC NC NC NC NC NC
12 NC NC NC NC NC NC NC NC NC NC NC NC NC NC
11 NC NC NC NC NC NC
9 NC NC NC VSF Vcc NC NC NC
8 NC NC NC RFU Vss NC NC NC
Top View
7 RFU NC NC Vss RFU NC NC RFU
5 DAT2 DAT6 NC RFU Vcc Vss DS Vss RST_n CMD VssQ VccQ
1 NC NC NC NC NC NC NC NC NC NC NC NC NC NC
A B C D E F G H J K L M N P
Pin Number Name Pin Number Name Pin Number Name Pin Number Name
Part Numbers
Available e-MMC Module Products – Part Numbers
TOSHIBA Part Number Density Package Size NAND Flash Type Weight
Performance
X8 mode/ Sequential access (4MByte access size)
Typ. Performance
Interleave Frequency [MB/sec]
TOSHIBA Part Number Density NAND Flash Type VccQ
Operation /Mode
Read Write
1.8V 47 12
52MHz/SDR
3.3V 47 12
Non 1.8V 88 12
THGBMBG5D1KBAIL 4GB 1 x 32Gb A19nm 52MHz/DDR
Interleave 3.3V 88 12
Power Supply
Vcc = 2.7V to 3.6V
VccQ = 1.7V to 1.95V / 2.7V to 3.6V
Max Operating
Interleave Frequency Current [mA]
TOSHIBA Part Number Density NAND Flash Type VccQ
Operation /Mode
Iccq Icc
1.8V 80 45
52MHz/SDR
3.3V 95 45
Non 1.8V 95 45
THGBMBG5D1KBAIL 4GB 1 x 32Gb A19nm 52MHz/DDR
Interleave 3.3V 120 45
Non
THGBMBG5D1KBAIL 4GB 1 x 32Gb A19nm 110 810 130 860
Interleave
*1: The conditions of typical values are 25°C and VccQ = 3.3V or 1.8V.
*2: The conditions of maximum values are 85°C and VccQ = 3.6V or 1.95V.
Product Architecture
The diagram in Figure 1 illustrates the main functional blocks of the THGBMBG5D1KBAIL.
Specification of the CREG and recommended values of the CVCC, and CVCCQ in the Figure 1 are as follows.
Package
Vcc(3.3V)
CVCC
VccQ(1.8V/3.3V)
CVCCQ NAND
REGULATOR Control signal
NAND I/O BLOCK
MMC I/O BLOCK
VDDi
I/O BLOCK
CREG
CORE LOGIC NAND
x11 NAND I/O
MMC I/F(1.8V/3.3V)
Remark: Data A, B and S are defined by the least square method of all solder balls
Register Informations
OCR Register
CID Register
CSD Register
Size
CSD-slice Name Field Cell Type Value
(Bytes)
R/W, 0x00
[171] User area write protection register USER_WP 1 R/W/C_P &
R/W/E_P
PARTITION_SETTING_ 0x00
[155] Partitioning Setting 1 R/W
COMPLETED
[154:143] General Purpose Partition Size 3 GP_SIZE_MULT 12 R/W 0x00
4
[142:140] Enhanced User Data Area Size ENH_SIZE_MULT 3 R/W 0x00
1 Although these fields can be re-written by host, TOSHIBA e-MMC does not support.
2 Max Enhanced Area Size (MAX_ENH_SIZE_MULT [159:157]) has to be calculated by following formula.
Max Enhanced Area = MAX_ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512kBytes
4
4 Enhanced User Data Area Size (ENH_SIZE_MULT [142:140]) has to be calculated by following formula.
16 8
Enhanced User Data Area x Size = (ENH_SIZE_MULT_2 x 2 + ENH_SIZE_MULT_1 x 2
0
+ ENH_SIZE_MULT_0 x 2 ) x HC_WP_GRP_SIZE
x HC_ERASE_GRP_SIZE x 512kBytes
5
- Pre loading data size = PRE_LOADING_DATA_SIZE x Sector Size
Pre-loading data size should be multiple of 4KB and the pre-loading data should be written by multiple of 4KB
chunk size, aligned with 4KB address. This is because the valid data size will be treated as 4KB when host
writes data less than 4KB.
- If the host continues to write data in Normal state (after it wrote PRE_LOADING_DATA_SIZE amount
of data) and before soldering, the pre-loading data might be corrupted after soldering.
- If a power cycle is occurred during the data transfer, the amount of data written to device is not clear.
Therefore in this case, host should erase the entire pre-loaded data and set again
PRE_LOADING_DATA_SIZE[25:22], PRODUCTION_STATE_AWARENESS[133], and
PRODUCT_STATE_AWARENESS_ENABLEMENT[17].
If the Host could not initialize the V5.0 device, Host should modify the treatment of
EXT_CSD_REV[192].
General
Parameter Symbol Test Conditions Min Max Unit
Peak voltage on all lines -0.5 VccQ+0.5 V
All Inputs
Input Leakage Current (before initialization sequence1
-100 100 μA
and/or the internal pull up resistors connected)
Input Leakage Current (after initialization sequence and
-2 2 μA
the internal pull up resistors disconnected)
All Outputs
Output Leakage Current (before initialization sequence) -100 100 μA
Output Leakage Current (after initialization sequence) -2 2 μA
1.7 1.95 V
Supply voltage 2 VccQ
2.7 3.6 V
1) Once the power supply VCC or VCCQ falls below the minimum guaranteed voltage (for example, upon sudden power fail),
the voltage level of VCC or VCCQ shall be kept less than 0.5 V for at least 1ms before it goes beyond 0.5 V again.
Supply Current
Interleave Min Max
Parameter Symbol Mode VccQ Unit
Operation Iccq Icc Iccq Icc
1.8V 80 20
SDR mA
3.3V 95 20
1.8V 95 25
Read IROP Non Interleave DDR mA
3.3V 120 25
HS200 1.8V 140 45 mA
Output HIGH voltage VOH IOH = -100μA @ VDD min 0.75 * VccQ V
Output LOW voltage VOL IOL = 100μA @ VDD min 0.125 * VccQ V
Output HIGH voltage VOH IOH = -2mA @ VDD min VccQ - 0.45 V
Driver Type-0 is targeted for transmission line, based distributed system with 50Ω nominal line impedance.
Therefore, it is defined as 50Ω nominal driver.
For HS200, when tested with CL = 15pF Driver Type-0 shall meet all AC characteristics and HS200 Device output
timing requirements. The test circuit defined in section 10.5.4.3 of JEDEC/MMCA Standard 5.0 is used for testing of
Driver Type-0.
For HS400, when tested with the reference load defined in page 24 HS400 reference load figure, Driver Type-0 or
Driver Type-1 or Driver-4 shall meet all AC characteristics and HS400 Device output timing requirements.
The Optional Driver Types are defined with reference to Driver Type-0.
1) Support of Driver Type-0 is mandatory for HS200&HS400 Device, while supporting Driver types 1, 2 and 3 is optional for
HS200 and Driver type 4 is optional for HS400 Device.
2) Nominal impedance is defined by I-V characteristics of output driver at 0.9V when VCCQ = 1.8V.
Bus Timing
Clock frequency Identification Mode (OD) fOD Tolerance: +20KHz 0 400 KHz
Output Delay time during Data Transfer tODLY CL <= 30pF 13.7 ns
Clock frequency Data Transfer Mode (PP)3 fpp CL <= 30pF 0 26 MHz
Clock frequency Identification Mode (OD) fOD Tolerance: +20KHz 0 400 KHz
1) The e-MMC must always start with the backward-compatible interface timing. The timing mode can be switched to
high-speed interface timing by the host sending the SWITCH command (CMD6) with the argument for high-speed
interface select.
2) CLK timing is measured at 50% of VccQ
3) For compatibility with e-MMCs that support the v4.2 standard or earlier, host should not use >26MHz before switching to
high-speed interface timing.
4) CLK rise and fall times are measured by min(VIH) and max(VIL).
5) tOSU and tOH are defined as values from clock rising edge. However, the e-MMC device will utilize clock falling edge to
output data in backward compatibility mode. Therefore, it is recommended for hosts either to set tWL value as long as
possible within the range which will not go over tCK - tOH(min) in the system or to use slow clock frequency, so that host
could have data set up margin for the device.
Toshiba e-MMC device utilize clock falling edge to output data in backward compatibility mode.
Host should optimize the timing in order to have data set up margin as follows.
tWL
CLK
Bus Timing for DAT signals for during 2x data rate operation
These timings applies to the DAT[7:0] signals only when the device is configured for dual data mode operation. In
this dual data mode, the DAT signals operates synchronously of both the rising and the falling edges of CLK. the
CMD signal still operates synchronously of the rising edge of CLK and therefore complies with the bus timing
specified in High-speed interface timing or Backward-compatible interface timing.
Input CLK 1
ΔTPH consideration
Implementation Guide:
Host should design to avoid sampling errors that may be caused by the ΔTPH drift.
It is recommended to perform tuning procedure while Device wakes up, after sleep.
One simple way to overcome the ΔTPH drift is by reduction of operating frequency.
Driver
Device I/O Measurement Point
Z0 = 50 Ohm
Td = 350 ps
CREFERENCE =4pF
Reference Load
HS400 Capacitance
Parameter Symbol Min Typ. Max Unit Remark
Pull-up resistance for CMD RCMD 4.7 100 kΩ
Pull-up resistance for DAT0-7 RDAT 10 100 kΩ
Pull-down resistance for Data Strobe RDS 10 100 kΩ
Internal pull up resistance DAT1-DAT7 Rint 10 150 kΩ
Bus signal line capacitance CL 13 pF
Single Device capacitance CDEVICE 6 pF
Overshoot/Undershoot Specification
VCCQ Unit
1.70V-1.95V
Maximum peak amplitude allowed for overshoot area. Max 0.9 V
(See Figure Overshoot/Undershoot definition)
Maximum peak amplitude allowed for undershoot area. Max 0.9 V
(See Figure Overshoot/Undershoot definition)
Maximum area above VCCQ Max 1.5 V-ns
(See Figure Overshoot/Undershoot definition)
Maximum area below VSSQ Max 1.5 V-ns
(See Figure Overshoot/Undershoot definition)
(Note) *1 : Device will detect the rising edge of RST_n signal to trigger internal reset sequence
1) 74 cycles of clock signal required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA
2) During the device internal initialization sequence right after power on, device may not be able to detect RST_n signal,
because the device may not complete loading RST_n_ENABLE bits of the extended CSD register into the controller yet.
Power-up sequence
Supply voltage
Vcc max
Vcc min
VccQ max
VccQ min
0.5V
time
Power-up parameter
Parameter Symbol Test Conditions Min Max Remark
Functional restrictions
- Pre loading data size is limited to MAX_PRE_LOADING_DATA_SIZE[21-18] regardless of using Production
State Awareness function.
- MAX_PRE_LOADING_DATA_SIZE[21-18] value will change when host sets Enhanced User area Partition.
Reliability Guidance
This reliability guidance is intended to notify some guidance related to using raw NAND flash. Although random
bit errors may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be
marked as bad when a program status failure or erase status failure is detected. The other failure modes may be
recovered by a block erase. ECC treatment for read data is mandatory due to the following Data Retention and
Read Disturb failures.
-Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after
either an auto program or auto block erase operation. The cumulative bad block count will increase along with the
number of write/erase cycles.
-Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge gain.
After block erasure and reprogramming, the block may become usable again. Also write/erase endurance
deteriorates data retention capability. The figure below shows a generic trend of relationship between write/erase
endurance and data retention.
-Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit errors
occur on other pages in the block, not the page being read. After a large number of read cycles (between block
erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure
and reprogramming, the block may become usable again.