BE/BTECH (FULL-TIME) DEGREE END SEMESTER EXAMINATIONS NOWDEC-2013

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

IH SEMESTER ^ ,
EC8301 ELECTRONIC CmCUITS-I f |£
(Regulation 2012) ' ' ^
Time:3Hrs Max Marks: 100
Answer all questions
Part-A (10 X 2=20 Marks)

1) What are the design constraints required for thermally-stabilized biasing circuit.
2) What is the role of bypass capacitor in BJT CE-amplifier circuit?
3) Determine the input impedance o f eommon base amplifier.
4) A small signal source Vi(t)=20cos20t+30sinl0 t is applied to a transistor amplifier as shown
6

in Figure-1. The transistor has P=150, ro=oo and r =3kQ. Determine Vo(t)?
n

5) Find the unity gain bandwidth o f MOSFET whose g =6mA/V, C =8pF, C d=4pF and Cd =
m gs g S

lpF.
6) The ac schematic of an NMOS common-source stage is shown in the Figure-2, where part of
the biasing circuits has been omitted for simplicity. For the N-channel MOSFET M l , the
transconductance, gm = l m A / V , and body effect and channel length modulation effect are to be
neglected. Find the lower cutoff frequency?
7) Draw the small signal equivalent circuit diagram o f PMOS and NMOS transistor by
considering body effects.
8) The small-signal resistance (i.e.,dVB/dIo) in kD offered by the n-channel MOSFET M2
shown in the Figure-3, at a bias point o f V B ^ V is (device data for M2: device
Transconductance parameter KN=u Cox(W/L)=60uA/V , threshold voltage Vtn=lV, and neglect
n

body effect and channel length modulation effects).

9) The DC-load line of MOSFET-Common Source amplifier is shown in Figure-4, Let
VDSsatmin-O.SV, R D = R L 2 . 5 K . Determine its maximum output voltage swing?
=

10) Determine the output impedance of a JFET amplifier shown in Figure-5. Let.gm=2mA/V and
1=0.
+5V

1 v B

lOOkO 0
•In

OkQ JV12

soon

Figure-1 Figure-2 Figure-3

1
 V DD Qf5V
7.8mA

V
4mA Vo H O

1MQ kO > lOkfi

lOkO M
T
•V DS
1 2V

0 Vossatmin 5\/ 9.6V

Figure-4 Figure-5 Figure-6

PART-B f 5X 16=80 Marks)

11) i)With neat circuit diagram explain C M O S differential amplifier with active load. Draw its
equivalent circuit and derive for its C M R R using small signal parameters. (12)

ii) For the N M O S inverter circuit with saturated load (vide Figure-6), the transistor parameters
are: (device data for M D : V U I D =1V, KnD=u Cox(W/L)=100uA / V , Xn =0 and device data for
n
2
D

M : V t n =1V K n = u Cox(W/L) = 20uA / V , and Xn = 0). Draw its voltage-transfer

L L L n
2
L

characteristics curve, and mark down its transition points. (4)

12)a)i)Define and derive the stability factors for BJT self bias (voltage-divider bias) circuit. (10)

ii) Design a JFET circuit with self bias to operate as amplifier with ID = 2mA, loss 12mA and =

V = 4V. Assume VDD 22V, also calculate the maximum peak to peak output voltage of your
P
=

designed circuit. {6)

(OR)
b) i) The parameters for each transistor in the circuit in Fi,gure-7, are P =100, and VBEon 0.7V. =

Determine the Q-point values of base, collector and emitter currents in Qj and Q 2 . (please note
that p=hfe) (8)
ii) Determine the change in collector current produced in each bias referred to in example
Figures 8(a) & 8(b). When the circuit temperature raised from 25°C to 105°C and ICBO =15nA
@ 25°C. (8)
Q +5V

^+18V
I +18V

1- Q: 33KC
1.2KO
470Kf 2.2KO
=100
=100
20kQ 12KC 1KQ
Figure-/ f igure-8(a) —b Figure-8(b)
13)a)i) For the circuit shown in Figure-9, the transistor parameters are (3=125, VA=°O, V C C 1 8 V ,
=

R =4kQ,R =3kQ, Rc=4kQ, R!=25.6kQ and R =10.4kQ. The input signal is a current.
L E 2

Determine its small signal voltage gain, current gain, maximum voltage gain and input
impedance. _ _ (12)

=100kQ

Figure-9

ii) Derive for current gain of Common Emitter amplifier ^self-bias) circuit. (4)
(OR)
b)i) A differential amplifier has a differential gain of 70 dB and CMRR of 90 dB, i f V = 20uV t

and V 2 = 16uV.calculate the output voltage of amplifier and common mode gain. (4)
ii) Draw the circuit diagram of bootstrapped emitter follower with its equivalent circuit, -derive
for its input and output impedance. (6)
iii) Draw a cascode amplifier, with the help of its equivalent circuit diagram derive its voltage-
gain and input impedance. (6)

14)a)i) Draw a NMOS discrete common gate amplifier and its equivalent circuit. Derive for its
Av,R andRo.
in (10)
ii) For the p-channel JFET common-source amplifier in Figure-10, the transistor parameters
lDss 8mA, V = 4V and X=0. Design the circuit such that lDQ=4mA, V S D Q 7 . 5 V , A V = -3 and
=
P
=

R!+R =400kQ.
2 (6)
(OR)
b)i) Determine voltage gain, current gain, input impedance and output impedance of JFET source
follower amplifier. (10)
ii) Determine the value of R D , R S , voltage gain, input and output impedance of the amplifier
having parameters I = 0.5mA Vtp=1.2V, K '=u Cox=80uA/V , V = 4 V and (W/L)= 6.25
D P P
2
SD

(vide Figure-11) (6)

Figure-11

Figure-10
Vcl/V

3
15)a)i) Derive for fp and fa. (6)
ii) For the circuit shown in Figure-12 has following parameters: hf =125, C = 24pF , C = 3pF,
e n M

wiring capacitance is 8pF. (x) Determine its mid-band gain, upper-cut o f f frequency (y) Find the
value of C o , Ca and Ce by assuming lower cut-off frequency o f 100 Hz. (10)
(OR)
b) For the circuit shown in Figure-13, the NMOS transistor parameters are: Kn=u Cox(W/L) n

=2mA/V , V Q = 3 . 2 5 V , Vtn=2V, X=0, C =0.1pF and C =lpF. Assume C G = C = C =lpF.

2
GS gd gs D s

Calculate the mid-band gain, input impedance, output impedance, bandwidth and Maximum
output voltage swing. (16)

*8V
2 10V

1MQ
5 2.3KO

0
Vo
r yvW-ii
234 kO

|
4kQ

C2 10 kQ " >
5KQ 20kO
ci 166 kQ
V
1/ 5KO
0.5k

Figure-12 Figure-13