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09 Axi Stream Fifo

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Broke D
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14 views12 pages

09 Axi Stream Fifo

Uploaded by

Broke D
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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AXI Stream based FIFO

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Top level Block Diagram
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Port Declartion
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Test Bench Wrapper
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Test Plan
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Test Cases - Simulation
Results
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Timing Analysis
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Utilization Report
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Hardware Setup
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Validation
Top level Block Diagram
Port Declaration
Functional Block Diagram
Port Declaration
ASYN_FIFO signals Direction Port Description
Width
FIFO - Write Port
Write clock - for data write operation
wr_clk Input 1
connected to i_wr_clock
Write enable signal to write data to FIFO
wr_en Input 1
memory
din[11:0] Input 256 FIF0 Input data port (256 bits)
full Output 1 FIFO full signal
almost_full Output 1 FIFO almost full signal
overflow Output 1 FIFO overflow flag
FIFO - Read Port
Read clock - for data read operation
rd_clk Input 1
connected to i_rd_clock
Read enable signal to read data from FIFO
rd_en Input 1
memory
dout[11:0] Output 256 FIF0 Output data port (256 bits)
empty Output 1 FIFO empty signal
almost_empty Output 1 FIFO almost empty signal
underflow Outout 1 FIFO underfolw flag
IP Cores - ASYNFIFO IP
IPCORE Version FIFO Generator 13.2
Basic options
Interface Type Native
FIFO Implementation Independent Clocks Block RAM
Native ports options
Read Mode Standard
Data Port Parameters
Write Width 256
Write Depth 8092
Read Width 256
Optional Flags
Almost Full Flag Enable
Almost Empty Flag Enable
Handshacking Options
Overflow Flag Enable
Underflow Flag Enable
Timing Diagram - AXI Stream FIFO Write Operation
Timing Diagram - AXI Stream FIFO Read Operation
Test Plan - AXI Stream FIFO Buffer
Test Bench Block Diagarm
Simulation Result

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