Scsi Controller

This document contains information on a product under development at Advanced Micro Devices Inc.
The information is intended

to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 16506 Rev. C Amendment /0
Issue Date: May 1993
Advanced
Micro
Devices
Am53C94/Am53C96
High Performance SCSI Controller
PRELIMINARY
DISTINCTIVE CHARACTERISTICS
I Pin/function compatible with NCR53C94/53C96
I AMDs Patented GLITCH EATER
TM
Circuitry on
REQ and ACK inputs
I 5 Mbytes per second synchronous SCSI
transfer rate
I 20 Mbytes per second DMA transfer rate
I 16-bit DMA Interface plus 2 bits of parity
I Flexible three bus architecture
I Single ended SCSI bus supported by
Am53C94
I Single ended and differential SCSI bus
supported by Am53C96
I Selection of multiplexed or non-multiplexed
address and data bus
I High current drivers (48 mA) for direct
connection to the single ended SCSI bus
I Supports Disconnect and Reselect commands
I Supports burst mode DMA operation with a
threshold of 8
I Supports 3-byte-tagged queuing as per the
SCSI-2 specification
I Supports group 2 and 5 command recognition
as per the SCSI-2 specification
I Advanced CMOS process for low power
consumption
I Am53C94 available in 84-pin PLCC package
I Am53C96 available in 100-pin PQFP package
GENERAL DESCRIPTION
The High Performance SCSI Controller (HPSC) has a
flexible three bus architecture. The HPSC has a 16-bit
DMA interface, an 8 bit host data interface and an 8-bit
SCSI data interface. The HPSC is designed to minimize
host intervention by implementing common SCSI se-
quences in hardware. An on-chip state machine re-
duces protocol overheads by performing the required
sequences in response to a single command from the
host. Selection, reselection, information transfer and
disconnection commands are directly supported.
The 16-byte-internal FIFO further assists in minimizing
host involvement. The FIFO provides a temporary stor-
age for all command, data, status and message bytes as
they are transferred between the 16 bit host data bus
and the 8 bit SCSI data bus. During DMA operations the
FIFO acts as a buffer to allow greater latency in the DMA
channel. This permits the DMA channel to be sus-
pended for higher priority operations such as DRAM re-
fresh or reception of an ISDN packet.
Parity on the DMA bus is optional. Parity can either be
generated and checked or it can be simply passed
through.
The patented GLITCH EATER Circuitry in the High Per-
formance SCSI Controller detects signal changes that
are less than or equal to 15 ns and filters them out. It is
designed to dramatically increase system performance
and reliability by detecting and filtering glitches that can
cause system failure.
The GLITCH EATER Circuitry is implemented on the
ACK and REQ lines only. These lines often encounter
many electrical anomalies which degrade system per-
formance and reliability. The two most common are Re-
flections and Voltage Spikes. Reflections are a result of
high current SCSI signals that are mismatched by stubs,
cables and terminators. These reflections vary from ap-
plication to application and can trigger false handshake
signals on the ACK and REQ lines if the voltage ampli-
tude is at the TTL threshold levels. Spikes are generated
by high current SCSI signals switching concurrently. On
the control signals (ACK and REQ) they can trigger false
data transfers which result in loss of data, addition of
random data, double clocking and reduced system reli-
ability. AMDs GLITCH EATER Circuitry helps maintain
excellent system performance by treating the glitches.
Refer to the diagram on the next page.
P R E L I M I N A R Y AMD
2 Am53C94/Am53C96
SCSI Environment
Valid Signal Glitches
>15 ns <15 ns
Glitches pass through as valid signals
ACK or
REQ Input
Device without the
GLITCH EATER Circuit
Glitches Filtered
AMDs Device with the
GLITCH EATER Circuit
Valid Signal Passes
16506C-1
GLITCH EATER Circuitry in SCSI Environment
ACK or
REQ Input
SYSTEM BLOCK DIAGRAM
9
CPU
DMA
Memory
Am53C94/96
8
16
16
4
9
SCSI Data
16
DMA
Addr
Data
16506C-2
SCSI Control
16
3 Am53C94/Am53C96
SYSTEM BUS MODE DIAGRAMS
16506C-3
8-Bit Data Bus
Address Bus
DMA
Controller
Host
Processor
Am53C94/96
Bus
Controller
DMA 70
A 30
RD
WR
DMAWR
BUSMD 0
BUSMD 1
DREQ
DACK
Bus Mode 0
16506C-4
Data Bus
Address Bus
RD
WR
DMAWR
DREQ
DACK
DMA
Controller
Host
Processor
Am53C94/96
Bus
Controller
DMA 150
A 30
BUSMD 0
BUSMD 1
8 16
VDD
Bus Mode 1
4 Am53C94/Am53C96
SYSTEM BUS MODE DIAGRAMS
DMARD
VDD
8-Bit Data Bus
16506C-5
DMA
Controller
Host
Processor
Am53C94/96
DMA 150
AD 70
WR
DMAWR
BUSMD 0
BUSMD 1
DREQ
DACK
RD
BHE
AS0
ALE
16-Bit Data Bus
Bus Mode 2
VDD
Address Bus
16506C-6
DMA
Controller
Host
Processor
Am53C94/96
DMA 150
A 30
WR
DMAWR
BUSMD 0
BUSMD 1
DREQ
DACK
RD
16-Bit Data Bus
8-Bit Data Bus
AD 70
Bus Mode 3
5 Am53C94/Am53C96
BLOCK DIAGRAM
16506C-7
B
u
s

I
n
t
e
r
f
a
c
e

U
n
i
t
18 18 16 x 9 FIFO
(including parity)
Parity Logic
D
a
t
a

T
r
a
n
c
e
i
v
e
r
s
S
C
S
I

C
o
n
t
r
o
l
M
U
X
8
8
8
9
CLK
6
4
DMA
15-0
DMAP
1-0
DMA Control
AD
7-0
Host Control
BUSMD
1-0
RESET
CS
9
SCSI Control
SCSI Bus
Data + Parity
(Single Ended)
Main
Sequencer
SCSI
Sequencer
Register
Bank
DFMODE
9
SCSI Bus
Data + Parity
Direction Control
7 SCSI Control
Direction Control
6 Am53C94/Am53C96
CONNECTION DIAGRAMS
Top View
16506C-8
D
M
A
1
1
D
M
A
1
0
D
M
A
9
D
M
A
8
D
M
A
7
D
M
A
3
D
M
A
2
D
M
A
1
D
M
A
0
D
M
A
4
D
M
A
P
0
D
M
A
P
1
D
M
A
1
4
D
M
A
1
3
D
M
A
1
2
D
M
A
1
5
D
M
A
5
D
M
A
6
AD3
AD2
AD1
AD0
CLK
ALE [A3]
DMARD [A2]
BHE [A1]
AS0 [A0]
AD4
AD5
DREQ
DACK
DMAWR
AD6
AD7
CS
RD
WR
B
S
Y
C
R
E
Q
C
M
S
G
C
/
D
I
/
O
A
T
N
R
S
T
C
S
E
L
B
S
Y
R
E
Q
A
C
K
R
S
T
B
U
S
M
D

0
I
N
T
R
E
S
E
T
S
E
L
C
B
U
S
M
D

1
A
C
K
C
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
59
58
57
56
55
54
60
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
Am53C94
84-Pin PLCC
SD6
SD7
SDP
V
DD
VSS
V
SS
SD3
SD4
SD5
SD0
SD1
SD2
SDC3
SDC0
SDC1
SDC2
SDC6
SDC7
SDCP
SDC4
SDC5
V
DD
V
SS
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
N
C
I
S
E
L
T
S
E
L
D
M
A
0
D
M
A
1
D
M
A
2
D
M
A
3
D
M
A
4
D
M
A
5
D
M
A
6
D
M
A
7
D
M
A
P
0
D
M
A
8
D
M
A
9
D
M
A
1
0
D
M
A
1
1
D
M
A
1
2
D
M
A
1
3
D
M
A
1
4
D
M
A
1
5
D
M
A
P
1
N
C
S
D

0
S
D

1
D
A
C
K
D
M
A
W
R
N
C
S
D
C

7
S
D
C

P
B
U
S
M
D

0
B
U
S
M
D

1
R
S
T
A
C
K
R
E
Q
S
E
L
A
T
N
I
/
O
C
/
D
M
S
G
A
C
K
C
R
E
Q
C
B
S
Y
C
V
S
S
R
S
T
C
B
S
Y
R
D
N
C
R
E
S
E
T
I
N
T
W
R
S
E
L
C
V
S
S
NC
SDC 6 CS
AS0 [A0]
BHE [A1]
DMARD [A2]
ALE [A3]
CLK
DFMODE
NC
AD0
AD1
AD2
AD3
V
SS
V
SS
AD4
AD5
AD6
AD7
DREQ
V
S
S
V
S
S
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
SDC 0
SDC 1
SDC 2
SDC 3
SDC 4
SDC 5
SD 2
SD 3
V
S
S
V
S
S
SD 4
SD 5
SD 6
SD 7
SD P
V
S
S
V
S
S
31
32
33
34
35
36
37
38
39
40
41
42
43
45
46
47
48
49
50
44
Am53C96
100-Pin PQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30
52 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 51
V
S
S
V
S
S
16506C-9
7 Am53C94/Am53C96
LOGIC SYMBOL
SDCP
BUSMD10
*DFMODE
INT
CS
WR
RD
Am53C94/96
SD70
SDP
BSYC
MSG
C/D
I/O
ATN
SELC
RSTC
REQC
ACKC
SDC70
BSY
SEL
RST
REQ
ACK
*ISEL
*TSEL
DMA150
DMAP10
DREQ
BHE [A1]
AS0 [A0]
ALE [A3]
AD70
DMARD [A2]
DACK
DMAWR
CLK
RESET
Note:
*Pins available on the Am53C96 only.
16506C-10
RELATED AMD PRODUCTS
Part Number Description
85C30 Enhanced Serial Communcaiton
Controller
26LSXX Line Drivers/Receivers
33C93A Enhanced CMOS SCSI Bus
Interface Controller
80C186 Highly Integrated 16-Bit
Microprocessor
80C286 High-Performance 16-Bit
80286 Microprocessor
Part Number Description
Am386
TM
High-Performance 32-Bit
Microprocessor
80188 Highly Integrated 8-Bit Microprocessor
53C80A SCSI Bus Controller
85C80 Combination 53C80A SCSI and
85C30 ESCC
53C94LV Low Voltage, High Performance
SCSI Controller
8 Am53C94/Am53C96
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
TEMPERATURE RANGE
C = Commercial
PACKAGE TYPE
J = 84-Pin PLCC (PL 084)
K = 100-Pin PQFP (PQR100)
DEVICE NUMBER/DESCRIPTION
Am53C94/Am53C96
High Performance SCSI Conroller
AM53C94
AM53C96
AM53C96 K C
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations or to check on newly released
combinations.
JC
KC, KC/W
Valid Combinations
ALTERNATE PACKAGING OPTION
/W= Trimmed and Formed in a Tray (PQJ100)
Blank = Molded Carrier Ring (35 mm)
/W
9 Am53C94/Am53C96
SCSI OUTPUT CONNECTIONS
Am53C94
Am53C94 Single Ended SCSI Bus Configuration
SDC70, P
SELC, BSYC, REQC,
ACKC, RSTC
SD70, P
SEL, BSY, REQ, ACK, RST
MSG, C/D, I/O, ATN
16506C-11
10 Am53C94/Am53C96
SCSI OUTPUT CONNECTIONS
Am53C96
Am53C96 Single Ended SCSI Bus Configuration
SDC70, P
SELC, BSYC, REQC,
ACKC, RSTC
SD70, P
SEL, BSY, REQ, ACK, RST
MSG, C/D, I/O, ATN
DFMODE
VCC
16506C-12
SDC70, P
SELC, BSYC, RSTC
SD70, P
SEL, BSY, RST
MSG, C/D, I/O, REQ
DFMODE
ATN, ACK
Am53C96 Differential SCSI Bus Configuration
TSEL
ISEL
Am53C96
DT
DT
DT
DT
16506C-13
11 Am53C94/Am53C96
TSEL
Vcc
Differential Transceiver Connections for the Differential SCSI Bus Configuration
Using 75ALS170 and 75ALS171 Transceivers
Vcc
SELC
GND
SEL
+ SEL
SEL
BSYC
GND
BSY
+ BSY
BSY
RSTC
GND
RST
+ RST
RST
GND
75ALS171
SDC 6
SD 6
SD 6
+ SD 6
SDC 7
SD 7
SD 7
+ SD 7
SDC P
SD P
SD P
+ SD P
75ALS170
SDC 3
SD 3
SD 3
+ SD 3
SDC 4
SD 4
SD 4
+ SD 4
SDC 5
SD 5
SD 5
+ SD 5
75ALS170
SDC 0
SD 0
SD 0
+ SD 0
SDC 1
SD 1
SD 1
+ SD 1
SDC 2
SD 2
SD 2
+ SD 2
75ALS170
ATN
ISEL
ATN
+ ATN
75ALS170
MSG
+ MSG
C/D
TSEL
MSG
TSEL
C/D
+ C/D
TSEL
I/O
I/O
+ I/O
75ALS170
REQC
ACKC
REQ
+ REQ
REQ
ISEL
ACK
+ ACK
ACK
75ALS171
GND
16506C-14
12 Am53C94/Am53C96
SDC 6
SD 6
Differential Transceiver Connections for the Differential
SCSI Bus Configuration Using 75176A Transceiver
SD 6
+ SD 6
SD 6
SDC 6
RSTC
GND
RST
+ RST
RST
GND
SDC 0
SD 0
SD 0
+ SD 0
SDC 0
SD 0
TSEL
MSG
MSG
+ MSG
MSG
TSEL
SDC 1
SD 1
SD 1
+ SD 1
SD 1
SDC 1
TSEL
C/D
C/D
+ C/D
C/D
TSEL
SDC 2
SD 2
SD 2
+ SD 2
SD 2
SDC 2
TSEL
I/O
I/O
+ I/O
I/O
TSEL
SDC 3
SD 3
SD 3
+ SD 3
SD 3
SDC 3
ISEL
ATN
ATN
+ ATN
ATN
ISEL
SDC 4
SD 4
SD 4
+ SD 4
SD 4
SDC 4
SELC
GND
SEL
+ SEL
SEL
GND
SDC 5
SD 5
SD 5
+ SD 5
SD 5
SDC 5
BSYC
GND
BSY
+ BSY
BSY
GND
SDC 7
SD 7
SD 7
+ SD 7
SD 7
SDC 7
TSEL
REQC
REQ
+ REQ
REQ
GND
SDC P
SD P
SD P
+ SD P
SD P
SDC P
ISEL
ACKC
ACK
+ ACK
ACK
GND
16506C-15
13 Am53C94/Am53C96
PIN DESCRIPTION
Host Interface Signals
DMA 150
Data/DMA Bus
(Input/Output, Active High, Internal Pull-up)
The configuration of this bus depends on the Bus Mode
10 (BUSMD 10) inputs. When the device is config-
ured for a single bus operation, the host can access the
internal register set on the lower eight lines and the DMA
accesses can be made to the FIFO using entire bus.
When using the Byte Mode via the BHE and A0 inputs
the data can be transferred on either the upper or lower
half of the DMA 150 bus.
DMAP 10
Data/DMA Parity Bus
These lines are odd parity for the DMA 150 bus. DMAP
1 is the parity for the upper half of the bus DMA 158 and
DMAP 0 is the parity for the lower half of the bus
DMA 70.
ALE [A3]
Address Latch Enable [Address 3]
(Input, Active High)
This is a dual function input. When the device is config-
ured for the dual bus mode (two buses, multiplexed and
byte control), this input acts as ALE. As ALE, this input
latches the address on the AD 70 bus on its Low going
edge. When the device is configured for all other bus
modes, this input acts as A3. As A3, this input is the third
bit of the address bus.
DMARD [A2]
DMA Read [Address 2]
(Input, Active Low [Active High])
byte control), this input acts as DMARD. As DMARD,
this input is the read signal for the DMA 150 bus. When
the device is configured for all other bus modes, this in-
put acts as A2. As A2, this input is the second bit of the
address bus.
BHE [A1]
Bus High Enable [Address 1]
byte control), this input acts as BHE. As BHE, this input
works in conjunction with AS0 to indicate the lines on
which data transfer will take place. When the device is
configured for all other bus modes this input acts as A1.
As A1, this input is the first bit of the address bus.
AS0 [A0]
Address Status [Address 0]
byte control), this input acts as AS0. As AS0, this input
works in conjunction with BHE to indicate the lines on
which data transfer will take place. When the device is
configured for all other bus modes, this input acts as A0.
As A0, this input is the zeroth bit of the address bus.
The following is the decoding for the BHE and AS0
inputs:
BHE AS0 Bus Used
1 1 Upper Bus DMA 158, DMAP 1
1 0 Full Bus DMA 150, DMAP 10
0 1 Reserved
0 0 Lower Bus DMA 70, DMAP 0
DREQ
DMA Request
(Output, Active High, Hi-Z)
This output signal to the DMA controller will be active
during DMA read and write cycles. During a DMA read
cycle it will be active as long as there is a word (or a byte
in the byte mode) in the FIFO to be transferred to mem-
ory. During a DMA write cycle it will be active as long as
there is an empty space for a word (or a byte in the byte
mode) in the FIFO.
DACK
DMA Acknowledge
(Input, Active Low)
This input signal from the DMA controller will be active
during DMA read and write cycles. The DACK signal is
used to access the DMA FIFO only and should never be
active simultaneously with the CS signal, which ac-
cesses the registers only.
AD 70
Host Address Data Bus
This bus is used only in the dual bus mode. This bus al-
lows the host processor to access the devices internal
registers while the DMA bus is transferring data. When
using multiplexed bus, these lines can be used for ad-
dress and data. When using non multiplexed bus these
lines can be used for the data only.
14 Am53C94/Am53C96
DMAWR
DMA Write
(Input, Active Low)
This signal writes the data on the DMA 150 bus into the
internal FIFO when DACK is also active. When in the
single bus mode this signal must be tied to the WR
signal.
RD
Read
(Input Active Low)
This signal reads the internal device registers and
places their contents on the data bus, when either CS
signal or DACK signal is active.
WR
Write
(Input Active Low)
This signal writes the internal device registers with the
value present on the data bus, when the CS signal is
also active.
CS
Chip Select
(Input Active Low)
This signal enables the read and write of the device reg-
isters. CS enables access to any register (including the
FIFO) while the DACK enables access only to the FIFO.
CS and DACK should never be active simultaneously in
the single bus mode, they may however be active simul-
taneously in the dual bus mode provided the CS signal is
not enabling access to the FIFO.
INT
Interrupt
(Output, Active Low, Open Drain)
This signal is a non maskable interrupt flag to the host
processor. This signal is latched on the output on the
high going edge of the clock. This flag may be cleared by
reading the Interrupt Status Register (ISTAT) or by per-
forming a device reset (hard or soft). This flag is not
cleared by a SCSI reset.
DFMODE
Differential Mode
(Input, Active Low)
This input is available only on the Am53C96. This input
configures the SCSI bus to either single ended or differ-
ential mode. When this input is active, the device oper-
ates in the differential SCSI mode. The SCSI data is
available on the SD 70 lines and the high active trans-
ceiver enables on the SDC 70 outputs. When this input
is inactive, the device operates in the single ended SCSI
mode. The SCSI input data is available on SD 70 lines
and the output data is available on SDC 70 lines. In the
single ended SCSI mode, the SD 70 and the SDC 70
buses can be tied together externally.
BUSMD 10
Bus Mode
These inputs configure the device for single bus or dual
bus operation and the DMA width.
BUSMD1 BUSMD0 Bus Configuration
1 1 Two buses: 8-bit Host Bus
and 16-bit DMA Bus
Register Address on A 30
and Data on AD Bus
1 0 Two buses: Multiplexed
and byte control
Register Address on AD 30
and Data on AD Bus
0 1 Single bus: 8-bit Host Bus
and 16-bit DMA Bus
and Data on DMA Bus
0 0 Single bus: 8-bit Host Bus
and 8-bit DMA Bus
and Data on DMA Bus
CLK
Clock
(Input)
Clock input used to generate all the internal device tim-
ings. The maximum frequency of this input is 25 MHz.
and a minimum of 10 MHz to maintain the SCSI bus
timings.
RESET
Reset
This input when active resets the device. The RESET in-
put must be active for at least two CLK periods after the
voltage on the power inputs have reached Vcc
minimum.
SCSI Interface Signals
SD 70
SCSI Data
(Input/Output, Active Low, Schmitt Trigger)
When the device is configured in the Single Ended SCSI
Mode (DFMODE inactive) these pins are defined as in-
puts for the SCSI data bus. When the device is config-
ured in the Differential SCSI Mode (DFMODE active)
these pins are defined as bidirectional SCSI data bus.
15 Am53C94/Am53C96
SDP
SCSI Data Parity
Mode (DFMODE inactive) this pin is defined as the input
for the SCSI data parity. When the device is configured
in the Differential SCSI Mode (DFMODE active) this pin
is defined as bidirectional SCSI data parity.
SDC 70
SCSI Data Control
Mode (DFMODE inactive) these pins are defined as out-
puts for the SCSI data bus. When the device is config-
these pins are defined as direction controls for the exter-
nal differential transceivers. In this mode, a signal high
state corresponds to an output to the SCSI bus and a
low state corresponds to an input from the SCSI bus.
SDCP
SCSI Data Control Parity
Mode (DFMODE inactive) this pin is defined as an out-
put for the SCSI data parity. When the device is config-
this pin is defined as the direction control for the external
differential transceiver. In this mode, a signal high state
corresponds to an output to the SCSI bus and a low
state corresponds to an input from the SCSI bus.
MSG
Message
This is a bidirectional signal with 48 mA output driver. It
is an output in the target mode and a Schmitt trigger in-
put in the initiator mode.
C/D
Command/Data
(Input/Output, Schmitt Trigger)
I/O
Input/Output
(Input/Output, Schmitt Trigger)
ATN
Attention
This signal is a 48 mA output in the initiator mode and a
Schmitt trigger input in the target mode. This signal will
be asserted when the initiator detects a parity error or it
can be asserted via certain initiator commands.
BSY
Busy
(Input, Active Low, Schmitt Trigger)
This is a SCSI input signal with a Schmitt trigger.
SEL
Select
RST
Reset
REQ
Request
ACK
Acknowledge
BSYC
Busy Control
This is a SCSI output with 48 mA drive. When the device
is configured in the Single Ended SCSI Mode (DFMODE
inactive) this pin is defined as a BSY output for the SCSI
bus. When the device is configured in the Differential
SCSI Mode (DFMODE active) this pin is defined as the
direction control for the external differential transceiver.
In this mode, a signal high state corresponds to an out-
put to the SCSI bus and a low state corresponds to an
input from the SCSI bus.
16 Am53C94/Am53C96
SELC
Select Control
This is a SCSI output with 48 mA drive. When the device
is configured in the Single Ended SCSI Mode (DFMODE
inactive) this pin is defined as a SEL output for the SCSI
bus. When the device is configured in the Differential
SCSI Mode (DFMODE active) this pin is defined as the
direction control for the external differential transceiver.
In this mode, a signal high state corresponds to an out-
put to the SCSI bus and a low state corresponds to an
input from the SCSI bus.
RSTC
Reset Control
This is a SCSI output with 48 mA drive. The Reset SCSI
command will cause the device to drive RSTC active for
25 ms40 ms, which will depend on the CLK frequency
and the conversion factor. When the device is config-
ured in the Single Ended SCSI Mode (DFMODE inac-
tive) this pin is defined as a RST output for the SCSI bus.
When the device is configured in the Differential SCSI
Mode (DFMODE active) this pin is defined as the direc-
tion control for the external differential transceiver. In
this mode, a signal high state corresponds to an output
to the SCSI bus and a low state corresponds to an input
from the SCSI bus.
REQC
Request Control
This is a SCSI output with 48 mA drive. This signal is ac-
tivated only in the target mode.
ACKC
Acknowledge Control
This is a SCSI output with 48 mA drive. This signal is ac-
tivated only in the initiator mode.
ISEL
Initiator Select
(Output, Active High)
This signal is available on the Am53C96 only. This sig-
nal is active whenever the device is in the initiator mode.
In the differential mode this signal is used to enable the
initiator signals ACKC and ATN and the device also
drives these signals.
TSEL
Target Select
(Output, Active High)
This signal is available on the Am53C96 only. This sig-
nal is active whenever the device is in the target mode.
In the differential mode this signal is used to enable the
target signals REQC, MSG, C/D and I/O and the device
also drives these signals.
FUNCTIONAL DESCRIPTION
Register Map
Address
(Hex.) Operation Register
00 Read Current Transfer Count
Register LSB
00 Write Start Transfer Count Register
LSB
01 Read Current Transfer Count
Register MSB
01 Write Start Transfer Count Register
MSB
02 Read/Write FIFO Register
03 Read/Write Command Register
04 Read Status Register
04 Write SCSI Destination ID Register
05 Read Interrupt Status Register
05 Write SCSI Timeout Register
Address
(Hex.) Operation Register
06 Read Internal State Register
06 Write Synchronous Transfer Period
Register
07 Read Current FIFO/Internal State
Register
07 Write Synchronous Offset Register
08 Read/Write Control Register 1
09 Write Clock Factor Register
0A Write Forced Test Mode Register
0B Read/Write Control Register 2
0C Read/Write Control Register 3
0F Write Data Alignment Register
Note:
Not all registers in this device are both readable and writable. Some read only registers share the same address with write only
registers. The registers can be accessed by asserting the CS signal and then asserting either RD or WR signal depending on the
operation to be performed. Only the FIFO Register can be accessed by asserting either CS or DACK in conjunction with RD and
WR signals or DMARD and DMAWR signals. The register address inputs are ignored when DACK is used but must be valid
when CS is used.
17 Am53C94/Am53C96
Current Transfer Count Register
(00H01H) Read Only
Current Transfer Count Register
CTCREG
Address: 00H01H
Type: Read
15 14 13 12 11 10 9 8
CRVL15 CRVL14 CRVL13 CRVL12 CRVL11 CRVL10 CRVL9 CRVL8
x x x x x x x x
7 6 5 4 3 2 1 0
CRVL7 CRVL6 CRVL5 CRVL4 CRVL3 CRVL2 CRVL1 CRVL0
x x x x x x x x
16506C-16
CTCREG Bits 15:0 CRVL 15:0 Current
Value 15:0
This is a two-byte register. It counts down to keep track
of the number of DMA transfers. Reading this registers
will return the current value of the counter. The counter
will decrement by one for every byte transferred and two
for every word transferred over the SCSI bus. The trans-
action is complete when the count reaches zero. These
registers are automatically loaded with the values in the
Start Transfer Count Register every time a DMA com-
mand is issued.
In the target mode, this counter is decremented by the
active edge of DACK during the Data-In phase and by
REQC during the Data-Out phase.
In the initiator mode, the counter is decremented by the
active edge of DACK during the Synchronous Data-In
phase or by ACKC during the Asynchronous Data-In
phase and by DACK during the Data-Out phase.
Start Transfer Count Register (00H01H)
Write Only
Start Transfer Count Register
STCREG
Address: 00H01H
Type: Write
15 14 13 12 11 10 9 8
STVL15 STVL14 STVL13 STVL12 STVL11 STVL10 STVL9 STVL8
x x x x x x x x
7 6 5 4 3 2 1 0
STVL7 STVL6 STVL5 STVL4 STVL3 STVL2 STVL1 STVL0
x x x x x x x x
16506C-017
STCREG Bits 15:0 STVL 15:0 Start Value 15:0
This is a two-byte register. It contains the number of
bytes to be transferred during a DMA operation. The
value of this register is set to the number of bytes to be
transferred prior to a DMA transfer command. This reg-
ister retains its programmed value until it is overwritten
and is not affected by hardware or software reset.
Therefore, it is not necessary to reprogram the count for
subsequent DMA transfers of the same size. Writing a
zero to this register sets a maximum transfer count of
65536 bytes. The value in this register is undefined at
power-up.
FIFO Register (02H) Read/Write
FIFO Register
FFREG
Address: 02H
Type: Read/Write
7 6 5 4 3 2 1 0
FF7 FF6 FF5 FF4 FF3 FF2 FF1 FF0
0 0 0 0 0 0 0 0
16506C-18
FFREG Bits 7:0 FF 7:0 FIFO 7:0
The bottom of the 16x9 FIFO is mapped into the FIFO
Register address. By reading and writing this register
the bottom of the FIFO can be read or written. This is the
only register that can also be accessed by DACK along
with DMARD or DMAWR. This register is reset to zero
by hardware or software reset and also at the start of a
selection or reselection sequence.
Command Register (03H) Read/Write
Command Register
CMDREG
Address: 03H
Type: Read/Write
7 6 5 4 3 2 1 0
DMA CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0
x x x x x x x x
Command 6:0
Direct Memory
Access
16506C-019
Commands to the device are issued by writing to this
register. This register is two deep which allows for com-
mand queuing. The second command can be issued be-
fore the first one is completed. The Reset command and
the Stop DMA command are not queued and are exe-
cuted immediately. Reading this register will return the
command currently being executed (or the last com-
mand executed if there are no pending commands).
18 Am53C94/Am53C96
CMDREG Bit 7 DMA Direct Memory Access
The DMA bit when set notifies the device that the com-
mand is a DMA instruction, when reset it is a non-DMA
instruction. For DMA instructions the Current Transfer
Count Register (CTCREG) will be loaded with the con-
tents of the Start Transfer Count Register (STCREG).
The data is then transferred and the CTCREG is decre-
mented for each byte until it reaches zero.
CMDREG Bits 6:0 CMD 6:0 Command 6:0
These command bits decode the commands that the
device needs to perform. There are a total of 29
commands grouped into four categories. The groups
are Initiator Commands, Target Commands, Selection/
Reselection Commands and General Purpose Com-
mands.
Initiator Commands
CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 Command
0 0 1 0 0 0 0 Information Transfer
0 0 1 0 0 0 1 Initiator Command Complete Steps
0 0 1 0 0 1 0 Message Accepted
0 0 1 1 0 0 0 Transfer Pad Bytes
0 0 1 1 0 1 0 Set ATN
0 0 1 1 0 1 1 Reset ATN
Target Commands
0 1 0 0 0 0 0 Send Message
0 1 0 0 0 0 1 Send Status
0 1 0 0 0 1 0 Send Data
0 1 0 0 0 1 1 Disconnect Steps
0 1 0 0 1 0 0 Terminate Steps
0 1 0 0 1 0 1 Target Command Complete Steps
0 1 0 0 1 1 1 Disconnect
0 1 0 1 0 0 0 Receive Message Steps
0 1 0 1 0 0 1 Receive Command
0 1 0 1 0 1 0 Receive Data
0 1 0 1 0 1 1 Receive Command Steps
0 0 0 0 1 0 0 DMA Stop
Idle Commands
1 0 0 0 0 0 0 Reselect Steps
1 0 0 0 0 0 1 Select without ATN Steps
1 0 0 0 0 1 0 Select with ATN Steps
1 0 0 0 0 1 1 Select with ATN and Stop Steps
1 0 0 0 1 0 0 Enable Selection/Reselection
1 0 0 0 1 0 1 Disable Selection/Reselection
1 0 0 0 1 1 0 Select with ATN3 Steps
General Commands
0 0 0 0 0 0 0 No Operation
0 0 0 0 0 0 1 Clear FIFO
0 0 0 0 0 1 0 Reset Device
0 0 0 0 0 1 1 Reset SCSI Bus
19 Am53C94/Am53C96
Status Register (04H) Read
Status Register
STATREG
Address: 04H
Type: Read
7 6 5 4 3 2 1 0
INT IOE PE CTZ GCV MSG C/D I/O
0 0 0 0 0 x x x
Illegal Operation Error
Parity Error
Count to Zero
Group Code Valid
Message
Command/Data
Input/Output
Interrupt
16506C-20
This read only register contains flags to indicate the
status and phase of the SCSI transactions. It indicates
whether an interrupt or error condition exists. It should
be read every time the host is interrupted to determine
which device is asserting an interrupt. The data is
latched until the Interrupt Status Register is read. The
phase bits will be latched only if latching is enabled in the
Control Register 2, otherwise, it will indicate the current
SCSI phase. If command stacking is used, two inter-
rupts might occur. Reading this register will clear the
status information for the first interrupt and update the
Status Register for the second interrupt.
STATREG Bit 7 INT Interrupt
The INT bit is set when the device asserts the interrupt
output. This bit will be cleared by a hardware or software
reset. Reading the Interrupt Status Register will deas-
sert the interrupt output and also clear this bit.
STATREG Bit 6 IOE Illegal Operation Error
The IOE bit is set when an illegal operation is attempted.
This condition will not cause an interrupt, it will be de-
tected by reading the status register while servicing an-
other interrupt. The following conditions will cause the
IOE bit to be set:
I DMA and SCSI transfer directions are opposite.
I FIFO overflows.
I In initiator mode an unexpected phase change
detected during synchronous data transfer.
I Command Register overwritten.
This bit will be cleared by reading the Interrupt Status
Register or by a hard or soft reset.
STATREG Bit 5 PE Parity Error
The PE bit is set if the parity checking option is enabled
in Control Register 1 and the device detects a parity er-
ror on incoming SCSI data, command, status or mes-
sage bytes. Detection of a parity error condition will not
cause an interrupt but will be reported with other inter-
rupt causing conditions. When a parity error is detected
in the information phase of the initiator mode ATN is as-
serted on the SCSI bus.
This bit will be cleared by reading the Interrupt Status
Register or by a hard or soft reset.
STATREG Bit 4 CTZ Count To Zero
The CTZ bit is set when the Current Transfer Count
Register (CTCREG) has counted down to zero. This bit
will be reset when the CTCREG is written.
Reading the Interrupt Status Register will not affect this
bit. This bit will however be cleared by a hard or soft re-
set.
Note:
A non-DMA NOP will not reset the CTZ bit since it does
not load the CTCREG but a DMA NOP will reset this bit
since it loads the CTCREG.
STATREG Bit 3 GCV Group Code Valid
The GCV bit is set if the group code field in the Com-
mand Descriptor Block (CDB) is one that is defined by
the ANSI Committee in their document X3.131 1986. If
the SCSI-2 Feature Enable (S2FE) bit in the Control
Register 2 (CNTLREG2) is set, Group 2 commands will
be treated as ten byte commands and the GCV bit will be
set. If S2FE is reset then Group 2 commands will be
treated as reserved commands. Group 3 and 4 com-
mand will always be considered as reserved com-
mands. The device will treat all reserved commands as
six byte commands. Group 6 commands will always be
treated as vendor unique six byte commands and Group
7 commands will always be treated as vendor unique
ten byte commands.
The GCV bit is cleared by reading the Interrupt Status
Register (INSTREG) or by a hard or soft reset.
20 Am53C94/Am53C96
STATREG Bit 2 MSG Message
STATREG Bit 1 C/D Command/Data
STATREG Bit 0 I/O Input/Output
Bit2 Bit1 Bit0
MSG C/D I/O SCSI Phase
1 1 1 Message In
1 1 0 Message Out
1 0 1 Reserved
1 0 0 Reserved
0 1 1 Status
0 1 0 Command
0 0 1 Data_In
0 0 0 Data_Out
The MSG, C/D and I/O bits together can be referred to
as the SCSI Phase bits. They indicate the phase of the
SCSI bus. These bits may be latched or unlatched de-
pending on the option selected in Control Register 2
(CNTLREG2) by the Latch SCSI Phase (LSP) bit.
In the latched mode the SCSI phase bits are latched at
the end of a command and the latch is opened when the
Interrupt Status Register (INSTREG) is read. In the un-
latched mode, they indicate the phase of the SCSI bus
when this register is read.
SCSI Destination ID Register (04H) Write
RES RES RES RES RES
0 0 0 0 0
SCSI Destination ID Register
SDIDREG
Address: 04H
Type: Write
7 6 5 4 3 2 1 0
DID2 DID1 DID0
x x x
Reserved
Reserved
Reserved
Reserved
SCSI Destination ID 2:0
Reserved
16506C-21
SDIDREG Bits 7:3 RES Reserved
SDIDREG Bits 2:0 DID 2:0 Destination ID 2:0
The DID 2:0 bits are the encoded SCSI ID of the device
on the SCSI bus which needs to be selected or
reselected.
DID2 DID1 DID0 SCSI ID
1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 3
0 1 0 2
0 0 1 1
0 0 0 0
At power-up the state of these bits is undefined. The DID 2:0
bits are not affected by reset.
21 Am53C94/Am53C96
Interrupt Status Register (05H) Read
SRST ICMD DIS SR SO
0 0 0 0 0
Interrupt Status Register
INSTREG
Address: 05h
Type: READ
7 6 5 4 3 2 1 0
RESEL SELA SEL
0 0 0
Invalid Command
Disconnected
Service Request
Successful Operation
Selected with Attention
SCSI Reset
16506C-22
Selected
Reselected
The Interrupt Status Register (INSTREG) will indicate
the reason for the interrupt. This register is used with the
Status Register (STATREG) and Internal Status Regis-
ter (ISREG) to determine the reason for the interrupt.
Reading the INSTREG will clear all three registers.
INSTREG Bit 7 SRST SCSI Reset
The SRST bit will be set if a SCSI Reset is detected and
SCSI reset reporting is enabled via the DISR (bit 6) of
the CNTLREG1.
INSTREG Bit 6 ICMD Invalid Command
The ICMD bit will be set if the device detects an illegal
command code. This bit is also set if a command code
from a different mode is detected than the mode the de-
vice is currently in.
INSTREG Bit 5 DIS Disconnected
The DIS bit can be set in the target or the initiator mode
when the device disconnects from the SCSI bus. In the
target mode this bit will be set if a terminate or a com-
mand complete sequence causes the device to discon-
nect from the SCSI bus. In the Initiator mode this bit will
be set if the target disconnects or a selection or reselec-
tion timeout occurs.
INSTREG Bit 4 SR Service Request
The SR bit can be set in the target or the initiator mode
when another device on the SCSI bus has a service re-
quest. In the target mode this bit will be set when the in-
itiator asserts the ATN signal. In the Initiator mode this
bit is set whenever the target requests an information
transfer phase.
INSTREG Bit 3 SO Successful Operation
The SO bit can be set in the target or the initiator mode
when an operation is successfully complete. In the
target mode this bit will be set when any target mode
command is completed. In the initiator mode this bit is
set after a target has been successfully selected, after a
command is successfully completed and after an infor-
mation transfer command when the target requests a
message in phase.
INSTREG Bit 2 RESEL Reselected
The RESEL bit is set at the end of the reselection phase
indicating that the device has been reselected as an in-
itiator.
INSTREG Bit 1 SELA Selected with Attention
The SELA bit is set at the end of the selection phase indi-
cating that the device has been selected and that the
ATN signal was active during the selection.
INSTREG Bit 0 SEL Selected
The SEL bit is set at the end of the selection phase indi-
cating that the device has been selected and that the
ATN signal was inactive during the selection.
22 Am53C94/Am53C96
SCSI Timeout Register (05H) Write
SCSI Timeout Register
STIMREG
Address: 05H
Type: Write
7 6 5 4 3 2 1 0
STIM7 STIM6 STIM5 STIM4 STIM3 STIM2 STIM1 STIM0
x x x x x x x x
16506C-23
This register determines how long the initiator (target)
will wait for a target to respond to a selection (reselec-
tion) before timing out. It should be set to yield 250 ms to
comply with ANSI standards for SCSI.
STIMREG Bits 7:0 STIM 7:0 SCSI Timer 7:0
The value loaded in STIM 7:0 can be calculated from the
following formula:
STIM 7:0 =
[(SCSI Time Out) (Clock Frequency) / (8192 (Clock
Factor))]
Example:
SCSI Time Out (in seconds): 250 ms. (Recommended
by the ANSI Standard) = 250 x 103 s.
Clock Frequency: 20 MHz. (assume) = 20 x 106 Hz.
Clock Factor: CLKF 2:0 from Clock Conversion Regis-
ter (09H) = 5
STIM 7:0 = (250 x 103) X (20 x 106) / (8192 (5)) = 122
decimal
Internal State Register (06H) Read
Internal State Register
ISREG
Address: 06H
Type: Read
7 6 5 4 3 2 1 0
RES RES RES RES SOF IS2 IS1 IS0
x x x x 0 0 0 0
Reserved
Reserved
Reserved
Synchronous Offset Flag
Internal State 2:0
Reserved
16506C-24
The Internal State Register (ISREG) tracks the progress
of a sequence-type command. It is updated after each
successful completion of an intermediate operation. If
an error occurs, the host can read this register to deter-
mined at where the command failed and take the neces-
sary procedure for recovery. Reading the Interrupt
Status Register will clear this register.
ISREG Bits 7:4 RES Reserved
ISREG Bit 3 SOF Synchronous Offset Flag
The SOF is reset when the Synchronous Offset Register
(SOFREG) has reached its maximum value.
Note:
The SOF bit is active Low.
ISREG Bits 2:0 IS 2:0 Internal State 2:0
The IS 2:0 bits along with the Interrupt Status Register
(INSTREG) indicates the status of the successfully
completed intermediate operation. Refer to the Status
Decode section for more details.
23 Am53C94/Am53C96
Initiator Select without ATN Steps
Internal State Interrupt Status
Register (06H) Register (05H) Explanation
Bits 2:0 (Hex) Bits 7:0 (Hex)
0 20 Arbitration steps completed or disconnected or selection timeout
4 18 Selection with ATN steps fully executed
3 18 Sequence halted during command transfer due to premature phase change
(target)
2 18 Arbitration and selection completed; sequence halted because target failed to
assert command phase
Initiator Select with ATN Steps
4 18 Selection with ATN steps fully executed
3 18 Sequence halted during command transfer due to premature phase change;
some CDB bytes may not have been sent; check FIFO flags
2 18 Message out completed; sent one message byte with ATN true, then released
ATN; sequence halted because target failed to assert command phase after
message byte was sent
0 18 Arbitration and selection completed; sequence halted because target did not
assert message out phase; ATN still driven by HPSC
Initiator Select with ATN3 Steps
4 18 Selection with ATN3 steps fully executed
3 18 Sequence halted during command transfer due to premature phase change;
some CDB bytes may not have been sent; check FIFO flags
2 18 One, two, or three message bytes sent; sequence halted because target failed
to assert command phase after third message byte, or prematurely released
message out phase; ATN released only if third message byte was sent
assert message out phase; ATN still driven by HPSC
Initiator Select with ATN and Stop Steps
assert message out phase; ATN still asserted by HPSC
1 18 Message out completed; one message byte sent; ATN on
24 Am53C94/Am53C96
Target Selected without ATN Steps
2 11 Selected; received entire CDB; check group code valid bit; initiator asserted ATN
in command phase
1 11 Sequence halted in command phase due to parity error; some CDB bytes may
not have been received; check FIFO flags; initiator asserted ATN in command
phase
2 01 Selected; received entire CDB; check group code valid bit
1 01 Sequence halted in command phase because of parity error; some CDB bytes
may not have been received; check FIFO flags
0 01 Selected; loaded bus ID into FIFO; nullbyte message loaded into FIFO
Target Select with ATN Steps, SCSI2 Bit NOT SET
2 12 Selection complete; received one message byte and entire CDB; initiator as-
serted ATN during command phase
1 12 Halted in command phase; parity error and ATN true
0 12 Selected with ATN; stored bus ID and one message byte; sequence halted be-
cause ATN remained true after first message byte
2 02 Selection completed; received one message byte and the entire CDB
1 02 Sequence halted in command phase because of parity error; some CDB bytes
not received; check group code valid bit and FIFO flags
cause of parity error or invalid ID message
Target Select with ATN Steps, SCSI2 Bit SET
5 12 Halted in command phase; parity error and ATN true
4 12 ATN remained true after third message byte
cause of parity error or invalid ID message
6 02 Selection completed; received three message bytes and the entire CDB
5 02 Received three message bytes then halted in command phase because of parity
error; some CDB bytes not received; check group code valid bit and FIFO flags
402Parity error during second or third message byte
Target Receive Command Steps
2 18 Received entire CDB; initiator asserted ATN
1 18 Sequence halted during command transfer due to parity error; ATN asserted by
initiator
2 08 Received entire CDB
1 08 Sequence halted during command transfer due to parity error; check FIFO flags
Target Disconnect Steps
2 28 Disconnect steps fully executed; disconnected; bus is free
1 18 Two message bytes sent; sequence halted because initiator asserted ATN
0 18 One message byte sent; sequence halted because initiator asserted ATN
25 Am53C94/Am53C96
Target Terminate Steps
2 28 Terminate steps fully executed; disconnected; bus is free
1 18 Status and message bytes sent; sequence halted because initiator asserted
ATN
0 18 Status byte sent; sequence halted because initiator asserted ATN
Target Command Complete Steps
1 18 Status and message bytes sent; sequence halted because initiator set ATN
0 18 Status byte sent; sequence halted because initiator set ATN
2 08 Command complete steps fully executed
26 Am53C94/Am53C96
Synchronous Transfer Period Register (06H) Write
6
Synchronous Transfer Period Register
STPREG
Address: 06H
Type: Write
7 5 4 3 2 1 0
RES RES RES STP4 STP3 STP2 STP1 STP0
x x x 0 0 1 0 1
Reserved
Reserved
Synchronous Transfer Period 4:0
Reserved
16506C-25
The Synchronous Transfer Period Register (STPREG)
contains a 5-bit value indicating the number of clock cy-
cles each byte will take to be transferred over the SCSI
bus in synchronous mode. The minimum value allowed
is 5. The STPREG defaults to five after a hard or soft
reset.
STPREG Bits 7:5 RES Reserved
STPREG Bits 4:0 STP 4:0 Synchronous
Transfer Period 4:0
The STP 4:0 bits are programmed to specify the syn-
chronous transfer period or the number of clock cycles
for each byte transfer in the synchronous mode. The
minimum value for STP 4:0 is five. Missing table entries
follow the binary code.
Clocks/
STP4 STP3 STP2 STP1 STP0 Byte
0 0 1 0 0 5
0 0 1 0 1 5
0 0 1 1 0 6
0 0 1 1 1 7

1 1 1 1 1 31
0 0 0 0 0 32
0 0 0 0 1 33
0 0 0 1 0 34
0 0 0 1 1 35
27 Am53C94/Am53C96
Current FIFO/Internal State Register (07H) Read
Current FIFO/Internal State Register
CFISREG
Address: 07H
Type: Read
7 6 5 4 3 2 1 0
IS2 IS1 IS0 CF4 CF3 CF2 CF1 CF0
0 0 0 0 0 0 0 0
Internal State 2:0
Current FIFO 4:0
16506C-26
This register has two fields, the Current FIFO field and
the Internal State field.
CFISREG Bits 7:5 IS 2:0 Internal State 2:0
The Internal State Register (ISREG) tracks the progress
of a sequence-type command.
The IS 2:0 bits are duplicated from the IS 2:0 field in the
Internal State Register (ISREG) in the normal mode. If
the device is in the test mode, IS 0 is set to indicate that
the offset value is non zero. A non zero value indicates
that synchronous data transfer can continue. A zero
value indicates that the synchronous offset count has
been reached and no more data can be transferred until
an acknowledge is received.
CFISREG Bits 4:0 CF 4:0 Current FIFO 4:0
The CF 4:0 bits are the binary coded value of the num-
ber of bytes in the FIFO. These bits should not be read
when the device is transferring data since this count
may not be stable.
Synchronous Offset Register (07H) Write
Synchronous Offset Register
SOFREG
Address: 07H
Type: Write
7 6 5 4 3 2 1 0
SO3 SO2 SO1 SO0 RES RES RES RES
x x x x 0 0 0 0
Reserved
Reserved
Reserved
Synchronous Offset 3:0
Reserved
16506C-27
The Synchronous Offset Register (SOFREG) contains
a 4-bit count of the number of bytes that can be sent to
(or received from) the SCSI bus without an ACK (or
REQ). Bytes exceeding the threshold will be sent one
byte at a time (asynchronously). That is, each byte will
require an ACK/REQ handshake. To set up an asyn-
chronous transfer, the SOFREG is set to zero. The
SOFREG is set to zero after a hard or soft reset.
SOFREG Bits 7:4 RES Reserved
SOFREG Bits 3:0 SO 3:0 Synchronous Offset
3:0
The SO 4:0 bits are the binary coded value of the num-
ber of bytes that can be sent to (or received from) the
SCSI bus without an ACK (or REQ) signal.
28 Am53C94/Am53C96
Control Register One (08H) Read/Write
Control Register One
CNTLREG1
Address: 08H
Type: Read/Write
7 6 5 4 3 2 1 0
ETM DISR PTE PERE STE CID2 CID1 CID0
0 0 0 0 0 x x x
Disable Interrupt on SCSI Reset
Parity Test Enable
Parity Error Reporting Enable
Self Test Enable
Chip ID 2:0
Extended Timing Mode
16506C-28
The Control Register 1 (CNTLREG1) sets up the device
with various operating parameters.
CNTLREG1 Bit 7 ETM Extended Timing Mode
The ETM bit is set if an extra clock period is required be-
tween the data being driven on the bus and the REQ or
ACK being asserted. This is some times necessary in
high capacitive loading environments. The ETM bit is re-
set to zero by a hard or soft reset.
CNTLREG1 Bit 6 DISR Disable Interrupt on
SCSI Reset
The DISR bit masks the reporting of the SCSI reset.
When the DISR bit is set and a SCSI reset is asserted,
the device will disconnect from the SCSI bus and remain
idle without interrupting the host processor. When the
DISR bit is reset and a SCSI reset is asserted the device
will respond by interrupting the host processor. The
DISR bit is reset to zero by a hard or soft reset.
CNTLREG1 Bit 5 PTE Parity Test Enable
The PTE bit is for test use only. When the PTE bit is set
the parity on the output (SCSI or host processor) bus is
forced to the value of the MSB (bit 7) of the output data
from the internal FIFO. This allows parity errors to be
created to test the hardware and software. The PTE bit
is reset to zero by a hard or soft reset.
CNTLREG1 Bit 4 PERE Parity Error Report-
ing Enable
The PERE bit enables the checking and reporting of par-
ity errors on incoming SCSI bytes during the information
transfer phase. When the PERE bit set and a bad parity
is detected, the PE bit in the STATREG is will be set but
an interrupt will not be generated. In the initiator mode
the ATN signal will also be asserted on the SCSI bus.
When the PERE bit is reset and a bad parity occurs it is
not detected and no action is taken.
CNTLREG1 Bit 3 STE Self Test Enable
The STE bit is for test use only. When the STE bit is set
the device is placed in a test mode which enables the
device to access the test register at address 0AH. To re-
set this bit and to resume normal operation the device
must be issued a hard or soft reset.
CNTLREG1 Bit 2:0 CID 2:0 Chip ID 2:0
The Chip ID 2:0 bits specify the binary coded value of
the device ID on the SCSI bus. The device will arbitrate
with this ID and will respond to selection or reselection to
this ID. At power-up the state of these bit are undefined.
These bits are not affected by hard or soft reset.
29 Am53C94/Am53C96
Clock Factor Register (09H) Write
3
Clock Factor Register
CLKFREG
Address: 09H
Type: Write
7 6 5 4 2 1 0
RES RES RES RES RES CLKF2 CLKF1 CLKF0
x x x x x 0 1 0
Reserved
Reserved
Reserved
Reserved
Clock Factor 2:0
Reserved
16506C-29
The Clock Factor Register (CLKFREG) must be set to
indicate the input frequency range of the device. This
value is crucial for controlling various timings to meet the
SCSI specification. The selector can be calculated by
rounding off the quotient of (Input Clock Frequency in
MHz)/(5 MHz). The device has a frequency range of 10
to 25 MHz.
CLKFREG Bits 7:3 RES Reserved
CLKFREG Bits 2:0 CLKF 2:0 Clock Factor 2:0
The CLKF 2:0 bits specify the binary coded value of the
clock factor. The CLKF 2:0 bits will default to a value of 2
by a hard or soft reset.
Input Clock
CLKF2 CLKF1 CLKF0 Frequency in MHz
0 1 0 10
0 1 1 10.01 to 15
1 0 0 15.01 to 20
1 0 1 20.01 to 25
Forced Test Mode Register (0AH) Write
3
Forced Test Mode Register
FTMREG
Address: 0AH
Type: Write
7 6 5 4 2 1 0
RES RES RES RES RES FHI FIM FTM
x x x x x 0 0 0
Reserved
Reserved
Reserved
Reserved
Forced High Impedance Mode
Forced Initiator Mode
Forced Target Mode
Reserved
16506C-30
The Forced Test Mode Register (FTMREG) is for test
use only. The STE bit in the CNTLREG1 must be set for
the FTMREG to operate.
FTMREG Bits 7:3 RES Reserved
FTMREG Bit 2 FHI Forced High Impedance
Mode
The FHI bit when set places all the output and bidirec-
tional pins into a high impedance state.
30 Am53C94/Am53C96
FTMREG Bit 1 FIM Forced Initiator Mode
The FIM bit when set forces the device into the initiator
mode. The device will then execute all initiator com-
mands irrespective of the SCSI bus status.
FTMREG Bit 0 FTM Forced Target Mode
The FTM bit when set forces the device into the target
mode. The device will then execute all target commands
irrespective of the SCSI bus status.
Control Register Two (0BH) Read/Write
Control Register Two
CNTLREG2
Address: 0BH
Type: Read/Write
7 6 5 4 3 2 1 0
DAE LSP SBO TSDR S2FE ACDPE PGRP PGDP
0 0 0 0 0 0 0 0
Latch SCSI Phase
Select Byte Order
TriState DMA Request
SCSI2 Features Enable
Abort on Command/Data Parity Error
Pass Through/Generate Register Parity
Pass Through/Generate Data Parity
Data Alignment Enable
16506C-31
The Control Register 2 (CNTLREG2) sets up the device
with various operating parameters.
CNTLREG2 Bit 7 DAE Data Alignment Enable
The DAE bit is used in the initiator Synchronous Data-In
phase only. When the DAE bit is set one byte is reserved
at the end of the FIFO when the phase changes to the
Synchronous Data-In phase. The contents of this byte
will become the lower byte of the DMA word (16-bit)
transfer to the memory, the upper byte being the first
byte of the first word received from the SCSI bus.
Note:
If an interrupt is received for a misaligned boundary on a
phase change to synchronous data the following recov-
ery procedure may be followed. The host processor
should copy the byte at the start address in the host
memory to the Data Alignment Register 0FH (DALREG)
and then issue an information transfer command. The
first word the device will write to the memory (via DMA)
will consists of the lower byte from the DALREG and the
upper byte from the first byte received from the SCSI
bus.
The DAE bit must be set before the phase changes to
the Synchronous Data-In. The DAE bit is reset to zero by
a hard or soft reset or by writing the DALREG when in-
terrupted in the Synchronous Data-In phase.
CNTLREG2 Bit 6 LSP Latch SCSI Phase
The LSP bit is used to enable or disable the latching of
the SCSI phase bits (MSG, C/D and I/O) in the Status
Register (STATREG) 04H.
When the LSP bit is set the phase bits STSTREG Bits
2:0 are latched at the end of each command. This simpli-
fies software for stacked commands. When the LSP bit
is reset the phase bits STATREG Bits 2:0 reflect the
actual state of the SCSI phase lines at any instant of
time. The LSP bit is reset by a hard or soft reset.
CNTLREG2 Bit 5 SBO Select Byte Order
The SBO bit is used only when the BUSMD 1:0 = 10 to
enable or disable the byte control on the DMA interface.
When SBO is set and the BUSMD 1:0 = 10, the byte con-
trol inputs BHE and AS0 control the byte positions.
When SBO is reset the byte control inputs BHE and AS0
are ignored.
CNTLREG2 Bit 4 TSDR Tri-State DMA
Request
The TSDR bit when set sends the DREQ output signal to
high impedance state and the device ignores all activity
on the DMA request (DREQ) input. This is useful for
wiring-OR several devices that share a common DMA
request line. When the TSDR bit is reset the DREQ
output is driven to TTL levels.
CNTLREG2 Bit 3 S2FE SCSI2 Features
Enable
The S2FE bit allows the device to recognize two SCSI-2
features. The two features are extended message fea-
ture and the Group 2 command recognition.
Extended Message Feature: When the S2FE bit is set
and the device is selected with attention, the device will
monitor the ATN signal at the end of the first message
byte. If the ATN signal is active, the device will request
two more message bytes before switching to the com-
mand phase. If the ATN signal is inactive the device will
switch to the command phase. When the S2FE bit is re-
set the device as a target will request a single message
byte. As an initiator, the device will abort the selection
sequence if the target does not switch to the command
phase after receiving a single message byte.
31 Am53C94/Am53C96
Group 2 Command Recognition: When the S2FE bit is
set the group 2 commands are recognized as 10 byte
commands. The GCV (Group Code Valid) bit in the
STATREG (04H) is set. When the S2FE bit is reset, the
device will interpret the group 2 commands as reserved
commands and will request 6 byte commands. The
GCV bit in the STATREG will not be set in this case.
CNTLREG2 Bit 2 ACDPE Abort on Command/
Data Parity Error
The ACDPE bit when set allows the device to abort a
command or data transfer when a parity error is de-
tected. When the ACDPE bit is reset parity error is ig-
nored.
CNTLREG2 Bit 1 PGRP Pass Through/Gener-
ate Register Parity
The PGRP bit when set causes the data along with the
parity from the host to pass through to the FIFO under
the control of the CS and the WR signals. When the
PGRP bit is reset, the device generates the parity on the
data from the host before writing it to the FIFO.
When the device is placing the data on the SCSI bus, it
will check for an outgoing parity error if either the PGRP
bit is set or the PGDP (Pass Through/Generate Data
Parity) bit is set.
CNTLREG2 Bit 0 PGDP Pass Through/Gener-
ate Data Parity
The PGDP bit when set causes the data along with the
parity from the host to pass through to the FIFO under
the control of the DACK and the WR signals. When the
PGDP bit is reset, the device generates the parity on the
data from the host before writing it to the FIFO.
When the device is placing the data on the SCSI bus, it
will check for an outgoing parity error if either the PGDP
bit is set or the PGRP (Pass Through/Generate Register
Parity) bit is set.
4
Control Register Three
CNTLREG3
Address: 0CH
Type: Read/Write
7 6 5 3 2 1 0
RES RES RES RES RES LBTM MDM BS8
0 0 0 0 0 0 0 0
Reserved
Reserved
Reserved
Reserved
Last Byte Transfer Mode
Modify DMA Mode
Burst Size 8
Reserved
16506C-32
Control Register Three (0CH) Read/Write
CNTLREG3 Bits 7:3 RES Reserved
CNTLREG3 Bit 2 LBTM Last Byte Transfer
Mode
The LBTM bit specifies how the last byte in an odd byte
transfer is handled during 16-bit DMA transfers. This
mode is not used if byte control is selected via BUSMD
1:0 inputs and BSO (Byte Select Order) bit in the
CNTLREG2. This mode has no affect during 8-bit DMA
transfers and on transfers on the SCSI bus.
When the LBTM bit is set the DREQ signal will not be
asserted for the last byte, instead the host will read or
write the last byte from or to the FIFO. When the LBTM
bit is reset the DREQ signal will be asserted for the last
byte and the following 16-bit DMA transfer will contain
the last byte on the lower bus. If the transfer is a DMA
read the upper bus will be all ones.
The LBTM bit is reset by hard or soft reset.
CNTLREG3 Bit 1 MDM Modify DMA Mode
The MDM bit is used to modify the timing of the DACK
signal with respect to the DMARD and DMAWR signals.
The MDM bit is used in conjunction with the Burst Size 8
(BS8) bit in the CNTLREG3. Both bits have to be set for
proper operation.
When the MDM bit is set and the device is in a DMA read
or write mode the DACK signal will remain asserted
while the data is strobed by the DMARD or DMAWR sig-
nals. In the DMA read mode when BUSMD 1:0 = 11 the
DACK signal will toggle for every DMA read.
When the MDM bit is reset and the device is in a DMA
read or write mode the DACK signal will toggle every
time the data is strobed by the DMARD or DMAWR
signals.
32 Am53C94/Am53C96
CNTLREG3 Bit 0 BS8 Burst Size 8
The BS8 bit is used to modify the timing of the DREQ
signal with respect to the DMARD and DMAWR signals.
The BS8 bit is used in conjunction with the Modify DMA
Mode (MDM) bit in the CNTLREG3. Both bits have to be
set for proper operation.
When the BS8 bit is set the device delays the assertion
of the DREQ signal until 8 bytes or 4 words transfer is
possible.
When the BS8 bit is set and the device is in a DMA write
mode the DREQ signal will be asserted only when 8 byte
locations are available for writing. In the DMA read
mode the DREQ signal will go active under the following
circumstances:
At the end of a transfer,
I In the target mode,
when the transfer is complete
or
when the ATN signal is active
I In the initiator mode,
when the Current Transfer Register
is decremented to zero
or
after any phase change
In the middle of a transfer
I In the initiator mode,
when the last 8 bytes of the FIFO are full
during Synchronous Data-In transfer when the
Event Transfer Count Register is greater than
7 and the last 8 bytes of the FIFO are full.
When the BS8 bit is reset and the device is in a DMA
read or write mode the DREQ signal will toggle every
time the data is strobed by the DMARD or DMAWR
signals.
Using Bit 0 (BS8) and Bit 1 (MDM) of Control
Register 3, one can enable the different combination
modes shown in the table below.
Maximum
(MDM) (BS8) Function Synchronous
Bit 1 Bit 0 Offset
0 0 Normal DMA Mode 15
0 1 Burst Size 8 Mode 7
1 0 Reserved
1 1 Modified DMA Mode 15
Data Alignment Register (0FH) Write
16506C-33
The Data Alignment Register (DALREG) is used if the
first byte of a 16-bit DMA transfer from the SCSI bus to
the host processor is misaligned. Prior to issuing an in-
formation transfer command, the host processor must
set the Data Alignment Enable (DAE) bit in the
CNTLREG2.
DALREG Bits 7:0 DA 7:0 Data Alignment 7:0
33 Am53C94/Am53C96
COMMANDS
The device commands can be broadly divided into two
categories, DMA commands and non-DMA commands.
DMA commands are those which cause data movement
between the host memory and the SCSI bus while non-
DMA commands are those that cause data movement
between the device FIFO and the SCSI bus. The MSB of
the command byte differentiate the DMA from the non-
DMA commands.
Summary of Commands

Non-
DMA DMA
Mode Mode
Initiator Commands
Information Transfer 10 90
Initiator Command Complete Steps 11 91
Message Accepted 12
Transfer Pad Bytes 18 98
Set ATN 1A
Reset ATN 1B
Target Commands
Send Message 20 A0
Send Status 21 A1
Send Data 22 A2
Disconnect Steps 23 A3
Terminate Steps 24 A4
Target Command Complete Steps 25 A5
Disconnect 27 A7
Receive Message 28 A8
Receive Command Steps 29 A9
Receive Data 2A AA
Receive Command Steps 2B AB
Target Abort DMA 04 84

Non-
DMA DMA
Mode Mode
Idle State Commands
Reselect Steps 40 C0
Select without ATN Steps 41 C1
Select with ATN Steps 42 C2
Select with ATN and Stop Steps 43 C3
Enable Selection/Reselection 44 C4
Disable Selection/Reselection 45 C5
Select With ATN3 46 C6
General Commands
No Operation 00 80
Clear FIFO 01 81
Reset Device 02 82
Reset SCSI bus 03 83
Command Code
(Hex.)
Command Code
(Hex.)
Command Command
34 Am53C94/Am53C96
COMMAND DESCRIPTION
Initiator Commands
Initiator commands are executed by the device when it
is in the initiator mode. If the device is not in the initiator
mode and an initiator command is received the device
will ignore the command, generate an illegal command
interrupt and clear the Command Register (CMDREG)
03H.
Information Transfer Command
(Command Code 10H/90H)
The Information Transfer command is used to transfer
information bytes over the SCSI bus. This command
may be issued during any SCSI Information Transfer
phase. Information transfer for synchronous data must
use the DMA mode.
The device will continue to transfer information until it is
terminated by any one of the following conditions:
I The target changes the SCSI bus phase before the
expected number of bytes are transferred. The
device clears the Command Register (CMDREG)
03H, and generates a service interrupt when the
target asserts REQ.
I Transfer is successfully complete. If the phase is
Message Out, the device deasserts ATN before
asserting ACK for the last byte of the message.
When the target asserts REQ, a service interrupt is
generated.
I In the Message In phase when the device receives
the last byte. The device keeps the ACK signal
asserted and generates a Successful Operation
interrupt.
During synchronous data transfers the target may send
up to the maximum synchronous threshold number of
REQ pulses to the initiator. If it is the Synchronous Data-
In phase then the target sends the data and the REQ
pulses. These bytes are stored by the initiator in the
FIFO as they are received.
Information Transfer Command when issued during the
following SCSI phases and terminating in synchronous
data phases, is handled as described below:
I Message In/Status Phase When a phase change
to Synchronous Data-In or Synchronous Data-Out is
detected by the device, the Command Register
(CMDREG) 03H is cleared and the DMA interface is
disabled to disallow any transfer of data phase bytes.
If the phase change is to Synchronous Data-In and
bad parity is detected on the data bytes coming in, it
is not reported since the Status Register
(STATREG) 04H will report the status of the
command just completed. The parity error flag and
the ATN signal will be asserted when the Transfer
Information command begins execution.
I Message Out/Command Phase When a phase
change to Synchronous Data-In or Synchronous
Data-Out is detected by the device, the Command
Register (CMDREG) 03H is cleared and the DMA
interface is disabled to allow any transfer of data
phase bytes. If the phase change is to Synchronous
Data-In and bad parity is detected on the data bytes
coming in, it is not reported since the Status Register
(STATREG) 04H will report the status of the
command just completed. The parity error flag and
the ATN signal will be asserted when the Transfer
Information command begins execution. The FIFO
Register29 (FFREG) 02H will be latched and will
remain in that condition until the next command
begins execution. The value in the FFREG indicates
the number of bytes in the FIFO when the phase
changed to Synchronous Data-In. These bytes are
cleared from the FIFO, which now contains only the
incoming data bytes.
I In the Synchronous Data-Out phase, the threshold
counter is incremented as REQ pulses are received.
The transfer is completed when the FIFO is empty
and the Current Transfer Count Register (CTCREG)
00H01H is zero. The threshold counter will not be
zero.
I In the Synchronous Data-In phase, the Current
Transfer Count Register (CTCREG) is decre-
mented as bytes are read from the FIFO rather than
being decremented when the bytes are being written
to the FIFO. The transfer is completed when Current
Transfer Count Register (CTCREG) is zero but the
FIFO may not be empty.
Initiator Command Complete Steps
The Initiator Command Complete Steps command is
normally issued when the SCSI bus is in the Status In
phase. One Status byte followed by one Message byte
is transferred if this command completes normally. After
receiving the message byte the device will keep the
ACK signal asserted to allow the initiator to examine the
message and assert the ATN signal if it is unacceptable.
The command terminates early if the target does not
switch to the Message In phase or if the target discon-
nects from the SCSI bus.
Message Accepted Command
(Command Code 12H)
The Message Accepted Command is used to release
the ACK signal. This command is normally used to com-
plete a Message In handshake. Upon execution of this
command the device generates a service request inter-
rupt after REQ is asserted by the target.
35 Am53C94/Am53C96
After the device has received the last byte of message, it
keeps the ACK signal asserted. This allows the device
to either accept or reject the message. To accept the
message, Message Accepted Command is issued. To
reject the message the ATN signal must be asserted
(with the help of the Set ATN Command) before issuing
the Message Accepted Command. In either case the
Message Accepted Command has to be issued to re-
lease the ACK signal.
Transfer Pad Bytes Command
The Transfer Pad Bytes Command is used to recover
from an error condition. This command is similar to the
Information Transfer Command, only the information
bytes consists of null data. It is used when the target ex-
pects more data bytes than the initiator has to send. It is
also used when the initiator receives more information
than it expected from the target.
When sending data to the SCSI bus, the FIFO is loaded
with null bytes and these bytes are sent out to the SCSI
bus. DMA has to be enabled when pad bytes are trans-
ferred to the SCSI bus. No actual DMA requests are
made but the device uses the Current Transfer Count
Register (CTCREG) 00H01H to terminate the
transfer.
When receiving data from the SCSI bus, the device will
receive the pad bytes and place them on the top of the
FIFO and unload them from the bottom of the FIFO.
The command terminates under the same condition as
the Information Transfer Command, only the device
does not keep the ACK signal asserted during the last
byte of the Message In phase. If this command termi-
nates prematurely, due to a disconnect or a phase
change, before the CTCREG decrements to zero, the
FIFO may contain residual pad bytes.
Set ATN Command (Command Code 1AH)
The Set ATN Command is used to drive the ATN signal
active on the SCSI bus. An interrupt is not generated at
the end of this command. The ATN signal is deasserted
before asserting the ACK signal during the last byte of
the Message Out phase.
Note:
The ATN signal is asserted by the device without this
command in the following cases:
I If any select with ATN command is issued and the
arbitration is won.
I An initiator needs the targets attention to send a
message. The ATN signal is asserted before deas-
serting the ACK signal.
Reset ATN Command (Command Code 1BH)
The Reset ATN Command is used to deassert the ATN
signal on the SCSI bus. An interrupt is not generated at
the end of this command. This command is used only
when interfacing with devices that do not support the
Common Command Set (CCS). These older devices do
not deassert their ATN signal automatically on the last
byte of the Message Out phase. This device does deas-
sert its ATN signal automatically on the last byte of the
Message Out phase.
Target Commands
Target commands are executed by the device when it is
in the target mode. If the device is not in the target mode
and a target command is received the device will ignore
the command, generate an illegal command interrupt
and clear the Command Register (CMDREG) 03H.
A SCSI bus reset during any target command will cause
the device to abort the command sequence , flag a SCSI
bus reset interrupt (if the interrupt is enabled) and dis-
connect from the SCSI bus.
Normal or successful completion of a target command
will cause a Successful Operation interrupt to be
flagged. If the ATN signal is asserted during a target
command sequence the Service Request bit is asserted
in the Interrupt Status Register (INSTREG) 05H. If the
ATN signal is asserted when the device is in an idle state
a Service Request interrupt will be generated, the Suc-
cessful Operation bit in the INSTREG will be reset and
the CMDREG cleared.
Send Message Command
(Command Code 20H/A0H)
The Send Message Command is used by the target to
inform the initiator to receive a message. The SCSI bus
phase lines are set to the Message In Phase and mes-
sage bytes are transferred from the device FIFO to the
buffer memory.
Send Status Command
The Send Status Command is used by the target to in-
form the initiator to receive status information. The SCSI
bus phase lines are set to the Status Phase and status
bytes are transferred from the target device to the initia-
tor device.
Send Data Command (Command Code 22H/A2H)
The Send Data Command is used by the target to inform
the initiator to receive data bytes. The SCSI bus phase
lines are set to the Data-In Phase and data bytes are
transferred from the target device to the initiator device.
Disconnect Steps Command
The Disconnect Steps Command is used by the target to
disconnect from the SCSI bus. This command consists
of two steps. The first step consists of sending two bytes
of the Save Data Pointers commands by the target in the
Message In Phase. In the second step the target discon-
nects from the SCSI bus. Successful Operation and Dis-
connected bits are set in the Interrupt Status Register
(INSTREG) 05H upon command completion. If ATN sig-
nal is asserted by the initiator then Successful Operation
and Service Request bits are set in the INSTREG, the
CMDREG is cleared and Disconnect Steps Command
terminates without disconnecting.
36 Am53C94/Am53C96
Terminate Steps Command
The Terminate Steps Command is used by the target to
disconnect from the SCSI bus. This command consists
of three steps. The first step consists of sending one
status byte by the target in the Status Phase. The sec-
ond step consists of sending one message byte by the
target in the Message In Phase. As the third step the tar-
get disconnects from the SCSI bus. Successful Opera-
tion and Disconnected bits are set in the Interrupt Status
Register (INSTREG) 05H upon command completion. If
ATN signal is asserted by the initiator then Successful
Operation and Service Request bits are set in the IN-
STREG, the CMDREG is cleared and Terminate Steps
Command terminates without disconnecting.
Target Command Complete Steps Command
The Target Command Complete Steps Command is
used by the target to inform the initiator of a linked com-
mand completion. This command consists of two steps.
The first step consists of sending one status byte by the
target in the Status Phase. The second step consists of
sending one message byte by the target in the Message
In Phase. The Successful Operation bit is set in the In-
terrupt Status Register (INSTREG) 05H upon command
completion. If ATN signal is asserted by the initiator then
Successful Operation and Service Request bits are set
in the INSTREG, the CMDREG is cleared and Target
Command Complete Steps Command terminates
prematurely.
Disconnect Command
The Disconnect Command is used by the target to dis-
connect from the SCSI bus. All SCSI bus signals except
RSTC are released and the device returns to the Dis-
connected state. The RSTC signal is driven active for
about 25 micro seconds (depending on clock frequency
and clock factor). Interrupt is not generated to the micro-
processor.
Receive Message Steps Command
(Command Code 28H A8H)
The Receive Message Steps Command is used by the
target to request message bytes from the initiator. Dur-
ing this command the target receives the message
bytes from the initiator while the SCSI bus is in the Mes-
sage Out Phase. The Successful Operation bit is set in
the Interrupt Status Register (INSTREG) 05H upon
command completion. If ATN signal is asserted by the
initiator then Successful Operation and Service Re-
quest bits are set in the INSTREG, the CMDREG is
cleared. If a parity error is detected, the device ignores
the received message bytes until ATN signal is as-
serted, the Successful Operation bit is set in the IN-
STREG, and the CMDREG is cleared.
Receive Commands Command
The Receive Commands Command is used by the tar-
get to request the initiator for command bytes. During
this command the target receives the command bytes
from the initiator while the SCSI bus is in the Command
Phase. The Successful Operation bit is set in the Inter-
rupt Status Register (INSTREG) 05H upon command
completion. If ATN signal is asserted by the initiator then
Successful Operation and Service Request bits are set
in the INSTREG, the CMDREG is cleared and the com-
mand terminates prematurely. If a parity error is de-
tected, the device continues to receive command bytes
until the transfer is complete if the Abort on Command/
Data Parity Error (ACDPE) bit in the Control Register
(CNTLREG2) 0BH is reset. If the ACDPE bit is set, the
command is terminated immediately. The Parity Error
(PE) bit in the Status Register (STATREG) 04H is set
and CMDREG is cleared.
Receive Data Command
(Command Code 2AH/AAH)
The Receive Data Command is used by the target to re-
quest the initiator for data bytes. During this command
the target receives the data bytes from the initiator while
the SCSI bus is in the Data-Out Phase. The Successful
Operation bit is set in the Interrupt Status Register (IN-
STREG) 05H upon command completion. If ATN signal
is asserted by the initiator then Successful Operation
and Service Request bits are set in the INSTREG, the
CMDREG is cleared and the command terminates pre-
maturely. If a parity error is detected, the device contin-
ues to receive data bytes until the transfer is complete if
the Abort on Command/Data Parity Error (ACDPE) bit in
the Control Register (CNTLREG2) 0BH is reset. If the
ACDPE bit is set, the command is terminated immedi-
ately. The Parity Error (PE) bit in the Status Register
(STATREG) 04H is set and CMDREG is cleared.
Receive Command Steps Command
(Command Code 2BH/ABH)
The Receive Command Steps Command is used by the
target to request the initiator for command information
bytes. During this command the target receives the
command information bytes from the initiator while the
SCSI bus is in the Command Phase.
The target device determines the command byte length
from the first command byte. If an unknown length is re-
ceived, the Start Transfer Count Register (STCREG)
00H01H is loaded with 5 and the Group Code Valid
(GCV) bit in the Status Register (STATREG) 04H is re-
set. If a valid length is received, the STCREG is loaded
with the appropriate value and the GCV bit in the
STATREG is set. If ATN signal is asserted by the initia-
tor then the Service Request bit is set in the INSTREG,
and the CMDREG is cleared If a parity error is detected,
the command is terminated prematurely and the
CMDREG is cleared.
DMA Stop Command (Command Code 04H/84H)
The DMA Stop Command is used by the target to allow
the microprocessor to discontinue data transfers due to
a lack of activity on the DMA channel. This command is
executed from the top of the command queue. If there is
a queued command waiting execution, it will be over-
written and the Illegal Operation Error (IOE) bit in the
37 Am53C94/Am53C96
Status Register (STATREG) 04H will be set. This com-
mand is cleared from the command queue once it is
decoded.
Caution must be exercised when using this command.
The DMA Stop Command can be used only during a
DMA Target Send Data Command or DMA Target Re-
ceive Data Command execution. In both cases the DMA
controller has to be in the idle state.
During a DMA Target Send Data Command the FIFO
has to be empty or the Current FIFO (CF 4:0) bits in the
Current FIFO/Internal State Register (CFISREG) 07H
are zero.
During a DMA Synchronous Target Receive Data Com-
mand the Current Transfer Count Register (CTCREG)
0001H is zero, which is indicated by the Count to Zero
(CTZ) bit of the Status Register (STATREG) 04H. or
when the Synchronous Offset Register (SOFREG) 07H
has reached its maximum value which is indicated by
the Synchronous Offset Flag (SOF) bit of the Internal
State Register (ISREG) 06H.
During a DMA Asynchronous Target Receive Data
Command the FIFO is full which is indicated by the Cur-
rent FIFO (CF 4:0) bits in the Current FIFO/Internal
State Register (CFISREG) 07H being all high or Current
Transfer Count Register (CTCREG) 0001H is zero,
which is indicated by the Count to Zero (CTZ) bit of the
Status Register (STATREG) 04H.
Idle State Commands
The Idle State Commands can be issued to the device
only when the device is disconnected from the SCSI
bus. If these commands are issued to the device when it
is logically connected to the SCSI bus, the commands
are ignored, and the device will generate an illegal com-
mand interrupt and clear the Command Register
(CMDREG) 03H.
Reselect Steps Command
(Command Code 40H/C0H)
The Reselect Steps Command is used by the target de-
vice to reselect an initiator device. When this command
is issued the device arbitrates for the control of the SCSI
bus. If the device wins arbitration, it reselects the initia-
tor device and transfers a single byte identify message.
Before issuing this command the SCSI Timeout Regis-
ter (STIMREG) 05H, the Control Register One
(CNTLREG1) 08H and the SCSI Destination ID Regis-
ter (SDIDREG) 04H must be set to the proper values. If
DMA is enabled, the Start Transfer Count Register
(STCREG) 00H01H must be set to one. If DMA is not
enabled, the single byte identify message must be
loaded into the FIFO before issuing this command. This
command will be terminated early if the SCSI Timeout
Register times out. This command also resets the Inter-
nal State Register (ISREG) 06H.
Select without ATN Steps Command
The Select without ATN Steps Command is used by the
initiator to select a target. When this command is issued
the device arbitrates for the control of the SCSI bus.
When the device wins arbitration, it selects the target
device and transfers the Command Descriptor Block
(CDB). Before issuing this command the SCSI Timeout
Register (STIMREG) 05H, the Control Register One
(STCREG) 00H01H must be set to the total length of
the command. If DMA is not enabled, the data must be
command will be terminated early if the SCSI Timeout
Register times out or if the target does not go to the
Command Phase following the Selection Phase or if the
target exits the Command Phase early.
Select with ATN Steps Command
The Select with ATN Steps Command is used by the in-
itiator to select a target. When this command is issued
the device arbitrates for the control of the SCSI bus.
When the device wins arbitration, it selects the target
device with the ATN signal asserted and transfers the
Command Descriptor Block (CDB) and a one byte mes-
sage. Before issuing this command the SCSI Timeout
Register (STIMREG) 05H, the Control Register One
(STCREG) 00H01H must be set to the total length of
the command. If DMA is not enabled, the data must be
command will be terminated early in the following situ-
ations:
I The SCSI Timeout Register times out
I The target does not go to the Message Out Phase
following the Selection Phase
I The target exits the Message Phase early
I The target does not go to the Command Phase
I The target exits the Command Phase early.
Select with ANT and Stop Steps Command
The Select with ATN and Stop Steps Command is used
by the initiator to select a target. When this command is
issued the device arbitrates for the control of the SCSI
bus. When the device wins arbitration, it selects the tar-
get device with the ATN signal asserted and transfers
the Command Descriptor Block (CDB) and stops after
one message byte is sent, but the ATN signal is not
38 Am53C94/Am53C96
deasserted at the end of the command which allows the
initiator to send other messages after the ID message is
sent out. Before issuing this command the SCSI
Timeout Register (STIMREG) 05H, the Control Register
One (CNTLREG1) 08H and the SCSI Destination ID
Register (SDIDREG) 04H must be set to the proper val-
ues. This command will be terminated early if the SCSI
Timeout Register times out or if the target does not go to
the Message Out Phase following the Selection Phase.
Enable Selection/Reselection Command
The Enable Selection/Reselection Command is used by
the target to respond to a bus-initiated reselection. Upon
disconnecting from the bus the Selection/Reselection
circuit is automatically disabled by device. This circuit
has to be enabled for the device to respond to subse-
quent reselection attempts and the Enable Selection/
Reselection Command is issued to do that. This com-
mand is normally issued within 250 ms (select/reselect
timeout) after the device disconnects from the bus. If
DMA is enabled the device loads the received data to
the buffer memory, but if the DMA is disabled, the re-
ceived data stays in the FIFO.
Disable Selection/Reselection Command
The Disable Selection/Reselection Command is used
by the target to disable response to a bus-initiated
reselection. When this command is issued before a bus
initiated selection or reselection is initiated, it resets the
internal mode bits previously set by the Enable Selec-
tion/Reselection Command. The device also generates
a function complete interrupt to the processor. If how-
ever, this command is issued after a bus initiated selec-
tion/reselection has already begun the command is ig-
nored since the Command Register is held reset and all
incoming commands are ignored. The device generates
a selected or reselected interrupt when the sequence is
complete.
Select with ATN3 Steps Command
The Select with ATN3 Steps Command is used by the
initiator to select a target. This command is similar to the
Select with ATN Steps Command, except that it sends
exactly three message bytes. When this command is
issued the device arbitrates for the control of the SCSI
bus. When the device wins arbitration, it selects the
target device with the ATN signal asserted and transfers
the Command Descriptor Block (CDB) and three
message bytes. Before issuing this command the SCSI
Timeout Register (STIMREG) 05H, the Control Register
One (CNTLREG1) 08H and the SCSI Destination ID
Register (SDIDREG) 04H must be set to the proper
values. If DMA is enabled, the Start Transfer Count
Register (STCREG) 00H01H must be set to the total
length of the command. If DMA is not enabled, the data
must be loaded into the FIFO before issuing this
command. This command will be terminated early in the
following situations:
I The SCSI Timeout Register times out
I The target does not go to the Message Out Phase
I The target exits the Message Phase early
I The target does not go to the Command Phase
I The target exits the Command Phase early.
General Commands
No Operation Command
The No Operation Command is used to perform no op-
eration and no interrupt is generated at the end of this
command. This command is issued after the Reset De-
vice Command to enable the Command Register. A No
Operation Command in the DMA mode may be used to
verify the contents of the Start Transfer Count Register
(STCREG) 00H 01H. After the STCREG is loaded with
the transfer count and a No Operation Command is is-
sued, reading the Current Transfer Count Register
(CTCREG) 00H01H will give the transfer count value.
Clear FIFO Command
The Clear FIFO Command is used to initialize the FIFO
to the empty condition. The Current FIFO Register
(CFISREG) 07H reflects the empty FIFO status and the
bottom of the FIFO is set to zero. No interrupt is gener-
ated at the end of this command.
Reset Device Command
The Reset Device Command immediately stops any de-
vice operation and resets all the functions of the device.
It returns the device to the disconnected state and it also
generates a hard reset. The Reset Device Command re-
mains on the top of the Command Register FIFO hold-
ing the device in the reset state until the No Operation
Command is loaded. The No Operation command
serves to enable the Command Register.
Reset SCSI Bus Command
The Reset SCSI Bus Command is used to assert the
RSTC signal for approximately 25 ms. This command
causes the device to go to the disconnected state. No
interrupt is generated upon command completion. A
SCSI reset interrupt is however generated upon com-
mand completion if the interrupt is not disabled in the
Control Register One (CNTLREG1) 08H.
39 Am53C94/Am53C96
ABSOLUTE MAXIMUM RATINGS
Storage Temperature 65C to +150C . . . . . . . . . . .
Ambient Temperature Under Bias 55C to +125C .
VDD 0.5 V to +7.0 V . . . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Applied to Any Pin 0.5 to (VDD +0.5) V .
Input Static Discharge Protection 4000 V pin to pin . .
(Human body model: 100 pF at 1.5K )
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maxi-
mum ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial Devices
Ambient Temperature (TA) 0C to +70C . . . . . . .
Supply Voltage (VDD) +4.75 V to +5.25 V . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
40 Am53C94/Am53C96
DC OPERATING CHARACTERISTICS
IDDS Static Supply Current VDD MAX 4.0 mA
IDDD Dynamic Supply Current VDD MAX 35 mA
ILU Latch Up Current All I/O VLU 10 V 100 +100 mA
C Capacitance All Pins 10 pF
VIH Input High Voltage All SCSI Inputs 2.0 VDD + 0.5 V
VIL Input Low Voltage All SCSI Inputs VSS 0.5 0.8 V
VIHST Input Hysterisis All SCSI Inputs 4.75 V < VDD < 5.25 V 300 mV
VOH Output High Voltage SD 70, SDP IOH = 2 mA 2.4 VDD V
VSOL1 SCSI Output Low Voltage SD 70, SDP IOL= 4 mA VSS 0.4 V
VSOL2 SCSI Output Low Voltage SDC 70, SDCP, IOL= 48 mA VSS 0.5 V
MSG, C/D, I/O,
ATN, RSTC,
SELC, BSYC,
ACKC and REQC
IIL Input Low Leakage 0.0 V < VIN < 2.7 V 10 +10 A
IIH Input High Leakage 2.7 V < VIN < VDD 10 +10 A
IOZ High Impedance Leakage 0 V < VOUT < VDD 10 +10 A
VIH Input High Voltage 2.0 VDD + 0.5 V
VIL Input Low Voltage VSS 0.5 0.8 V
VOH Output High Voltage DMA 150, IOH = 2 mA 2.4 VDD V
DMAP 10 and
AD 70
VOL Output Low Voltage DMA 150, IOL= 4 mA VSS 0.4 V
DMAP 10 and
AD 70
IIL Input Low Leakage DMA 150, VIN = VIL 400 +10 A
DMAP 10 and
AD 70
IIH Input High Leakage DMA 150, VIN = VIH 10 +10 A
DMAP 10 and
AD 70
IOZ High Impedance Leakage 0 V < VOUT < VDD 100 400 A
VOH Output High Voltage DREQ, ISEL, IOH = 2 mA 2.4 VDD V
TSEL
VOL Output Low Voltage DREQ, ISEL, IOL= 4 mA VSS 0.4 V
TSEL
IOZ High Impedance Leakage 0 V < VOUT < VDD 10 +10 A
Parameter
Symbol Parameter Description Pin Names Test Conditions Min Max Unit
SCSI Pins
Bidirectional Pins
Output Pins
41 Am53C94/Am53C96
DC OPERATING CHARACTERISTICS (continued)
Parameter
Symbol Parameter Description Pin Names Test Conditions Min Max Unit
VIH Input High Voltage A 3-0, CS, RD. WR, 2.0 VCC + 0.5 V
DMAWR, CLK,
BUSMD 1-0, DACK,
RESET, and
DFMODE
VIL Input Low Voltage A 3-0, CS, RD. WR, VSS + 0.5 0.8 V
DMAWR, CLK,
BUSMD 1-0, DACK,
RESET, and
DFMODE
IIL Input Low Leakage A 3-0, CS, RD. WR, 10 +10 A
DMAWR, CLK,
BUSMD 1-0, DACK,
RESET, and
DFMODE
IIH Input High Voltage A 3-0, CS, RD. WR, 10 +10 A
DMAWR, CLK,
BUSMD 1-0, DACK,
RESET, and
DFMODE
Input Pins
VIN = VIH
VIN = VIL
VT
IOL
IOH
CL
0 V
From Output
Under Test
16505C-34
SWITCHING TEST CIRCUIT
SWITCHING TEST WAVEFORMS
True Data Outputs AD 70, DMA 150, DMAP10
All Inputs
1.5 V
3.0 V
0.0 V
Hi-Z Outputs AD 70, DMA 150, DMAP10
0.8 V
All Open Drain Outputs
1.5 V
All Other Outputs
VOH
VOL
VOL +0.3 V
VOL
VOL
VOH
1.5 V
VOH 0.3 V
1.5 V
16505C-35
1.5 V
2.0 V
0.8 V
42 Am53C94/Am53C96
KEY TO SWITCHING WAVEFORMS
KS000010
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Dont Care,
Any Change
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
Off State
WAVEFORM INPUTS OUTPUTS
43 Am53C94/Am53C96
Parameter
No. Symbol Parameter Description Test Conditions Min Max Unit
1 tPWL Clock Pulse Width Low 14.58 ns
2 tCP Clock period 40 100 ns
3 tL Synchronization latency 54.58 185.42 ns
(parameter 2 + parameter 1)
4 tPWH Clock Pulse Width High 14.58 ns
RESET
Parameter
Reset Input
5 tPWH Reset Pulse Width High 500 ns
CLK
Clock Input
3
5
1 4
2
Note:
Clock Frequency Range = 10 to 25 MHz for Asynchronous SCSI Bus
= 12 to 25 MHz for Synchronous SCSI Bus
16505C-36
16505C-37
Note:
There is a one-to-one relationship between every AMD and NCR Parameter (refer to Appendix B).

44 Am53C94/Am53C96
6 tS INT to RD Set Up Time 0 ns
7 tPD RD to INT Delay 0 100 ns
8 tPWL RD Pulse Width Low 50 ns
9 tPD RD to INT Delay tL tPD ns
Parameter
INT
RD
Interrupt Output
6 8 9
7
16505C-38
Note:


45 Am53C94/Am53C96
Parameter
10 tS Address to CS Set Up Time 0 ns
11 tH Address to CS Hold Time 50 ns
12 tS CS to RD Set Up Time 0 ns
13 tPD CS to Data Valid Delay 90 ns
15 tPD RD to Data Valid Delay 50 ns
16 tH RD to CS Hold Time 0 ns
17 tZ RD to Data High Impedance 40 ns
18 tH RD to Data Hold Time 2 ns
19 tPWH CS Pulse Width High 40 ns
20 tS CS to WR Set Up Time 0 ns
21 tPWL WR Pulse Width Low 40 ns
22 tS Data to WR Set Up Time 15 ns
23 tH WR to CS Hold Time 0 ns
24 tS WR to CS Set Up Time 60 ns
25 tPWH WR Pulse Width High 60 ns
26 tH Data to WR Hold Time 0 ns
CS
RD
WR
AD 70
DMA 70
DMAP 0
A30
Register Read/Write with Non-Multiplexed Address Data Bus
10
11
10 11
19
19
23
24
16
12 14
20
21
25
22 26
15
13 18
17
16505C-39
Note:

46 Am53C94/Am53C96
31
27 tPWH ALE Pulse Width High 20 ns
28 tS Address to ALE Set Up Time 10 ns
29 tH Address to ALE Hold Time 10 ns
30 tS ALE to CS Set Up Time 10 ns
31 tPD CS to Data Valid Delay 90 ns
32 tS CS to RD Set Up Time 0 ns
33 tPD RD to Data Valid Delay 50 ns
35 tH RD to Data Hold Time 2 ns
36 tH RD to CS Hold Time 0 ns
37 tZ RD to Data High Impedance 40 ns
38 tS CS to ALE Set Up Time 50 ns
39 tS CS to WR Set Up Time 0 ns
40 tPWL WR Pulse Width Low 40 ns
41 tS Data to WR Set Up Time 15 ns
42 tS WR to ALE Set Up Time 50 ns
43 tH Data to WR Hold Time 0 ns
44 tH WR to CS Hold Time 0 ns
Parameter
CS
RD
WR
AD 70
AL
Register Read/Write with Multiplexed Address Data Bus
28 29
27
30
38
32 34 36
33
35
39 40 44
41
43
27
28 29
30
Address Data Address Data
37
42
16506C-40
Note:


47 Am53C94/Am53C96
45 tPD DACK to DREQ Valid Delay 38 ns
46 tP DACK to DACK period 100 ns
47 tPWL DACK Pulse Width Low 60 ns
48 tPD DACK to Data Valid Delay 41 ns
50 tP DACK to DACK period t3+50t51 ns
51 tPWH DACK Pulse Width High 12 ns
52 tZ DACK to Data High Impedance 40 ns
53 tH DACK to Data Hold Time 2 ns
54 tS DACK to DMAWR Set Up Time 0 ns
55 tPWL DMAWR Pulse Width Low 50 ns
56 tS Data to DMAWR Set Up Time 15 ns
57 tH DMAWR to DACK Hold Time 0 ns
58 tPWH DMAWR Pulse Width High 40 ns
59 tH Data to DMAWR Hold Time 0 ns
Parameter
Note:
DMA Read without Byte Control
45 49
46
47 67 51
48
53
52
50
DREQ
DACK
DMA 150
DMAP 10
49 45
51 47
DMA Write without Byte Control
45 49
46
47 51
55 57 54
56
59
50
58
52
49
45
47
48
53
51
DMA 150
DMAP 10
DREQ
DACK
DMAWR
16506C-41
16506C-42

48 Am53C94/Am53C96
DMA Read with Byte Control
DMA 150
DMAP 10
DREQ
DACK
DMARD
AS 0
BHE
60 71
61
62 73
64 67
63 68
66
72
70
69 69
70
71
60
61
73
62
65
66
DMA Write with Byte Control
60 71
61
62 73
75
78
72
74 76
79
77 81
80
DREQ
DACK
AS 0
BHE
DMAWR
DMA 150
DMAP 10
71
60
61
73
62
16506C-53
16506C-52


49 Am53C94/Am53C96
63 tS DACK to DMARD Set Up Time 0 ns
64 tS BHE, AS0 to DMARD Set Up Time 20 ns
65 tPWL DMARD Pulse Width Low 60 ns
66 tPD DMARD to Data Valid Delay 51 ns
67 tH BHE, AS0 to DMARD Hold Time 20 ns
68 tH DMARD to DACK Hold Time 0 ns
69 tZ DMARD to Data High Impedance 40 ns
70 tH DMARD to Data Hold Time 2 ns
75 tS BHE, AS0 to DMAWR Set Up Time 20 ns
78 tH BHE, AS0 to DMAWR Hold Time 20 ns
79 tH DMAWR to DACK Hold Time 0 ns
Parameter
Note:

50 Am53C94/Am53C96
DACK
DREQ
DREQ
DACK
DMA 150
DMAP 10
DMA 150
DMAP 10
DMARD
DMAWR
Burst DMA Read without Byte Control
Burst DMA Write without Byte Control
93
93 82
83
83
94
94
87
97
90
101
84
95
85
96
88
98
89
99
86
92
100
91
102
16506C-43
16506C-44
82


51 Am53C94/Am53C96
85 tP DMARD to DMARD period 130 ns
87 tPWH DMARD Pulse Width High 60 ns
89 tP DMARD to DMARD period t3 + 50 ns
90 tPD DMARD to DREQ Valid Delay 140 ns
96 tP DMAWR to DMAWR period 160 ns
99 tP DMAWR to DMAWR period t3 + 50 ns
101 tPD DMAWR to DREQ Valid Delay 140 ns
Parameter

Note:

52 Am53C94/Am53C96
Burst DMA Write with Byte Control
Burst DMA Read with Byte Control
116
116
103
103
104
104
117
117
121
109
125
113
118
106
120
107
122
110
124
112
108
127
115
126
114
DREQ
DACK
DMA 150
DMAP 10
DMAWR
AS 0
BHE
DREQ
DACK
DMA 150
DMAP 10
DMARD
AS 0
BHE
119
105
123
111
16506C-45
16506C-46


53 Am53C94/Am53C96
105 tS BHE, AS0 to DMARD Set Up Time 20 ns
107 tP DMARD to DMARD period 130 ns
109 tPWH DMARD Pulse Width High 60 ns
111 tH BHE, AS0 to DMARD Hold Time 20 ns
112 tP DMARD to DMARD period t3 + 50 ns
113 tPD DMARD to DREQ Valid Delay 140 ns
119 tS BHE, AS0 to DMAWR Set Up Time 20 ns
120 tP DMAWR to DMAWR period 160 ns
123 tH BHE, AS0 to DMAWR Hold Time 20 ns
124 tP DMAWR to DMAWR period t3 + 50 ns
125 tPD DMAWR to DREQ Valid Delay 140 ns
Parameter
Note:

54 Am53C94/Am53C96
Parameter
132 tPD REQ to ACKC Delay 43 ns
128 tS Data to ACKC Set Up Time 55 ns
129 tPD REQ to Data Delay 80 ns
Parameter
REQ
ACKC
Asynchronous Initiator Receive
SDC 70
SDCP
Asynchronous Initiator Send
129
132 133
REQ
ACKC
128
130 131
16505C-47
16505C-48
Note:


55 Am53C94/Am53C96
Parameter
138 tPD ACK to REQC Delay 60 ns
134 tS Data to REQC Set Up Time 55 ns
135 tPD ACK to Data Delay 78 ns
Parameter
ACK
REQC
Asynchronous Target Receive
SDC 70
SDCP
Asynchronous Target Send
135
138 139
ACK
REQC
134
136 137
16505C-49
16505C-50
Note:

56 Am53C94/Am53C96
140 tPD CLK to Data Delay 15* 90 ns
141 tS ACKC or REQC to Data 55 ns
Set Up Time
142 tPD CLK to ACKC or REQC Delay 13* 68 ns
143 tPD CLK to ACKC or REQC Delay 17 70 ns
Parameter
Synchronous Initiator Target Transmit
140
REQC
ACKC
SDC 70
SDCP
CLK
142
141
140
143
142
16505C-51
Note:
* The minimum values have a wide range since they depend on the Synchronization latency. The synchronization latency, in
turn, depends on the operating frequency of the device.
57 Am53C94/Am53C96
APPENDIX A
Pin Connection Cross Reference for Am53C94
Pin# AMD NCR
1 DMAP0 DBP0
2 VSS VSS
3 DMA8 DB8
4 DMA9 DB9
5 DMA10 DB10
6 DMA11 DB11
7 DMA12 DB12
8 DMA13 DB13
9 DMA14 DB14
10 DMA15 DB15
11 DMAP1 DBP1
12 SD0 SDI0/
13 SD1 SDI1/
14 SD2 SDI2/
15 SD3 SDI3/
16 SD4 SDI4/
17 SD5 SDI5/
18 SD6 SDI6/
19 SD7 SDI7/
20 SDP SDIP/
21 VDD VDD
22 VSS VSS
23 SDC0 SDO0/
24 SDC1 SDO1/
25 SDC2 SDO2/
26 SDC3 SDO3/
27 VSS VSS
28 SDC4 SDO4/
29 SDC5 SDO5/
30 SDC6 SDO6/
31 SDC7 SDO7/
32 SDCP SDOP/
33 VSS VSS
34 SELC SELO/
35 BSYC BSYO/
36 REQC REQO/
37 ACKC ACKO/
38 VSS VSS
39 MSG MSGIO/
40 C/D C/DIO
41 I/O I/OIO
42 ATN ATNIO/
Pin# AMD NCR
43 RSTC RSTO/
44 VSS VSS
45 SEL SELI/
46 BSY BSYI/
47 REQ REQI/
48 ACK ACKI/
49 RST RSTI/
50 BUSMD 1 MODE 1
51 BUSMD 0 MODE 0
52 INT INT/
53 RESET RESET
54 WR WR/
55 RD RD/
56 CS CS/
57 ASO [AO] A0SA0
58 BHE [A1] A1BHE
59 DMARD [A2] A2DBRD/
60 ALE [A3] A3ALE
61 CLK CLK
62 VDD VDD
63 AD0 PAD0
64 AD1 PAD1
65 AD2 PAD2
66 AD3 PAD3
67 VSS VSS
68 AD4 PAD4
69 AD5 PAD5
70 AD6 PAD6
71 AD7 PAD7
72 DREQ DREQ
73 DACK DACK/
74 DMAWR DBWR/
75 VSS VSS
76 VSS VSS
77 DMA0 DB0
78 DMA1 DB1
79 DMA2 DB2
80 DMA3 DB3
81 DMA4 DB4
82 DMA5 DB5
83 DMA6 DB6
84 DMA7 DB7
58 Am53C94/Am53C96
APPENDIX A
Pin Connection Cross Reference for Am53C96
Pin# AMD NCR
1 DACK DACK
2 DMAWR DBWR/
3 NC NC
4 ISEL IGS
5 VSS VSS
6 TSEL TGS
7 VSS VSS
8 DMA0 DB0
9 DMA1 DB1
10 DMA2 DB2
11 DMA3 DB3
12 DMA4 DB4
13 DMA5 DB5
14 DMA6 DB6
15 DMA7 DB7
16 DMAP0 DBP0
17 VSS VSS
18 VSS VSS
19 DMA8 DB8
20 DMA9 DB9
21 DMA10 DB10
22 DMA11 DB11
23 DMA12 DB12
24 DMA13 DB13
25 DMA14 DB14
26 DMA15 DB15
27 DMAP1 DBPI
28 NC NC
29 SD0 SDI0/
30 SD1 SDI1/
31 SD2 SDI2/
32 SD3 SDI3/
33 SD4 SDI4/
34 SD5 SDI5/
35 SD6 SDI6/
36 SD7 SDI7/
37 SDP SDIP/
38 VDD VDD
39 NC NC
40 VSS VSS
41 VSS VSS
42 SDC0 SDO0/
43 SDC1 SDO1/
44 SDC2 SDO2/
45 SDC3 SDO3/
46 VSS VSS
47 VSS VSS
48 SDC4 SDO4/
49 SDC5 SDO5/
50 SDC6 SDO6/
Pin# AMD NCR
51 SDC 7 SDO7/
52 SDC P SDOP/
53 NC NC
54 VSS VSS
55 VSS VSS
56 SELC SELO/
57 BSYC BSYO/
58 REQC REQO/
59 ACKC ACKO/
60 VSS VSS
61 VSS VSS
62 MSG MSGIO/
63 C/D C/DIO
64 I/O I/OIO
65 ATN ATNIO/
66 RSTC RSTO/
67 VSS VSS
68 VSS VSS
69 SEL SELI/
70 BSY BSYI/
71 REQ REQI/
72 ACK ACKI/
73 RST RSTI/
74 BUSMD 1 MODE 1
75 BUSMD 0 MODE 0
76 INT INT/
77 RESET RESET
78 NC NC
79 WR WR/
80 RD RD/
81 CS CS/
82 ASO [A0] A0SAO
83 BHE [A1] A1BHE
84 DMARD [A2] A2DBRD/
85 ALE [A3] A3ALE
86 CLK CLK
87 DFMODE DIFFM/
88 VDD VDD
89 NC NC
90 AD0 PAD0
91 AD1 PAD1
92 AD2 PAD2
93 AD3 PAD3
94 VSS VSS
95 VSS VSS
96 AD4 PAD4
97 AD5 PAD5
98 AD6 PAD6
99 AD7 PAD7
100 DREQ DREQ
59 Am53C94/Am53C96
APPENDIX B
AMD/NCR Timing Parameters Cross Reference
AMD
Parameter #
tCH 4
tCL 1
tCP 2
tCS 3
tRST 5
tIR 6
tRD 8
tRI 7
tICY 9
tRDP1 10
tRDP2 11
tRDP3 19
tRDP4 13
tRDP5 12
tRDP6 14
tRDP7 16
tRDP8 15
tRDP9 (max) 17
tRDP9 (min) 18
tRDP10 20
tRDP11 21
tRDP12 23
tRDP13 22
tRDP14 26
tRDP15 24
tRDP16 25
tRMP1 28
tRMP2 29
tRMP3 27
tRMP4 30
tRMP5 31
tRMP6 38
tRMP7 32
tRMP8 34
tRMP9 36
tRMP10 33
tRMP11 (max) 37
tRMP11 (min) 35
tRMP12 39
tRMP13 40
tRMP14 44
tRMP15 41
tRMP16 43
tRMP17 42
tDNB1 45
tDNB2 49
tDNB3 51
tDNB4 47
AMD
Parameter #
tDNB5 46
tDNB6 50
tDNB7 48
tDNB8 (max) 52
tDNB8 (min) 53
tDNB9 54
tDNB10 55
tDNB11 57
tDNB12 56
tDNB13 59
tDNB14 58
tDBC1 60
tDBC2 71
tDBC3 73
tDBC4 62
tDBC5 61
tDBC6 72
tDBC7 64
tDBC8 67
tDBC9 63
tDBC10 65
tDBC11 68
tDBC12 66
tDBC13 (max) 69
tDBC13 (min) 70
tDBC14 75
tDBC15 78
tDBC16 74
tDBC17 76
tDBC18 79
tDBC19 77
tDBC20 81
tDBC21 80
tDAN1 93
tDAN2 82
tDAN3 94
tDAN4 83
tDAN5 90
tDAN6 84
tDAN7 88
tDAN8 87
tDAN9 86
tDAN10 (max) 91
tDAN10 (min) 92
tDAN11 85
tDAN12 89
tDAN13 101
tDAN14 95
AMD
Parameter #
tDAN15 98
tDAN16 97
tDAN17 100
tDAN18 102
tDAN19 96
tDAN20 99
tDAB1 116
tDAB2 103
tDAB3 117
tDAB4 104
tDAB5 113
tDAB6 105
tDAB7 111
tDAB8 106
tDAB9 110
tDAB10 109
tDAB11 108
tDAB12 (max) 114
tDAB12 (min) 115
tDAB13 107
tDAB14 112
tDAB15 125
tDAB16 119
tDAB17 123
tDAB18 118
tDAB19 122
tDAB20 121
tDAB21 127
tDAB22 126
tDAB23 120
tDAB24 124
tLAXDA 128
tLAXAH 130
tLAXRD 129
tLAXAL 131
tLARAH 132
tLARAL 133
tTAXDR 134
tTAXRH 136
tTAXAD 135
tTAXRL 137
tTARRH 138
tTARRL 139
tSXD 140
tSXRAL 142
tSXRAH 143
tSXDSU 141
NCR
Symbol
NCR
Symbol
NCR
Symbol
60 Am53C94/Am53C96
PHYSICAL DIMENSIONS*
PL 084
Plastic Leaded Chip Carrier (measured in inches)
.050
REF
.042
.048
1.150
1.156
1.185
1.195
1.150
1.156
1.185
1.195
.042
.056
.165
.180
.090
.130
.007
.013
1.000
REF
.013
.021
1.090
1.130
.020
MIN
.025
.045
09980B
CG08 PL 084
8/14/92 c dc
R
TOP VIEW SIDE VIEW
.026
.032
* For reference only. BSC is an ANSI standard for Basic Space Centering.
61 Am53C94/Am53C96
PQR100
Plastic Quad Flatpack Trimmed and Formed (measured in millimeters)
0.22
0.38
13.90
14.10
17.10
17.30
18.85
REF
19.90
20.10
23.00
23.40
0.65
REF
Pin 1 I.D.
12.35
REF
2.60
3.00
3.35
MAX
0.70
0.90
TOP VIEW
SIDE VIEW
15590D
BX 45
9/6/91 SG
PQJ 100 (Plastic Quad Flat Pack; Trimmed and Formed)
(measured in millimeters)
0.25
MIN
62 Am53C94/Am53C96
PQR100
Molded Carrier Ring Plastic Quad Flatpack (measured in millimeters)
TOP VIEW
Pin 1 I.D.
19.80
20.10
27.87
28.13
31.37
31.63
35.87
36.13
13.80
14.10
25.20
BSC
27.87
28.13
31.37
31.63
35.50
35.90
35.87
36.13
.65 NOM
.65 Typ
.65 Pitch
.45 Typ
2.00 4.80
1.80
SIDE VIEW
CB 48
6/25/92 SG
0.22
0.38
25.15
25.25 22.15
22.25
35.50
35.90
25.15
25.25
22.15
22.25
30
50
80
100
63 Am53C94/Am53C96
Trademarks
Copyright 1993 Advanced Micro Devices, All rights reserved.
GLITCH EATER is a trademark of Advanced Micro Devices, Inc.
AMD and Am386 are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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