UGM154 BScIII PHY3

UGM-154
B. Sc. (Part-III) Examination, 2020

PHYSICS
[ Third Paper ]
(Basic Digital Electronics and Photonic Devices)
Time : Two Hours ] [ Maximum Marks : 38
Note : Question No. 1 is compulsory and carries 11 marks. Attempt any three questions from remaining
questions carrying 9 marks each. In each question symbols have their usual meaning.
uksV % iz'u la[;k 1 vfuok;Z gS] tks 11 vadksa dk gS rFkk blds vfrfjDr fdUgha rhu vU; iz'uksa dk mÙkj nhft, rFkk
izR;sd 9 vadks dk gSA izR;sd iz'u esa izrhdksa ds lkekU; vFkZ gSaA
1. Answer any two of the following :
fuEufyf[kr eas ls fdUgha nks dk mÙkj nhft, %
(a) Convert decimal number 212 into corresponding hexadecimal number.
n'keyo la[;k 212 dks gsDlk Msfley la[;k eas cnfy;sA
(b) When the gate to source voltage of a JFET is changed from –4.0 volt to –4.1 volt, the
corresponding drain current changes from 1.72 mA to 1.82 mA. Calculate the
transconductance of the JFET.
,d taD'ku QsV eas tc xsV lkslZ oksYVst dks –4.0 oksYV ls –4.1 oksYV cnyk tkrk gS rks Mªsu /kkjk 1.72
feyh ,fEi;j ls cny dj 1.82 feyh ,fEi;j gks tkrh gSA taD'ku QsV ds VªkUl&dUMDVsl a dh x.kuk
dhft,A
(c) Using theorems of Boolean Algebra prove that.
( A + B).( A + C ).( B + C ) = ( A + B).( A + C )
cwfy;u chtxf.kr dk iz;ksx djrs gq, fl) dhft,A
( A + B).( A + C ).( B + C ) = ( A + B).( A + C )
2. (a) What are delay time, rise time and storage time in a transistor working as a switch. How do
these limit the high switching speed of the transistor ?
,d fLop dh rjg dk;Z djrs gq, Vªk¡ftLVj eas fMys le;] jkbt+ le; rFkk LVksjst le; D;k gksrs gSa \
;g lc Vªk¡ftLVj dh mPp fLofpax xfr dks dSls izHkkfor djrs gSa \
(b) In an RTL Invertor gate : Rc = 750, Rb = 600, Vcc = 5 volt. Calculate the base current that
draws the transistor in deep saturation with  = 0.2.
Given hic = 50, VBE(sat) = .75 volt, and VCE(sat) = .18 volt.
,d vkj0Vh0,y0 buoVZj xsV esa % Rc = 750, Rb = 600, Vcc = 5 oksYV ml csl dks Kkr dhft, tks
fd Vªk¡ftLVj dks xgjs lSpqjs'ku ( = 0.2) eas ys tkrh gSA fn;k gS % hic = 50; VBE(sat.) = .75 oksYV vkSj
VCE(sat) = .18 oksYVA
3. (a) State the advantages of an Integrated circuit over a discrete circuit. What are the SSI, the MSI,
the LSI and the VLSI ?
fMLØhV ifjiFk dh rqyuk eas bUVhxzsVsM ifjiFk ds ykHk crkb,A SSI, MSI, LSI vkSj VLSI D;k gaS \
(b) Discuss the steps involved in the fabrication of an IC.
IC ds fuekZ.k ds fofHkUu pj.kkas dh foospuk dhft,A
4. (a) Describe the theory of photoconductor and obtain expressions for the current gain and
transit time. How could the gain be increased and transit time reduced ? What are the
limitations for this ?
,d QksVksdUMDVj ds fl)kUr dk o.kZu dhft, rFkk blds /kkjk xsu rFkk Vªk¡ftV le; dk O;atd
fudkfy,A xsu dSls c<+;k tk ldrk gS vkSj Vªk¡ftV le; dSls ?kVk;k tk ldrk gS \ bldh lhek;sa D;k
gSa \
UGM-154/700 P. T. O.
(2)
(b) What is a Karnaugh map ? Minimize the following four variables function using Karnaugh
map :
(i) f(A, B, C, D) = m(0, 1, 3, 5, 6, 9, 11, 12, 13, 15)
(ii) f(A, B, C, D) = m(0, 3, 4, 5, 6, 7, 11, 13, 14, 15)
dkuksZ eSi D;k gksrk gS \ pkj oSfj;scy ds fuEu Qyuksa dks dkuksZ eSi dh lgk;rk ls ljy dhft, %
(i) f(A, B, C, D) = m(0, 1, 3, 5, 6, 9, 11, 12, 13, 15)
(ii) f(A, B, C, D) = m(0, 3, 4, 5, 6, 7, 11, 13, 14, 15)
5. (a) A two input DTL NAND gate has R = 2 k, Rc = 2 k, Rb = 5 k, VBB = 0, VCC = 5 volt and hFE =
100. One input is in logic '1'. Calculate the other input Vi for which the output transistor is
driven into saturation with  = 0.4 and VCE = 0.2 volt.
fdlh nks fuos'k okys DTL-NAND xsV esa R = 2 k, Rc = 2 k, Rb = 5 k, VBB = 0, VCC = 5 volt vkSj
hFE = 100 ,d fuos'k ykWftd '1' esa gSA nwljs fuos'k Vi dh x.kuk dhft, ftlds fy;s fuxZr Vªk¡ftLVj
lar`Ir voLFkk eas bruk pyk tk, fd  = 0.4 rFkk VCE = 0.2 oksYVA
(b) Draw the circuit diagram of a TTL NAND gate. Explain the advantage of an Active Pull up over
a passive pull up.
TTL NAND xsV dk ifjiFk fp= [khafp;sA fuf"Ø; iqy vi dh rqyuk eas lfØ; iqy&vi dk ykHk
le>kb,A
6. (a) Explain why is the channel in a JFET lightly doped while the gate is heavily doped ?
le>kb, fd JFET ds pSuy esa vinzO; lkUnzrk de rFkk xsV eas vf/kd D;kas j[kh tkrh gS \
(b) Draw a circuit diagram of an NMOS switch and explain its working. What are the driver MOS
and the Load MOS ?
,d NMOS fLop dk ifjiFk fp= [khafp, rFkk bldh dk;Zfof/k le>kb,A Mªkboj MOS rFkk yksM MOS
D;k gksrs gSa \
7. (a) Describe the photo etching process. How many masks are required to complete an IC ?
s sl dk o.kZu dhft,A ,d IC dks iwjk djus ds fy;s fdrus eLd pkfg, \
QksVks ,fpax izkl
(b) Define the sheet resistance Rs. What is the order of magnitude of Rs. for the base region and
also for the emitter region ? Draw the equivalent circuit of a base diffused resistor showing all
parasitic elements.
'khV izfrjks/k dh ifjHkk"kk nhft,A csl rFkk ,feVj {ks=ksa eas Rs dh ifjek.k dksfV D;k gS \ lHkh iSjkflfVd
rRokas ds lkFk csl fM¶;wTM izfrjks/k dk rqY; ifjiFk [khafp,A
8. (a) What is a digital comparator ? Draw the logic circuit of a one bit digital comparator and
explain its working.
,d fMftVy dkWEijsVj D;k gksrk gS \ ,d fcV ds fMftVy dkWEijsVj dk ykWftd ifjiFk cukb, rFkk
bldh dk;Ziz.kkyh le>kb,A
(b) Write down the truth table of a full adder and design its logic circuit using minimum number
of gates.
,d Qqy ,sMj dk VªqFk lkj.kh cukb, rFkk de ls de xsV dk iz;ksx djrs gq, bldk ykWftd ifjiFk
cukb,A
9. Write short note on any two of the following :
fuEu esa ls fdUgha nks ij fVIi.kh fyf[k, %
(a) Ebers-Moll-Equation for the transistor.
Vªkfa tLVj ds fy;s ,scj ekWy lehdj.kA
(b) Show that while AND operation is associative, NAND operation is not associative.
n'kkZb;s] tcfd AND vkWijs'ku ,lksfl,fVo gksrk gS] fdUrq NAND vkWijs's ku ,lksfl,fVo ugha gksrk gSA
(c) Venn diagram.
osu MkbxzkeA
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UGM-154

B. Sc. (Part-III) Examination, 2020

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